Cirrus Logic CS43L22 User Manual
+1.60 V to +5.25 V
Battery
+1.65 V to +2.63 V
Digital Supply
Pulse-Width
Modulator
Battery Level Monitoring & Compensation
Multi-bit
ΔΣ DAC
Level Shifter
+1.65 V to +3.47 V
Interface Supply
Control Port
Serial Audio Port
Beep
Generator
Digital Volume,
Mono Mix,
Limiter, Bass,
Treble Adjust
Left
Inputs
Σ
4321
Summing
Amplifiers
Left HP/Line
Output
Ground-Centered
Amps
Right HP/Line
Output
+1.65 V to +2.63 V
Headphone Supply
Speaker/HP
Switch
Charge Pump
+VHP
-VHP
+1.65 V to +2.63 V
Analog Supply
Stereo/Mono
Full-Bridge
Speaker
Outputs
Class D Amps
+
+
-
I²C
Control
Reset
Serial
Audio
Input
Right
Inputs
Σ
4321
Confidential Draft
3/4/10
CS43L22
Low Power, Stereo DAC w/Headphone & Speaker Amps
FEATURES
98 dB Dynamic Range (A-wtd)
88 dB THD+N
Headphone Amplifier - GND Centered
– No DC-Blocking Capacitors Required
– Integrated Negative Voltage Regulator
– 2 x 23 mW into Stereo 16 Ω @ 1.8 V
– 2 x 44 mW into Stereo 16 Ω @ 2.5V
Stereo Analog Input Passthrough Architecture
– Analog Input Mixing
– Analog Passthrough with Volume Control
Digital Signal Processing Engine
– Bass & Treble Tone Control, De-Emphasis
– PCM Input w/Independent Vol Control
– Master Digital Volume Control and Limiter
– Soft-Ramp & Zero-Cross Transitions
Programmable Peak-Detect and Limiter
Beep Generator w/Full Tone Control
– Tone Selections Across Two Octaves
– Separate Volume Control
– Programmable On and Off Time Intervals
– Continuous, Periodic, One-Shot Beep
Selections
Class D Stereo/Mono Speaker Amplifier
No External Filter Required
High Stereo Output Power at 10% THD+N
– 2 x 1.00 W into 8 Ω @ 5.0 V
– 2 x 550 mW into 8 Ω @ 3.7 V
– 2 x 230 mW into 8 Ω @ 2.5 V
High Mono Output Power at 10% THD+N
– 1 x 1.90 W into 4 Ω @ 5.0 V
– 1 x 1.00 W into 4 Ω @ 3.7 V
– 1 x 350 mW into 4 Ω @ 2.5 V
Direct Battery Powered Operation
– Battery Level Monitoring & Compensation
81% Efficiency at 800 mW
Phase-Aligned PWM Output Reduces Idle
Channel Current
Spread Spectrum Modulation
Low Quiescent Current
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MARCH '10
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System Features
12, 24, and 27 MHz Master Clock Support in
Addition to Typical Audio Clock Rates
High Performance 24-bit Converters
– Multi-bit Delta–Sigma Architecture
– Very Low 64Fs Oversampling Clock Reduces
Power Consumption
Low Power Operation
– Stereo Analog Passthrough: 10 mW @ 1.8 V
– Stereo Playback: 14 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.6 V to 5 V Class D Amplifier
– 1.8 V to 2.5 V Headphone Amplifier
– 1.8 V to 3.3 V Interface Logic
Power Down Management
– DAC, Passthrough Amplifier, Headphone
Amplifier, Speaker Amplifier
Flexible Clocking Options
– Master or Slave Operation
– Quarter-Speed Mode - (i.e. allows 8 kHz Fs
while maintaining a flat noise floor up to 16 kHz)
– 4 kHz to 96 kHz Sample Rates
I²CTM Control Port Operation
Headphone/Speaker Detection Input
Pop and Click Suppression
Pin-Compatible w/CS42L52
Applications
PDA’s
Personal Media Players
Portable Game Consoles
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CS43L22
General Description
The CS43L22 is a highly integrated, low power stereo DAC
with headphone and Class D speaker amplifiers. The
CS43L22 offers many features suitable for low power, portable system applications.
The DAC output path includes a digital signal processing engine with various fixed function controls. Tone Control
provides bass and treble adjustment of four selectable corner
frequencies. Digital Volume controls may be configured to
change on soft ramp transitions while the analog controls can
be configured to occur on every zero crossing. The DAC also
includes de-emphasis, limiting functions and a BEEP generator delivering tones selectable across a range of two full
octaves.
The stereo hea dphone amplifier is powered from a separate
positive supply and the integrated charge pump provides a
negative supply. This allows a ground-centered analog output
with a wide signal swing and elimina tes the need for external
DC-blocking capacitors.
The Class D stereo speaker amplifier does not require an
external filter and provides the high efficiency amplification required by power sensitive portable applications. The speaker
amplifier may be powered directly from a battery while the internal DC supply monitoring and compensation provides a
constant gain level as the battery’s voltage decays.
The CS43L22 accommodates analog routing of the analog input signal directly to the headphone ampli fier. This feature is
useful in applications that utilize an FM tuner where audio recovered over-the-air must be transmitted to the headphone
amplifier directly.
In addition to its many features, the CS43L22 operates from a
low voltage analog and digital core making it ideal for portable
systems that require extremely low power consumption in a
minimal amount of space.
The CS43L22 is available in a 40-pin QFN package in Commercial (-40 to +85 °C) grade. The CS43L22 Customer
Demonstration board is also available for device evaluation
and implementation suggestions. Please refer to “Ordering In-
formation” on page 66 for complete ordering information.
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TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 7
1.1 I/O Pin Characteristics ..................................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 9
3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 10
RECOMMENDED OPERATING CONDITIONS .................................................................................. 10
ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 10
ANALOG OUTPUT CHARACTERISTICS .......................................................................................... 11
ANALOG PASSTHROUGH CHARACTERISTICS .............................................................................. 12
PWM OUTPUT CHARACTERISTICS ................................................................................................. 13
HEADPHONE OUTPUT POWER CHARACTERISTICS ..................................................................... 14
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS .................................................................... 15
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................. 15
SWITCHING SPECIFICATIONS - SERIAL PORT .............................................................................. 16
SWITCHING SPECIFICATIONS - I²C CONTROL PORT .................................................................... 17
DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... .......................................... ...................... 18
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS .................................................... 18
POWER CONSUMPTION ................................................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ..................................... ...................................... .... ... ... ................................................... 20
4.1.1 Basic Architecture ................................................................................................................. 20
4.1.2 Line Inputs ............................................................................................................................. 20
4.1.3 Line & Headphone Outputs ................................................................................................... 20
4.1.4 Speaker Driver Outputs ......................................................................................................... 20
4.1.5 Fixed Function DSP Engine .................................................................................................. 20
4.1.6 Beep Generator ..................................................................................................................... 20
4.1.7 Power Management .............................................................................................................. 20
4.2 DSP Engine .................................................................................................................................. 21
4.2.1 Beep Generator ..................................................................................................................... 22
4.2.2 Limiter .................................................................................................................................... 22
4.3 Analog Passthrough ....................... ....................................... ... ... ... ... .... ... ... ... .... ... ......................... 24
4.4 Analog Outputs .... ... ... .... ... ... ....................................... ... ... .... ... ... ... ................................................ 25
4.5 PWM Outputs .................... ... ... .... ... ... ... ....................................... ... ... .... ... ... ................................... 26
4.5.1 Mono Speaker Output Configuration ..................... .................................... ............................ 27
4.5.2 VP Battery Compensation ........... ... .... ... ... ... .... .......................................... ... ... ... ... .... ... ... ...... 27
4.5.2.1 Maintaining a Desired Output Level ........................................................................... 27
4.6 Serial Port Clocking ................ .... ...................................... .... ... ... ... ... .... ......................................... 29
4.7 Digital Interface Formats ............................. ... .......................................... ... ................................... 30
4.7.1 DSP Mode ............................................................................................................................. 31
4.8 Initialization ... .... ...................................... .... ... ... ... .... ... ....................................... ... ......................... 31
4.9 Recommended Power-Up Sequence ............................................................................................ 31
4.10 Recommended Power-Down Sequence ...................................................................................... 31
4.11 Required Initialization Settings ..................................................................................................... 32
5. CONTROL PORT OPERATION ........................................................................................................... 33
5.1 I²C Control .................. .... ... ... ... .... ... ....................................... ... ... ... ... ............................................. 33
5.1.1 Memory Address Pointer (MAP) ......................... .......... ......... .......... .......... ......... .......... ......... 34
5.1.1.1 Map Increment (INCR) ..................... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ... 34
6. REGISTER QUICK REFERENCE ........................................................................................................ 35
7. REGISTER DESCRIPTION .................................................................................................................. 37
7.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 37
7.1.1 Chip I.D. (Read Only) ............................................................................................................ 37
7.1.2 Chip Revision (Read Only) .................................................................................................... 37
7.2 Power Control 1 (Address 02h) ...................................................................................................... 37
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7.2.1 Power Down ...... .... ... ... ... .... ...................................... .... ... ... ... ... .... ......................................... 37
7.3 Power Control 2 (Address 04h) ...................................................................................................... 38
7.3.1 Headphone Power Control .... ... ... ... .... ... ... ... .... ... .......................................... ... ...................... 38
7.3.2 Speaker Power Control ............... ... .... ... ... ... .... ...................................... .... ... ... ... ... .... ... ... ...... 38
7.4 Clocking Control (Address 05h) ..................................................................................................... 38
7.4.1 Auto-Detect ........................ ... ... ... ... .... ... ... ....................................... ... ... .... ... ... ...................... 38
7.4.2 Speed Mode ...... .... ... ... ... .... ...................................... .... ... ... ... ... .... ......................................... 39
7.4.3 32kHz Sample Rate Group ................................................................................................... 39
7.4.4 27 MHz Video Clock .............................................................................................................. 39
7.4.5 Internal MCLK/LRCK Ratio ................................................................................................... 39
7.4.6 MCLK Divide By 2 .......... .... ...................................... .... ... ... ... ... .... ......................................... 40
7.5 Interface Control 1 (Address 06h) ............................... .......................................... ......................... 40
7.5.1 Master/Slave Mode ............................... ... ............................................................................. 40
7.5.2 SCLK Polarity ........ ... ... ... .... ... ....................................... ... ... ... ... .... ... ...................................... 40
7.5.3 DSP Mode ......... .... ... ... ... .... ...................................... .... ... ... ... ... .... ......................................... 40
7.5.4 DAC Interface Format ..................................................................... ...................................... 40
7.5.5 Audio Word Length ................................................................................................................ 41
7.6 Interface Control 2 (Address 07h) ............................... .......................................... ......................... 41
7.6.1 SCLK equals MCLK .............................................................................................................. 41
7.6.2 Speaker/Headphone Switch Invert .................................. ... ... ... .... ... ...................................... 41
7.7 Passthrough x Select: PassA (Address 08h), PassB (Address 09h) ............................................. 42
7.7.1 Passthrough Input Channel Mapping .................................................................................... 42
7.8 Analog ZC and SR Settings (Address 0Ah) ................................................................................... 42
7.8.1 Ch. x Analog Soft Ramp . .... ... ....................................... ... ... ... ... .... ... ... ... .... ............................ 42
7.8.2 Ch. x Analog Zero Cross ....... ... ... ... .... ... ... ... ....................................... ... .... ... ... ... ... .... ... ......... 42
7.9 Passthrough Gang Control (Address 0Ch) .................................................................................... 42
7.9.1 Passthrough Channel B=A gang Control .............................................. .... ... ... ... ... .... ... ... ... ... 42
7.10 Playback Control 1 (Address 0Dh) .. ....................................... ... ... ... ............................................. 43
7.10.1 Headphone Analog Gain ........ ... ... .... ... ... ... .... ... ... ... .......................................... ... ................ 43
7.10.2 Playback Volume Setting B=A ............................................................................................ 43
7.10.3 Invert PCM Signal Polarity .................................................................................................. 43
7.10.4 Master Playback Mute ......................................................................................................... 43
7.11 Miscellaneous Controls (Address 0Eh) ........................................................................................ 44
7.11.1 Passthrough Analog ............................................................................................................ 44
7.11.2 Passthrough Mute ............................................................................................................... 44
7.11.3 Freeze Registers .............................. ................................................................... ................ 44
7.11.4 HP/Speaker De-Emphasis ..................................................................................................44
7.11.5 Digital Soft Ramp ................................................................................................................ 44
7.11.6 Digital Zero Cross ...................... ....... ...... ....... ...... ....... ...... ... ....... ...... ....... ...... ...... ................ 45
7.12 Playback Control 2 (Address 0Fh) .................. ... .... ... ... ... .... ...................................... ... .... ... ......... 45
7.12.1 Headphone Mute ................................................................................................................. 45
7.12.2 Speaker Mute ...................................................................................................................... 45
7.12.3 Speaker Volume Setting B=A ..............................................................................................45
7.12.4 Speaker Channel Swap ....................................................................................................... 45
7.12.5 Speaker MONO Control ...................................................................................................... 46
7.12.6 Speaker Mute 50/50 Control ............................................................................................... 46
7.13 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h) .................... 46
7.13.1 Passthrough x Volume ........................................................................................................ 46
7.14 PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh) ................................................... 47
7.14.1 PCM Channel x Mute .......................................................................................................... 47
7.14.2 PCM Channel x Volume ...................... ................................................................ ................47
7.15 Beep Frequency & On Time (Address 1Ch) ................................................................................ 47
7.15.1 Beep Frequency .................................................................................................................. 47
7.15.2 Beep On Time ..................................................................................................................... 48
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7.16 Beep Volume & Off Time (Address 1Dh) .................. ... ... .... ...................................... ... .... ... ... ... ... 48
7.16.1 Beep Off Time ..................... ... ... ... .... ... ... ... .... ... .......................................... ... ...................... 48
7.16.2 Beep Volume .......... ... ... .... ... .......................................... ... ... ... .... ... ...................................... 49
7.17 Beep & Tone Configuration (Address 1Eh) .................................................................................. 49
7.17.1 Beep Configuration ........................................... ... ... .... ... ... ... ................................................ 49
7.17.2 Beep Mix Disable ................................................................................................................ 49
7.17.3 Treble Corner Frequency ................. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 50
7.17.4 Bass Corner Frequency ......................... ... .... ... ... ... .... ... ... .......................................... ... ...... 50
7.17.5 Tone Control Enable .............................. ... .... ... ... ... .... ... ... ... ... .... ... ...................................... 50
7.18 Tone Control (Address 1Fh) ........................................................................................................ 50
7.18.1 Treble Gain ............................................................................. ............................................. 50
7.18.2 Bass Gain ..................................... .... ... ... ... .... ... ....................................... ... ... ... ... ................ 51
7.19 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h) ....................................... 51
7.19.1 Master Volume Control ........................................................................................................ 51
7.20 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h) .................................... 51
7.20.1 Headphone Volume Control ................................................................................................51
7.21 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h) ..................................... 52
7.21.1 Speaker Volume Control ..................................................................................................... 52
7.22 PCM Channel Swap (Address 26h) ............................................................................................. 52
7.22.1 PCM Channel Swap ............................................................................................................ 52
7.23 Limiter Control 1, Min/Max Thresholds (Address 27h) ................. ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 53
7.23.1 Limiter Maximum Threshold ............. ... ... ... .... ... ... ... .... ......................................... .... ... ... ... ... 53
7.23.2 Limiter Cushion Threshold .................................................................................................. 53
7.23.3 Limiter Soft Ramp Disable ................................ ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 53
7.23.4 Limiter Zero Cross Disable .. .......................................... ... ... ... .... ... ...................................... 54
7.24 Limiter Control 2, Release Rate (Address 28h) ........................................................................... 54
7.24.1 Peak Detect and Limiter ............ ... .... ... ... ... .... ... ... ... .... ... ... ... ... ............................................. 54
7.24.2 Peak Signal Limit All Channels ........................................................................................... 54
7.24.3 Limiter Release Rate ........ ... ... ... ... .......................................... .... ... ... ... .... ............................ 54
7.25 Limiter Attack Rate (Address 29h) ............................................................................................... 55
7.25.1 Limiter Attack Rate ....... .... ... ... ... ... .... ... ... ... .... ... ... .......................................... ... ................... 55
7.26 Status (Address 2Eh) (Read Only) ........................................................... ... .... ... ... ... ................... 55
7.26.1 Serial Port Clock Error (Read Only) .................................................................................... 55
7.26.2 DSP Engine Overflow (Read Only) ..................................................................................... 55
7.26.3 PCMx Overflow (Read Only) ...............................................................................................56
7.27 Battery Compensation (Address 2Fh) .......................................................................................... 56
7.27.1 Battery Compensation ................................... ... ... ... .......................................... ................... 56
7.27.2 VP Monitor .............................................................................. .... ......................................... 56
7.27.3 VP Reference ............ ... .... ... ... ... ... .... ... ... ... .......................................... .... ............................ 57
7.28 VP Battery Level (Address 30h) (Read Only) .............................................................................. 57
7.28.1 VP Voltage Level (Read Only) ............................................................................................57
7.29 Speaker Status (Address 31h) (Read Only) ................................................................................ 57
7.29.1 Speaker Current Load Status (Read Only) ......................................................................... 57
7.29.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 58
7.30 Charge Pump Frequency (Address 34h) ..................................................................................... 58
7.30.1 Charge Pump Frequency .................... ... .............................................................................58
8. ANALOG PERFORMANCE PLOTS ....................................................................................................59
8.1 Headphone THD+N versus Output Power Plots ............................................................................ 59
9. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 61
9.1 Auto Detect Enabled ...................................... ... .... ... ... ... .... ... ... ................................................... 61
9.2 Auto Detect Disabled ... ... ... ....................................... ... ... .... ... ... ... ................................................ 61
10. PCB LAYOUT CONSIDERATIONS ................................... ... .... ... ... ... ....................................... ... ... ... 62
10.1 Power Supply, Grounding ............................................................................................................ 62
10.2 QFN Thermal Pad ........................................................................................................................ 62
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11. DIGITAL FILTER PLOTS ................................................................................................................... 63
12. PARAMETER DEFINITIONS .............................................................................................................. 64
13. PACKAGE DIMENSIONS .................................................................................................................. 65
THERMAL CHARACTERISTICS ......................................................................................................... 65
14. ORDERING INFORMATION .............................................................................................................. 66
15. REFERENCES .................................................................................................................................... 66
16. REVISION HISTORY .......................................................................................................................... 66
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 9
Figure 2. Headphone Output Test Load .................................................................................................... 14
Figure 3. Serial Audio Interface Timing ..................................................................................................... 16
Figure 4. Control Port Timing - I²C ............................................................................................................ 17
Figure 5. DSP Engine Signal Flow .. .......................................... ... .... ... ... ... ................................................ 21
Figure 6. Beep Configuration Options ....................................................................................................... 22
Figure 7. Peak Detect & Limiter ................................................................................................................ 23
Figure 8. Analog Passthrough Signal Flow ............................................................................................... 24
Figure 9. Analog Outputs ................ ... .... ... ... ... ... .... ... .......................................... ...................................... 25
Figure 10. PWM Output Stage .................................................................................................................. 26
Figure 11. Battery Compensation ............................................................................................................. 28
Figure 12. I²S Format ...... ... ... .... ... ... ... .... ... ... ... ... .... .......................................... ... ...................................... 30
Figure 13. Left-Justified Format ................................................................................................................ 30
Figure 14. Right-Justified Format\ ............................................................................................................. 30
Figure 15. DSP Mode Format) .................................................................................................................. 31
Figure 16. Control Port Timing, I²C Write .. ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 33
Figure 17. Control Port Timing, I²C Read ............................... ... ... .... ... ... ................................................... 33
Figure 18. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) ................................................... 59
Figure 19. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) ................................................... 59
Figure 20. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) ................................................... 60
Figure 21. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) ................................................... 60
Figure 22. Passband Ripple ................................... ... ... ... .... ... ... ... .... ... ... ... ... ............................................. 63
Figure 23. Stopband .................................. ... ... ... .... .......................................... ......................................... 63
Figure 24. DAC Transition Band ............................................................................................................... 63
Figure 25. Transition Band (Detail) ........................................................................................................... 63
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12
11
13
14
15
16
17
18
19
20
29
30
28
27
26
25
24
23
22
21
39
40
38
37
36
35
34
33
32
31
2
1
3
4
5
6
7
8
9
10
GND/Thermal Pad
TSTO
MCLK
SCLK
SDIN
SDA
LRCK
FLYN
+VHP
HP/LINE_OUTB
HP/LINE_OUTA
VQ
TSTO
AIN4A
AIN2A
AD0
SPKR_OUTA+
VP
VP
VD
SPKR_OUTB-
-VHPFILT
AIN4B
AIN1B
AIN2B
AFILTB
AIN3B
AFILTA
AIN1A
AIN3A
SPKR_OUTB+
SCL
DGND
SPKR_OUTA-
FLYP
VA
AGND
FILT+
RESET
VL
SPKR/HP
Top-Down (Through-Package) View
40-Pin QFN Package
1. PIN DESCRIPTIONS
3/4/10
CS43L22
Pin Name # Pin Description
SDA 1 Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode.
SCL 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0
SPKR_OUTA+
SPKR_OUTASPKR_OUTB+
SPKR_OUTB-
VP
-VHPFILT
FLYN
FLYP
+VHP
HP/LINE_OUTB, A 14,15 Headphone/Line Audio Output (Output) - Stereo headphone or line level analog outputs.
VA 16 Analog Power (Input) - Positive power for the internal analog section.
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3
Address Bit 0 (I²C) (Input) - AD0 is a chip address pin in I²C Mode.
4
6
PWM Speaker Output (Output) - Full-bridge amplified PWM speaker outputs.
7
9
5
Power for PWM Drivers (Input) - Power supply for the PWM output driver stages.
8
10 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge
pump that provides the negative rail for the hea dphone/line amplifiers.
11 Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s fly-
ing capacitor.
12 Charge Pump Cap Positive Node (Output) - Positive node for the inverting charge pump’s flying
capacitor.
13 Positive Analog Power for Headphone (Input) - Positive voltage rail and power for the internal
headphone amplifiers and inverting charge pump.
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AGND 17 Analog Ground (Input) - Ground reference for the internal analog section.
FILT+ 18 Positive Voltage Reference (Output) - Filter connection for the internal sampling circuits.
VQ 19 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
TSTO
AIN4A,B
AIN3A,B
AIN2A,B
AIN1A,B
AFILTA,AFILTB 27,28 Anti-alias Filter Connection (Output) - Anti-alias filter connection for analog passthrough mode.
SPKR/HP
RESET
VL
VD 34 Digital Power (Input) - Positive power for the internal digital section.
DGND 35 Digital Ground (Input) - Ground reference for the internal digital section.
MCLK 37 Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK 38 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN 39 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
LRCK
GND/Thermal Pad
20,36 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no
connection external to the pin).
21,22
23,24
Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.
25,26
29,30
31 Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker
and/or headphone outputs.
32
Reset (Input) - The device enters a low power mode when this pin is driven low.
33 Digital Interface Power (Input) - Determines the required signal level for the serial audio inter-
face and host control port.
40 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the serial audio data line.
- Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat
dissipation.
CS43L22
1.1 I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
Power
Supply
VL
VA SPKR/HP Input - - 1.65 V - 2.63 V
VP
Pin Name I/O Internal
RESET Input - - 1.65 V - 3.47 V, with Hysteresis
AD0 Input - - 1.65 V - 3.47 V, with Hysteresis
SCL Input - - 1.65 V - 3.47 V, with Hysteresis
SDA Input/
Output
MCLK Input - - 1.65 V - 3.47 V
LRCK Input/
Output
SCLK Input/
Output
SDIN Input - - 1.65 V - 3.47 V
SPKR_OUTA+ Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTA- Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTB+ Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTB- Output - 1.6 V - 5.25 V Power MOSFET -
Driver Receiver
Connections
- 1.65 V - 3.47 V, CMOS/Open
Drain
Weak Pull-up
(~1 MΩ)
Weak Pull-up
(~1 MΩ)
1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V
1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V
1.65 V - 3.47 V, with Hysteresis
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Note 3
Note 2
Note 1
1 µF
+1.8 V to +2.5 V
0.1 µF
1 µF
DGND
VL
0.1 µF
+1.8 V to +3.3 V
SCL
SDA
RESET
2 k
Ω
LRCK
Digital Audio
Processor
MCLK
SCLK
VD
SDIN
CS43L22
2 k
Ω
+1.8 V to +2.5 V
HP/LINE_OUTB
HP/LINE_OUTA
AIN1A
Left 1
100 kΩ
100 Ω
AIN1B
Right 1
0.1 µF
VA
Headphone Out
Left & Right
Line Level Out
Left & Right
FLYP
FLYN
-VHPFILT
51.1 Ω
0.022 µF
100 kΩ
100 Ω
SPKR_OUTA+
SPKR_OUTA-
SPKR/HP
51.1 Ω
0.022 µF
1 µF
1 µF
0.1 µF
+VHP
1 µF
VQ
AGND
* Capacitors must be C0G or equivalent
1 µF
**
**
See Note 4
SPKR_OUTB+
SPKR_OUTB-
1 µF
VP
VP
+1.6 V to
+5 V
Stereo Speakers
AIN2A
Left 2
100 kΩ
100 Ω
AIN2B
Right 2
100 kΩ
100 Ω
1 µF
1 µF
0.1 µF
0.1 µF
Analog
Input 1
Analog
Input 2
10 µF
47 kΩ
Notes:
1. Recommended values for the default charge pump switching
frequency. The required capacitance follows an inverse
relationship with the charge pump’s switching frequency. When
increasing the switching frequency, the capacitance may
decrease; when lowering the switching frequency, the
capacitance must increase.
2. Larger capacitance reduces the ripple on the internal
amplifier’s supply. This may reduce the distortion at higher
output power levels.
3. Additional bulk capacitance may be added to improve PSRR
at low frequencies.
4. Series resistance in the path of the power supplies must be
avoided. Any voltage drop on VHP will directly impact the
negative charge pump supply (-VHPFILT) and clip the audio
output.
AIN3A
Left 3
100 kΩ
100 Ω
AIN3B
Right 3
100 kΩ
100 Ω
1 µF
1 µF
Analog
Input 3
AIN4A
Left 4
100 kΩ
100 Ω
AIN4B
Right 4
100 kΩ
100 Ω
1 µF
1 µF
Analog
Input 4
FILT+
10 µF
150 pF
150 pF
AFILTA
AFILTB
** Low ESR, X7R/X5R dielectric capacitors.
**
**
**
**
**
**
**
**
*
*
TSTO
TSTO
AD0
Figure 1. Typical Connection Diagram
2. TYPICAL CONNECTION DIAGRAM
DS792F2 9
3/4/10
CS43L22
Confidential Draft
3/4/10
CS43L22
3. CHARACTERISTIC AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
AGND=DGND=0 V, all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply
Analog VA 1.65 2.63 V
Headphone Amplifier +VHP 1 .65 2.63 V
Speaker Amplifier VP 1.60 5.25 V
Digital VD 1.65 2.63 V
Serial/Control Port Interface VL 1.65 3.47 V
Ambient Temperature Commercial T
A
-40 +85 °C
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply Analog
Speaker
Digital
Serial/Control Port Interface
Input Current (Note 1) I
Analog Input Voltage (Note 2)
External Voltage Applied to Analog Input (Note 2)
External Voltage Applied to Analog Output
External Voltage Applied to Digital Input (Note 2) V
Ambient Operating Temperature (power applied) T
Storage Temperature T
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
VA, VHP
VP
VD
VL
in
V
IN
V
IN
V
IN
IND
A
stg
-0.3
-0.3
-0.3
-0.3
-±10mA
AGND-0.7 VA+0.7
AGND-0.3 VA+0.3
-VHP - 0.3 +VHP + 0.3
-0.3 VL+ 0.3 V
-50 +115 °C
-65 +150 °C
3.0
5.5
3.0
4.0
V
V
V
V
V
V
V
Notes:
1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
2. The maximum over/under voltage is limited by the input current.
10 DS792F2
Confidential Draft
3/4/10
CS43L22
ANALOG OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = +25°C;
Sample Frequency = 48 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load R
(see Figure 2); Test load R
= 16 Ω, CL = 10 pF (see Figure 2) for the headphone output; HP_GAIN[2:0] = 011.
L
VA = 2.5 V VA = 1.8 V
Parameters
RL = 10 k
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
16-Bit 0 dB
RL = 16
Dynamic Range
18 to 24-Bit A-weighted
16-Bit A-weighted
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
16-Bit 0 dB
Other Characteristics for R
Output Parameters Modulation Index (MI)
(Note 4) Analog Gain Multiplier (G)
Full-scale Output Voltage (2•G•MI•VA) (Note 4) Refer to Table “Headphone Output Power Characteris-
Full-scale Output Power (Note 4) Refer to Table “Headphone Output Power Characteristics” on
Interchannel Isolation (1 kHz) 16 Ω
Speaker Amp to HP Amp Isolation - 80 - - 80 - dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
AC-Load Resistance (R
Load Capacitance (C
Ω
Ω
L
) (Note 5) - - 150 - - 150 pF
L
(Note 3) Min Typ Max Min Typ Max Unit
92
89
-
unweighted
-20 dB
-60 dB
-20 dB
-60 dB
unweighted
unweighted
-20 dB
-60 dB
-20 dB
-60 dB
= 16 Ω or 10 k
L
) (Note 5) 16 - - 16 - - Ω
Ω
10 kΩ
-
-
-
-
-
-
-
92
89
-
-
-
-
-
-
-
-
-
-
tics” on page 14
page 14
-
-
98
95
96
93
-86
-75
-35
-86
-73
-33
98
95
96
93
-75
-75
-35
-75
-73
-33
0.6787
0.6047
80
95
= 10 kΩ, CL = 10 pF for the line output
L
-
-
-
-
-80
-
-29
-
-
-
-
-
-
-
-69
-
-29
-
-
-
-
-
-
-
89
86
89
86
95
92
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
93
90
-88
-72
-32
-88
-70
-30
95
92
93
90
-75
-72
-32
-75
-70
-30
0.6787
0.6047
80
93
-
-
-
-
-82
-
-26
-
-
-
-
-
-
-
-69
-
-26
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
V/V
V/V
Vpp
dB
dB
3. One (least-significant bit) LSB of triangular PDF dither is added to data.
4. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain” on page 43. High gain settings at certain VA and VHP supply levels may cause clipping when the
audio signal approaches full-scale, maximum power output, as shown in Figures 18 - 21 on page 60.
DS792F2 11
Confidential Draft
3/4/10
CS43L22
5. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, C
will effectively
L
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable.
ANALOG PASSTHROUGH CHARACTERISTICS
Test Conditions (unless otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter;
Passthrough Amplifier and HP/Line Gain = 0 dB; All Supplies = VA; TA = +25°C; Sample Frequency = 48 kHz; Measurement
Bandwidth is 20 Hz to 20 kHz.
VA = 2.5 V VA = 1.8 V
Parameters Min Typ Max Min Typ Max Unit
Analog In to HP/Line Amp
R
= 10 k
= 16
Ω
Ω
unweighted
-60 dBFS
unweighted
-60 dBFS
-
-
-
-
-
-
-
-
-
-
-96
-93
-70
-73
-33
-96
-93
-70
-73
-33
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-94
-91
-70
-71
-31
-94
-91
-70
-71
-31
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
L
Dynamic Range A-weighted
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB
R
L
Dynamic Range A-weighted
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Output Power - 32 - - 17 - mW
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB
12 DS792F2
Confidential Draft
3/4/10
CS43L22
PWM OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK = 12.2880 MHz; Measurement
Bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 8 Ω for stereo full-bridge, RL = 4 Ω for mono parallel
full-bridge; VD = VL = VA = VHP = 1.8V; PWM Modulation Index of 0.85; PWM Switch Rate = 384 kHz.
Parameters (Note 7) Symbol Conditions Min Typ Max Units
VP = 5.0 V
Power Output per Channel P
Stereo Full-Bridge THD+N < 10%
Mono Parallel Full-Bridge THD+N < 10%
Total Harmonic Distortion + Noise THD+N
Stereo Full-Bridge PO = 0 dBFS = 0.8W - 0.52 - %
Mono Parallel Full-Bridge P
Dynamic Range DR
Stereo Full-Bridge P
Mono Parallel Full-Bridge P
VP = 3.7 V
Power Output per Channel P
Stereo Full-Bridge THD+N < 10%
Mono Parallel Full-Bridge THD+N < 10%
Total Harmonic Distortion + Noise THD+N
Stereo Full-Bridge P
Mono Parallel Full-Bridge PO = -3 dBFS = 0.41 W
Dynamic Range DR
Stereo Full-Bridge P
Mono Parallel Full-Bridge P
VP =2.5 V
Power Output per Channel P
Stereo Full-Bridge THD+N < 10%
Mono Parallel Full-Bridge THD+N < 10%
Total Harmonic Distortion + Noise THD+N
Stereo Full-Bridge P
Mono Parallel Full-Bridge P
Dynamic Range DR
Stereo Full-Bridge P
Mono Parallel Full-Bridge P
MOSFET On Resistance R
MOSFET On Resistance R
O
O
O
DS(ON)
DS(ON)
-
1.00
THD+N < 1%
THD+N < 1%
= -3 dBFS = 0.75 W
O
PO = 0 dBFS = 1.5 W
= -60 dBFS, A-Weighted
O
PO = -60 dBFS, Unweighted
= -60 dBFS, A-Weighted
O
PO = -60 dBFS, Unweighted
THD+N < 1%
THD+N < 1%
= 0 dBFS = 0.43 W - 0.54 - %
O
= 0 dBFS = 0.81 W
P
O
= -60 dBFS, A-Weighted
O
PO = -60 dBFS, Unweighted
= -60 dBFS, A-Weighted
O
PO = -60 dBFS, Unweighted
THD+N < 1%
THD+N < 1%
= 0 dBFS = 0.18 W - 0.50 - %
O
= -3 dBFS = 0.17 W
O
P
= 0 dBFS = 0.35 W
O
= -60 dBFS, A-Weighted
O
P
= -60 dBFS, Unweighted
O
= -60 dBFS, A-Weighted
O
P
= -60 dBFS, Unweighted
O
-
0.80
-
1.90
-
1.50
-
0.10
-
0.50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
91
88
91
88
0.55
0.45
1.00
0.84
0.09
0.45
91
88
95
92
0.23
0.19
0.44
0.35
0.08
0.43
91
88
94
91
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VP = 5.0V, Id = 0.5 A - 600 - mΩ
VP = 3.7V, Id = 0.5 A - 640 - mΩ
W
W
W
W
W
W
W
W
W
W
W
W
rms
rms
rms
rms
%
%
dB
dB
dB
dB
rms
rms
rms
rms
%
%
dB
dB
dB
dB
rms
rms
rms
rms
%
%
dB
dB
dB
dB
DS792F2 13
Confidential Draft
AOUTx
AGND
R
L
C
L
0.022 μF
51 Ω
Figure 2. Headphone Output Test Load
3/4/10
CS43L22
Parameters (Note 7) Symbol Conditions Min Typ Max Units
MOSFET On Resistance R
DS(ON)
Efficiency η VP = 5.0V, P
Output Operating Peak Current I
VP Input Current During Reset I
PC
VP
VP = 2.5V, Id = 0.5 A - 760 - mΩ
= 2 x 0.8 W, RL =
O
-81-%
8 Ω
--1.5A
RESET, pin 32, is held low
-0.85.0µA
6. The PWM driver should be used in captive speaker systems only.
7. Optimal PWM performance is achieved when MCLK > 12 MHz.
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Frequency = 48 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz; Test load RL = 16 Ω, CL = 10 pF (see Figure 2); “Required Initialization Settings”
on page 32 written on power up.
Parameters VA = 2.5V
Min Typ Max
AOUTx Power Into RL = 16
HP_GAIN[2:0] Analog
Gain (G)
000 0.3959 1.8 V - 14 - - 7 - mW
001 0.4571 1.8 V - 19 - - 10 - mW
010 0.5111 1.8 V - 23 - - 12 - mW
011 (default) 0.6047 1.8 V (Note 8) - 17 - mW
100 0.7099 1.8 V (Note 8) - 23 - mW
101 0.8399 1.8 V (Note 4) See Figure 18 on
110 1.0000 1.8 V (Note 4, 8) See Figures 18 and 19 on page 59 mW
111 1.1430 1.8 V mW
Ω
VHP
2.5 V - 14 - - 7 - mW
2.5 V - 19 - - 10 - mW
2.5 V - 23 - - 12 - mW
2.5 V - 32 - - 17 - mW
2.5 V - 44 - - 23 - mW
2.5 V - 32 - mW
2.5 V mW
2.5 V mW
Min Typ Max
8. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.
VA = 1.8V
page 59
Unit
mW
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
14 DS792F2
Confidential Draft
3/4/10
CS43L22
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz
to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 kΩ, CL = 10 pF (see Figure 2); “Required Initialization Settings” on
page 32 written on power up.
Parameters VA = 2.5V
Min Typ Max
AOUTx Voltage Into RL = 10 k
HP_GAIN[2:0] Analog
Gain (G)
000 0.3959 1.8 V - 1.34 - - 0.97 - V
001 0.4571 1.8 V - 1.55 - - 1.12 - V
010 0.51 11 1.8 V - 1.73 - - 1.25 - V
011 (default) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 V
100 0.7099 1.8 V - 2.41 - - 1.73 - V
101 0.8399 1.8 V - 2.85 - 2.05 V
1 1 0 1.0000 1.8 V - 3.39 - - 2.44 - V
111 1.1430 1.8 V (See (Note 8) 2.79 V
Ω
VHP
2.5 V - 1.34 - - 0.97 - V
2.5 V - 1.55 - - 1.12 - V
2.5 V - 1.73 - - 1.25 - V
2.5 V 1.95 2.05 2.15 - 1.48 - V
2.5 V - 2.41 - - 1.73 - V
2.5 V - 2.85 - - 2.05 - V
2.5 V - 3.39 - - 2.44 - V
2.5 V - 3.88 - - 2.79 - V
Min Typ Max
VA = 1.8V
Unit
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameters (Note 9) Min Typ Max Unit
Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB
Passband to -0.05 dB corner
to -3 dB corner00
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 10) 50 - - dB
Group Delay - 9/Fs - s
De-emphasis Error Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 22 and 25 on
page 63) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
10. Measurement Bandwidth is from Stopband to 3 Fs.
-
-
-
-
-
0.4780
0.4996
+1.5/+0
+0.05/-0.25
-0.2/-0.4
Fs
Fs
dB
dB
dB
DS792F2 15
Confidential Draft
//
//
//
//
//
//
t
s(SD-SK)
MSB MSB-1
LRCK
SCLK
SDIN
t
s(LK-SK)
t
P
t
h
Figure 3. Serial Audio Interface Timing
3/4/10
CS43L22
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND; Logic 1 = VL.
Parameters Symbol Min Max Units
RESET pin Low Pulse Width (Note 11)
MCLK Frequency (Note 12) (See “Serial Port Clock-
MCLK Duty Cycle 45 55 %
Slave Mode
Sample Rate (LRCK) F
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/t
SCLK Duty Cycle 45 55 %
LRCK Setup Time Before SCLK Rising Edge t
SDIN Setup Time Before SCLK Rising Edge t
SDIN Hold Time After SCLK Rising Edge t
s
P
s(LK-SK)
s(SD-SK)
h
Master Mode
Sample Rate (LRCK) F
LRCK Duty Cycle 45 55 %
SCLK Frequency SCLK=MCLK mode 1/t
MCLK=12.0000 MHz 1/t
all other modes 1/t
SCLK Duty Cycle 45 55 %
SDIN Setup Time Before SCLK Rising Edge t
SDIN Hold Time After SCLK Rising Edge t
s
P
P
P
s(SD-SK)
h
11. After powering up the CS43L22, RESET should be held low after the power supplies and clocks are
settled.
12. See “Example System Clock Frequencies” on page 61 for typical MCLK frequencies.
1-ms
MHz
ing” on page 29)
(See “Serial Port Clock-
ing” on page 29)
-64•FsHz
40 - ns
20 - ns
20 - ns
(See “Serial Port Clock-
ing” on page 29)
- 12.0000 MHz
-68•FsHz
-64•FsHz
20 - ns
20 - ns
kHz
Hz
16 DS792F2
Confidential Draft
t
buf
t
hdst
t
hdst
t
low
t
r
t
f
t
hdd
t
high
t
sud
t
sust
t
susp
Stop Start
Start
Stop
Repeated
SDA
SCL
t
irs
RESET
Figure 4. Control Port Timing - I²C
3/4/10
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND; Logic 1 = V; SDA CL=30pF.
Parameters Symbol Min Max Unit
SCL Clock Frequency f
RESET Rising Edge to Start
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 13) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
scl
t
irs
buf
hdst
low
high
sust
hdd
sud
rc
fc
susp
ack
CS43L22
- 100 kHz
550 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 1000 ns
DS792F2 17
Confidential Draft
3/4/10
CS43L22
DC ELECTRICAL CHARACTERISTICS
AGND = 0 V; all voltages with respect to ground.
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink
Power Supply Rejection Ratio Characteristics
PSRR @ 1 kHz (Note 14) DAC (HP & Line Amps) - 60 - dB
PSRR @ 60 Hz (Note 14) DAC (HP & Line Amps) - 60 - dB
PSRR @ 217 Hz Full-Bridge PWM Outputs - 56 - dB
-
-
-
0.5•VA
23
-
-
-
1
V
kΩ
μA
14. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 15) Symbol Min Max Units
Input Leakage Current I
Input Capacitance -10pF
1.8 V - 3.3 V Logic
High-Level Output Voltage (I
Low-Level Output Voltage (IOL = 100 μA) V
High-Level Input Voltage VL = 1.65 V
Low-Level Input Voltage V
= -100 μA) V
OH
VL = 1.8 V
VL = 2.0 V
VL > 2.0 V
in
OH
OL
V
IH
IL
-±10μA
VL - 0.2 - V
-0.2V
0.85•VL
0.77•VL
0.68•VL
0.65•VL
- 0.30•VL V
-
-
-
-
V
V
V
V
15. See “I/O Pin Characteristics” on page 8 for serial and control port power rails.
18 DS792F2
Confidential Draft
POWER CONSUMPTION
Operation
1
Off (Note 17)
Standby (Note 18)
2
Stereo Passthrough to Headphone
3
Mono Playback to Headphone
4
Stereo Playback to Headphone
5
Mono Playback to Speaker
6
Stereo Playback to Speaker
7
3/4/10
See (Note 16)
Register Settings Typical Current (mA)
02h 04h
i
VHP
PDN[7:0]
PDN_HPA[1:0]
PDN_HPB[1:0]
PDN_SPKB[1:0]
PDN_SPKA[1:0]
V
x x x x x 1.8 0.00 0.00 0.00
2.5 0.00 0.00 0.00 0.00
0x9F x x x x 1.8 0.00 0.00 0.01
2.5 0.00 0.00 0.02 0.05
0x9E 10 10 11 1 1 1.8 2.79 1.91 1 .06
2.5 3.18 2.14 1.81 17.85
0x9E 10 11 11 11 1.8 1.59 1.99 2.72
2.5 2.07 2.62 4.27 22.43
0x9E 10 10 11 11 1.8 2.77 2.00 2.91
2.5 3.27 2.63 4.28 25.48
0x9E 11 11 10 10 1.8 0.00 0.20 4.42
2.5 0.00 0.22 6.77 21.21
0x9E 11 11 10 10 1.8 0.00 0.20 4.38
2.5 0.00 0.22 6.80 21.28
i
VA
i
VD
i
VL
VL=3.3V
(Note 19)
VP=3.7V
0.00 0.00
0.00 0.00
0.01 0.00
0.01 0.00
0.01 0.00
0.01 1.00
0.01 1.00
CS43L22
i
VP
Total
Power
(mW
0.00
0.02
10.39
11.36
13.84
12.05
11.98
rms
)
16. Unless otherwise noted, test conditions are as follows: All zeros input, Slave Mode, sample
rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode
and master/slave operation.“Required Initialization Settings” on page 32 written on power up.
17. RESET
18. RESET
pin 25 held LO, all clocks and data lines are held LO.
pin 25 held HI, all clocks and data lines are held HI.
19. VL current will slightly increase in Master Mode.
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Confidential Draft
4. APPLICATIONS
4.1 Overview
4.1.1 Basic Architecture
The CS43L22 is a highly integrated, low power, 24-bit audio DAC comprised of a Digital Signal Processing
Engine, headphone amplifiers, a digital PWM modulator and two full-bridge power ba ck-end s. Other features include battery level monitoring and compensation and temperature monitoring. The DAC is designed using multi-bit delta-sigma techniques and operates at an oversampling ratio of 128Fs, where Fs
is equal to the system sample rate.
The PWM modulator operates at a fixed frequency of 384 kHz. The power MOSFETs are configured for
either stereo full-bridge or mono parallel full bridge output. The DAC operates in one of four sample rate
speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks
(SCLK, LRCK) derived from an input Master Clock (MCLK).
4.1.2 Line Inputs
4 pairs of stereo analog inputs are provided for applications that require analog passthrough directly to
the HP/Line amplifiers. This analog input portion allows selection from and configuration of multiple combinations of these stereo sources.
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CS43L22
4.1.3 Line & Headphone Outputs
The analog output portion of the CS43L22 includes a head phone amplifier ca pable o f driving he adphone
and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale
output swing centered around groun d. Th is elim in at es the need for large DC-Blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages.
4.1.4 Speaker Driver Outputs
The Class D power amplifiers drive 8 Ω (stereo) and 4 Ω (mono) speakers directly, without the need for
an external filter. The power MOSFETS are powered directly from a battery eliminating the efficiency loss
associated with an external regulator. Battery level monitoring and compensation maintains a steady output as battery levels fall. A temperature monitor continually measures the die temperature and registers
when predefined thresholds are exceeded.
systems where the outputs are permanently tied to the speaker terminals.
4.1.5 Fixed Function DSP Engine
The fixed-function digital signal processing engine processes the PCM serial input data. Independ ent volume control, left/right channel swaps, mono mixes, tone control and limiting functions also comprise the
DSP engine.
4.1.6 Beep Generator
The beep generator delivers tones at select frequencies across approximately two octave major scales.
With independent volume control, beeps may be configured to occur continuously, perio dically, or at single time intervals.
NOTE: The CS43L22 should only be used in captive speaker
4.1.7 Power Management
Two control registers provide independent power-down control of the DAC, Headphone and Speaker output blocks in the CS43L22 allowing operation in select applications with minimal power consumption.
20 DS792F2
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