Cirrus Logic CS43L21 User Manual

1.8 V to 3.3 V

Multibit

Modulator

Charge

Pump

Left HP Out

Right HP Out

Serial Audio

Input

1.8 V to 2.5 V

PCM Serial Interface

Register

Configuration

Level Translator

Reset

Hardware

Mode or I

2

C &

SPI Software

Mode

Control Data

Beep

Generator

MUX

MUX

Headphone
Amp - GND

Centered

Headphone
Amp - GND

Centered

1.8 V to 2.5 V

Switched

Capacitor DAC

and Filter

Switched

Capacitor DAC

and Filter

Digital
Signal

Processing

Engine

CS43L21

Low-Power, Stereo Digital-to-Analog Converter

FEATURES

 98 dB dynamic range (A-weighted)
 -86 dB THD+N
 Headphone amplifier–GND centered

– On-chip charge pump provides -VA_HP
– No DC-blocking capacitor required
– 46 mW power into stereo 16  @ 1.8 V
– 88 mW power into stereo 16  @ 2.5 V
– -75 dB THD+N

 Digital signal processing engine

– Bass and treble tone control, de-emphasis
– PCM mix with independent volume control
– Master digital volume control and limiter
– Soft-ramp and zero-cross transitions

 Beep generator

– Tone selections across two octaves
– Separate volume control
– Programmable On and Off time intervals
– Continuous, periodic, or one-shot beep

selections

 Programmable peak-detect and limiter
 Pop and click suppression

SYSTEM FEATURES

 24-bit Conversion
 4- to 96-kHz sample rate
 Multibit delta–sigma architecture

 Low power operation

– Stereo playback: 12.93 mW @ 1.8 V

 Variable power supplies

– 1.8- to 2.5-V digital and analog
– 1.8- to 3.3-V interface logic

 Power-down management
 Software Mode (I²C™ and SPI™ control)
 Hardware mode (standalone control)
 Digital routing/mixes:

– Mono mixes

 Flexible clocking options

– Master or slave operation
– High-impedance digital output option (for

easy MUXing between DAC and other data
sources)

– Quarter-speed mode (allows 8-kHz Fs

while maintaining a flat noise floor up to
16 kHz)

APPLICATIONS

 Portable audio players
 MD players
 PDAs
 Personal media players
 Portable game consoles
 Smart phones
 Wireless headsets

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2013

(All Rights Reserved)

DS723F1

JAN ‘13

CS43L21

GENERAL DESCRIPTION

The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modu­lation, it allows infinite sample rate adju stm e nt be tw ee n 4 kH z an d 96 kHz. The DAC offers many features suit ab le
for low power, portable system applications.

The DAC output path includes a digital signal processing engine. Tone Control provides bass an d treble adjustment
of four selectable corner frequencies. The Mixer allows independent volume control for PCM mix, as well as a mas­ter digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp
and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering
tones selectable across a range of two full octaves.

The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump pro­vides a negative supply. This allows a ground-centered analog output with a wide signal swing and eliminates
external DC-blocking capacitors.

In addition to its many features, the CS43L21 operates from a low- voltage analog and digital core, makin g this DAC
ideal for portable systems that require extremely low power consumption in a minimal amount of space.

The CS43L21 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (­40 to +85° C). The CS43L21 Customer Demonstration b oa rd is a lso availa ble for d evice evaluation and imp leme n­tation suggestions. Please see “Ordering Information” on page 64 for complete details.

2 DS723F1

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6

1.1 Digital I/O Pin Characteristics ........................................................................................................... 8

2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9

3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11

SPECIFIED OPERATING CONDITIONS ............................................................................................. 11

ABSOLUTE MAXIMUM RATINGS .......................................................................................................11

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 12

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ................ ... ... .... ... ... ...................... 13

LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 14

HEADPHONE OUTPUT POWER CHARACTERISTICS ................................... ... .... ... ... ... ... .... ... ... ... ... 15

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16

SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 16

SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 18

SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 19

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 20

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 20

POWER CONSUMPTION .................................................................................................................... 21

4. APPLICATIONS ................................................................................................................................... 22

4.1 Overview ......................................................................................................................................... 22

4.1.1 Architecture ........................................................................................................................... 22

4.1.2 Line & Headphone Outputs ................................................................................................... 22

4.1.3 Signal Processing Engine ..................................................................................................... 22

4.1.4 Beep Generator ..................................................................................................................... 22

4.1.5 Device Control (Hardware or Software Mode) ...................................................................... 22

4.1.6 Power Management .............................................................................................................. 22

4.2 Hardware Mode .............................................................................................................................. 23

4.3 Analog Outputs ............................................................................................................................... 24

4.3.1 De-Emphasis Filter ................................................................................................................ 24

4.3.2 Volume Controls .................................................................................................................... 25

4.3.3 Mono Channel Mixer ............................................................................................................. 25

4.3.4 Beep Generator ..................................................................................................................... 25

4.3.5 Tone Control .......................................................................................................................... 26

4.3.6 Limiter .................................................................................................................................... 26

4.3.7 Line-Level Outputs and Filtering ........................................................................................... 27

4.3.8 On-Chip Charge Pump .......................................................................................................... 28

4.4 Serial Port Clocking ........................................................................................................................ 28

4.4.1 Slave ..................................................................................................................................... 29

4.4.2 Master ................................................................................................................................... 29

4.4.3 High-Impedance Digital Output ............................................................................................. 30

4.4.4 Quarter- and Half-Speed Mode .................................... .........................................................30

4.5 Digital Interface Formats ................................................................................................................ 30

4.6 Initialization ..................................................................................................................................... 31

4.7 Recommended Power-Up Sequence ............................................................................................. 31

4.8 Recommended Power-Down Sequence ........................................................................................ 32

4.9 Software Mode ............................................................................................................................... 34

4.9.1 SPI Control .............................................................................................................

4.9.2 I²C Control ............................................................................................................................. 34

4.9.3 Memory Address Pointer (MAP) ......................... .......... ......... .......... .......... ......... .......... ......... 36

4.9.3.1 Map Increment (INCR) ..................... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ... 36

5. REGISTER QUICK REFERENCE ........................................................................................................ 37

6. REGISTER DESCRIPTION .................................................................................................................. 40

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40

CS43L21

............... 34

DS723F1 3

CS43L21

6.2 Power Control 1 (Address 02h) ...................................................................................................... 40

6.3 Speed Control (Address 03h) ......................................................................................................... 41

6.4 Interface Control (Address 04h) ..................................................................................................... 42

6.5 DAC Output Control (Address 08h) ................................................................................................ 42

6.6 DAC Control (Address 09h) ............................................................................................................ 43

6.7 PCMX Mixer Volume Control:

PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 45

6.8 Beep Frequency & Timing Configuration (Address 12h) ................................................................ 46

6.9 Beep Off Time & Volume (Address 13h) ........................................................................................ 46

6.10 Beep Configuration & Tone Configuration (Address 14h) ... ......................................................... 48

6.11 Tone Control (Address 15h) ......................................................................................................... 49

6.12 AOUTx Volume Control:

AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 49

6.13 PCM Channel Mixer (Address 18h) .............................................................................................. 50

6.14 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 51

6.15 Limiter Release Rate Register (Address 1Ah) .............................................................................. 52

6.16 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 53

6.17 Status (Address 20h) (Read Only) ............................................................................................... 53

6.18 Charge Pump Frequency (Address 21h) ...................................................................................... 54

7. ANALOG PERFORMANCE PLOTS .......... ... .... ... ... ... .... ... ... ... .... ... ... .......................................... ... ... ...55

7.1 Headphone THD+N versus Output Power Plots ............................................................................ 55

7.2 Headphone Amplifier Efficiency ................................................................................................ ...... 57

8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 58

8.1 Auto Detect Enabled ....................................................................................................................... 58

8.2 Auto Detect Disabled ...................................................................................................................... 59

9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 60

9.1 Power Supply, Grounding ............................................................................................................... 60

9.2 QFN Thermal Pad .......................................................................................................................... 60

10. DIGITAL FILTERS .............................................................................................................................. 61

11. PARAMETER DEFINITIONS .............................................................................................................. 62

12. REFERENCES .................................................................................................................................... 62

13. PACKAGE DIMENSIONS ............................................................................................................. 63

THERMAL CHARACTERISTICS .......................................................................................................... 63

14. ORDERING INFORMATION ............................................................................................................. 64

15. REVISION HISTORY ......................................................................................................................... 64

LIST OF FIGURES

Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9

Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10

Figure 3.Headphone Output Test Load ..................................................................................................... 15

Figure 4.Serial Audio Interface Slave Mode Timing ..................... .......................................... ................... 17

Figure 5.Serial Audio Interface Master Mode Timing ....................................... ... ... ... .... ... ... ... ... .... ... ... ...... 17

Figure 6.Control Port Timing - I²C ... ... .... ... ... ... ... .......................................... .... ... ... ... .... ... ... ... ................... 18

Figure 7.Control Port Timing - SPI Format ............................. ... ... .... ... ... ... ................................................ 19

Figure 8.Output Architecture ..................................................................................................................... 24

Figure 9.De-Emphasis Curve .................................... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ......................... 25

Figure 10.Beep Configuration Options ...................................................................................................... 26

Figure 11.Peak Detect & Limiter ............................................................................................................... 27

Figure 12.Master Mode Timing .................... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ................................................ 29

Figure 13.Tri-State SCLK/LRCK .................. ... ... ....................................................................................... 30

Figure 14.I²S Format ............. .... ... ... ... .... ... .......................................... ... ... ... .... ... ... ... .... ... ......................... 30

Figure 15.Left-Justified Format .............. ... ... ... ... .... ... ... ... .... ... ... ... .... ......................................................... 31

Figure 16.Right-Justified Format (DAC only) ..... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ......................................... 31

Figure 17.Initialization Flow Chart ................................ .......................................... ................................... 33

4 DS723F1

Figure 18.Control Port Timing in SPI Mode .............................. ... .... ... ... ... ... .... ... ...................................... 34

Figure 19.Control Port Timing, I²C Write ................................................................................................... 35

Figure 20.Control Port Timing, I²C Read ................................................................................................... 35

Figure 21.THD+N vs. Output Power per Channel at 1.8 V (16  load) .................................................... 55

Figure 22.THD+N vs. Output Power per Channel at 2.5 V (16  load) .................................................... 55

Figure 23.THD+N vs. Output Power per Channel at 1.8 V (32  load) .................................................... 56

Figure 24.THD+N vs. Output Power per Channel at 2.5 V (32  load) .................................................... 56

Figure 25.Power Dissipation vs. Output Power into Stereo 16 

Figure 26.Power Dissipation vs. Output Power into Stereo 16 (Log Detail) .... ... ... .... ... ......................... 57

Figure 27.Passband Ripple ....................................................................................................................... 61

Figure 28.Stopband ................................................................................................................................... 61

Figure 29.Transition Band ......................................................................................................................... 61

Figure 30.Transition Band (Detail) ............................................................................................................ 61

LIST OF TABLES

Table 1. I/O Power Rails ............................................................................................................................. 8

Table 2. Hardware Mode Feature Summary ............................................................................................. 23

Table 3. MCLK/LRCK Ratios .................... ... ... ... .... ... .......................................... ... ... .... ... ... ...................... 29

CS43L21

DS723F1 5

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE

109

8

7

6

5

4

3

2

1

11

12

13 14 15 16

17

18

19

20

21

22

23

24

25

262728

29

303132

CS43L21

VD

DGND

TSTO(M/S

)

MCLK

SDIN

SCLK

VSS_HP

AOUTB

AOUTA

VA

AGND

FILT+

NIC

VQ

SDA/CDIN (MCLKDIV2)

SCL/CCLK (I²S/LJ

)

ADO/CS

(DEM)

FLYP

VL

RESET

GND_HP

FLYN

TSTO

TSTO

TSTO

TSTO

TSTO

TSTO

TSTO

TSTO

VA_HP

LRCK

CS43L21

Pin Name # Pin Description

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

LRCK

SDA/CDIN
(MCLKDIV2)

SCL/CCLK

)

(I²S/LJ

AD0/CS
(DEM)

VA_HP
FLYP
GND_HP
FLYN

VSS_HP

6 DS723F1

1

serial audio data line.
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the

control port interface in SPI Mode.

2

MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
Serial Control Port Clock (Input) - Serial clock for the serial control port.

3

Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-
mats for the DAC.

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
is the chip-select signal for SPI format.

4

De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.

5

Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.

6
7
8

9

Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.
Analog Ground (Input) - Ground reference for the internal headphone/charge pump section.
Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.
Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-

phone section.

CS43L21

AOUTB
AOUTA

VA
AGND
FILT+
VQ

NIC

TSTO

TSTO

TSTO

TSTO

TSTO

TSTO
RESET
VL
VD

DGND

TSTO
(M/S

)

MCLK
SCLK
SDIN
Thermal Pad

10

Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-

11

tics specification table

12

Analog Power (Input) - Positive power for the internal analog section.

13

Analog Ground (Input) - Ground reference for the internal analog section.

14

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

15

Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
Not Internally Connected - This pin is not connected internal to the device and may be connected to

16

ground or left “floating”. No other external connection should be made to this pin.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

17

nection external to the pin).
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

18

nection external to the pin).
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

19

nection external to the pin).
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

20

nection external to the pin).

21

Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

22

nection external to the pin).

23

Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

24

nection external to the pin).

25

Reset (Input) - The device enters a low power mode when this pin is driven low.
Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and

26

host control port. Refer to the Recommended Operating Conditions for appropriate voltages.

27

Digital Power (Input) - Positive power for the internal digital section.

28

Digital Ground (Input) - Ground reference for the internal digital section.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

29

Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and
Slave Mode for the serial port.

30

Master Clock (Input) - Clock source for the delta-sigma modulators.

31

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

32

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

-

Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 60.

DS723F1 7

1.1 Digital I/O Pin Characteristics

The logic level for each input should not exceed the maximum ratings for the VL power supply.

CS43L21

Pin Name

SW/(HW)

RESET Input

SCL/CCLK

(I²S/LJ)

SDA/CDIN

(MCLKDIV2)

AD0/CS

(DEM)

MCLK Input
LRCK Input/Output

SCLK Input/Output

TSTO

(M/S)
SDIN Input

Input

Input/Output

Input

Input/Output

I/O Driver Receiver

- 1.8 V - 3.3 V

- 1.8 V - 3.3 V, with Hysteresis

1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis

- 1.8 V - 3.3 V

- 1.8 V - 3.3 V

1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

- 1.8 V - 3.3 V

Table 1. I/O Power Rails

8 DS723F1

2. TYPICAL CONNECTION DIAGRAMS

1 µF

+1.8 V or +2.5 V

1 µF

VQ

FILT+

0.1 µF

1 µF

DGND

VL

0.1 µF

+1.8 V, +2.5 V

or +3.3 V

SCL/CCLK
SDA/CDIN

RESET

2 k



See Note 1

LRCK

AGND

AD0/CS

MCLK
SCLK

0.1 µF

VA_HP

VD

SDIN

CS43L21

2 k



1 µF

+1.8 V or +2.5 V

AOUTB

AOUTA

470



470



C

C

R

ext

R

ext

See Note 2

Note 1:

Resistors are required for I²C
control port operation

For best response to Fs/2 :



4704

470



ext

ext

RFs

R

C



This circuitry is intended for applications where the
CS43L21 connects directly to an unbalanced output of the
device. For internal routing applications please see the
DAC Analog Output Characteristics section for loading
limitations.

Note 2 :

Digital Audio

Processor

0.1 µF

VA

Headphone Out
Left & Right

Line Level Out
Left & Right

Speaker Driver

FLYP
FLYN
VSS_HP

GND_HP

1 µF

51.1 

0.022 µF

1 µF

**

**

* *Use low ESR ceramic capacitors.

See Note 3

Note 3:

Series resistance in the path of the power supplies must
be avoided. Any voltage drop on VA_HP will directly
impact the negative charge pump supply (VSS_HP) and
result in clipping on the audio output .

1.5 µF

1.5 µF

See Note 4

Note 4 :

Larger capacitors, such as 1.5 µF, improves the charge
pump performance (and subsequent THD+N) at the full
scale output power achieved with gain (G) settings
greater than default.

**

**

Figure 1. Typical Connection Diagram (Software Mode)

CS43L21

DS723F1 9

CS43L21

+1.8V or +2.5V

1 µF

VQ

FILT+

0.1 µF

1 µF

DGND

VL

0.1 µF

+1.8V, 2.5 V

or +3.3V

I²S/LJ
MCLKDIV2

RESET

LRCK

AGND

DEM

MCLK

SCLK

0.1 µF

VA_HP

VD

SDIN

CS43L21

1 µF

+1.8V or +2.5V

AOUTB

AOUTA

470

470

C

C

R

ext

R

ext

See Note 2

For best response to Fs/2 :



4704

470



ext

ext

RFs

R

C



This circuitry is intended for applications where the CS43L21 connects directly to an unbalanced output of the device . For
internal routing applications please see the DAC Analog Output Characteristics section for loading limitations .

Note 2 :

Digital Audio

Processor

0.1 µF

VA

Headphone Out
Left & Right

Line Level Out
Left & Right

Speaker Driver

FLYP
FLYN
VSS_HP

GND_HP

51.1 

0.022 µF

1 µF

See Note 1

Note 1:

Series resistance in the path of the power supplies (typically
used for added filtering) must be avoided. Any voltage drop
on VA_HP will directly impact the negative charge p ump
supply (VSS_HP) and result in clipping on the audio output.

1 µF

1 µF

**

**

* *Use low ESR ceramic capacitors.

See Note 3

Note 3:
Pull-up to VL (47 kfor Master Mode. Pull-
down to DGND for Slave Mode.

47k

TSTO/M/S

VL or DGND

k

Figure 2. Typical Connection Diagram (Hardware Mode)

10 DS723F1

CS43L21

3. CHARACTERISTIC AND SPECIFICATION TABLES

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per­formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T

= 25° C.)

A

SPECIFIED OPERATING CONDITIONS

(AGND=DGND=0 V, all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply (Note 1)
Analog Core
Headphone Amplifier
Digital Core
Serial/Control Port Interface
Ambient Temperature Commercial - CNZ

Automotive - DNZ

VA 1.65 2.63 V

VA_HP 1.65 2.63 V

VD 1.65 2.63 V

VL 1.65 3.47 V
T

A

-10

-40

+70
+85

C
C

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial/Control Port Interface

Input Current (Note 2)
External Voltage Applied to Analog Output
External Voltage Applied to Digital Input (Note 3) V

Ambient Operating Temperature (power applied)
Storage Temperature

VA, VA_HP

VD
VL

V

T

T

I

in

IN

IND

A

stg

-0.3

-0.3

-0.3

-±10mA

-VA_HP - 0.3 +VA_HP + 0.3

-0.3 VL+ 0.3 V

-50 +115 °C

-65 +150 °C

3.0

3.0

4.0

V
V
V

V

WARNING:Operation at or beyo nd these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Notes:

1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and
serial/control port interface supplies.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

DS723F1 11

CS43L21

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)

(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R

(see Figure 3), and test load R

= 16  CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)

L

= 10 k CL = 10 pFfor the line output

L

Parameter (Note 4)

R

= 10 k

L

Dynamic Range

18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted

unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

RL = 16 

Dynamic Range
18 to 24-Bit A-weighted

unweighted
16-Bit A-weighted

unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Other Characteristics for RL = 16  or 10 k

Output Parameters Modulation Index (MI)

(Note 5) Analog Gain Multiplier (G)

Full-scale Output Voltage (2•G•MI•VA) (Note 5)

Full-scale Output Power (Note 5)
Interchannel Isolation (1 kHz) 16 

Interchannel Gain Mismatch
Gain Drift
AC-Load Resistance (R

Load Capacitance (C

) (Note 6)

L

) (Note 6)

L



10 k

VA = 2.5V (nominal)

Min Typ Max

92
89

-

-

-

-

-

-

-

-

92
89

-

-

-

-

-

-

-

-

-

Refer to Table “Line Output Voltage Characteristics” on

Refer to Table “Headphone Output Power Characteristics”

-

-

- 0.1 0.25 - 0.1 0.25 dB

- ±100 - - ±100 -

16 - - 16 - - 

- - 150 - - 150 pF

98
95
96
93

-86

-75

-35

-86

-73

-33

98
95
96
93

-75

-75

-35

-75

-73

-33

0.6787

0.6047

80
95

-

-

-

-

-78

-

-

-

-

-

-

-

-

-

-69

-

-

-

-

-

--

page 14

on page 15

-

-

VA = 1.8V (nominal)

Min Typ Max Unit

89
86

-

-

-

-

-

-

-

-

89
86

-

-

-

-

-

-

-

-

-

-

95
92
93
90

-88

-72

-32

-88

-70

-30

95
92
93
90

-75

-72

-32

-75

-70

-30

0.6787

0.6047

80
93

-

-

-

-

-82

-

-

-

-

-

-

-

-

-

-69

-

-

-

-

-

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

Vpp

mW

dB
dB

ppm/°

C

12 DS723F1

CS43L21

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)

(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load R

line output (see Figure 3), and test load R

= 16  CL = 10 pF (see Figure 3) for the headphone output.

L

HP_GAIN[2:0] = 011.)

= 10 k CL = 10 pFfor the

L

Parameter (Note 4)

R

= 10 k

L

Dynamic Range

18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted

unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

RL = 16



Dynamic Range

18 to 24-Bit A-weighted

unweighted
16-Bit A-weighted

unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Other Characteristics for RL = 16  or 10 k

Output Parameters Modulation Index (MI)

(Note 5) Analog Gain Multiplier (G)

Full-scale Output Voltage (2•G•MI•VA) (Note 5)

Full-scale Output Power (Note 5)
Interchannel Isolation (1 kHz) 16 

Interchannel Gain Mismatch
Gain Drift
AC-Load Resistance (R

Load Capacitance (C

) (Note 6)

L

) (Note 6)

L



10 k

VA = 2.5V (nominal)

Min Typ Max

90
87

-

-

-

-

-

-

-

-

90
87

-

-

-

-

-

-

-

-

-

Refer to Table “Line Output Voltage Characteristics” on

Refer to Table “Headphone Output Power Characteristics”

-

-

- 0.1 0.25 - 0.1 0.25 dB

- ±100 - - ±100 -

16 - - 16 - - 

- - 150 - - 150 pF

98
95
96
93

-86

-75

-35

-86

-73

-33

98
95
96
93

-75

-75

-35

-75

-73

-33

0.6787

0.6047

80
95

-

-

-

-

-73

-

-

-

-

-

-

-

-

-

-67

-

-

-

-

-

--

page 14

on page 15

-

-

VA = 1.8V (nominal)

Min Typ Max Unit

87
84

-

-

-

-

-

-

-

-

87
84

-

-

-

-

-

-

-

-

-

-

95
92
93
90

-88

-72

-32

-88

-70

-30

95
92
93
90

-75

-72

-32

-75

-70

-30

0.6787

0.6047

80
93

-

-

-

-

-80

-

-

-

-

-

-

-

-

-

-67

-

-

-

-

-

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

Vpp

mW

dB
dB

ppm/°

C

DS723F1 13

CS43L21

LINE OUTPUT VOLTAGE CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band­width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R

= 10 k CL = 10 pF (see Figure 3).

L

Parameter

AOUTx Voltage Into R

HP_GAIN[2:0]

000 0.3959

001 0.4571

010 0.5111

011 (default) 0.6047

100 0.7099

101 0.8399

110 1.0000

111 1.1430

Analog

Gain (G)

= 10 k

L

VA = 2.5V (nominal)

Min Typ Max

VA = 1.8V (nominal)

Min Typ Max Unit



VA_HP

1.8 V - 1.34 - - 0.97 - V

2.5 V - 1.34 - - 0.97 - V

1.8 V - 1.55 - - 1.12 - V

2.5 V - 1.55 - - 1.12 - V

1.8 V - 1.73 - - 1.25 - V

2.5 V - 1.73 - - 1.25 - V

1.8 V - 2.05 - 1.41 1.48 1.55 V

2.5 V 1.95 2.05 2.15 - 1.48 - V

1.8 V - 2.41 - - 1.73 - V

2.5 V - 2.41 - - 1.73 - V

1.8 V - 2.85 - 2.05 V

2.5 V - 2.85 - - 2.05 - V

1.8 V - 3.39 - - 2.44 - V

2.5 V - 3.39 - - 2.44 - V

1.8 V

2.5 V - 3.88 - - 2.79 - V

(See (Note 7) 2.79 V

pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp

14 DS723F1

CS43L21

AOUTx

AGND

R

L

C

L

0.022 F

51 

Figure 3. Headphone Output Test Load

HEADPHONE OUTPUT POWER CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band­width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R

= 16  CL = 10 pF (see Figure 3).

L

Parameter

AOUTx Power Into R

HP_GAIN[2:0]

000 0.3959

001 0.4571

010 0.5111

011 (default) 0.6047

100 0.7099

101 0.8399

110 1.0000

111 1.1430

Analog
Gain (G)

4. One LSB of triangular PDF dither is added to data.

5. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog

Gain (HP_GAIN[2:0])” on page 42. High gain settings at certain VA and VA_HP supply levels may

cause clipping when the audio signal approaches full-scale, maximum power output, as shown in

Figures 21 - 24 on page 56.

6. See Figure 3. R
quired for the internal op-amp's stability and signal integrity. In this circuit topology, C
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom­mended 150 pF can cause the internal op-amp to become unstable.

7. VA_HP settings lower than VA reduces the headroom of the headph one amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.

= 16

L

VA = 2.5V (nominal)

Min Typ Max



VA = 1.8V (nominal)

Min Typ Max Unit

VA_HP

1.8 V - 14 - - 7 - mW

2.5 V - 14 - - 7 - mW

1.8 V - 19 - - 10 - mW

2.5 V - 19 - - 10 - mW

1.8 V - 23 - - 12 - mW

2.5 V - 23 - - 12 - mW

1.8 V (Note 7) -17 -mW

2.5 V - 32 - - 17 - mW

1.8 V (Note 7) -23 -mW

2.5 V - 44 - - 23 - mW

1.8 V (Note 5) mW

2.5 V -32 -mW

1.8 V

2.5 V mW

(Note 5, 7)

1.8 V mW

2.5 V mW

and CL reflect the recommended minimum resistance and maximum capacitance re-

L

will effectively

L

mW

rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms

DS723F1 15

CS43L21

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Parameter

Frequency Response 10 Hz to 20 kHz
Passband to -0.05 dB corner

StopBand
StopBand Attenuation (Note 9)
Group Delay
De-emphasis Error Fs = 32 kHz

(Note 8) Min Typ Max Unit

to -3 dB corner

Fs = 44.1 kHz

Fs = 48 kHz

Notes:

8. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30

on page 61) have been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs.

9. Measurement Bandwidth is from Stopband to 3 Fs.

SWITCHING SPECIFICATIONS - SERIAL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL.)

Parameters Symbol Min Max Units

RESET

MCLK Frequency
MCLK Duty Cycle (Note 11)

Slave Mode

Input Sample Rate (LRCK) Quarter-Speed Mode

LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge

pin Low Pulse Width (Not e 10)

Half-Speed Mode

Single-Speed Mode

Double-Speed Mode

-0.01 - +0.08 dB
0

0

0.5465 - - Fs
50 - - dB

- 10.4/Fs - s

-

-

-

F

s

F

s

F

s

F

s

1/t

P

t

s(LK-SK)

t

s(SD-SK)

t

h

-

-

-

-

-

1-ms

1.024 38.4 MHz
45 55 %

4
8
4

50
45 55 %

-64•FsHz
45 55 %
40 - ns
20 - ns
20 - ns

0.4780

0.4996

+1.5/+0

+0.05/-0.25

-0.2/-0.4

12.5
25
50

100

kHz
kHz
kHz
kHz

Fs
Fs

dB
dB
dB

16 DS723F1

Master Mode (Note 12)

MCLK

128

-----------------

//

//

//

//

//

//

t

s(SD-SK)

MSB MSB-1

LRCK

SCLK

SDIN

t

s(LK-SK)

t

P

t

h

Figure 4. Serial Audio Interface Slave Mode Timing

//

//

//

//

//

//

t

s(SD-SK)

MSB MSB-1

LRCK

SCLK

SDIN

t

d(MSB)

t

P

t

h

Figure 5. Serial Audio Interface Master Mode Timing

CS43L21

Parameters Symbol Min Max Units

Output Sample Rate (LRCK) All Speed Modes

(Note 13)

LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDIN MSB Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge

10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are
settled.

11. See “Example System Clock Frequencies” on page 58 for typical MCLK frequencies.

12. See“Master” on page 29.

13. “MCLK” refers to the external master clock applied.

F

s

1/t

P

t

d(MSB)

t

s(SD-SK)

t

h

-Hz

45 55 %

- 64•F

s

Hz

45 55 %

52 ns
20 - ns
20 - ns

DS723F1 17

SWITCHING SPECIFICATIONS - I²C CONTROL PORT

t

buf

t

hdst

t

hdst

t

low

t

r

t

f

t

hdd

t

high

t

sud

t

sust

t

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

t

irs

RST

Figure 6. Control Port Timing - I²C

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency

RESET Rising Edge to Start

Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 14)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling

f
t
t

t

hdst

t

low

t

high

t

sust

t

hdd

t

sud

t
t

t

susp

t

ack

scl

irs

buf

rc

fc

CS43L21

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

300 3450 ns

14. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

fc

18 DS723F1

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

CS

CCLK

CDIN

RST

t

srs

t

scl

t

sch

t

css

t

r2

t

f2

t

csh

t

dsu

t

dh

Figure 7. Control Port Timing - SPI Format

(Inputs: Logic 0 = DGN D, Lo gic 1 = VL)

Parameter Symbol Min Max Units

CS43L21

CCLK Clock Frequency

RESET Rising Edge to CS Falling

Falling to CCLK Edge

CS
CS

High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 15)
Rise Time of CCLK and CDIN (Note 16)
Fall Time of CCLK and CDIN (Note 16)

15. Data must be held for sufficient time to bridge the transition time of CCLK.

16. For f

<1 MHz.

sck

f

t
t

t
t

sck

t

srs

css

csh

t

scl

sch

dsu

t

t
t

06.0MHz
20 - ns
20 - ns

1.0 - s
66 - ns
66 - ns
40 - ns

dh

r2

f2

15 - ns

-100ns

-100ns

DS723F1 19

DC ELECTRICAL CHARACTERISTICS

(AGND = 0 V; all voltages with respect to ground.)

Parameters Min Typ Max Units

VQ Characteristics

Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 17)

FILT+

-

-

-

-VA-V

0.5•VA
23

-

VSS_HP Characteristics

Nominal Voltage
DC Current Source

Power Supply Rejection Ratio (PSRR) (Note 18) 1 kHz

-

-

-60-dB

-0.8•(VA_HP) -

17. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage
through electrolytic de-coupling capacitors.

18. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS

Parameters (Note 19) Symbol Min Max Units

Input Leakage Current
Input Capacitance

1.8 V - 3.3 V Logic
High-Level Output Voltage (I

Low-Level Output Voltage
High-Level Input Voltage

Low-Level Input Voltage

= -100 A)

OH

(IOL = 100 A)

I

in

V

OH

V

OL

V

IH

V

IL

-±10A

-10pF

VL - 0.2 - V

-0.2V

0.68•VL - V

- 0.32•VL V

CS43L21

-

-

10

10

V
k
A

V
A

19. See “Digital I/O Pin Characteristics” on page 8 for serial and control port power rails.

20 DS723F1