–32 kHz to 54 kHz Sampling Rates
–50 kHz to 108 kHz Sampling Rates
–100 kHz to 216 kHz Sampling Rates
Selectable Serial Audio Interface Formats
–Left-Justified, up to 24 bit
–I²S, up to 24 bit
–Right-Justified 16 bit
–Right-Justified 24 bit
Auto Mute Output Polarity Detect
Auto Mute on Static PCM Samples
44.1 kHz 50/15 µs De-Emphasis Available
Soft Volume Ramp-up after Reset is Released
Control Port Mode Features
Selectable Oversampling Modes
–32 kHz to 54 kHz Sampling Rates
–50 kHz to 108 kHz Sampling Rates
–100 kHz to 216 kHz Sampling Rates
Selectable Serial Audio Interface Formats
–Left-Justified, up to 24 bit
–I²S, up to 24 bit
–Right-Justified 16 bit
–Right-Justified 18 bit
–Right-Justified 20 bit
–Right-Justified 24 bit
Direct Stream Digital Mode
Selectable Auto or Manual Mute Polarity
Selectable Interpolation Filters
Selectable 32, 44.1, and 48 kHz De-Emphasis
Configurable ATAPI Mixing Functions
Configurable Volume and Muting Controls
Description
The CS4398 is a complete stereo 24 bit/192 kHz digitalto-analog system. This D/A system includes digital deemphasis, half dB step size volume control, ATAPI
channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled multi-bit deltasigma modulator that includes mismatch shaping technology that eliminates distortion due to capacitor
mismatch. Following this stage is a multi-element
switched capacitor stage and low pass filter with differential analog outputs.
The CS4398 also has an proprietary DSD processor
that allows for volume control and 50 kHz on-chip filtering without an intermediate decimation stage. It also
offers an optional path for direct DSD conversion by directly using the multi-element switched capacitor array.
The CS4398 accepts PCM data at sample rates from
32 kHz to 216 kHz, DSD audio data, has selectable digital filters, consumes little power, and delivers excellent
sound quality.
DSD_SCLK2DSD SerialClock (Input) - Serial clock for the Direct Stream Digital audio interface.
SDIN3Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK4SerialClock (Input) - Serial clock for the serial audio interface.
LRCK5
MCLK6Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD7Digital Power (Input) - Positive power for the digital section.
DGND8Digital Ground (Input) - Ground reference for the digital section.
RST13Reset
VLC14Control Port Power (Input) - Positive power for Control Port I/O.
FILT+15
REF_GND16Reference Ground (Input) - Ground reference for the internal sampling circuits.
VREF17Vol tage Reference (Input) - Positive voltage reference for the internal sampling circuits.
BMUTEC
AMUTEC
AOUTB+
AOUTB-
AGND21Analog Ground (Input) - Ground reference for the analog section.
VA22Analog Power (Input) - Positive power for the analog section.
AOUTA+
AOUTA-
VQ26Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
VLS27Serial Audio Interface Power (Input) - Positive power for serial audio interface I/O.
Stand-Alone Mode Definitions
M3
M2
M1
M0
Control Port Mode Definitions
AD1/CDIN9
SCL/CCLK10Serial Control Port Clock (Input) - Serial clock for the serial Control Port.
SDA/CDOUT11
AD0/CS
28
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
1
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on
the serial audio data line.
(Input) - The device enters system reset when enabled.
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Mute Control (Output) - The Mute Control pin is active during power-up initialization, mut-
18
ing, power-down or if the master clock to left/right clock frequency ratio is incorrect. During
25
reset, these outputs are set to a high impedance.
2019Differential Right Channel Analog Output (Output) - The full-scale differential analog
output level is specified in the Analog Characteristics specification table.
2324Differential Left Channel Analog Output (Output) - The full-scale differential analog out-
put level is specified in the Analog Characteristics specification table.
9
10
Mode Selection (Input) - Determines the operational mode of the device.
11
12
Address Bit 1 (I²C) / Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C
mode; CDIN is the input data line for the Control Port interface in SPI mode.
Serial Control Data (I²C) / Control Data Output (SPI) (Input/Output) - SDA is a data I/O
line in I²C mode. CDOUT is the output data line for the Control Port interface in SPI mode.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin
12
in I²C mode; CS
is the chip select signal for SPI format.
DS568F17
CS4398
2. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics are derived from measurements taken at T
=25°C, VA = 5.0 V, VD = 3.3 V.)
A
SPECIFIED OPERATING CONDITIONS
(AGND = 0 V; all voltages with respect to ground.)
ParametersSymbol Min TypMaxUnits
DC Power SupplyAnalog power
Voltage reference
Digital power
Serial audio interface power
Control port interface power
Specified Temperature Range-CZ & -CZZT
VREF
VLS
VLC
VA
VD
4.75
4.75
3.1
1.7
1.7
A
-10-70°C
5.0
5.0
3.3
3.3
3.3
5.25
5.25
5.25
5.25
5.25
V
V
V
V
V
ABSOLUTE MAXIMUM RATINGS
(AGND = 0 V; all voltages with respect to ground.)
ParametersSymbolMinMaxUnits
DC Power SupplyAnalog power
Voltage reference
Digital power
Serial audio interface power
Control port interface power
Input Current any pin except suppliesI
Digital Input VoltageSerial audio interface
Control port interface
Ambient Operating Temperature (power applied)T
Storage TemperatureT
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
VA
VREF
VD
VLS
VLC
in
V
IN-LS
V
IN-LC
A
stg
-0.3
-0.3
-0.3
-0.3
-0.3
-±10mA
-0.3
-0.3
-55125°C
-65150°C
6.0
6.0
6.0
6.0
6.0
VLS+ 0.4
VLC+ 0.4
V
V
V
V
V
V
V
8DS568F1
CS4398
ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement
bandwidth is 10 Hz to 20 kHz; test load R
ParameterSymbolMinTypMaxUnit
Dynamic Performance - All PCM modes and DSD Processor mode
Dynamic Range (Note 1) 24-bit A-Weighted
Total Harmonic Distortion + Noise (Note 1)
Idle Channel Noise / Signal-to-noise ratio-120-dB
Dynamic Performance - Direct DSD
Dynamic Range (Note 3) A-Weighted
Total Harmonic Distortion + Noise (Note 3)
Dynamic Performance for All Modes
Interchannel Isolation(1 kHz)-110-dB
DC Accuracy
Interchannel Gain MismatchICGM-0.1-dB
Gain Drift-100-ppm/°C
Analog Output Characteristics and Specifications
Full Scale Differential PCM, DSD processor
Output VoltageDirect DSD mode
Output ImpedanceZ
Minimum AC-Load ResistanceR
Maximum Load CapacitanceC
= 1 kΩ, CL = 10 pF.)
L
unweighted
16-bit A-Weighted
(Note 2) unweighted
24-bit 0 dB
-20 dB
-60 dB
16-bit 0 dB
(Note 2) -20 dB
-60 dB
unweighted
0 dB
-20 dB
-60 dB
THD+N
THD+N
OUT
L
L
114
111
-
-
-
-
-
-
-
-
111
108
-
-
-
132%•V
94%•V
A
A
120
117
97
94
-107
-97
-57
-94
-74
-34
117
114
-104
-94
-54
134%•V
96%•V
A
A
-
-
-
-
-100
-
-
-
-
-
-
-
-98
-
-
136%•V
98%•V
A
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
A
Vpp
-118-Ω
-1-kΩ
-100-pF
Notes:
1.One-half LSB of triangular PDF dither is added to data.
2. Performance limited by 16-bit quantization noise.
3. DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index.
DS568F19
CS4398
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.)
(See note 9.)
Parameter
Combined Digital and On-Chip Analog Filter Response - Single-Speed Mode - 48 kHz (Note 5)
Passband (Note 6)to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
StopBand0.547--Fs
StopBand Attenuation(Note 7)102--dB
Group Delay -9.4/Fs-s
De-emphasis Error (Note 8)Fs = 32 kHz
(Relative to 1 kHz)Fs = 44.1 kHz
Combined Digital and On-Chip Analog Filter Response - Double-Speed Mode - 96 kHz (Note 5)
Passband (Note 6)to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-0.01dB
StopBand.583--Fs
StopBand Attenuation(Note 7)80--dB
Group Delay-4.6/Fs-s
Combined Digital and On-Chip Analog Filter Response - Quad-Speed Mode - 192 kHz (Note 5)
Passband (Note 6) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-0.01dB
StopBand.635--Fs
StopBand Attenuation(Note 7)90--dB
Group Delay-4.7/Fs-s
4. Slow Roll-off interpolation filter is only available in Control Port mode.
5. Filter response is guaranteed by design.
6. Response is clock-dependent and will scale with Fs.
7. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
8. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone mode.
9. Amplitude vs. Frequency plots of this data are available in the “Appendix” on page 41.
to -3 dB corner
Fs = 48 kHz
to -3 dB corner
to -3 dB corner
0
0
-
-
-
0
0
0
0
Fast Roll-Off
-
-
-
-
-
-
-
-
-
.454
.499
±0.23
±0.14
±0.09
.430
.499
.105
.490
UnitMin TypMax
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
10DS568F1
CS4398
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(Continued)
Slow Roll-Off (Note 4)
Parameter
Single-Speed Mode - 48 kHz (Note 5)
Passband (Note 6)to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
StopBand.583--Fs
StopBand Attenuation(Note 7)64--dB
Group Delay -6.65/Fs-s
De-emphasis Error (Note 8)Fs = 32 kHz
(Relative to 1 kHz)Fs = 44.1 kHz
Fs = 48 kHz
Double-Speed Mode - 96 kHz (Note 5)
Passband (Note 6)to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-0.01dB
StopBand.792--Fs
StopBand Attenuation(Note 7)70--dB
Group Delay-3.9/Fs-s
Quad-Speed Mode - 192 kHz (Note 5)
Passband (Note 6) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-0.01dB
StopBand.868--Fs
StopBand Attenuation(Note 7)75--dB
Group Delay-4.2/Fs-s
0
0
-
-
-
0
0
0
0
-
-
-
-
-
-
-
-
-
0.417
0.499
±0.23
±0.14
±0.09
.296
.499
.104
.481
UnitMinTypMax
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
DSD COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE
ParameterMinTypMaxUnit
DSD Processor Mode (Note 5)
Passband (Note 6)to -3 dB corner0-50kHz
Frequency Response 10 Hz to 20 kHz-0.05-0.05dB
Roll-off27--dB/Oct
Direct DSD Mode (Note 5)
Passband (Note 6) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.1-0dB
Figure 3. Format 0 - Left-Justified up to 24-bit Data
LRCK
SCLK
SDATA+3 +2 +1
MSB
-1 -2 -3 -4 -5
Left Channel
+5 +4
Figure 4. Format 1 - I²S up to 24-bit Data
LRCK
SCLK
Left Channel
LSB
LSB
MSB
-1 -2 -3 -4
MSB
-1 -2 -3 -4
Right Channel
+3 +2 +1
+5 +4
Right Channel
+3 +2 +1
+5 +4
Right Channel
LSB
LSB
SDATA
LSB
+6
LSB+5
MSB -1 -2 -3 -4 -5
32 clocks
-6
+4 +3 +2
+5
+1
-1 -2 -3 -4
MSB
-5
-6
+6
Figure 5. Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data.
Format 4, Right-Justified 20-Bit Data. (Available in Control Port Mode only)
Format 5, Right-Justified 18-Bit Data. (Available in Control Port Mode only)
(128x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup timet
DSD_SCLK rising to DSD_A or DSD_B hold timet
DSD clock to data transition (Phase Modulation mode)t
DSD_SCLK
=20pF)
L
t
sdlrstsdh
sclkl
sclkh
sdlrs
sdh
dpm
t
sclkl
160--ns
160--ns
1.024
2.048
-
-
3.2
6.4
20--ns
20--ns
-20-20ns
t
sclkh
MHz
MHz
DSD_A,DSD_B
Figure 6. Direct Stream Digital - Serial Audio Input Timing
t
dpm
DSD_SCLK
(128Fs)
DSD_SCLK
(64Fs)
DSD_A, DSD_B
Figure 7. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode
t
dpm
14DS568F1
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL=20pF)
ParameterSymbolMinMaxUnit
SCL Clock Frequencyf
RST
Rising Edge to Startt
Bus Free-Time Between Transmissionst
Start Condition Hold Time (prior to first clock pulse)t
Clock Low Timet
Clock High Timet
Setup Time for Repeated Start Conditiont
SDA Hold Time from SCL Falling(Note 10)t
SDA Setup Time to SCL Risingt
Rise Time of SCL and SDAt
Fall Time SCL and SDAt
Setup Time for Stop Conditiont
Acknowledge Delay from SCL Fallingt
scl
irs
buf
hdst
low
high
sust
hdd
sud
, t
rc
, t
fc
susp
ack
rd
fd
-100kHz
500-ns
4.7-µs
4.0-µs
4.7-µs
4.0-µs
4.7-µs
0-µs
250-ns
-1µs
-300ns
4.7-µs
3001000ns
CS4398
10. Data must be held for sufficient time to bridge the transition time, t
RST
t
irs
StopS ta rt
SDA
SCL
t
buf
t
hdst
t
low
t
high
t
hdd
t
sud
t
ack
Figure 8. Control Port Timing - I²C Format
, of SCL.
fc
Repeated
Start
t
sust
t
hdst
t
rd
t
fc
t
rc
Stop
t
fd
t
susp
DS568F115
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL=20pF)
ParameterSymbolMinMaxUnit
CCLK Clock Frequencyf
RST
Rising Edge to CS Fallingt
CCLK Edge to CS
CS
High Time Between Transmissionst
CS
Falling to CCLK Edget
Falling(Note 11)t
CCLK Low Timet
CCLK High Timet
CDIN to CCLK Rising Setup Timet
CCLK Rising to DATA Hold Time(Note 12)t
Rise Time of CCLK and CDIN(Note 13)t
Fall Time of CCLK and CDIN(Note 13)t
Transition time from CCLK to CDOUT valid(Note 14)t
Time from CS
rising to CDOUT high-Z(Note 15)t
sclk
srs
spi
csh
css
scl
sch
dsu
dh
r2
f2
scdov
cscdo
-6MHz
500-ns
500-ns
1.0-µs
20-ns
66-ns
66-ns
40-ns
15-ns
-100ns
-100ns
-40ns
-20ns
CS4398
11. t
only needed before first falling edge of CS after RST rising edge. t
spi
spi
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For F
< 1 MHz.
SCK
14. CDOUT should not be sampled during this time period.
15. This time is by design and not tested.
RST
CS
CCLK
CDIN
CDOUT
t
srs
t
t
css
spi
t
r2
t
t
scl
sch
t
f2
t
t
dsu
dh
t
csh
= 0 at all other times.
Hi-Impedance
t
scdov
t
scdov
t
cscdo
Figure 9. Control Port Timing - SPI Format (Read/Write)
16DS568F1
DC ELECTRICAL CHARACTERISTICS
ParametersSymbolMinTypMaxUnits
Normal Operation
Power Supply CurrentVA= 5 V (Note 17)
(Note 16)
V
= 5 V
ref
= 5 V
V
D
= 3.3 V
V
D
Interface current (Note 18)
CS4398
I
A
I
ref
I
D
I
D
I
LC
I
LS
-
-
-
-
-
-
25
1.5
25
18
2
80
28
2
38
27
-
-
mA
mA
mA
mA
µA
µA
Power DissipationVA = 5 V, VD = 5 V
VA = 5 V, VD = 3.3 V
Power-Down Mode
(Note 19)
Power Supply CurrentI
Power DissipationVA = 5 V, VD = 5 V
VA = 5 V, VD = 3.3 V
pd
-
-
258
192
340
240
mW
mW
-200- µA
-
-
1
1
-
-
mW
mW
All Modes of Operation
Power Supply Rejection Ratio (Note 20) (1 kHz)
(60 Hz)
Common Mode VoltageV
Max Current draw from VQI
FILT+ Nominal Voltage-0.93•V
16. Normal operation is defined as RST pin = High with a 997 Hz, 0 dBFS input sampled at the highest Fs for
each speed mode, and open outputs, unless otherwise specified.
17. I
measured with no loading on the AMUTEC and BMUTEC pins.
A
18. I
19. Power-Down mode is defined as RST
measured with no external loading on pin 11 (SDA).
LC
pin = Low with all clock and data lines held static.
20. Valid with the recommended capacitor values on FILT+ and V
as shown in the “Typical Connection Dia-
Q
gram” on page 19.
21. This current is sourced/sinked directly from the VA supply.
High-Level Output Voltage (IOH= -1.2 mA)Control I/OV
Low-Level Output Voltage (IOL= 1.2 mA) Control I/OV
V
IH
V
IH
V
IL
V
IL
OH
OL
MUTEC auto detect input high voltage70%VA
MUTEC auto detect input low voltage30%VA
--±10µA
70%
70%
-
-
-
-
-
-
-
-
30%
30%
V
V
V
V
80%--V
--20%V
LS
LC
LS
LC
LC
LC
18DS568F1
3. TYPICAL CONNECTION DIAGRAM
CS4398
+1.8V
to
+5V
+3.3V to
+5V
System
0.1 uF
Clock
10 uF
PCM
Digital
Audio
Source
DSD
Audio
Source
0.1 uF
VDVA
MCLK
SCLK
LRCK
SDIN
VLS
DSD_SCLK
DSD_A
DSD_B
AMUTEC
AOUTA -
AOUTA+
AOUTB+
AOUTB -
BMUTEC
0.1 uF
10 uF
Left Channel
Analog
Conditioning
and Mute
Right Channel
Analog
Conditioning
and Mute
+5V
+1.8V
to
+5V
0.1 uF
Controler
µ
or
stand alone
pull-ups/
downs
CS4398
VLC
M0 (AD0/CS)
M1 (SDA/CDOUT)
M2 (SCL/CCLK)
REF_GND
M3 (AD1/CDIN)
RSTVREF
DGNDAGND
Figure 10. Typical Connection Diagram
VQ
FILT+
0.1 uF
0.1 uF
3.3 uF
100 uF
33 uF
VA
DS568F119
4. APPLICATIONS
4.1Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4398 requires careful attention to power supply and grounding
arrangements to optimize performance. The Typical Connection Diagram shows the recommended power
arrangement with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same
supply, but the recommended decoupling capacitors should still be placed on each supply pin. The AGND
and DGND pins should be tied together with solid ground plane fill underneath the converter extending out
to the GND side of the decoupling caps for VA, VD, VREF, and FILT+. This recommended layout can be
seen in the CDB4398 evaluation board and datasheet.
4.2Analog Output and Filtering
The Cirrus Logic application note “Design Notes for a 2-Pole Filter with Differential Input” (AN48) discusses
the second-order Butterworth filter and differential to single-ended converter topology that was implemented
on the CS4398 evaluation board, CDB4398, as seen in Figure 11.
The CS4398 does not include phase or amplitude compensation for an external filter. Therefore, the DAC
system phase and amplitude response is dependent on the external analog circuitry.
CS4398
Figure 11. Recommended Output Filter
4.3The MUTEC Outputs
The AMUTEC and BMUTEC pins have an auto-polarity detect feature. The MUTEC output pins are high
impedance at the time of reset. The external mute circuitry needs to be self-biased into an active state in
order to be muted during reset. Upon release of reset, the CS4398 detects the status of the MUTEC pins
(high or low) and then selects that state as the polarity to drive when the mutes become active. The externalbias voltage level that the MUTEC pins see at the time of release of reset must meet the “MUTEC auto detect input high/low voltage” specifications as outlined in the Digital Characteristics in Section 2.
Figure 12 shows a single example of both an active-high and an active-low mute drive circuit. In these designs, the pull-up and pull-down resistors have been specifically chosen to meet the input high/low threshold
when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 kΩ.
20DS568F1
CS4398
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Figure 12. Recommended Mute Circuitry
4.4Oversampling Modes
The CS4398 operates in one of three oversampling modes based on the input sample rate. Single-Speed
mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode
supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
4.5Master and Serial Clock Ratios
The required MCLK-to-LRCK ratio and suggested SCLK-to-LRCK ratio are outlined in Table 1. MCLK can
be at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing
relationships outlined in Section 2. Some common MCLK frequencies have been outlined in Table 2.
* This MCLK ratio limits the audio word length to 16 bits; see Table 1 on page 21
Table 2. Common Clock Frequencies
4.6Stand-alone Mode Settings
In Stand-Alone mode (also referred to as “Hardware mode”) the device is configured using the M0 through
M3 pins. These pins must be connected to either the VLC supply or ground. The Interface format is set by
pins M0 and M1. The sample rate range/oversampling mode (Single/Double/Quad-Speed mode) and deemphasis are set by pins M2 and M3. The settings can be found in Tables 3 and 4.
MCLK (MHz)
MCLKDIV2MCLKDIV3
768x1024x1152x
24.576032.768036.8640
33.868845.1584-
36.864049.1520-
512x-
32.7680-
45.1584-
49.1520-
256x-
45.1584-
49.1520-
M1M0DescriptionFormatFigure
00
01
10
11
Table 3. Digital Interface Format, Stand-Alone Mode Options
M3M2Description
00
01
10
11
The following features are always enabled in Stand-Alone mode: Auto-mute on zero data, Auto MUTEC polarity detect, ramp volume from mute to 0dB by 1/8th dB steps every LRCK (soft ramp) after reset or clock
mode change, and the fast roll-off interpolation filter is used.
The following features are not available in Stand-Alone mode: DSD mode, Right-Justified 20- and 18-bit serial audio interfaces, MCLK divide-by-2 and MCLK divide-by-3 (allows 1024 and 1152 clock ratios), slow rolloff interpolation filter, volume control, ATAPI mixing, 48 kHz and 32 kHz de-emphasis, and all other features
enabled by registers that are not mentioned above.
Single-Speed without De-Emphasis (32 to 50 kHz sample rates)
Single-Speed with 44.1 kHz De-Emphasis; see Figure 17 on page 30
Double-Speed (50 to 100 kHz sample rates)
Quad-Speed (100 to 200 kHz sample rates)
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit Data
Right-Justified, 24-bit Data
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control
Port is reset to its default settings.
CS4398
2. Bring RST
up sequence following approximately 2
high. The device will remain in a low power state and will initiate the Stand-Alone power-
18
MCLK cycles.
4.7Control Port Mode
4.7.1Recommended Power-up Sequence (Control Port Mode)
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control
Port is reset to its default settings.
2. Bring RST
quence (approximately 2
and initializes the Control Port to its default settings. The desired register settings can be loaded while
keeping the PDN bit (Reg. 8h) set to 1.
3. Clear the PDN bit to initiate the power-up sequence.
If the CPEN bit is not written within the allotted time, the device will start-up in stand-alone mode and begin
converting data according to the current state of the M0 to M3 pins. Since these pins are also the control
port pins an undesired mode may be entered. For this reason, if the CPEN bit is not set before the allotted
time elapses, the SDIN line must be kept at static 0 (not dithered) until the device is properly configured.
This will keep the device from converting data improperly.
high. Set the CPEN bit (Reg. 8h) prior to the completion of the Stand-Alone power-up se-
18
MCLK cycles). Setting this bit halts the Stand-Alone power-up sequence
4.7.2Sample Rate Range/Oversampling Mode (Control Port Mode)
Sample rate mode selection is determined by the FM bits (Reg. 02h).
4.7.3Serial Audio Interface Formats (Control Port Mode)
The desired serial audio interface format is selected using the DIF2:0 bits (Reg. 02h).
4.7.4MUTEC Pins (Control Port Mode)
The auto-mute polarity feature (mentioned in Section 4.3) is defeatable. The MUTEP1:0 bits in register
04h give the option to override the mute polarity which was auto detected at startup (see the Register Description section for more details).
4.7.5Interpolation Filter (Control Port Mode)
To accommodate the increasingly complex requirements of digital audio systems, the CS4398 incorporates selectable interpolation filters. A fast and a slow roll-off filter are available in each of Single-, Double, and Quad-Speed modes. These filters have been designed to accommodate a variety of musical tastes
and styles. The FILT_SEL bit (Reg. 07h) is used to select which filter is used (see the Register Description
section for more details).
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 20 to 43
in the “Appendix” on page 41.
DS568F123
4.7.6Direct Stream Digital (DSD) Mode (Control Port Mode)
In Control Port mode, the FM bits (Reg. 02h) are used to configure the device for DSD mode. The DIF
bits (Reg 02h) then control the expected DSD rate and MCLK ratio.
The DSD_SRC bit (Reg. 02h) selects the input pins for DSD clocks and data. During DSD operation, the
PCM-related pins should either be tied low or remain active with clocks. When the DSD related pins are
not being used, they should either be tied low or remain active with clocks.
The DIR_DSD bit (Reg 07h) selects between two proprietary methods for DSD-to-analog conversion. The
first method uses a decimation-free DSD processing technique that allows for features such as matched
PCM level output, DSD volume control, and 50 kHz on-chip filter. The second method sends the DSD data
directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features).
The DSD_PM_EN bit (Reg. 09h) selects Phase Modulation (data plus data inverted) as the style of data
input. In this mode, the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see Figure 13). Use of phase modulation mode may not directly effect the performance
of the CS4398, but may lower the sensitivity to board-level routing of the DSD data signals.
The CS4398 can detect errors in the DSD data that do not comply to the SACD specification. The
STATIC_DSD and INVALID_DSD bits (Reg. 09h) allow the CS4398 to alter the incoming invalid DSD data. Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the
MUTEC pins would set according to the DAMUTE bit (Reg. 04h)).
More information for any of these register bits can be found in the Register Description section.
CS4398
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time;
however, performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required,
the digital volume control should be set to -3.0 dB. This same volume control register affects PCM output
levels. There is no need to change the volume control setting between PCM and DSD in order to have the
0 dB output levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).
DSD Normal Mode
DSD_SCLK
BCKA
(64Fs)
DSD_A,
DSD_B
D1
D1
D1D0D2
D2D0
DSD Phase
Modulation Mode
BCKA
(128Fs)
BCKD
(64Fs)
DSD_A,
DSD_B
DSD_SCLK
DSD_SCLK
Figure 13. DSD Phase Modulation Mode Diagram
24DS568F1
CS4398
5. CONTROL PORT INTERFACE
The Control Port is used to load all the internal settings. The operation of the Control Port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the Control Port pins should
remain static if no operation is required.
5.1Memory Address Pointer (MAP)
5.1.1Memory Address Pointer (MAP) Register Detail
7654 3210
INCRReservedReservedReservedMAP3MAP2MAP1MAP0
00000000
5.1.2INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled, the MAP will stay constant for successive writes
1 - Enabled, the MAP will auto increment after each byte is written, allowing block reads or writes of successive registers
5.1.3MAP3-0 (Memory Address Pointer)
Default = ‘0000’
5.2Enabling the Control Port
On the CS4398, the Control Port pins are shared with Stand-Alone configuration pins. To enable the Control
Port, the user must set the CPEN bit. This is done by performing an I²C or SPI write. Once the Control Port
is enabled, these pins are dedicated to Control Port functionality.
To prevent audible artifacts, the CPEN bit (see Section 7) should be set prior to the completion of the StandAlone power-up sequence, approximately 2
sequence and initializes the Control Port to its default settings. Note, the CPEN bit can be set any time after
RST
goes high; however, setting this bit after the stand-alone power-up sequence has completed can cause
audible artifacts.
5.3Format Selection
The Control Port has two formats: SPI and I²C, with the CS4398 operating as a slave device.
If I²C operation is desired, AD0/CS
transition on AD0/CS
after power-up, SPI format will automatically be selected.
5.4I²C Format
In I²C Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL,
with a clock-to-data relationship as shown in Figure 14. The receiving device should send an acknowledge
(ACK) after each byte received. There is no CS
should be tied to VLC or GND as required. The upper five bits of the 7-bit address field must be 10011.
18
MCLK cycles. Setting this bit halts the stand-alone power-up
should be tied to VLC or GND. If the CS4398 ever detects a high-to-low
pin. Pins AD0 and AD1 form the partial chip address and
DS568F125
5.4.1Writing in I²C Format
To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the
chip address. The eighth bit of the address byte is the R/W
ory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by
the data to be written. To write multiple registers, continue providing a clock and data, waiting for the
CS4398 to acknowledge between each byte. To end the transaction, send a STOP condition.
5.4.2Reading in I²C Format
To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the
chip address. The eighth bit of the address byte is the R/W
ister pointed to by the MAP will be output after the chip address. To read multiple registers, continue providing a clock and issue an ACK after each byte. To end the transaction, send a STOP condition.
CS4398
bit (low for a write). The next byte is the Mem-
bit (high for a read). The contents of the reg-
Note 1
SDA
SCL
Start
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
5.5SPI Format
In SPI format, CS is the CS4398 chip select signal; CCLK is the Control Port bit clock; CDIN is the input
data line from the microcontroller; CDOUT is the output data line and the chip address is 1001100. CS
CCLK,and CDIN are all inputs, and data is clocked in on the rising edge of CCLK. CDOUT is an output and
is high-impedance when not actively outputting data.
5.5.1Writing in SPI
Figure 15 shows the operation of the Control Port in SPI format. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write indicator (R/W
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into register designated by the MAP. To write multiple registers, keep CS
viding clocks on CCLK. End the read transaction by setting CS
), which must be low to write. The next eight bits form the Memory Address Pointer (MAP),
10011
AD1
Figure 14. Control Port Timing, I²C Format
AD0
R/W
ACK
DATA
1-8
high.
ACK
DATA
1-8
ACK
Stop
,
low and continue pro-
26DS568F1
CS4398
CS
CCLK
CDIN
5.5.2Reading in SPI
Figure 16 shows the operation of the Control Port in SPI format. To read to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write control
(R/W
), which must be high to read. The CDOUT line will then output the data from the register designated
by the MAP. To read multiple registers, keep CS
read transaction by setting CS
high.
CS
CCLK
CHIP
ADDRESS
1001100
R/W
MAP
MSB
byte 1
MAP = Memory Address Pointer
Figure 15. Control Port Timing, SPI Format (Write)
low and continue providing clocks on CCLK. End the
high. The CDOUT line will go to a high-impedance state once CS goes
** All register access is R/W unless specified otherwise**
7.1Chip ID - Register 01h
76543210
PART4PART3PART2PART1PART0REV2REV1REV0
01110- - -
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID, which is 01110b (14h), and the remaining Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
7.2Mode Control 1 - Register 02h
76543210
DSD_SRCDIF2DIF1DIF0DEM1DEM0FM1FM0
00000000
7.2.1 DSD Input Source Select (DSD_SRC) BIT 7
Function:
When set to 0 (default), the dedicated DSD pins will be the active DSD inputs.
When set to 1, the source for DSD inputs will be as follows:
DSDA input on SDATA pin
DSDB input on LRCK pin
DSD_SCLK input on SCLK pin
The dedicated DSD pins must be tied low while not in use.
7.2.2Digital Interface Format (DIF2:0) BITs 6-4
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format, and the options are detailed in Figures 3 through 5.
DIF2DIF1DIF0DescriptionFormatFigure
000
001
010
011
100
101
110
111
Left-Justified, up to 24-bit data0 (Default)
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Reserved
Reserved
Table 5. Digital Interface Formats - PCM Mode
3
14
25
35
45
55
DS568F129
CS4398
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master Clock to DSD data rate is defined by the Digital Interface Format pins.
DIF2DIF1DIF0Description
00064x oversampled DSD data with a 4x MCLK to DSD data rate (Default)
00164x oversampled DSD data with a 6x MCLK to DSD data rate
01064x oversampled DSD data with a 8x MCLK to DSD data rate
01164x oversampled DSD data with a 12x MCLK to DSD data rate
100128x oversampled DSD data with a 2x MCLK to DSD data rate
101128x oversampled DSD data with a 3x MCLK to DSD data rate
110128x oversampled DSD data with a 4x MCLK to DSD data rate
111128x oversampled DSD data with a 6x MCLK to DSD data rate
7.3.1Channel B Volume = Channel A Volume (VOLB=A) Bit 7
Function:
When set to 0 (default), the AOUTA and AOUTB volume levels are independently controlled by the A and
the B Channel Volume Control Bytes.
When set to 1, the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and
Volume Control Bytes, and the B Channel Bytes are ignored.
7.3.2Invert Signal Polarity (Invert_A) Bit 6
Function:
When set to 1, this bit inverts the signal polarity of channel A.
When set to 0 (default), this function is disabled.
7.3.3Invert Signal Polarity (Invert_B) Bit 5
Function:
When set to 1, this bit inverts the signal polarity of channel B.
When set to 0 (default), this function is disabled.
CS4398
7.3.4ATAPI Channel Mixing and Muting (ATAPI4:0) Bits 4-0
Default = 01001 - AOUTA=aL, AOUTB=bR (Stereo)
Function:
The CS4398 implements the channel-mixing functions of the ATAPI CD-ROM specification. Refer to Table and Figure 18 for additional information.
When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be
retained, and the Mute Control pin will go active during the mute period.
When set to 0, this function is disabled.
7.4.2DSD Auto-mute (DAMUTE) Bit 6
Function:
When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 256 repeated 8-bit DSD mute patterns (as defined in the SACD specification).
A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained, and
the Mute Control pin will go active during the mute period.
When set to 0, this function is disabled.
7.4.3AMUTEC = BMUTEC (MUTEC A=B) Bit 5
Function:
When set to 0 (default) the AMUTEC and BMUTEC pins operate independently.
When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an
AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only
when the requirements for both AMUTEC and BMUTEC are valid.
7.4.4A Channel Mute (MUTE_A) Bit 4
B Channel Mute (MUTE_B) Bit 3
Function:
When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will
be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross
bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any
ramping due to the soft and zero cross function.
When set to 0 (default), this function is disabled.
DS568F133
7.4.5MUTE Polarity and DETECT (MUTEP1:0) Bits 1-0
Default = 00
00 - Auto polarity detect, selected from AMUTEC pin
01 - Reserved
10 - Active low mute polarity
11 - Active high mute polarity
Function:
Auto mute polarity detect (00)
See section 4.3 on page 20 for description.
Active low mute polarity (10)
CS4398
When RST
released and after this bit is set, the MUTEC output pins will be active low polarity.
Active high mute polarity (11)
At reset time, the outputs are high-impedance and will need to be biased active. Once reset has been
released and after this bit is set, the MUTEC output pins will be active high polarity.
is low, the outputs are high-impedance and will need to be biased active. Once reset has been
7.5Channel A Volume Control - Register 05h
7.6Channel B Volume Control - Register 06h
76543210
VOL7VOL6VOL5VOL4VOL3VOL2VOL1VOL0
00000000
7.6.1Digital Volume Control (VOL7:0) Bits 7-0
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments
from 0 to -127.5 dB. Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that
the values in the volume setting column in Table 7 are approximate. The actual attenuation is determined
by taking the decimal value of the volume register and multiplying by 6.02/12.
7.7.1Soft Ramp AND Zero Cross CONTROL (SZC1:0) Bits 7-6
Default = 10
SZC1 SZC0PCM DescriptionDSD Description
00Immediate ChangeImmediate Change
01Zero Cross
10Soft RampSoft Ramp
11Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level-change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp PCM
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp DSD
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 512 DSD_SCLK periods
(1024 periods if 128x DSD_SCLK is used).
Soft Ramp and Zero Cross
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
DS568F135
CS4398
7.7.2Soft Volume Ramp-up after Error (RMP_UP) Bit 5
Function:
An un-mute will be performed after executing an LRCK/MCLK ratio change or error, and after changing
the Functional Mode.
When set to 1 (default), this un-mute is effected, similar to attenuation changes, by the Soft and Zero
Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
7.7.3Soft Ramp-down before Filter Mode Change (RMP_DN) Bit 4
Function:
If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to
change its filter values. This bit selects how the data is effected prior to and after the change of the filter
values.
When set to 1 (default), a mute will be performed prior to executing a filter mode change and an un-mute
will be performed after executing the filter mode change. This mute and un-mute are effected, similar to
attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
7.7.4Interpolation Filter Select (FILT_SEL) Bit 2
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the Analog characteristics table, and response plots can
be found in figures 20 to 43 found in the “Appendix” on page 41.
7.7.5Direct DSD Conversion (DIR_DSD) Bit 0
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control functions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode, the full-scale DSD and PCM levels will not be matched (see Section 2), the dynamic range
performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available
(see Section 2 for filter specifications).
When set to 1 (default), the entire device enters a low-power state, and the contents of the control registers is retained. The power-down bit defaults to ‘1’ on power-up and must be disabled before normal operation in Control Port mode can occur. This bit is ignored if CPEN is not set.
7.8.2Control Port Enable (CPEN) Bit 6
Function:
This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode
can be accessed by setting this bit to 1. This allows operation of the device to be controlled by the registers, and the pin definitions will conform to Control Port Mode.
7.8.3Freeze Controls (Freeze) Bit 5
Function:
When set to 1, this function allows modifications to be made to the registers without the changes taking
effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect
simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
When set to 0 (default), register changes take effect immediately.
7.8.4Master Clock Divide-by-2 ENABLE (MCLKDIV2) Bit 4
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
7.8.5Master Clock Divide-by-3 ENABLE (MCLKDIV3) Bit 3
Function:
When set to 1, the MCLKDIV bit enables a circuit that divides the externally applied MCLK signal by 3
prior to all other internal circuitry.
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
7.9.2Invalid DSD Detect (Invalid_DSD) Bit 2
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if detected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
7.9.3DSD Phase Modulation Mode Select (DSD_PM_mode) Bit 1
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation
mode. (See Figure 13 on page 24)
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode.
7.9.4DSD Phase Modulation Mode Enable (DSD_PM_EN) Bit 0
Function:
When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
38DS568F1
CS4398
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
THD+N is the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS
signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique
ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output
with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
9. REFERENCES
1. CDB4398 Evaluation Board Datasheet
2. “Design Notes for a 2-Pole Filter with Differential Input”. Cirrus Logic Application Note AN48
3. The I²C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com “
Figure 19. 28L TSSOP (4.4 mm Body) Package Drawing
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm
total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS AND SPECIFICATIONS
ParametersSymbolMinTypMaxUnits
Package Thermal Resistance (Note 4)28-TSSOPθ
JA
θ
JC
4. θJA is specified according to JEDEC specifications for multi-layer PCBs.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
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PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR
SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY
OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY
CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS
PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT
FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
46DS568F1
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