CS4397
24-Bit, Multi-Standard D/A Converter for Digital Audio
Features
24 Bit Conversion
Up to 192 kHz Sample Rates
120 dB Dynamic Range
-100 dB THD+N
Supports PCM, DSD and External
Interpolation filters
Advanced Dynamic-Element Matching
Low Clock Jitter Sensitivity
Digital De-emphasis for 32 kHz, 44.1 kHz and
48 kHz
External Reference Input
I
SCLK
LRCK
SDATA
SERIAL INTERFACE
AND FORMAT SELECT
Description
The CS4397 is a complete high performance 24-bit
48/96/192 kHz stereo digital-to-analog conversion system. The device includes a digital interpolation filter
followed by a oversampled multi-bit delta-sigma modulator which drives dynamic-element-matching (DEM)
selection logic. The output from the DEM block controls
the input to a multi-element switched capacitor DAC/lowpass filter, with fully-differential outputs. This multi-bit architecture features significantly lower out-of-band noise
and jitter sensitivity than traditional 1-bit designs, and the
advanced DEM guarantees low noise and distortion at
all signal levels.
ORDERING INFORMATION
CS4397-KS -10° to 70° C 28-pin Plastic SOIC
CS4397-KSZ -10° to 70° C 28-pin Plastic SOIC Lead free
CDB4397 Evaluation Board
SOFT MUTE
DE-EMPHASIS
FILTER
MCLK
DIVIDER
M4
(AD0/CS)
CLOCK
http://www.cirrus.com
INTERPOLATION
INTERPOLATION
HARDWARE MODE CONTROL
M3 M2
(AD1/CDIN) (SCL/CCLK)
FILTER
FILTER
(CONTROL PORT)
M1
(SDA/CDOUT)
MULTI-BIT
∆Σ
MODULATOR
MULTI-BIT
∆Σ
MODULATOR
M0
Copyright © Cirrus Logic, Inc. 2004
RESET MUTEC MUTE
(All Rights Reserved)
DYNAMIC
ELEMENT
MATCHING
DYNAMIC
ELEMENT
MATCHING
LOGIC
LOGIC
CAPACITOR-DAC
CAPACITOR-DAC
VOLTAGE REFERENCE
VREF CMOUTFILT-
FILT+
SWITCHED
AND FILTER
SWITCHED
AND FILTER
AOUTL+
AOUTL-
AOUTR+
AOUTR-
SEP ‘04
DS333F1
1
TABLE OF CONTENTS
1.0 CHARACTERISTICS/SPECIFICATIONS ..................................................................... 4
ANALOG CHARACTERISTICS................................................................................... 4
Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz ...................... 4
Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz .................... 4
Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz ..................... 4
ANALOG CHARACTERISTICS................................................................................... 5
Power Supplies .................................................................................................... 5
Analog Output ...................................................................................................... 5
Combined Digital and On-chip Analog Filter Response - Single Speed Mode .... 6
Combined Digital and On-chip Analog Filter Response - Double Speed Mode ... 6
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode ..... 6
ANALOG CHARACTERISTICS - DSD MODE ............................................................ 7
Dynamic Performance - DSD Mode ..................................................................... 7
Analog Output - DSD Mode ................................................................................. 7
Combined Digital and On-chip Analog Filter Response - DSD Mode .................. 7
ANALOG CHARACTERISTICS - 8X INTERPOLATOR MODE .................................. 8
Dynamic Performance Mode ................................................................................ 8
Analog Output ...................................................................................................... 8
Combined Digital and On-chip Analog Filter Response - 8x Interpolator Mode ... 8
DIGITAL CHARACTERISTICS.................................................................................... 9
ABSOLUTE MAXIMUM RATINGS.............................................................................. 9
RECOMMENDED OPERATING CONDITIONS.......................................................... 9
SWITCHING CHARACTERISTICS ........................................................................... 10
DSD - SWITCHING CHARACTERISTICS ................................................................ 11
8X INTERPOLATOR - SWITCHING CHARACTERISTICS....................................... 12
SWITCHING CHARACTERISTICS - CONTROL PORT ........................................... 13
2
I
C® Mode ......................................................................................................... 13
SPI Mode ........................................................................................................... 14
2.0 TYPICAL CONNECTION DIAGRAM .......................................................................... 15
3.0 REGISTER DESCRIPTION ........................................................................................ 16
3.1 Differential DC offset calibration ........................................................................ 16
3.2 Soft Mute ........................................................................................................... 16
3.3 Mode Select ....................................................................................................... 17
3.4 Power DowN ...................................................................................................... 17
4.0 PIN DESCRIPTION - PCM MODE .............................................................................. 18
5.0 PIN DESCRIPTION - DSD MODE .............................................................................. 23
6.0 PIN DESCRIPTION - 8X INTERPOLATOR MODE .................................................... 24
7.0 APPLICATIONS .......................................................................................................... 25
7.1 Recommended Power-up Sequence ................................................................. 25
8.0 CONTROL PORT INTERFACE .................................................................................. 26
8.1 SPI Mode ........................................................................................................... 26
2
8.2 I
C Mode ........................................................................................................... 26
8.2 Memory Address Pointer (MAP) ....................................................................... 26
9.0 PARAMETER DEFINITIONS ...................................................................................... 33
10.0 REFERENCES .......................................................................................................... 33
11.0 PACKAGE DIMENSIONS ......................................................................................... 34
CS4397
2 DS333F1
TABLE OF FIGURES
Figure 1. Serial Audio Input Timing ......................................................................... 10
Figure 2. Direct Stream Digital - Serial Audio Input Timing ..................................... 11
Figure 3. Serial Audio Input Timing ......................................................................... 12
Figure 4. I2C Control Port Timing ............................................................................ 13
Figure 5. SPI Control Port Timing ........................................................................... 14
Figure 6. Typical Connection Diagram - Hardware Mode (Control Port Mode) ....... 15
Figure 7. Control Port Timing, I
Figure 8. Control Port Timing, SPI mode ................................................................ 27
Figure 9. Single-speed Transition Band .................................................................. 29
Figure 10.Single-speed Stopband Rejection ............................................................ 29
Figure 11.Single-speed Transition Band .................................................................. 29
Figure 12.Single-speed Frequency Response ......................................................... 29
Figure 13.Double-speed Stopband .......................................................................... 29
Figure 14.Double-speed Transition Band ................................................................. 29
Figure 15.Double-speed Transition Band ................................................................. 29
Figure 16.Double-speed Frequency Response ........................................................ 29
Figure 17.Quad-speed Stopband Rejection ............................................................. 30
Figure 18.Quad-speed Transition Band ................................................................... 30
Figure 19.Quad-speed Transition Band ................................................................... 30
Figure 20.Quad-speed Frequency Response .......................................................... 30
Figure 21.8x Interpolator Stop Band ........................................................................ 30
Figure 22.8x Interpolator Transition Band ................................................................ 30
Figure 23.8x Interpolator Transition Band ................................................................ 30
Figure 24.8x Interpolator Frequency Response ....................................................... 30
Figure 25.DSD Frequency Response ...................................................................... 31
Figure 26.DSD Transition Band ............................................................................... 31
Figure 27.DSD Transition Band ............................................................................... 31
Figure 28.De-Emphasis Curve ................................................................................. 31
Figure 29.Format 0, Left Justified ............................................................................. 32
Figure 30.Format 1, I
Figure 31.Format 2, Right Justified, 16-Bit Data ...................................................... 32
Figure 32.Format 3, Right Justified, 24-Bit Data ...................................................... 32
Figure 33.Format 4, 8x Interpolator Mode ................................................................ 32
2
C Mode ................................................................. 27
2
S ........................................................................................... 32
CS4397
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
“The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information descr ibes products which are in development and subj ect to development changes . Cirrus Logic, Inc. has made best eff orts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or ot her rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publicati on may be copied, reproduced, stored i n a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photograp hic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, sto red in a retrieval syst em, or t ransmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of thi s publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or ser vice marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirr us.com.
DS333F1 3
1.0 CHARACTERISTICS/SPECIFICATIONS
CS4397
ANALOG CHARACTERISTICS (T
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz
to 20 kHz, unless otherwise specified. Test load R
Parameter Symbol Min Typ Max Unit
= 25 °C; Logic "1" = VD = 5 V; VA = 5V; Logic "0" = DGND;
A
= 1 kΩ, CL = 10 pF)
L
Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz
Dynamic Range (Note 1)
24-Bit unweighted
A-Weighted
16-Bit unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
(Note 2) -20 dB
-60 dB
THD+N
TBD
TBD
-
-
-
-
-
-
-
-
117
120
95
98
-100
-97
-57
-95
-75
-35
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz
Dynamic Range (Note 1)
24-Bit unweighted
A-Weighted
40 kHz bandwidth unweighted
16-Bit unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
(Note 2) -20 dB
-60 dB
THD+N
TBD
TBD
TBD
-
-
-
-
-
-
-
-
117
120
114
92
98
-100
-97
-57
-95
-75
-35
-
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz
Dynamic Range (Note 1)
24-Bit unweighted
A-Weighted
40 kHz bandwidth unweighted
16-Bit unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
(Note 2) -20 dB
-60 dB
THD+N
TBD
TBD
TBD
-
-
-
-
-
-
-
-
117
120
114
92
98
-100
-97
-57
-95
-75
-35
-
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Notes: 1. Triangular PDF dithered data.
2. Performance limited by 16-bit quantization noise.
4 DS333F1
ANALOG CHARACTERISTICS (Continued)
CS4397
Parameter Symbol VD = 3 V VD = 5 V
Power Supplies
Supply Current normal operation
VA = 5 V normal operation
power-down state
Power Dissipation normal operation
VA = 5 V power-down
Power Supply Rejection Ratio (1 kHz) (Note 3)
(120 Hz)
Parameter Symbol Min
Min Typ Max Min Typ Max
I
A
I
D
ID + I
A
PSRR -
-
20
-
TBD
-
60
--TBD
0.3
60
-
40
TBD
TBD
TBD---TBD
-
20
-
TBD
-
-
30
0.3
-
-
60
-
-
40
Typ M ax
TBD
TBD
-
TBD-mW
-
-
Unit
mA
mA
µA
mW
dB
dB
Unit
Analog Output
Full Scale Differential Output Voltage TBD 1.4VREF TBD Vpp
Common Mode Voltage - 0.5VREF - VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Differential DC Offset - 2.0 TBD mV
AC-Load Resistance R
Load Capacitance C
Interchannel Isolation (1 kHz) - 90 - dB
L
L
1--kΩ
- - 100 pF
Notes: 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing
the capacitance will also increase the PSRR.
DS333F1 5
CS4397
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -.020 - +0.015 dB
Passband Ripple - - ±0.0001 dB
StopBand .5465 - - Fs
StopBand Attenuation (Note 5) 102 - - dB
Group Delay (Note 6) tgd - 37/Fs - s
De-emphasis Error (Note 7)
Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double Speed Mode
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.017 - 0.035 dB
Passband Ripple - - ±0.0008 dB
StopBand .570 - - Fs
StopBand Attenuation (Note 5) 82 - - dB
Group Delay tgd - 20/Fs - s
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz 0 - +0.015 dB
Passband Ripple - - ±0.00065 dB
StopBand 0.635 - - Fs
StopBand Attenuation (Note 5) 83 - - dB
Group Delay tgd - 11/Fs - s
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
-
0.470
0.492
±0.10
±0.10
±0.13
0.448
0.486
0.385
0.472
dB
dB
dB
Fs
Fs
Fs
Fs
Fs
Fs
Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 1.4 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.570 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.635 Fs to 1.3 Fs.
6. Group Delay for Fs=48 kHz 37/48 kHz=770 µs
7. De-emphasis is available only in Single Speed Mode.
6 DS333F1
Figures 9-28
) have
CS4397
ANALOG CHARACTERISTICS - DSD MODE (T
Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R
Parameter Symbol Min Typ Max Unit
= 1 kΩ, CL = 10 pF)
L
= 25 °C; Logic "1" = VD = 5 V; VA = 5V;
A
Dynamic Performance - DSD Mode
Dynamic Range (Note 1)
unweighted
A-Weighted
Total Harmonic Distortion + Noise (Note 1)
0 dB
-20 dB
-60 dB
THD+N
TBD
TBD
-
-
-
117
120
-100
-94
-54
-
-
TBD
TBD
TBD
dB
dB
dB
dB
dB
Analog Output - DSD Mode
Full Scale Differential Output Voltage (Note 8) TBD 1.2VREF TBD Vpp
Common Mode Voltage - 0.5VREF - VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Differential DC Offset - 2.0 TBD mV
Combined Digital and On-chip Analog Filter Response - DSD Mode
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.013 - 0 dB
Group Delay tgd - 0.2/Fs - s
-
-
-
-
0.95
2.70
Fs
Fs
Notes: 8. Assumes a DSD modulation index of 0.7.
DS333F1 7
CS4397
ANALOG CHARACTERISTICS - 8X INTERPOLATOR MODE (T
VD = 5 V; VA = 5V; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; Base Band Fs = 48 kHz, SCLK =
6.144 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R
10 pF)
Parameter Symbol Min Typ Max Unit
= 25 °C; Logic "1" =
A
= 1 kΩ, CL =
L
Dynamic Performance Mode
Dynamic Range (Note 1)
unweighted
A-Weighted
Total Harmonic Distortion + Noise (Note 1)
0 dB
-20 dB
-60 dB
THD+N
TBD
TBD
-
-
-
117
120
-100
-97
-57
-
-
TBD
TBD
TBD
dB
dB
dB
dB
dB
Analog Output
Full Scale Differential Output Voltage TBD 0.7VREF TBD Vpp
Common Mode Voltage - 0.5VREF - VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Differential DC Offset - 2.0 TBD mV
Combined Digital and On-chip Analog Filter Response - 8x Interpolator Mode
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.0008 - 0 dB
Passband Ripple - - 0 dB
StopBand 6.08 - - Fs
StopBand Attenuation (Note 9) 56 - - dB
Group Delay tgd - 0.9/Fs - s
-
-
-
-
2.10
3.52
Fs
Fs
Notes: 9. Measurement Bandwidth is 6.08 to 9.6 Fs
8 DS333F1
CS4397
DIGITAL CHARACTERISTICS (T
Parameters Symbol Min Typ Max Units
High-Level Input Voltage VD = 5 V
Low-Level Input Voltage VD = 5 V
Input Leakage Current I
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
= 25°C; VD = 3.0V - 5.25V)
A
V
VD = 3 V
VD = 3 V
IH
V
IL
in
2.0
2.0
-
-
--±10µA
-
-
-
-
-
-
0.8
0.8
V
V
V
V
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)
Parameter Symbol Min Max Unit
DC Power Supply: Positive Analog
Positive Digital
Reference Voltage
Input Current, Any Pin Except Supplies I
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
VA
VD
VREF
in
IND
A
stg
-0.3
-0.3
-0.3
-±10mA
-0.3 (VD)+0.4 V
-55 125 °C
-65 150 °C
6.0
6.0
VA
V
V
V
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
DC Power Supply: Positive Digital
Positive Analog
Reference Voltage
Specified Temperature Range T
VD
VA
VREF
(DGND = 0V; all voltages with respect to ground)
3.0
4.75
TBD
A
-10 - 70 °C
3.3
5.0
5.0
5.25
5.25
VA
V
V
V
DS333F1 9
CS4397
SWITCHING CHARACTERISTICS (T
1 = VD = 5.25 to 3.0 Volts; C
=20pF)
L
= -10 to 70°C; Logic 0 = AGND = DGND; Logic
A
Parameter Symbol Min Typ Max Unit
Input Sample Rate (Single-speed mode)
(Double-speed mode)
(Quad-speed mode)
Fs
Fs
Fs
16
50
100
-
-
-
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle 45 50 55 %
MCLK Frequency (Single-speed 256 Fs,
Double speed 128 Fs or Quad-speed 64 Fs)
MCLK Frequency (Single-speed 384 Fs,
Double speed 192 Fs or Quad-speed, 96 Fs
MCLK Frequency (Single-speed 512 Fs,
Double speed 256 Fs or Quad-speed, 128 Fs
MCLK Frequency (Single-speed 768 Fs,
Double speed 384 Fs or Quad-speed, 192 Fs
4.096
6.144
8.192
12.288
- 12.8 MHz
- 19.2 MHz
- 25.6 MHz
- 38.4 MHz
MCLK Duty Cycle 40 50 60 %
SCLK Frequency (Single-speed mode)
(Double-speed mode)
(Quad-speed mode)
SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t
slrd
slrs
sdlrs
sdh
-
-
-
-
-
-
256×Fs
128×Fs
64×Fs
20 --ns
20 --ns
20 --ns
20 --ns
Hz
Hz
Hz
LRCK
t
slrs
t
sdh
SCLK
SDATA
t
slrd
t
sdlrs
Figure 1. Serial Audio Input Timing
10 DS333F1
CS4397
DSD - SWITCHING CHARACTERISTICS (T
1 = VD = 5.25 to 3.0 Volts; C
Input Bit Rate per Channel (64x Oversampled)
Master Clock Frequency (CLKMODE = 0)
MCLK Duty Cycle (All DSD modes) 40 - 60 %
DSD_SCLK Pulse Width Low t
DSD_SCLK Pulse Width High t
DSD_SCLK Frequency (64x Oversampled)
DSD_LI_R valid to DSD_SCLK rising setup time t
DSD_SCLK rising to DSD_L or DSD_R hold time t
=20pF)
L
Parameter Symbol Min Typ Max Unit
(128x Oversampled)
(CLKMODE = 1)
(128x Oversampled)
= -10 to 70°C; Logic 0 = AGND = DGND; Logic
A
sclkl
sclkh
sdlrs
sdh
1.024
2.048
4.096
6.144
20 --ns
20 --ns
1.024
2.048
20 --ns
20 --ns
t
sclkh
t
sclkl
-
-
-
-
-
-
3.2
6.4
12.8
19.2
3.2
6.4
Mb/s
Mb/s
MHz
MHz
MHz
MHz
DSD_SCLK
DSD_L, DSD_R
Figure 2. Direct Stream Digital - Serial Audio Input Timing
sdlrstsdh
t
DS333F1 11
CS4397
8X INTERPOLATOR - SWITCHING CHARACTERISTICS (T
Logic 0 = AGND = DGND; Logic 1 = VD = 5.25 to 3.0 Volts; C
=20pF)
L
= -10 to 70°C;
A
Parameter Symbol Min Typ Max Unit
Input Sample Rate (Note 10) Fs 128 - 400 kHz
MCLK Frequency (MCLK = 32×Fs)
(MCLK = 48×Fs)
(MCLK = 64×Fs)
(MCLK = 96×Fs)
4.096
6.144
8.192
12.288
-
-
-
-
12.8
19.2
25.6
28.4
MHz
MHz
MHz
MHz
MCLK Duty Cycle 40 - 50 %
WCKI Duty Cycle 25 - 75 %
BCKI Frequency 32xFs MHz
BCKI rising to WCKI edge delay t
BCKI rising to WCKI edge setup time t
SDATA valid to BCKI rising setup time t
BCKI rising to DIL/DIR hold time t
slrd
slrs
sdlrs
sdh
20 --ns
20 --ns
20 --ns
20 --ns
Notes: 10. Fs refers to the input sample rate to the Digital-to-Analog converter, i.e. Fs = 44.1 kHz × 8 = 352.8 kHz.
WCKI
BCKI
DIL/DIR
t
t
slrd
t
sdlrs
slrs
Figure 3. Serial Audio Input Timing
t
sclkl
t
sdh
t
sclkh
12 DS333F1
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)
Parameter Symbol Min Max Unit
I2C® Mode
SCL Clock Frequency f
RST
Rising Edge to Start t
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 11) t
SDA Setup time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
scl
irs
buf
hdst
low
high
sust
hdd
sud
r
f
susp
- 100 KHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
CS4397
Notes: 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
SDA
SCL
irs
Stop Start
t
buf
t
t
hdst
low
t
hdd
t
high
t
sud
Repeated
Start
t
sust
t
hdst
t
f
t
r
Figure 4. I2C Control Port Timing
Stop
t
susp
DS333F1 13
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency f
RST
Rising Edge to CS Falling t
CCLK Edge to CS
CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
Falling (Note 12) t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 13) t
Rise Time of CCLK and CDIN (Note 14) t
Fall Time of CCLK and CDIN (Note 14) t
CCLK Falling to CDOUT valid t
sclk
srs
spi
csh
css
scl
sch
dsu
dh
r2
f2
ov
-6MHz
500 - ns
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
45 ns
CS4397
Notes: 12. t
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
only needed before first falling edge of CS after RST rising edge. t
spi
< 1 MHz
SCK
RST
CS
CCLK
CDIN
CDOUT
t
srs
t
t
css
spi
t
r2
t
t
scl
t
f2
dsu
t
sch
t
dh
= 0 at all other times.
spi
t
csh
t
ov
Figure 5. SPI Control Port Timing
14 DS333F1
2.0 TYPICAL CONNECTION DIAGRAM
CS4397
+5 to +3 V
Digital
(Control Port)
Mode
Select
Audio
Data
Processor
+
1 µF
0.1 µF
7
VD
5
M0 (SDA/CDOUT)
14
M1 (GND)
4
M2 (SCL/CCLK)
3
M3 (AD1/CDIN)
2
M4 (AD0/CS)
16
C/H
12
LRCK
11
SCLK
13
SDATA
15
MUTE
1
RST
10
MCLK
8
VD
CS4397
22
VA
VREF
FILT+
FILT-
CMOUT
AOUTL-
AOUTL+
MUTEC
AOUTR-
AOUTR+
28
27
26
25
24
23
17
19
20
0.1 µf
Conditioning
Conditioning
+5V
+
1.0 µF
0.1 µf
0.1 µf 100 µf
0.1 µf
Analog
+
5.6 µf
+
Analog
Analog
+5V
Analog
DGND
6
External Clock
AGND
21
189
Figure 6. Typical Connection Diagram - Hardware Mode (Control Port Mode)
DS333F1 15
CS4397
3.0 REGISTER DESCRIPTION
3.1 DIFFERENTIAL DC OFFSET CALIBRATION
Mode Control Register (address 01h)
76543210
CAL MUTE
Access:
R/W in I2C and SPI.
Default:
0 - Disabled
Function:
Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be
automatically reset following completion of the calibration sequence.
CAL MODE
M4 M3 M2 M1 M0 PDN
0 Disabled : CAL complete
1 Enabled : CAL initiated
Table 1.
3.2 SOFT MUTE
Mode Control Register (address 01h)
76543210
CAL
MUTE
M4 M3 M2 M1 M0 PDN
Access:
R/W in I2C and SPI.
Default:
0 - Enabled
Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias voltage on the outputs will be retained and MUTEC
The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC
MUTE
0 Enabled
1 Disabled
will go low at the completion of the ramp period.
will go high immediately on disabling of MUTE.
MODE
Table 2.
16 DS333F1
CS4397
3.3 MODE SELECT
Mode Control Register (address 01h)
76543210
CAL MUTE
Access:
R/W in I2C and SPI.
Default:
00000
Function:
The Mode Select pins determine the operational mode of the device as detailed in Tables 9-14. The options include:
Selection of the Digital Interface Format which determines the required relationship between the
Left/Right clock, serial clock and serial data as detailed in Figures 29-33
Selection of the standard 15 µs/50 µs digital de-emphasis filter response, Figure 28, which requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate clocking mode to match the input sample rates.
M4 M3 M2 M1 M0 PDN
Access to the Direct Stream Digital Mode
Access to the 8x Interpolation Input Mode
3.4 POWER DOWN
Mode Control Register (address 01h)
76543210
CAL MUTE
M4 M3 M2 M1 M0 PDN
Access:
R/W in I2C and SPI.
Default:
1 - Powered Down
Function:
The analog and digital sections will be placed into a power-down mode when this function is enabled. This
bit must be cleared to resume normal operation.
PDN MODE
0 Disabled
1 Enabled
Table 3.
DS333F1 17
4.0 PIN DESCRIPTION - PCM MODE
CS4397
Reset RST
See Description M4(AD0/CS
See Description M3(AD1/CDIN) FILT- Reference Ground
See Description M2(SCL/CCLK) CMOUT Common ModeS Voltage
See Description M0(SDA/CDOUT) AOUTL- Differential Output
Digital Ground DGND AOUTL+ Differential Output
Digital Power VD VA Analog Power
Digital Power VD AGND Analog Ground
Digital Ground DGND AOUTR+ Differential Output
Master Clock MCLK AOUTR- Differential Output
Serial Clock SCLK AGND Analog Ground
Left/Right Clock LRCK MUTEC
Serial Data SDATA C/H
See Description M1 MUTE
Reset - RST
Pin 1, Input
Function:
The device enters a low power mode and all internal state machines registers are reset when low. When
high, the device will be in a normal operation mode .
1
1
) FILT+ Reference Filter
2
2
3
4
5
5
6
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREF Voltage Reference
Mute Control
Control port/Hardware select
Soft Mute
Digital Ground - DGND
Pins 6 and 9, Inputs
Function:
Digital ground reference.
Digital Power - VD
Pins 7 and 8, Input
Function:
Digital power supply. Typically 5.0 to 3.0 VDC.
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in Single
Speed Mode; either 128x, 192x 256x or 384x the input sample rate in Double Speed Mode; or 64x, 96x
128x or 192x the input sample rate in Quad Speed Mode. Tables 4-6 illustrate the standard audio sample
rates and the required master clock frequencies.
RST
0
1
DESCRIPTION
Enabled
Normal operation mode
18 DS333F1
CS4397
Sample Rate
(kHz)
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Sample Rate
(kHz)
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
176.4 11.2896 16.9344 22.5792 33.8688
192 12.2880 18.4320 24.5760 36.8640
Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
Serial Clock - SCLK
Pin 11, Input
Function:
MCLK (MHz)
256x 384x 512x 768x
Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies
MCLK (MHz)
128x 192x 256x 384x
MCLK (MHz)
64x 96x 128x 192x
Clocks individual bits of serial data into the SDATA pin. The required relationship between the Left/Right
clock, serial clock and serial data is defined by either the Mode Control Byte in Control Port Mode or the
M0 - M4 pins in Hardware Mode. The options are detailed in Figures 29-33
Left/Right Clock - LRCK
Pin 12, Input
Function:
The Left/Right clock determines which channel is currently being input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 29-33
Serial Audio Data - SDATA
Pin 13, Input
Function:
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed inin Figures 29-33
Soft Mute - MUTE
Pin 15, Input
Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-
DS333F1 19
CS4397
cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias voltage on the outputs will be retained and MUTEC
The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC
The converter analog outputs will mute when enabled. The bias voltage on the outputs will be retained
and MUTEC
will go active during the mute period.
will go active at the completion of the ramp period.
will release immediately on setting MUTE = 1.
Mute
0
1
Control Port / Hardware Mode Select - C/H
Pin 16, Input
Function:
Determines if the device will operate in either the Hardware Mode or Control Port Mode.
C/H
0
1
Mute Control - MUTEC
Pin 17, Output
Function:
The
Mute Control pin goes low during power-up initialization, reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute minimum in extraneous clicks
Analog Ground - AGND
Pins 18 and 21, Inputs
Function:
Analog ground reference.
DESCRIPTION
Enabled
Normal operation mode
DESCRIPTION
Hardware Mode Enabled
Control Port Mode Enabled
and pops.
Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+
Pins 19, 20, 23 and 24, Outputs
Function:
The full scale differential analog output level is specified in the Analog Characteristics specifications table.
Analog Power - VA
Pin 22, Input
Function:
Power for the analog and reference circuits. Typically 5VDC.
20 DS333F1
Common Mode Voltage - CMOUT
Pin 25, Output
Function:
Filter connection for internal bias voltage, typically 50% of VREF. Capacitors must be connected from
CMOUT to analog ground, as shown in Figure 6. CMOUT has a typical source impedence of 25 kΩ and
any current drawn from this pin will alter device performance
Reference Ground - FILT-
Pin 26, Input
Function:
Ground reference for the internal sampling circuits. Must be connected to analog ground.
Reference Filter - FILT+
Pin 27, Output
Function:
Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog
ground, as shown in Figure 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz
and 40 dB of PSRR at 120 Hz. FILT+ is not intended to supply external current.
CS4397
Voltage Reference Input- VREF
Pin 28, Input
Function:
Analog voltage reference. Typically 5VDC.
HARDWARE MODE
Mode Select - M0, M1, M2, M3, M4
Pins 2, 3, 4, 5 and 14, Inputs
Function:
The Mode Select pins determine the operational mode of the device as detailed in Tables 9-14. The options include;
Selection of the Digital Interface Format which determines the required relationship between the
Left/Right clock, serial clock and serial data as detailed in Figures 29-33
Selection of the standard 15 µs/50 µs digital de-emphasis filter response, Figure 28, which requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate clocking mode to match the input sample rates.
Access to the Direct Stream Digital Mode
Access to the 8x Interpolation Input Mode
CONTROL PORT MODE
Address Bit 0 / Chip Select - AD0 / CS
Pin 2, Input
Function:
In I2C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The
device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
DS333F1 21
Address Bit 1 / Control Data Input - AD1/CDIN
Pin 3, Input
Function:
In I2C mode, AD1 is a chip address bit. CDIN is the control data input line for the control port interface in
SPI mode.
Serial Control Interface Clock - SCL/CCLK
Pin 4, Input
Function:
In I2C mode, SCL clocks the serial control data into or from SDA/CDOUT.
In SPI mode, CCLK clocks the serial data into AD1/CDIN and out of SDA/CDOUT.
Serial Control Data I/O - SDA/CDOUT
Pin 5, Input/Output
Function:
In I2C mode, SDA is a data input/output. CDOUT is the control data output for the control port interface in
SPI mode.
M1 - Mode Select
CS4397
Pin 14, Input
Function:
This pin is not used in Control Port Mode and must be terminated to ground.
22 DS333F1
5.0 PIN DESCRIPTION - DSD MODE
CS4397
Refer to PCM mode RST VREF Refer to PCM mode
Refer to PCM mode M4(ADO/CS
Refer to PCM mode M3(AD1/CDIN) FILT- Refer to PCM mode
Refer to PCM mode M2(SCL/CCLK) CMOUT Refer to PCM mode
Refer to PCM mode M0(SDA/CDOUT) AOUTL- Refer to PCM mode
Refer to PCM mode DGND AOUTL+ Refer to PCM mode
Refer to PCM mode VD VA Refer to PCM mode
Refer to PCM mode VD AGND Refer to PCM mode
Refer to PCM mode DGND AOUTR+ Refer to PCM mode
Master Clock MCLK AOUTR- Refer to PCM mode
DSD Serial Clock DSD_SCLK AGND Refer to PCM mode
Master Clock Mode CLKMODE MUTEC
Left Channel Data DSD_L C/H
Right Channel Data DSD_R MUTE
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 4x or 6x the DSD data rate for 64x oversampled DSD data
and 2x or 3x the DSD data rate for 128x oversampled DSD data, refer to Table 7.
1
1
) FILT+ Refer to PCM mode
2
2
3
4
5
5
6
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
CLKMODE
Pin 12, Input
Function:
This pin determines the allowable Master Clock to DSD data ratio as defined in Table 7.
DSD Over-
Sampling Ratio
DSD Serial Clock - DSD_SCLK
Pin 11, Input
Function:
Clocks the individual bits of the DSD audio data into the DSD_L and DSD_R pins.
Audio Data - DSD_L and DSD_R
Pins 13 and 14, Inputs
Function:
Direct Stream Digital audio data is clocked into DSD_L and DSD_R via the DSD serial clock.
CLKMODE
01
64x 4x 6x
128x 2x 3x
Table 7. MCLK to DSD Data Rate Clock Ratios
DS333F1 23
6.0 PIN DESCRIPTION - 8X INTERPOLATOR MODE
CS4397
Refer to PCM mode RST VREF Refer to PCM mode
Refer to PCM mode M4(AD0/CS) FILT+ Refer to PCM mode
Refer to PCM mode M3(AD1/CDIN) FILT- Refer to PCM mode
Refer to PCM mode M2(SCL/CCLK) CMOUT Refer to PCM mode
Refer to PCM mode M0(SDA/CDOUT) AOUTL- Refer to PCM mode
Refer to PCM mode DGND AOUTL+ Refer to PCM mode
Refer to PCM mode VD VA Refer to PCM mode
Refer to PCM mode VD AGND Refer to PCM mode
Refer to PCM mode DGND AOUTR+ Refer to PCM mode
Master Clock MCLK AOUTR- Refer to PCM mode
Bit Clock BCKI AGND Refer to PCM mode
Word Clock WCKI MUTEC
Left Channel Data DIL C/H
Right Channel Data DIR MUTE
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 32x, 48x, 64x or 96x the input sample rate. Table 8 illustrates
the standard audio sample rates and the required master clock frequencies.
1
1
2
2
3
4
5
5
6
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Sample Rate
(kHz)
32 x 8 8.1920 12.2880 16.384 24.576
44.1 x 8 11.2896 16.9344 22.579 33.869
48 x 8 12.2880 18.4320 24.576 36.864
Bit Clock - BCKI
Pin 11, Input
Function:
Clocks the individual serial data bits into the DIL and DIR pins. Refer to Figure 33
Word Clock - WCKI
Pin 12, Input
Function:
The word clock determines which channel is currently being input on the serial audio data input, SDATA.
The frequency of the word clock must be at 8x the baseband sample rate. Refer to Figure 33.
Serial Audio Data - DIR and DIL
Pins 12 and 13, Inputs
Function:
Two's complement MSB-first serial data is input on these pins. The data is clocked into DIL and DIR via
the bit clock. Refer to Figure 33.
MCLK (MHz)
32x 48x 64x 96x
Table 8. Common Clock Frequencies
24 DS333F1
7.0 APPLICATIONS
7.1 Recommended Power-up Sequence
1. Hold RST low until the power supplies, master, and left/right clocks are stable.
2. Bring RST high.
CS4397
DS333F1 25
CS4397
8.0 CONTROL PORT INTERFACE
The control port is used to load all the internal settings of the CS4397. The operation of the control port
may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
The control port has 2 modes: SPI and I2C, with the CS4397 operating as a slave device in both modes. If
I2C operation is desired, AD0/CS should be tied to VD or DGND. If the CS4397 ever detects a high to low
transition on AD0/CS after power-up, SPI mode will be selected.
8.1 SPI Mode
In SPI mode, CS is the CS4397 chip select signal, CCLK is the control port bit clock, CDIN is the input
data line from the microcontroller, CDOUT is the data output and the chip address is 0010000. The data
is clocked on the rising edge of CCLK.
Figure 7 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first
7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W).
The next 8 bits form the Memory Address Pointer (MAP), which is set to 01h. The next 8 bits are the data
which will be placed into the register designated by the MAP.
8.2 I2C Mode
In I2C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL,
with the clock to data relationship as shown in Figure 3. There is no CS pin. Pins AD0 and AD1 form the
partial chip address and should be tied to VD or DGND as required. The 7-bit address field, which is the
first byte sent to the CS4397, must be 00100(AD1)(AD0) where (AD1) and (AD0) match the setting of the
AD0 and AD1 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If
the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to
be read or written. The MAP is then followed by the data to be written. If the operation is a read, then the
contents of the register pointed to by the MAP will be output after the chip address.
For more information on I2C, please see “The I2C-Bus Specification: Version 2.0”, listed in the References
section.
Memory Address Pointer (MAP)
76543210
INCR Reserved Reserved Reserved Reserved MAP2 MAP1 MAP0
00000001
INCR (Auto MAP Increment Enable) MAP0-2 (Memory Address Pointer)
Default = ‘0’ Default = ‘001’
0 - Disabled
1 - Enabled
26 DS333F1
CS4397
CS
CCLK
SDA
CDIN
CHIP
ADDRESS
0010000
R/W
MAP
MAP = Memory Address Pointer = 0
Figure 7. Control Port Timing, SPI mode
001000
ADDR
AD0
R/W
ACK
MSB
byte 1
DATA
1-8
DATA
Note 1
ACK
LSB
byte n
DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 8. Control Port Timing, I2C Mode
DS333F1 27
CS4397
M4 M1
(DIF1)
00 0
00 1
01 0
01 1
Table 9. Single Speed (16 to 50 kHz) Digital Interface Format Options
M4 M3
(DEM1)
00 0
00 1
01 0
01 1
M4 M3 M2 M1 M0 DESCRIPTION
11100
11101
11110
11111
Table 11. Double Speed (50 to 100 kHz) Sample Rate Mode Options
M4 M3 M2 M1 M0 DESCRIPTION
11000
11001
11010
11011
M0
(DIF0)
Left Justified, up to 24-bit data
2
I
S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
M2
(DEM0)
32 kHz De-Emphasis
44.1 kHz De-Emphasis
48 kHz De-Emphasis
De-Emphasis Disabled
Table 10. Single Speed (16 to 50 kHz) De-Emphasis Options
Table 12. Quad (100 to 200 kHz) Sample Rate Mode Options
DESCRIPTION FORMAT FIGURE
DESCRIPTION FIGURE
Left Justified up to 24-bit data, Format 0
2
I
S up to 24-bit data, Format 1
Right Justified 16-bit data, Format 2
Right Justified 24-bit data, Format 3
Left Justified up to 24-bit data, Format 0
2
I
S up to 24-bit data, Format 1
Right Justified 16-bit data, Format 2
Right Justified 24-bit data, Format 3
029
130
231
333
28
28
28
-
M4 M3 M2 M1 M0 DESCRIPTION
1000
(DIR)
1000
(DIR)
Table 13. 8x Interpolated Input Mode Options
M4 M3 M2 M1 M0 DESCRIPTION
1010
(DSD_R)
1010
(DSD_R)
Table 14. Direct Stream Digital Options
Right Justified 20-bit data
0
Right Justified 24-bit data
1
64x Oversampled DSD
0
128x Oversampled DSD
1
28 DS333F1
0
-20
-40
-60
-80
-100
Amplitude dB
-120
-140
-160
0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6
Freque ncy (normali zed to Fs)
Figure 9. Single-speed Transition Band Figure 10. Single-speed Stopband Rejection
CS4397
0
-20
-40
-60
-80
-100
Amplitude dB
-120
-140
-160
0.45 0 .5 0.55 0.6 0.65 0. 7 0.75 0.8 0.85 0. 9 0.95 1
Frequency (normaliz ed to Fs)
0
-1
-2
-3
-4
-5
-6
Amplitude dB
-7
-8
-9
-10
0.45 0.46 0. 47 0.48 0.49 0.5 0.51 0.52
Freque ncy (normalize d to Fs)
0.1
0.08
0.06
0.04
0.02
0
-0. 02
Amplitude dB
-0. 04
-0. 06
-0. 08
-0. 1
0 0.05 0 .1 0.15 0.2 0.25 0. 3 0.35 0.4 0.45
Frequency (normaliz ed to Fs)
Figure 11. Single-speed Transition Band Figure 12. Single-speed Frequency Response
0
-20
-40
-60
-80
Amplitude dB
-100
-120
-140
0.4 0. 45 0.5 0. 55 0.6 0 .65 0.7 0.75 0.8 0.85 0.9 0.95 1
Frequency (normaliz ed to Fs)
0
-20
-40
-60
-80
Amplitude dB
-100
-120
-140
0.4 0.45 0. 5 0.55 0. 6
Frequency (normaliz ed to Fs)
Figure 13. Double-speed Stopband Figure 14. Double-speed Transition Band
0
-1
-2
-3
-4
-5
-6
Amplitude dB
-7
-8
-9
-10
0.42 0. 43 0.44 0.45 0. 46 0. 47 0 .48 0.49 0.5 0.51 0. 52
Freque ncy (normalize d to Fs)
0.1
0.08
0.06
0.04
0.02
0
-0. 02
Amplitude dB
-0. 04
-0. 06
-0. 08
-0. 1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
Frequency (normaliz ed to Fs)
Figure 15. Double-speed Transition Band Figure 16. Double-speed Frequency Response
DS333F1 29
CS4397
0
-20
-40
-60
-80
-100
Amplitude dB
-120
-140
-160
0.4 0. 45 0.5 0. 55 0.6 0 .65 0.7 0.75 0.8 0.85 0.9 0.95 1
Frequency (normaliz ed to Fs)
0
-20
-40
-60
-80
-100
Amplitude dB
-120
-140
-160
0.5 0.52 0.54 0.56 0.58 0. 6 0. 62 0.64 0.6 6 0. 68 0. 7
Frequency (normaliz ed to Fs)
Figure 17. Quad-speed Stopband Rejection Figure 18. Quad-speed Transition Band
0
-1
-2
-3
-4
-5
-6
Amplitude dB
-7
-8
-9
-10
0.35 0. 37 0.39 0.41 0.43 0.45 0.47 0. 49 0.51 0.53
Freque ncy (normalize d to Fs)
0.1
0.08
0.06
0.04
0.02
0
-0. 02
Amplitude dB
-0. 04
-0. 06
-0. 08
-0. 1
0 0.05 0.1 0.15 0.2 0. 25 0. 3 0.35 0. 4
Frequency (normaliz ed to Fs)
Figure 19. Quad-speed Transition Band Figure 20. Quad-speed Frequency Response
0
-20
-40
-60
-80
Amplitude dB
-100
-120
-140
.3 .4 .5 .6 .7 .8 .9 1.0
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
Frequency (normalized to Fs)
20
0
-20
-40
-60
Amplitude dB
-80
-100
-120
.3 .4 .5 .6 .7 .8
2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
Frequency (normalized to Fs)
Figure 21. 8x Interpolator Stop Band Figure 22. 8x Interpolator Transition Band
0
-1
-2
-3
-4
-5
-6
Amplitude dB
-7
-8
-9
-10
.25 .3 3.5 4.0 4.5 5.0 5.5 6.0
2 2.4 2.8 3.2 3.6 4.0 4.4 4.8
0.5 0. 6 0.7 0.8 0.9 1 1. 1 1.2
Frequency (normali zed to Fs)
0.1
0.08
0.06
0.04
0.02
0
-0.02
Amplitude dB
-0.04
-0.06
-0.08
-0.1
0 .0 5 .1 1.5 .2 .25 .3
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (normaliz ed to Fs)
Figure 23. 8x Interpolator Transition Band Figure 24. 8x Interpolator Frequency Response
30 DS333F1
CS4397
0
-10
-20
-30
-40
-50
-60
Amplitude dB
-70
-80
-90
-100
012345678910
Freque ncy (normali zed to Fs)
Figure 25. DSD Frequency Response Figure 26. DSD Transition Band
0
-1
-2
-3
-4
-5
-6
Amplitude dB
-7
-8
-9
-10
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (norma lize d to Fs)
0
-10
-20
-30
-40
-50
-60
Amplitude dB
-70
-80
-90
-100
2.5 3 3.5 4 4. 5 5 5.5 6
Frequency (normaliz ed to Fs)
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1 F2
Frequency
3.183 kHz 10.61 kHz
Figure 27. DSD Transition Band Figure 28. De-Emphasis Curve
DS333F1 31
CS4397
LRCK
SCLK
SDATA +3 +2 +1
LRCK
SCLK
SDATA +3 +2 +1
LRCK
SCLK
SDATA
MSB
-1 -2 -3 -4 -5 +3 +2 +1
MSB
-1 -2 -3 -4 -5
15 14 13 12 11 10
Left Channel
+5 +4
Left Channel
+5 +4
Left Channel
LSB
MSB
-1 -2 -3 -4
Figure 29. Format 0, Left Justified
LSB
MSB
-1 -2 -3 -4
Figure 30. Format 1, I2S
6543210987
15 14 13 12 11 10
Right Channel
+5 +4
Right Channel
+3 +2 +1
+5 +4
Right Cha nnel
LSB
LSB
6543210987
LRCK
SCLK
SDATA
WCKI
BCKI
DIL/DIR
0
LSB
32 clocks
Left Channel
32 clocks
Figure 31. Format 2, Right Justified, 16-Bit Data
6543210723 22 21 20 19 18 6543210723 22 21 20 19 18
Figure 32. Format 3, Right Justified, 24-Bit Data
MSB
23 22
21 20
18 17 16 1519
13
12 11 1014
Figure 33. Format 4, 8x Interpolator Mode
Right Channel
7
8
9
6
5
3
LSB
21
4
32 DS333F1
9.0 PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
CS4397
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
10.0 REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB4397 Evaluation Board Datasheet
3) “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
DS333F1 33
11.0 PACKAGE DIMENSIONS
28L SOIC (300 MIL BODY) PACKAGE DRAWING
1
b
CS4397
HE
c
SEATING
PLANE
D
L
A
e
A1
∝
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.093 0.104 2.35 2.65
A1 0.004 0.012 0.10 0.30
B 0.013 0.020 0.33 0.51
C 0.009 0.013 0.23 0.32
D 0.697 0.713 17.70 18.10
E 0.29G10
0.299 7.40 7.60
1
e 0.040 0.060 1.02 1.52
H 0.394 0.419 10.00 10.65
L 0.016 0.050 0.40 1.27
∝
0° 8° 0° 8°
JEDEC #: MS-013
34 DS333F1
Loading...