24-Bit, Multi-Standard D/A Converter for Digital Audio
Features
24 Bit Conversion
Up to 192 kHz Sample Rates
120 dB Dynamic Range
-100 dB THD+N
Supports PCM, DSD and External
Interpolation filters
Advanced Dynamic-Element Matching
Low Clock Jitter Sensitivity
Digital De-emphasis for 32 kHz, 44.1 kHz and
48 kHz
External Reference Input
I
SCLK
LRCK
SDATA
SERIAL INTERFACE
AND FORMAT SELECT
Description
The CS4397 is a complete high performance 24-bit
48/96/192 kHz stereo digital-to-analog conversion system. The device includes a digital interpolation filter
followed by a oversampled multi-bit delta-sigma modulator which drives dynamic-element-matching (DEM)
selection logic. The output from the DEM block controls
the input to a multi-element switched capacitor DAC/lowpass filter, with fully-differential outputs. This multi-bit architecture features significantly lower out-of-band noise
and jitter sensitivity than traditional 1-bit designs, and the
advanced DEM guarantees low noise and distortion at
all signal levels.
ORDERING INFORMATION
CS4397-KS-10° to 70° C 28-pin Plastic SOIC
CS4397-KSZ -10° to 70° C 28-pin Plastic SOIC Lead free
CDB4397Evaluation Board
C Mode ................................................................. 27
2
S ........................................................................................... 32
CS4397
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
“The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information descr ibes products which are in development and subj ect to development changes . Cirrus Logic, Inc. has made best eff orts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or ot her rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publicati on may be copied, reproduced, stored i n a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photograp hic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, sto red in a retrieval syst em, or t ransmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of thi s publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or ser vice marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirr us.com.
DS333F13
1.0 CHARACTERISTICS/SPECIFICATIONS
CS4397
ANALOG CHARACTERISTICS (T
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz
to 20 kHz, unless otherwise specified. Test load R
2. Performance limited by 16-bit quantization noise.
4DS333F1
ANALOG CHARACTERISTICS (Continued)
CS4397
ParameterSymbolVD = 3 VVD = 5 V
Power Supplies
Supply Currentnormal operation
VA = 5 Vnormal operation
power-down state
Power Dissipation normal operation
VA = 5 Vpower-down
Power Supply Rejection Ratio (1 kHz)(Note 3)
(120 Hz)
ParameterSymbolMin
MinTypMax MinTypMax
I
A
I
D
ID + I
A
PSRR-
-
20
-
TBD
-
60
--TBD
0.3
60
-
40
TBD
TBD
TBD---TBD
-
20
-
TBD
-
-
30
0.3
-
-
60
-
-
40
TypM ax
TBD
TBD
-
TBD-mW
-
-
Unit
mA
mA
µA
mW
dB
dB
Unit
Analog Output
Full Scale Differential Output VoltageTBD1.4VREFTBDVpp
Common Mode Voltage-0.5VREF-VDC
Interchannel Gain Mismatch-0.1-dB
Gain Drift-100-ppm/°C
Differential DC Offset-2.0TBDmV
AC-Load ResistanceR
Load CapacitanceC
Interchannel Isolation(1 kHz)-90-dB
L
L
1--kΩ
--100pF
Notes: 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing
the capacitance will also increase the PSRR.
DS333F15
CS4397
ANALOG CHARACTERISTICS (Continued)
ParameterSymbolMinTypMaxUnit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-.020-+0.015dB
Passband Ripple--±0.0001dB
StopBand.5465--Fs
StopBand Attenuation(Note 5)102--dB
Group Delay(Note 6)tgd-37/Fs-s
De-emphasis Error(Note 7)
Fs = 32 kHz
(Relative to 1 kHz)Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double Speed Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.017-0.035dB
Passband Ripple--±0.0008dB
StopBand.570--Fs
StopBand Attenuation(Note 5)82--dB
Group Delaytgd-20/Fs-s
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz0-+0.015dB
Passband Ripple--±0.00065dB
StopBand0.635--Fs
StopBand Attenuation(Note 5)83--dB
Group Delaytgd-11/Fs-s
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
-
0.470
0.492
±0.10
±0.10
±0.13
0.448
0.486
0.385
0.472
dB
dB
dB
Fs
Fs
Fs
Fs
Fs
Fs
Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 1.4 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.570 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.635 Fs to 1.3 Fs.
6. Group Delay for Fs=48 kHz 37/48 kHz=770 µs
7. De-emphasis is available only in Single Speed Mode.
6DS333F1
Figures 9-28
) have
CS4397
ANALOG CHARACTERISTICS - DSD MODE (T
Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R
ParameterSymbolMinTypMaxUnit
= 1 kΩ, CL = 10 pF)
L
= 25 °C; Logic "1" = VD = 5 V; VA = 5V;
A
Dynamic Performance - DSD Mode
Dynamic Range(Note 1)
unweighted
A-Weighted
Total Harmonic Distortion + Noise(Note 1)
0 dB
-20 dB
-60 dB
THD+N
TBD
TBD
-
-
-
117
120
-100
-94
-54
-
-
TBD
TBD
TBD
dB
dB
dB
dB
dB
Analog Output - DSD Mode
Full Scale Differential Output Voltage(Note 8)TBD1.2VREFTBDVpp
Common Mode Voltage-0.5VREF-VDC
Interchannel Gain Mismatch-0.1-dB
Gain Drift-100-ppm/°C
Differential DC Offset-2.0TBDmV
Combined Digital and On-chip Analog Filter Response - DSD Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.013-0dB
Group Delaytgd-0.2/Fs-s
-
-
-
-
0.95
2.70
Fs
Fs
Notes: 8. Assumes a DSD modulation index of 0.7.
DS333F17
CS4397
ANALOG CHARACTERISTICS - 8X INTERPOLATOR MODE (T
VD = 5 V; VA = 5V; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; Base Band Fs = 48 kHz, SCLK =
6.144 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R
10 pF)
ParameterSymbolMinTypMaxUnit
= 25 °C; Logic "1" =
A
= 1 kΩ, CL =
L
Dynamic Performance Mode
Dynamic Range(Note 1)
unweighted
A-Weighted
Total Harmonic Distortion + Noise(Note 1)
0 dB
-20 dB
-60 dB
THD+N
TBD
TBD
-
-
-
117
120
-100
-97
-57
-
-
TBD
TBD
TBD
dB
dB
dB
dB
dB
Analog Output
Full Scale Differential Output VoltageTBD0.7VREFTBDVpp
Common Mode Voltage-0.5VREF-VDC
Interchannel Gain Mismatch-0.1-dB
Gain Drift-100-ppm/°C
Differential DC Offset-2.0TBDmV
Combined Digital and On-chip Analog Filter Response - 8x Interpolator Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.0008-0dB
Passband Ripple--0dB
StopBand6.08--Fs
StopBand Attenuation(Note 9)56--dB
Group Delaytgd-0.9/Fs-s
-
-
-
-
2.10
3.52
Fs
Fs
Notes: 9. Measurement Bandwidth is 6.08 to 9.6 Fs
8DS333F1
CS4397
DIGITAL CHARACTERISTICS (T
ParametersSymbol Min TypMaxUnits
High-Level Input VoltageVD = 5 V
Low-Level Input VoltageVD = 5 V
Input Leakage CurrentI
Input Capacitance-8-pF
Maximum MUTEC Drive Current-3-mA
= 25°C; VD = 3.0V - 5.25V)
A
V
VD = 3 V
VD = 3 V
IH
V
IL
in
2.0
2.0
-
-
--±10µA
-
-
-
-
-
-
0.8
0.8
V
V
V
V
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)
ParameterSymbol Min MaxUnit
DC Power Supply: Positive Analog
Positive Digital
Reference Voltage
Input Current, Any Pin Except SuppliesI
Digital Input VoltageV
Ambient Operating Temperature (power applied)T
Storage TemperatureT
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
VA
VD
VREF
in
IND
A
stg
-0.3
-0.3
-0.3
-±10mA
-0.3(VD)+0.4V
-55125°C
-65150°C
6.0
6.0
VA
V
V
V
RECOMMENDED OPERATING CONDITIONS
ParameterSymbol Min TypMaxUnit
DC Power Supply: Positive Digital
Positive Analog
Reference Voltage
Specified Temperature RangeT
VD
VA
VREF
(DGND = 0V; all voltages with respect to ground)
3.0
4.75
TBD
A
-10-70°C
3.3
5.0
5.0
5.25
5.25
VA
V
V
V
DS333F19
CS4397
SWITCHING CHARACTERISTICS (T
1 = VD = 5.25 to 3.0 Volts; C
=20pF)
L
= -10 to 70°C; Logic 0 = AGND = DGND; Logic
A
ParameterSymbol Min TypMaxUnit
Input Sample Rate (Single-speed mode)
(Double-speed mode)
(Quad-speed mode)
Fs
Fs
Fs
16
50
100
-
-
-
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle455055%
MCLK Frequency (Single-speed 256 Fs,
Double speed 128 Fs or Quad-speed 64 Fs)
MCLK Frequency (Single-speed 384 Fs,
Double speed 192 Fs or Quad-speed, 96 Fs
MCLK Frequency (Single-speed 512 Fs,
Double speed 256 Fs or Quad-speed, 128 Fs
MCLK Frequency (Single-speed 768 Fs,
Double speed 384 Fs or Quad-speed, 192 Fs
4.096
6.144
8.192
12.288
-12.8MHz
-19.2MHz
-25.6MHz
-38.4MHz
MCLK Duty Cycle405060%
SCLK Frequency (Single-speed mode)
(Double-speed mode)
(Quad-speed mode)
SCLK rising to LRCK edge delayt
SCLK rising to LRCK edge setup timet
SDATA valid to SCLK rising setup timet
SCLK rising to SDATA hold timet