Cirrus Logic CS4391A User Manual
CS4391A
24-Bit, 192 kHz Stereo DAC with Volume Control
Features
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
108 dB Dynamic Range
94 dB THD+N
Direct Stream Digital Mode
Low Clock Jitter Sensitivity
+5 V Power Supply
ATAPI Mixing
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
Volume Control with Soft Ramp
– 119 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
Direct Interface with 5 V to 1.8 V Logic
I
M1
(SDA/CDIN)
M3
M2
(SCL/CCLK) (AD0/CS)
Description
The CS4391A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter.
The CS4391A accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, consumes very little
power and operates over a wide power supply range.
These features are ideal for DVD, A/V receivers, CD and
set-top box systems.
ORDERING INFORMATION
CS4391A-KS 20-pin SOIC -10 to 70 °C
CS4391A-KZ 20-pin TSSOP -10 to 70 °C
CS4391A-KZZ 20-pin TSSOP, Lead Free -10 to 70 °C
CDB4391A Evaluation Board
M0
AMUTEC
CMOUT
FILT+BMUTEC
MODE SELECT
(CONTROL PORT)
RST
SCLK
LRCK
SDATA
SERIAL
PORT
Preliminary Product Information
www.cirrus.com
INTERPOLATION
FILTER
INTERPOLATOR
FILTER
MUTE CONTROL
VOLUM E
CONTROL
MIXER
VOLUM E
CONTROL
MCLK
EXTERNAL
∆Σ
DAC
∆Σ
DAC
REFERENCE
ANALOG
FILTER
ANALOG
FILTER
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 20 04
(All Rights Reserved)
AOUTA+
AOUTA-
AOUTB+
AOUTB-
JUL ‘04
DS600PP3
1
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5
2. TYPICAL CONNECTION DIAGRAMS ...................................................................................13
3. REGISTER QUICK REFERENCE ..........................................................................................15
3.1 Mode Control 1 (address 01h) .......................................................................................... 15
3.2 Volume and Mixing Control (address 02h)........................................................................ 16
3.3 Channel A Volume Control (address 03h) ........................................................................ 16
3.4 Channel B Volume Control (address 04h) ........................................................................ 16
3.5 Mode Control 2 (address 05h) .......................................................................................... 17
4. REGISTER DESCRIPTION .................................................................................................... 18
4.1 Mode Control 1 - Address 01h .......................................................................................... 18
4.1.1 Auto-Mute (Bit 7) ................................................................................................. 18
4.1.2 Digital Interface Formats (Bits 6:4) ...................................................................... 18
4.1.3 De-Emphasis Control (Bits 3:2) ........................................................................... 18
4.1.4 Functional Mode (Bits 1:0) .................................................................................. 18
4.2 Volume and Mixing Control (Address 02h) .......................................................................19
4.2.1 Channel A Volume = Channel B Volume (Bit 7) ................................................. 19
4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ......................................................... 19
4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) ...................................................... 19
4.3 Channel A Volume Control - Address 03h........................................................................ 19
4.4 Channel B Volume Control - Address 04h .......................................................................20
4.4.1 Mute (Bit 7) .......................................................................................................... 20
4.4.2 Volume Control (Bits 6:0) .................................................................................... 20
4.5 Mode Control 2 - Address 05h .......................................................................................... 20
4.5.1 Invert Signal Polarity (Bits 7:6) ............................................................................ 20
4.5.2 Control Port Enable (Bit 5) .................................................................................. 20
4.5.3 Power Down (Bit 4) .............................................................................................20
4.5.4 AMUTEC = BMUTEC (Bit 3) ............................................................................... 20
4.5.5 Freeze (Bit 2) ...................................................................................................... 21
4.5.6 Master Clock Divide (Bit 1) .................................................................................. 21
CS4391A
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") beli eve that the information contai ned in this document is accurate and rel iable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to veri fy, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and condi tions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitati on of liabil ity. No responsibility is assumed by Cirrus for the use of thi s infor mation, i ncluding use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Thi s document is the property of Cirrus
and by furni shing this information, Cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyri ghts associated with the information contained herein and gives consent for copies to be made of the
information only for use within your organi zation with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying
such as copying for general distri bution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtai ned from the competent authorities of the Japanese Government if any of the products or technologies described in thi s material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export li cense and/or quota needs to be
obtained f rom the competent author ities of t he Chinese Government if any of the products or tec hnologies describ ed in this mater ial is subj ect to the PRC Forei gn
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE I N LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I
those components in a standard I
Cirrus Logic, Cirrus, and the Ci rrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or servi ce marks of their respective owners.
2 DS600PP3
2
C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use
2
C system.
5. PIN DESCRIPTION - PCM DATA MODE ............................................................................... 22
6. PIN DESCRIPTION - DSD MODE .......................................................................................... 26
7. APPLICATIONS ..................................................................................................................... 33
7.1 Recommended Power-up Sequence for Hardware Mode ............................................... 33
7.2 Recommended Power-up Sequence and Access to Control Port Mode ......................... 33
7.3 Analog Output and Filtering ............................................................................................. 33
8. CONTROL PORT INTERFACE .............................................................................................. 34
8.1 SPI Mode ......................................................................................................................... 34
8.2 I2C Mode ......................................................................................................................... 34
9. PARAMETER DEFINITIONS .................................................................................................. 38
10. REFERENCES ...................................................................................................................... 38
11. PACKAGE DIMENSIONS ................................................................................................. 39
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Modes ................................................................................ 27
Table 2. Digital Interface Formats - DSD Mode...................................................................................27
Table 3. De-Emphasis Mode Selection .............................................................................................. 27
Table 4. Functional Mode Selection .................................................................................................... 27
Table 5. Soft Cross or Zero Cross Mode Selection............................................................................ 27
Table 6. ATAPI Decode....................................................................................................................... 28
Table 7. Digital Volume Control........................................................................................................... 28
Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies................................ 29
Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies ......................... 29
Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies ........................ 29
Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options .............. 29
Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options ..................... 29
Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options......... 29
Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options ......... 30
Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options ................................................... 30
Table 16. Memory Address Pointer (MAP)..........................................................................................35
CS4391A
DS600PP3 3
LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 9
Figure 2. Direct Stream Digital - Serial Audio Input Timing........................................................... 10
Figure 3. I
Figure 4. SPI Control Port Timing ................................................................................................. 12
Figure 5. Typical Connection Diagram - PCM Mode.....................................................................13
Figure 6. Typical Connection Diagram - DSD Mode ..................................................................... 14
Figure 7. Format 0, Left Justified up to 24-Bit Data....................................................................... 31
Figure 8. Format 1, I2S up to 24-Bit Data .....................................................................................31
Figure 9. Format 2, Right Justified 16-Bit Data ............................................................................. 31
Figure 10. Format 3, Right Justified 24-Bit Data ........................................................................... 31
Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 32
Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 32
Figure 13. De-Emphasis Curve..................................................................................................... 32
Figure 14. ATAPI Block Diagram ..................................................................................................32
Figure 15. CS4391A Output Filter .................................................................................................33
Figure 16. Control Port Timing, SPI mode ....................................................................................35
Figure 17. Control Port Timing, I
Figure 18. Single-Speed Frequency Response ............................................................................ 36
Figure 19. Single-Speed Transition Band .....................................................................................36
Figure 20. Single-Speed Transition Band .....................................................................................36
Figure 21. Single-Speed Stopband Rejection ............................................................................... 36
Figure 22. Double-Speed Frequency Response ........................................................................... 36
Figure 23. Double-Speed Transition Band .................................................................................... 36
Figure 24. Double-Speed Transition Band .................................................................................... 37
Figure 25. Double-Speed Stopband Rejection .............................................................................. 37
2
C Control Port Timing .................................................................................................. 11
CS4391A
2
C Mode .....................................................................................35
4 DS600PP3
CS4391A
1. CHARACTERISTICS/SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics are derived from measurements taken at T
SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters Symbol Min Typ Max Units
DC Power Supply VA
VL
Specified Temperature Range -KS & -KZ T
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
DC Power Supply VA
Input Current, Any Pin Except Supplies I
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
A
VL
in
IND
A
stg
= 25 °C, VA = 5.0 V)
A
4.75
1.8
-10 - 70 °C
-0.3
-0.3
-0.3 VL+0.4 V
-55 125 °C
-65 150 °C
5.0
-
-±10mA
6.0
VA
5.25
VA
V
V
V
V
DS600PP3 5
CS4391A
ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a
997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; Test load R
Parameter
Symbol Min Typ Max Unit
Dynamic Performance
Dynamic Range (Note 1)
unweighted
A-Weighted
40 kHz Bandwidth A-Weighted
Total Harmonic Distortion + Noise (Note 1,2)
THD+N
0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-Noise Ratio - 108 - dB
Interchannel Isolation (1 kHz) - 100 - dB
Power Supplies
Power Supply Current normal operation
power-down state
I
+ I
A
IA + I
L
L
Power Dissipation
normal operation
power-down
Power Supply Rejection Ratio (1 kHz) (Note 3)
PSRR -
(60 Hz)
= 5 kΩ, CL = 10 pF)
L
VA = 5 V
100
103
-
-
-
-
-
-
-
-
105
108
102
-94
-85
-45
17
60
85
0.3
60
-
40
-
-
-
-89
-
-40
35
-
dB
dB
dB
dB
dB
dB
mA
µA
175-mW
mW
-
-
dB
dB
Parameter Symbol Min Typ Max Units
Analog Ou tput
Full Scale Differential Output Voltage 1.05VA 1.1VA 1.15VA Vpp
Common Mode Voltage CMOUT - 0.43VA - VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
AC-Load Resistance R
Load Capacitance C
L
L
5--kΩ
- - 100 pF
6 DS600PP3
CS4391A
ANALOG CHARACTERISTICS (continued)
Parameter Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode
Passband (Note 3)
to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -.02 - +.035 dB
StopBand .5465 - - Fs
StopBand Attenuation (Note 5) 50 - - dB
Group Delay tgd - 9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s
De-emphasis Error (Relative to 1 kHz)
Control Port Mode Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Stand-Alone Mode Fs = 44.1 kHz
Combined Digital and On-chip Analog Filter Response - Double Speed Mode
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB
StopBand .577 - - Fs
StopBand Attenuation (Note 5) 55 - - dB
Group Delay tgd - 9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - ±0.23/Fs - s
On-chip Analog Filter Response - Quad Speed Mode
Passband (Note 4)
to -3 dB corner 0 - 0.25 Fs
Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB
On-chip Analog Filter Response - DSD Mode
Passband (Note 4)
to -3 dB corner 0 - 1.0 Fs
Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB
Notes: 1. Triangular PDF dithered data.
2. THD+N specifications for 48 kHz sample rates are made over a 20 kHz Bandwidth.
3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing
the capacitance will also increase the PSRR.
4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 18-25) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
0
0
-
-
-
-
0
0
-
-
-
-
-
-
-
-
.4535
.4998
+.2/-.1
+.05/-.14
+0/.22
+.05/-.14
.4621
.4982
Fs
Fs
dB
dB
dB
dB
Fs
Fs
DS600PP3 7
CS4391A
DIGITAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Typ Max Units
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current I
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
V
IH
V
IL
in
70% - - VL
- 20% VL
--±10µA
8 DS600PP3
CS4391A
SWITCHING CHARACTERISTICS - PCM MODES (Inputs: Logic 0 = 0 V, Logic 1 = VL)
Parameters Symbol Min Typ Max Units
Input Sample Rate Fs 4 - 200 kHz
LRCK Duty Cycle 45 50 55 %
MCLK Duty Cycle 40 50 60 %
SCLK Frequency
SCLK Frequency (Note 6)
SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t
slrd
slrs
sdlrs
sdh
-
-
20 - - ns
20 - - ns
20 - - ns
20 - - ns
Notes: 6. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
-MCLK/2Hz
-MCLK/4Hz
LRCK
SCLK
SDATA
t
t
slrd
t
sdlrs
slrs
t
sdh
Figure 1. Serial Mode Input Timing
DS600PP3 9
CS4391A
SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VL)
Parameter Symbol Min Typ Max Unit
MCLK Duty Cycle 40 50 60 %
SCLK Pulse Width Low t
SCLK Pulse Width High t
SCLK Period t
SDIN valid to SCLK rising setup time t
SCLK rising to SDIN hold time t
sclkl
sclkh
sclkw
sdlrs
sdh
t
sclkl
20 - - ns
20 - - ns
20
--ns
20 - - ns
20 - - ns
t
sclkh
SCLK
t
sdlrstsdh
SDATA
Figure 2. Direct Stream Digital - Serial Audio Input Timing
10 DS600PP3
CS4391A
SWITCHING CHARACTERISTICS - I2C CONTROL PORT (Inputs: logic 0 = AGND,
logic 1 = VL)
Parameter Symbol Min Max Unit
2C®
Mode
I
SCL Clock Frequency f
RST
Rising Edge to Start t
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 7) t
SDA Setup time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
scl
irs
buf
hdst
low
high
sust
hdd
sud
r
f
susp
-100KHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
Notes: 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
SDA
SCL
irs
Stop S tart
t
buf
t
hdst
t
low
t
hdd
t
high
t
sud
Repeated
Start
t
t
sust
hdst
t
f
t
r
Figure 3. I2C Control Port Timing
Stop
t
susp
DS600PP3 11
CS4391A
SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND,
logic 1 = VL)
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency f
RST
Rising Edge to CS Falling t
CCLK Edge to CS
CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
Falling (Note 8) t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 9) t
Rise Time of CCLK and CDIN (Note 10) t
Fall Time of CCLK and CDIN (Note 10) t
sclk
srs
spi
csh
css
scl
sch
dsu
dh
r2
f2
-6MHz
500 - ns
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
Notes: 8. t
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F
only needed before first falling edge of CS after RST rising edge. t
spi
< 1 MHz
SCK
RST
CS
CCLK
CDIN
t
srs
t
t
css
spi
t
r2
t
t
sch
scl
t
f2
t
t
dsu
dh
= 0 at all other times.
spi
t
csh
Figure 4. SPI Control Port Timing
12 DS600PP3
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