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CS4391
User Manual
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Cirrus Logic CS4391 User Manual

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CS4391
24-Bit, 192 kHz Stereo DAC with Volume Control
Features
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
108 dB Dynamic Range
94 dB THD+N
Direct Stream Digital Mode
Low Clock Jitter Sensitivity
+5 V to +3 V Power Supply
ATAPI Mixing
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
Volume Control with Soft Ramp
–119 dB Attenuation –1 dB Step Size –Zero Crossing Click-Free Transitions
36 mW with 3 V supply
Direct Interface with 5 V to 1.8 V Logic
I
M1
(SDA/CDIN)
M3
M2
(SCL/CCLK) (AD0/CS)
Description
The CS4391 is a complete stereo digital-to-analog sys­tem including digital interpolation, fourth-order delta­sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera­ture and a high tolerance to clock jitter.
The CS4391 accepts PCM data at sample rates from 2 kHz to 192 kHz, DSD audio data, consumes very little power and operates over a wide power supply range. These features are ideal for DVD, A/V receivers, CD and set-top box systems.
ORDERING INFORMATION
CS4391-KZ 20-pin TSSOP -10 to 70 °C CS4391-KZZ 20-pin TSSOP, Lead Free -10 to 70°C
CDB4391 Evaluation Board
M0
AMUTEC
CMOUT
FILT+BMUTEC
MODE SELECT
(CONTROL PORT)
RST
SCLK
LRCK
SDATA
SERIAL
PORT
Preliminary Product Information
INTERPOLATION
FILTER
INTERPOLATOR
FILTER
MUTE CONTROL
VOLUM E
CONTROL
MIXER
VOLUM E
CONTROL
MCLK
EXTERNAL
∆Σ
DAC
∆Σ
DAC
REFERENCE
ANALOG
FILTER
ANALOG
FILTER
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
AOUTA+
AOUTA-
AOUTB+
AOUTB-
Jul ‘04
DS335PP4
1
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS .......................................................................... 5
ANALOG CHARACTERISTICS...................................................................................... 5
DIGITAL CHARACTERISTICS....................................................................................... 7
ABSOLUTE MAXIMUM RATINGS ................................................................................. 7
RECOMMENDED OPERATING CONDITIONS ............................................................. 7
SWITCHING CHARACTERISTICS - PCM MODES....................................................... 8
SWITCHING CHARACTERISTICS - DSD ..................................................................... 9
SWITCHING CHARACTERISTICS - I2C CONTROL PORT ........................................ 10
SWITCHING CHARACTERISTICS - SPI CONTROL PORT ....................................... 11
2. TYPICAL CONNECTION DIAGRAMS ............................................................................ 12
3. REGISTER QUICK REFERENCE ................................................................................... 14
3.1 Mode Control 1 (address 01h)................................................................................ 14
3.2 Volume and Mixing Control (address 02h) ............................................................. 15
3.3 Channel A Volume Control (address 03h).............................................................. 15
3.4 Channel B Volume Control (address 04h).............................................................. 15
3.5 Mode Control 2 (address 05h)................................................................................ 16
4. REGISTER DESCRIPTION ............................................................................................. 17
4.1 Mode Control 1 - Address 01h................................................................................ 17
4.1.1 Auto-Mute (Bit 7) .............................................................................17
4.1.2 Digital Interface Formats (Bits 6:4) ..................................................17
4.1.3 De-Emphasis Control (Bits 3:2) .......................................................17
4.1.4 Functional Mode (Bits 1:0) ..............................................................17
4.2 Volume and Mixing Control (Address 02h)............................................................. 18
4.2.1 Channel A Volume = Channel B Volume (Bit 7) ..............................18
4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) .....................................18
4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) ..................................18
4.3 Channel A Volume Control - Address 03h.............................................................. 18
4.4 Channel B Volume Control - Address 04h.............................................................. 19
4.4.1 Mute (Bit 7) ......................................................................................19
4.4.2 Volume Control (Bits 6:0) ................................................................19
4.5 Mode Control 2 - Address 05h................................................................................ 19
4.5.1 Invert Signal Polarity (Bits 7:6) ........................................................19
4.5.2 Control Port Enable (Bit 5) ..............................................................19
4.5.3 Power Down (Bit 4) .........................................................................19
4.5.4 AMUTEC = BMUTEC (Bit 3) ...........................................................19
4.5.5 Freeze (Bit 2) ..................................................................................20
4.5.6 Master Clock Divide (Bit 1) ..............................................................20
5. PIN DESCRIPTION - PCM DATA MODE ........................................................................ 21
Reset - RST.................................................................................................................. 21
Interface Power - VL..................................................................................................... 21
CS4391
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com
I2C is a registered trademark of Philips Semiconductors.
Preliminary product informati on describes products which are in producti on, but for which full characterization data is not yet available. Advance product infor­mation descr ibes products which are in dev elopment and subject to development changes. Ci rrus Logic, Inc. has made best eff orts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the proper ty of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, i n any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, sto red in a retrieval sys tem, or transmit ted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppli ers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdicti ons. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.
2 DS335PP4
Serial Audio Data - SDATA ...........................................................................................21
Serial Clock - SCLK ......................................................................................................22
Left / Right Clock - LRCK ..............................................................................................22
Master Clock - MCLK ....................................................................................................22
Mode Select - M3, M2, M1 and M0 (Stand-alone Mode) .............................................22
Mode Select - M3 (Control Port Mode) ........................................................................22
Serial Control Interface Clock - SCL/CCLK (Control Port Mode) .................................23
Serial Control Data I/O - SDA/CDIN (Control Port Mode) .............................................23
Address Bit / Chip Select - AD0 / CS
Positive Voltage Reference - FILT+ ..............................................................................23
Common Mode Voltage - CMOUT ................................................................................23
Channel A and Channel B Mute Control - AMUTEC and BMUTEC .............................23
Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTA- ......................24
Analog Ground - AGND ................................................................................................24
Analog Power - VA ........................................................................................................24
6. PIN DESCRIPTION - DSD MODE ....................................................................................25
DSD Audio Data - DSD_A and DSD_B.........................................................................25
DSD Mode - DSD_Mode ...............................................................................................25
Master Clock - MCLK ....................................................................................................25
DSD Serial Clock - DSD_SCLK ...................................................................................25
7. APPLICATIONS ...............................................................................................................32
7.1 Recommended Power-up Sequence for Hardware Mode ....................................32
7.2 Recommended Power-up Sequence and Access to Control Port Mode ..............32
7.3 Analog Output and Filtering ..................................................................................32
8. CONTROL PORT INTERFACE ........................................................................................33
8.1 SPI Mode ..............................................................................................................33
8.2 I2C Mode ..............................................................................................................33
9. PARAMETER DEFINITIONS ...........................................................................................37
Total Harmonic Distortion + Noise (THD+N) .................................................................37
Dynamic Range.............................................................................................................37
Interchannel Isolation ....................................................................................................37
Interchannel Gain Mismatch .........................................................................................37
Gain Error......................................................................................................................37
Gain Drift .......................................................................................................................37
10. REFERENCES ...............................................................................................................37
11. PACKAGE DIMENSIONS ...........................................................................................38
(Control Port Mode)...........................................23
CS4391
DS335PP4 3
LIST OF TABLES
Figure:1. Digital Interface Formats - PCM Modes ....................................................................... 26
Figure:2. Digital Interface Formats - DSD Mode ......................................................................... 26
Figure:3. De-Emphasis Mode Selection ..................................................................................... 26
Figure:4. Functional Mode Selection ...........................................................................................26
Figure:5. Soft Cross or Zero Cross Mode Selection ................................................................... 26
Figure:6. ATAPI Decode ............................................................................................................. 27
Figure:7. Digital Volume Control ................................................................................................. 27
Figure:8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies ...................... 28
Figure:9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies ................ 28
Figure:10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies .............. 28
Figure:11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options ..... 28
Figure:12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options ............ 28
Figure:13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options 28 Figure:14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options 29
Figure:15. Direct Stream Digital (DSD), Stand-Alone Mode Options .......................................... 29
Figure:16. Memory Address Pointer (MAP) ................................................................................34
LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 8
Figure 2. Direct Stream Digital - Serial Audio Input Timing............................................................. 9
Figure 3. I
Figure 4. SPI Control Port Timing ................................................................................................. 11
Figure 5. Typical Connection Diagram - PCM Mode.....................................................................12
Figure 6. Typical Connection Diagram - DSD Mode ..................................................................... 13
Figure 7. Format 0, Left Justified up to 24-Bit Data....................................................................... 30
Figure 8. Format 1, I2S up to 24-Bit Data .....................................................................................30
Figure 9. Format 2, Right Justified 16-Bit Data .............................................................................30
Figure 10. Format 3, Right Justified 24-Bit Data ........................................................................... 30
Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 31
Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 31
Figure 13. De-Emphasis Curve.....................................................................................................31
Figure 14. ATAPI Block Diagram ..................................................................................................31
Figure 15. CS4391 Output Filter ................................................................................................... 32
Figure 16. Control Port Timing, SPI mode .................................................................................... 34
Figure 17. Control Port Timing, I
Figure 18. Single-Speed Frequency Response ............................................................................ 35
Figure 19. Single-Speed Transition Band .....................................................................................35
Figure 20. Single-Speed Transition Band .....................................................................................35
Figure 21. Single-Speed Stopband Rejection ............................................................................... 35
Figure 22. Double-Speed Frequency Response ........................................................................... 35
Figure 23. Double-Speed Transition Band .................................................................................... 35
Figure 24. Double-Speed Transition Band .................................................................................... 36
Figure 25. Double-Speed Stopband Rejection .............................................................................. 36
2
C Control Port Timing ..................................................................................................10
CS4391
2
C Mode ..................................................................................... 34
4 DS335PP4

1. CHARACTERISTICS/SPECIFICATIONS

CS4391
ANALOG CHARACTERISTICS (T
= 25° C; Logic "1" = VL = VA; Logic "0" = AGND; Full-Scale Out-
A
put Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Sample Rate = 48, 96 or 192 kHz, 24-bit data, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R
= 5 kΩ, CL = 10 pF)
L
VA = 3 V VA = 5 V
Parameter
Symbol Min Typ Max Min Typ Max Unit
Dynamic Performance
Dynamic Range (Note 17)
unweighted
A-Weighted
40 kHz Bandwidth A-Weighted
Total Harmonic Distortion + Noise (Note 17,2)
0 dB
-20 dB
-60 dB
THD+N
97
100
-
-
-
-
102 105
99
-94
-82
-42
-
-
-
-89
-
-37
100 103
-
-
-
-
105 108 102
-94
-85
-45
-
-
-
-89
-
-40
dB dB dB
dB dB dB
Idle Channel Noise / Signal-to-Noise Ratio - 105 - - 108 - dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
Power Supplies
Power Supply Current normal operation
power-down state
I
+ I
A
IA + I
-
L
-
L
1230TBD
-
-
-
17 60
TBD-mA
µA
Power Dissipation
normal operation
power-down
Power Supply Rejection Ratio (1 kHz) (Note 3)
(60 Hz)
PSRR -
-
-
-
36
0.09
60 40
TBD
-
-
-
-
-
-
-
85
0.3
60 40
TBD-mW
mW
-
-
dB dB
Parameter Symbol Min Typ Max Units
Analog Ou tput
Full Scale Differential Output Voltage TBD 1.1VA TBD Vpp Common Mode Voltage CMOUT - 0.5VA - VDC Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C AC-Load Resistance R Load Capacitance C
L
L
5--kΩ
- - 100 pF
DS335PP4 5
CS4391
ANALOG CHARACTERISTICS (continued)
Parameter Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode
Passband (Note 3)
to -0.05 dB corner
to -3 dB corner Frequency Response 10 Hz to 20 kHz -.02 - +.035 dB StopBand .5465 - - Fs StopBand Attenuation (Note 5) 50 - - dB Group Delay tgd - 9/Fs - s Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s De-emphasis Error (Relative to 1 kHz)
Control Port Mode Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Stand-Alone Mode Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double Speed Mode
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB StopBand .577 - - Fs StopBand Attenuation (Note 5) 55 - - dB Group Delay tgd - 9/Fs - s Passband Group Delay Deviation 0 - 20 kHz - ±0.23/Fs - s
On-chip Analog Filter Response - Quad Speed Mode
Passband (Note 4)
to -3 dB corner 0 - 0.25 Fs Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB
On-chip Analog Filter Response - DSD Mode
Passband (Note 4)
to -3 dB corner 0 - 1.0 Fs Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB
Notes: 17. Triangular PDF dithered data.
18. THD+N specifications for 48 kHz sample rates are made over a 20 kHz Bandwidth.
19. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing the capacitance will also increase the PSRR.
20. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 18-25) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
21. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
0 0
-
-
-
-
-
-
0 0
-
-
-
-
-
-
-
-
-
-
.4535 .4998
+.2/-.1
+.05/-.14
+0/.22
TBD
+.05/-.14
TBD
.4621 .4982
Fs Fs
dB dB dB dB dB dB
Fs Fs
6 DS335PP4
CS4391
DIGITAL CHARACTERISTICS (T
Parameters Symbol Min Typ Max Units
High-Level Input Voltage
Low-Level Input Voltage Input Leakage Current I Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 3 - mA
= 25° C)
A
V
IH
V
IL
in
70% - - VL
- 20% VL
--±10µA
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
DC Power Supply VA
VL Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
in
IND
A
stg
-0.3
-0.3
-±10mA
-0.3 VL+0.4 V
-55 125 °C
-65 150 °C
6.0 VA
V V
RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters Symbol Min Typ Max Units
DC Power Supply VA
VL
2.7
1.8
5.0
-
5.5 VA
V V
DS335PP4 7
CS4391
SWITCHING CHARACTERISTICS - PCM MODES (T
= -10 to 70° C; VL = 5.5 to 1.8 Volts;
A
Inputs: Logic 0 = 0 V, Logic 1 = VL, CL = 20 pF)
Parameters Symbol Min Typ Max Units
Input Sample Rate Fs 4 - 200 kHz
LRCK Duty Cycle 45 50 55 %
MCLK Duty Cycle 40 50 60 %
SCLK Frequency
SCLK Frequency Note 22
SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t
slrd
slrs
sdlrs
sdh
-
-
20 - - ns
20 - - ns
20 - - ns
20 - - ns
-MCLK/2Hz
-MCLK/4Hz
Notes: 22. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
LRCK
SCLK
SDATA
t
t
slrd
t
sdlrs
slrs
t
sdh

Figure 1. Serial Mode Input Timing

8 DS335PP4
CS4391
SWITCHING CHARACTERISTICS - DSD (T
Logic 1 = VL = 5.5 to 1.8 Volts; C
=20pF)
L
= -10 to 70° C; Logic 0 = AGND = DGND;
A
Parameter Symbol Min Typ Max Unit
MCLK Duty Cycle 40 50 60 %
SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Period t
SDIN valid to SCLK rising setup time t SCLK rising to SDIN hold time t
SCLK
t
sdlrstsdh
sclkl
sclkh
sclkw
sdlrs
sdh
t
sclkl
TBD - - ns TBD - - ns
TBD
--ns
TBD - - ns TBD - - ns
t
sclkh
SDATA

Figure 2. Direct Stream Digital - Serial Audio Input Timing

DS335PP4 9
SWITCHING CHARACTERISTICS - I2C CONTROL PORT
(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)
Parameter Symbol Min Max Unit
2C®
Mode
I
SCL Clock Frequency f
RST
Rising Edge to Start t
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 23) t
SDA Setup time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
scl
irs
buf
hdst
low
high
sust
hdd
sud
r
f
susp
-100KHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
CS4391
Notes: 23. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
SDA
SCL
irs
Stop S tart
t
buf
t
hdst
t
low
t
hdd
t
high
t
sud
Repeated
Start
t
t
sust
hdst
t
f
t
r

Figure 3. I2C Control Port Timing

Stop
t
susp
10 DS335PP4
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency f
RST
Rising Edge to CS Falling t
CCLK Edge to CS
CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
Falling (Note 24) t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 25) t
Rise Time of CCLK and CDIN (Note 26) t
Fall Time of CCLK and CDIN (Note 26) t
sclk
srs
spi
csh
css
scl
sch
dsu
dh
r2
f2
-6MHz
500 - ns
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
CS4391
Notes: 24. t
25. Data must be held for sufficient time to bridge the transition time of CCLK.
26. For F
only needed before first falling edge of CS after RST rising edge. t
spi
< 1 MHz
SCK
RST
CS
CCLK
CDIN
t
srs
t
t
css
spi
t
r2
t
t
scl
t
t
f2
dsu
sch
t
dh
= 0 at all other times.
spi
t
csh

Figure 4. SPI Control Port Ti ming

DS335PP4 11

2. TYPICAL CONNECTION DIAGRAMS

10
M0 (AD0/CS)
9
M1 (SDA/
8
M2 (SCL/CCLK)
7
M3
2
VL
5
LRCK
Logic Power
+5V to 1.8V
Mode
Select
(Control Port) *
0.1 µf
17
VA
CDIN
)
CS4391
0.1 µf
FILT+
AOUTA-
AMUTEC
AOUTA+
11
19
20
18
+
1.0 µf
0.1 µf 1.0 µf
Analog
Conditioning
&
Mute
CS4391
+5V to +3V Analog
+
Audio
Data
Processor
*
External Clock

Figure 5. Typical Connection Diagram - PCM Mode

* A high logic level for all digital inputs should not exceed VL.
4
3
1
6
SCLK
SDATA
RST
MCLK
AOUTB-
BMUTEC
AOUTB+
CMOUT
AGND
16
14
13
15
12
Analog
Conditioning
&
Mute
1.0 µf
+
12 DS335PP4
Logic Power
+5V to 1.8V
Mode
Select
(Control Port)
0.1 µf
10
M0 (AD0/CS)
9
M1 (SDA/
8
M2 (SCL/CCLK)
2
VL
5
DSD_MODE
7
DSD_CLK
)
CDIN
CS4391
17
VA
FILT+
AOUTA-
AMUTEC
AOUTA+
0.1 µf
19
20
18
11
CS4391
+5V to +3V
+
1.0 µf
0.1 µf 1.0 µf
Analog
Conditioning
&
Mute
Analog
+
Audio
Data
Processor
*
4
3
DSD_B
AOUTB-
DSD_A
BMUTEC
1
6
RST
MCLK
AOUTB+
CMOUT
AGND
16
External Clock

Figure 6. Typical Connection Diagram - DSD Mode

* A high logic level for all digital inputs should not exceed VL.
14
13
15
12
Analog
Conditioning
&
Mute
1.0 µf
+
DS335PP4 13
CS4391

3. REGISTER QUICK REFERENCE

** “default” ==> bit status after power-up-sequence or reset**

3.1 MODE CONTROL 1 (ADDRESS 01H)

76543210
AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0
10000000
AMUTE (Auto-mut e)
Default = ‘1’. 0 - Disabled 1 - Enabled
DIF2, D I F 1 and DIF0 (Di gital I nterface Format - PCM Modes) . See Table 1
Default = ‘0’. 000 - Format 0, Left Justified, up to 24-bit data 001 - Format 1, I 010 - Format 2, Right Justified, 16-bit Data 011 - Format 3, Right Justified, 24-bit Data 100 - Format 4, Right Justified, 20-bit Data 101 - Format 5, Right Justified, 18-bit Data 110 - Reserved 111 - Reserved
2
S, up to 24-bit data
DIF2, D I F 1 and DIF0 (Di gital I nterface Format - DSD Mode Only ). SeeTab le 2
Default = ‘0’. 000 - Format 0, 64x oversampled DSD data with a 4x MCLK to DSD data rate 001 - Format 1, 64x oversampled DSD data with a 6x MCLK to DSD data rate 010 - Format 2, 64x oversampled DSD data with a 8x MCLK to DSD data rate 011 - Format 3, 64x oversampled DSD data with a 12x MCLK to DSD data rate 100 - Format 4, 128x oversampled DSD data with a 2x MCLK to DSD data rate 101 - Format 5, 128x oversampled DSD data with a 3x MCLK to DSD data rate 110 - Format 6, 128x oversampled DSD data with a 4x MCLK to DSD data rate 111 - Format 7, 128x oversampled DSD data with a 6x MCLK to DSD data rate
DEM1, DEM0 (De-Emphasis Mode). See Table 3
Default = ‘00’. 00 - No De-emphasis 01 - 44.1 kHz De-Emphasis 10 - 48 kHz De-Emphasis 11 - 32 kHz De-Emphasis
FM1, FM0 (F unctional M ode). See T able 4
Default = ‘00’. 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode
14 DS335PP4
CS4391

3.2 VOLUME AND MIXING CONTROL (ADDRESS 02H)

76543210
A = B Soft Zero Cross ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0
01001001
A = B (Channel A Volume = Channel B Volume)
Default = ‘0’. 0 - AOUTA volume is determined by register 03h and AOUTB volume is determined by reg­ister 04h. 1 - AOUTA and AOUTB volumes are determined by register 03h and register 04h is ig­nored.
Soft & Zero Cross (Soft control and zero cross detection control)
Default = ‘10’. SoftZero CrossMode 00 Changes take effect immediately 01 Changes take effect on zero crossings 10 Changes take effect with a soft ramp (default) 11 Changes take effect in 1/8 dB steps on each zero crossing
ATAPI 0-4 (C hannel mixing and mu ti ng). SeeTable 6
Default = ‘01001’, (Stereo) AOUTA = Left Channel AOUTB = Right Channel

3.3 CHANNEL A VOLUME CONTROL (ADDRESS 03H)

See Channel B Volume Control (address 04h)

3.4 CHANNEL B VOLUME CONTROL (ADDRESS 04H)

76543210
MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0
00000000
MUTE
Default = ‘0’ 0 - Disabled 1 - Enabled
Volume
Default = ‘0’ (Refer to Table 7)
DS335PP4 15
CS4391

3.5 MODE CONTROL 2 (ADDRESS 05H)

76543210
INVERT_A INVERT_B CPEN PDN MUTEC A = B FREEZE MCLK Divide Reserved
00110000
INVERT _A (Invert Channel A)
Default = ‘0’. 0 - Disabled 1 - Enabled
INVERT_B (Invert Channel B)
Default = ‘0’. 0 - Disabled 1 - Enabled
CPEN (Control Port Enable)
Default = ‘0’ 0 - Disabled (Stand-Alone Mode) 1 - Enabled (Control Port Mode)
PDN (Power-Down)
Default =’1’. 0 - Disabled 1 - Enabled
MUTEC A=B
FREEZE
MCLK Div ide
Default = ‘0’. 0 - Disabled 1 - Enabled
Default = 0. 0 - Disabled 1 - Enabled
Default = 0. 0 - Disabled 1 - Enabled
16 DS335PP4
CS4391

4. REGISTER DESCRIPTION

** All register access is R/W in I2C mode and write only in SPI mode **

4.1 MODE CONTROL 1 - ADDRESS 01H

76543210
AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

4.1.1 Auto-Mute (Bit 7)

Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. (However, Auto-Mute detection and muting can be­come dependent on either channel if the Mute A = B function is enabled.) The common mode on the output will be retained and the Mute Control pin for that channel will go active during the mute period. The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.

4.1.2 Digital Interface Formats (Bits 6:4)

Function:
PCM Mode - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Table 2 and Figures 7-24.
DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional Mode registers must be set to DSD Mode.
See Table 1 (PCM Modes)
See Table 2 (DSD Mode)

4.1.3 De-Emphasis Control (Bits 3:2)

Function:
Implementation of the standard 15 µs/50 µs digital de-emphasis filter response, Figure 13, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. NOTE: De-emphasis is available only in Single-Speed Mode.
See Table 3

4.1.4 Functional Mode (Bits 1:0)

Function:
Selects the required range of input sample rates or DSD Mode.
See Table 4
DS335PP4 17
CS4391

4.2 VOLUME AND MIXING CONTROL (ADDRESS 02H)

76543210
A = B Soft Zero Cross ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

4.2.1 Channel A Volume = Channel B Volume (Bit 7)

Function:
The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Vol­ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de­termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.

4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5)

Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
See Table 5

4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0)

Function:
The CS4391 implements the channel mixing functions of the ATAPI CD-ROM specification. See Table 6

4.3 CHANNEL A VOLUME CONTROL - ADDRESS 03H

See 4.4 Channel B Volume Control - Address 04h
18 DS335PP4
CS4391

4.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H

76543210
MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

4.4.1 Mute (Bit 7)

Function:
The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled.

4.4.2 Volume Control (Bits 6:0)

Function:
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -119 dB. Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings less than - 119 dB are equivalent to enabling the Mute bit.

4.5 MODE CONTROL 2 - ADDRESS 05H

76543210
INVERT_A INVERT_B CPEN PDN MUTEC A = B FREEZE MCLK Divide Reserved

4.5.1 Invert Signal Polarity (Bits 7:6)

Function:
When set, this bit inverts the signal polarity.

4.5.2 Control Port Enable (Bit 5)

Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power­up, the user should write 11h to register 5 within 10 ms following the release of Reset.

4.5.3 Power Down (Bit 4)

Function:
The device will enter a low-power state whenever this function is activated. The power-down bit de­faults to ‘enabled’ on power-up and must be disabled before normal operation will begin. The contents of the control registers are retained when the device is in power-down.

4.5.4 AMUTEC = BMUTEC (Bit 3)

Function:
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con­nected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
DS335PP4 19

4.5.5 Freeze (Bit 2)

Function:
This function allows modifications to the registers without the changes being taking effect until Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the Freeze Bit, make all register changes, then Disable the Freeze bit.

4.5.6 Master Clock Divide (Bit 1)

Function:
This function allows the user to select an internal divide by 2 of the Master Clock. This selection is required to access the higher Master Clock rates as shown in Table 9.
CS4391
20 DS335PP4

5. PIN DESCRIPTION - PCM DATA MODE

CS4391
Logic Voltage VL AOUTA- Differential Output
Left/Right Clock LRCK AGND Analog Ground
See Description M3 AOUTB- Differential Output See Description (SCL/CCLK) M2 BMUTEC Channel B Mute Control
See Description (SDA/CDIN) M1 CMOUT Common Mode Voltage See Description (AD0/CS

Reset - RST

Pin 1, Input Function:
Hardware Mode: The device enters a low power mode and the internal state machine is reset to the de­fault setting when low. When high, the device becomes operational.
Control Port Mode: The device enters a low power mode and all internal registers are reset to the default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port can not be accessed when reset is low. The Control Port Enable Bit must also be enabled after a device reset.
Reset RST
Serial Data SDATA AOUTA+ Differential Output
Serial Clock SCLK VA Analog Power
Master Clock MCLK AOUTB+ Differential Output
) M0 FILT+ Positive Voltage Reference
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13
12
11
AMUTEC Channel A Mute Control
RST
is required to remain low until the power supplies and clocks are applied and stable.

Interface Power - VL

Pin 2, Input Function:
Digital interface power supply. Typically 1.8 to 5.0 VDC. The voltage on this pin determines the logic level high threshold for the digital inputs. The voltage on VL is the maximum allowable input level for all digital inputs.

Serial Audio Data - SDATA

Pin 3, Input Function:
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or the Mode Pins in Hardware Mode. The options are detailed in Figures 7-24.
DS335PP4 21

Serial Clock - SCLK

Pin 4, Input Function:
Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or the Mode pins in Hardware Mode. The options are detailed in Figures 7-24.

Left / Right Clock - LRCK

Pin 5, Input Function:
The Left / Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or the Mode pins in Stand-alone Mode. The options are detailed in Figures 7-24.

Master Clock - MCLK

CS4391
Pin 6, Input Function:
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Sin­gle Speed Mode; either 128x, 192x 256x, 384x or 512x the input sample rate in Double Speed Mode; or 64x, 96x 128x, 192x or 256 x the input sample rate in Quad Speed Mode. Tables 8-10 illustrate the stan­dard audio sample rates and the required master clock frequencies.
Note: These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled.

Mode Select - M3, M2, M1 and M0 (Stand-alone Mode)

Pins 7, 8, 9 and 10 Inputs Function:
The Mode Select Pins, M0-M3, select the operational mode of the device as detailed in Tables 11-15.

Mode Select - M3 (Control Port Mode)

Pin 7, Input Function:
The Mode Select Pin, M3, is not used in PCM Control Port mode and should be terminated to ground.
22 DS335PP4

Serial Control Interface Clock - SCL/CCLK (Control Port Mode)

Pin 8, Input Function:
Clocks the serial control data into or from SDA/CDIN.

Serial Control Data I/O - SDA/CDIN (Control Port Mode)

Pin 9, Input/Output Function:
2
C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode.
In I
CS4391
Address Bit / Chip Select - AD0 / CS
Pin 10, Input Function:
2
In I
C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.

Positive Voltage Reference - FILT+

Pin 11, Output Function:
Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog ground, as shown in Figure 5 and 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance.

Common Mode Voltage - CMOUT

Pin 12, Output Function:
Filter connection for internal common mode reference voltage, typically 50% of VA. Capacitors must be connected from CMOUT to analog ground, as shown in Figure 56. CMOUT is not intended to supply external current. CMOUT has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance.
(Control Port Mode)

Channel A and Channel B Mute Control - AMUTEC and BMUTEC

Pins 13 and 20, Outputs Function:
The Mute Control pins go high during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. These pins are intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
DS335PP4 23

Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTA-

Pins 14, 15 and 18, 19, Outputs Function:
The full scale differential analog output level is specified in the Analog Characteristics specifications table.

Analog Ground - AGND

Pin 16, Input Function:
Analog ground reference.

Analog Power - VA

Pin 17, Input Function:
Analog power supply. Typically 3 to 5 VDC.
CS4391
24 DS335PP4

6. PIN DESCRIPTION - DSD MODE

CS4391
Reset RST
Logic Voltage VL AOUTA- Refer to PCM Mode Channel A Data DSD_A AOUTA+ Refer to PCM Mode Channel B Data DSD_B VA Refer to PCM Mode
DSD Mode Select DSD_MODE AGND Refer to PCM Mode
Master Clock MCLK AOUTB+ Refer to PCM Mode
DSD Serial Clock DSD_SCLK AOUTB- Refer to PCM Mode Refer to PCM Mode (SCL/CCLK) M2 BMUTEC Refer to PCM Mode
Refer to PCM Mode (SDA/CDIN) M1 CMOUT Refer to PCM Mode Refer to PCM Mode (AD0/CS

DSD Audio Data - DSD_A and DSD_B

Pins 3 and 4, Inputs Function:
Direct Stream Digital audio data is clocked into DSD_A and DSD_B via the DSD serial clock.

DSD Mode - DSD_Mode

Pin 5, Input
) M0 FILT+ Refer to PCM Mode
1 2 3 4 5 6 7 8 9 10
20 19 18 17
16 15 14 13
12
11
AMUTEC Refer to PCM Mode
Function:
This pin must be set to a logic ‘1’ and M0-M2 must be properly set to access the DSD Mode in Hardware Mode. Refer to Table 19.
In Control Port Mode, this pin must be set to a logic ‘1’ and the Control Registers must be properly set to access the DSD Mode. Refer to register descriptions.

Master Clock - MCLK

Pin 6, Input Function:
The master clock frequency must be either 4x, 6x, 8x or 12x the DSD data rate for 64x oversampled DSD data or 2x, 3x, 4x or 6x the DSD data rate for 128x oversampled DSD data.

DSD Serial Clock - DSD_SCLK

Pin 7, Input Function:
Clocks the individual bits of the DSD audio data into the DSD_A and DSD_B pins.
DS335PP4 25
DIF2 DIF1 DIFO DESCRIPTION
0 0 0 Left Justified, up to 24-bit data 001
0 1 0 Right Justified, 16-bit Data 0 1 1 Right Justified, 24-bit Data 1 0 0 Right Justified, 20-bit Data 1 0 1 Right Justified, 18-bit Data 1 1 0 Reserved 1 1 1 Reserved
2
S, up to 24-bit data
I

Table 1. Digital Interface Formats - PCM Modes

DIF2 DIF1 DIFO DESCRIPTION
0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate 0 0 1 64x oversampled DSD data with a 6x MCLK to DSD data rate 0 1 0 64x oversampled DSD data with a 8x MCLK to DSD data rate 0 1 1 64x oversampled DSD data with a 12x MCLK to DSD data rate 1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate 1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate 1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate 1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 2. Digital Interface Formats - DSD Mode

CS4391
DEM1 DEMO DESCRIPTION
00Disabled 0 1 44.1 kHz de-emphasis 1 0 48 kHz de-emphasis 1 1 32 kHz de-emphasis

Table 3. De-Emphasis Mode Selection

FM1 FM0 MODE
0 0 Single-Speed Mode (4 to 50 kHz sample rates) 0 1 Double-Speed Mode (50 to 100 kHz sample rates) 1 0 Quad-Speed Mode (100 to 200 kHz sample rates) 1 1 Direct Stream Digital Mode

Table 4. Functional Mode Selection

SOFT ZERO Mode
0 0 Changes to affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled

Table 5. Soft Cross or Zero Cross Mode Selection

26 DS335PP4
CS4391
ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB
00000 MUTE MUTE 00001 MUTE bR 00010 MUTE bL 00011 MUTE b[(L+R)/2] 00100 aR MUTE 00101 aR bR 00110 aR bL 00111 aR b[(L+R)/2] 01000 aL MUTE 01001 aL bR 01010 aL bL 01011 aL b[(L+R)/2] 01100 a[(L+R)/2] MUTE 01101 a[(L+R)/2] bR 01110 a[(L+R)/2] bL 01111 a[(L+R)/2] b[(L+R)/2] 10000 MUTE MUTE 10001 MUTE bR 10010 MUTE bL 10011 MUTE [(bL+aR)/2] 10100 aR MUTE 10101 aR bR 10110 aR bL 10111 aR [(aL+bR)/2] 11000 aL MUTE 11001 aL bR 11010 aL bL 11011 aL [(aL+bR)/2] 11100 [(aL+bR)/2] MUTE 11101 [(aL+bR)/2] bR 11110 [(bL+aR)/2] bL 11111 [(aL+bR)/2] [(aL+bR)/2]

Table 6. ATAPI Decode

Binary Code Decimal Value Volume Setting
0000000 0 0 dB 0010100 20 -20 dB 0101000 40 -40 dB
0111100 60 -60 dB
1011010 90 -90 dB

Table 7. Digital V olume Control

DS335PP4 27
CS4391
Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled.
Sample Rate
(kHz)
32 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520
Sample Rate
(kHz)
64 8.1920 12.2880 16.3840 24.5760 32.7680
88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520
Sample Rate
(kHz)
176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520

Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies

256x 384x 512x 768x 1024x

Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies

128x 192x 256x 384x 512x

Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies

64x 96x 128x 192x 256x
MCLK (MHz) See Note
MCLK (MHz) See Note
MCLK (MHz) See Note
M3 M1
(DIF1)
00 0 00 1
01 0 01 1

Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options

M0
(DIF0)
DESCRIPTION FORMAT FIGURE
Left Justified, up to 24-bit data
2
S, up to 24-bit data
I Right Justified, 16-bit Data Right Justified, 24-bit Data
07 18
29 310
M3 M2
(DEM)
00 01

Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options

No De-Emphasis De-Emphasis Enabled
DESCRIPTION FIGURE
13 13
M3 M2 M1 M0 DESCRIPTION FORMAT FIGURE
1000 1001
1010 1011

Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options

28 DS335PP4
Left Justified up to 24-bit data
2
S up to 24-bit data
I Right Justified 16-bit data Right Justified 24-bit data
07 18
29 310
CS4391
M3 M2 M1 M0 DESCRIPTION FORMAT FIGURE
1100 1101
1110 1111

Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options

DSD_Mode M2 M1 M0 DESCRIPTION
1000 1001 1010 1011 1100 1101 1110 1111

Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options

Left Justified up to 24-bit data
2
S up to 24-bit data
I Right Justified 16-bit data Right Justified 24-bit data
64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate
07 18
29 310
DS335PP4 29
CS4391
LRCK
SCLK
SDATA +3 +2 +1
MSB
-1 -2 -3 -4 -5
Left Channel
+5 +4

Figure 7. Format 0, Left Justified up to 24-Bit Data

LRCK
SCLK
SDATA +3 +2 +1
MSB
-1 -2 -3 -4 -5
Left Channel
+5 +4

Figure 8. Format 1, I2S up to 24-Bit Data

LSB
LSB
MSB
-1 -2 -3 -4
MSB
-1 -2 -3 -4
Right Channel
+3 +2 +1
+5 +4
Right Channel
+3 +2 +1
+5 +4
LSB
LSB
LRCK
SCLK
SDATA
LRCK
SCLK
SDATA
Left Channel
15 14 13 12 11 10
32 clocks
654321 0987
15 14 13 12 11 10
Right Channel
65432 10987

Figure 9. Format 2, Right Justified 16-Bit Data

Left Channel
0
23 22 21 20 19 18
32 clocks
65432107
23 22 21 20 19 18
Right Channel
65432107

Figure 10. Format 3, Right Justified 24-Bit Data

30 DS335PP4
CS4391
LRCK
SCLK
SDATA
LRCK
SCLK
SDATA
Left Channel
10 6543210987
10

Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)

17 16 17 16
19 18 19 18

Figure 11. Format 4, Right Justif ied 20-Bit Data. (Available in Control Port Mode only)

15 14 1 3 12 11 10
32 clocks
Left Channel
32 clocks
6543210987
654321098715 14 13 12 11 10
15 14 13 12 11 10
Right Channel
Right Channel
654321098715 14 13 12 11 1017 16 17 16
Gain
dB
T1=50 µs
0dB
Left Channel
Audio Data
Right Channel
Audio Data
T2 = 15 µs
-10dB
F1 F2
Frequency
3.183 kHz 10.61 kHz

Figure 13. De-Emphasis Curve

A Channel
Volume
Control
MUTE
Aout A
ΣΣ
B Channel
Volume
Control
MUTE
Aout B

Figure 14. ATAPI Block Diagram

DS335PP4 31
CS4391

7. APPLICATIONS

7.1 Recommended Power-up Sequence for Hardware Mode

1) Hold RST low until the power suppl ies, mast er,
and left/right clocks are stable.
2) Bring RST high.

7.2 Recommended Power-up Sequence and Access to Control Port Mode

1) Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the control port is reset to its default settings and CMOUT will remain low.
2) Bring RST high. The device will remain in a
low power state with CMOUT low and the con­trol port is accessible.
3) Write 11h to register 5 withi n 10 ms cycles fol-
lowing the release of RST.
4) The desired register settings can be loaded while keeping the PDN bit set to 1.
5) Set the PDN bit to 0 which will initiate the pow­er-up sequence which requires approximately 10 µS.

7.3 Analog Output and Filtering

The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the sec­ond-order Butterworth filter and differential to s in­gle-ended converter which was implemented on the CS4391 evaluation board, CDB4391. The CS4391 filter, as seen in Figure 14, is a line ar phas e design and does not include phase or amplitude compensa­tion for an external filter. Therefore, the DAC sys­tem phase and amplitude response will be dependent on the external analog circuitry.
AOUTA-
AOUTA+
C42
C43
10UF
10UF
AMUTEC
R24
R26
5.62K
5.62K
1
GND
C7
2700PF COG
GND
GND
C14
2700PF COG
3
Q4 MMUN2211LT1
2
R17
R18
R15
5.62K
GND
1.18K
1.18K
R28
C6
VCC
V+
2
-
3
+
C5
V-
560PF COG
VEE
GND
VA+3/+5
2
1
MMUN2111LT1 Q3
3

Figure 15. CS4391 Output Filter

5.62K
560PF COG
8
U11
MC33078D
4
C49
.1UF
R5 47K
CON_RCA_RA
1
2
GNDGND
J3
3 4
AOUTA
NC
GND
1
C48
.1UF
GND
R25
R20
560
HDR8
12
HDR1X2
Q1
2SC2878
2K
2
3
1
GND
32 DS335PP4
CS4391

8. CONTROL PORT INTERFACE

The control port is used to load all the internal set­tings of the CS4391. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interfer­ence problems, the control port pins should remain static if no operation is required.
The control port has 2 modes: SPI and I2C, with the CS4391 operating as a slave device in both modes. If I2C operation is desired, AD0/CS should be tied to VA or AGND. If the CS4391 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. The control port registers are write-only in SPI mode.

8.1 SPI Mode

In SPI mode, CS is the CS4391 chip select signal, CCLK is the control port bit cloc k, C DIN is the in­put data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK.
Figure 16 shows the operation of the control por t in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write in­dicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the r egister that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See Table 16.
The CS4391 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc­cessive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowi ng block reads or writes of successive registers.

8.2 I2C Mode

In I2C mode, SDA is a bi-directional da ta line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 3. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VA or AGND as required. The upper 6 bits of the 7-bit ad­dress field must be 001000. To communicate with the CS4391 the LSB of the chip address field, which is the first byte sent to the CS4391, should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which se­lects the register to be read or written. The MAP is then followed by the data to be written. If the op­eration is a read, the n the contents of the register pointed to by the MAP will be output after the chip address.
The CS4391 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for suc­cessive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowi ng block reads or writes of successive registers.
For more information on I2C, please see “The I2C­Bus Specification: Version 2.0”, listed in the Ref­erences section.
DS335PP4 33
CS4391
76543210
INCR Reserved Reserved Reserved Reserved MAP2 MAP1 MAP0
00000000
INCR (Auto MAP Increment Enable)
Default = ‘0’. 0 - Disabled 1 - Enabled
MAP0-2 (Memory Address Pointer)
Default = ‘000’.

Table 16. Memor y Address Poin te r ( M AP)

CS
CCLK
CDIN
CHIP
ADDRESS
0010000
R/W
MAP
MSB
byte 1
DATA
LSB
byte n
MAP = Memory Address Pointer

Figure 16. Control Port Timing, SPI mode

N ote 1
SDA
SCL
Note: If o pera tio n is a write, this byte contain s the M em ory Address Pointer, M A P .
001000
Start
ADDR AD0
R/W
ACK
DATA 1-8
ACK
DATA 1-8
ACK

Figure 17. Con trol Port Timing, I2C Mode

Stop
34 DS335PP4
0.25
0.2
0.15
0.1
0.05
0
-0.05
Amplitude dB
-0.1
-0.15
-0.2
-0.25 0 0.05 0.1 0.15 0.2 0 .25 0.3 0 .35 0.4 0.45 0.5
Frequency (normalized to Fs)

Figure 18. Single-Spee d Fre que n cy Response Figure 19. Single-Sp ee d Trans ition Band

CS4391

Figure 20. Single-Speed Transition Band Figure 21. Single-Speed Stopband Rejection

0.25
0.2
0.15
0.1
0.05
0
-0.05
Amplitu de dB
-0.1
-0.15
-0.2
-0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (normalized to Fs)

Figure 22. Double-Speed Frequency Response Figure 23. Double-Speed Transiti on Ban d

DS335PP4 35
CS4391

Figure 24. Double-Speed Transition Band Figure 25. Double-Speed Stopband Rejection

36 DS335PP4

9. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering So­ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.
CS4391

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

10.REFERENCES

1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4391 Evaluation Board Datasheet
3. “The I
2
http://www.semiconductors.philips.com
C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
DS335PP4 37

11.PACKAGE DIMENSIONS

20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
CS4391
1
23
TOP VIEW
D
E
e
2
b
SIDE VIEW
A2
A1
A
SEATING
PLANE
L
INCHES MILLIMETERS
1
E1
END VIEW
NOT
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.043 -- -- 1.10 A1 0.002 0.004 0.006 0.05 -- 0.15 A2 0.03346 0.0354 0.037 0.85 0.90 0.95
b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 D 0.252 0.256 0.259 6.40 6.50 6.60 1 E 0.248 0.2519 0.256 6.30 6.40 6.50
E1 0.169 0.1732 0.177 4.30 4.40 4.50 1
e -- -- 0.026 -- -- 0.65
L 0.020 0.024 0.028 0.50 0.60 0.70
∝
0° 4° 8° 0° 4° 8°
∝
E
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
38 DS335PP4
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