Cirrus Logic CS4385 User Manual
CS4385
114 dB, 192 kHz 8-Channel D/A Converter
Features
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Automatic Detection of Sample Rates up to
192 kHz
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital Mode
– Non-Decimating Volume Control
– On-Chip 50 kHz Filter
– Matched PCM and DSD Analog Output
Levels
Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
Selectable Digital Filters
Volume Control with 1/2-dB Step Size and Soft
Ramp
Low Clock-Jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control and Serial Ports
Control Port Supply = 1.8 V to 5 V
Digital Supply = 2.5 V
Description
The CS4385 is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
half-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma modulator which includes mismatch-shaping technology
that eliminates distortion due to capacitor mismatch.
Following this stage is a multi-element switched capacitor stage and low-pass filter with differential analog
outputs.
The CS4385 also has a proprietary DSD processor
which allows for volume control and 50 kHz on-chip filtering without an intermediate decimation stage. It also
offers an optional path for direct DSD co nver sion by directly using the multi-element switched capacitor array.
The CS4385 is available in a 48-pin LQFP package in
both Commercial (-40°C to +85°C) and Automotive
(-40°C to +105°C) grades. The CDB4385 Customer
Demonstration board is also available for device evaluation and implementation suggestions. Please see
“Ordering Information” on page 5 4 for complete details.
The CS4385 accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These fe atures are ideal for multichannel audio systems, including SACD players, A/V
receivers, digital TV’s, mixing console s, e ffe ct s pr oc es sors, sound cards, and automotive audio systems.
Analog Supply = 5 V
Hardware Mode or
2
I
C/SPI Software Mode
Control Data
Reset
Serial Audio Port
Supply = 1.8 V to 5 V
PCM Serial
Audio Input
TDM Serial
Audio Input
DSD Audio
Input
http://www.cirrus.com
Register/Hardware
Configuration
Level Translator
Volume
Controls
8
DSD Processor
-Volume control
Serial Interface
Level Translator
-50 kHz filter
Digital
Filters
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
Multi-bit ΔΣ
Modulators
Internal Voltage
Reference
Switch-Cap
DAC and
Analog Filters
External Mute
Control
8
8
2
Eight Channels
of Differential
Outputs
Mute Signals
FEB '08
DS671F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ...................................................................................................................... 6
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ..................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 8
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ............................................................. 9
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ............................................................ 10
POWER AND THERMAL CHARACTERISTICS .................................................................................. 11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...................................... 12
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) .............. 13
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE ............................................. 13
DIGITAL CHARACTERISTICS ............................................................................................................. 14
SWITCHING CHARACTERISTICS - PCM ........................................................................................... 15
SWITCHING CHARACTERISTICS - DSD ........................................................................................... 16
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ........... ... .... ... ... ... ....... ... ... ... ... 17
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................................. 18
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 21
4.1 Master Clock ................................................................................................................................... 21
4.2 Mode Select .................................................................................................................................... 22
4.3 Digital Interface Formats ................................................................................................................ 23
4.3.1 OLM #1 .................................. ....................................... ... ... ................................................... 24
4.3.2 OLM #2 .................................. ....................................... ... ... ................................................... 24
4.3.3 OLM #3 .................................. ....................................... ... ... ................................................... 25
4.3.4 OLM #4 .................................. ....................................... ... ... ................................................... 25
4.3.5 TDM ....................... ... ... ... .... ... ... ... ....................................... ... ... .... ......................................... 26
4.4 Oversampling Modes ...................................................................................................................... 26
4.5 Interpolation Filter ........................................................................................................................... 26
4.6 De-Emphasis .................................................................................................................................. 27
4.7 ATAPI Specification ........................................................................................................................ 27
4.8 Direct Stream Digital (DSD) Mode .................................................................................................. 28
4.9 Grounding and Power Supply Arrangements ................................................................. .... ... ......... 29
4.9.1 Capacitor Placement ... .......................................................................................................... 29
4.10 Analog Output and Filtering .......................................................................................................... 29
4.11 The MUTEC Outputs .................................................................................................................... 30
4.12 Recommended Power-Up Sequence ........................................................................................... 31
4.12.1 Hardware Mode ................................................................................................................... 31
4.12.2 Software Mode .................................................................................................................... 32
4.13 Recommended Procedure for Switching Operational Modes ....................................................... 32
4.14 Control Port Interface ................................................................................................................... 32
4.14.1 MAP Auto Increment ........................................................................................................... 32
4.14.2 I²C Mode ................................. ... ....................................... ... ... .... ......................................... 32
4.14.2.1 I²C Write ................................ ... ....................................... ... ... ... ................................ 33
4.14.2.2 I²C Read ..................... ....................................... ... ... ....................................... ... ...... 33
4.14.3 SPI Mode ............................................................................................................................. 34
4.14.3.1 SPI Write ............................... ... ....................................... ... ... ... ................................ 34
4.15 Memory Address Pointer (MAP) ..................... .......................................... ................................... 34
4.15.1 INCR (Auto Map Increment Enable) ....................... .... ...... ...... ....... ...... ....... ...... ....... ...... ... ... 34
4.15.2 MAP4-0 (Memory Address Pointer) .............. ... ....................................... ... ... ...................... 34
5. REGISTER QUICK REFERENCE ....................................................................................................... 35
6. REGISTER DESCRIPTION .................................................................................................................. 37
6.1 Chip Revision (address 01h) ......................................................................................................... 37
6.1.1 Part Number ID (PART) [Read Only] .................................................................................... 37
CS4385
2 DS671F2
CS4385
6.2 Mode Control 1 (address 02h) ........................................................................................................ 37
6.2.1 Control Port Enable (CPEN) .................................................................................................. 37
6.2.2 Freeze Controls (FREEZE) ................................................................................................... 37
6.2.3 PCM/DSD Selection (DSD/PCM) .......................................................................................... 38
6.2.4 DAC Pair Disable (DACx_DIS) ..............................................................................................38
6.2.5 Power Down (PDN) ..... ... .... ... ....................................... ... ... ... ....................................... ......... 38
6.3 PCM Control (address 03h) ............................................................................................................ 38
6.3.1 Digital Interface Format (DIF) ................................................................................................ 38
6.3.2 Functional Mode (FM) ........................................................................................................... 39
6.4 DSD Control (address 04h) ............................................................................................................ 39
6.4.1 DSD Mode Digital Interface Format (DSD_DIF) ........... ......... .......... .......... ......... .......... ......... 39
6.4.2 Direct DSD Conversion (DIR_DSD) ...................................................................................... 40
6.4.3 Static DSD Detect (STATIC_DSD) ........................................................................................ 40
6.4.4 Invalid DSD Detect (INVALID_DSD) ..................................................................................... 40
6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE) .................................. ... .... ... ... ... ... 40
6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ................... ... ... .... ... ... ... ... .... ... ...... ... 40
6.5 Filter Control (address 05h) ............................................................................................................ 41
6.5.1 Interpolation Filter Select (FILT_SEL) ...................................................................................41
6.6 Invert Control (address 06h) ........................................................................................................... 41
6.6.1 Invert Signal Polarity (Inv_xx) ................................................................................................ 41
6.7 Group Control (address 07h) .......................................................................................................... 41
6.7.1 Mutec Pin Control (MUTEC) .................................................................................................. 41
6.7.2 Channel A Volume = Channel B Volume (Px_A=B) .............................................................. 42
6.7.3 Single Volume Control (SNGLVOL) ...................................................................................... 42
6.8 Ramp and Mute (address 08h) .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ...... ... .... ... ... ... .... ... ... ... ... .... ... . ........ 42
6.8.1 Soft Ramp and Zero Cross CONTROL (SZC) ...................................................................... 42
6.8.2 Soft Volume Ramp-Up after Error (RMP_UP) ....................................................................... 43
6.8.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ..................................... .... ... ... ... ... 43
6.8.4 PCM Auto-Mute (PAMUTE) .................................................................................................. 43
6.8.5 DSD Auto-Mute (DAMUTE) ...................................................................................................44
6.8.6 MUTE Polarity and DETECT (MUTEP1:0) ............................................................................ 44
6.9 Mute Control (address 09h) ............................................................................................................ 44
6.9.1 Mute (MUTE_xx) ................................................................................................................... 44
6.10 Mixing Control (address 0Ah, 0Dh, 10h, 13h) ..................... ... ... ... ....... ... ... ... .... ... ... ... ... .... ... ... ... ... 45
6.10.1 De-Emphasis Control (PX_DEM1:0) .......................... ......................................................... 45
6.10.2 ATAPI Channel Mixing and Muting (ATAPI) ........................................................................ 45
6.11 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) ............................................ 46
6.11.1 Digital Volume Control (xx_VOL7:0) ................................................................................... 46
6.12 PCM Clock Mode (address 16h) .................................................................................................. 47
6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV) .......... ...................................................... 47
7. FILTER PLOTS ..................................................................................................................................... 48
8. PARAMETER DEFINITIONS ................................................................................................................ 52
9. PACKAGE DIMENSIONS ................................................................................................................... 53
10. ORDERING INFORMATION . ... ....................................... ... ... .... ...................................... ... .... ............ 54
11. REFERENCES ....................... ... ... .... ... ... ... ....................................... ... ... ............................................. 54
12. REVISION HISTORY ................................................................... ... ... ... .... ... ... ................................... 54
DS671F2 3
LIST OF FIGURES
Figure 1.Serial Audio Interface Timing ... ... ... ... ... .... ... ... ... .... ...... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 15
Figure 2.TDM Serial Audio Interface Timing ............................................................................................. 15
Figure 3.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16
Figure 4.Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode ........................... 16
Figure 5.Control Port Timing - I²C Format ....................... .... ...................................... .... ... ... ...................... 17
Figure 6.Control Port Timing - SPI Format ................................ ... .... ... ... ... ... .... ... ... ... .... ... ... ... ....... ............ 18
Figure 7.Typical Connection Diagram, Software Mode ................ ............. ............. ............. ............. .........19
Figure 8.Typical Connection Diagram, Hardware ..................................................................................... 20
Figure 9.Format 0 - Left-Justified up to 24-bit Data .................................................................................. 23
Figure 10.Format 1 - I²S up to 24-bit Data ................................... .... ... ... ... ................................................ 23
Figure 11.Format 2 - Right-Justified 16-bit Data ....................................................................................... 23
Figure 12.Format 3 - Right-Justified 24-bit Data ....................................................................................... 23
Figure 13.Format 4 - Right-Justified 20-bit Data ....................................................................................... 23
Figure 14.Format 5 - Right-Justified 18-bit Data ....................................................................................... 24
Figure 15.Format 8 - One-Line Mode 1 ..................................................................................................... 24
Figure 16.Format 9 - One-Line Mode 2 ..................................................................................................... 24
Figure 17.Format 10 - One-Line Mode 3 ................................................................................................... 25
Figure 18.Format 11 - One Line Mode 4 ................................ ... ... .... ... ... ... ................................................ 25
Figure 19.Format 12 - TDM Mode ................................ ....................................... ... ... ................................ 26
Figure 20.De-Emphasis Curve .................................. ... ... ....................................... ... .... ............................ 27
Figure 21.ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) ................................................... ............ 27
Figure 22.DSD Phase Modulation Mode Diagram .................................................................... .... ... ... ......28
Figure 23.Full-Scale Output ............................................................. ... ... ... ... .... ... ... ....... ... ... ...................... 29
Figure 24.Recommended Output Filter ..................................................................................................... 30
Figure 25.Recommended Mute Circuitry .................. ... ... .... ...... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 31
Figure 26.Control Port Timing, I²C Mode .................................................................................................. 33
Figure 27.Control Port Timing, SPI Mode ................................................................................................. 34
Figure 28.Single-Speed (fast) Stopband Rejection ................................................................................... 48
Figure 29.Single-Speed (fast) Transition Band ......................................................................................... 48
Figure 30.Single-Speed (fast) Transition Band (detail) ............................................................................. 48
Figure 31.Single-Speed (fast) Passband Ripple ....................................................................................... 48
Figure 32.Single-Speed (slow) Stopband Rejection ................................................................................. 48
Figure 33.Single-Speed (slow) Transition Band ........................................................................................ 48
Figure 34.Single-Speed (slow) Transition Band (detail) ............................................................................ 49
Figure 35.Single-Speed (slow) Passband Ripple ...................................................................................... 49
Figure 36.Double-Speed (fast) Stopband Rejection ................................................................................. 49
Figure 37.Double-Speed (fast) Transition Band ........................................................................................ 49
Figure 38.Double-Speed (fast) Transition Band (detail) ............................................................................ 49
Figure 39.Double-Speed (fast) Passband Ripple .................................................................................
Figure 40.Double-Speed (slow) Stopband Rejection ...... .... ... ... ... .... ... ...................................... .... ... ... ......50
Figure 41.Double-Speed (slow) Transition Band ................................................ ...................................... 50
Figure 42.Double-Speed (slow) Transition Band (detail) .......................................................................... 50
Figure 43.Double-Speed (slow) Passband Ripple .............................................. ... ... ................................ 50
Figure 44.Quad-Speed (fast) Stopband Rejection .... ... ... .... ... ... ... .... ... ... ... ... .... ...... ... .... ... ... ... ... .... ... ... .. . ... 50
Figure 45.Quad-Speed (fast) Transition Band ............................................. .... ... ... ... .... ... ... ... ... .... ............ 50
Figure 46.Quad-Speed (fast) Transition Band (detail) ................................. .... ... ... ... .... ............................ 51
Figure 47.Quad-Speed (fast) Passband Ripple ........................................................................................ 51
Figure 48.Quad-Speed (slow) Stopband Rejection ................................................................................... 51
Figure 49.Quad-Speed (slow) Transition Band ......................................................................................... 51
Figure 50.Quad-Speed (slow) Transition Band (detail) ............................................................................. 51
Figure 51.Quad-Speed (slow) Passband Ripple ....................................................................................... 51
CS4385
..... 49
4 DS671F2
LIST OF TABLES
Table 1. Single-Speed Mode Standard Frequencies ................................................................................21
Table 2. Double-Speed Mode Standard Frequencies ............................................................................... 21
Table 3. Quad-Speed Mode Standard Frequencies .............. ... ... .... ... ... ....................................... ... ... ......21
Table 4. PCM Digital Interface Format, Hardware Mode Options ............................................................. 22
Table 5. Mode Selection, Hardware Mode Options .................................................................................. 22
Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... 22
Table 7. Digital Interface Formats - PCM Mode ........................................................................................ 39
Table 8. Digital Interface Formats - DSD Mode ........................................................................................ 39
Table 9. ATAPI Decode Table ..................... ... ... .... ... ... ... .... ...................................... .... ... ......................... 45
Table 10. Example Digital Volume Settings .............................................................................................. 46
CS4385
DS671F2 5
1. PIN DESCRIPTION
AOUTB1+
AOUTB1-
AOUTA1-
VLS
DSDB3
DSDA3
DSDB4
DSDA4
DSDB2
48 47 46 45 44 43 42 41 40 39 38 37
DSDA2
1
DSDB1
2
DSDA1
3
4
VD
GND
5
6
MCLK
LRCK
SDIN1
SCLK
M4(TST)
SDIN2
M3(TST)
7
8
9
10
11
2
1
13 14 15 16 17 18 19 20 21 22
SDIN3
SDIN4
M2(SCL/CCLK)
CS4385
VLC
M0(AD0/CS)
M1(SDA/CDIN)
Pin Name # Pin Description
VD 4
GND
MCLK 6
LRCK 7
SDIN1
SDIN2
SDIN3
SDIN4
SCLK 9 Serial Clock (Input) - Serial clock for the serial audio interface.
VLC 18
RST
FILT+ 20
VQ 21
MUTEC1
MUTEC234
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages.
5
Ground (Input) - Ground reference. Should be connected to analog ground.
31
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Tables 1-3 illus-
trate several standard audio sample rates and the required master clock frequency.
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
8
11
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
13
14
Control Port Power (Input) - Determines the required signal level for the control port. Refer to the
Recommended Operating Conditions for appropriate voltages.
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
19
settings when low.
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be
used to bias the analog circuitry assuming there is no AC signal component and the DC current is less
than the maximum specified in the Analog Characteristics and Specifications section.
Mute Control (Output) - The Mute Control pins go high during power-u p initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are
41
intended to be used as a control for external mute circuits to prevent the clicks and pops that can
22
occur in any single supply system. The use of external mute circuits are not mandatory but may be
desired for designs requiring the absolute minimum in extraneous clicks and pops.
AOUTA1+
MUTEC1
DSD_SCLK
AOUTA2-
36
AOUTA2+
35
AOUTB2+
34
AOUTB2-
33
32
VA
GND
31
30
AOUTA3-
29
AOUTA3+
AOUTB3+
28
27
AOUTB3-
26
AOUTA4-
25
AOUTB4-
AOUTA4+
AOUTB4+
23 24
VQ
RST
FILT+
MUTEC234
CS4385
6 DS671F2
Pin Name # Pin Description
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,-
VA 32
VLS 43
39, 40
38, 37
35, 36
34, 33
29, 30
28, 27
25, 26
24, 23
Differential Analog Output (Output) - The full-scale differential analog output level is specified in the
Analog Characteristics specification table.
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended
Operating Conditions for appropriate voltages.
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
Software Mode Definitions
SCL/CCLK 15
SDA/CDIN 16
AD0/CS 17
TST 10, 12
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-
up resistor to the logic interface voltage in I²C
Serial Control Data (Input/Output) - SDA is a data I/O line in I²C Mode and requires an external pull-
up resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the
input data line for the control port interface in SPI
Address Bit 0 (I²C) / Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
select signal for SPI format.
Test (Input) - These pins are not used in Software Mode and should not be left floating (connect to
ground).
®
Mode as shown in the Typical Connection Diagram.
™
Mode.
Hardware Mode Definitions
M0
M1
M2
M3
M4
17
16
Mode Selection (Input) - Determines the operational mode of the device as detailed in
15
Tables 4 and 5.
12
10
DSD Definitions
DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4
3
2
1
48
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
47
46
45
44
CS4385
is the chip
DS671F2 7
CS4385
2. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Typ Max Units
DC Power Supply Analog power
Digital internal power
Serial data port interface power
Control port interface powe r
Ambient Operating Temperature (Power Applied)
Commercial Grade (-CQZ)
Automotive Grade (-DQZ)
VA
VD
VLS
VLC
T
A
4.75
2.37
1.71
1.71
-40
-40
5.0
2.5
5.0
5.0
5.25
2.63
5.25
5.25
-
-
+ 85
+105
V
V
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply Analog power
Digital internal power
Serial data port interface power
Control port interface powe r
Input Current Any Pin Except Supplies I
Digital Input Voltage Serial data port interface
Control port interface
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
VLS
VLC
V
V
VA
VD
in
IND-S
IND-C
op
stg
-0.3
-0.3
-0.3
-0.3
-±10mA
-0.3
-0.3
-55 125 °C
-65 150 °C
6.0
3.2
6.0
6.0
VLS+ 0.4
VLC+ 0.4
V
V
V
V
V
V
8 DS671F2
CS4385
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ)
Test Conditions (unless otherwise specified): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25°C; Full-scale 997 Hz
input sine wave
“Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
Fs = 48 kHz, 96 kHz, 192 kHz and DSD
Dynamic Range 24-bit A-weighted
Total Harmonic Distortion + Noise 24-bit
Idle Channel Noise / Signal-to-noise ratio A-weighted - 114 - dB
Interchannel Isolation (1 kHz) - 110 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°
Analog Output
Full-Scale Differential- PCM, DSD processor
Output Voltage (Note 3) Direct DSD Mode
Output Impedance Z
Max DC Current draw from an AOUT pin I
Min AC-Load Resistance R
Max Load Capacitance C
Quiescent Voltage VQ - 50% V
Max Current draw from VQ I
(Note 1); Tested under max ac-load resistance; Valid with FILT + and VQ capacitors as shown in
Parameters Symbol Min Typ Max Unit
unweighted
16-bit A-weighted
(Note 2) unweighted
0 dB
-20 dB
-60 dB
(Note 2) 16-bit 0 dB
-20 dB
-60 dB
THD+N
V
FS
OUT
OUTmax
L
L
QMAX
108
105
-
-
-
-
-
-
-
-
1.28•V
A
0.90•V
A
- 130 - Ω
-1.0-mA
-3-kΩ
- 100 - pF
-10-μA
114
111
97
94
-100
-91
-51
-94
-74
-34
1.32•V
0.94•V
-
-
-
-
-94
-
-45
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
C
A
A
A
1.36•V
0.98•V
-VDC
Vpp
A
Vpp
A
Notes:
1. One-half LSB of triangular PDF dither is added to data.
2. Performance limited by 16-bit quantization noise.
3. V
is tested under load RL and includes attenuation due to Z
FS
OUT
.
DS671F2 9
CS4385
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ)
Test Conditions (unless otherwise specified): VA = 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1.71 to 5.25 V;
VD = 2.37 to 2.63 V; T
resistance
; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measure-
ment Bandwidth 10 Hz to 20 kHz.
Fs = 48 kHz, 96 kHz, 192 kHz and DSD
Dynamic Range (Note 1) 24-bit A-weighted
Total Harmonic Distortion + Noise (Note 1)
Idle Channel Noise / Signal-to-noise ratio A-weighted - 114 - dB
Interchannel Isolation (1 kHz) - 110 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Analog Output
Full-Scale Differential- PCM, DSD processor
Output Voltage (Note 3) Direct DSD Mode
Output Impedance Z
Max DC Current draw from an AOUT pin I
Min AC-Load Resistance R
Max Load Capacitance C
Quiescent Voltage VQ - 50% V
Max Current draw from VQ I
= -40°C to 85°C; Full-scale 997 Hz input sine wave (Note 1); Tested under max ac-load
A
Parameters Symbol Min Typ Max Units
unweighted
16-bit A-weighted
(Note 2) unweighted
24-bit 0 dB
-20 dB
-60 dB
(Note 2) 16-bit 0 dB
-20 dB
-60 dB
THD+N
V
FS
OUT
OUTmax
L
L
QMAX
105
102
-
-
-
-
-
-
-
-
1.28•V
A
0.90•V
A
-130-Ω
-1.0-mA
-3-kΩ
-100-pF
-10-μA
114
111
97
94
-100
-91
-51
-94
-74
-34
1.32•V
0.94•V
-
-
-
-
-91
-
-42
-
-
-
1.36•V
A
A
A
A
0.98•V
A
-VDC
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
Vpp
10 DS671F2
POWER AND THERMAL CHARACTERISTICS
Parameters Symbol Min Typ Max Units
Power Supplies
Power Supply Current normal operation, VA= 5 V
(Note 4) VD= 2.5 V
(Note 5) Interface current, VLC=5 V
VLS=5 V
(Note 6) power-down state (all supplies)
Power Dissipation (Note 4) VA = 5V, VD = 2.5V
normal operation
(Note 6) power-down
Package Thermal Resistance multi-layer
dual-layer
Power Supply Rejection Ratio (Note 7) (1 kHz)
(60 Hz)
Notes:
4. Current consumption increases with increasing Fs within a given spee d mode and is signal depend ent.
Max values are based on highest Fs and highest MCLK.
5. I
6. Power-Down Mode is defined as RST
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 7 and 8.
measured with no external loading on the SDA pin.
LC
pin = Low with all clock and data lines held static.
I
A
I
D
I
LC
I
LS
I
pd
θ
JA
θ
JA
θ
JC
PSRR
CS4385
-
-
-
-
-
-
-
-
-
-
-
-
84
20
2
75
200
470
1
48
65
15
60
40
91
25
-
-
-
520
-
-
-
-
-
-
mA
mA
μA
μA
μA
mW
mW
°C/Watt
°C/Watt
°C/Watt
dB
dB
DS671F2 11
CS4385
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been norma lized to th e sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.
Parameter
Combined Digital and On-chip Analog Filter Response - Single -Speed Mode - 48 kHz
Passband (Note 9) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand 0.547 - - Fs
StopBand Attenuation (Note 10) 102 - - dB
Group Delay - 10.4/Fs - s
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Combined Digital and On-chip Analog Filter Response - Double- Speed Mode - 96 kHz
Passband (Note 9) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 10) 80 - - dB
Group Delay - 6.15/Fs - s
Combined Digital and On-chip Analog Filter Response - Quad-Sp eed Mode - 192 kHz
Passband (Note 9) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .635 - - Fs
StopBand Attenuation (Note 10) 90 - - dB
Group Delay - 7.1/Fs - s
See Note 12.
to -3 dB corner
Fs = 48 kHz
to -3 dB corner
to -3 dB corner
Fast Roll-Off
Min Typ Max
0
0
-
-
-
0
0
0
0
-
-
-
-
-
-
-
-
-
.454
.499
±0.36
±0.21
±0.14
.430
.499
.105
.490
Unit
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
Notes:
8. Slow roll-off interpolation filter is only available in Software Mode.
9. Response is clock-dependent and will scale with Fs.
10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode; only 44.1 kHz De-emphasis is available in Hardware Mode.
12. Amplitude vs. Frequency plots of this data are available in Section 7. “Filter Plots” on page 48.
12 DS671F2
CS4385
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED)
Parameter
Single-Speed Mode - 48 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 10) 64 - - dB
Group Delay - 7.8/Fs - s
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
Double-Speed Mode - 96 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .792 - - Fs
StopBand Attenuation (Note 10) 70 - - dB
Group Delay - 5.4/Fs - s
Quad-Speed Mode - 192 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .868 - - Fs
StopBand Attenuation (Note 10) 75 - - dB
Group Delay - 6.6/Fs - s
Slow Roll-Off (Note 8)
Min Typ Max
0
0
-
-
-
0
0
0
0
-
-
-
-
-
-
-
-
-
0.417
0.499
±0.36
±0.21
±0.14
.296
.499
.104
.481
Unit
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
Parameter Min Typ Max Unit
DSD Processor Mode
Passband (Note 9) to -3 dB corner 0 - 50 kHz
Frequency Response 10 Hz to 20 kHz -0.05 - +0.05 dB
Roll-off 27 - - dB/Oct
Direct DSD Mode
Passband (Note 9) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB
DS671F2 13
0
0
-
-
26.9
176.4
kHz
kHz
CS4385
DIGITAL CHARACTERISTICS
Parameters Symbol Min Typ Max Units
Input Leakage Current (Note 13) I
in
Input Capacitance - 8 - pF
High-Level Input Voltage Serial I/O
Control I/O
Low-Level Input Voltage Serial I/O
Control I/O
Low-Level Output Voltage (I
Low-Level Output Voltage (I
= -1.2 mA) Control I/O = 3.3 V, 5 V V
OL
= -1.2 mA) Control I/O = 1.8 V, 2.5 V V
OL
MUTEC auto detect input high voltage V
MUTEC auto detect input low voltage V
Maximum MUTEC Drive Current I
MUTEC High-Level Output Voltage V
MUTEC Low-Level Output Voltage V
V
V
V
V
max
OH
OL
IH
IH
IL
IL
OL
OL
IH
IL
Notes:
13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latchup.
--±10μA
0.70•V
LS
0.70•V
LC
-
-
- - 0.20•V
- - 0.25•V
0.70•V
A
- - 0.30•V
-
-
-
-
-
-
0.30•V
0.30•V
LS
LC
LC
LC
--V
A
-3-mA
-VA-V
-0-V
V
V
V
V
V
V
V
14 DS671F2
CS4385
SWITCHING CHARACTERISTICS - PCM
Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF.
Parameters Symbol Min Max Units
RST pin Low Pulse Width (Note 14) 1-ms
MCLK Frequency 1.024 55.2 MHz
MCLK Duty Cycle (Note 15) 45 55 %
Input Sample Rate - LRCK (Manual selection) Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Input Sample Rate - LRCK (Auto detect) Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
LRCK Duty Cycle (Note 16) 45 55 %
SCLK Duty Cycle 45 55 %
SCLK High Time t
SCLK Low Time t
LRCK Edge to SCLK Rising Edge t
SCLK Rising Edge to LRCK Falling Edge t
TDM LRCK hightime pulse (Note 17 ) t
SDIN Setup Time Before SCLK Rising Edge t
SDIN Hold Time After SCLK Rising Edge t
F
F
F
Fs
Fs
Fs
sckh
sckl
lcks
lckd
lpw
ds
dh
s
s
s
4
50
100
4
84
170
54
108
216
54
108
216
kHz
kHz
kHz
kHz
kHz
kHz
8-ns
8-ns
5-ns
5-ns
1/f
SCLK
7/f
SCLK
ns
3-ns
5-ns
Notes:
14. After powering up, RST
should be held low until after the power supplies and clocks are settled.
15. See Tables 1 - 3 for suggested MCLK frequencies.
16. Not valid for TDM Mode.
17. MSB of CH1 is always the second SCLK rising edge following LRCK rising edge.
LRCK
SCLK
SDINx
LRCK
SCLK
SDIN1
t
lcks
t
sckh
t
t
ds
dh
MSB
Figure 1. Serial Audio Interface Timing
t
lpw
t
lcks
t
sckh
t
sckl
t
ds
t
sckl
MSB-1
t
lckd
MSB MSB-1
t
lcks
t
dh
Figure 2. TDM Serial Audio Interface Timing
DS671F2 15
CS4385
SWITCHING CHARACTERISTICS - DSD
Logic 0 = GND; Logic 1 = VLS; CL=20pF.
Parameter Symbol Min Typ Max Unit
MCLK Duty Cycle 40 - 60 %
DSD_SCLK Pulse Width Low t
DSD_SCLK Pulse Width High t
DSD_SCLK Frequency (64x Oversampled)
(128x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup time t
DSD_SCLK rising to DSD_A or DSD_B hold time t
DSD clock to data transition (Phase Modulation Mode) t
DSD_SCLK
sclkl
sclkh
sdlrs
sdh
dpm
t
160 - - ns
160 - - ns
1.024
2.048
20 - - ns
20 - - ns
-20 - 20 ns
t
sclkh
-
-
sclkl
3.2
6.4
MHz
MHz
sdlrstsdh
t
DSDxx
Figure 3. Direct Stream Digital - Serial Audio Input Timing
t
dpm
DSD_SCLK
(128Fs)
DSD_SCLK
(64Fs)
DSDxx
Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode
t
dpm
16 DS671F2
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = GND, Logic 1 = VLC, CL=20pF.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Rising Edge to Start t
RST
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 18) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
Notes:
18. Data must be held for sufficient time to bridge the transition time, t
scl
buf
hdst
low
high
sust
hdd
sud
rc
fc
susp
ack
irs
, t
rc
, t
fc
- 100 kHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
-300ns
4.7 - µs
300 1000 ns
, of SCL.
fc
CS4385
RST
SDA
SCL
t
irs
Stop Start
t
buf
t
hdst
t
t
high
low
t
hdd
Figure 5. Control Port Timing - I²C Format
t
sud
Repeated
Start
t
t
sust
hdst
Stop
t
f
t
r
t
susp
DS671F2 17
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