Cirrus Logic CS4341A-KS, CDB4341A Datasheet

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CS4341A

24-Bit, 192 kHz Stereo DAC with Volume Co ntro l

Features



101 dB Dynamic Range



-91 dB THD+N



+3.3 V or +5 V Power Supply



50 mW with 3. 3V supply



Low Clock Jitter Sensitivity



Filtered Line Level Outputs



On-Chip Digital De-emphasis for 32, 44.1, and 48 kHz



ATAPI Mixing



Digital Volume Control with Soft Ramp

– 94 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions



Up to 200 kHz Sample Rates



Automatic Mode Detection for Samp le Rates between 4 and 2 0 0kHz



Pin Compatible with the CS4341

Description

The CS4341A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter.

The CS4341A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, operates over a wide power supply range and is pin compatible with the CS4341, as described in section 3.1. These features are ideal for DVD audio players.

ORDERING INFORMATION

CS4341A-KS 16-pin SOIC, -10 to 70 °C CDB4341A Evaluation Board

RST

SCLK

LRCK

SDIN

SCL/CCLK MUTECAD0/C S

Inte r fa c e

Serial Audio

SDA/CDIN

Control Port

Interface

Preliminary Product Information

Cirrus Logic, Inc.

P.O. Box 17847, Austin, Texas 78760 http://www.cirrus.com

External

Mute Control

Volume Contro lInterpolation Filter Analog Filter

Mixer

Volume Contro lInterpola t ion Filte r ∆Σ

÷2

MCLK

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

∆Σ

DAC

Analog Filter

AOU TA

AOUT B

DS582PP1

AUG ‘02

CS4341A

1. PIN DESCRIPT IO N ....... ................ ........................ ........................ ....................... .....................5

2. TYPICAL CONNECTION DIAGRAM ............................................ .. ..... ..... .. ..... .. ..... .. ..... ... .... ..6

3. APPLICATIONS ................................... ........................ ........................ .....................................7

3.1 Upgrading from the CS4341 t o the CS4341A ....................................................................7

3.2 Sample Rate Range/Operational Mode Detect ..................................................................7

3.2.1 Auto-Detect Enabled .............................................................................................7

3.2.2 Auto-Detect Disabled ............................................................................................7

3.3 System Clocking ................................................................................................................ 8

3.4 Digital Interface Format ......................................................................................................8

3.5 De-Em phasis Control ... .. ...................... .. .. ...................... .. .. ...................... .. .. ......................9

3.6 Recommended Power-up S equenc e .................................................................................9

3.7 Popguard

3.7.1 Power-up .............................................................................................................10

3.7.2 Power-down ........................................................................................................10

3.7.3 Discharge Time ...................................................................................................10

3.8 Grounding and Powe r Supply Arrangements ..................................................................10

3.9 Control Port Interface .......................................................................................................11

3.9.1 MAP Auto Increment ...........................................................................................11

3.9.2 I2C Mode . . ...........................................................................................................11

3.9.3 SPI Mode ............................................................................................................13

3.10 Memory Address Pointer (MAP) ..............................................................................14

3.10.1 INCR (Auto Map Increment Enable) ..... ..... .. .......... .. ..... .. ....... ..... ..... .. ....... ..... .. ..... ..... ..14

3.10.2 MAP (Memory Address Pointer)..................................................................................14

Transient Control ...........................................................................................10

3.9.2a I2C Write ..............................................................................................11

3.9.2b I2C Read ..............................................................................................12

3.9.3a SPI Write ..............................................................................................13

4. REGISTER QUICK REFERENCE ............ ........................ ........................ ....................... .......14

Contacting Cirrus Logic Support

F or a co mp lete listing of Direct S a le s, D is tribu tor, a n d Sale s R e p res e n tativ e co n ta cts , vis it the C irru s Lo g ic w e b site a t:

http://www .cirrus.com /corpo rate/contacts /sales.cfm

IMPORTANT NOTICE "Preliminary" product information describes prod u cts that are in pr oduction, but for wh ic h full c hara c terization data is not yet available. "Advance" product infor-

mation describes products that are in development and subject t o development changes. Ci r r u s Logic, In c . an d i ts su b sid ia r i es ("C i rru s ") b elie ve th a t the information contained in thi s document is accurate and reli able. However, the infor mation is subj ect to change without noti ce and is provi ded "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the l atest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products a re sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibili ty i s assume d by Cirrus for the use of this information, including use of this information as the basis f or manufacture or sale of any items, or for infringement of patents or other rights of third par t ies. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, ma sk w or k rights, copyrights, trademarks, trade secrets or other intellect ual property rights. Cirrus owns the copyright s of the information contained herei n and gives consent for copies to be made of the information only for use within your organizati on with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorit ies of the Japanese Government if any of the products or technolog i e s de sc r ib e d in t h i s ma terial and control l ed under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorit i es of the Chinese Government if any of the products or technologi es descri bed in this material is s ubject to the PRC Foreign Trade Law and is to be exported or taken out of t he PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LI FE-SUPPORT DEVICES O R SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Purchase of I those components in a standard I

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and pr oduct names in this docume nt may be trademarks or service marks of their respective owners.

C components of Cirrus Logi c, Inc., or one of its sublicensed Associated Companies co nveys a license under th e Phillips I2C Patent Rights to use

C system.

2 DS582PP1

CS4341A

5. REGISTER DESCRIPTION ........................... ........................ ....................... ........................ ..15

5.1 Mode Control 1 (address 00h).......................................................................................... 15

5.2 Mode Control 2 (address 01h).......................................................................................... 15

5.3 Tr ansition and Mixing Control (address 02h).................................................................... 17

5.4 Channel A Volume Control (address 03h)........................................................................ 20

5.5 Channel B Volume Control (address 04h)........................................................................ 20

6. CHARACTERISTICS AND SPECIFICATIONS ......................................................................21

ANALOG CHARACTERISTICS (CS4341A -KS)..................................................................... 21

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................23

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ..........................................26

SWITCHING SPECIFICA TIO NS - CONTROL PORT INT ERFA CE......... ................ .............. 27

SWITCHING SPECIFICA TIO NS - CONTROL PORT INT ERFA CE......... ................ .............. 28

DC ELECTRICAL CHARACTERISTICS................................................................................29

DIGITAL INPUT CHARACTERISTICS...................................................................................29

DIGITAL INTERFACE SPECIFICATIONS.............................................................................29

THERMAL CHARACTERISTICS AND SPECIFICATIONS....................................................29

RECOMMENDED OPERATING SPECIFICATION .............................................................. 30

ABSOLUTE MAXIMUM RATINGS......................................................................................... 30

7. PARAMETER DEFI NITIONS ....................... ....................... ................. ....................... ............ 31

Total Harmonic Distortion + Noise (THD+N).......................................................................... 31

Dynamic Range ......................................................................................................................31

Interchannel Isolation ............................................................................................... ..............31

Interchannel Gain Mismatch................................................................................................. ..31

Gain Error...............................................................................................................................31

Gain Drift................................................................................................................................ 31

8. REFERENC ES ..................................... ........................ ........................ ................................... 31

9. PACKAGE DIMENSI O NS ... ................ ............................... ........................ ............................ 32

LIST OF FIGURES

Figure 1. Typical Connection Diagram .......................................................................................... 6

Figure 2. I

Figure 3. Left Justified up to 24-Bit Data ....................................................................................... 9

Figure 4. Right Justified Data ........................................................................................................ 9

Figure 5. De-Emphasis Curve ....................................................................................................... 9

Figure 6. Control Port Timing, I2C Mode .................................................................................... 12

Figure 7. Control Port Timing, SPI mode .............................. .. ....... ....... ..... ....... ....... ....... ..... .......13

Figure 8. ATAPI Block Diagram ..................................................................................................19

Figure 9. Output Test Load ......................................................................................................... 22

Figure 10. Maximum Loading ........................................................................................................ 22

Figure 11. Single-Speed Stopband Rejection ............................................................................... 24

Figure 12. Single-Speed Transition Band ..................................................................................... 24

Figure 13. Single-Speed Transition Band (Detail) ......................................................................... 24

Figure 14. Single-Speed Passband Ripple ...................................................................................24

Figure 15. Double-Speed Stopband Rejection .............................................................................. 24

Figure 16. Double-Speed Transition Ban d .................................................................................... 24

Figure 17. Double-Speed Transition Ban d (Detail) ....................................................................... 25

Figure 18. Double-Speed Passband Ripple .................................................................................. 25

Figure 19. Serial Input Timing ....................................................................................................... 26

Figure 20. Control Port Timing - I2C Mode ...................................................................................27

Figure 21. Control Port Timing - SPI Mode ................................................................................... 28

S Data .........................................................................................................................8

DS582PP1 3

LIST OF TABLES

Table 1. CS4341A Auto-Detect .......................................................................................................... 7

Table 2. CS4341A Mode Select .........................................................................................................7

Table 3. Single-Speed Mode Standard Frequencies..........................................................................8

Table 4. Double-Speed Mode Standard Frequencies........................................................................8

Table 5. Quad- Speed Mode Standard Frequencies ...........................................................................8

Table 7. ATAPI Decode....................................................................................................................18

Table 8. Example Digital Volume Settings .......................................................................................20

CS4341A

4 DS582PP1

1. PIN DESCRIPTION

RST MUTEC

SDIN AOUTA

161 152

CS4341A

SCLK VA

LRCK AGND

MCLK AOUTB

SCL/CCLK REF_GND

SDA/CDIN VQ

AD0/CS

Pin Name # Pin Description

RST SDIN SCLK LRCK

MCLK SCL/CCLK SDA/CDIN

AD0/CS

FILT+

VQ REF_GND AOUTR

AOUTL AGND

MUTEC

Reset (Input) - Powers down device when enabled.

Serial Audio Data (Input) - Input for two’s complement serial audio data.

Serial Clock (Input) -Serial cloc k f or the serial audio interface.

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the

serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

Serial Control Port Clock (Input) - Serial clock for the control port interface.

6 7

Serial Control Data I/O Address Bit / Chip Select (Input) - Chip address bit in I

the chip in SPI mode. Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir-

cuits. Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

Reference Ground (Input) - Ground reference for the internal sampling ci rc uits.

Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac-

teristics table.

Analog Ground (Input) - Ground reference.

Power (Input) - Positive power for the analog, digital, control port interfa ce, and serial audio

interface sections. Mute Control (Output) - Control signal for optional mute circuit.

143 134 125 116 107

(Input/Output)

FILT+

- Input/Output for I2C data. Input for SPI data.

C Mode. Control signal used to select

DS582PP1 5

2. TYPICAL CONNECTION DIAGRAM

CS4341A

Serial Audio

Data

Processor

ExternalC lock

Micro-

Controlled

Configuration

8 1

SDIN

SCLK

LRCK

CS4341A

MCLK

SCL/CC LK

SDA/C DIN

AD0/CS

RST

AGND

0.1 µF

AO UT A

MUTEC

FILT+

REF_GND

AO UT B

3.3 µF

10 k

.1 µF

3.3 µF

10 k

1µF

560

1µF

560

+3.3V or +5.0V

Ω

1µF

0.1 µF

Ω

OPTIONAL

MUTE

CIRCUIT

R 560

Fs(R

560 )

Audio

Output A

Audio

O utput B

Ω

Figure 1. Typical Connection Diagram

6 DS582PP1

CS4341A

3. APPLICATIONS

3.1 Upgrading from the CS4341 to the CS4341A

The CS4341A is pin and functionally compatible with all CS4341 designs, operating at the standard audio sample rates, that use pin 3 as a serial clock input. In addition to the features of the CS4341, the CS4341A supports standard sample rates up to 192 kHz, as well as automatic mode detection for sample rates between 4 and 200 kHz. The automatic speed mode detection feature allows sample rate changes between single, double and quad-speed modes without external intervention.

The CS4341A does not support an internal serial clock mode or sample rates between 50 kHz and 84 kHz (unless otherwise stated), as does the CS4341.

3.2 Sample Rate Range/Operational Mode Detect

The device operates in one of three operational modes. The allowed sample rate range in each mode will depend on whether the Auto-Detect Defeat bit is enabled/disabled.

3.2.1 Auto-Detect Enabled

The Auto-Detect feature is enable d by default in the control port register 5.1. In this state, the CS4341A will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for each mode are not supported.

Input Sample Rate (FS)MODE

4kHz - 50kHz Single Speed Mode 84kHz - 100kHz Double Speed Mode 170kHz - 200kHz Quad Speed M ode

Table 1. CS4341A Auto-Detect

3.2.2 Auto-Detect Disabled

The Auto-Detect feature can be defeated via the control port register 5.1. In this state, the CS4341A will not auto-detect the correct mode based on the input sample rate (Fs). The operational mode must be set appropriately if Fs falls within one of the ranges illustrated in Table 2. Please refer to section 5.1.1 for implementation details. Sample rates outside the specified range for each mode are not supported.

MC1 MC0 Input Sample Rate (FS)MODE

0 0 4kHz - 50kHz Single Speed Mode 0 1 50kHz - 100kHz Double Speed Mode 1 0 100kHz - 200kHz Quad Speed Mode

Table 2. CS4341A Mode Select

DS582PP1 7

CS4341A

3.3 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The s pecified ratios of MCLK to LRCK for each Speed Mode, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.

Sample Rate

(kHz)

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520

256x 384x 512x 768x 1024x*

MCLK (MHz)

Table 3. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz)

64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520

128x 192x 256x 384x 512x*

MCLK (MHz)

Table 4. Double-Speed Mode Standard Frequencies

Sample Rate

(kHz)

176.4 22.5792 33.8688 45.1584 192 24.5760 36.8640 49.1520

128x 192x 256x*

MCLK (MHz)

Table 5. Quad-Speed Mode Standard Frequencies

* Requires MCLKDIV bit = 1 in the Mode Control 1 register (address 00h).

3.4 Digital Interface Format

The device will accept audio samples in several digital interface formats. The desired format is selected via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.2.2) . For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 2-4.

LRCK

SCLK

SDIN +3 +2 +1+5 +4

MSB

-1 -2 -3 -4 -5

Left Channel

LSB

MSB

-1 -2 -3 -4

Figure 2. I2S Data

8 DS582PP1

Right Channel

+3 +2 +1+5 +4

LSB

CS4341A

LRCK

SCLK

SDIN +3 +2 +1+5 +4

MSB

-1 -2 -3 -4 -5

Left Channel

LSB

MSB

-1 -2 -3 -4

Right Channel

+3 +2 +1+5 +4

LSB

Figure 3. Left Justified up to 24-Bit Data

LRCK

SCLK

SDIN

MSB

Left Channel

LSB MSB

32 clocks

-6 -5 -4 -3 -2 -1-7+1 +2 +3 +4 +5

Figure 4. Right Justified Data

LSB -6 -5 -4 -3 -2 -1-7 MSB

Right Channel

+1 +2 +3 +4

3.5 De-Emphasis Control

The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48 kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for Fs equa l to 44 .1 kH z. Th e fre que ncy response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 5.2.3 for the desired de-emphasis control.

NOTE: De-emphasis is only available in Single-Speed Mode.

Gain

T1=50 µs

0dB

-1 0d B

3.18 3 kHz 10 .61 kH z

Figure 5. De-Emphasis Curve

3.6 Recommended Power-up Sequence

1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequences, as discussed in section 3.2. In this state, the control port is reset to its default settings and VQ will remain low.

2. Bring RST high. The device will remain in a low power s tate with VQ low.

3. Load the desired register settings while keeping the PDN bit set to 1.

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximatel y 50µS when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description of power-up timing.

F1 F2

T2 = 15 µs

Frequency

DS582PP1 9

CS4341A

3.7 Popguard® Transient Control

The CS4341A uses Popguard® technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the PDN bit or the RST pin is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.

3.7.1 Power-up

When the device is initially powered-up, the audio outputs, AOUTL a nd AOU TR, are clampe d to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time f or the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.

3.7.2 Power-down

To prevent transients at power-down, the device must first enter its power-down state by enabling RST or PDN. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.

3.7.3 Discharge Time

To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is rela ted to the value of the DC -blocking capacitance. For example, with a 3.3 µ F capacitor, the minimum power-down time will be approximately 0.4 seconds.

3.8 Grounding and Power Supply Arrangements

As with any high resolution converter, the CS4341A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane.

Decoupling capacitors should be as clos e to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimze impedance, these capacitors should be located on the same layer as the DAC.

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0. 1µF, must be positioned to minimize the electrical path from FILT+ to REF_GND (and VQ to REF_GND), and should also be located on the same layer as the DAC. The CDB4341A evaluation board demonstrates the optimum layout and power supply arrangements.

10 DS582PP1

CS4341A

3.9 Control Port Interface

The control port is used to load all the internal register settings (see section 5). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.

The control port operates in one of two modes: I2C or SPI.

Notes: MCLK must be appli e d during all I2C communication.

3.9.1 MAP Auto Increment

The device has MAP (memory address pointer) auto increment capabi lity enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.

3.9.2 I2C Mode

In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 6 for the clock to data relationship). There is no CS pin. Pin AD0 e nables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VA or GND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected.

3.9.2a I2C Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 7.

1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit.

2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written.

3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP.

4) If the INCR bit (see section 3.9.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step

1. If no further writes to other registers are desired, initiate a STOP condition to the bus.

DS582PP1 11

CS4341A

3.9.2b I2C Read

To read from the device, follow the procedure below while adher ing to the control port Switching Specifications.

1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit.

2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the la st register written to the MAP, or the default address (see section 8.3) if an I2C read is the first operation performed on the device.

3) Once the device has transmitted the contents of the register pointed to by t he MAP, issue an ACK.

4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step

1. If no further reads from other registers are desired, initi ate a STOP condition to the bus.

NOTE

SDA

SCL

NOT E : If operation is a write, this byte co ntains the Memory A ddress Pointer, MAP. If

operation is a read, this byte contains the data of the register pointed to by the MAP.

001000

Start

AD0

R/W

ACK

DATA 1-8

Figure 6. Control Port Timing, I2C Mode

ACK

DATA 1-8

ACK

Stop

12 DS582PP1

CS4341A

3.9.3 SPI Mode

In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 7 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power -up, SP I mode w ill be select ed. All signals ar e inputs and data is clocked in on the rising edge of CCLK.

3.9.3a SPI Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 6.

1) Bring CS low.

2) The address byte on the CDIN pin must then be 00100000.

3) Write to the memory address pointer, MAP. This byte points to the register to be written.

4) Write the desired data to the register pointed to by the MAP.

5) If the INCR bit (see section 3.9.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high.

6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high.

CCLK

CHIP

ADDRESS

CDIN

Figure 7. Control Port Timing, SPI mode

001000 0

MAP = Memory Address Pointer

R/W

MAP

MSB

by te 1

DATA

LSB

byte n

DS582PP1 13

CS4341A

3.10 Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved Reserved MAP2 MAP1 MAP0

00000000

3.10.1 INCR (AUTO MAP INCREMENT ENABLE)

Default = ‘0’

0 - Disabled 1 - Enabled

3.10.2 MAP (MEMORY ADDRESS POINTER)

Default = ‘000’

4. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

0h Mode Control 1 Reserved MC1 MC0 Reserved Reserved AUTOD MCLKDIV Reserved

DEFAULT

1h Mode Control 2 AMUTE DIF2 DIF1 DIF0 DEM1 DEM1 POR PDN

DEFAULT 10000011

2h Tra nsiti on and Mixin g

Control

DEFAULT 00000000

3h Channel A Volume

Control

DEFAULT 00000000

4h Channel B Volume

Control

DEFAULT 00000000

00000000

A = B SOFT ZER O

CROSS

MUTEA VOLA6 VOLA5 VOLA4 VOLA3 VOLA2 VOLA1 VOLA0

MUTEB VOLB6 VOLB5 VOLB4 VOLB3 VOLB2 VOLB1 VOLB0

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

14 DS582PP1

CS4341A

5. REGISTER DESCRIPTION

NOTE: All registers are read/write in I2C mode and write only in SPI mode, unles s otherwise state d.

5.1 MODE CONTROL 1 (ADDRESS 00H)

76543210

Reserved MC1 MC0 Reserved Reserved AUTOD MCLKDIV Reserved

00000000

5.1.1 SPEED MODE CONTROL (MC)

Default = 00

00 - Single-Speed Mode 01 - Double-Speed Mode 10 - Quad-Speed Mode

The operational speed mode must be set if the auto-detect defeat bit is enabled (AUTOD = 1). These bits are ignored if the auto-detect defeat is disabled (AUTOD = 0).

5.1.2 AUTO-DETECT DEFEAT (AUTOD)

Default = 0

0 - Disabled 1 - Enabled

The Auto -De tec t f unction can be defeated to allow sample rate changes from 50 to 84 kHz, and from 100 to 170 kHz. The operational speed mode must be set via the speed mode control bits (see section

5.1.1) if the auto-detect feature is defeated.

5.1.3 MCLK DIVIDE-BY-2 (MCLKDIV)

Default = 0

0 - Disabled 1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divide s the ext ernally applied MCLK signal by 2.

BIT 5-6

BIT 1

BIT 2

5.2 MODE CONTROL 2 (ADDRESS 01H)

76543210

AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 POR PDN

10000011

DS582PP1 15

CS4341A

5.2.1 AUTO-MUTE (AMUTE)

BIT 7

Default = 1

0 - Disabled 1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similiar to volume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register.

5.2.2 DIGITAL INTERFACE FORMAT (DIF)

Default = 000 - Format 0 (I

S, up to 24-bit data)

BIT 4-6

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 2-4.

DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

000I 0 0 1 Identical to Format 1 1 2 0 1 0 Left Justified, up to 24-bit data, 2 3 0 1 1 Right Justified, 24-bit data 3 4 1 0 0 Right Justified, 20-bit data 4 4 1 0 1 Right Justified, 16-bit data 5 4 1 1 0 Right Justified, 18-bit data 6 4 1 1 1 Identical to Format 1 1 2

S, up to 24-bit data 1 2

Tabl e 6 . Digital Interface Form a t

5.2.3 DE-EMPHASIS CONTROL (DEM)

BIT 2-3

Default = 00

00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz

Function:

Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 5, requires reconfiguration of the digital filte r to mainta in t he prope r filter response for 32, 44.1 or 48 kHz sample rates.

NOTE: De-emphasis is only available in Single-Speed M ode.

16 DS582PP1

CS4341A

5.2.4 POPGUARD® TRANSIENT CONTROL (POR)

Default = 1

0 - Disabled 1 - Enabled

Function:

The PopGuard the quiescent voltage during power-on or power-down. Please refer to section 3.7 for implementation details.

5.2.5 POWER DOWN (P DN)

Default = 1

0 - Disabled 1 - Enabled

Function:

The device will enter a low-power state when this function is enabled. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur. The contents of the control registers are retained in this mode.

Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to

BIT 0

BIT 1

5.3 TRANSITION AND MIXING CONTROL (ADDRESS 02H)

76543210

A = B SZC1 SZC0 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

01001001

5.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A = B)

Default = 0

0 - Disabled 1 - Enabled

Fucntion:

The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this fu nction is disabled. The volume on bot h AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.

BIT 7

DS582PP1 17

CS4341A

5.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Changes 01 - Changes On Zero Crossings 10 - Soft Ramped Changes 11 - Soft Ramped Changes On Zero Crossings

Fucntion:

Immediate Changes

When Immediate Changes is selected all level changes will take effect immediately in one step.

Changes On Zero Crossings

Changes on Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) i f the signal does not encounter a zero crossing. The zero cross function is independenttly monitored and implemented for each channel.

Soft Ramped Changes

Soft Ramped Changes allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the n ew l e vel at a rate of 1dB per 8 left/right clock periods.

BIT 5-6

Soft Ramped Changes on Zero Crossings

Soft Ramped Changes On Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21 .3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is indepently monitored a nd implemented for each channel.

5.3.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo)

Fucntion:

The CS4341A implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 7 and Figure 8 for additiona l information.

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB

00000 MUTE MUTE 00001 MUTE bR 00010 MUTE bL 00011 MUTE b[(L+R)/2] 00100 aR MUTE 00101 aR bR 00110 aR bL 00111 aR b[(L+R)/2] 01000 aL MUTE 01001 aL bR

BIT 0-4

Table 7. AT API Decode

18 DS582PP1

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB

01010 aL bL 01011 aL b[(L+R)/2] 01100 a[(L+R)/2] MUTE 01101 a[(L+R)/2] bR 01110 a[(L+R)/2] bL 0 1 1 1 1 a[(L+R)/2] b[(L+R)/2] 10000 MUTE MUTE 10001 MUTE bR 10010 MUTE bL 1 0 0 1 1 MUTE [(aL+bR)/2] 10100 aR MUTE 10101 aR bR 10110 aR bL 1 0 1 1 1 aR [(bL+aR)/2] 11000 aL MUTE 11001 aL bR 11010 aL bL 1 1 0 1 1 aL [(aL+bR)/2] 1 1 1 0 0 [(aL+bR)/ 2] M U TE 1 1 1 0 1 [(aL+bR)/ 2] bR 1 1 1 1 0 [(bL+aR)/ 2] bL 1 1 1 1 1 [(aL+bR)/ 2] [(aL+bR)/2]

CS4341A

Left Channel

Audio Data

Right Channel

Audio Data

Table 7. ATAPI Decode (Continued)

A Ch an nel

Volume

Control

ΣΣ

B Ch an ne l

Volume

Control

Figure 8. ATAPI Block Diagram

MUTE

AoutA

AoutB

DS582PP1 19

CS4341A

5.4 CHANNEL A VOLUME CONTROL (ADDRESS 03H)

5.5 CHANNEL B VOLUME CONTROL (ADDRESS 04H)

76543210

MUTEx VOLx6 VOLx5 VOLx4 VOLx3 VOLx2 VOLx1 VOLx 0

00000000

5.5.1 MUTE (MUTE)

Default = 0

0 - Disabled 1 - Enabled

Fucntion:

The Digital-to-Analog converter outp ut will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. The MUTEC will go active during the mute period if the Mute function is enabled for both channels.

5.5.2 VOLUME (VOLx)

Default = 0 dB (No Attenuation)

Function:

The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. All volume settings less than - 94 dB are equivalent to enabling the Mute bit.

Binary Code Decimal Value Volume Setting

0000000 0 0 dB 0010100 20 -20 dB 0101000 40 -40 dB

0111100 60 -60 dB

1011010 90 -90 dB

Table 8. example Digital Volume Settings

BIT 7

BIT 0-6

20 DS582PP1

6. CHARACTERISTICS AND SPECIFICATIONS

CS4341A

ANALOG CHARACTERISTICS (CS4341A-KS)

Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R 10kΩ, C

temperature and voltages.

= 10 pF (see Figure 9). Typical performance characteristics are derived from measurements taken at

= 25 °C, VA = 5.0V and 3.3V. Min/Max performance characteristics are guaranteed over the specified operating

)

(Test conditions (unless otherwise specified):

VA = 5 .0V VA = 3.3V

Parameter

Min Typ Max Min Typ Max Unit

Single-Speed Mode Fs = 48kHz

Dynamic Range 18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 1)

A-Weighted A-Weighted

(Note 1)

-20 dB

-60 dB

-20 dB

-60 dB

92 95

101

92 95

-91

-78

-38

-90

-72

-32

-85

88 91

94 97

92 95

-94

-74

-34

-91

-72

-32

-88

Double-Speed Mode Fs = 96kHz

Dynamic Range 18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 1)

A-Weighted A-Weighted

(Note 1)

-20 dB

-60 dB

-20 dB

-60 dB

92 95

101

92 95

-91

-78

-38

-90

-72

-32

-85

88 91

94 97

92 95

-94

-74

-34

-91

-72

-32

-88

Quad-Speed Mode Fs = 192kHz

Dynamic Range 18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 1)

A-Weighted A-Weighted

(Note 1)

-20 dB

-60 dB

-20 dB

-60 dB

92 95

101

92 95

-91

-78

-38

-90

-72

-32

-85

88 91

94 97

92 95

-94

-74

-34

-91

-72

-32

-88

dB dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

DS582PP1 21

CS4341A

ANALOG CHARACTERISTICS (CS4341A-KS)

(Continued)

Parameters Symbol Min Typ Max Units

Dynamic Perform ance for All Modes

Interchannel Isolation (1 kHz) - 102 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB Gain Drift - ±100 - ppm/°C

Analog Output Characteris tic s and Specifications

Full Scale Output Voltage 0.6•VA 0.7•VA 0.8•VA Vpp Output Impedance - 100 - Ω Minimum AC-Load Resistance Maximum Load Capacitance

(Note 2) (Note 2)

-3-kΩ

- 100 - pF

Notes: 1. One-half LS B of triangular PDF dither is added to data.

2. Ref er t o Figure 10.

AGN D

3.3 µF

AOUTx

Figure 9. Output Test Load

125

out

100

Capacitive Load -- C (pF)

2.5 5 10 15 3

Safe Operating

Resistive Load -- R (kΩ)

Region

Figure 10. Maximum Loading

22 DS582PP1

CS4341A

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

filter characteristics and the X -axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic b y Fs.)

Parameter Min Typ Max Unit

Single-Speed Mode - (4kHz to 50kHz sample rates)

Passband

to -0.05 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.02 - +0.08 dB StopBand 0.5465 - - Fs StopBand Attenuation Group Delay - 9/Fs - s Passband Group Delay Dev iation 0 - 20 kHz - ±0.36/Fs - s De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz

(Note 4)

Double-Speed Mode - (50kHz to 100kHz sample rates)

Passband

Frequency Response 10 Hz to 20 kHz -0.06 - +0.2 dB StopBand 0.577 - - Fs StopBand Attenuation Group Delay - 4/Fs - s Passband Group Delay Dev iation 0 - 40 kHz

Quad-Speed Mode - (100kHz to 200kHz sample rates)

Frequency Response 1 0 Hz to 20 kHz -1 - 0 dB Group Delay - 3/Fs - s

Fs = 44.1 kHz

to -0.1 dB corner

to -3 dB corner

(Note 3)

Fs = 48 kHz

(Note 3)

0 - 20 kHz

0 0

50 - - dB

0 0

55 - - dB

±1.39/Fs ±0.23/Fs

0.4535

0.4998

+0.2/-0.1

+0.05/-0.14

+0/-0.22

0.4621

0.4982

(The

Fs Fs

dB dB dB

Fs Fs

s s

Notes: 3. For Single-Speed Mode , the measurement bandwidth is 0.5465 Fs to 3 Fs.

For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

4. De-em phas is is only available in Single-Speed Mode.

DS582PP1 23

CS4341A

Figure 11. Single-Speed Stopband Rejection Figure 12. Single-Speed Transition Band

Figure 13. Single-Speed Transition Band (Detail) Figure 14. Single-Speed Passband Ripple

Figure 15. Double-Speed Stopband Rejection Figure 16. Double-Speed Transition Band

24 DS582PP1

CS4341A

Figure 17. Double-Speed Transition Band (Detail) Figure 18. Double-Speed Passband Ripple

DS582PP1 25

CS4341A

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Max Units

MCLK Frequency 1.024 51.2 MHz MCLK Duty Cycle 45 55 % Input Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

Fs Fs Fs

100

50 100 200

kHz kHz

kHz LRCK Duty Cycle 40 60 % SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Frequency MCLKDIV Disabled

MCLKDIV Enabled

SCLK rising to LRCK edge delay t SCLK rising to LRCK edge setup time t SDIN valid to SCLK rising setup time t SCLK rising to SDIN hold time t

sclkl

sclkh

slrd

slrs

sdlrs

sdh

20 - ns 20 - ns

MCLK

-----------------2

MCLK

-----------------4

20 - ns 20 - ns 20 - ns 20 - ns

LRCK

SCLK

SDIN

slrd

sdlrs

Figure 19. Serial Input Timing

slrs

sclkl

sdh

sclkh

26 DS582PP1

CS4341A

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

0 = AGND, Logic 1 = VA)

Parameter Symbol Min Max Unit

C Mode

SCL Clock Frequency f RST

Rising Edge to Start

Bus Free Time Between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling

(Note 5)

SDA Setup time to SCL Rising t Rise Time of SCL and SDA t Fall Time SCL and SDA t Setup Time for Stop Condition t

hdst

low high sust

hdd

sud

susp

scl

irs

buf

, t , t

rc fc

Notes: 5. Data m u st be held for sufficie nt time to bridge the transition t ime, t

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

, of SCL.

(Inputs: Logic

RST

SDA

SCL

irs

Stop S tart

buf

hdst

lo w

high

hdd

sud

ack

Figure 20. Control Port Timing - I2C Mode

Repeated

Start

sust

hdst

Stop

susp

DS582PP1 27

CS4341A

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f RST

Rising Edge to CS Falling CCLK Edge to CS CS

High Time Between Transmissions

Falling to CCLK Edge

Falling

(Note 6)

CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN

Notes: 6. t

only needed before first falling edge of CS after RST rising edge. t

spi

(Note 7) (Note 8) (Note 8)

7. D a ta must be held for sufficient time to bridge the transition time of CCLK.

8. For f

< 1 MHz.

sclk

t t t

dsu

srs

spi csh css

scl sch

-6MHz 500 - ns 500 - ns

1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns

- 100 ns

= 0 at all other times.

spi

(Continued)

RST

CCLK

CDIN

srs

spi

css

scl

dsu

sch

Figure 21. Control Port Timing - SPI Mode

csh

28 DS582PP1

CS4341A

DC ELECTRICAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Normal Operation

Powe r Supp l y Current

Power Dissipation VA = 5.0V

Power-d ow n Mo de

Powe r Supp l y Current VA = 5.0V VA = 3.3V

Power Dissipation VA = 5.0V

All Modes of Operation

Power Supply Rejection Ratio

Nominal Voltage

Output Impedance Maximum allowable DC current source/sink

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink MUTEC Low-Level Output Voltage - 0 - V MUTEC High-Level Output Voltage - VA - V Maximum MU TEC Drive Current - 3 - mA

(Note 9)

(Note 10)

(Note 11)

(AGND = 0V; all voltages with respect to AGND.)

VA = 5.0V VA = 3.3V

VA = 3.3V

1 kHz 60 Hz

PSRR -

18 15

90 50

60 35

0.3

0.1

60 40

0.5•VA 250

0.01 VA

250

0.01

25 20

125 100

mA mA

mW mW

µA µA

mW mW

dB dB

kΩ

DIGITAL INPUT CHARACTERISTIC S

Parameters Symbol Min Typ Max Units

Input Leakage Current I Input Capacitance - 8 - pF

DIGITAL INTERFACE SPECIFIC ATIONS

Parameters Symbol Min Max Units

Interface Voltage Supply = 3.3V or 5.0V

High-Level Input Voltage V Low-Level Input Voltage V

(AGND = 0V; all voltages with respect to AGND.)

(GND = 0 V; all voltages with respect to GND.)

--±10µA

IH IL

2.0 - V

-0.8V

THERMAL CHARACTERISTICS AND SPECIFICATIONS

Parameters Symbol Min Typ Max Units

Package Thermal Resistance θ Ambient Operating Temperature (Power Applied) T

- 125 - °C/Watt

-10 - +70 °C

DS582PP1 29

RECOMMENDED OPERATING SPECIFICATION

Parameters Symbol Min Typ Max Units

DC Power Supply

Analog VA 2.7

4.5

3.3 5

CS4341A

3.6

5.5

V V

ABSOLUTE MAXIMUM RATINGS

beyond these limits may result in perman ent damage to the device. Normal operation is not guaranteed at these extremes.)

Parameters Symbol Min Max Units

DC Power Supply VA -0.3 6.0 V Input Current Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

Notes: 9. Normal operation is defined as RST

speed mode, and open outputs, unless otherwise specified.

10. P ower Down Mode is defined as RST

11. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR.

12. A ny pi n excep t supplies.

(AGND = 0 V; all voltages with respect to AGND. Operation

(Note 1 2)

= HI with a 997 Hz, 0dBFS input sampled at the highest Fs for each

= LO with all clocks and data lines held static.

IND

stg

-±10mA

-0.3 VA+0.4 V

-55 125 °C

-65 150 °C

30 DS582PP1

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typic a lly 10Hz to 20kHz), includi ng distortion components. Expressed in decibel s.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise m easurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full sc ale. Thi s techn ique ensures that the di s tor t ion components are below t he noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and t he Electronic Industries A ssociation of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

CS4341A

The gain difference bet ween left and right channels. Uni ts in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

8. REFERENCES

1) CDB4341A Evaluation Board Datasheet

2) “The I http://www.semiconductors.philips.com

C Bus Specification: Version 2.1” Phi lips Semiconduc to rs, Jan uary 2000.

DS582PP1 31

9. PACKAGE DIMENSIONS

16L SOIC (150 MIL BODY) PACKAGE DRAWING

CS4341A

SEATING

PLANE

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.053 0.069 1.35 1.75

A1 0.004 0.010 0.10 0.25

B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.386 0.394 9.80 10.0 0

E 0.150 0.157 3.80 4.00

e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20

L 0.016 0.050 0.40 1.27

∝

0° 8° 0° 8°

JEDEC # : MS-012

∝

32 DS582PP1

Cirrus Logic CS4341A-KS, CDB4341A Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

TABLE OF CONTENTS

1. PIN DESCRIPTION

2. TYPICAL CONNECTION DIAGRAM

Figure 1. Typical Connection Diagram

3. APPLICATIONS

3.2.1 Auto-Detect Enabled

3.2.2 Auto-Detect Disabled

Figure 2. I2S Data

Figure 3. Left Justified up to 24-Bit Data

Figure 4. Right Justified Data

Figure 5. De-Emphasis Curve

3.7.1 Power-up

3.7.2 Power-down

3.7.3 Discharge Time

3.9.1 MAP Auto Increment

3.9.2 I2C Mode

3.9.2a I2C Write

3.9.2b I2C Read

Figure 6. Control Port Timing, I2C Mode

3.9.3 SPI Mode

3.9.3a SPI Write

Figure 7. Control Port Timing, SPI mode

4. REGISTER QUICK REFERENCE

5. REGISTER DESCRIPTION

Tabl e 6 . Digital Interface Form a t

Figure 8. ATAPI Block Diagram

6. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (CS4341A-KS)

Figure 9. Output Test Load

Figure 10. Maximum Loading

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Figure 11. Single-Speed Stopband Rejection Figure 12. Single-Speed Transition Band

Figure 13. Single-Speed Transition Band (Detail) Figure 14. Single-Speed Passband Ripple

Figure 15. Double-Speed Stopband Rejection Figure 16. Double-Speed Transition Band

Figure 17. Double-Speed Transition Band (Detail) Figure 18. Double-Speed Passband Ripple

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Figure 19. Serial Input Timing

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

Figure 20. Control Port Timing - I2C Mode

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

Figure 21. Control Port Timing - SPI Mode

DC ELECTRICAL CHARACTERISTICS

DIGITAL INPUT CHARACTERISTIC S

DIGITAL INTERFACE SPECIFIC ATIONS

THERMAL CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING SPECIFICATION

ABSOLUTE MAXIMUM RATINGS

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

Dynamic Range

Interchannel Isolation

Interchannel Gain Mismatch

Gain Error

Gain Drift

8. REFERENCES

9. PACKAGE DIMENSIONS