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CS4341A
User Manual
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Cirrus Logic CS4341A User Manual

CS4341A

24-Bit, 192 kHz Stereo DAC with Volume Control

Features

and 48 kHz
z ATAPI Mixing z Digital Volume Control with Soft Ramp
– 94 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions
z Up to 200-kHz Sample Rates z Automatic Mode Detection for Sample Rates
between 4 and 200 kHz
z Pin Compatible with the CS4341

Description

The CS4341A is a complete stereo digital-to-analog sys­tem including digital interpolation, fourth-order delta­sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera­ture and a high tolerance to clock jitter.
The CS4341A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, oper­ates over a wide power supply range and is pin compatible with the CS4341, as described in section 3.1. These features are ideal for DVD audio players.
ORDERING INFORMATION
CS4341A-KS 16-pin SOIC, -10 to 70 °C CS4341A-KSZ, Lead Free 16-pin SOIC, -10 to 70 °C CDB4341A Evaluation Board
RST
SCLK
LRCK
SDIN
Cirrus Logic, Inc.
http://www.cirrus.com
SCL/CCLK MUTECAD0/CS
Interface
Serial Audio
SDA/CDIN
Control Port
Interface
Copyright © Cirrus Logic, Inc. 2004
External
Mute Control
Volume ControlInterpolation Filter Analog Filter
Mixer
Volume ControlInterpolation Filter ∆Σ
÷2
MCLK
(All Rights Reserved)
∆Σ
DAC
DAC
Analog Filter
AOUTA
AOUTB
JUL ‘04
DS582F2
1

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................... 5
2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 6
3. APPLICATIONS ........................................................................................................................ 7
3.1 Upgrading from the CS4341 to the CS4341A .................................................................... 7
3.2 Sample Rate Range/Operational Mode Detect .................................................................. 7
3.2.1 Auto-Detect Enabled ............................................................................................. 7
3.2.2 Auto-Detect Disabled ............................................................................................ 7
3.3 System Clocking ................................................................................................................ 8
3.4 Digital Interface Format ...................................................................................................... 8
3.5 De-Emphasis Control ......................................................................................................... 9
3.6 Recommended Power-up Sequence ................................................................................. 9
3.7 Popguard
3.7.1 Power-up ............................................................................................................. 10
3.7.2 Power-down ........................................................................................................ 10
3.7.3 Discharge Time ................................................................................................... 10
3.8 Grounding and Power Supply Arrangements .................................................................. 10
3.9 Control Port Interface ....................................................................................................... 11
3.9.1 Rise Time for Control Port Clock ......................................................................... 11
3.9.2 MAP Auto Increment ........................................................................................... 11
3.9.3 I
3.9.4 SPI Mode ............................................................................................................ 14
3.10 Memory Address Pointer (MAP) .............................................................................. 15
®
Transient Control ........................................................................................... 10
2
C Mode ............................................................................................................. 12
3.9.3a I
3.9.3b I
3.9.4a SPI Write .............................................................................................. 14
CS4341A
2
C Write ............................................................................................... 12
2
C Read .............................................................................................. 13
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM­ER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade­marks or service marks of their respective owners.
2
C system.
Cirrus Logic, Inc. and its
2 DS582F2
CS4341A
3.10.1 INCR (Auto Map Increment Enable) ............................................................................ 15
3.10.2 MAP (Memory Address Pointer) .................................................................................. 15
4. REGISTER QUICK REFERENCE .......................................................................................... 16
5. REGISTER DESCRIPTION .................................................................................................... 17
5.1 Mode Control 1 (address 00h).......................................................................................... 17
5.2 Mode Control 2 (address 01h).......................................................................................... 17
5.3 Transition and Mixing Control (address 02h).................................................................... 19
5.4 Channel A Volume Control (address 03h)........................................................................ 22
5.5 Channel B Volume Control (address 04h)........................................................................ 22
6. CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 23
SPECIFIED OPERATING CONDITIONS ............................................................................. 23
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 23
ANALOG CHARACTERISTICS (CS4341A-KS) ..................................................................... 24
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 26
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE .......................................... 29
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE....................................... 30
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE....................................... 31
DC ELECTRICAL CHARACTERISTICS ................................................................................ 32
DIGITAL INPUT CHARACTERISTICS ................................................................................... 32
DIGITAL INTERFACE SPECIFICATIONS ............................................................................. 32
7. PARAMETER DEFINITIONS .................................................................................................. 33
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range ...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch................................................................................................... 33
Gain Error ............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
8. REFERENCES ........................................................................................................................ 33
9. PACKAGE DIMENSIONS ...................................................................................................... 34
THERMAL CHARACTERISTICS AND SPECIFICATIONS.................................................... 34
DS582F2 3
LIST OF FIGURES
CS4341A
Figure 1. Typical Connection Diagram .......................................................................................... 6
Figure 2. I
Figure 3. Left Justified up to 24-Bit Data ....................................................................................... 9
Figure 4. Right Justified Data ........................................................................................................ 9
Figure 5. De-Emphasis Curve ....................................................................................................... 9
Figure 6. I
Figure 7. Control Port Timing, I2C Mode ..................................................................................... 13
Figure 8. Control Port Timing, SPI mode .................................................................................... 14
Figure 9. ATAPI Block Diagram .................................................................................................. 21
Figure 10. Output Test Load ......................................................................................................... 25
Figure 11. Maximum Loading ........................................................................................................ 25
Figure 12. Single-Speed Stopband Rejection ............................................................................... 27
Figure 13. Single-Speed Transition Band ..................................................................................... 27
Figure 14. Single-Speed Transition Band (Detail) ......................................................................... 27
Figure 15. Single-Speed Passband Ripple ................................................................................... 27
Figure 16. Double-Speed Stopband Rejection .............................................................................. 27
Figure 17. Double-Speed Transition Band .................................................................................... 27
Figure 18. Double-Speed Transition Band (Detail) ....................................................................... 28
Figure 19. Double-Speed Passband Ripple .................................................................................. 28
Figure 20. Serial Input Timing ....................................................................................................... 29
Figure 21. Control Port Timing - I
Figure 22. Control Port Timing - SPI Mode ................................................................................... 31
2
S Data .......................................................................................................................... 8
2
C Buffer Example ...................................................................................................... 11
2
C Mode .................................................................................... 30
LIST OF TABLES
Table 1. CS4341A Auto-Detect .......................................................................................................... 7
Table 2. CS4341A Mode Select ......................................................................................................... 7
Table 3. Single-Speed Mode Standard Frequencies.......................................................................... 8
Table 4. Double-Speed Mode Standard Frequencies ........................................................................ 8
Table 5. Quad-Speed Mode Standard Frequencies........................................................................... 8
Table 6. Digital Interface Format ...................................................................................................... 18
Table 7. ATAPI Decode.................................................................................................................... 20
Table 8. Example Digital Volume Settings ....................................................................................... 22
4 DS582F2

1. PIN DESCRIPTION

RST MUTEC
SDIN AOUTA
161
152
CS4341A
SCLK VA
LRCK AGND
MCLK AOUTB
SCL/CCLK REF_GND
SDA/CDIN VQ
AD0/CS
Pin Name # Pin Description
RST
SDIN
SCLK
LRCK
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
FILT+
VQ
REF_GND
AOUTR AOUTL
AGND
VA
MUTEC
Reset (Input) - Powers down device when enabled.
1
Serial Audio Data (Input) - Input for two’s complement serial audio data.
2
Serial Clock (Input) -Serial clock for the serial audio interface.
3
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
4
serial audio data line.
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
5
Serial Control Port Clock (Input) - Serial clock for the control port interface.
6
7
Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Input for SPI data.
Address Bit / Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select
8
the chip in SPI mode.
Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir-
9
cuits.
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
10
Reference Ground (Input) - Ground reference for the internal sampling circuits.
11
Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac-
12
teristics table.
15
Analog Ground (Input) - Ground reference.
13
14 Power (Input) - Positive power for the analog, digital, control port interface, and serial audio
interface sections.
Mute Control (Output) - Control signal for optional mute circuit.
16
143
134
125
116
107
98
FILT+
DS582F2 5

2. TYPICAL CONNECTION DIAGRAM

CS4341A
Serial Audio
Data
Processor
External Clock
Micro-
Con trolled
Configuration
2
3
4
5
6
7
8
1
SDIN
SCLK
LRCK
CS4341A
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
RST
AGND
14
VA
13
0.1 µF
AOUTA
MUTEC
FILT+
VQ
REF_GND
AOUTB
12
15
16
9
10
11
3.3 µF
+
10 k
.1 µF
3.3 µF
+
10 k
1µF
560
1µF
560
+3.3V or +5.0V
Ω
C
+
0.1 µF
1µF
Ω
C
C=
OPTIONAL
MUTE
CIRCUIT
R560
+
L
π
4
Fs(R
L
560)
Audio
Output A
R
L
Audio
Output B
R
L
+
Ω
+
Ω

Figure 1. Typical Connection Diagram

6 DS582F2
CS4341A

3. APPLICATIONS

3.1 Upgrading from the CS4341 to the CS4341A

The CS4341A is pin and functionally compatible with all CS4341 designs, operating at the standard audio sample rates, that use pin 3 as a serial clock input. In addition to the features of the CS4341, the CS4341A supports standard sample rates up to 192 kHz, as well as automatic mode detection for sample rates be­tween 4 and 200 kHz. The automatic speed mode detection feature allows sample rate changes between single, double and quad-speed modes without external intervention.
The CS4341A does not support an internal serial clock mode, sample rates between 50 kHz and 84 kHz (unless otherwise stated), or 2.7 V operation as does the CS4341.

3.2 Sample Rate Range/Operational Mode Detect

The device operates in one of three operational modes. The allowed sample rate range in each mode will depend on whether the Auto-Detect Defeat bit is enabled/disabled.

3.2.1 Auto-Detect Enabled

The Auto-Detect feature is enabled by default in the control port register 5.1. In this state, the CS4341A will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (FS)MODE
4 kHz - 50 kHz Single Speed Mode 84 kHz - 100 kHz Double Speed Mode 170 kHz - 200 kHz Quad Speed Mode
Table 1. CS4341A Auto-Detect

3.2.2 Auto-Detect Disabled

The Auto-Detect feature can be defeated via the control port register 5.1. In this state, the CS4341A will not auto-detect the correct mode based on the input sample rate (F must be set appropriately if Fs falls within one of the ranges illustrated in Table 2. Please refer to section 5.1.1 for implementation details. Sample rates outside the specified range for each mode are not supported.
MC1 MC0 Input Sample Rate (FS)MODE
0 0 4 kHz - 50 kHz Single Speed Mode 0 1 50 kHz - 100 kHz Double Speed Mode 1 0 100 kHz - 200 kHz Quad Speed Mode
Table 2. CS4341A Mode Select
). The operational mode
s
DS582F2 7
CS4341A

3.3 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK for each Speed Mode, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.
Sample Rate
(kHz)
32 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520
256x 384x 512x 768x 1024x*
MCLK (MHz)
Table 3. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64 8.1920 12.2880 16.3840 24.5760 32.7680
88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520
128x 192x 256x 384x 512x*
MCLK (MHz)
Table 4. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
176.4 22.5792 33.8688 45.1584 192 24.5760 36.8640 49.1520
128x 192x 256x*
MCLK (MHz)
Table 5. Quad-Speed Mode Standard Frequencies
* Requires MCLKDIV bit = 1 in the Mode Control 1 register (address 00h).

3.4 Digital Interface Format

The device will accept audio samples in several digital interface formats. The desired format is selected via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.2.2) . For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 2-4.
LRCK
SCLK
SDIN +3 +2 +1+5 +4
MSB
-1 -2 -3 -4 -5
Left C hannel
LSB
MSB
-1 -2 -3 -4

Figure 2. I2S Data

8 DS582F2
Right Channel
+3 +2 +1+5 +4
LSB
CS4341A
LRCK
SCLK
SDIN +3 +2 +1+5 +4
MSB
-1 -2 -3 -4 -5
Left Cha nnel
LSB
MSB
-1 -2 -3 -4
Right C hannel
+3 +2 +1+5 +4
LSB

Figure 3. Left Justified up to 24-Bit Data

LRCK
SCLK
SDIN
MSB
Left Channel
+1 +2 +3 +4
LSB MSB
32 clocks
+5
-6 -5 -4 -3 -2 -1-7

Figure 4. Right Justified Data

LSB -6 -5 -4 -3 -2 -1-7
Right Channel
+1 +2 +3 +4
+5
MSB

3.5 De-Emphasis Control

The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48 kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 5.2.3 for the desired de-emphasis control.
NOTE: De-emphasis is only available in Single-Speed Mode.
Gain
dB
T1=50 µs
0dB
-10dB
F1 F2
3.183 kHz 10.61 kHz
T2 = 15 µs
Frequency

Figure 5. De-Emphasis Curve

3.6 Recommended Power-up Sequence

1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequences, as discussed in section 3.3. In this state, the control port is reset to its default settings and VQ will remain low.
2. Bring RST
3. Load the desired register settings while keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description of power-up timing.
high. The device will remain in a low power state with VQ low.
DS582F2 9
CS4341A

3.7 Popguard® Transient Control

The CS4341A uses Popguard® technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the au­dio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the PDN bit or the RST pin is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.

3.7.1 Power-up

When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to­ward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capac­itors to charge to the quiescent voltage, minimizing the power-up transient.

3.7.2 Power-down

To prevent transients at power-down, the device must first enter its power-down state by enabling RST or PDN. When this occurs, audio output ceases and the internal output buffers are disconnect­ed from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.

3.7.3 Discharge Time

To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.

3.8 Grounding and Power Supply Arrangements

As with any high resolution converter, the CS4341A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane.
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimze impedance, these capacitors should be located on the same layer as the DAC.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwant­ed coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ to REF_GND (and VQ to REF_GND), and should also be located on the same layer as the DAC. The CDB4341A evaluation board demonstrates the optimum layout and power supply arrangements.
10 DS582F2
CS4341A

3.9 Control Port Interface

The control port is used to load all the internal register settings (see section 5). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I2C or SPI.
Notes: MCLK must be applied during all I2C communication.

3.9.1 Rise Time for Control Port Clock

When excess capacitive loading is present on the I2C clock line, pin 6 (SCL/CCLK) may not have sufficient hysteresis to meet the standard I2C rise time specification. This prevents the use of com­mon I2C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt Trigger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341A. This will not affect the operation of the I2C bus as pin 6 is an input only.
VA
SCL
Figure 6. I2C Buffer Example
Pin 6

3.9.2 MAP Auto Increment

The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
DS582F2 11
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