Cirrus Logic CS4341A User Manual

CS4341A

24-Bit, 192 kHz Stereo DAC with Volume Control

Features

z 101 dB Dynamic Range z -91 dB THD+N z +3.3 V or +5 V Power Supply z 50 mW with 3.3 V supply z Low Clock Jitter Sensitivity z Filtered Line-level Outputs z On-Chip Digital De-emphasis for 32, 44.1,

and 48 kHz

z ATAPI Mixing z Digital Volume Control with Soft Ramp

– 94 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions

z Up to 200-kHz Sample Rates z Automatic Mode Detection for Sample Rates

between 4 and 200 kHz

z Pin Compatible with the CS4341

Description

The CS4341A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter.

The CS4341A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, operates over a wide power supply range and is pin compatible with the CS4341, as described in section 3.1. These features are ideal for DVD audio players.

ORDERING INFORMATION

CS4341A-KS 16-pin SOIC, -10 to 70 °C CS4341A-KSZ, Lead Free 16-pin SOIC, -10 to 70 °C CDB4341A Evaluation Board

RST

SCLK

LRCK

SDIN

Cirrus Logic, Inc.

http://www.cirrus.com

SCL/CCLK MUTECAD0/CS

Interface

Serial Audio

SDA/CDIN

Control Port

Interface

External

Mute Control

Volume ControlInterpolation Filter Analog Filter

Mixer

Volume ControlInterpolation Filter ∆Σ

÷2

MCLK

∆Σ

DAC

Analog Filter

AOUTA

AOUTB

JUL ‘04

DS582F2

1. PIN DESCRIPTION ................................................................................................................... 5

2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 6

3. APPLICATIONS ........................................................................................................................ 7

3.1 Upgrading from the CS4341 to the CS4341A .................................................................... 7

3.2 Sample Rate Range/Operational Mode Detect .................................................................. 7

3.2.1 Auto-Detect Enabled ............................................................................................. 7

3.2.2 Auto-Detect Disabled ............................................................................................ 7

3.3 System Clocking ................................................................................................................ 8

3.4 Digital Interface Format ...................................................................................................... 8

3.5 De-Emphasis Control ......................................................................................................... 9

3.6 Recommended Power-up Sequence ................................................................................. 9

3.7 Popguard

3.7.1 Power-up ............................................................................................................. 10

3.7.2 Power-down ........................................................................................................ 10

3.7.3 Discharge Time ................................................................................................... 10

3.8 Grounding and Power Supply Arrangements .................................................................. 10

3.9 Control Port Interface ....................................................................................................... 11

3.9.1 Rise Time for Control Port Clock ......................................................................... 11

3.9.2 MAP Auto Increment ........................................................................................... 11

3.9.3 I

3.9.4 SPI Mode ............................................................................................................ 14

3.10 Memory Address Pointer (MAP) .............................................................................. 15

Transient Control ........................................................................................... 10

C Mode ............................................................................................................. 12

3.9.3a I

3.9.3b I

3.9.4a SPI Write .............................................................................................. 14

CS4341A

C Write ............................................................................................... 12

C Read .............................................................................................. 13

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

C system.

Cirrus Logic, Inc. and its

2 DS582F2

CS4341A

3.10.1 INCR (Auto Map Increment Enable) ............................................................................ 15

3.10.2 MAP (Memory Address Pointer) .................................................................................. 15

4. REGISTER QUICK REFERENCE .......................................................................................... 16

5. REGISTER DESCRIPTION .................................................................................................... 17

5.1 Mode Control 1 (address 00h).......................................................................................... 17

5.2 Mode Control 2 (address 01h).......................................................................................... 17

5.3 Transition and Mixing Control (address 02h).................................................................... 19

5.4 Channel A Volume Control (address 03h)........................................................................ 22

5.5 Channel B Volume Control (address 04h)........................................................................ 22

6. CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 23

SPECIFIED OPERATING CONDITIONS ............................................................................. 23

ABSOLUTE MAXIMUM RATINGS ......................................................................................... 23

ANALOG CHARACTERISTICS (CS4341A-KS) ..................................................................... 24

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 26

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE .......................................... 29

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE....................................... 30

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE....................................... 31

DC ELECTRICAL CHARACTERISTICS ................................................................................ 32

DIGITAL INPUT CHARACTERISTICS ................................................................................... 32

DIGITAL INTERFACE SPECIFICATIONS ............................................................................. 32

7. PARAMETER DEFINITIONS .................................................................................................. 33

Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33

Dynamic Range ...................................................................................................................... 33

Interchannel Isolation ............................................................................................................. 33

Interchannel Gain Mismatch................................................................................................... 33

Gain Error ............................................................................................................................... 33

Gain Drift ................................................................................................................................ 33

8. REFERENCES ........................................................................................................................ 33

9. PACKAGE DIMENSIONS ...................................................................................................... 34

THERMAL CHARACTERISTICS AND SPECIFICATIONS.................................................... 34

DS582F2 3

LIST OF FIGURES

CS4341A

Figure 1. Typical Connection Diagram .......................................................................................... 6

Figure 2. I

Figure 3. Left Justified up to 24-Bit Data ....................................................................................... 9

Figure 4. Right Justified Data ........................................................................................................ 9

Figure 5. De-Emphasis Curve ....................................................................................................... 9

Figure 6. I

Figure 7. Control Port Timing, I2C Mode ..................................................................................... 13

Figure 8. Control Port Timing, SPI mode .................................................................................... 14

Figure 9. ATAPI Block Diagram .................................................................................................. 21

Figure 10. Output Test Load ......................................................................................................... 25

Figure 11. Maximum Loading ........................................................................................................ 25

Figure 12. Single-Speed Stopband Rejection ............................................................................... 27

Figure 13. Single-Speed Transition Band ..................................................................................... 27

Figure 14. Single-Speed Transition Band (Detail) ......................................................................... 27

Figure 15. Single-Speed Passband Ripple ................................................................................... 27

Figure 16. Double-Speed Stopband Rejection .............................................................................. 27

Figure 17. Double-Speed Transition Band .................................................................................... 27

Figure 18. Double-Speed Transition Band (Detail) ....................................................................... 28

Figure 19. Double-Speed Passband Ripple .................................................................................. 28

Figure 20. Serial Input Timing ....................................................................................................... 29

Figure 21. Control Port Timing - I

Figure 22. Control Port Timing - SPI Mode ................................................................................... 31

S Data .......................................................................................................................... 8

C Buffer Example ...................................................................................................... 11

C Mode .................................................................................... 30

LIST OF TABLES

Table 1. CS4341A Auto-Detect .......................................................................................................... 7

Table 2. CS4341A Mode Select ......................................................................................................... 7

Table 3. Single-Speed Mode Standard Frequencies.......................................................................... 8

Table 4. Double-Speed Mode Standard Frequencies ........................................................................ 8

Table 5. Quad-Speed Mode Standard Frequencies........................................................................... 8

Table 6. Digital Interface Format ...................................................................................................... 18

Table 7. ATAPI Decode.................................................................................................................... 20

Table 8. Example Digital Volume Settings ....................................................................................... 22

4 DS582F2

1. PIN DESCRIPTION

RST MUTEC

SDIN AOUTA

161

152

CS4341A

SCLK VA

LRCK AGND

MCLK AOUTB

SCL/CCLK REF_GND

SDA/CDIN VQ

AD0/CS

Pin Name # Pin Description

RST

SDIN

SCLK

LRCK

MCLK

SCL/CCLK

SDA/CDIN

AD0/CS

FILT+

REF_GND

AOUTR AOUTL

AGND

MUTEC

Reset (Input) - Powers down device when enabled.

Serial Audio Data (Input) - Input for two’s complement serial audio data.

Serial Clock (Input) -Serial clock for the serial audio interface.

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

Serial Control Port Clock (Input) - Serial clock for the control port interface.

Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Input for SPI data.

Address Bit / Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select

the chip in SPI mode.

Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir-

cuits.

Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

Reference Ground (Input) - Ground reference for the internal sampling circuits.

Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac-

teristics table.

Analog Ground (Input) - Ground reference.

14 Power (Input) - Positive power for the analog, digital, control port interface, and serial audio

interface sections.

Mute Control (Output) - Control signal for optional mute circuit.

143

134

125

116

107

FILT+

DS582F2 5

2. TYPICAL CONNECTION DIAGRAM

CS4341A

Serial Audio

Data

Processor

External Clock

Micro-

Con trolled

Configuration

SDIN

SCLK

LRCK

CS4341A

MCLK

SCL/CCLK

SDA/CDIN

AD0/CS

RST

AGND

0.1 µF

AOUTA

MUTEC

FILT+

REF_GND

AOUTB

3.3 µF

10 k

.1 µF

3.3 µF

10 k

1µF

560

1µF

560

+3.3V or +5.0V

Ω

0.1 µF

1µF

Ω

OPTIONAL

MUTE

CIRCUIT

R560

Fs(R

560)

Audio

Output A

Audio

Output B

Ω

Figure 1. Typical Connection Diagram

6 DS582F2

CS4341A

3. APPLICATIONS

3.1 Upgrading from the CS4341 to the CS4341A

The CS4341A is pin and functionally compatible with all CS4341 designs, operating at the standard audio sample rates, that use pin 3 as a serial clock input. In addition to the features of the CS4341, the CS4341A supports standard sample rates up to 192 kHz, as well as automatic mode detection for sample rates between 4 and 200 kHz. The automatic speed mode detection feature allows sample rate changes between single, double and quad-speed modes without external intervention.

The CS4341A does not support an internal serial clock mode, sample rates between 50 kHz and 84 kHz (unless otherwise stated), or 2.7 V operation as does the CS4341.

3.2 Sample Rate Range/Operational Mode Detect

The device operates in one of three operational modes. The allowed sample rate range in each mode will depend on whether the Auto-Detect Defeat bit is enabled/disabled.

3.2.1 Auto-Detect Enabled

The Auto-Detect feature is enabled by default in the control port register 5.1. In this state, the CS4341A will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for each mode are not supported.

Input Sample Rate (FS)MODE

4 kHz - 50 kHz Single Speed Mode 84 kHz - 100 kHz Double Speed Mode 170 kHz - 200 kHz Quad Speed Mode

Table 1. CS4341A Auto-Detect

3.2.2 Auto-Detect Disabled

The Auto-Detect feature can be defeated via the control port register 5.1. In this state, the CS4341A will not auto-detect the correct mode based on the input sample rate (F must be set appropriately if Fs falls within one of the ranges illustrated in Table 2. Please refer to section 5.1.1 for implementation details. Sample rates outside the specified range for each mode are not supported.

MC1 MC0 Input Sample Rate (FS)MODE

0 0 4 kHz - 50 kHz Single Speed Mode 0 1 50 kHz - 100 kHz Double Speed Mode 1 0 100 kHz - 200 kHz Quad Speed Mode

Table 2. CS4341A Mode Select

). The operational mode

DS582F2 7

CS4341A

3.3 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK for each Speed Mode, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.

Sample Rate

(kHz)

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520

256x 384x 512x 768x 1024x*

MCLK (MHz)

Table 3. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz)

64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520

128x 192x 256x 384x 512x*

MCLK (MHz)

Table 4. Double-Speed Mode Standard Frequencies

Sample Rate

(kHz)

176.4 22.5792 33.8688 45.1584 192 24.5760 36.8640 49.1520

128x 192x 256x*

MCLK (MHz)

Table 5. Quad-Speed Mode Standard Frequencies

* Requires MCLKDIV bit = 1 in the Mode Control 1 register (address 00h).

3.4 Digital Interface Format

The device will accept audio samples in several digital interface formats. The desired format is selected via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.2.2) . For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 2-4.

LRCK

SCLK

SDIN +3 +2 +1+5 +4

MSB

-1 -2 -3 -4 -5

Left C hannel

LSB

MSB

-1 -2 -3 -4

Figure 2. I2S Data

8 DS582F2

Right Channel

+3 +2 +1+5 +4

LSB

CS4341A

LRCK

SCLK

SDIN +3 +2 +1+5 +4

MSB

-1 -2 -3 -4 -5

Left Cha nnel

LSB

MSB

-1 -2 -3 -4

Right C hannel

+3 +2 +1+5 +4

LSB

Figure 3. Left Justified up to 24-Bit Data

LRCK

SCLK

SDIN

MSB

Left Channel

+1 +2 +3 +4

LSB MSB

32 clocks

-6 -5 -4 -3 -2 -1-7

Figure 4. Right Justified Data

LSB -6 -5 -4 -3 -2 -1-7

Right Channel

+1 +2 +3 +4

MSB

3.5 De-Emphasis Control

The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48 kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 5.2.3 for the desired de-emphasis control.

NOTE: De-emphasis is only available in Single-Speed Mode.

Gain

T1=50 µs

0dB

-10dB

F1 F2

3.183 kHz 10.61 kHz

T2 = 15 µs

Frequency

Figure 5. De-Emphasis Curve

3.6 Recommended Power-up Sequence

1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequences, as discussed in section 3.3. In this state, the control port is reset to its default settings and VQ will remain low.

2. Bring RST

3. Load the desired register settings while keeping the PDN bit set to 1.

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description of power-up timing.

high. The device will remain in a low power state with VQ low.

DS582F2 9

CS4341A

3.7 Popguard® Transient Control

The CS4341A uses Popguard® technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the PDN bit or the RST pin is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.

3.7.1 Power-up

When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.

3.7.2 Power-down

To prevent transients at power-down, the device must first enter its power-down state by enabling RST or PDN. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.

3.7.3 Discharge Time

To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.

3.8 Grounding and Power Supply Arrangements

As with any high resolution converter, the CS4341A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane.

Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimze impedance, these capacitors should be located on the same layer as the DAC.

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ to REF_GND (and VQ to REF_GND), and should also be located on the same layer as the DAC. The CDB4341A evaluation board demonstrates the optimum layout and power supply arrangements.

10 DS582F2

CS4341A

3.9 Control Port Interface

The control port is used to load all the internal register settings (see section 5). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.

The control port operates in one of two modes: I2C or SPI.

Notes: MCLK must be applied during all I2C communication.

3.9.1 Rise Time for Control Port Clock

When excess capacitive loading is present on the I2C clock line, pin 6 (SCL/CCLK) may not have sufficient hysteresis to meet the standard I2C rise time specification. This prevents the use of common I2C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt Trigger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341A. This will not affect the operation of the I2C bus as pin 6 is an input only.

SCL

Figure 6. I2C Buffer Example

Pin 6

3.9.2 MAP Auto Increment

The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.

DS582F2 11

CS4341A

3.9.3 I2C Mode

In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 7 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VA or GND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected.

3.9.3a I2C Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 7.

1) Initiate a START condition to the I must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W

2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written.

3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP.

C bus followed by the address byte. The upper 6 bits

bit.

4) If the INCR bit (see section 3.9.2) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step

1. If no further writes to other registers are desired, initiate a STOP condition to the bus.

12 DS582F2

CS4341A

3.9.3b I2C Read

To read from the device, follow the procedure below while adhering to the control port Switching Specifications.

1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit.

2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see section 3.9.2) if an I2C read is the first operation performed on the device.

3) Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.

4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step

1. If no further reads from other registers are desired, initiate a STOP condition to the bus.

NOTE

SDA

SCL

NOTE: If operation is a write, this byte contains the Memory Address Pointer, MAP. If

operation is a read, this byte contains the data of the register pointed to by the MAP.

001000

Start

AD0

R/W

ACK

DATA 1-8

Figure 7. Control Port Timing, I2C Mode

ACK

DATA 1-8

ACK

Stop

DS582F2 13

CS4341A

3.9.4 SPI Mode

In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 7 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.

3.9.4a SPI Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 6.

1) Bring CS low.

2) The address byte on the CDIN pin must then be 00100000.

3) Write to the memory address pointer, MAP. This byte points to the register to be written.

4) Write the desired data to the register pointed to by the MAP.

5) If the INCR bit (see section 3.9.2) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high.

6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high.

CCLK

CHIP

ADDRESS

CDIN

Figure 7. Control Port Timing, SPI mode

0010000

MAP = Memory Address Pointer

R/W

MAP

MSB

byte 1

DATA

LSB

byte n

14 DS582F2

3.10 Memory Address Poi n te r ( MA P )

76543210

INCR Reserved Reserved Reserved Reserved MAP2 MAP1 MAP0

00000000

3.10.1 INCR (AUTO MAP INCREMENT ENABLE)

Default = ‘0’

0 - Disabled 1 - Enabled

3.10.2 MAP (MEMORY ADDRESS POINTER)

Default = ‘000’

CS4341A

DS582F2 15

CS4341A

4. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

0h Mode Control 1 Reserved MC1 MC0 Reserved Reserved AUTOD MCLKDIV Reserved

DEFAULT 00000000

1h Mode Control 2 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 POR PDN

DEFAULT 10000011

2h Transition and Mixing

Control

DEFAULT 00000000

3h Channel A Volume

Control

DEFAULT 00000000

4h Channel B Volume

Control

DEFAULT 00000000

A = B SOFT ZERO

CROSS

MUTEA VOLA6 VOLA5 VOLA4 VOLA3 VOLA2 VOLA1 VOLA0

MUTEB VOLB6 VOLB5 VOLB4 VOLB3 VOLB2 VOLB1 VOLB0

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

16 DS582F2

CS4341A

5. REGISTER DESCRIPTION

NOTE: All registers are read/write in I2C mode and write only in SPI mode, unless otherwise stated.

5.1 MODE CONTROL 1 (ADDRESS 00H)

76543210

Reserved MC1 MC0 Reserved Reserved AUTOD MCLKDIV Reserved

00000000

5.1.1 SPEED MODE CONTROL (MC) BIT 5-6

Default = 00

00 - Single-Speed Mode 01 - Double-Speed Mode 10 - Quad-Speed Mode

The operational speed mode must be set if the auto-detect defeat bit is enabled (AUTOD = 1). These bits are ignored if the auto-detect defeat is disabled (AUTOD = 0).

5.1.2 AUTO-DETECT DEFEAT (AUTOD)

Default = 0

0 - Disabled 1 - Enabled

The Auto-Detect function can be defeated to allow sample rate changes from 50 to 84 kHz, and from 100 to 170 kHz. The operational speed mode must be set via the speed mode control bits (see section

5.1.1) if the auto-detect feature is defeated.

5.1.3 MCLK DIVIDE-BY-2 (MCLKDIV)

Default = 0

0 - Disabled 1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.

BIT 2

BIT 1

5.2 MODE CONTROL 2 (ADDRESS 01H)

76543210

AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 POR PDN

10000011

DS582F2 17

5.2.1 AUTO-MUTE (AMUTE) BIT 7

Default = 1

0 - Disabled 1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similiar to volume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register.

CS4341A

5.2.2 DIGITAL INTERFACE FORMAT (DIF)

BIT 4-6

Default = 000 - Format 0 (I2S, up to 24-bit data)

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 2-4.

DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

000I 0 0 1 Identical to Format 1 1 2 0 1 0 Left Justified, up to 24-bit data, 2 3 0 1 1 Right Justified, 24-bit data 3 4 1 0 0 Right Justified, 20-bit data 4 4 1 0 1 Right Justified, 16-bit data 5 4 1 1 0 Right Justified, 18-bit data 6 4 1 1 1 Identical to Format 1 1 2

S, up to 24-bit data 1 2

Table 6. Digital Interface Format

5.2.3 DE-EMPHASIS CONTROL ( DEM[1:0] ) BIT 2-3

Default = 00

00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz

Function:

Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 5, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.

NOTE: De-emphasis is only available in Single-Speed Mode.

18 DS582F2

5.2.4 POPGUARD® TRANSIENT CONTROL (POR) BIT 1

Default = 1

0 - Disabled 1 - Enabled

Function:

The PopGuard the quiescent voltage during power-on or power-down. Please refer to section 3.7 for implementation details.

Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to

CS4341A

5.2.5 POWER DOWN (PDN)

Default = 1

0 - Disabled 1 - Enabled

Function:

The device will enter a low-power state when this function is enabled. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur. The contents of the control registers are retained in this mode.

BIT 0

5.3 TRANSITION AND MIXING CONTROL (ADDRESS 02H)

76543210

A = B SZC1 SZC0 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

01001001

5.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A = B) BIT 7

Default = 0

0 - Disabled 1 - Enabled

Fucntion:

The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.

DS582F2 19

5.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 5-6

Default = 10

00 - Immediate Changes 01 - Changes On Zero Crossings 10 - Soft Ramped Changes 11 - Soft Ramped Changes On Zero Crossings

Fucntion:

Immediate Changes

When Immediate Changes is selected all level changes will take effect immediately in one step.

Changes On Zero Crossings

Changes on Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independenttly monitored and implemented for each channel.

Soft Ramped Changes

Soft Ramped Changes allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods.

CS4341A

Soft Ramped Changes on Zero Crossings

Soft Ramped Changes On Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is indepently monitored and implemented for each channel.

5.3.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo)

Fucntion:

The CS4341A implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 7 and Figure 8 for additional information.

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB

00000 MUTE MUTE 00001 MUTE bR 00010 MUTE bL 00011 MUTE b[(L+R)/2] 00100 aR MUTE 00101 aR bR 00110 aR bL 00111 aR b[(L+R)/2] 01000 aL MUTE 01001 aL bR

Table 7. ATAPI Decode

BIT 0-4

20 DS582F2

CS4341A

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB

01010 aL bL 01011 aL b[(L+R)/2] 0 1 1 0 0 a[(L+R)/2] MUTE 0 1 1 0 1 a[(L+R)/2] bR 0 1 1 1 0 a[(L+R)/2] bL 0 1 1 1 1 a[(L+R)/2] b[(L+R)/2] 10000 MUTE MUTE 10001 MUTE bR 10010 MUTE bL 1 0 0 1 1 MUTE [(aL+bR)/2] 10100 aR MUTE 10101 aR bR 10110 aR bL 1 0 1 1 1 aR [(bL+aR)/2] 11000 aL MUTE 11001 aL bR 11010 aL bL 1 1 0 1 1 aL [(aL+bR)/2] 1 1 1 0 0 [(aL+bR)/2] MUTE 1 1 1 0 1 [(aL+bR)/2] bR 1 1 1 1 0 [(bL+aR)/2] bL 1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]

Table 7. ATAPI Decode (Continued)

Left Channel

Audio Data

Right Channel

Audio Data

A Channel

Volume Control

MUTE

AoutA

ΣΣ

B Channel

Volume Control

Figure 8. ATAPI Block Diagram

MUTE

AoutB

DS582F2 21

CS4341A

5.4 CHANNEL A VOLUME CONTROL (ADDRESS 03H)

5.5 CHANNEL B VOLUME CONTROL (ADDRESS 04H)

76543210

MUTEx VOLx6 VOLx5 VOLx4 VOLx3 VOLx2 VOLx1 VOLx0

00000000

5.5.1 MUTE (MUTE) BIT 7

Default = 0

0 - Disabled 1 - Enabled

Fucntion:

The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. The MUTEC will go active during the mute period if the Mute function is enabled for both channels.

5.5.2 VOLUME (VOLx)

Default = 0 dB (No Attenuation)

Function:

The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. All volume settings less than - 94 dB are equivalent to enabling the Mute bit.

BIT 0-6

Binary Code Decimal Value Volume Setting

0000000 0 0 dB 0010100 20 -20 dB 0101000 40 -40 dB

0111100 60 -60 dB

1011010 90 -90 dB

Table 8. Example Digital Volume Settings

22 DS582F2

CS4341A

6. CHARACTERISTICS AND SPECIFICATIONS

(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at T

SPECIFIED OPERATING CONDITIONS

Parameters Symbol Min Typ Max Units

DC Power Supply

Analog VA 3.0

Ambient Operating Temperature (Power Applied) T

= 25°C.)

3.3

4.5

-10 - +70 °C

3.6

5.5

V V

ABSOLUTE MAXIMUM RATINGS

beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)

Parameters Symbol Min Max Units

DC Power Supply VA -0.3 6.0 V

Input Current

Digital Input Voltage V

Ambient Operating Temperature (power applied) T

Storage Temperature T

Notes: 1. Any pin except supplies.

(AGND = 0 V; all voltages with respect to AGND. Operation

(Note 1) I

IND

stg

-±10mA

-0.3 VA+0.4 V

-55 125 °C

-65 150 °C

DS582F2 23

CS4341A

ANALOG CHARACTERISTICS (CS4341A-KS) (Test conditions (unless otherwise specified):

Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R 10 kΩ, C

= 10 pF (see Figure 9))

VA = 5.0 V VA = 3 . 3 V

Parameter

Min Typ Max Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range 18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 2)

A-Weighted

(Note 2)

-20 dB

-60 dB

-20 dB

-60 dB

92 95

101

92 95

-91

-78

-38

-90

-72

-32

-85

94 97 92

-94

-74

-34

-91

-72

-32

-88

Double-Speed Mode Fs = 96 kHz

Dynamic Range 18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 2)

A-Weighted

(Note 2)

-20 dB

-60 dB

-20 dB

-60 dB

92 95

101

92 95

-91

-78

-38

-90

-72

-32

-85

94 97 92

-94

-74

-34

-91

-72

-32

-88

Quad-Speed Mode Fs = 192 kHz

Dynamic Range 18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 2)

A-Weighted

(Note 2)

-20 dB

-60 dB

-20 dB

-60 dB

92 95

101

92 95

-91

-78

-38

-90

-72

-32

-85

94 97 92

-94

-74

-34

-91

-72

-32

-88

dB dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

24 DS582F2

CS4341A

ANALOG CHARACTERISTICS (CS4341A-KS) (Continued)

Parameters Symbol Min Typ Max Units

Dynamic Performance for All Modes

Interchannel Isolation (1 kHz) - 102 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Drift - ±100 - ppm/°C

Analog Output Characteristics and Specifications

Full Scale Output Voltage 0.6•VA 0.7•VA 0.8•VA Vpp

Output Impedance - 100 - Ω

Minimum AC-Load Resistance

Maximum Load Capacitance

Notes: 2. One-half LSB of triangular PDF dither is added to data.

3. Refer to Figure 10.

(Note 3) R

(Note 3) C

-3-kΩ

- 100 - pF

AGND

3.3 µF

AOUTx

Figure 9. Output Test Load

125

100

out

Capacitive Load -- C (pF)

2.5

51015

Safe Operating

Region

Resistive Load -- R (kΩ)

Figure 10. Maximum Loading

DS582F2 25

CS4341A

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can

be referenced to the desired sample rate by multiplying the given characteristic by Fs.)

Parameter Min Typ Max Unit

Single-Speed Mode - (4 kHz to 50 kHz sample rates)

Passband

to -0.05 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -0.02 - +0.08 dB

StopBand 0.5465 - - Fs

StopBand Attenuation

Group Delay - 9/Fs - s

De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz

(Note 5) Fs = 44.1 kHz

Double-Speed Mode - (50 kHz to 100 kHz sample rates)

Passband

to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -0.06 - +0.2 dB

StopBand 0.577 - - Fs

StopBand Attenuation

Group Delay - 4/Fs - s

Passband Group Delay Deviation 0 - 40 kHz

Quad-Speed Mode - (100 kHz to 200 kHz sample rates)

Frequency Response 10 Hz to 20 kHz -1 - 0 dB

Group Delay - 3/Fs - s

(Note 4) 50 - - dB

Fs = 48 kHz

(Note 4) 55 - - dB

0 - 20 kHz

0 0

±1.39/Fs ±0.23/Fs

0.4535

0.4998

+0.2/-0.1

+0.05/-0.14

+0/-0.22

0.4621

0.4982

Fs Fs

dB dB dB

Fs Fs

s s

Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.

For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

5. De-emphasis is only available in Single-Speed Mode.

26 DS582F2

Figure 10. Single-Speed Stopband Rejection Figure 11. Single-Speed Transition Band

CS4341A

Figure 12. Single-Speed Transition Band (Detail) Figure 13. Single-Speed Passband Ripple

Figure 14. Double-Speed Stopband Rejection Figure 15. Double-Speed Transition Band

DS582F2 27

CS4341A

Figure 16. Double-Speed Transition Band (Detail) Figure 17. Double-Speed Passband Ripple

28 DS582F2

CS4341A

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Max Units

MCLK Frequency 1.024 51.2 MHz

MCLK Duty Cycle 45 55 %

Input Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

Fs Fs Fs

100

50 100 200

kHz kHz kHz

LRCK Duty Cycle 40 60 %

SCLK Pulse Width Low t

SCLK Pulse Width High t

SCLK Frequency MCLKDIV Disabled

MCLKDIV Enabled

SCLK rising to LRCK edge delay t

SCLK rising to LRCK edge setup time t

SDIN valid to SCLK rising setup time t

SCLK rising to SDIN hold time t

SCLK rising to MCLK edge delay (

NOTE 7)t

sclkl

sclkh

slrd

slrs

sdlrs

sdh

smd

20 - ns

MCLK

-----------------2

MCLK

-----------------4

20 - ns

8-ns

6. Only required for Quad-speed mode.

MCLK

LRCK

SCLK

SDATA

smd

slrd

sdlrs

slrs

sdh

Figure 18. Serial Input Timing

sclkl

sclkh

DS582F2 29

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

(Inputs: Logic 0 = AGND, Logic 1 = VA)

Parameter Symbol Min Max Unit

C Mode

SCL Clock Frequency f

Rising Edge to Start

RST

Bus Free Time Between Transmissions t

Start Condition Hold Time (prior to first clock pulse) t

Clock Low time t

Clock High Time t

Setup Time for Repeated Start Condition t

SDA Hold Time from SCL Falling

(Note 7) t

SDA Setup time to SCL Rising t

Rise Time of SCL

(Note 8) t

Fall Time SCL t

Rise Time of SDA t

Fall Time SDA t

Setup Time for Stop Condition t

scl

irs

buf

hdst

low

high

sust

hdd

sud

susp

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

0-µs

250 - ns

-25ns

-1µs

-300ns

4.7 - µs

CS4341A

Notes: 7. Data must be held for sufficient time to bridge the transition time, t

8. See “Rise Time for Control Port Clock” on page 11. for a recommended circuit to meet rise time specification.

RST

SDA

SCL

irs

Stop Sta rt

buf

hdst

low

hdd

high

sud

Repeated

Start

sust

Figure 19. Control Port Timing - I2C Mode

, of SCL.

hdst

Stop

susp

30 DS582F2

CS4341A

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

Rising Edge to CS Falling

RST

CCLK Edge to CS

High Time Between Transmissions

Falling to CCLK Edge

Falling (Note 9)

CCLK Low Time t

CCLK High Time t

CDIN to CCLK Rising Setup Time t

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

(Note 10) t

(Note 11) t

sclk

srs

spi

csh

css

scl

sch

dsu

-6MHz

500 - ns

1.0 - µs

20 - ns

66 - ns

40 - ns

15 - ns

-100ns

Notes: 9. t

10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For f

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz.

sclk

RST

CCLK

CDIN

srs

css

spi

scl

dsu

sch

Figure 20. Control Port Timing - SPI Mode

= 0 at all other times.

spi

csh

DS582F2 31

CS4341A

DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)

Parameters Symbol Min Typ Max Units

Normal Operation

Power Supply Current VA = 5 .0 V

Power Dissipation VA = 5.0 V

Power-down Mode

Power Supply Current VA = 5.0 V VA = 3.3 V

Power Dissipation VA = 5.0 V

All Modes of Operation

Power Supply Rejection Ratio

Nominal Voltage

Output Impedance Maximum allowable DC current source/sink

Filt+ Nominal Voltage

Output Impedance Maximum allowable DC current source/sink

MUTEC Low-Level Output Voltage - 0 - V

MUTEC High-Level Output Voltage - VA - V

Maximum MUTEC Drive Current - 3 - mA

(Note 12)

(Note 13)

VA = 3.3 V

(Note 14) 1 kHz

60 Hz

PSRR -

18 15

90 50

60 35

0.3

0.1

60 40

0.5•VA 250

0.01

250

0.01

25 20

125 100

mA mA

mW mW

µA µA

mW mW

dB dB

kΩ

DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)

Parameters Symbol Min Typ Max Units

Input Leakage Current I

Input Capacitance - 8 - pF

--±10µA

DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to GND.)

Parameters Symbol Min Max Units

Interface Voltage Supply = 3.3 V or 5.0 V

High-Level Input Voltage V

Low-Level Input Voltage V

12. Normal operation is defined as RST speed mode, and open outputs, unless otherwise specified.

13. Power Down Mode is defined as RST

14. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR.

= HI with a 997 Hz, 0dBFS input sampled at the highest Fs for each

= LO with all clocks and data lines held static.

2.0 - V

-0.8 V

32 DS582F2

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units are in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS4341A

Gain Error

The deviation from the nominal, full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

8. REFERENCES

1) CDB4341A Evaluation Board Datasheet

2) “The I http://www.semiconductors.philips.com

C Bus Specification: Version 2.1” Philips Semiconductors, January 2000.

DS582F2 33

9. PACKAGE DIMENSIONS

16L SOIC (150 MIL BODY) PACKAGE DRAWING

CS4341A

SEATING

PLANE

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.053 0.069 1.35 1.75

A1 0.004 0.010 0.10 0.25

B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.386 0.394 9.80 10.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27

∝

0° 8° 0° 8°

JEDEC # : MS-012

THERMAL CHARACTERISTICS AND SPECIFICATIONS

Parameters Symbol Min Typ Max Units

Package Thermal Resistance θ

-125-°C/Watt

∝

34 DS582F2

Cirrus Logic CS4341A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CS4341A

Features

Description

TABLE OF CONTENTS

1. PIN DESCRIPTION

2. TYPICAL CONNECTION DIAGRAM

Figure 1. Typical Connection Diagram

3. APPLICATIONS

3.1 Upgrading from the CS4341 to the CS4341A

3.2 Sample Rate Range/Operational Mode Detect

3.2.1 Auto-Detect Enabled

3.2.2 Auto-Detect Disabled

3.3 System Clocking

3.4 Digital Interface Format

Figure 2. I2S Data

Figure 3. Left Justified up to 24-Bit Data

Figure 4. Right Justified Data

3.5 De-Emphasis Control

Figure 5. De-Emphasis Curve

3.6 Recommended Power-up Sequence

3.7 Popguard® Transient Control

3.7.1 Power-up

3.7.2 Power-down

3.7.3 Discharge Time

3.8 Grounding and Power Supply Arrangements

3.9 Control Port Interface

3.9.1 Rise Time for Control Port Clock

Figure 6. I2C Buffer Example

3.9.2 MAP Auto Increment

3.9.3 I2C Mode

3.9.3a I2C Write

3.9.3b I2C Read

Figure 7. Control Port Timing, I2C Mode

3.9.4 SPI Mode

3.9.4a SPI Write

Figure 7. Control Port Timing, SPI mode

3.10 Memory Address Poi n te r ( MA P )

4. REGISTER QUICK REFERENCE

5. REGISTER DESCRIPTION

Figure 8. ATAPI Block Diagram

6. CHARACTERISTICS AND SPECIFICATIONS

SPECIFIED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ANALOG CHARACTERISTICS (CS4341A-KS) (Test conditions (unless otherwise specified):

Figure 9. Output Test Load

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Figure 10. Single-Speed Stopband Rejection Figure 11. Single-Speed Transition Band

Figure 12. Single-Speed Transition Band (Detail) Figure 13. Single-Speed Passband Ripple

Figure 14. Double-Speed Stopband Rejection Figure 15. Double-Speed Transition Band

Figure 16. Double-Speed Transition Band (Detail) Figure 17. Double-Speed Passband Ripple

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Figure 18. Serial Input Timing

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

Figure 19. Control Port Timing - I2C Mode

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)

Figure 20. Control Port Timing - SPI Mode

DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)

DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)

DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to GND.)

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

Dynamic Range

Interchannel Isolation

Interchannel Gain Mismatch

Gain Error

Gain Drift

8. REFERENCES

9. PACKAGE DIMENSIONS

THERMAL CHARACTERISTICS AND SPECIFICATIONS