Cirrus Logic CS4294-KQ, CS4294-JQ Datasheet

CS4294

SoundFusion® Audio/Docking Codec ’97 (AMC’97)

FEATURES

n AC ‘97 2.0 compatible
n 20-bit quad output and 18-bit dual stereo input

codec with fixed 48 kHz sampling rate

n Dedicated ADC for enhanced digital docking
n Three analog line-level stereo inputs for connec-

tion from LINE IN, CD, and AUX

n High quality pseudo-differential CD input
n Dual stereo line level output with independent 6-

bit volume control

n 6 General Purpose I/O pins

®

n Meets or ex ce e ds Mi cr o sof t' s

audio performance requirements

n CrystalClear™ Stereo Enhancement

MAIN D/A

CONVERTERS

PCM_OUT

PC 98 and PC 99

2

/

VOL MUTE

DAC

PCM OUT

PATH

DESCRIPTION

The CS4294 is an AC ‘97 compatible Audio Codec
designed for PC multimedia syst ems. Using the in ­dustry leading CrystalClear™ delta-sigma and
mixed signal technology, the CS4294 is ideal for
PC 98-compliant desktop, notebook, and enter­tainment PCs, where high-quality audio features
are required. The CS4294 offers four channels of
D/A and A/D conversion along with analog mixing
and stereo enhancement processing. For multi­channel audio systems, the CS4294 can provide
four audio channels. The CS4294 provides an en­hanced digital docking mode for portable
applications by providing a dedicat ed ADC capture
path from the analog input mixer.

ORDERING INFORMATION

CS4294-KQ 48-pin TQFP 9x9x1.4mm
CS4294-JQ 48-pin TQFP 9x9x1.4mm

VOL

MIC1

LINE

AUX

SDATA_OUT

RESET#

SYNC

Mode Control

CD

+20dB

2

/

2

/

2

/

3

/

2

/

VOL

VOL

VOL

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

MUTE

MUTE

MUTE

MUTE

STEREO

INPUT
MIXER

Σ

STEREO TO

MONO MIXER

AC-Link Interface

ADC DAC

3D

Σ

STEREO
OUTPUT

MIXER

Σ

MAIN ADC GAIN

ADC

INPUT

VOL MUTE ADC

MUX

MASTER VOLUME

VOL

ALTERNATE VOLUME

VOL

2

/

6

/

OUTPUT
BUFFER

OUTPUT
BUFFER

2

/

2

/

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2000

(All Rights Reserved)

LINE_OUT

ALT_LINE_OUT

SDATA_IN
BIT_CLK
GPIO

FEB ‘00

DS326PP4

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .................................. ....... ...... ....... ...... ....... ..... 5

AUDIO ANALOG CHARACTERISTICS....................................................................................5

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6

RECOMMENDED OPERATING CONDITIONS.......................................................................6

MIXER CHARACTERISTICS....................................................................................................6

DIGITAL CHARACTERISTICS................................................................................................. 6

SERIAL PORT TIMING.............................................................................................................7

2. GENERAL DESCRIPTION .....................................................................................................10

2.1 Overview ..........................................................................................................................10

2.2 Modes of Operation .........................................................................................................10

2.2.1 Mode 0 ................................................................................................................10

2.2.2 Mode 1 ................................................................................................................10

3. DIGITAL SECTION .................................................................................................................10

3.1 AC-Link ............................................................................................................................ 10

3.2 Control registers ............................................................................................................... 11

4. ANALOG SECTION ..... ....... ...... ....... ...................................... ....... ...... ....... ...... ....... ...... ..........11

4.1 Audio Output Mixer .......................................................................................................... 12

4.2 Audio Input Mux ...............................................................................................................12

4.3 Audio Input Mixer .............................................................................................................12

4.4 Audio Volume Control ......................................................................................................12

5. AC ‘97 ..................................................................................................................................... 12

5.1 AC ‘97 Frame Definition ...................................................................................................12

5.2 AC-Link Serial Data Output Frame .................................................................................. 12

5.3 AC-Link Audio Output Frame ...........................................................................................13

5.3.1 Serial Data Output Slot Tags (Slot 0)...................................................................13

5.3.2 Register Address (Slot 1).....................................................................................13

5.3.3 Register Write Data (Slot 2) .................................................................................14

5.3.4 Playback Data (Slots 3-11) ..................................................................................14

5.3.5 GPIO Data (Slot12)..............................................................................................14

5.4 AC-Link Audio Input Frame .............................................................................................. 14

5.4.1 Serial Data Input Slot Tag Bits (Slot 0) ............................................................... 14

5.4.2 Read-Back Address Port (Slot 1).........................................................................15

5.4.3 Read-Back Data Port (Slot 2)............................................................................... 15

5.4.4 PCM Capture Data (Slot 3-11).............................................................................15

5.4.5 GPIO Pin Status (Slot 12)....................................................................................15

CS4294

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

CrystalClear is a trademark of Cirrus Logic, Inc.
SoundFusion is a registered trademark of Cirrus Logic, Inc.

Preliminary product infor mation des cribes produ cts which are in production, but for which f ull characteriz ation data is n ot yet available. Advance prod­uct information descr ibes produ cts which are in development a nd subject to developmen t changes. Cirr us Logic, I nc. has made be st eff orts to ens ure
that the information c ontained in this d ocument is a ccurate an d reliab le. However, t he informa tion is s ubject to chang e without not ice and is provide d
“AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for
infringements of paten ts o r other rig hts of third p arties. This document is the pro perty of Cirrus Lo gic, In c. and i mplies no l icens e under pat ents, copy­rights, trademarks, or trade secrets. No part of this publication may be co pied, reproduced, stored in a retrieval system, or transmitted, in any fo rm
or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus
Logic webbiest or disk may be p rinted fo r use b y the us er . Howeve r, no p art of t he p rintout o r ele ctron ic fi les may be copie d, repr oduced , store d in a
retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent
of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a bas is for manufacture or sale of any items without the prior written
consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or othe r vendors and suppliers appearing in this document may be trade­marks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Lo gic, Inc. trademarks and service

2 DS326PP4

CS4294

5.5 AC ’97 Reset Modes ........................................................................................................ 15

5.5.1 Cold AC ‘97 Reset .............................................................................................. 15

5.5.2 Warm AC ’97 Reset ..... ...... ....... ...... ....... ...... ....................................... ...... ....... ... 15

5.5.3 AC ’97 Register Reset ........................................................................................ 16

5.6 AC-Link Protocol Violation - Loss of SYNC ..................................................................... 16

6. REGISTER INTERFACE ........................................................................................................ 17

6.1 Register Descriptions ......................................................................................................18

6.1.1 Reset (Index 00h) ............................................................................................... 18

6.1.2 Master Volume (Index 02h) ................................................................................. 18

6.1.3 Alternate Volume (Index 04h) ............................................................................. 19

6.1.4 Microphone Volume (Index 0Eh) ......................................................................... 19

6.1.5 Stereo Analog Mixer Input Gain (Index’s 10h - 12h, 16h - 18h)........................... 20

6.1.6 Input Mux Select (Index 1Ah)............................................................................... 20

6.1.7 Record Gain (Index 1Ch)..................................................................................... 21

6.1.8 General Purpose (Index 20h)............................................................................... 21

6.1.9 Stereo Enhancement Control (Index 22h) ........................................................... 21

6.1.10 Power Down Control/Status (Index 26h)............................................................ 22

6.1.11 Extended Audio ID (Index 28h) ......................................................................... 23

6.1.12 Extended Audio Status/Control (Index 2Ah) ..................................................... 23

6.1.13 PCM Front DAC Rate (Index 2Ch) .................................................................. 23

6.1.14 PCM Surround DAC Rate (Index 2Eh) ........................................................... 23

6.1.15 PCM LFE DAC Rate (Index 30h) .................................................................... 24

6.1.16 PCM LR ADC Rate (Index 32h)......................................................................... 24

6.1.17 Center LFE Volume (Index 36h) ..................................................................... ... 24

6.1.18 LR Surround Volume (Index 38h) ...................................................................... 24

6.1.19 Extended Codec ID (Index 3Ch) ....................................................................... 25

6.1.20 Extended Codec Status/Control (Index 3Eh) .................................................... 25

6.1.21 Extended Audio DAC1/ADC1 Rate (Index 40h)................................................. 26

6.1.22 Extended Audio DAC2/ADC2 (Index 44h) ......................................................... 26

6.1.23 Extended Audio DAC1/ADC1 Level (Index 46h)................................................ 26

6.1.24 Extended AudioDAC2/ADC2 Level (Index 4Ah)................................................ 26

6.1.25 GPIO Pin Configuration (Index 4Ch).................................................................. 27

6.1.26 GPIO Pin Polarity/Type Configuration (Index 4Eh)............................................ 27

6.1.27 GPIO Pin Sticky (Index 50h).............................................................................. 27

6.1.28 GPIO Pin Wakeup Mask (Index 4Ch) ............................................................... 28

6.1.29 GPIO Pin Status (Index 54h) ............................................................................. 28

6.1.30 AC Mode Control (Index 5Eh)............................................................................ 28

6.1.31 Vendor ID1 (Index 7Ch)..................................................................................... 29

6.1.32 Vendor ID2 (Index 7Eh)..................................................................................... 29

7. ANALOG HARDWARE DESCRIPTION .......................... ...... ................................................. 30

7.1 Line-Level Inputs ............................................................................................................. 30

7.2 Microphone Level Inputs ................................................................................................. 30

7.3 Line Level Outputs ........................................................................................................... 31

7.4 Miscellaneous Analog Signals ......................................................................................... 31

7.5 Power Supplies ................................................................................................................ 32

8. PIN DESCRIPTIONS ....................................................... ...... ....... ...... ....... ...... ....... ...... .......... 33

8.1 Digital I/O Pins ................................................................................................................. 33

8.2 Analog I/O Pins ................................................................................................................ 35

8.3 Filter and Reference Pins ................................................................................................ 36

8.4 Power Supplies ................................................................................................................ 37

9. PARAMETER AND TERM DEFINITIONS .............................................................................. 38

10. REFERENCES ...................................................................................................................... 39

11. PACKAGE DIMENSIONS .................................................................................................... 40

DS326PP4 3

LIST OF FIGURES

Figure 1. Power Up Timing..............................................................................................................8

Figure 2. Clocks ..............................................................................................................................8

Figure 3. Codec Ready from Startup or Fault Condition.................................................................8

Figure 4. Data Setup and Hold........................................................................................................ 9

Figure 5. PR4 Powerdown ..............................................................................................................9

Figure 6. Test Mode ........................................................................................................................ 9

Figure 7. AC-link Connections.......................................................................................................11

Figure 8. Mixer Diagram................................................................................................................ 11

Figure 9. AC-link Input and Output Framing . ....... ...... ....................................... ...... ....... ...... ....... ... 1 2

Figure 10. Line Inputs....................................................................................................................30

Figure 11. Differential CDROM In .................................................................................................30

Figure 12. PC ‘99 Microphone Pre-amplifier ................................................................................. 31

Figure 13. Headphones Driver......................................................................................................32

Figure 14. Voltage Regulator ........................................................................................................32

LIST OF TABLES

Table 1. Mixer Registers ...............................................................................................................17

Table 2. Alternate Line-Out and Master Mono Attenuation...........................................................19

Table 3. Analog Mixer Input Gain Values......................................................................................19

Table 4. Stereo Volume Register Index ........................................................................................20

Table 5. Input Mux Selection.........................................................................................................20

Table 6. 6 Channel Volume Attenuation........................................................................................24

Table 7. GPIO Input/Output Configuration ....................................................................................27

Table 8. Slot Assignments............................................................................................................28

Table 9. Reg. 7Eh Defined Part ID’s .............................................................................................29

CS4294

4 DS326PP4

CS4294

1. CHARACTERISTICS AND SPECIFICATIONS

AUDIO ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted:

T
Z
for ADC, 20- bit linear coding for DAC; Mixer registers set for unity gain.

= 25° C, AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz;

ambient

=10 kΩ/680 pF load CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding

AL

CS4294-KQ CS4294-JQ

UnitMin Typ Max Min Typ Max

Parameter (Note 2) Symbol

Path

(Note 3)

Full Scale Analog Input Voltage
Line Inputs
Mic Inputs (20 dB=0)
Mic Inputs (20 dB=1)

A-D
A-D
A-D

0.91

0.91

0.091

1.00

1.00

0.10

-

0.91

-

0.91

-

0.091

1.00

1.00

0.10

-

V
V
V

RMS
RMS
RMS

-

-

Full Scale Output Voltage (Note 4)
Line and Alternate Line Outputs D-A 0.91 1.0 1.13 0.91 1.0 1.13 V

RMS

Frequency Response
Analog Ac = ± 0.5 dB
DAC Ac = ± 0.5 dB
ADC Ac = ± 0.5 dB

FR A-A

D-A
A-D

20
20
20

-

-

-

20,000
20,000
20,000

20
20
20

-

-

-

20,000
20,000
20,000

Hz
Hz
Hz

Dynamic Range

dB FS A

Stereo Analog inputs to LINE_OUT
Mono Analog inputs to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

DR A-A

A-A
D-A
A-D

90
85
85
85

95
90
90
90

90

-

-

-

-

­85

­87

­85

-

-

-

-

-

dB FS A
dB FS A
dB FS A

DAC SNR (-20 dB FS input w/
CCIR-RMS filter on output) SNR D-A - 63 - - - - dB

Total Harmonic Distortion + Noise
(-3 dB FS input signal):
Line/Alternate Line Output
DAC
ADC (all inputs except phone/mic)
ADC (phone/mic)

THD+N A-A

D-A
A-D
A-D

-94

-

-86

-

-87

-

-87

-

-80

-80

-80

-74

-

-

-

-

­dB FS A

-74

­dB FS A

-74

­dB FS A

-74

-

dB FS A

-74

Power Supply Rejection Ratio
(1 kHz, 0.5 V

w/ 5 V DC offset)(Note 5) 40 60 - - 40 - dB

RMS

Interchannel Isolation 70 87 - - 87 - dB
Spurious Tone (Note 5) - -100 - - -100 - dB FS
Input Impedance (Note 5) 10 - - 10 - - k

Ω

External Load Impedance 10 - - 10 - - kΩ
Output Impedance (Note 5) - 730 - - 730 - Ω
Input Capacitance (Note 5) - 5 - - 5 - pF
Vrefout 2.0 2.3 2.4 2.0 2.3 2.4 V

Notes: 1. Z

refers to the analog output pin loading and CDL refers to the digital output pin loading.

AL

2. Parameter definitions are given in the Paramete r and Term Defini tions section.

3. Path refers to the signal path used to generate this data. These paths are defined in the Parameter and
Term Definition section.

4. Typical measured with Z

=47kΩ/680 pF load.

AL

5. This specification is guaranteed by silicon characterization, it is not production tested.

DS326PP4 5

CS4294

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog
Total Power Dissipation (Supplies, Inputs, Outputs) - - 750 mW
Input Current per Pin (Except Supply Pins) -10 - 10 mA
Output Current per Pin (Except Supply Pins) -15 - 15 mA
Analog Input voltage -0.3 - AVdd + 0.3 V
Digital Input voltage -0.3 - DVdd + 0.3 V
Ambient Temperature (Power Applied) -55 - 110 °C
Storage Temperature -65 - 150 °C

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog

Operating Current +3.3 V Digital

+5 V Digital
Analog
Operating Ambient Temperature 0 - 70 °C

DVdd1, DVdd2
DVdd1, DVdd2

AVdd1, AVdd2

DVdd1, DVdd2

DVdd1, DVdd2

AVdd1, AVdd2

-0.3

-0.3

-0.3

3.135

4.75

4.75

-

-

-

3.3
5
5

40
40
75

6.0

6.0

6.0

3.465

5.25

5.25

97.5

52
52

V
V
V

V
V
V

mA
mA
mA

MIXER CHARACTERISTICS (for CS4294-KQ only)

Parameter Min Typ Max Unit

Mixer Gain Range Span Line In, Aux, CD, Mic1

Line Out, Alternate Line Out

Step Size All volume controls - 1.5 - dB

-

-

46.5

94.5

-

-

dB
dB

DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)

Parameter Symbol Min Typ Max Unit

DVdd = 3.3V

Low level input voltage V
High level input voltage V
High level output voltage V
Low level output voltage V
Input Leakage Current (AC-link inputs) -10 - 10 µA
Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA
Output buffer drive current BIT_CLK

SDATA_IN, EAPD

DVdd = 5.0 V

Low level input voltage V
High level input voltage V
High level output voltage V
Low level output voltage V
Input Leakage Current (AC-link inputs) -10 - 10 µA
Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA
Output buffer drive current BIT_CLK

SDATA_IN, EAPD

oh

oh

il

ih

ol

il

ih

ol

2.15 V

3.0 3.25 V

0.03 .35 V

24

4

3.25 V

4.5 4.95 V

-0.03.35V

24

4

0.8 V

mA
mA

0.8 V

mA
mA

6 DS326PP4

CS4294

SERIAL PORT TIMING

Parameter Symbol Min Typ Max Unit

RESET# Timing

Vdd stable to RESET# inactive T
RESET# active low pulse width T
RESET# inactive to BIT_CLK star t-up delay T
1st SYNC active to CODEC READY set T

vdd2rst#

rst_low

rst2clk

sync2crd

Clocks

BIT_CLK frequency F
BIT_CLK period T

clk

clk_period

BIT_CLK output jitter (depends on XTAL_IN source) - - 750 ps
BIT_CLK high pulse width T
BIT_CLK low pulse width T
SYNC frequency F
SYNC period T
SYNC high pulse width T
SYNC low pulse width T

clk_high

clk_low

sync

sync_period

sync_high

sync_low

Data Setup and Hold

Output Propagation delay from rising edge of BIT_CLK T
Input setup time from falling edge of BIT_CLK T
Input hold time from falling edge of BIT_CLK T
Input Signal rise time T
Input Signal fall time T
Output Signal rise time (Note 5, 6) T
Output Signal fall time (Note 5, 6) T

co

isetup

ihold

irise

ifall

orise

ofall

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T
SYNC pulse width (PR4) Warm Reset T
SYNC inactive (PR4) to BIT_CLK start-up delay T
Setup to trailing edge of RESET# (test mode) (Note 5) T
Rising edge of RESET# to Hi-Z delay (Note 5) T

s2_pdown

sync_pr4

sync2clk

setup2rst

off

Notes: 6. BIT_CLK measured with 47 Ω series termination and CL=50 pF.

5. ms

1.0 - - µs
25 120 - µs

- 62.4 - µs

- 12.288 - MHz

- 81.4 - ns

36 40.7 45 ns
36 40.7 45 ns

-48-kHz

- 20.8 - µs

-1.3-µs

- 19.5 - µs

- 6 12 ns

10 - - ns

0--ns
2-6ns
2-6ns
246ns
246ns

-.341.0µs

1.1 - - µs

162.8 350 - ns
15 - - ns

- - 25 ns

DS326PP4 7

BIT_CLK

RESET#

Vdd

T

rst_low

T

vdd2rst#

Figure 1. Power Up Timing

T

rst2clk

CS4294

BIT_CLK

SYNC

CODEC_READY

BIT_CLK

T

orise

SYNC

T

irise

T

sync2crd

Figure 2. Clocks

T

clk_highTclk_low

T

sync_high

T

T

clk_period

T

ifall

T

sync_low

ifall

T

sync_period

Figure 3. Codec Ready from Startup or F ault Conditi on

8 DS326PP4

BIT_CLK

BIT_CLK

SDATA_IN

SDATA_OUT,
SYNC

T

co

T

isetup

Figure 4. Data Setup and Hold

T

CS4294

ihold

SDATA_OUT

SDATA_IN

SYNC

Slot 1 Slot 2

Write to 0x20 Data PR4 Don’t Care

T

s2_pdown

T

Figure 5. PR4 Powerdown

RESET#

T

setup2rst

SDATA_OUT,
SYNC

T

off

sync_pr4

T

sync2clk

SDATA_IN,
BIT_CLK

Hi-Z

Figure 6. Test Mode

DS326PP4 9

CS4294

2. GENERAL DESCRIPTION

2.1 Overview

The CS4294 is a Mixed-Signal Audio Codec based
on the AC ‘97 1.0 Specification, and the AC ‘97

2.0 Extensions. It is designed to be paired with a
digital controller, typically located on the PCI bus.
The Controller is responsible for all communica­tions between the CS4294 and the rest of the sys­tem. The CS4294 functions as an analog mixer, a
stereo audio ADC, a stereo audio DAC, and a con­trol and digital stream interface to the Controller.
The CS4294 contains three distinct functional sec­tions: Digital, Analog Audio, and Extended Analog
Audio.

The Digital section includes the AC-Link registers,
power management support, SYNC detection cir­cuitry, and AC-Link serial port interface logic. The
Analog Audio section includes the analog input
multiplexer (mux), stereo input mixer, stereo out­put mixer, stereo ADCs, stereo DACs, and analog
volume controls. The Extended Audio section in­cludes dual ADCs, dual DACs, GPIO control and
status, and power down and wake-up logic.

2.2 Modes of Operation

The CS4294 has two basic modes of operation.
Each mode allows varying functionality to meet a
wide variety of software and hardware configura­tions. On power up or system reset, the device re­verts to the basic configuration Mode 0. The four
channel expansion and enhanced digital docking
are activate in Mode 1.

2.2.1 Mode 0

This is the default operating mode for the CS4294.
It supports the legacy AC ‘97 audio modes of oper­ation including audio mixer, ADC’s, and DAC’s.

2.2.2 Mode 1

Mode 1 is the four channel expansion mode. The
second ADC/DAC pairs are utilized for enhanced

audio functionality. The second stereo DAC’s are
routed to the alternate line audio outputs providing
2 additional audio channels. The secondary ADC
inputs may be connected to the output of the analog
stereo input mixer for enhanced audio effect pr o­cessing or enhanced digital docking in a note book
application.

3. DIGITAL SECTION

3.1 AC-Link

All communication with the Codec is established
with a 5-wire digital interface to the Controller chip
as shown in Figure 7. All clocking for the serial
communication is synchronous to the BIT_CLK
signal. BIT_CLK is generated by the primary Co­dec and is used to slave the Controller and any sec­ondary Codecs, if applicable. An AC-link audio
frame is a sequence of 256 serial bits organized into
13 groups referred to as ‘slots’. One frame consists
of one 16-bit slot and twelve 20-bit slots. During
each audio frame, data is passed bi-directionally
between the Codec and the Controller. The input
frame is driven from the Codec on the SDATA_IN
line. The output frame is driven from the Controller
SDATA_OUT line. Both input and output frames
contain the same number of bits and are organized
with the same ‘slot’ configuration. The input and
output frame have differing functions for each slot.
The Controller synchronizes the beginning of a
frame with the SYNC signal. In Figure 9 the posi­tion of each bit location within the frame is noted.
The first bit position in a new serial data frame is F0
and the last bit position in the serial data frame is
F255. When SYNC goes active (high) and is sam­pled active by the CS4294 (on the falling edge of
BIT_CLK), both devices are synchronized to a new
serial data frame. The data on the SDATA_OUT
pin at this clock edge is the final bit of the previous
frame’s serial data. On the next rising edge of
BIT_CLK, the first bit of Slot 0 is driven by the
Controller on the SDATA_OUT pin. The CS4294
latches in this data, as the first bit of the frame, on

10 DS326PP4

CS4294

CODEC

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

Digital AC’97

Controller

Figure 7. AC-link Connections

the next falling edge of the BIT_CLK clock signal.
The Controller is also responsible for issuing reset
via the RESET# signal. After being reset, the Co­dec is responsible for flagging the C ontroller that it
is ready for operation after synchronizing its inter­nal functions. The AC-link signals may be refer­enced to either 5 Volts or 3.3 Volts. The CS4294
must use the same digital supply voltage as the
Controller chip.

3.2 Control registers

All read accesses to the Codec are generated by re­questing a register address (index number) in slot 1
of a SDATA_OUT frame. The following
SDATA_IN frame will contain the register content
in its slot 2. The write operation is identical with the
index in slot 1 and the write data in slot 2. The
AC ‘97 Frame Definition section details the func­tion of each input and output frame. Individual reg­ister descriptions are found in the Register
Interface section.

AC-97 Register Interface

The CS4294 implements the AC ’97 Registers in
accordance with the AC ’97 2.0 Specification. See
the Register Interface section for details on the
CS4294’s register set.

4. ANALOG SECTION

Please refer to Figure 8, Mixer diagram, for a high­level graphical representation of the CS4294 ana­log mixer structure.

MIC1

LINE

CD

AUX

SDATA_OUT

RESET#

SYNC

Mode Control

CONVERTERS

PCM_OUT

2

/

2

/

2

/

3

/

2

/

MAIN D/A

DAC

+20dB

2

/

VOL MUTE

MUTE

VOL

MUTE

VOL

MUTE

VOL

MUTE

VOL

PCM OUT

PATH

STEREO

INPUT
MIXER

Σ

STEREO TO

MONO MIXER

AC-Link Interface

ADC DAC

3D

Σ

Figure 8. Mixer Diagram

STEREO
OUTPUT

ADC

INPUT

MUX

Σ

MIXER

MAIN ADC GA IN

VOL MUTE ADC

MASTER VOLUME

VOL

ALTERNATE VOLUME

VOL

2

/

6

/

OUTPUT
BUFFER

OUTPUT
BUFFER

2

/

2

/

LINE_OUT

ALT_LINE_OUT

SDATA_IN
BIT_CLK
GPIO

DS326PP4 11

CS4294

4.1 Audio Output Mixer

The stereo output mixer sums together the analog
outputs from the Input Mixer, stereo enhancement,
and the PCM DAC output. The stereo output mix is
sent to the LINE_OUT and ALT_LINE_OUT out­put pins of the CS4294. When the device is set to
Mode 1 or the EAM bit in AC Mode Control (Index
5Eh) is set, the secondary DAC outputs are routed
to ALT_LINE_OUT.

4.2 Audio Input Mux

The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
sent to the Digital Controller chip in Slots 3 and 4
of the AC-Link SDATA_IN signal.

4.3 Audio Input Mixer

The input mixer is an analog mix of the analog in­put signals such as MIC, LINE_IN, etc., and the
PCM Audio DAC output. The output of the mixer
is routed to the ADC Input Mux, Audio Output
Mixer, and may be routed to the Extended Audio
ADC input.

4.4 Audio Volume Control

The volume control registers of the AC ’97 Regis­ter interface control analog input level to the input

mixer, the master volume level, and the alternate
volume level. All analog volume controls imple­ment volume steps at nominally 1.5 dB per step.
The analog inputs allow a mixing range of +12 dB
of signal gain to -34.5 dB of signal attenuation. The
analog output volume controls allows from 0 dB to

-94.5 dB of attenuation.

5. AC ‘97

5.1 AC ‘97 Frame Definition

The AC Link is a bi-directional serial port with
thirteen time-division multiplexed slots in each di­rection. The first slot is 16 bits long and termed the
tag slot. Bits in the tag slot determine if the Codec
is ready and indicate which, if any, other slots con­tain valid data. Slots 1 through 11 are 20-bits long
and can contain audio data. Slot 12 contains data to
be written and read from GPIO. The serial data line
is defined from the Controller’s perspective, NOT
from the Audio Codec’s perspective.

5.2 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the
SDATA_OUT pin TO the CS4294 FROM the
Controller. Figure 9 illustrates the serial port tim­ing.

20.8 µS
(48 kHz)

F36 F57

F35

R/W 0 WD15

F36

00000

0

F56

LP19 LP18 RP19

F57

LC17 LC16 RC17RD15

F76

F97

X

F97

0

F255

X

F255

0

SYNC

BIT_CLK

Bit Frame Position:

SDATA_OUT

Bit Frame Position:

SDATA_IN

12.288 MHz

81.4 nS

F0 F1 F2 F16F15F14F13F12

F255

Valid

Frame

F0 F1 F2 F16F15F14F13F12 F35 F56 F76F255

Codec
Ready

Slot 1

Valid

Slot 1
Valid

X

0

Tag Phase Data Phase

Slot 2

Valid

Slot 2
Valid

00

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slots 5-12

SCRA1 SCRA0

Figure 9. AC-l ink Input and Output Framing

12 DS326PP4

CS4294

5.3 AC-Link Audio Output Frame

5.3.1 Serial Data Output Slot Tags (Slot 0)

Bit 1514131211109 8 76543210

Valid

Slot 1

Frame

Valid

Valid Frame

Slot [1:2] Valid

Slot [3:11] Valid

Slot 12 Valid

SCRA[1:0] Secondary Codec Register Access. Unlike the primary Codec, SCRA[1:0] indicate valid slot data when

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 11

Valid

Slot 12

Valid

SCRA1SCRA

0

Determines if any of the following slots contain either valid playback data for the Codec’s DACs, data
for read/write operation, or GPIO data. When set, at least one of the other AC-link slots contain valid
data. If this bit is clear, the remainder of the frame is ignored.

Indicates valid slot data when accessing the register set of the primary Codec (SCRA[1:0] = 00). For a
read operation, Slot 1 Valid is set when Register Address (Slot 1) contains valid data. For a write oper-
ation, Slot 1 Valid and Slot 2 Valid are set indicating Register Address ( Slo t 1) and Register Write Data
(Slot 2) contain valid data. The register address and write data must be valid within the same frame.
SCRA[1:0] must be cleared when accessing the primary Codec. The physical address of a Codec is
determined by the ID[1:0]# input pins which are reflected in the Extended Audio ID (Index 28h) register
and the Extended Codec ID (Index 3Ch) register.

If a Slot Valid bit is set, the named slot contains valid audio data. If the bit is clear, the slot will be ignored.
The definition of each slot is determined by the basic operating mode selected for the CS4294. For more
information, see the AC Mode Control (Index 5Eh) register.

If Slot 12 Valid is set, Slot 12 contains valid write data for the GPIO pins.

accessing the register set of a secondary Codec. The value set in SCRA[1:0] (01,10,11) determines
which of the three possible secondary Codecs is accessed. For a read operation, the SCRA[1:0] bits
are set when Register Address (Slot 1) contains valid data. For a write operation, SCRA[1:0] bits are
set when Register Address (Slot 1) and Register Write Data (Slot 2) contain valid data. The write oper­ation requires the register address and the write data to be valid within the same frame. SCRA[1:0] must
be cleared wh en acce ssing t he prima ry Code c. They must al so be cl eared du ring the idle perio d where
no register read or write is pending. The physical address of a Codec is determined by the ID[1:0]# input
pins which are reflected in the Extended Audio ID (Index 28h) register and the Extended Codec ID (In-
dex 3Ch) register. The SCRA[1:0] bits are listed as the ID[1:0] bits in Slot 0 in the AC ‘97 specification.

5.3.2 Register Address (Slot 1)

Bit 191817161514131211109876543210

R/W# RI6 RI5 RI4 RI3 RI2 RI1 RI0

R/W # Read/Write#. Determines if a read (R/W# = 1) or write (R/W# = 0) operation is requested. For a read

operation, the following Input Frame will return the register index in the Read-Back Address Port (Slot

1) and the contents of the register in the Read-Back Data Port (Slot 2). A write operation does not return
any valid data in the following frame. If the R/W# bit = 0, data must be valid in both the Register Address
(Slot 1) and the Register Write Data (Slot 2)

RI[6:0] Register index/address. Registers can only be accessed on word boundaries; RI0 must be set to 0.

RI[6:0] must contain valid data during a frame when the Slot 1 Valid or SCRA[1:0] are set.

DS326PP4 13

during a frame when Slot [1:2] Valid or SCRA[1:0] are set.