CIRRUS LOGIC CS4270 Service Manual

CS4270

24-Bit, 192 kHz Stereo Audio CODEC

D/A Features

 High Performance

– 105 dB Dynamic Range – -95 dB THD+N

 Selectable Serial Audio Interface Formats

– Left-Justified up to 24-bit – I²S up to 24-bit – Right-Justified 16-, and 24-Bit

 Control Output for External Muting  On-Chip Digital De-Emphasis  Popguard Technology  Multi-bit ∆Σ Conversion  Digital Volume Control

A/D Features

 High Performance

– 105 dB Dynamic Range – -95 dB THD+N

 Multi-bit Delta Sigma Conversion  High-Pass Filter to remove DC Offsets  Selectable Serial Audio Interface Formats

– Left-Justified up to 24-bit – I²S up to 24-bit

System Features

 Direct Interface with Logic Levels 1.8 V to 5 V  Internal Digital Loopback  Stand-Alone or Control Port Functionality  Single-Ended Analog Architecture  Supports all Audio Sample Rates from 4 kHz to

216 kHz

Control Port Supply

1.8 V to 5 V

Hardware Mode or

C/SPI Software Mode

Control Data

Reset

PCM Serial

Audio Input

PCM Serial

Audio Output

Level Translator

Advance Product Information

http://www.cirrus.com

Configuration

Volume

Controls

Serial Interface

Digital Supply

3.3 V to 5 V

Digital Filters

High-Pass

Filter

Multi-bit ∆Σ Modulators

Digital

Filters

Analog Supply

3.3 V to 5 V

Internal Voltage

Reference

External Mute

Control

Switch-Cap

DAC and

Analog Filters

Switch-Cap

ADC

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Mute Signals

Single-Ended Outputs

Single-Ended Inputs

MAY '05

DS686A1

CS4270

Stand-Alone Mode Feature Set

 System Features

– Serial Audio Port Master or Slave Operation – Sing l e, Do ub le , or Quad -Speed Operation



D/A Features

– Auto-mute on Static Samples – 44.1 kHz 50/15 µs De-emphasis Available – Selectable Serial Audio Interface Formats

 Left-Justified up to 24-bit  I²S up to 24-bit



A/D Features

– High-Pass Filter – Selectable Serial Audio Interface Formats

 Left-Justified up to 24-bit  I²S up to 24-bit

Software Mode Feature Set

 System Features

– Serial Audio Port Master or Slave Operation – Internal Digital Loopback Available



D/A Features

– Selectable Auto-mute – 44.1-kHz De-emphasis Filters – Configurable Muting Controls – Volume Control – Selectable Serial Audio Interface Formats

 Left-Justified up to 24-bit  I²S up to 24-bit  Right Justified 16, and 24-bit



A/D Features

– Selectable High-Pass Filter or DC Offset

Calibration

– Selectable Serial Audio Interface Formats

 Left-Justified up to 24-bit  I²S up to 24-bit

General Description

The CS4270 is a high-performance, integrated audio CODEC. The CS4270 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 216 kHz.

Standard 50/15 µs de-emphasis is available for sampling rates of 44.1 kHz for compatibility with digital audio programs mastered using the 50/15 µs pre-emphasis technique.

Integrated level translators allow easy interfacing between the CS4270 and other devices operating over a wide range of logic levels.

Independently addressable high-pass filters are available for the right and left channel of the A/D. This allows the A/D to be used in a wide variety of applications where one audio channel and one DC measurement channel is desired.

The CS4270’s wide dynamic range, negligible distortion, and low noise make it ideal for applications such as DVD-recorders, digital televisions, set top boxes, effects processors, and automotive audio systems.

ORDERING INFORMATION

Product Description Package Pb-Free Grade Temp Range Cont ainer Order #

CS4270

CDB4270 CS4270 Evaluation Board - - - - - CDB4270

2 DS686A1

24-Bit 192 kHz Stereo

Audio CODEC

24-Bit 192 kHz Stereo

Audio CODEC

24-TSSOP YES Commercial -10° to +85° C

24-TSSOP YES Commercial -40° to +85° C

Rail CS4270-CZZ

Tape & Reel CS4270-CZZR

Rail CS4270-DZZ

Tape & Reel CS4270-DZZR

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - SOFTWARE MODE ............................................................................. 6

2. PIN DESCRIPTIONS - STAND-ALONE MODE ....................................................................... 7

3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8

SPECIFIED OPERATING CONDITIONS................................................................................. 8

ABSOLUTE MAXIMUM RATINGS........................................................................................... 8

THERMAL CHARACTERISTICS.............................................................................................. 8

DAC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................... 9

DAC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................... 9

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 11

ADC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................. 12

ADC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................. 13

ADC ANALOG CHARACTERISTICS - ALL MODES ............................................................. 14

ADC DIGITAL FILTER CHARACTERISTICS ........................................................................ 14

DC ELECTRICAL CHARACTERISTICS ....................................................... ... ... .... ... ... ... ... ... 15

DIGITAL CHARACTERISTICS............................................................................................... 16

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 16

SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT....................................... 19

SWITCHING CHARACTERISTICS - SPI CONTROL PORT.................................................. 20

4. TYPICAL CONNECTION DIAGRAM ..................................................................................... 21

5. APPLICATIONS ..................................................................................................................... 22

5.1 Stand-Alone Mode ................. .... ... ... ... ... .... ... ... ... .............................................................22

5.1.1 Recommended Power-Up Sequence ................................................................. 22

5.1.2 Master/Slave Mode ............................................................................................. 22

5.1.3 System Clocking .............................. ... ... .......................................... .... ... ... ... ... ... 22

5.1.4 Clock Ratio Selection .......................................................................................... 23

5.1.5 Interpolation Filter .............................................................................................. 23

5.1.6 High-Pass Filter .. ... ... .... ... ... .......................................... ... ... .... ... ... ... .... ............... 23

5.1.7 Mode Selection & De-Emphasis ......................................................................... 24

5.1.8 Serial Audio Interface Format Selection ............................................................. 24

5.2 Control Port Mode .................................................. ... ... ... .......................................... ... . .. 24

5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode ................ 24

5.2.2 Master / Slave Mode Selection ........................................................................... 24

5.2.3 System Clocking .............................. ... ... .......................................... .... ... ... ... ... ... 25

5.2.4 Clock Ratio Selection .......................................................................................... 25

5.2.5 Internal Digital Loopback .................................................................................... 26

5.2.6 Auto-Mute .... .......................................... .... ... ... ... .... ... ... ...................................... 26

5.2.7 High-Pass Filter and DC Offset Calibration ........................................................ 26

5.2.8 De-Emphasis ... ... ... ... .... ... ... .......................................... ... ... .... ... ... ... ................... 27

5.2.9 Oversampling Modes .... ... ... ... ... .... ... ... ... .... ... ............................................. ... ... ... 27

5.3 De-Emphasis Filter ................................................. ... ... ... ................................................ 27

5.4 Analog Connections ............................................... ... ... ... .... ... ... ... ... ................................ 28

5.4.1 Input Connections ............................................................................................... 28

5.4.2 Output Connections ...................................... ... ... .... ............................................ 29

5.5 Mute Control ....................................................... .... ... ... ... ................................................ 29

5.6 Synchronization of Multiple Devices ................................................................................ 30

5.7 Grounding and Power Supply Decoupling ....................................................................... 30

6. CONTROL PORT INTERFACE .............................................................................................. 31

6.1 SPI™ Mode ..................... ... ... .... ... ... ... ... .... .......................................... ... ... ... .... ... ... ......... 31

6.2 I²C Mode ................... .... ... ... ... .......................................... .... ... ... ... ... .... ... ......................... 32

7. REGISTER QUICK REFERENCE .......................................................................................... 33

8. REGISTER DESCRIPTION .................................................................................................... 34

8.1 Chip ID - Address 01h ..................................................................................................... 34

CS4270

DS686A1 3

CS4270

8.2 Power Control - Address 02h .......................................................................................... 34

8.2.1 Freeze (Bit 7) ...................................................................................................... 34

8.2.2 PDN_ADC (Bit 5) ................................................................................................ 34

8.2.3 PDN_DAC (Bit 1) ................................................................................................ 34

8.2.4 Power Down (Bit 0) ............................................................................................. 34

8.3 Mode Control - Address 03h ............................................................................................ 35

8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) .................................... 35

8.3.2 Ratio Select (Bits 3:1) ......................................................................................... 35

8.3.3 PopGuard Disable (Bit 0) .................................................................................... 35

8.4 ADC and DAC Control - Address 04h ............................................................................. 35

8.4.1 ADC HPF Freeze A (Bit 7) .................................................................................. 35

8.4.2 ADC HPF Freeze B (Bit 6) .................................................................................. 36

8.4.3 Digital Loopback (Bit 5) ....................................................................................... 36

8.4.4 DAC Digital Interface Format (Bits 4:3) ............... ............. ............. ............. ......... 36

8.4.5 ADC Digital Interface Format (Bit 0) ................................................................... 36

8.5 Transition Control - Address 05h ..................................................................................... 37

8.5.1 DAC Single Volume (Bit 7) .................................................................................. 37

8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ........................................................ 37

8.5.3 Invert Signal Polarity (Bits 4:1) ............................................................................ 37

8.5.4 De-Emphasis Control (Bit 0) ............................................................................... 38

8.6 Mute Control - Address 06h ............................................................................................. 38

8.6.1 Auto-Mute (Bit 5) ................................................................................................. 38

8.6.2 ADC Channel A & B Mute (Bits 4:3) ................................................................... 38

8.6.3 Mute Polarity (Bit 2) ............................................................................................ 38

8.6.4 DAC Channel A & B Mute (Bits 1:0) ................................................................... 38

8.7 DAC Channel A Volume Control - Address 07h .............................................................. 39

8.8 DAC Channel B Volume Control - Address 08h .............................................................. 39

10. PACKAGE DIMENSIONS .................................................................................................... 41

11. APPENDIX ....................................................................................................................... 42

12. REVISION HISTORY ............................................................................................................ 48

LIST OF FIGURES

Figure 1. Output Test Load ....................................................................................................................... 10

Figure 2. Maximum Loading ...................................................................................................................... 10

Figure 3. Master Mode Serial Audio Port Timing ...................................................................................... 17

Figure 4. Slave Mode Serial Audio Port Timing ........................................................................................ 17

Figure 5. Format 0, Left Justified up to 24-Bit Data .................................................................................. 18

Figure 6. Format 1, I²S up to 24-Bit Data .................................................................................................. 18

Figure 7. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only)

Format 3, Right Justified 24-Bit Data. (Available in Control Port Mode only ) ................ ................ ............ 18

Figure 8. I²C Mode Control Port Timing .................................................................................................... 19

Figure 9. SPI Control Port Timing .......................................... ... ... .... ... ... ... ... .... ......................................... 20

Figure 10. CS4270 Typical Connection Diagram ............................. ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 21

Figure 11. De-Emphasis Curve ................................................................................................................. 27

Figure 12. CS4270 Recommended Analog Input Network .......................................................................28

Figure 13. CS5344 Example Analog Input Network .................................................................................. 29

Figure 14. CS4270 Recommended Analog Output Filter .......................................................................... 29

Figure 15. Suggested Active-Low Mute Circuit ......................................................................................... 30

Figure 16. Control Port Timing, SPI mode ............................................. ... ... .... ... ... ................................... 31

Figure 17. Control Port Timing, I²C Mode ................................................. ... .... ... ... ... .... ... ... ... ... .... ............ 32

Figure 18. De-Emphasis Curve ................................................................................................................. 38

Figure 19. DAC Single-Speed (fast) Stopband Rejection ................................... ... ... .... ... ... ... ... .... ... ... ... ... 42

Figure 20. DAC Single-Speed (fast) Transition Band ............................................................................... 42

4 DS686A1

CS4270

Figure 21. DAC Single-Speed (fast) Transition Band (detail) ................................................................... 42

Figure 22. DAC Single-Speed (fast) Passband Ripple .............................................................................42

Figure 23. DAC Single-Speed (slow) Stopband Rejection ........................................................................ 42

Figure 24. DAC Single-Speed (slow) Transition Band .............................................................................. 42

Figure 25. DAC Single-Speed (slow) Transition Band (detail) .................................................................. 43

Figure 26. DAC Single-Speed (slow) Passband Ripple ...................................................................... ... ... 43

Figure 27. DAC Double-Speed (fast) Stopband Rejection ........................................................................ 43

Figure 28. DAC Double-Speed (fast) Transition Band .............................................................................. 43

Figure 29. DAC Double-Speed (fast) Transition Band (detail) .................................................................. 43

Figure 30. DAC Double-Speed (fast) Passband Ripple ............................................................................ 43

Figure 31. DAC Double-Speed (slow) Stopband Rejection ...................................................................... 44

Figure 32. DAC Double-Speed (slow) Transition Band .............................................................................44

Figure 33. DAC Double-Speed (slow) Transition Band (detail) .............................. ................ ................ ... 44

Figure 34. DAC Double-Speed (slow) Passband Ripple ........................................................................... 44

Figure 35. DAC Quad-Speed (fast) Stopband Rejection .......................................................................... 44

Figure 36. DAC Quad-Speed (fast) Transition Band ................................................................................. 44

Figure 37. DAC Quad-Speed (fast) Transition Band (detail) .....................................................................45

Figure 38. DAC Quad-Speed (fast) Passband Ripple ...............................................................................45

Figure 39. DAC Quad-Speed (slow) Stopband Rejection ................................................................... ... ... 45

Figure 40. DAC Quad-Speed (slow) Transition Band ...............................................................................45

Figure 41. DAC Quad-Speed (slow) Transition Band (detail) ................................................................... 45

Figure 42. DAC Quad-Speed (slow) Passband Ripple ............................................................................. 45

Figure 43. ADC Single-Speed Mode Stopband Rejection ........................................................................ 46

Figure 44. ADC Single-Speed Mode Transition Band ...............................................................................46

Figure 45. ADC Single-Speed Mode Transition Band (Detail) .................................................................. 46

Figure 46. ADC Single-Speed Mode Passband Ripple ............................................................................. 46

Figure 47. ADC Double-Speed Mode Stopband Rejection ....................................................................... 46

Figure 48. ADC Double-Speed Mode Transition Band ............................................................................. 46

Figure 49. ADC Double-Speed Mode Transition Band (Detail) ................................................................. 47

Figure 50. ADC Double-Speed Mode Passband Ripple ........................................................................... 47

Figure 51. ADC Quad-Speed Mode Stopband Rejection ............................. .... ... ... ... .... ............................ 47

Figure 52. ADC Quad-Speed Mode Transition Band ................................... .... ... ... ... .... ... ... ... ... .... ... ... ...... 47

Figure 53. ADC Quad-Speed Mode Transition Band (Detail) ....................................... ... ... ... ... .... ... ... ... ... 47

Figure 54. ADC Quad-Speed Mode Passband Ripple .............................................................................. 47

LIST OF TABLES

Table 1. Speed Modes..... ... ... .... ... ... ... ...................................................................................................... 22

Table 2. Clock Ratios - Stand-Alone Mode............................................................................................... 23

Table 3. CS4270 Stand-Alone Mode Control............................................................................................ 24

Table 4. Speed Modes..... ... ... .... ... ... ... ...................................................................................................... 25

Table 5. Clock Ratios - Control Port Mode................................................................................................ 25

Table 6. Analog Input Design Parameters................................................................................................ 28

Table 7. Memory Address Pointer.................... ... .... ... ... ... .... ... ... ... .... ... ... ... ............................................. .. 32

Table 8. Functional Mode Selection................................. .... ... ... ... ............................................. .... ... ........ 35

Table 9. MCLK Divider Configuration........................................................................................................ 35

Table 10. DAC Digital Interface Formats ... ... ... ... .............................................. ... ... ... .... ... ... ... .................. 36

Table 11. ADC Digital Interface Formats ... ... ... ... .............................................. ... ... ... .... ... ... ... .................. 36

Table 12. Soft Cross or Zero Cross Mode Selection................................................................................. 37

Table 13. Digital Volume Control ........ .... ... ... .......................................................................................... .. 39

DS686A1 5

1. PIN DESCRIPTIONS - SOFTWARE MODE

CS4270

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

SDA/CDOUT

SCL/CCLK

AD0/CS

AD1/CDIN

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2

Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. LRCK MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

SCLK VD DGND SDOUT VLC

SDA/CDOUT SCL/CCLK AD0/CS

AD1/CDIN AD2

RST AINA

AINB VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. VA 19 Analog Power (Input) - Positive power for the analog sections. AGND

MUTEA MUTEB

AOUTA AOUTB

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

Digital Power (Input) - Positive power supply for the digital section.

Digital Ground (Input) - Ground reference for the internal digital section.

Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

Control Port Power (Input) - Determines the signal level for the control port.

Serial Control Data (Input/Output) - SDA is a data I/O in I²C mode. CDOUT is the output data line for

the control port interface in SPI mode. Serial Control Port Clock (Input) - Serial clock for the serial control port.

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode.

CS is the chip select signal for SPI format. Address Bit 1 (I²C) / Serial Control Data (Input) - AD1 is a chip address pin in I²C mode. CDIN is the

input data line for the control port i nt erf ace in SPI mode. Address Bit 2 (I²C) (Input) - AD2 is a chip address pin in I²C mode.

Reset (Input) - The device enters a low power mode when low.

14 15

Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table.

Analog Ground (Input) - Ground reference. Must be connected to analog ground.

20 21

Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down.

24 22

Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Character- istics specification table.

6 DS686A1

2. PIN DESCRIPTIONS - STAND-ALONE MODE

CS4270

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

M1 M0

I²S/LJ

MDIV1

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2

Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. LRCK MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

SCLK VD DGND SDOUT

(M/S

) VLC M1

I²S/LJ 11

MDIV1 MDIV2

RST AINA

AINB VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VA 19

AGND MUTEA

MUTEB AOUTA

AOUTB

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

Digital Power (Input) - Positive power supply for the digital section.

Digital Ground (Input) - Ground reference for the internal digital section.

Serial Audio Data Output (Output) - Output for two’s complement serial audio data. This pin must be

pulled-up or pulled-down to select Master or Slave Mode. Control Port Power (Input) - Determines the signal level for the control port.

8 9

Mode Selection (Input) - Determines the operational mode of the device.

Serial Audio Interface Select (Input) - Selects either the left-justified orI²S format for the Serial Audio Interface.

MCLK Divide (Input) - Configures MCLK divider to divide by 1, 1.5, 2, or 4.

Reset (Input) - The device enters a low power mode when low.

14 15

Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table.

Analog Power (Input) - Positive power for the analog sectio n s . Analog Ground (Input) - Ground reference. Must be connected to analog ground.

20 21

Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down.

24 22

Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris- tics specification table.

DS686A1 7

CS4270

3. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specificatio ns ar e gu a rant ee d over the Specified Operating Conditions. Typical performance characteristics and spe cif icat ion s ar e de riv e d from measurements taken at nominal supply voltages and T

= 25°C.)

SPECIFIED OPERATING CONDITIONS

(AGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Control Port Interface

Ambient Operating Temperature (Power Applied) (-CZZ)

(-DZZ)

VA VD

VLC

A-CZZ

A-DZZ

3.1

1.7

-10

-40

5.0

3.3

5.25

5.25 +70

+85

V V V

°C °C

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V, All voltages with respect to ground.) (Note 1)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Digital

Control Port Interface

Input Current (Note 2) Analog Input Voltage Digital Input Voltage Control Port Interface

Digital Interface

Ambient Operating Temperature (Power Applied) Storage Temperature

VLC

IND-C

IND-D

T T

VA VD

AC stg

-0.3

+6.0 +6.0 +6.0

-10 - +10 mA

AGND-0.7 - VA+0.7 V

-0.3

-VLC+0.3 VD+0.3

-50 - +95 °C

-65 - +150 °C

V V V

V V

Notes:

1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SRC latch-up.

THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Allowable Junction Temperature Junction to Ambient Thermal Impedance (Note 3)

(Multi-layer PCB) TSSOP

(Multi-layer PCB) SOIC

(Single-layer PCB) TSSOP (Single-layer PCB) SOIC

JA-TM

JA-SM

JA-TS

JA-SS

3. θJA is specified according to JEDEC specifications for multi-layer PCBs.

8 DS686A1

- - 135 °C

70 60

105

°C/W °C/W °C/W °C/W

DAC ANALOG CHARACTERISTICS (CS4270-CZZ)

(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF (see Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

VA = 5V VA = 3.3V

Parameter

Dynamic Range 18 to 24-Bit A-weighted unweighted

16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB 16-Bit 0 dB

-20 dB

-60 dB

Min Typ Max Min Typ Max Unit

99 96 90 87

105 102

96 93

-95

-82

-42

-93

-73

-33

-89

-76

-36

-87

-67

-27

97 94 90 87

103 100

96 93

-95

-80

-40

-93

-73

-33

DAC ANALOG CHARACTERISTICS (CS4270-DZZ)

(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF (see Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

CS4270

-89

-74

-34

-87

-67

-27

dB dB dB dB

dB dB dB dB dB dB

Parameter

Dynamic Range 18 to 24-Bit A-weighted unweighted

16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB 16-Bit 0 dB

-20 dB

-60 dB

4. One-half LSB of triangular PDF dither added to data.

VA = 5V VA = 3.3V

Min Typ Max Min Typ Max Unit

95 92 86 83

105 102

96 93

-95

-82

-42

-93

-73

-33

-85

-72

-32

-83

-63

-23

93 90 86 83

103 100

96 93

-95

-80

-40

-93

-73

-33

-85

-70

-30

-83

-63

-23

dB dB dB dB

dB dB dB dB dB dB

DS686A1 9

DAC ANALOG CHARACTERISTICS - ALL MODES

Parameter Symbol Min Typ Max Unit

Interchannel Isolation (1 kHz)

DC Accuracy

Interchannel Gain Mismatch Gain Drift

Analog Output

Full Scale Output Voltage Max DC Current draw from AOUTA or AOUTB Max AC-Load Resistance (see Figure 2) R Max Load Capacitance (see Figure 2) C Output Impedance of AOUTA and AOUTB

OUTmax

L L

OUT

-100 +100 ppm/°C

0.640•VA 0.688•VA 0.739•VA Vpp

CS4270

-100-dB

- 0.1 0.25 dB

-10-µA

-3-kΩ

-100-pF

-100-Ω

125

100

Ca p a c itive L o a d -- C (pF )

2.5

51015

Safe Operating

Resistive Load -- R (kΩ)

AGND

AOUTx

3.3 µF

out

Figure 1. Output Test Load Figure 2. Maximum Loading

Region

10 DS686A1

CS4270

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) (See Note 5)

Parameter Symbol Min Typ Max Unit

Single-Speed Mode Passband (

to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 7) Group Delay De-emphasis Error (Note 8) Fs = 32 kHz

Note 6) to -0.05 dB corner

Fs = 44.1 kHz

Fs = 48 kHz

Double-Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 7) Group Delay

Quad-Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 7) Group Delay

0 0

-.01 - +.08 dB

.5465 - - Fs

50 - - dB

tgd - 10/Fs - s

0 0

-.05 - +.2 dB

.5770 - - Fs

55 - - dB

tgd - 5/Fs - s

0 0

0 - +0.00004 dB

0.7 - - Fs 51 - - dB

tgd - 2.5/Fs - s

.4780 .4996

+1.5/+0

+.05/-.25

-.2/-.4

.4650 .4982

0.397

0.476

Fs Fs

dB dB dB

Fs Fs

5. Amplitude vs. Frequency plots of this data are available in Section 11. “Appendix” on page 42. See

Figures 19 through 42.

6. Response is clock dependent and will scale with Fs.

7. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

8. De-emphasis is available only in Single-Speed Mode.

DS686A1 11

ADC ANALOG CHARACTERISTICS (CS4270-CZZ)

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.

VA = 5V VA = 3.3V

CS4270

Parameter Symbol

Single-Speed Mode Fs = 48 kHz Dynamic Range

unweighted Total Harmonic Distortion + Noise

-1 dB

A-weighted

(Note 9)

-20 dB

-60 dB

Double-Speed Mode Fs = 96 kHz Dynamic Range

unweighted

A-weighted

40 kHz bandwidth unweighted

Total Harmonic Distortion + Noise (Note 9)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

Quad-Speed Mode Fs = 192 kHz Dynamic Range

unweighted

A-weighted

40 kHz bandwidth unweighted

THD+N

Min Typ Max Min Typ Max Unit

99 96

105 102

-98

-82

-42

105 102

-98

-82

-42

-95

105 102

-92

9693102

-95

-79

-39

102

96 93

-95

-79

-39

-87

102

-89

Total Harmonic Distortion + Noise

40 kHz bandwidth -1 dB

(Note 9)

-1 dB

-20 dB

-60 dB

THD+N

-98

-82

-42

-95

-92

-95

-79

-39

-87

-89

9. Referred to the typical full-scale input voltage.

12 DS686A1

ADC ANALOG CHARACTERISTICS (CS4270-DZZ)

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.

VA = 5V VA = 3.3V

CS4270

Parameter Symbol

Single-Speed Mode Fs = 48 kHz Dynamic Range

unweighted Total Harmonic Distortion + Noise

-1 dB

A-weighted

(Note 10)

-20 dB

-60 dB

Double-Speed Mode Fs = 96 kHz Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

Total Harmonic Distortion + Noise

(Note 10)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

Quad-Speed Mode Fs = 192 kHz Dynamic Range

A-weighted

unweighted

40 kHz bandwidth unweighted

THD+N

Min Typ Max Min Typ Max Unit

9794105

102

-98

-82

-42

105

102

-98

-82

-42

-95

105

102

-90

9491102

-95

-79

-39

102

94 91

-95

-79

-39

-87

102

-87

Total Harmonic Distortion + Noise

40 kHz bandwidth -1 dB

(Note 10)

-1 dB

-20 dB

-60 dB

THD+N

-98

-82

-42

-95

-90

-95

-79

-39

-87

10. Referred to the typical full-scale input voltage.

DS686A1 13

ADC ANALOG CHARACTERISTICS - ALL MODES

CS4270

Interchannel Isolation

-90-dB

DC Accuracy

Interchannel Gain Mismatch Gain Error Gain Drift

-0.1-dB

-3 - 3 %

-100 - +100 ppm/°C

Analog Input Characteristics

Full-scale Input Voltage

Input Impedance

ADC DIGITAL FILTER CHARACTERISTICS

0.54*V A

-300-kΩ

(Note 11)

(Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified)

Parameter Symbol Min Typ Max Unit

Single-Speed Mode

Passband (-0.1 dB) (Note 12) Passband Ripple Stopband (Note 12) Stopband Attenuation Group Delay Interchannel Phase Deviation

Double-Speed Mode

Passband (-0.1 dB) (Note 12) Passband Ripple Stopband (Note 12) Stopband Attenuation Group Delay Interchannel Phase Deviation

Quad-Speed Mode

Passband (-0.1 dB) (Note 12) Passband Ripple Stopband (Note 12) Stopband Attenuation Group Delay Interchannel Phase Deviation

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 13)

Phase Deviation @ 20 Hz (Note 13)

0.56*VA 0.58*V

0 - 0.47 Fs

-0.1 - 0.035 dB

0.58 - - Fs

-95 - - dB

-12/Fs- s

- - 0.0001 deg

0 - 0.45 Fs

-0.1 - 0.035 dB

0.68 - - Fs

-92 - - dB

-9/Fs- s

- - 0.0001 deg

0 - 0.24 Fs

-0.1 - 0.035 dB

0.78 - - Fs

-97 - - dB

-5/Fs- s

- - 0.0001 deg

-120-

-10-deg

Vpp

14 DS686A1

Parameter Symbol Min Typ Max Unit

Passband Ripple Filter Settling Time

--0dB 105/Fs s

11. Plots of this data are contained in Section 11. “Appendix” on page 42. See Figures 43 through 54.

12. The filter frequency response scales precisely with Fs.

13. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

DC ELECTRICAL CHARACTERISTICS

(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; MLCK=12.288 MHz; Master Mode)

Parameter Symbol Min Typ Max Unit

Power Supply

Power Supply Current VA = 5 V (Normal Operation) VA = 3.3 V VD, VLC = 5 V

VD, VLC = 3.3 V

Power Supply Current VA = 5 V (Power-Down Mode) (Note 14) VD, VLC = 5 V

Power Consumption VA = 5 V, VD = VLC= 3.3 V Normal Operation

VA = 5 V, VD = VLC = 5 V Normal Operation Power-Down Mode (Note 14)

Power Supply Rejection Ratio (1 kHz) (Note 15)

Common Mode Voltage

Nominal Common Mode Voltage Maximum DC Current Source/Sink from VQ VQ Output Impedance

Positive Voltage Reference

FILT+ Nominal Voltage Maximum DC Current Source/Sink from FILT+ FILT+ Output Impedance

Mute Control

MUTEA, MUTEB Low-Level Output Voltage MUTEA, MUTEB High-Level Output Voltage Maximum MUTEA & MUTEB Drive Current

31 27 29 20

1.51

0.45

221 255

9.8

PSRR - 60 - dB

VQ - VA/2 - VDC

-1-µA

-25-kΩ

FILT + - VA - VDC

-10-µA

-18-kΩ

-0-V

-VA-V

-3-mA

40 35 38 29

296

323

CS4270

mA mA mA mA

mA mA

mW mW mW

14. Power Down Mode is defined as RST

= Low with all clocks and data lines held static.

15. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.

DS686A1 15

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