CIRRUS LOGIC CS4265 Service Manual

CS4265

105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

D/A Features

z Multi-bit Delta Sigma modulator z 105 dB Dynamic Range z -95 dB THD+N z Up to 192 kHz Sampling Rates z Single-ended Analog Architecture z Volume Control with Soft Ramp

– 0.5 dB Step Size – Zero Crossing Click-free Transitions

z Popguard

– Minimizes the effects of output transients.

z Filtered Line-level Outputs z Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit

–I

S up to 24-bit

– Right Justified 16, 18, 20 and 24-bit

z Selectable 50/15 µs De-emphasis

Technology

A/D Features

z Multi-bit Delta Sigma Modulator z 105 dB Dynamic Range z -95 dB THD+N z Stereo 2:1 Input Multiplexer z Programmable Gain Amplifier (PGA)

– +/- 12 dB gain, 0.5 dB Step Size – Zero Crossing, Click-free Transitions

z Pseudo-differential Stereo Line Inputs z Stereo Microphone Inputs

– +32 dB Gain Stage – Low-noise Bias Supply

z Up to 192 kHz Sampling Rates z Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit – I²S up to 24-bit

z High-pass Filter or DC Offset Calibration

1.8 V to 5 V

Volume

PC M S erial Interfa ce / Loopb ac k

C ontrol

Volume C ontrol

IEC 60958-3 Transmitter

High Pass

F ilte r

High Pass

F ilte r

Serial Audio

Input

Serial Audio

O utput

I2C C ontrol

Data

Reset

Level Translator Level Translator

Re gister Configuration

Advance Product Information

Cirrus Logic, Inc.

www.cirrus.com

3.3 V to 5 V 3.3 V to 5 V

Inte rpolation

Filter

Inte rpolation

Filter

Linear Phase

Anti-Alias Filter

Linear Phase

Anti-Alias Filter

M ultib it

∆Σ Modulator

M u ltibit

∆Σ Modulator

O ve rsa m p ling

Switched Capacitor

DA C and F ilter

Switched Capacitor

DA C and F ilter

Internal Voltage

Reference

M u ltibit

ADC

M u ltibit

ADC

PGA

Control

Mic Bias

MUX

Mute

+32 dB

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Le ft DA C O u tput

Mute C ontrol

Right DAC Output

Transmitter Output

Microphone Bias

Mic Input 1 & 2

Stereo Line Input

NOV ‘04

DS657A2

CS4265

System Features

z Synchronous IEC60958-3 Transmitter

– Up to 192 kHz Sampling Rates –75 Ω Drive Capability

z Serial Audio Data Input Multiplexer z Internal Digital Loopback z Supports Master or Slave Operation z Mute Output Control z Power Down Mode

– Available for A/D, D/A, CODEC, Mic

Preamplifier

z +3.3 V to +5 V Analog Power Supply z +3.3 V to +5 V digital Power Supply z Direct Interface with 1.8 V to 5 V Logic

Levels

z Supports I²C Control Port Interface

General Description

The CS4265 is a highly integrated stereo audio CODEC. The CS4265 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 192 kHz.

A 2:1 stereo input multiplexer is included for selecting between line level or microphone level inputs. The microphone input path includes a +32 dB gain stage and a low noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain or attenuation of ±12 dB in 0.5 dB steps.

The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either slave or master mode.

The D/A converter is based on a 4th-order multi-bit delta sigma modulator with an ultra-linear low pass filter and offers a volume control that operates with a 0.5 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops.

Standard 50/15 µs de-emphasis is available for a

44.1 kHz sample rate for compatibility with digital audio programs mastered using the 50/15 µs pre-emphasis technique.

Integrated level translators allow easy interfacing between the CS4265 and other devices operating over a wide range of logic levels.

ORDERING INFORMATION

CS4265-CNZ, Lead Free -10° to 70° C 32-pin QFN CDB4265 Evaluation Board

2 DS657A2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................... 5

2. CHARACTERISTICS AND SPECIFICATIONS ..... ................ .................................................. 7

SPECIFIED OPERATING CONDITIONS................................................................................. 7

ABSOLUTE MAXIMUM RATINGS........................................................................................... 7

DAC ANALOG CHARACTERISTICS............................ ................................................... ... .... . 8

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE.................. 9

ADC ANALOG CHARACTERISTICS............................ ................................................... ... ... 11

ADC ANALOG CHARACTERISTICS............................ ................................................... ... ... 13

ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 14

DC ELECTRICAL CHARACTERISTICS .......................................... ... ... .... ............................ 15

DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 16

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 17

SWITCHING CHARACTERISTICS - I²C CONTROL PORT................................................... 20

3. TYPICAL CONNECTION DIAGRAM ........................... ... ... ... ................................................ 21

4. APPLICATIONS .................................................................................................................... 22

4.1 Recommended Power-Up Sequence ....................................... ... ... .... ... ... ... .... ... ... ... ... ... 22

4.2 System Clocking ............................. ... ... .... ................................................ ... .... ... ... ... ...... 22

4.2.1 Master Clock ...................................................................................................... 22

4.2.2 Master Mode ...................................................................................................... 23

4.2.3 Slave Mode ........................................................................................................ 23

4.3 High Pass Filter and DC Offset Calibration ........................................... ... ... ................... 23

4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................ 24

4.5 Input Connections ................. .... ... ................................................ ... .... ... ... ... .... ... ... ......... 24

4.5.1 Pseudo-Differential Input .......................................... ... ... ... .... ... ... ... .... ............... 24

4.6 Output Connections ........................................................................................................25

4.7 Output Transient Control ................................................................................................ 25

4.7.1 Power-up .................................. .... ... ................................................ .... ... ... ... ... ... 25

4.7.2 Power-down ....................................................................................................... 25

4.7.3 Serial Interface Clock Changes ......................................................................... 25

4.8 DAC Serial Data Input Multiplexer ..................... ....................................................... ...... 26

4.9 De-Emphasis Filter ......................................................................................................... 26

4.10 Internal Digital Loopback .............................................................................................. 26

4.11 Mute Control ................................................................................................................. 26

4.12 AES3 Transmitter .........................................................................................................27

4.12.1 TxOut Driver ..................................................................................................... 27

4.12.2 Mono Mode Operation ..................................................................................... 27

4.13 I²C Control Port Description and Timing ....................................................................... 28

4.14 Status Reporting ........................................................................................................... 29

4.15 Reset ........................................................................................................................... 29

4.16 Synchronization of Multiple Devices ............................................................................. 30

4.17 Grounding and Power Supply Decoupling .................................................................... 30

4.18 Package Considerations ............................................................................................... 30

5. REGISTER QUICK REFERENCE ............ ... .... ... ... .................................................... ... ......... 31

6. REGISTER DESCRIPTION ................................................................................................... 33

6.1 Chip ID - Register 01h . ... ... ... .... ................................................ ... ... .... ... ... ... .... ... ... .........33

6.2 Power Control - Address 02h ......................................................................................... 33

6.3 DAC Control - Address 03h ............................................................................................ 34

6.4 ADC Control - Address 04h ............................................................................................ 34

6.5 MCLK Frequency - Address 05h .................................................................................... 36

6.6 Signal Selection - Address 06h ...................................................................................... 36

6.7 Channel A PGA Control - Address 07h .......................................................................... 36

6.8 Channel B PGA Control - Address 08h .......................................................................... 37

CS4265

DS657A2 3

CS4265

6.9 ADC Input Control - Address 09h ...................................................................................37

6.10 DAC Channel A Volume Control - Address 0Ah ........................................................... 38

6.11 DAC Channel B Volume Control - Address 0Bh ........................................................... 38

6.12 DAC Control 2 - Address 0Ch . ... ... ... ................................................. ... ... ... .... ...............38

6.13 Status - Address 0Dh ....................................................................................................39

6.14 Status Mask - Address 0Eh .......................................................................................... 40

6.15 Status Mode MSB - Address 0Fh ................................................................................. 40

6.16 Status Mode LSB - Address 10h ...................................................................................40

6.17 Transmitter Control 1 - Address 11h .............................................................................40

6.18 Transmitter Control 2 - Address 12h .............................................................................41

7. PARAMETER DEFINITIONS ................................................................................................. 43

8. PACKAGE DIMENSIONS .....................................................................................................44

9. THERMAL CHARACTERISTICS AND SPECIFICATIONS .................................................44

Appendix A: DAC Filter Plots .........................................................................................45

Appendix B: ADC Filter Plots ..............................................................................................47

Appendix C: External IEC60958-3 Transmitter Components ..............................................49

C.1 IEC60958-3 Transmitter External Components ............................................................. 49

C.2 Isolating Transformer Requirements ........................ ...................................................... 49

Appendix D: Channel Status Buffer Management ............................................................... 50

D.1 IEC60958-3 Channel Status (C) Bit Management .........................................................50

D.1.1 Accessing the E buffer .......................................................................................50

D.1.2 Serial Copy Management System (SCMS) .................... ... ....... ... ... .... ... ... ... ... ... 51

D.1.3 Channel Status Data E Buffer Access ............................................................... 51

D.1.3.1 One Byte mode ...................................................................................51

D.1.3.2 Two Byte mode ...................................................................................51

4 DS657A2

1. PIN DESCRIPTIONS

CS4265

SDA

SCL VLC

RESET

AGND

AINA AINB

TXOUTVDDGND

SGND

MCLK

LRCK

SCLK

303132

Thermal Pad

Top-Down (Through Package) View

32-Pin QFN Package

109

13 14 15 16

AFILTA

AFILTB

FILT+

MICIN1

SDOUT

262728

MICIN2

SDIN1

MICBIAS

SDIN2 TXSDIN

VLS MUTEC AOUTB AOUTA AGND VA

Pin Name # Pin Description

SDA SCL

VLC

RESET VA AGND AINA

AINB SGND AFILTA

AFILTB VQ FILT+ MICIN1

MICIN2

Serial Control Data (Input/Output) - Bidirectional data line for the I²C control port.

Serial Control Port Clock (Input) - Serial clock for the I²C control port.

Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to

the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode when this pin is driven low.

Analog Power (Input) - Positive power for the internal analog section.

Analog Ground (Input) - Ground reference for the internal analog section.

Analog Input (Input) - The full scale level is specified in the ADC Analog Characteristics specification table.

Signal Ground (Input) - Ground reference for the analog line inputs.

10,

Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs.

Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

14,

Microphone Input (Input) - The full scale level is specified in th e ADC Analog Characteristics specification table.

DS657A2 5

CS4265

MICBIAS

VA AGND AOUTA

AOUTB

MUTEC

VLS

TXSDIN SDIN2 SDIN1 SDOUT SCLK

LRCK

MCLK DGND VD TXOUT Thermal Pad

Microphone Bias (Output) - Low noise bias supply for external microphone. Electrical characteristics

are specified in the DC Electrical Characteristics table. Analog Power (Input) - Positive power for the internal analog section.

Analog Ground (Input) - Ground reference for the internal analog section.

19,

Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Characteris- tics specification table.

Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master

clock left/right clock frequency ratio is incorrect, or power-down. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-

face. Refer to the Recommended Operating Conditions for appropriate voltages. Transmitter Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

Serial Audio Data Input 2 (Input) - Input for two’s complement serial audio data.

Serial Audio Data Input 1 (Input) - Input for two’s complement serial audio data.

Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line. Master Clock (Input) -Clock source for the delta-sigma modulators.

Digital Ground (Input) - Ground reference for the internal digital section.

Digital Power (Input) - Positive power for the internal digital section.

Transm itter Line Driver Output (Output) - IEC60958-3 driver output.

Thermal Pad - Thermal relief pad for optimized heat dissipation.

6 DS657A2

CS4265

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to

ground.)

ABSOLUTE MAXIMUM RATINGS (AGND= DGND = 0 V All voltages with respect to ground.) (Note

= 25°C.)

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port

Ambient Operating Temperature (Power Applied) T

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port Input Current (Note 2) I Analog Input Voltage V Digital Input Voltage Logic - Serial Port

Logic - Control Port Ambient Operating Temperature (Power Applied) T Storage Temperature T

VD VLS VLC

VLS

VLC

IND-S

IND-C

INA

stg

3.1

1.71

-10 - +70 °C

-0.3

AGND-0.3 - VA+0.3 V

-0.3

-20 - +85 °C

-65 - +150 °C

5.0

3.3

--±10 mA

5.25

--VLS+0.3

+6.0 +6.0 +6.0 +6.0

VLC+0.3VV

V V V V

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

DS657A2 7

CS4265

DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R

= 10 pF (see Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise speci-

= 3 kΩ,

fied.)

All Speed Modes

Parameter

Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range (Note 3)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 3)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

THD+N

96 99 87 90

102 105

93 96

-95

-82

-42

-93

-73

-33

-89

-76

-36

-87

-67

-27

dB dB dB dB

dB dB dB dB dB dB

Dynamic Performance for VA = 3.3 V

Dynamic Range (Note 3)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 3)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

THD+N

93 96 85 88

102

90 93

-92

-79

-39

-90

-70

-30

-84

-71

-31

-82

-62

-22

dB dB dB dB

dB dB dB dB dB dB

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 0.25 dB Gain Drift - 100 - ppm/°C

Analog Output

Full Scale Output Voltage 0.60*VA 0. 65 *VA 0.70*VA V DC Current draw from an AOUT pin (Note 4) I

OUT

AC-Load Resistance (Note 5) R Load Capacitance (Note 5) C Output Impedance Z

L L

OUT

--10µA

3--kΩ

--100pF

- 100 - Ω

Note: 3. One-half LSB of triangular PDF dither added to data.

4. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors.

5. Guaranteed by design. See Figure 2. R maximum capacitance required for the internal op-amp’s stability. C internal output amp; increasing C

and CL reflect the recommended minimum resistance and

affects the dominant pole of the

beyond 100 pF can cause the internal op-amp to become unstable.

8 DS657A2

CS4265

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Parameter (Note 6,9) Symbol Min Typ Max Unit

Combined Digital and On-chip Analog Filter Response Single Speed Mode

Passband (Note 6) to -0.05 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -.01 - +.08 dB StopBand .5465 - - Fs StopBand Attenuation (Note 7) 50 - - dB Group Delay tgd - 10/Fs - s De-emphasis Error (Note 8) Fs = 44.1 kHz - - +.05/-.25 dB

Combined Digital and On-chip Analog Filter Response Double Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -.05 - +.2 dB StopBand .5770 - - Fs StopBand Attenuation (Note 7) 55 - - dB Group Delay tgd - 5/Fs - s

Combined Digital and On-chip Analog Filter Response Quad Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB StopBand 0.7 - - Fs StopBand Attenuation (Note 7) 51 - - dB Group Delay tgd - 2.5/Fs - s

0 0

.4780 .4996

.4650 .4982

0.397

0.476

Fs Fs

Notes: 6. Filter response is guaranteed by design.

7. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

8. De-emphasis is available only in Single Speed Mode.

9. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 18 to 27) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

DS657A2 9

CS4265

125

3.3 µF

AOUTx

AGND

Figure 1. DAC Output Test Load

100

out

Capacitive Load -- C (pF)

2.5

51015

Safe Operating

Region

Resistive Load -- R (kΩ)

Figure 2. Maximum DAC Loading

10 DS657A2

CS4265

ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): Input test sig-

nal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Fs = 48/96/192 kHz.

Line Level Inputs

Parameter Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range

PGA Setting: -12 dB to +6 dB

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

PGA Setting: +12 dB Gain

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to +6 dB

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

99 96

93 90

THD+N

105 102

99 96 93

-95

-82

-42

-92

-89

dB dB dB

dB dB dB dB

PGA Setting: +12 dB Gain

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

Dynamic Performance for VA = 3.3 V

Dynamic Range

PGA Setting: -12 dB to +6 dB

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

PGA Setting: +12 dB Gain

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

94 91

90 87

-92

-76

-36

-89

102

99 96

96 93 90

-86

dB dB dB dB

dB dB dB

DS657A2 11

CS4265

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to +6 dB

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

PGA Setting: +12 dB Gain

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

Parameter Symbol Min Typ Max Unit

Interchannel Isolation - 90 - dB

Line Level Input Characteristics

Full-scale Input Voltage 0.53*VA 0.56*VA Input Impedance (Note 10) 6.12 6.8 7.48 kΩ

Maximum Interchannel Input Impedance Mismatch

Line Level and Microphone Level Inputs

Parameter Symbol Min Typ Max Unit

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB Gain Error -

Gain Drift -

Programmable Gain Characteristics

Gain Step Size - 0.5 Absolute Gain Step Error - -

THD+N

Line Level Inputs

-5-%

-92

-79

-39

-84

-89

-73

-33

-81

-86

-83

0.59*VA

±5

dB dB dB dB

±100 - ppm/°C

0.4

dB dB

10. Valid when the line level inputs are selected.

12 DS657A2

ADC ANALOG CHARACTERISTICS (cont)

Microphone Level Inputs

Parameter Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range

PGA Setting: -12 dB to 0 dB

A-weighted

unweighted

PGA Setting: +12 dB

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to 0 dB

-1 dB

-20 dB

-60 dB

THD+N

77 74

65 62

CS4265

83 80

71 68

-80

-60

-20

-74

dB dB

dB dB dB

PGA Setting: +12 dB

-1 dB

Dynamic Performance for VA = 3.3 V

Dynamic Range

PGA Setting: -12 dB to 0 dB

A-weighted

unweighted

PGA Setting: +12 dB

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to 0 dB

-1 dB

-20 dB

-60 dB

PGA Setting: +12 dB

-1 dB

Interchannel Isolation - 30 - dB

Microphone Level Input Characteristics

Full-scale Input Voltage 0.013*VA 0.014*VA 0.015*VA V Input Impedance (Note 13) - 50 - kΩ

THD+N

77 74

65 62

-68

83 80

71 68

-80

-60

-20

-68

-74

dB dB

dB dB dB

11. Referred to the typical line level full-scale input voltage

12. Valid for Double and Quad Speed Modes only.

13. Valid when the microphone level inputs are selected.

DS657A2 13

CS4265

ADC DIGITAL FILTER CHARACTERISTICS

Parameter (Note 14, 16) Symbol Min Typ Max Unit

Single Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs Passband Ripple - - 0.035 dB Stopband 0.5688 - - Fs Stopband Attenuation 70 - - dB Total Group Delay (Fs = Output Sample Rate) t

Double Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs Passband Ripple - - 0.025 dB Stopband 0.5604 - - Fs Stopband Attenuation 69 - - dB Total Group Delay (Fs = Output Sample Rate) t

Quad Speed Mode

Passband (-0.1 dB) 0 - 0.2604 Fs Passband Ripple - - 0.025 dB Stopband 0.5000 - - Fs Stopband Attenuation 60 - - dB Total Group Delay (Fs = Output Sample Rate) t

High Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 15) Phase Deviation @ 20 Hz (Note 15) - 10 - Deg Passband Ripple - - 0 dB Filter Settling Time 10

-12/Fs - s

-9/Fs - s

-5/Fs - s

-120-

/Fs s

Hz Hz

Note: 14. Filter response is guaranteed by design.

15. Response shown is for Fs = 48 kHz.

16. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 30 to 41) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

14 DS657A2

CS4265

DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V, all voltages with respect to

ground. MCLK=12.288 MHz; Fs=48 kHz, Master Mode)

Parameter Symbol Min Typ Max Unit

Power Supply Current VA = 5 V (Normal Operation) VA = 3.3 V

VD, VLS, VLC = 5 V

VD, VLS, VLC = 3.3 V

Power Supply Current. VA = 5 V (Power-Down Mode) (Note 17). VLS, VLC, VD=5 V

41 37 39 23

0.50

0.54

50 45 47 28

Power Consumption (Normal Operation). VA, VD, VLS, VLC = 5 V

VA, VD, VLS, VLC = 3.3 V

(Power-Down Mode). VA, VD, VLS, VLC = 5 V

400 198

4.2

485 241

Power Supply Rejection Ratio (1 kHz) (Note 18) PSRR - 60 - dB

VQ Characteristics

Quiescent Voltage VQ - 0.5 x VA - VDC DC Current from VQ (Note 19) I VQ Output Impedance Z

-- 1µA

-23 -kΩ FILT+ Nominal Voltage FILT+ - VA - VDC Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC Current from MICBIAS I

-- 2mA

mA mA mA mA

mA mA

mW mW mW

Notes: 17. Power Down Mode is defines as RESET

input.

18. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.

19. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors.

= Low with all clock and data lines held static and no analog

DS657A2 15

CS4265

DIGITAL INTERFACE CHARACTERISTICS

Parameters (Note 20) Symbol Min Typ Max Units

High-Level Input Voltage Serial Port

Control Port

Low-Level Input Voltage Serial Port

Control Port

High-Level Output Voltage at I

=2 mA Serial Port

Control Port

MUTEC

TXOUT

Low-Level Output Voltage at I

=2 mA Serial Port

Control Port

MUTEC

TXOUT

Input Leakage Current I

OL in

Input Capacitance (Note 21) - - 1 pF Maximum MUTEC Drive Current - 3 - mA

Notes: 20. Serial Port signals include: MCLK, SCLK, LRCK, SDIN1, SDIN2, TXSDIN, SDOUT.

Control Port signals include: SCL, SDA, RESET

21. Guaranteed by design.

0.7xVLS

0.7xVLC

VLS-1.0

VLC-1.0

VA-1.0

VD-1.0

0.2xVLS

0.2xVLC

0.4

--±10µA

V V

V V V V

16 DS657A2

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