CIRRUS LOGIC CS4265 Service Manual

CS4265

105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

D/A Features

z Multi-bit Delta Sigma modulator z 105 dB Dynamic Range z -95 dB THD+N z Up to 192 kHz Sampling Rates z Single-ended Analog Architecture z Volume Control with Soft Ramp

– 0.5 dB Step Size – Zero Crossing Click-free Transitions

z Popguard

– Minimizes the effects of output transients.

z Filtered Line-level Outputs z Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit

–I

S up to 24-bit

– Right Justified 16, 18, 20 and 24-bit

z Selectable 50/15 µs De-emphasis

Technology

A/D Features

z Multi-bit Delta Sigma Modulator z 105 dB Dynamic Range z -95 dB THD+N z Stereo 2:1 Input Multiplexer z Programmable Gain Amplifier (PGA)

– +/- 12 dB gain, 0.5 dB Step Size – Zero Crossing, Click-free Transitions

z Pseudo-differential Stereo Line Inputs z Stereo Microphone Inputs

– +32 dB Gain Stage – Low-noise Bias Supply

z Up to 192 kHz Sampling Rates z Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit – I²S up to 24-bit

z High-pass Filter or DC Offset Calibration

1.8 V to 5 V

Volume

PC M S erial Interfa ce / Loopb ac k

C ontrol

Volume C ontrol

IEC 60958-3 Transmitter

High Pass

F ilte r

High Pass

F ilte r

Serial Audio

Input

Serial Audio

O utput

I2C C ontrol

Data

Reset

Level Translator Level Translator

Re gister Configuration

Advance Product Information

Cirrus Logic, Inc.

www.cirrus.com

3.3 V to 5 V 3.3 V to 5 V

Inte rpolation

Filter

Inte rpolation

Filter

Linear Phase

Anti-Alias Filter

Linear Phase

Anti-Alias Filter

M ultib it

∆Σ Modulator

M u ltibit

∆Σ Modulator

O ve rsa m p ling

Switched Capacitor

DA C and F ilter

Switched Capacitor

DA C and F ilter

Internal Voltage

Reference

M u ltibit

ADC

M u ltibit

ADC

PGA

Control

Mic Bias

MUX

Mute

+32 dB

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Le ft DA C O u tput

Mute C ontrol

Right DAC Output

Transmitter Output

Microphone Bias

Mic Input 1 & 2

Stereo Line Input

NOV ‘04

DS657A2

CS4265

System Features

z Synchronous IEC60958-3 Transmitter

– Up to 192 kHz Sampling Rates –75 Ω Drive Capability

z Serial Audio Data Input Multiplexer z Internal Digital Loopback z Supports Master or Slave Operation z Mute Output Control z Power Down Mode

– Available for A/D, D/A, CODEC, Mic

Preamplifier

z +3.3 V to +5 V Analog Power Supply z +3.3 V to +5 V digital Power Supply z Direct Interface with 1.8 V to 5 V Logic

Levels

z Supports I²C Control Port Interface

General Description

The CS4265 is a highly integrated stereo audio CODEC. The CS4265 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 192 kHz.

A 2:1 stereo input multiplexer is included for selecting between line level or microphone level inputs. The microphone input path includes a +32 dB gain stage and a low noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain or attenuation of ±12 dB in 0.5 dB steps.

The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either slave or master mode.

The D/A converter is based on a 4th-order multi-bit delta sigma modulator with an ultra-linear low pass filter and offers a volume control that operates with a 0.5 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops.

Standard 50/15 µs de-emphasis is available for a

44.1 kHz sample rate for compatibility with digital audio programs mastered using the 50/15 µs pre-emphasis technique.

Integrated level translators allow easy interfacing between the CS4265 and other devices operating over a wide range of logic levels.

ORDERING INFORMATION

CS4265-CNZ, Lead Free -10° to 70° C 32-pin QFN CDB4265 Evaluation Board

2 DS657A2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................... 5

2. CHARACTERISTICS AND SPECIFICATIONS ..... ................ .................................................. 7

SPECIFIED OPERATING CONDITIONS................................................................................. 7

ABSOLUTE MAXIMUM RATINGS........................................................................................... 7

DAC ANALOG CHARACTERISTICS............................ ................................................... ... .... . 8

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE.................. 9

ADC ANALOG CHARACTERISTICS............................ ................................................... ... ... 11

ADC ANALOG CHARACTERISTICS............................ ................................................... ... ... 13

ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 14

DC ELECTRICAL CHARACTERISTICS .......................................... ... ... .... ............................ 15

DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 16

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 17

SWITCHING CHARACTERISTICS - I²C CONTROL PORT................................................... 20

3. TYPICAL CONNECTION DIAGRAM ........................... ... ... ... ................................................ 21

4. APPLICATIONS .................................................................................................................... 22

4.1 Recommended Power-Up Sequence ....................................... ... ... .... ... ... ... .... ... ... ... ... ... 22

4.2 System Clocking ............................. ... ... .... ................................................ ... .... ... ... ... ...... 22

4.2.1 Master Clock ...................................................................................................... 22

4.2.2 Master Mode ...................................................................................................... 23

4.2.3 Slave Mode ........................................................................................................ 23

4.3 High Pass Filter and DC Offset Calibration ........................................... ... ... ................... 23

4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................ 24

4.5 Input Connections ................. .... ... ................................................ ... .... ... ... ... .... ... ... ......... 24

4.5.1 Pseudo-Differential Input .......................................... ... ... ... .... ... ... ... .... ............... 24

4.6 Output Connections ........................................................................................................25

4.7 Output Transient Control ................................................................................................ 25

4.7.1 Power-up .................................. .... ... ................................................ .... ... ... ... ... ... 25

4.7.2 Power-down ....................................................................................................... 25

4.7.3 Serial Interface Clock Changes ......................................................................... 25

4.8 DAC Serial Data Input Multiplexer ..................... ....................................................... ...... 26

4.9 De-Emphasis Filter ......................................................................................................... 26

4.10 Internal Digital Loopback .............................................................................................. 26

4.11 Mute Control ................................................................................................................. 26

4.12 AES3 Transmitter .........................................................................................................27

4.12.1 TxOut Driver ..................................................................................................... 27

4.12.2 Mono Mode Operation ..................................................................................... 27

4.13 I²C Control Port Description and Timing ....................................................................... 28

4.14 Status Reporting ........................................................................................................... 29

4.15 Reset ........................................................................................................................... 29

4.16 Synchronization of Multiple Devices ............................................................................. 30

4.17 Grounding and Power Supply Decoupling .................................................................... 30

4.18 Package Considerations ............................................................................................... 30

5. REGISTER QUICK REFERENCE ............ ... .... ... ... .................................................... ... ......... 31

6. REGISTER DESCRIPTION ................................................................................................... 33

6.1 Chip ID - Register 01h . ... ... ... .... ................................................ ... ... .... ... ... ... .... ... ... .........33

6.2 Power Control - Address 02h ......................................................................................... 33

6.3 DAC Control - Address 03h ............................................................................................ 34

6.4 ADC Control - Address 04h ............................................................................................ 34

6.5 MCLK Frequency - Address 05h .................................................................................... 36

6.6 Signal Selection - Address 06h ...................................................................................... 36

6.7 Channel A PGA Control - Address 07h .......................................................................... 36

6.8 Channel B PGA Control - Address 08h .......................................................................... 37

CS4265

DS657A2 3

CS4265

6.9 ADC Input Control - Address 09h ...................................................................................37

6.10 DAC Channel A Volume Control - Address 0Ah ........................................................... 38

6.11 DAC Channel B Volume Control - Address 0Bh ........................................................... 38

6.12 DAC Control 2 - Address 0Ch . ... ... ... ................................................. ... ... ... .... ...............38

6.13 Status - Address 0Dh ....................................................................................................39

6.14 Status Mask - Address 0Eh .......................................................................................... 40

6.15 Status Mode MSB - Address 0Fh ................................................................................. 40

6.16 Status Mode LSB - Address 10h ...................................................................................40

6.17 Transmitter Control 1 - Address 11h .............................................................................40

6.18 Transmitter Control 2 - Address 12h .............................................................................41

7. PARAMETER DEFINITIONS ................................................................................................. 43

8. PACKAGE DIMENSIONS .....................................................................................................44

9. THERMAL CHARACTERISTICS AND SPECIFICATIONS .................................................44

Appendix A: DAC Filter Plots .........................................................................................45

Appendix B: ADC Filter Plots ..............................................................................................47

Appendix C: External IEC60958-3 Transmitter Components ..............................................49

C.1 IEC60958-3 Transmitter External Components ............................................................. 49

C.2 Isolating Transformer Requirements ........................ ...................................................... 49

Appendix D: Channel Status Buffer Management ............................................................... 50

D.1 IEC60958-3 Channel Status (C) Bit Management .........................................................50

D.1.1 Accessing the E buffer .......................................................................................50

D.1.2 Serial Copy Management System (SCMS) .................... ... ....... ... ... .... ... ... ... ... ... 51

D.1.3 Channel Status Data E Buffer Access ............................................................... 51

D.1.3.1 One Byte mode ...................................................................................51

D.1.3.2 Two Byte mode ...................................................................................51

4 DS657A2

1. PIN DESCRIPTIONS

CS4265

SDA

SCL VLC

RESET

AGND

AINA AINB

TXOUTVDDGND

SGND

MCLK

LRCK

SCLK

303132

Thermal Pad

Top-Down (Through Package) View

32-Pin QFN Package

109

13 14 15 16

AFILTA

AFILTB

FILT+

MICIN1

SDOUT

262728

MICIN2

SDIN1

MICBIAS

SDIN2 TXSDIN

VLS MUTEC AOUTB AOUTA AGND VA

Pin Name # Pin Description

SDA SCL

VLC

RESET VA AGND AINA

AINB SGND AFILTA

AFILTB VQ FILT+ MICIN1

MICIN2

Serial Control Data (Input/Output) - Bidirectional data line for the I²C control port.

Serial Control Port Clock (Input) - Serial clock for the I²C control port.

Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to

the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode when this pin is driven low.

Analog Power (Input) - Positive power for the internal analog section.

Analog Ground (Input) - Ground reference for the internal analog section.

Analog Input (Input) - The full scale level is specified in the ADC Analog Characteristics specification table.

Signal Ground (Input) - Ground reference for the analog line inputs.

10,

Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs.

Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

14,

Microphone Input (Input) - The full scale level is specified in th e ADC Analog Characteristics specification table.

DS657A2 5

CS4265

MICBIAS

VA AGND AOUTA

AOUTB

MUTEC

VLS

TXSDIN SDIN2 SDIN1 SDOUT SCLK

LRCK

MCLK DGND VD TXOUT Thermal Pad

Microphone Bias (Output) - Low noise bias supply for external microphone. Electrical characteristics

are specified in the DC Electrical Characteristics table. Analog Power (Input) - Positive power for the internal analog section.

Analog Ground (Input) - Ground reference for the internal analog section.

19,

Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Characteris- tics specification table.

Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master

clock left/right clock frequency ratio is incorrect, or power-down. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-

face. Refer to the Recommended Operating Conditions for appropriate voltages. Transmitter Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

Serial Audio Data Input 2 (Input) - Input for two’s complement serial audio data.

Serial Audio Data Input 1 (Input) - Input for two’s complement serial audio data.

Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line. Master Clock (Input) -Clock source for the delta-sigma modulators.

Digital Ground (Input) - Ground reference for the internal digital section.

Digital Power (Input) - Positive power for the internal digital section.

Transm itter Line Driver Output (Output) - IEC60958-3 driver output.

Thermal Pad - Thermal relief pad for optimized heat dissipation.

6 DS657A2

CS4265

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to

ground.)

ABSOLUTE MAXIMUM RATINGS (AGND= DGND = 0 V All voltages with respect to ground.) (Note

= 25°C.)

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port

Ambient Operating Temperature (Power Applied) T

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port Input Current (Note 2) I Analog Input Voltage V Digital Input Voltage Logic - Serial Port

Logic - Control Port Ambient Operating Temperature (Power Applied) T Storage Temperature T

VD VLS VLC

VLS

VLC

IND-S

IND-C

INA

stg

3.1

1.71

-10 - +70 °C

-0.3

AGND-0.3 - VA+0.3 V

-0.3

-20 - +85 °C

-65 - +150 °C

5.0

3.3

--±10 mA

5.25

--VLS+0.3

+6.0 +6.0 +6.0 +6.0

VLC+0.3VV

V V V V

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

DS657A2 7

CS4265

DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R

= 10 pF (see Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise speci-

= 3 kΩ,

fied.)

All Speed Modes

Parameter

Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range (Note 3)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 3)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

THD+N

96 99 87 90

102 105

93 96

-95

-82

-42

-93

-73

-33

-89

-76

-36

-87

-67

-27

dB dB dB dB

dB dB dB dB dB dB

Dynamic Performance for VA = 3.3 V

Dynamic Range (Note 3)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 3)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

THD+N

93 96 85 88

102

90 93

-92

-79

-39

-90

-70

-30

-84

-71

-31

-82

-62

-22

dB dB dB dB

dB dB dB dB dB dB

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 0.25 dB Gain Drift - 100 - ppm/°C

Analog Output

Full Scale Output Voltage 0.60*VA 0. 65 *VA 0.70*VA V DC Current draw from an AOUT pin (Note 4) I

OUT

AC-Load Resistance (Note 5) R Load Capacitance (Note 5) C Output Impedance Z

L L

OUT

--10µA

3--kΩ

--100pF

- 100 - Ω

Note: 3. One-half LSB of triangular PDF dither added to data.

4. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors.

5. Guaranteed by design. See Figure 2. R maximum capacitance required for the internal op-amp’s stability. C internal output amp; increasing C

and CL reflect the recommended minimum resistance and

affects the dominant pole of the

beyond 100 pF can cause the internal op-amp to become unstable.

8 DS657A2

CS4265

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Parameter (Note 6,9) Symbol Min Typ Max Unit

Combined Digital and On-chip Analog Filter Response Single Speed Mode

Passband (Note 6) to -0.05 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -.01 - +.08 dB StopBand .5465 - - Fs StopBand Attenuation (Note 7) 50 - - dB Group Delay tgd - 10/Fs - s De-emphasis Error (Note 8) Fs = 44.1 kHz - - +.05/-.25 dB

Combined Digital and On-chip Analog Filter Response Double Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -.05 - +.2 dB StopBand .5770 - - Fs StopBand Attenuation (Note 7) 55 - - dB Group Delay tgd - 5/Fs - s

Combined Digital and On-chip Analog Filter Response Quad Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB StopBand 0.7 - - Fs StopBand Attenuation (Note 7) 51 - - dB Group Delay tgd - 2.5/Fs - s

0 0

.4780 .4996

.4650 .4982

0.397

0.476

Fs Fs

Notes: 6. Filter response is guaranteed by design.

7. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

8. De-emphasis is available only in Single Speed Mode.

9. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 18 to 27) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

DS657A2 9

CS4265

125

3.3 µF

AOUTx

AGND

Figure 1. DAC Output Test Load

100

out

Capacitive Load -- C (pF)

2.5

51015

Safe Operating

Region

Resistive Load -- R (kΩ)

Figure 2. Maximum DAC Loading

10 DS657A2

CS4265

ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): Input test sig-

nal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Fs = 48/96/192 kHz.

Line Level Inputs

Parameter Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range

PGA Setting: -12 dB to +6 dB

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

PGA Setting: +12 dB Gain

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to +6 dB

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

99 96

93 90

THD+N

105 102

99 96 93

-95

-82

-42

-92

-89

dB dB dB

dB dB dB dB

PGA Setting: +12 dB Gain

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

Dynamic Performance for VA = 3.3 V

Dynamic Range

PGA Setting: -12 dB to +6 dB

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

PGA Setting: +12 dB Gain

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

94 91

90 87

-92

-76

-36

-89

102

99 96

96 93 90

-86

dB dB dB dB

dB dB dB

DS657A2 11

CS4265

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to +6 dB

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

PGA Setting: +12 dB Gain

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

Parameter Symbol Min Typ Max Unit

Interchannel Isolation - 90 - dB

Line Level Input Characteristics

Full-scale Input Voltage 0.53*VA 0.56*VA Input Impedance (Note 10) 6.12 6.8 7.48 kΩ

Maximum Interchannel Input Impedance Mismatch

Line Level and Microphone Level Inputs

Parameter Symbol Min Typ Max Unit

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB Gain Error -

Gain Drift -

Programmable Gain Characteristics

Gain Step Size - 0.5 Absolute Gain Step Error - -

THD+N

Line Level Inputs

-5-%

-92

-79

-39

-84

-89

-73

-33

-81

-86

-83

0.59*VA

±5

dB dB dB dB

±100 - ppm/°C

0.4

dB dB

10. Valid when the line level inputs are selected.

12 DS657A2

ADC ANALOG CHARACTERISTICS (cont)

Microphone Level Inputs

Parameter Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range

PGA Setting: -12 dB to 0 dB

A-weighted

unweighted

PGA Setting: +12 dB

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to 0 dB

-1 dB

-20 dB

-60 dB

THD+N

77 74

65 62

CS4265

83 80

71 68

-80

-60

-20

-74

dB dB

dB dB dB

PGA Setting: +12 dB

-1 dB

Dynamic Performance for VA = 3.3 V

Dynamic Range

PGA Setting: -12 dB to 0 dB

A-weighted

unweighted

PGA Setting: +12 dB

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to 0 dB

-1 dB

-20 dB

-60 dB

PGA Setting: +12 dB

-1 dB

Interchannel Isolation - 30 - dB

Microphone Level Input Characteristics

Full-scale Input Voltage 0.013*VA 0.014*VA 0.015*VA V Input Impedance (Note 13) - 50 - kΩ

THD+N

77 74

65 62

-68

83 80

71 68

-80

-60

-20

-68

-74

dB dB

dB dB dB

11. Referred to the typical line level full-scale input voltage

12. Valid for Double and Quad Speed Modes only.

13. Valid when the microphone level inputs are selected.

DS657A2 13

CS4265

ADC DIGITAL FILTER CHARACTERISTICS

Parameter (Note 14, 16) Symbol Min Typ Max Unit

Single Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs Passband Ripple - - 0.035 dB Stopband 0.5688 - - Fs Stopband Attenuation 70 - - dB Total Group Delay (Fs = Output Sample Rate) t

Double Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs Passband Ripple - - 0.025 dB Stopband 0.5604 - - Fs Stopband Attenuation 69 - - dB Total Group Delay (Fs = Output Sample Rate) t

Quad Speed Mode

Passband (-0.1 dB) 0 - 0.2604 Fs Passband Ripple - - 0.025 dB Stopband 0.5000 - - Fs Stopband Attenuation 60 - - dB Total Group Delay (Fs = Output Sample Rate) t

High Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 15) Phase Deviation @ 20 Hz (Note 15) - 10 - Deg Passband Ripple - - 0 dB Filter Settling Time 10

-12/Fs - s

-9/Fs - s

-5/Fs - s

-120-

/Fs s

Hz Hz

Note: 14. Filter response is guaranteed by design.

15. Response shown is for Fs = 48 kHz.

16. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 30 to 41) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

14 DS657A2

CS4265

DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V, all voltages with respect to

ground. MCLK=12.288 MHz; Fs=48 kHz, Master Mode)

Parameter Symbol Min Typ Max Unit

Power Supply Current VA = 5 V (Normal Operation) VA = 3.3 V

VD, VLS, VLC = 5 V

VD, VLS, VLC = 3.3 V

Power Supply Current. VA = 5 V (Power-Down Mode) (Note 17). VLS, VLC, VD=5 V

41 37 39 23

0.50

0.54

50 45 47 28

Power Consumption (Normal Operation). VA, VD, VLS, VLC = 5 V

VA, VD, VLS, VLC = 3.3 V

(Power-Down Mode). VA, VD, VLS, VLC = 5 V

400 198

4.2

485 241

Power Supply Rejection Ratio (1 kHz) (Note 18) PSRR - 60 - dB

VQ Characteristics

Quiescent Voltage VQ - 0.5 x VA - VDC DC Current from VQ (Note 19) I VQ Output Impedance Z

-- 1µA

-23 -kΩ FILT+ Nominal Voltage FILT+ - VA - VDC Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC Current from MICBIAS I

-- 2mA

mA mA mA mA

mA mA

mW mW mW

Notes: 17. Power Down Mode is defines as RESET

input.

18. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.

19. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors.

= Low with all clock and data lines held static and no analog

DS657A2 15

CS4265

DIGITAL INTERFACE CHARACTERISTICS

Parameters (Note 20) Symbol Min Typ Max Units

High-Level Input Voltage Serial Port

Control Port

Low-Level Input Voltage Serial Port

Control Port

High-Level Output Voltage at I

=2 mA Serial Port

Control Port

MUTEC

TXOUT

Low-Level Output Voltage at I

=2 mA Serial Port

Control Port

MUTEC

TXOUT

Input Leakage Current I

OL in

Input Capacitance (Note 21) - - 1 pF Maximum MUTEC Drive Current - 3 - mA

Notes: 20. Serial Port signals include: MCLK, SCLK, LRCK, SDIN1, SDIN2, TXSDIN, SDOUT.

Control Port signals include: SCL, SDA, RESET

21. Guaranteed by design.

0.7xVLS

0.7xVLC

VLS-1.0

VLC-1.0

VA-1.0

VD-1.0

0.2xVLS

0.2xVLC

0.4

--±10µA

V V

V V V V

16 DS657A2

CS4265

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic ‘0’ = DGND = 0 V;

Logic ‘1’ = VL, C

Sample Rate Single Speed Mode

MCLK Specifications

MCLK Frequency f MCLK Input Pulse Width High/Low t MCLK Output Duty Cycle 45 50 55 %

Master Mode

LRCK Duty Cycle - 50 - % SCLK Duty Cycle - 50 - % SCLK falling to LRCK edge t SCLK falling to SDOUT valid t SDIN valid to SCLK rising setup time t SCLK rising to SDIN hold time t

Slave Mode

LRCK Duty Cycle 40 50 60 % SCLK Period

= 20 pF) (Note 22)

Parameter Symbol Min Typ Max Unit

Double Speed Mode

Quad Speed Mode

Single Speed Mode

Double Speed Mode

Quad Speed Mode

Fs Fs Fs

mclk 1.024 - 51.200 MHz clkhl 8--ns

slr sdo sdis

sdih

sclkw

100

50 100 200

-10 - 10 ns 0 - 32 ns

16 - - ns 20 - - ns

-------------------- -

128()Fs

----------------- -

64()Fs

----------------- 64()Fs

kHz kHz kHz

SCLK Pulse Width High t SCLK Pulse Width Low t SCLK falling to LRCK edge t SCLK falling to SDOUT valid t SDIN valid to SCLK rising setup time t SCLK rising to SDIN hold time t

sclkh

sclkl

slr

sdo sdis sdih

30 - - ns 48 - - ns

-10 - 10 ns 0 - 32 ns

16 - - ns 20 - - ns

Notes: 22. See figures 3 and 4 on page 18.

DS657A2 17

LRCK

Output

SCLK

Output

SDOUT

sdo

CS4265

slr

SDIN

LRCK

Input

SCLK

Input

SDOUT

sdis

Figure 3. Master Mode Serial Audio Port Timing

sclkh

sclkw

slr

sdo

sdih

sclkl

sdis

SDIN

Figure 4. Slave Mode Serial Audio Port Timing

18 DS657A2

sdih

CS4265

Left Channel

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Channel A - Left

+5 +4

Figure 5. Format 0, Left Justified up to 24-Bit Data

Channel A - Left

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

Figure 6. Format 1, I²S up to 24-Bit Data

LRCK

SCLK

Channel A - Left

Left Channel

LSB

MSB

-1 -2 -3 -4

MSB

-1 -2 -3 -4

Channel B - Right

Right Channel

+3 +2 +1

+5 +4

Right Channel

Channel B - Right

+3 +2 +1

+5 +4

Channel B - Right

Right Channel

LSB

SDATA

+4 +3 +2

LS B +5

MSB -1 -2 -3 -4 -5

32 clocks

-6

+1 LSB

MSB -1 -2 -3 -4

-5

-6

Figure 7. Format 2, Right Justified 16-Bit Data.

Format 3, Right Justified 24-Bit Data.

+4 +3 +2

+1 LSB

DS657A2 19

SWITCHING CHARACTERISTICS - I²C CONTROL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VLC, C

Parameter Symbol Min Max Unit

SCL Clock Frequency f RESET

Rising Edge to Start t Bus Free Time Between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 23) t SDA Setup time to SCL Rising t Rise Time of SCL and SDA (Note 24) t Fall Time SCL and SDA (Note 24) t Setup Time for Stop Condition t Acknowledge Delay from SCL Falling t

=30pF)

scl irs

buf

hdst

low high sust

hdd sud

rc fc

susp

ack

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 0-µs

250 - ns

-1µs

-300ns

4.7 - µs

300 1000 ns

CS4265

Notes: 23. Data must be held for sufficient time to bridge the transition time, t

24. Guaranteed by design.

RST

irs

Stop Start

SDA

SCL

buf

hdst

lo w

high

hdd

sud

ack

Figure 8. Control Port Timing - I²C Format

, of SCL.

Repeated

Start

sust

hdst

Stop

susp

20 DS657A2

3. TYPICAL CONNECTION DIAGRAM

CS4265

+3.3V to +5V

+1.8V

to +5V

Digital Audio

Processor

Digital Audio

Output

Micro-

Controller

2 kΩ

+1.8V

Note 1

to +5V

Note 1: Resistors are required for I²C control port operation

Note 3: The value of RL is dictated by the microphone carteridge.

Note 4: Sets the LSB of the 7-bit chip address. See the I²C Control Port Description and Timing section.

0.1 µF

47 kΩ

Note 4

2 kΩ

10 µF

0.1 µF

VLS

SDOUT SDIN1

SDIN2

TXSDIN

MCLK SCLK LRCK

TXOUT

RST

SCL

SDA

VLC

CS4265

DGND

0.1 µF

10 µF

+3.3V to +5V

VAVD

10 kΩ

1800 pF

Mute Drive

470Ω

Optional

Analog Muting

470Ω

470

ext

()

4704

RFs

ext

10 µF

100 Ω

100 kΩ

Left Analog Input 1

MUTEC

AOUTA

AOUTB

AIN1A

3.3 µF

Note 2 : For best response to Fs/2 :

This circuitry is intended for applications where the CS4265 connects directly to an unbalanced output of the design. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations.

10 µF

SGND S i gnal Ground

1800 pF

100 kΩ

AIN1B

MICIN1 MICIN2

MICBIAS

10 µF

Note 3

10 µF

100 Ω

LRL

Right Analog Input 1

Microphone Input 1 Microphone Input 2

FILT+

10 µF

0.1 µF

AGND AGND

AFILTA

0.1 µF

2.2nF

47 µF

2.2nF

AFILTB

* Capacitors must be C0G or equivalent

10 µF

See Note 2

ext

Figure 9. Typical Connection Diagram

DS657A2 21

CS4265

4. APPLICATIONS

4.1 Recommended Power-Up Sequence

1) Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to its default settings.

2) Bring RESET will be accessible.

3) The desired register settings can be loaded while the PDN bit remains set.

4) Clear the PDN bit to initiate the power-up sequence.

4.2 System Clocking

The CS4265 will operate at sampling frequencies from 4 kHz to 200 k Hz. This range is divided into three speed modes as shown in Table 1 below.

high. The device will remain in a low power state with the PDN bit set by default. The control port

Mode Sampling Frequency

Single Speed 4-50 kHz

Double Speed 50-100 kHz

Quad Speed 100-200 kHz

Table 1. Speed Modes

4.2.1 Master Clock

MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The FM bits (see page 35) and the MCLK Freq bits (see page 36) configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies.

22 DS657A2

CS4265

LRCK

(kHz)

44.1 48 64

88.2 96

128

176.4 192

Mode

64x 96x 128x 192x 256x 384x 512x 768x 1024x

- ---8.1920 12.2880 16.3840 24.5760 32.7680

- ---11.2896 16.9344 22.5792 33.8680 45.1584

- ---12.2880 18.4320 24.5760 36.8640 49.1520

- - 8.1920 12.2880 16.3840 24.5760 32.7680 - -

- - 11.2896 16.9344 22.5792 33.8680 45.1584 - -

- - 12.2880 18.4320 24.5760 36.8640 49.1520 - -

8.1920 12.2880 16.3840 24.5760 32.7680 - - - -

11.2896 16.9344 22.5792 33.8680 45.1584 - - - -

12.2880 18.4320 24.5760 36.8640 49.1520 - - - -

QSM

MCLK (MHz)

DSM SSM

Table 2. Common Clock Frequencies

4.2.2 Master Mode

As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 10.

MC LK F req Bits

MC LK

÷1

÷1.5

÷2

÷3

÷4

000

001

010

011

100

÷256

÷128

÷64

÷4

÷2

÷1

FM Bits

LRC K

SCLK

Figure 10. Master Mode Clocking

4.2.3 Slave Mode

In Slave mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.

The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to 128x, 64x, 48x or 32x Fs depending on the desired speed mode. Refer to Table 3 for required clock ratios.

Single Speed Double Speed Quad Speed

SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x

Table 3. Slave Mode Serial Bit Clock Ratios

4.3 High Pass Filter and DC Offset Calibration

When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven into the A/D converter. The CS4265 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.

DS657A2 23

CS4265

The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPFFreeze bit (see page 35) is set during normal o peration, the current value of the DC offset for the each channe l is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:

1) Running the CS4265 with the high pass filter enabled until the filter settles. See the ADC Digital Filter Characteristics section for filter settling time.

2) Disabling the high pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS4265.

4.4 Analog Input Multiplexer, PGA, and Mic Gain

The CS4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA). The input multiplexer is able to select either a line-level input source, or a mic-level input source and route it to the PGA. The mic-level input passes through a +32 dB gain stage prior to the input multiplexer, allowing it to be used for microphone level signals without the need for any external gain. The PGA sta ge provides 12 dB of gain or attenuation in 0.5 dB steps. Figure 11 shows the architecture of the input multiplexer, PGA, and mic gain stages.

AINA

MICIN1

AINB

MICIN2

+32 dB

MUX

Analog Input

Selection Bits

MUX

PGA

Channel A

PGA Gain Bits

Channel B

PGA Gain Bits

PGA

Out to ADC Channel A

Out to ADC Channel B

Figure 11. Analog Input Architecture

The “Analog Input Selection (Bit 0)” section on page 38 outlines the bit settings necessary to control the input multiplexer and mic gain. “Channel A PGA Control - Address 07h” on page 36 and “Channel B PGA Control - Address 08h” on page 37 outlines the register settings necessary to control the PGA. By default, the line level input is selected by the input multiplexer, and the PGA is set to 0 dB.

4.5 Input Connections

The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog input pairs should be left unconnected.

× 6.144 MHz) the digital

4.5.1 Pseudo-Differential Input

The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a pseudodifferential reference signal. This feature allows for common mode noise rejection with single-ended signals. Figure 12 shows a basic diagram outlining the internal implementation of the pseudo-differential input stage. The Typical Connection Diagram shows the recommended pseudo-d ifferential input topology. If pseudo-differential inp ut

24 DS657A2

CS4265

functionality is not required, simply connect the SGND pin to AGND through the parallel combination of a 10 µF and a 0.1 µF capacitor.

CS4265

AINA

SGND

AINB

Note: If pseudo-differential input functionality is not required, the

10 µF

0.1 µF

connections shown with dashed line should be added.

Figure 12. Pseudo-Differential Input Stage

In to P GA

4.6 Output Connections

The CS4265 DAC’s implement a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is shown in the “DAC Filter Plots” section beginning on page 45. The recommended external analog circuitry is shown in the Typical Connection Diagram.

The CS4265 DAC is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.

4.7 Output Transient Control

The CS4265 uses Popguard™ technology to minimize the effects of output transients during power-up and powerdown. This technique eliminates the audio transients commonly prod uced by single-ended single- supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation.

4.7.1 Power-up

When the device is initially powered-up, the DAC outputs AOUTA and AOUTB are clamped to VQ which is initially low. After the PDN bit is released (set to ‘0’), the outputs begin to ramp with VQ towards the nominal quiescent vo ltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Audio output will begin after approximately 2000 sample periods.

4.7.2 Power-down

To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, either the PDN should be set or the device should be reset about 250 ms before removing power. During this time, the voltage on VQ and the DAC outputs will gradually discharge to GND. If power is removed before this 250 ms time period has passed a transient will occur when the VA supply drops below that of VQ. There is no minimum time for a power cycle, power may be re-applied at any time.

4.7.3 Serial Interface Clock Changes

When changing the clock ratio or sample rate it is recommended that zero data (or near zero data) be present on the selected SDIN pin for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it’s zero data state.

DS657A2 25

CS4265

4.8 DAC Serial Data Input Multiplexer

The CS4265 contains a 2-to-1 serial data input multiplexer. This allows two separate data sources to be input into the DAC without the use of any external multiplexing components. The “DAC SDIN Source (Bit 7)” section on page 36 describes the control port settings necessary to control the multiplexer.

4.9 De-Emphasis Filter

The CS4265 includes on-chip digital de -emphasis optimized for a sample rate of 44 .1 kHz. The filter response is shown in Figure 13. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 6.3.3 for de-emphasis control.

The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction.

De-emphasis is only available in Single Speed Mode.

Gain

T1=50 µs

0dB

T2 = 15 µs

-10dB

F1 F2

3.183 kHz 10.61 kHz

Figure 13. De-Emphasis Curve

Frequency

4.10 Internal Digital Loopback

The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (06h - See page 36).

When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4265. Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin in the format selected by the ADC_DIF bit in register 04h.

4.11 Mute Control

The MUTEC pin becomes active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is incorrect, and during power-down. The M UTEC add off-chip mute capability.

Use of the Mute Control function is not mandatory but recommended for designs requiri ng the a bsolute m inimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle

pin is intended to be used as control for an external mute circuit in order to

26 DS657A2

CS4265

channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTEC pin is an activelow CMOS driver. See Figure 14 below for a suggested active-low mute circuit.

AOUT

CS4265

MUT E C

LPF

Couple

-V

MMUN2111LT1

47 kΩ

-V

560 Ω

10 kΩ

2 kΩ

Audio

Out

Figure 14. Suggested Active-Low Mute Circuit

4.12 AES3 Transmitter

The CS4265 includes an IEC60958-3 digital audio transmitter. A comprehensive buffering scheme provides write access to the channel status data. This buffering scheme is described in “Channel Status Buffer Management” on page 50.

The IEC60958-3 transmitter encodes and transmits audio and digital data according to the IEC60958-3 (S/PDIF) interface standard. Audio and control data are multiplexed together and bi-phase mark encoded. The resulting bit stream is driven to an output connector either directly or through a transformer. Th e tr a nsm itt er is clocked from the clock input pin MCLK.

The channel status (C) bits in the transmitted data stream are taken from stor age areas within the CS4265. The user can manually access the internal storage of the CS4265 to configure the transmitted channel status data. The section “Channel Status Buffer Management” on page 50 describes the method of manually accessing the storage areas. The CS4265 transmits all ‘0’s in the user (U) data fields.

4.12.1 TxOut Driver

The line driver is a low skew, low impedance, single-ended output capable of driving cables directly. The driver is set to ground during reset (RESET

= LOW), when no transmit clock is provided, and optionally under the control of a register bit. The CS4265 also allows immediate muting of the IEC60958-3 transmitter a udio data through a control register bit.

External components are used to terminate and isolate the external cable from the CS4265 . These components are detailed in “External IEC60958-3 Transmitter Components” on page 49.

4.12.2 Mono Mode Operation

An IEC60958-3 stream may be used in more than on e way to tr ansm it 192 kHz sample rate data. One method is to double the frame rate of the current format. This results is a stereo signal with a sample rate of 192 kHz. An alternate method is implemented using the two sub-frames in a 96 kHz frame rate IEC60958-3 signal to carry consecutive samples of a mono signal, resulting in a 192 kHz sample rate stream. This allows older equipment, whose IEC60958-3 transmitters and receivers are not rated for 192kHz frame rate operation, to handle 192 kHz sample

DS657A2 27

CS4265

rate information. In this “mono mode”, two cables are needed for stereo data transfer. The CS4265 offers mono mode operation. The CS4265 is set placed into and out of mono mode with the MMT control bit.

In mono mode, the input port will run at the audio sample rate (Fs), while the IEC60958-3 transmitter frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for transmission on the A and B sub-frames, and the channel status block transmitted is also selectable.

Using mono mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains both left and right audio data words. The “mono mode” IEC60958-3 output stream may also be achieved by keeping the CS4265 in normal stereo mode, and placing consecutive audio samples in the left and ri ght positions in an incoming 96 kHz word rate data stream.

4.13 I²C Control Port Description and Timing

The control port is used to access the registers, allowing the CS4265 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.

SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 kΩ pull-up or pulldown on the SDOUT pin will set AD0, the least significant bit of the chip address. A pull-up to VLS will set AD0 to ‘1’ and a pull-down to DGND will set AD0 to ‘0’. The state of SDOUT is sensed and AD0 is set upon the release of RESET.

The signal timings for a read and write cycle are shown in Figure 15 and Figure 16. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4265 after a Start condition consists of a 7 bit chip address field and a R/W are fixed at 100111. To communicate with a CS4265, the chip address field, which is the first byte sent to the CS4265, should match 100111 followed by the setting of AD0. The eighth bit of the address is the R/W operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4265 after each input byte is read, and is input to the CS4265 fro m the microcontroller after each transmitted byte.

bit (high for a read, low for a write). The uppe r 6 bits o f the 7-b it addre ss field

bit. If the

DATA +1

DATA +n

ACKACKACK

STOP

SCL

SDA

0 1 2 3 8 9 1 2 16 17 18 1910 11 13 14 15 27 28

CHIP ADDRESS (WRITE) MAP BYTE DATA

1 0 0 1 1 1 AD0 0

START

4 5 6 7 24 25

INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

ACK

Figure 15. Control Port Timing, I²C Write

28 DS657A2

CS4265

168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24

STOP

ACK

START

CHIP ADDRESS (READ)

1 0 0 1 1 1 AD0 1

26 27 28

DATA

7 0 7 0 7 0

ACK

DATA +1

ACK

DATA + n

ACK

STOP

SCL

SDA

2 3 10 11 17 18 19 25

CHIP ADDRESS (WRITE)

1 0 0 1 1 1 AD0 0

START

MAP BYTE

INCR 6 5 4 3 2 1 0

ACK

Figure 16. Control Port Timing, I²C Read

Since the read operation can n ot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition. Send 100111x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100111x1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition.

Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.

4.14 Status Reporting

The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status register, as listed in the status register descriptions. See “ Status - Address 0Dh” on page 39. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.

4.15 Reset

When RESET is low, the CS4265 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RESET desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low power state and begin operation.

The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RESET

pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this voltage reference ramp delay, both SDOUT and DAC outputs will be automatically muted.

is high, the control port becomes operational and the

DS657A2 29

CS4265

It is recommended that RESET be activated if the analog or digital supplies drop below th e recommended operating condition to prevent power glitch related issues.

4.16 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS4265’s in the system. If only one master clock source is needed, on e so lu tion is to pl ace one CS4 2 65 in Ma st er Mode , an d slave all of the other CS4265’s to the one master. If multiple master clock sources are needed, a possible solution would b e to supply all clocks from the same external source and time the CS4265 reset with the inactive edge o f master clock. This will ensure that all converters begin sampling on the same clock edge.

4.17 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4265 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 9 shows the recommended power arrange ments, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the syst em logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS4265 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CS4265 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS4265 digital outputs only to CMOS inputs.

4.18 Package Considerations

The CS4265 is available in the compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS4265 evaluation board demonstrates the optimum thermal pad and via configuration.

30 DS657A2

CS4265

5. REGISTER QUICK REFERENCE

This table shows the register names and their associated default values.

Addr Function 7 6 5 4 3 2 1 0

01h Chip ID

02h Power Control Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC PDN_DAC PDN

03h DAC Control 1

04h ADC Control

05h MCLK

Frequency

06h Signal Selec-

tion

07h PGA Ch B Gain

Control

08h PGA Ch A Gain

Control

09h Analog Input

Control

0Ah DAC Ch A Vol-

ume Control

0Bh DAC Ch B Vol-

ume Control

0Ch DAC Contro l 2 DACSoft DACZero InvertDAC Reserved Reserved Reserved Reserved Reserved

0Dh Status Reserved Reserved Reserved EFTC ClkErr Reserved ADCOvfl ADCUndrfl

0Eh Status Mask Reserved Reserved Reserved EFTCM ClkErrM Reserved ADCOvflM ADCUndrflM

0Fh Status Mode

MSB

10h St at us Mode

LSB

PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

1101 0 0 0 1

0000 0 0 0 1

Reserved Reserved DAC_DIF1 DAC_DIF0 Reserved MuteDAC DeEmph

0000 1 0 0 0

FM1 FM0 Reserved ADC_DIF Reserved MuteADC HPFFreeze M/S

0000 0 0 0 0

Reserved

0000 0 0 0 0

SDINSel Reserved Reserved Reserved Reserved Reserved LOOP Reserved

0100 0 0 0 0

Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0

0000 0 0 0 0

Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0

0000 0 0 0 0

Reserved Reserved Reserved PGASoft PGAZero Reserved Reserved Select

0001 1 0 0 1

Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

0000 0 0 0 0

Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

0000 0 0 0 0

1100 0 0 0 0

0000 0 0 0 0

Reserved Reserved Reserved EFTC1 ClkErr1 Reserved ADCOvfl1 ADCUndrfl1

0000 0 0 0 0

Reserved Reserved Reserved EFTC0 ClkErr0 Reserved ADCOvfl0 ADCUndrfl0

0000 0 0 0 0

MCLK

Freq2

MCLK

Freq1

MCLK

Freq0

Reserved Reserved Reserved Reserved

Reserved

DS657A2 31

CS4265

Addr Function 7 6 5 4 3 2 1 0

11h Transmitter

Control 1

12h Transmitter

Control 2

13h -

C-Data Buffer

2Ah

Reserved EFTCI CAM Reserved Reserved Reserved Reserved Reserved

0000 0 0 0 0

Tx_DIF1 Tx_DIF0 TxOff TxMute V MMT MMTCS MMTLR

0000 0 0 0 0

--- - - - - -

32 DS657A2

CS4265

6. REGISTER DESCRIPTION

6.1 Chip ID - Register 01h

B7 B6 B5 B4 B3 B2 B1 B0

PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

Function:

This register is Read-Only. Bits 7 through 4 are the part number ID which is 1101b (0Dh) and the remaining bits (3 through 0) are for the chip revision.

6.2 Power Control - Address 02h

76543210

Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC PDN_DAC PDN

6.2.1 Freeze (Bit 7)

Function:

This function allows modifications to be made to certain control port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed in Table 4 below.

Name Register Bit(s)

MuteDAC 03h 2 MuteADC 04h 2

Gain[5:0] 07h 5:0 Gain[5:0] 08h 5:0

Vol[7:0] 0Ah 7:0 Vol[7:0] 0Bh 7:0 TxMute 0Eh 4

6.2.2 Power Down MIC (Bit 3)

Function:

The microphone preamplifier block will enter a low-power state whenever this bit is set.

6.2.3 Power Down ADC (Bit 2)

Function:

The ADC pair will remain in a reset state whenever this bit is set.

6.2.4 Power Down DAC (Bit 1)

Function:

The DAC pair will remain in a reset state whenever this bit is set.

Table 4. Freeze-able Bits

6.2.5 Power Down Device (Bit 0)

Function:

DS657A2 33

CS4265

The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation can oc cur. The contents of the control re gisters are retained when the device is in power-down.

6.3 DAC Control - Address 03h

76543210

Reserved Reserved DAC_DIF1 DAC_DIF0 Reserved MuteDAC DeEmph

6.3.1 DAC Digital Interface Format (Bits 5:4)

Function:

The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital Interface Format and the options are detailed in Table 5 and Figures 5-7.

Table 5. DAC Digital Interface Formats

DAC_DIF1 DAC_DIF0 Description Format Figure

0 0 Left Justified, up to 24-bit data (default) 0 5 01

1 0 Right Justified, 16-bit Data 2 7 1 1 Right Justified, 24-bit Data 3 7

S, up to 24-bit data

6.3.2 Mute DAC (Bit 2)

Reserved

Function:

The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is active high, it should be noted that the MUTEC pin is active low. Th e common mode voltage on the outputs will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the DACSoft and DACZero bits in the DAC Control 2 register.

6.3.3 De-Emphasis Control (Bit 1)

Function:

The standard 50/15 µs digital de-emphasis filter response, Figure 17, may be implemented for a sample rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 6 below. NOTE: De-emphasis is available only in Single-Speed Mode.

Table 6. De-Emphasis Control

DeEmph Description

0 Disabled (default) 1 44.1 kHz de-em ph as is

6.4 ADC Control - Address 04h

76543210

FM1 FM0 Reserved ADC_DIF Reserved MuteADC HPFFreeze M/S

34 DS657A2

Gain

0dB

-10dB

CS4265

T1=50 µs

T2 = 15 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 17. De-Emphasis Curve

6.4.1 Functional Mode (Bits 7:6)

Function:

Selects the required range of sample rates.

Table 7. Functional Mode Selection

FM1 FM0 Mode

0 0 Single-Speed Mode: 4 to 50 kHz sample rates 0 1 Double-Speed Mode: 50 to 100 kHz sample rates 1 0 Quad-Speed Mode: 100 to 200 kHz sample rates 11Reserved

6.4.2 ADC Digital Interface Format (Bit 4)

Function:

The required relationship between LRCK, SCLK and SDOUT is defined by the ADC Digital Interface Format bit. The options are detailed in Table 8 and may be seen in Figure 5 and 6.

Table 8. ADC Digital Interface Formats

Frequency

ADC_DIF Description Format Figure

0 Left Justified, up to 24-bit data (default) 0 5 1

S, up to 24-bit data

6.4.3 Mute ADC (Bit 2)

Function:

When this bit is set, the serial audio output of the both ADC channels will be muted.

6.4.4 ADC High Pass Filter Freeze (Bit 1)

Function:

When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “High Pass Filter and DC Offset Calibration” on page 23.

DS657A2 35

CS4265

6.4.5 Master / Slave Mode (Bit 0)

Function:

This bit selects either master or slave operation for the serial audio port. Setting this bit will select master mode, while clearing this bit will select slave mode.

6.5 MCLK Frequency - Address 05h

76543210

Reserved

MCLK

Freq2

6.5.1 Master Clock Dividers (Bits 6:4)

Function:

Sets the frequency of the supplied MCLK signal. See Table 9 below for the appropriate settings.

MCLK Divider MCLK Freq2 MCLK Freq1 MCLK Freq0

MCLK

Freq1

÷1 000

÷1.5 001

÷2 010 ÷3 011

÷4 100 Reserved 101 Reserved 11x

MCLK

Freq0

Table 9. MCLK Frequency

Reserved Reserved Reserved Reserved

6.6 Signal Selection - Address 06h

76543210

SDINSel Reserved Reserved Reserved Reserved Reserved LOOP Reserved

6.6.1 DAC SDIN Source (Bit 7)

Function:

This bit is used to select the serial audio data source for the DAC as shown in Table 10 below.

Table 10. DAC SDIN Source Selection

SDINSel Setting DAC Data Source

0 SDIN1 1 SDIN2

6.6.2 Digital Loopback (Bit 1)

Function:

When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to “Internal Digital Loopback” on page 26.

6.7 Channel A PGA Control - Address 07h

76543210

Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0

36 DS657A2

CS4265

6.7.1 Channel A PGA Gain (Bits 5:0)

Function:

See “Channel B PGA Gain (Bits 5:0)” on page 37.

6.8 Channel B PGA Control - Address 08h

76543210

Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0

6.8.1 Channel B PGA Gain (Bits 5:0)

Function:

Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to +12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step. Register settings outside of the ±12 dB range are reserved and must not be used. See Table 11 for example settings.

Table 11. Example Gain and Attenuation Settings

Gain[5:0] S etting

101000 -12 dB 000000 0 dB 011000 +12 dB

6.9 ADC Input Control - Address 09h

76543210

Reserved Reserved Reserved PGASoft PGAZero Reserved Reserved Select

6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)

Function:

Soft Ramp Enable

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 12 on page 38.

Zero Cross Enable

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period between 512 and 1 024 sample periods ( 10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a ze ro cro s sing. The ze ro cross functi on is independ ently monitored and implemented for each channel. See Table 12 on page 38.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictate that signal level ch anges, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 51 2 and 1024 sample per iods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 12 on page 38.

DS657A2 37

Table 12. PGA Soft Cross or Zero Cross Mode Selection

PGASoft PGAZeroCross Mode

0 0 Change s to affect immediate ly 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled (default)

6.9.2 Analog Input Selection (Bit 0)

Function:

These bits are used to select the input source for the PGA and ADC. Please see Table 13 below.

Table 13. Analog Input Selection

Select PGA/ADC Input

0 Microphone Level Input 1 Line Level Input

6.10 DAC Channel A Volume Control - Address 0Ah

CS4265

See 6.11 DAC Channel B Volume Control - Address 0Bh

6.11 DAC Channel B Volume Control - Address 0Bh

76543210

Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 V ol0

6.11.1 Volume Control (Bits 7:0)

Function:

The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to

-127 dB. The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits activate attenuation equal to their decimal equivalent (in dB). Example volume settings are decoded as shown in Table Table 14. The volume changes are implemented as dictated by the DACSoft and DACZeroCross bits in the DAC Control 2 register (see section 6.12.1).

Table 14. Digital Vo lume Control Example Settings

Binary Code Volume Setting

00000000 0 dB 00000001 -0.5 dB 00101000 -20 dB 00101001 -20.5 dB

11111110 -127 dB 11111111 - 127.5 dB

6.12 DAC Control 2 - Address 0Ch

76543210

DACSoft DACZero InvertDAC Reserved Reserved Reserved Reserved Reserved

38 DS657A2

6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)

Function:

Soft Ramp Enable

Zero Cross Enable

Soft Ramp and Zero Cross Enable

CS4265

Table 15. DAC Soft Cross or Zero Cross Mode Selection

DACSoft DACZeroCross Mode

0 0 Changes to affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled (default)

6.12.2 Invert DAC Output (Bit 5)

Function:

When this bit is set, the output of the DAC will be inverted.

6.13 Status - Address 0Dh

76543210

Reserved Reserved Reserved EFTC ClkErr Reserved ADCOvfl ADCUndrfl

For all bits in this register, a ‘1’ means the associated condition has occur red at least once since the register was last read. A ‘0’ means the associated condition has NOT occurred since the la st reading of the register. Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register defaults to 00h.

6.13.1 E to F C-buffer Transfer

Function:

Indicates the completion of an E to F C-buffer transfer. See “Channe l Status Buffer Management” on page 50 for more information.

DS657A2 39

CS4265

6.13.2 Clock Error (Bit 3)

Function:

Indicates the occurrence of a clock error condition.

6.13.3 ADC Overflow (Bit 1)

Function:

Indicates the occurrence of an ADC overflow condition.

6.13.4 ADC Underflow (Bit 0)

Function:

Indicates the occurrence of an ADC underflow condition.

6.14 Status Mask - Address 0Eh

76543210

Reserved Reserved Reserved EFTCM ClkErrM Reserved ADCOvflM ADCUndrflM

Function:

The bits of this register serve as a mask for the Status source s found in the register “Status - Address 0Dh” on page 39. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status register. The bit positions align with the corresponding bits in the Status register.

6.15 Status Mode MSB - Address 0Fh

6.16 Status Mode LSB - Address 10h

76543210

Reserved Reserved Reserved EFTC1 ClkErr1 Reserved ADCOvfl1 ADCUndrfl1 Reserved Reserved Reserved EFTC0 ClkErr0 Reserved ADCOvfl0 ADCUndrfl0

Function:

The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to update the Status register in accordance with the status condition. In the Rising edge active mode, the status bit becomes active on the arrival of the condition. In the Falling edge active mode, the status bit becomes active on the removal of the condition. In Level active mode, the status bit is active during the condition.

00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

6.17 Transmitter Control 1 - Address 11h

76543210

Reserved EFTCI CAM Reserved Reserved Reserved Reserved Reserved

6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6)

Function:

When cleared, C-data E to F buffer transfers are allowed. When set, C-data E to F buffer transfers are inhibited. See “IEC60958-3 Channel Status (C) Bit Management” on page 50.

40 DS657A2

CS4265

6.17.2 C-Data Access Mode (Bit 5)

Function:

When cleared, the C-data buffer will operate in One-byte control port access mode. When set, the Cdata buffer will operate in Two-byte control port access mode. See “IEC60958-3 Channel Status (C) Bit Management” on page 50.

6.18 Transmitter Control 2 - Address 12h

76543210

Tx_DIF1 Tx_DIF0 TxOff TxMute V MMT MMTCS MMTLR

6.18.1 Transmitter Digital Interface Format (Bits 7:6)

Function:

The required relationship between LRCK, SCLK and SDIN for the transmitter is defined by the T ransmitter Digital Interface Format and the options are detailed in Table 16 and Figures 5-7.

Table 16. Transmitter Digital Interface Formats

Tx_DIF1 Tx_DIF0 Description Format Figure

0 0 Left Justified, up to 24-bit data (default) 0 5 01

1 0 Right Justified, 16-bit Data 2 7 1 1 Right Justified, 24-bit Data 3 7

S, up to 24-bit data

6.18.2 Transmitter Output Driver Control (Bit 5)

Function:

When this bit is cleared, the transmitter output pin driver will be in the normal operational mode. When set, the transmitter output pin driver will drive to a constant 0 V.

6.18.3 Transmitter Mute Control (Bit 4)

Function:

When this bit is cleared, the transmitter data will be in the normal operational mode. When set, the transmitter will output all zero data.

6.18.4 Transmitted Validity Bit Control (Bit 3)

Function:

This bit sets the transmitted Validity bit level. When this bit is cleared, valid linear PCM audio data is indicated. When this bit is set, invalid or non-

linear PCM audio data is indicated.

6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2)

Function:

When this bit is cleared, the transmitter will operate in stereo mode. When set, the transmitter will operate in mono mode with one input channel’ s data output in both A a nd B subframes (see “IEC609583 Channel Status (C) Bit Management” on page 50) and the CS data defined by the MMTCS bit (see section 6.18.6).

DS657A2 41

6.18.6 Mono Mode CS Data Source (Bit 1)

Function:

When this bit is cleared, the transmitter will transmit the channel A CS data in the A subframe and the channel B CS data in the B subframe.

When this bit is set, the transmitter will transmit the CS data defined for the channel selected by the MMTLR bit in both the A and B subframes.

6.18.7 Mono Mode Channel Selection (Bit 0)

Function:

When this bit is cleared, channel A input data will be transmitted in both channel A and B subframes in mono mode. When this bit is set, channel B input data will be transmitted in both channel A and B subframes in mono mode.

CS4265

42 DS657A2

7. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full- scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the conver ter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS4265

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

DS657A2 43

8. PACKAGE DIMENSIONS

32L QFN (5 X 5 mm BODY) PACKAGE DRAWING

CS4265

e Pin #1 Corner

NOTE

Pin #1 Corner

Top View

Side View

A1 A

Bottom View

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A----0.0394----1.001

A1 0.0000 -- 0.0020 0.00 -- 0.05 1

b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2 D 0.1969 BSC 5.00 BSC 1

D2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1

E 0.1969 BSC 5.00 BSC 1

E2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1

e 0.0197 BSC 0.50 BSC 1 L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1

JEDEC #: MO-220

Controlling Dimension is Millimeters.

Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1995.

2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip.

9. THERMAL CHARACTERISTICS AND SPECIFICATIONS

Parameters Symbol Min Typ Max Units

Package Thermal Resistance (Note 3) 32-QFN θ

Allowable Junction Temperature - - 125 °C

Notes: 3. θJA is specified according to JEDEC specifications for multi-layer PCBs.

44 DS657A2

38 52

°C/Watt °C/Watt

CS4265

APPENDIX A: DAC FILTER PLOTS

Figure 18. DAC Single Speed Stopband Rejection Figure 19. DAC Single Speed Transition Band

Figure 20. DAC Single Speed Transition Band Figure 21. DAC Single Speed Passband Ripple

Figure 22. DAC Double Speed Stopband Rejection Figure 23. DAC Double Speed Transition Band

DS657A2 45

CS4265

Figure 24. DAC Double Speed Transition Band Figure 25. DAC Double Speed Passband Ripple

-10

-20

-30

-40

-50

Amplitude (dB)

-60

-70

-80

-90

-100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency(normalized to Fs)

-10

-20

-30

Amplitude (dB)

-40

-50

-60

0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 Frequency(normalized to Fs)

Figure 26. DAC Quad Speed Stopband Rejection Figure 27. DAC Quad Speed Transition Band

-5

-10

-15

-20

-25

Amplitude (dB)

-30

-35

-40

-45

-50

0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency(normalized to Fs)

0.2

0.15

0.1

0.05

Amplitude (dB)

-0.05

-0.1

-0.15

-0.2

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs)

Figure 28. DAC Quad Speed Transition Band Figure 29. DAC Quad Speed Passband Ripple

46 DS657A2

APPENDIX B: ADC FILTER PLOTS

CS4265

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Amplitude (dB)

-110

-120

-130

-140

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Amplitude (dB)

-110

-120

-130

-140

0.40 0 .42 0.44 0.46 0.4 8 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Figure 30. ADC Single Speed Stopband Rejection Figure 31. ADC Single Speed Stopband Rejection

-1

-2

-3

-4

-5

-6

-7

Amplitude (dB)

-8

-9

-10

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to F s)

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

Amplitude (dB)

-0.06

-0.08

-0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (normalized to Fs)

Figure 32. ADC Single Speed Transition Band (Detail)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Amplitude (dB)

-110

-120

-130

-140

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to F s)

Figure 33. ADC Single Speed Passband Ripple

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Amplitude (dB)

-110

-120

-130

-140

0.40 0 .42 0.44 0.46 0.4 8 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Figure 34. ADC Double Speed Stopband Rejection Figure 35. ADC Double Speed Stopband Rejection

DS657A2 47

CS4265

-1

-2

-3

-4

-5

-6

-7

Amplitude (dB)

-8

-9

-10

0.46 0.47 0.48 0.49 0.50 0.51 0.52

Frequency (normalized to F s)

Figure 36. ADC Double Speed Transition Band (De-

tail)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Amplitude (dB)

-110

-120

-130

-140

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to F s)

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

Amplitude (dB)

-0.06

-0.08

-0.10

0.00 0 .05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 .45 0.50

Frequency (normalized to Fs)

Figure 37. ADC Double Speed Passband Ripple

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Amplitude (dB)

-110

-120

-130

-140

0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85

Frequency (normalized to Fs)

Figure 38. ADC Quad Speed Stopband Rejection Figure 39. ADC Quad Speed Stopband Rejection

-1

-2

-3

-4

-5

-6

-7

Amplitude (dB)

-8

-9

-10

0.10 0.15 0.20 0.25 0.30 0.35 0.4 0 0.45 0.50

Frequency (normalized to F s)

Figure 40. ADC Quad Speed Transition Band (Detail)

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

Amplitude (dB)

-0.06

-0.08

-0.10

0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0 .23 0.25 0.28

Frequency (normalized to Fs)

Figure 41. ADC Quad Speed Passband Ripple

48 DS657A2

CS4265

APPENDIX C: EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS

This section details the external components required to interface the IEC60958-3 transmitter to cables and fiberoptic components.

C.1 IEC60958-3 Transmitter External Components

The IEC60958-3 specifications call for an unbalanced drive circuit with an output impedance of 75 Ω ± 20% and a output drive level of 0.5 volts peak-to-peak ±20% when measured across a 75 Ω load using no cable. The circuit shown in Figure 42 provides the proper output impedance and drive level using standard 1% resistor s. If VD is driven from +3.3 V, use re sist or va lu es o f 24 3 Ω in place of the 374 Ω resistor and a 107 Ω resistor in place of the 90 .9 Ω resistor. The standard connector for a consumer application is an RCA phono socke t.

The TXOUT pin may be used to drive TTL or CMOS gates as shown in Figure 43. This circuit may be used for optical connectors for digital audio as they typically implement TTL or CMOS compatible inputs. This circuit is also useful when driving multiple digital audio outputs as RS422 line drivers typically implement TTL compatible inputs.

374-R

90.9

TXP

Ω

RCA Phono

TXOUT

CS4265

Figure 42. Consumer Output Circuit (VD = 5 V)

TXOUT

CS4265

Figure 43. TTL/CMOS Output Circuit

TTL or CMOS Gate

C.2 Isolating Transformer Requirements

Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on transformer selection.

DS657A2 49

CS4265

APPENDIX D: CHANNEL STATUS BUFFER MANAGEMENT

The CS4265 has a comprehensive channel status (C) data buffering scheme which allows the user to manage the C data through the control port.

D.1 IEC60958-3 Channel Status (C) Bit Management

The CS4265 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits). The user may read from or write to these RAM buffers through the control port.

The CS4265 manages the flow of channel status data at the b lock level, meaning that entire blocks of channel status information are buffered at the input, synchronized to the output time base, and then transmitted. The buffering scheme involves a cascade of 2 block-sized buffers, named E and F, as show n in Figure 44. The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port address 13h) is the consumer/professional bit for channel status block A.

The E buffer is accessible from the control port, allowing read and writing of the C data. Th e F buffer is u sed as th e source of C data for the IEC60958-3 transmitter. The F buffer accepts block transfers from the E buffer.

8-bits 8-bits

words

Transmit Data Buffer

To AES3 Transmitter

Control Port

Figure 44. Channel Status Data Buffer Structure

D.1.1 Accessing the E buffer

The user can monitor the data being tran sferre d by re ading the E b uffer, which is mapped into th e regi ster space of the CS4265, through the control port. The user can modify the data to be transmitted by writing to the E buffer.

The user can configure the status register such that EFTC bit is set whenever an E to F transfer completes. With this configuration in place, periodic polling of the status register allows determination of the time periods acceptable for E buffer interaction.

Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user sets this bit. This may be used whenever “long” control port interactions are occurring.

50 DS657A2

CS4265

A flowchart for reading and writing to the E buffer is shown in Figure 45. For writing, the sequence starts after an E to F transfer, which is based on the output timebase .

Begin

Configure the EFTC status bit as

Rising Edge active.

Read the Status Register

(Reg 0Dh)

Is the EFTC bit set?

Yes

Optionally set E to F inhibit

Write E data

If set, clear E to F inhibit

Figure 45. Flowchart for Writing the E Buffer

D.1.2 Serial Copy Management System (SCMS)

The CS4265 allows read/modify/write access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to manipulate the Category Code, Copy bit and L bit appropriately.

D.1.3 Channel Status Data E Buffer Access

The E buffer is organized as 24 x 16-bit words. For each word the most significant byte is the A channel data, and the least significant byte is the B channel data (see Figure 44).

There are two methods of accessing this memory, known as one byte mode and two byte mode. The desired mode is selected through a control register bit.

D.1.3.1 One Byte mode

In many applications, the channel status blocks for the A and B channels will be identical. In this situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would be ne cessary to write the same byte to the other block. One byte mode takes advantage of the often identical nature of A and B channel status data.

When reading data in one byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. If a write is being done, the CS4265 expects a single byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word.

One byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access t ime. If th e cont rol port's a uto increm ent ad dressing is used in combin ation with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently.

D.1.3.2 Two Byte mode

There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, two byte mode should be used to access the E buffer.

In this mode, a read will cause the CS4265 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two

DS657A2 51

CS4265

bytes must now be input to the CS4265's control port. The A channel status data is first, B channel status data second.

52 DS657A2

Release Date Changes

A1 May 2004 Initial Advance Release. A2 September 2004

– Updated descriptions of pins 3, 4, 5, and 6 on page 5. – Removed specifications for SPI control port. – Added specification for AD0 selection in the I²C Control Port

Description and Timing section on page 28.

– Updated the typical connection diagram on page 21 to reflect the

pin changes and AD0 selection method. – Added thermal pad to pin descriptions on page 6. – Added Package Considerations section on page 30. – Updated the Mic level input impedance specification on page 13.

Table 17. Revision History

CS4265

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE "Advance" product informat ion de scrib es produc ts that are in developmen t and subje ct to d evelopmen t changes . Cirr us Logic , Inc. and its subsidiaries ("Cirrus")

believe that the inf ormation contained in this document is accurate and relia ble. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are ad vised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current an d complete. All pr oducts are sold subject to the te rms and conditio ns of sa le supp lied at the time of order acknowledgment, including those pertaining to warranty, patent infr ingemen t, and limitation of lia bility. No responsib ility is assumed by Ci rrus for the use of th is informat ion, includi ng use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this informa tion, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellect ual prop erty rig hts. Cir rus owns t he copyri ghts asso ciated wit h the in formati on conta ined her ein and giv es consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertisi ng or p rom otional purposes, or for creating any work for resale.

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I2C is a registered trademark of Philips Semicondu ctor. Purchase of I2C C omponents of Cirrus L ogic, Inc., or one of its sublice nsed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.

DS657A2 53

CIRRUS LOGIC CS4265 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

System Features

General Description

1. PIN DESCRIPTIONS

2. CHARACTERISTICS AND SPECIFICATIONS

SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to

ABSOLUTE MAXIMUM RATINGS (AGND= DGND = 0 V All voltages with respect to ground.) (Note

DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Figure 1. DAC Output Test Load

Figure 2. Maximum DAC Loading

ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): Input test sig-

ADC ANALOG CHARACTERISTICS (cont)

DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V, all voltages with respect to

DIGITAL INTERFACE CHARACTERISTICS

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic ‘0’ = DGND = 0 V;

Figure 3. Master Mode Serial Audio Port Timing

Figure 4. Slave Mode Serial Audio Port Timing

Figure 5. Format 0, Left Justified up to 24-Bit Data

3. TYPICAL CONNECTION DIAGRAM

Figure 9. Typical Connection Diagram

4. APPLICATIONS

4.1 Recommended Power-Up Sequence

4.2 System Clocking

Table 1. Speed Modes

4.2.1 Master Clock

Table 2. Common Clock Frequencies

4.2.2 Master Mode

Figure 10. Master Mode Clocking

4.2.3 Slave Mode

Table 3. Slave Mode Serial Bit Clock Ratios

4.3 High Pass Filter and DC Offset Calibration

4.4 Analog Input Multiplexer, PGA, and Mic Gain

Figure 11. Analog Input Architecture

4.5 Input Connections

4.5.1 Pseudo-Differential Input

Figure 12. Pseudo-Differential Input Stage

4.6 Output Connections

4.7 Output Transient Control

4.7.1 Power-up

4.7.2 Power-down

4.7.3 Serial Interface Clock Changes

4.8 DAC Serial Data Input Multiplexer

4.9 De-Emphasis Filter

Figure 13. De-Emphasis Curve

4.10 Internal Digital Loopback

4.11 Mute Control

Figure 14. Suggested Active-Low Mute Circuit

4.12 AES3 Transmitter

4.12.1 TxOut Driver

4.12.2 Mono Mode Operation

4.14 Status Reporting

4.15 Reset

4.16 Synchronization of Multiple Devices

4.17 Grounding and Power Supply Decoupling

4.18 Package Considerations

5. REGISTER QUICK REFERENCE

6. REGISTER DESCRIPTION

6.1 Chip ID - Register 01h

6.2 Power Control - Address 02h

Table 4. Freeze-able Bits

6.3 DAC Control - Address 03h

Table 5. DAC Digital Interface Formats

Table 6. De-Emphasis Control

6.4 ADC Control - Address 04h

Figure 17. De-Emphasis Curve

Table 7. Functional Mode Selection

Table 8. ADC Digital Interface Formats

6.5 MCLK Frequency - Address 05h

Table 9. MCLK Frequency

6.6 Signal Selection - Address 06h

Table 10. DAC SDIN Source Selection

6.7 Channel A PGA Control - Address 07h

6.8 Channel B PGA Control - Address 08h

Table 11. Example Gain and Attenuation Settings

6.9 ADC Input Control - Address 09h

Table 12. PGA Soft Cross or Zero Cross Mode Selection