CS4245
105 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
Multi-bit Delta Sigma modulator
105 dB dynamic range
-95 dB THD+N
Up to 192 kHz sampling rates
Single-ended analog architecture
Volume control with soft ramp
– 0.5 dB step size
– Zero crossing click-free transitions
PopguardTM Technology
– Minimizes the effects of output transients
Filtered line level outputs
Selectable serial audio interface formats
– Left justified up to 24-bit
– I²S up to 24-bit
– Right justified 16, 18, 20 and 24-bit
Selectable 50/15 µs de-emphasis
Control Output for External Muting
A/D Features
Multi-bit Delta Sigma modulator
105 dB dynamic range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– +/- 12 dB gain, 0.5 dB step size
– Zero crossing, click-free transitions
Stereo microphone inputs
– +32 dB gain stage
– Low noise bias supply
Up to 192 kHz sampling rates
Selectable serial audio interface formats
– Left justified up to 24-bit
– I²S up to 24-bit
High pass filter or DC offset calibration
3.3 V to 5 V 3.3 V to 5 V
Register Config uration
Filter
Filter
Serial
Audio
Input
I2C/SPI
Control Data
Interrupt
ADC Overflow
Reset
Serial
Audio
Output
1.8 V to 5 V
Level
Translator
Level Translator
Level
Translator
PCM Serial InterfacePCM Serial Interface
Volum e
Control
Volume
Control
High Pass
High Pass
Preliminary Product Information
Cirrus Logic, Inc.
www.cirrus.com
Interpolation
Filter
Interpolation
Filter
Linear Phase
Anti-Alias Filter
Linear Phase
Anti-Alias Filter
Multibit
∆Σ Modulator
Multibit
∆Σ Modulator
Internal Volt age
Oversampling
Oversampling
Reference
Multibit
ADC
Multibit
ADC
Swit ched Capacitor
DAC and Filter
Swit ched Capacitor
DAC and Filter
PGA
PGA
MUX
Mute
Control
MUX
+32 dB
+32 dB
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
Left DAC Output
Mute Control
Right DAC Output
Left Aux Output
Right Aux Output
Stereo Inp ut 1
Stereo Inp ut 2
Stereo Inp ut 3
Stereo Inp ut 4 /
Mic Input 1 & 2
Stereo Inp ut 5
Stereo Inp ut 6
AUG ‘04
DS656PP1
1
CS4245
2
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................... 5
2. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 8
SPECIFIED OPERATING CONDITIONS................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8
DAC ANALOG CHARACTERISTICS ....................................................................................... 9
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 10
ADC ANALOG CHARACTERISTICS ..................................................................................... 12
ADC ANALOG CHARACTERISTICS ..................................................................................... 14
ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 15
AUXILIARY OUTPUT ANALOG CHARACTERISTICS .......................................................... 16
AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT’D) ......................................... 17
AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT’D) ......................................... 18
DC ELECTRICAL CHARACTERISTICS ................................................................................ 19
DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 20
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1.............................................. 21
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2.............................................. 23
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ................................ 26
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 27
3. TYPICAL CONNECTION DIAGRAM .................................................................................... 28
4. APPLICATIONS .................................................................................................................... 29
4.1 Recommended Power-Up Sequence ............................................................................. 29
4.2 System Clocking ............................................................................................................. 29
4.2.1 Synchronous / Asynchronous Mode .................................................................. 29
4.2.2 Master Clock ...................................................................................................... 29
4.2.3 Master Mode ...................................................................................................... 30
4.2.4 Slave Mode ........................................................................................................ 30
4.3 High Pass Filter and DC Offset Calibration .................................................................... 31
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................ 31
4.5 Input Connections ........................................................................................................... 32
4.6 Output Connections ........................................................................................................32
4.7 Output Transient Control ................................................................................................ 32
4.7.1 Power-up ............................................................................................................ 32
4.7.2 Power-down ....................................................................................................... 32
4.7.3 Serial Interface Clock Changes ......................................................................... 32
4.8 Auxiliary Analog Output .................................................................................................. 32
4.9 De-Emphasis Filter ......................................................................................................... 33
4.10 Internal Digital Loopback .............................................................................................. 33
4.11 Mute Control ................................................................................................................. 33
4.12 Control Port Description and Timing ............................................................................. 34
4.12.1 SPI Mode ......................................................................................................... 34
4.12.2 I²C Mode .......................................................................................................... 35
4.13 Interrupts and Overflow ................................................................................................ 37
4.14 Reset ........................................................................................................................... 37
4.15 Synchronization of Multiple Devices ............................................................................. 37
4.16 Grounding and Power Supply Decoupling .................................................................... 37
5. REGISTER QUICK REFERENCE ......................................................................................... 38
6. REGISTER DESCRIPTION ................................................................................................... 39
6.1 Chip ID - Register 01h ....................................................................................................39
6.2 Power Control - Address 02h ......................................................................................... 39
6.3 DAC Control - Address 03h ............................................................................................ 40
6.4 ADC Control - Address 04h ............................................................................................ 41
6.5 MCLK Frequency - Address 05h .................................................................................... 42
CS4245
3
CS4245
6.6 Signal Selection - Address 06h ....................................................................................... 43
6.7 Channel A PGA Control - Address 07h ........................................................................... 43
6.8 Channel B PGA Control - Address 08h ........................................................................... 44
6.9 ADC Input Control - Address 09h ...................................................................................44
6.10 DAC Channel A Volume Control - Address 0Ah ........................................................... 45
6.11 DAC Channel B Volume Control - Address 0Bh ........................................................... 45
6.12 DAC Control 2 - Address 0Ch ....................................................................................... 46
6.13 Interrupt Status - Address 0Dh ..................................................................................... 46
6.14 Interrupt Mask - Address 0Eh ....................................................................................... 47
6.15 Interrupt Mode MSB - Address 0Fh ..............................................................................47
6.16 Interrupt Mode LSB - Address 10h ............................................................................... 47
7. PARAMETER DEFINITIONS .................................................................................................48
8. PACKAGE DIMENSIONS ...................................................................................................... 49
9. THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................. 49
Appendix A: DAC Filter Plots ......................................................................................... 50
Appendix B: ADC Filter Plots .............................................................................................. 52
4
1. PIN DESCRIPTIONS
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RESET
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
OVFL
INT
VD
DGND
MCLK1
LRCK1
SCLK1
SDOUT
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
CS4245
CS4245
MCLK2
LRCK2
SCLK2
SDIN
VLSSDA/CDOUT
36
MUTEC
35
AOUTB
34
AOUTA
33
32
AGND
AGND
31
30
VA
29
AUXOUTB
28
AUXOUTA
27
AIN6B
26
AIN6A
25
MICBIAS
Pin Name # Pin Description
SDA/CDOUT
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RESET
AIN3A
AIN3B
Serial Control Data (
1
the control port interface in SPI mode.
Serial Control Port Clock (
2
Address Bit 0 (I²C) / Control Port Chip Select (SPI)
3
CS
is the chip select signal for SPI format.
Address Bit 1 (I²C) / Serial Control Data Input (SPI)
4
CDIN is the input data line for the control port interface in SPI mode.
Control Port Power (
5
to the Recommended Operating Conditions for appropriate voltages.
Reset (
Input
6
7,
Stereo Analog Input 3 (
specification table.
8
) - The device enters a low power mode when this pin is driven low.
13 14 15 16 17 18 19 20 21 22 23 24
VA
AGND
Input/Output
VQ1
VQ2
FILT1+
AFILTA
AFILTB
FILT2+
AIN4A/MICIN1
AIN5A
AIN4B/MICIN2
) - SDA is a data I/O in I²C mode. CDOUT is the output data line for
Input
) - Serial clock for the serial control port.
(Input)
(Input)
Input
) - Determines the required signal level for the control port interface. Refer
Input
) - The full scale level is specified in the ADC Analog Characteristics
AIN5B
- AD0 is a chip address pin in I²C mode;
- AD1 is a chip address pin in I²C mode;
5
CS4245
AIN2A
AIN2B
AIN1A
AIN1B
AGND
VA
AFILTA
AFILTB
VQ1
VQ2
FILT1+
FILT2+
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
MICBIAS
AIN6A
AIN6B
9,
Stereo Analog Input 2 (
specification table.
10
11,
Stereo Analog Input 1 (
specification table.
12
13 Analog Ground (
Analog Power
14
Antialias Filter Connection (
15
Antialias Filter Connection (
16
Quiescent Voltage 1 (
17
(Input)
18 Quiescent Voltage 2 (
19 Positive Voltage Reference 1 (
Positive Voltage Reference 2 (
20
21,
Stereo Analog Input 4 / Microphone Input 1 & 2 (
Analog Characteristics specification table.
22
23,
Stereo Analog Input 5 (
specification table.
24
Microphone Bias Supply (
25
teristics are specified in the DC Electrical Characteristics specification table.
26,
Stereo Analog Input 6 (
specification table.
27
Input
) - The full scale level is specified in the ADC Analog Characteristics
Input
) - The full scale level is specified in the ADC Analog Characteristics
Input
) - Ground reference for the internal analog section.
- Positive power for the internal analog section.
Output
) - Antialias filter connection for the channel A ADC input.
Output
) - Antialias filter connection for the channel B ADC input.
Output
) - Filter connection for the internal quiescent reference voltage.
Output
) - Filter connection for the internal quiescent reference voltage.
Output
) - Positive reference voltage for the internal sampling circuits.
Output
) - Positive reference voltage for the internal sampling circuits.
Input
) - The full scale level is specified in the ADC
Input
) - The full scale level is specified in the ADC Analog Characteristics
Output
) - Low noise bias supply for external microphone. Electrical charac-
Input
) - The full scale level is specified in the ADC Analog Characteristics
AUXOUTA
AUXOUTB
VA
AGND
AOUTA
AOUTB
MUTEC
VLS
SDIN
SCLK2
LRCK2
MCLK2
SDOUT
SCLK1
LRCK1
28,
Auxiliary Analog Audio Output (
impedance. See “Auxiliary Output Source Select (Bits 6:5)” on page 43.
29
Analog Power
30
31,
Analog Ground (
32
33,
DAC Analog Audio Output (
acteristics specification table.
34
Mute Control
35
clock to left/right clock frequency ratio is incorrect, or power-down.
Serial Audio Interface Power (
36
face. Refer to the Recommended Operating Conditions for appropriate voltages.
Serial Audio Data Input (
37
(Input)
Input
(Output)
- Positive power for the internal analog section.
) - Ground reference for the internal analog section.
- This pin is active during power-up initialization, reset, muting, when master
Input
38 Serial Port 2 Serial Bit Clock
Serial Port 2 Left Right Clock
39
active on the serial audio input data line.
Master Clock 2 (
40
lators.
Input/Output
41 Serial Audio Data Output (
Serial Port 1 Serial Bit Clock
42
Serial Port 1 Left Right Clock
43
active on the serial audio output data line.
Output
) - Analog output from either the DAC, the PGA block, or high
Output
) - The full scale output level is specified in the DAC Analog Char-
Input
) - Determines the required signal level for the serial audio inter-
) - Input for two’s complement serial audio data.
(Input/Output
(Input/Output
) -Optional asynchronous clock source for the DAC’s delta-sigma modu-
Output
) - Output for two’s complement serial audio data.
(Input/Output
(Input/Output
) - Serial bit clock for serial audio interface 2.
) - Determines which channel, Left or Right, is currently
) - Serial bit clock for serial audio interface 1.
) - Determines which channel, Left or Right, is currently
6
CS4245
7
CS4245
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and T
SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to
ground.)
ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V All voltages with respect to ground.) (Note
1)
= 25°C.)
A
Parameters Symbol Min Nom Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied) T
Parameter Symbol Min Typ Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Input Current (Note 2) I
Analog Input Voltage V
Digital Input Voltage Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
VA
VD
VLS
VLC
VLS
VLC
V
IND-S
V
IND-C
A
VA
VD
in
INA
stg
3.1
3.1
1.71
1.71
-10 - +70 °C
-0.3
-0.3
-0.3
-0.3
AGND-0.3 - VA+0.3 V
-0.3
-0.3
A
-20 - +85 °C
-65 - +150 °C
5.0
3.3
3.3
3.3
-
-
-
-
--±10 mA
--VLS+0.3
5.25
5.25
5.25
5.25
+6.0
+6.0
+6.0
+6.0
VLC+0.3VV
V
V
V
V
V
V
V
V
Notes: 1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
8
CS4245
DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R
C
= 10 pF (see Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise speci-
L
= 3 kΩ,
L
fied.) Synchronous mode.
All Speed Modes
Parameter
Symbol Min Typ Max Unit
Dynamic Performance for VA = 5 V
Dynamic Range (Note 3)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
Total Harmonic Distortion + Noise (Note 3)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
96
99
87
90
102
105
93
96
-
-
-
-
-
-
-95
-82
-42
-93
-73
-33
-
-
-
-
-89
-76
-36
-87
-67
-27
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Dynamic Performance for VA = 3.3 V
Dynamic Range (Note 3)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
Total Harmonic Distortion + Noise (Note 3)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
93
96
85
88
99
102
90
93
-
-
-
-
-
-
-92
-79
-39
-90
-70
-30
-
-
-
-
-84
-71
-31
-82
-62
-22
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 100 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 dB
Gain Drift - 100 - ppm/°C
Analog Output
Full Scale Output Voltage 0.60*VA 0.65*VA 0.70*VA V
DC Current draw from an AOUT pin (Note 4) I
OUT
AC-Load Resistance (Note 5) R
Load Capacitance (Note 5) C
Output Impedance Z
L
L
OUT
--10µA
3--kΩ
--100pF
- 100 - Ω
pp
Note: 3. One-half LSB of triangular PDF dither added to data.
4. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the electrolytic DC blocking capacitors.
5. Guaranteed by design. See Figure 2. R
and CL reflect the recommended minimum resistance and
L
maximum capacitance required for the internal op-amp’s stability. C
internal output amp; increasing C
beyond 100 pF can cause the internal op-amp to become unstable.
L
affects the dominant pole of the
L
9
CS4245
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 6,9) Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response Single Speed Mode
Passband (Note 6) to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -.01 - +.08 dB
StopBand .5465 - - Fs
StopBand Attenuation (Note 7) 50 - - dB
Group Delay tgd - 10/Fs - s
De-emphasis Error (Note 8) Fs = 44.1 kHz - - +.05/-.25 dB
Combined Digital and On-chip Analog Filter Response Double Speed Mode
Passband (Note 6) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -.05 - +.2 dB
StopBand .5770 - - Fs
StopBand Attenuation (Note 7) 55 - - dB
Group Delay tgd - 5/Fs - s
Combined Digital and On-chip Analog Filter Response Quad Speed Mode
Passband (Note 6) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB
StopBand 0.7 - - Fs
StopBand Attenuation (Note 7) 51 - - dB
Group Delay tgd - 2.5/Fs - s
0
0
0
0
0
0
-
-
-
-
-
-
.4780
.4996
.4650
.4982
0.397
0.476
Fs
Fs
Fs
Fs
Fs
Fs
Notes: 6. Filter response is guaranteed by design.
7. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
8. De-emphasis is available only in Single Speed Mode.
9. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
10
CS4245
125
3.3µF
AOUTx
AGND
Figure 1. DAC Output Test Load
100
L
V
out
R
L
C
L
75
50
Safe Operating
Region
25
Capacitive Load -- C (pF)
2.5
51015
3
Resistive Load -- R (kΩ)
L
20
Figure 2. Maximum DAC Loading
11
CS4245
ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): Input test sig-
nal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Fs = 48/96/192 kHz. Synchronous mode.
Line Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 5 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 12) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 12) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 12) 40 kHz bandwidth -1 dB
THD+N
99
96
93
90
105
102
-
-
-
-
-
-
99
99
96
93
-95
-82
-42
-92
-
-
-
-
-
-
-89
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 12) 40 kHz bandwidth -1 dB
Dynamic Performance for VA = 3.3 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 12) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 12) 40 kHz bandwidth unweighted
94
91
90
87
-
-
-
-
-
-
-92
-76
-36
-89
102
99
96
96
93
90
-86
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
12
CS4245
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 12) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 12) 40 kHz bandwidth -1 dB
Parameter Symbol Min Typ Max Unit
Interchannel Isolation - 90 - dB
Line Level Input Characteristics
Full-scale Input Voltage 0.53*VA 0.56*VA
Input Impedance (Note 10) 6.12 6.8 7.48 kΩ
Maximum Interchannel Input Impedance Mismatch
Line Level and Microphone Level Inputs
Parameter Symbol Min Typ Max Unit
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -
Gain Drift -
Programmable Gain Characteristics
Gain Step Size - 0.5
Absolute Gain Step Error - -
THD+N
Line Level Inputs
-
-
-
-
-
-
-
-
-5-%
-92
-79
-39
-84
-89
-73
-33
-81
-86
-
-
-
-83
-
-
-
0.59*VA
±5
dB
dB
dB
dB
dB
dB
dB
dB
V
pp
%
±100 - ppm/°C
-
0.4
dB
dB
10. Valid for the selected input pair.
13
ADC ANALOG CHARACTERISTICS (cont)
Microphone Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 5 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
THD+N
77
74
65
62
CS4245
83
80
71
68
-
-
-
-80
-60
-20
-
-
-
-
-74
-
-
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB
-1 dB
Dynamic Performance for VA = 3.3 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Interchannel Isolation - 30 - dB
Microphone Level Input Characteristics
Full-scale Input Voltage 0.013*VA 0.014*VA 0.015*VA V
Input Impedance (Note 13) - 100 - kΩ
THD+N
-
77
74
65
62
-
-
-
-
-68
83
80
71
68
-80
-60
-20
-68
-
-
-
-
-
-74
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
pp
14
11. Referred to the typical line level full-scale input voltage
12. Valid for Double and Quad Speed Modes only.
13. Valid when the microphone level inputs are selected.
CS4245
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 14, 16) Symbol Min Typ Max Unit
Single Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Double Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Quad Speed Mode
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
High Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 15)
Phase Deviation @ 20Hz (Note 15) - 10 - Deg
Passband Ripple - - 0 dB
Filter Settling Time 10
- 12/Fs - s
-9/Fs - s
-5/Fs - s
-120-
5
/Fs s
-
Hz
Hz
Note: 14. Filter response is guaranteed by design.
15. Response shown is for Fs equal to 48 kHz.
16. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
15
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS Test conditions (unless otherwise
specified): Synchronous mode, Fs = 48/96/192 kHz. Input test signal is a 1 kHz sine wave; measurement bandwidth
is 10 Hz to 20 kHz.
VA = 5 V
Parameter Symbol Min Typ Max Unit
Dynamic Performance with PGA Output Selected, Line Level Input
Dynamic Range (Note 18)
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 18)
PGA Setting: -12 dB to +12 dB
-1 dB
-20 dB
-60 dB
Dynamic Performance with PGA Output Selected, Mic Level Input
Dynamic Range (Note 18)
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
THD+N
99
96
93
90
-
-
-
77
74
105
102
99
96
-80
-82
-42
83
80
-
-
-
-
-74
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 18)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Dynamic Performance with DAC Output Selected
Dynamic Range (Notes 17, 18)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Notes 17, 18)
16 to 24-Bit 0 dB
-20 dB
-60 dB
THD+N
THD+N
65
62
99
96
90
87
71
68
-
-
-
-
-
-
-
-74
-60
-20
-68
105
102
96
93
-80
-82
-42
-
-
-68
-
-
-
-
-
-
-
-74
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
16
CS4245
17
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT’D)
VA = 5V or 3.3V
Parameter Symbol Min Typ Max Unit
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -
Gain Drift -
Analog Output
Full-Scale Output Voltage
PGA Output Selected
DAC Output Selected
Frequency Response 10 Hz to 20 kHz -0.1dB - +0.1dB dB
Analog In to Analog Out Phase Shift (Note 19) - 180 - deg
DC Current draw from an AUXOUT pin I
AC-Load Resistance R
Load Capacitance C
Output Impedance Z
OUT
L
L
OUT
-
-
--1µA
100 - - kΩ
--20pF
-1-kΩ
±5
-
±100 - ppm/°C
0.56*VA
0.7*VA
VA
0.75*VA
V
V
%
pp
pp
Notes: 19. Valid only when PGA output is selected.
18
CS4245
DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V, all voltages with respect to
ground. MCLK=12.288 MHz; Fs=48 kHz, Master Mode)
Parameter Symbol Min Typ Max Unit
Power Supply Current VA = 5 V
(Normal Operation) VA = 3.3 V
VD, VLS, VLC = 5 V
VD, VLS, VLC = 3.3 V
Power Supply Current. VA = 5 V
(Power-Down Mode) (Note 20). VLS, VLC, VD=5 V
Power Consumption
(Normal Operation). VA, VD, VLS, VLC = 5 V
VA, VD, VLS, VLC = 3.3 V
(Power-Down Mode). VA, VD, VLS, VLC = 5 V
Power Supply Rejection Ratio (1 kHz) (Note 21) PSRR - 60 - dB
VQ Characteristics
Quiescent Voltage 1 VQ1 - 0.5 x VA - VDC
DC Current from VQ1 (Note 22) I
VQ1 Output Impedance Z
Quiescent Voltage 2 VQ2 - 0.5 x VA - VDC
DC Current from VQ2 (Note 22) I
VQ2 Output Impedance Z
FILT1+ Nominal Voltage FILT1+ - VA - VDC
FILT2+ Nominal Voltage FILT2+ - VA - VDC
Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC
Current from MICBIAS I
I
A
I
A
I
D
I
D
I
A
I
D
-
-
-
Q1
Q1
Q2
Q2
MB
-
-
-
-
-
-
-
-
-
41
37
39
23
0.50
0.54
400
198
4.2
50
45
47
28
-
-
485
241
-
mA
mA
mA
mA
mA
mA
mW
mW
mW
-- 1µA
-23 -kΩ
-- 1µA
-23 -kΩ
-- 2mA
Notes: 20. Power Down Mode is defines as RESET
input.
21. Valid with the recommended capacitor values on FILT1+, FILT2+, VQ1 and VQ2 as shown in the
Typical Connection Diagram.
22. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage
through the electrolytic de-coupling capacitors.
= Low with all clock and data lines held static and no analog
19
DIGITAL INTERFACE CHARACTERISTICS
Parameters (Note 23) Symbol Min Typ Max Units
High-Level Input Voltage Serial Port
Control Port
Low-Level Input Voltage Serial Port
Control Port
High-Level Output Voltage at I
Low-Level Output Voltage at I
=2 mA Serial Port
o
Control Port
MUTEC
=2 mA Serial Port
o
Control Port
MUTEC
CS4245
V
IH
V
IH
V
IL
V
IL
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
0.7xVLS
0.7xVLC
-
-
VLS-1.0
VLC-1.0
VA-1. 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2xVLS
0.2xVLC
-
-
-
0.4
0.4
0.4
V
V
V
V
V
V
V
V
V
V
Input Leakage Current I
in
--±10µA
Input Capacitance (Note 24) - - 1 pF
Maximum MUTEC Drive Current - 3 - mA
Minimum OVFL Active Time
6
10
---------- ---------LRCK1
µs
Notes: 23. Serial Port signals include: MCLK1, MCLK2, SCLK1, SCLK2, LRCK1, LRCK2, SDIN, SDOUT.
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS
, AD1/CDIN, RESET, INT, OVFL.
24. Guaranteed by design.
20
CS4245
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1 (Logic ‘0’ = DGND = 0 V;
Logic ‘1’ = VL, C
Sample Rate Single Speed Mode
MCLK Specifications
MCLK1 Input Frequency fmclk 1.024 - 51.200 MHz
MCLK1 Input Pulse Width High/Low t
Master Mode
LRCK1 Duty Cycle - 50 - %
SCLK1 Duty Cycle - 50 - %
SCLK1 falling to LRCK1 edge t
SCLK1 falling to SDOUT valid t
Slave Mode
LRCK1 Duty Cycle 40 50 60 %
SCLK1 Period
= 20 pF) (Note 25)
L
Parameter Symbol Min Typ Max Unit
Double Speed Mode
Quad Speed Mode
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
clkhl 8- -ns
slr
sdo
t
sclkw
t
sclkw
t
sclkw
4
50
100
-
-
-
50
100
200
-10 - 10 ns
0 - 32 ns
9
10
------------- --------
128()Fs
9
10
----------- -------
64()Fs
9
10
----------- ------64()Fs
-
-
-
-
-
-
kHz
kHz
kHz
ns
ns
ns
SCLK1 Pulse Width High t
SCLK1 Pulse Width Low t
SCLK1 falling to LRCK1 edge t
SCLK1 falling to SDOUT valid t
25. See figures 3 and 4 on page 22.
sclkh
sclkl
slr
sdo
30 - - ns
48 - - ns
-10 - 10 ns
0 - 32 ns
21
LRCK1
Output
SCLK1
Output
SDOUT
t
t
sdo
CS4245
slr
LRCK1
Input
SCLK1
Input
SDOUT
Figure 3. Master Mode Timing - Serial Audio Port 1
t
sclkh
t
sclkw
t
t
slr
sdo
t
sclkl
22
Figure 4. Slave Mode Timing - Serial Audio Port 1
CS4245
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2 (Logic ‘0’ = DGND = 0 V;
Logic ‘1’ = VL, C
Sample Rate Single Speed Mode
MCLK Specifications
MCLK2 Input Frequency fmclk 1.024 - 51.200 MHz
MCLK2 Input Pulse Width High/Low t
Master Mode
LRCK2 Duty Cycle - 50 - %
SCLK2 Duty Cycle - 50 - %
SCLK2 falling to LRCK edge t
SDIN valid to SCLK2 rising setup time t
SCLK2 rising to SDIN hold time t
Slave Mode
LRCK2 Duty Cycle 40 50 60 %
SCLK2 Period
= 20 pF) (Note 26)
L
Parameter Symbol Min Typ Max Unit
Double Speed Mode
Quad Speed Mode
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
clkhl 8- -ns
slr
sdis
sdih
t
sclkw
t
sclkw
t
sclkw
4
50
100
-
-
-
50
100
200
-10 - 10 ns
16 - - ns
20 - - ns
9
10
------------- --------
128()Fs
9
10
----------- -------
64()Fs
9
10
----------- ------64()Fs
-
-
-
-
-
-
kHz
kHz
kHz
ns
ns
ns
SCLK2 Pulse Width High t
SCLK2 Pulse Width Low t
SCLK2 falling to LRCK2 edge t
SDIN valid to SCLK2 rising setup time t
SCLK2 rising to SDIN hold time t
26. See figures 5 and 6 on page 24.
sclkh
sclkl
slr
sdis
sdih
30 - - ns
48 - - ns
-10 - 10 ns
16 - - ns
20 - - ns
23
LRCK2
Output
SCLK2
Output
CS4245
t
slr
SDIN
LRCK2
Input
SCLK2
Input
t
sdis
Figure 5. Master Mode Timing - Serial Audio Port 2
t
slr
t
sclkh
t
sclkw
t
sdih
t
sclkl
24
SDIN
t
sdis
Figure 6. Slave Mode Timing - Serial Audio Port 2
t
sdih
CS4245
Left Channel
LRCK
SCLK
SDATA +3 +2 +1
MSB
-1 -2 -3 -4 -5
Channel A - Left
+5 +4
Figure 7. Format 0, Left Justified up to 24-Bit Data
Channel A - Left
LRCK
SCLK
SDATA +3 +2 + 1
MSB
-1 -2 -3 -4 -5 +3 +2 +1
Left Channel
+5 +4
Figure 8. Format 1, I²S up to 24-Bit Data
LRCK
SCLK
Channel A - Left
Left Channel
LSB
LSB
MSB
-1 -2 -3 -4
MSB
-1 -2 -3 -4
Channel B - Right
Right Channel
+3 +2 +1
+5 +4
Channel B - Right
Right Channel
+5 +4
Channel B - Right
Right Channel
LSB
LSB
SDATA
+6
LSB +5 +4 +3 +2
MSB-1 -2 -3 -4 -5
32 clocks
-6
+5 +4 +3 +2
+1 LSB
MSB-1-2-3-4-5
-6
+6
Figure 9. Format 2, Right Justified 16-Bit Data.
Format 3, Right Justified 24-Bit Data.
+1 LSB
25
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
p
(Inputs: Logic 0 = DGND, Logic 1 = VLC, C
Parameter Symbol Min Max Unit
SCL Clock Frequency f
RESET
Rising Edge to Start t
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 27) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA (Note 28) t
Fall Time SCL and SDA (Note 28) t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
=30pF)
L
scl
irs
buf
hdst
low
high
sust
hdd
sud
rc
fc
susp
ack
- 100 kHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 1000 ns
CS4245
Notes: 27. Data must be held for sufficient time to bridge the transition time, t
28. Guaranteed by design.
RST
t
irs
Stop S ta rt
SDA
SCL
t
buf
t
hdst
t
low
t
t
high
hdd
t
sud
t
ack
Figure 10. Control Port Timing - I²C Format
, of SCL.
fc
Repeated
Start
t
sust
t
t
hdst
Stop
rd
t
t
rc
t
fd
fc
t
sus
26
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, CL=30pF)
Parameter Symbol Min Typ Max Units
CS4245
CCLK Clock Frequency f
RESET
CS
CS
Rising Edge to CS Falling.
High Time Between Transmissions t
Falling to CCLK Edge t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 29) t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 30) t
Fall Time of CCLK and CDIN (Note 30) t
sck
t
srs
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
0-6.0MHz
500 - ns
1.0 - - µs
20 - - ns
66 - - ns
66 - - ns
40 - - ns
15 - - ns
- - 50 ns
- - 25 ns
- - 25 ns
- - 100 ns
- - 100 ns
Notes: 29. Data must be held for sufficient time to bridge the transition time of CCLK.
30. For f
<1 MHz.
sck
RST t
srs
CS
CCLK
CDIN
CDOUT
t
t
t
dsu
t
css
t
r2
Figure 11. Control Port Timing - SPI Format
scl
t
sch
f2
t
dh
t
pd
t
csh
27
CS4245
28
CS4245
4. APPLICATIONS
4.1 Recommended Power-Up Sequence
1) Hold RESET low until the power supply, MCLK1, MCLK2 (if used), LRCK1 and LRCK2 are stable. In this state,
the Control Port is reset to its default settings.
2) Bring RESET
will be accessible.
3) The desired register settings can be loaded while the PDN bit remains set.
4) Clear the PDN bit to initiate the power-up sequence.
4.2 System Clocking
The CS4245 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed
modes as shown in Table 1 below.
high. The device will remain in a low power state with the PDN bit set by default. The control port
Mode Sampling Frequency
Single Speed
Double Speed
Quad Speed
Table 1. Speed Modes
4-50 kHz
50-100 kHz
100-200 kHz
The CS4245 has two serial ports which may be operated synchronously or asynchronously. Serial port 1 consists
of the SCLK1 and LRCK1 signals and clocks the serial audio output, SDOUT. Serial port 2 consists of the SCLK2
and LRCK2 signals and clocks the serial audio input, SDIN.
Each serial port may be independently placed into Single, Double, or Quad Speed mode. The serial ports may also
be independently placed into Master or Slave mode.
4.2.1 Synchronous / Asynchronous Mode
By default, the CS4245 operates in synchronous mode with both serial ports synchronous to MCLK1. In this mode,
the serial ports may operate at different synchronous rates as set by the ADC_FM and DAC_FM bits, and MCLK2
does not need to be provided (the MCLK2 pin may be left unconnected).
If the Asynch bit is set (see “Asynchronous Mode (Bit 0)” on page 43), the CS4245 will operate in asynchronous
mode. The serial ports will operate asynchronously with Serial Port 1 clocked from MCLK1 and Serial Port 2 clocked
from MCLK2. In this mode, the serial ports may operate at different asynchronous rates.
4.2.2 Master Clock
In asynchronous mode MCLK1/LRCK1 and MCLK2/LRCK2 must maintain an integer ratio. In synchronous mode
MCLK1/LRCK1 and MCLK1/LRCK2 must maintain an integer ratio. Some common ratios are shown in Table 2.The
LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of
the device. The ADC_FM and DAC_FM bits and the MCLK Freq bits (see page 42) configure the device to generate
the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard
audio sample rates and the required MCLK and LRCK frequencies.
29
CS4245
LRCK
(kHz)
32
44.1
48
64
88.2
96
128
176.4
192
Mode
64x 96x 128x 192x 256x 384x 512x 768x 1024x
- ---8.1920 12.2880 16.3840 24.5760 32.7680
- ---11.2896 16.9344 22.5792 33.8680 45.1584
- ---12.2880 18.4320 24.5760 36.8640 49.1520
- - 8.1920 12.2880 16.3840 24.5760 32.7680 - -
- - 11.2896 16.9344 22.5792 33.8680 45.1584 - -
- - 12.2880 18.4320 24.5760 36.8640 49.1520 - -
8.1920 12.2880 16.3840 24.5760 32.7680 - - - -
11.2896 16.9344 22.5792 33.8680 45.1584 - - - -
12.2880 18.4320 24.5760 36.8640 49.1520 - - - -
QSM
MCLK (MHz)
DSM
SSM
Table 2. Common Clock Frequencies
4.2.3 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently placed into
Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK with LRCK equal to Fs
and SCLK equal to 64 x Fs as shown in Figure 13.
00
01
LRCK1
10
00
÷4
÷2
01
SCLK1
÷1
10
÷1
÷1. 5
÷2
÷3
÷4
000
001
010
011
100
÷256
÷128
÷64
4.2.4 Slave Mode
In Slave mode, SCLK and LRCK operate as inputs. Each serial port may be independently placed into Slave mode.
The Left/Right clock signal must be equal to the sample rate, Fs. If operating in asynchronous mode, LRCK1 must
be synchronously derived from MCLK1 and LRCK2 must be synchronously derived from MCLK2. If operating in synchronous mode, LRCK1, and LRCK2 must be synchronously derived from MCLK1. For more information on synchronous and asynchronous modes, see “Synchronous / Asynchronous Mode” on page 29.
30
CS4245
For each serial port, the serial bit clock must be equal to 128x, 64x, 48x or 32x Fs depending on the desired speed
mode. If operating in asynchronous mode, the serial bit clock SCLK1 must be synchronously derived from MCLK1
and SCLK2 must be synchronously derived from MCLK2. If operating in synchronous mode, SCLK1, and SCLK2
must be synchronously derived from MCLK1. Refer to Table 3 for required serial bit clock to Left/Right clock ratios.
Single Speed Double Speed Quad Speed
SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3 High Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven into the
A/D converter. The CS4245 includes a high pass filter after the decimator to remove any DC offset which could result
in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the
HPFFreeze bit (see page 42) is set during normal operation, the current value of the DC offset for the each channel
is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible
to perform a system DC offset calibration by:
1) Running the CS4245 with the high pass filter enabled until the filter settles. See the ADC Digital Filter Characteristics section for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration
point and the CS4245.
4.4 Analog Input Multiplexer, PGA, and Mic Gain
The CS4245 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA).
The input multiplexer can select one of 6 possible stereo analog input sources and route it to the PGA.
Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing them to be
used for microphone level signals without the need for any external gain. The PGA stage provides ±12 dB of gain
or attenuation in 0.5 dB steps. Figure 14 shows the architecture of the input multiplexer, PGA, and mic gain stages.
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
AIN5A
AIN6A
AIN1B
AIN2B
AIN3B
AIN4B/MICIN2
AIN5B
AIN6B
+32 dB
+32 dB
Analog Input
Selec tio n Bits
MUX
PGAMU X
Channel A
PGA Ga in Bits
Channel B
PGA Ga in Bits
PGA
Out to ADC
Channel A
Out to ADC
Channel B
Figure 14. Analog Input Architecture
The “Analog Input Selection (Bits 2:0)” section on page 45 outlines the bit settings necessary to control the input
multiplexer and mic gain. “Channel A PGA Control - Address 07h” on page 43 and “Channel B PGA Control - Ad-
31
CS4245
dress 08h” on page 44 outlines the register settings necessary to control the PGA. By default, line level input 1 is
selected, and the PGA is set to 0 dB.
4.5 Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n
passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input
circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient
(such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog
input pairs should be left unconnected.
4.6 Output Connections
The CS4245 DAC’s implement a switched-capacitor filter followed by a continuous time low pass filter. Its response,
combined with that of the digital interpolator, is shown in the “DAC Filter Plots” section beginning on page 50. The
recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4245 DAC is a linear phase design and does not include phase or amplitude compensation for an external
filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
4.7 Output Transient Control
The CS4245 uses Popguard™ technology to minimize the effects of output transients during power-up and powerdown. This technique eliminates the audio transients commonly produced by single-ended single-supply converters
when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make
best use of this feature, it is necessary to understand its operation.
× 6.144 MHz) the digital
4.7.1 Power-up
When the device is initially powered-up, the audio outputs AOUTA and AOUTB are clamped to VQ2 which is initially
low. After the PDN bit is released (set to ‘0’) the DAC outputs begin to ramp with VQ2 towards the nominal quiescent
voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ2, effectively blocking the quiescent DC voltage. Audio output will begin
after approximately 2000 sample periods.
4.7.2 Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the
power. In order to do this either the PDN bit should be set or the device should be reset about 250 ms before removing power. During this time, the voltage on VQ2 and the DAC outputs discharge gradually to GND. If power is removed before this 250 ms time period has passed a transient will occur when the VA supply drops below that of
VQ2. There is no minimum time for a power cycle, power may be re-applied at any time.
4.7.3 Serial Interface Clock Changes
When changing the DAC clock ratio or sample rate it is recommended that zero data (or near zero data) be present
on SDIN for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will
always be in a zero data state. If non-zero serial audio input is present at the time of switching, a slight click or pop
may be heard as the DAC output automatically goes to it’s zero data state.
4.8 Auxiliary Analog Output
The CS4245 includes an auxiliary analog output through the AUXOUT pins. These pins can be configured to output
the analog input to the ADC as selected with the input MUX and gained or attenuated with the PGA, the analog output of the DAC, or alternatively they may be set to high-impedance. See the “Auxiliary Output Source Select (Bits
6:5)” section on page 43 for information on configuring the auxiliary analog output.
32
CS4245
The auxiliary analog output can source very little current. As current from the AUXOUT pins increases, distortion will
increase. For this reason, a high input impedance buffer must be used on the AUXOUT pins to achieve full performance. Refer to the Auxiliary Output Analog Characteristics table on page 18 for acceptable loading conditions.
4.9 De-Emphasis Filter
The CS4245 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is
shown in Figure 15. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 6.3.4 for de-emphasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction.
De-emphasis is only available in Single Speed Mode.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1 F2
3.183 kHz 10.61 kHz
Figure 15. De-Emphasis Curve
Frequency
4.10 Internal Digital Loopback
The CS4245 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the
DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (06h - See page 43). To
use this mode, the ADC and DAC must be operating at the same synchronous sample rate.
When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4245. Any
changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until the LOOP
bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the format selected by
the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin in the format selected by
the ADC_DIF bit in register 04h.
4.11 Mute Control
The MUTEC pin becomes active during power-up initialization, reset, muting, if the MCLK2 to LRCK2 ratio is incorrect in asynchronous mode or the MCLK1 to LRCK2 ratio is incorrect in synchronous mode, and during power-down.
The MUTEC
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in
extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle
pin is intended to be used as control for an external mute circuit in order to add off-chip mute capability.
33
CS4245
channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTEC pin is an activelow CMOS driver. See Figure 16 below for a suggested active-low mute circuit.
+V
EE
AOUT
CS4245
MUTEC
LPF
AC
Couple
-V
EE
+V
A
MMUN2111LT1
47 kΩ
-V
EE
560 Ω
2 kΩ
10 kΩ
Audio
Out
Figure 16. Suggested Active-Low Mute Circuit
4.12 Control Port Description and Timing
The control port is used to access the registers, allowing the CS4245 to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to the audio
sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
The control port has 2 modes: SPI and I²C, with the CS4245 acting as a slave device. SPI mode is selected if there
is a high to low transition on the AD0/CS
connecting the AD0/CS
pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit
address state.
pin, after the RESET pin has been brought high. I²C mode is selected by
4.12.1 SPI Mode
In SPI mode, CS is the CS4245 chip select signal, CCLK is the control port bit clock (input into the CS4245 from the
microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 17 shows the operation of the control port in SPI mode. To write to a register, bring CS
bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W
should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of
the register that is to be updated. The next eight bits are the data which will be placed into the register designated
by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a
47 kΩ resistor, if desired.
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP
will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is
read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS
high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin
a read, bring CS
low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK
34
low. The first seven
), which
CS4245
will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively.
CS
CCLK
CHIP
ADDRESS
1001111
R/W
MSB
LSB
MSB
LSB
CDIN
CDOUT
CHIP
ADDRESS
1001111
High Impedance
MAP = Memory Address Pointer, 8 bits, MSB first
R/W
MAP
DATA
MSB
byte 1
LSB
byte n
Figure 17. Control Port Timing in SPI Mode
4.12.2 I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no
CS
pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through
a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS4245 is being reset.
The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is defined as
a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All
other transitions of SDA occur while the clock is low. The first byte sent to the CS4245 after a Start condition consists
of a 7 bit chip address field and a R/W
are fixed at 10011. To communicate with a CS4245, the chip address field, which is the first byte sent to the CS4245,
should match 10011 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W
operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or
written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto
increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4245 after each input byte is read, and is input to the CS4245 from
the microcontroller after each transmitted byte.
bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field
bit. If the
SCL
SDA
0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28
CHIP ADDRESS (WRITE) MAP BYTE DATA
1 0 0 1 1 AD1 AD0 0
START
4 5 6 7 24 25
INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
ACK
Figure 18. Control Port Timing, I²C Write
26
DATA +1
DATA +n
ACKACKACK
STOP
35
CS4245
2 3 10 11 17 18 19 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE
SDA 1 0 0 1 1 AD1 AD0 1
1 0 0 1 1 AD1 AD0 0
START
INCR 6 5 4 3 2 1 0
ACK
168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24
STOP
ACK
START
CHIP ADDRESS (READ)
26 27 28
DATA
7 0 7 0 7 0
ACK
DATA +1
ACK
DATA + n
NO
ACK
STOP
Figure 19. Control Port Timing, I²C Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in
Figure 19, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The
following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
36
CS4245
4.13 Interrupts and Overflow
The CS4245 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin
on the host microcontroller. The INT pin may function as either an active high CMOS driver or an active low opendrain driver (see “Active High/Low (Bit 0)” on page 46). When configured as active low open-drain, the INT pin has
no active pull-up transistor, allowing it to be used for wired-OR hook-ups with multiple peripherals connected to the
microcontroller interrupt input pin. In this configuration, an external pull-up resistor must be placed on the INT pin for
proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Interrupt Status
- Address 0Dh” on page 46. Each source may be masked off through mask register bits. In addition, each source
may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the
equipment designer.
The CS4245 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no
active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register, however, these conditions do not
need to be unmasked for proper operation of the OVFL pin.
4.14 Reset
When RESET is low, the CS4245 enters a low power mode and all internal states are reset, including the control
port and registers, and the outputs are muted. When RESET
desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register
will then cause the part to leave the low power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through
the application of power or by setting the RESET
reach a final value due to the presence of external capacitance on the FILT1+ and FILT2+ pins. During this voltage
reference ramp delay, both SDOUT and DAC outputs will be automatically muted.
It is recommended that RESET
condition to prevent power glitch related issues.
be activated if the analog or digital supplies drop below the recommended operating
pin high. However, the voltage reference will take much longer to
is high, the control port becomes operational and the
4.15 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS4245’s in the system. If only one master clock source is needed, one solution is to place one CS4245 in Master Mode, and slave all
of the other CS4245’s to the one master. If multiple master clock sources are needed, a possible solution would be
to supply all clocks from the same external source and time the CS4245 reset with the inactive edge of master clock.
This will ensure that all converters begin sampling on the same clock edge.
4.16 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4245 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 12 shows the recommended power arrangements, with
VA connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply (VLS
or VLC) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be
powered from VD. Power supply decoupling capacitors should be as near to the CS4245 as possible, with the low
value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT1+,
FILT2+, VQ1 and VQ2 pins in order to avoid unwanted coupling into the modulators. The FILT1+, FILT2+, VQ1 and
VQ2 decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT1+
and FILT2+ and AGND. The CS4245 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS4245 digital outputs only to CMOS inputs.
37
CS4245
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function 7 6 5 4 3 2 1 0
01h Chip ID
02h Power Control Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC PDN_DAC PDN
03h DAC Control 1
04h ADC Control
05h MCLK
Frequency
06h Signal Selec-
tion
07h PGA Ch B Gain
Control
08h PGA Ch A Gain
Control
09h Analog Input
Control
0Ah DAC Ch A Vol-
ume Control
0Bh DAC Ch B Vol-
ume Control
0Ch DAC Control 2
0Dh Interrupt Status Reserved Reserved Reserved Reserved ADCClkErr DACClkErr ADCOvfl ADCUndrfl
0Eh Interrupt Mask Reserved Reserved Reserved Reserved ADCClkErrM DACClkErrM ADCOvflM ADCUndrflM
0Fh Interrupt Mode
MSB
10h Interrupt Mode
LSB
PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
110 0 0 0 0 1
000 0 0 0 0 1
DAC_FM1 DAC_FM0 DAC_DIF1 DAC_DIF0 Reserved MuteDAC DeEmph
000 0 1 0 0 0
ADC_FM1 ADC_FM0 Reserved ADC_DIF Reserved MuteADC HPFFreeze ADC_M/S
000 0 0 0 0 0
Reserved
000 0 0 0 0 0
Reserved AOutSel1 AOutSel0 Reserved Reserved Reserved LOOP ASynch
010 0 0 0 0 0
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
000 0 0 0 0 0
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
000 0 0 0 0 0
Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0
000 1 1 0 0 1
Vol7 Vol6 Vol5 Vol4 Vol3 Vo l2 Vol1 Vo l0
000 0 0 0 0 0
Vol7 Vol6 Vol5 Vol4 Vol3 Vo l2 Vol1 Vo l0
000 0 0 0 0 0
DACSoft DACZero InvertDAC Reserved Reserved Reserved Reserved Active_H/L
110 0 0 0 0 0
000 0 0 0 0 0
000 0 0 0 0 0
Reserved Reserved Reserved Reserved ADCClkErr1 DACClkErr1 ADCOvfl1 ADCUndrfl1
000 0 0 0 0 0
Reserved Reserved Reserved Reserved ADCClkErr0 DACClkErr0 ADCOvfl0 ADCUndrfl0
000 0 0 0 0 0
MCLK1
Freq2
MCLK1
Freq1
MCLK1
Freq0
Reserved
MCLK2
Freq2
MCLK2
Freq1
DAC_M/S
MCLK2
Freq0
38
CS4245
6. REGISTER DESCRIPTION
6.1 Chip ID - Register 01h
B7 B6 B5 B4 B3 B2 B1 B0
PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID which is 1100b (0Ch) and the remaining bits (3 through 0) are for the chip revision.
6.2 Power Control - Address 02h
76543210
Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC PDN_DAC PDN
6.2.1 Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking
effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the
Freeze function are listed in Table 4 below.
Name Register Bit(s)
MuteDAC 03h 2
MuteADC 04h 2
Gain[5:0] 07h 5:0
Gain[5:0] 08h 5:0
Vol[7:0] 0Ah 7:0
Vol[7:0] 0Bh 7:0
6.2.2 Power Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3 Power Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
6.2.4 Power Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
Table 4. Freeze-able Bits
6.2.5 Power Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default
and must be cleared before normal operation can occur. The contents of the control registers are retained when the device is in power-down.
39
CS4245
6.3 DAC Control - Address 03h
76543210
DAC_FM1 DAC_FM0 DAC_DIF1 DAC_DIF0 Reserved MuteDAC DeEmph DAC_M/S
6.3.1 DAC Functional Mode (Bits 7:6)
Function:
Selects the required range of input sample rates.
Table 5. Functional Mode Selection
DAC_FM1 DAC_FM0 Mode
0 0 Single-Speed Mode: 4 to 50 kHz sample rates
0 1 Double-Speed Mode: 50 to 100 kHz sample rates
1 0 Quad-Speed Mode: 100 to 200 kHz sample rates
11Reserved
6.3.2 DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital
Interface Format and the options are detailed in Table 6 and Figures 7-9.
Table 6. DAC Digital Interface Formats
DAC_DIF1 DAC_DIF0 Description Format Figure
0 0 Left Justified, up to 24-bit data (default) 0 7
01
1 0 Right Justified, 16-bit Data 2 9
1 1 Right Justified, 24-bit Data 3 9
2
S, up to 24-bit data
I
6.3.3 Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this
bit is active high, it should be noted that the MUTEC pin is active low. The common mode voltage on
the outputs will be retained when this bit is set. The muting function is effected, similar to attenuation
changes, by the DACSoft and DACZero bits in the DAC Control 2 register.
6.3.4 De-Emphasis Control (Bit 1)
Function:
The standard 50/15 µs digital de-emphasis filter response, Figure 20, may be implemented for a sample rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 7 below. NOTE: De-emphasis is available only in Single-Speed Mode.
Table 7. De-Emphasis Control
DeEmph Description
0 Disabled (default)
1 44.1 kHz de-emphasis
18
40
Gain
dB
0dB
-10dB
CS4245
T1=50 µs
T2 = 15 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 20. De-Emphasis Curve
Frequency
6.3.5 DAC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 2. Setting this bit will select master
mode, while clearing this bit will select slave mode.
6.4 ADC Control - Address 04h
76543210
ADC_FM1 ADC_FM0 Reserved ADC_DIF Reserved MuteADC HPFFreeze ADC_M/S
6.4.1 ADC Functional Mode (Bits 7:6)
Function:
Selects the required range of output sample rates.
Table 8. Functional Mode Selection
ADC_FM1 ADC_FM0 Mode
0 0 Single-Speed Mode: 4 to 50 kHz sample rates
0 1 Double-Speed Mode: 50 to 100 kHz sample rates
1 0 Quad-Speed Mode: 100 to 200 kHz sample rates
11Reserved
6.4.2 ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Interface Format bit. The options are detailed in Table 9 and may be seen in Figure 7 and 8.
Table 9. ADC Digital Interface Formats
ADC_DIF Description Format Figure
0 Left Justified, up to 24-bit data (default) 0 7
1
2
S, up to 24-bit data
I
18
41
CS4245
6.4.3 Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels will be muted.
6.4.4 ADC High Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be
frozen and continue to be subtracted from the conversion result. See “High Pass Filter and DC Offset
Calibration” on page 31.
6.4.5 ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit will select master
mode, while clearing this bit will select slave mode.
6.5 MCLK Frequency - Address 05h
76543210
Reserved
MCLK1
Freq2
MCLK1
Freq1
MCLK1
Freq0
Reserved
MCLK2
Freq2
MCLK2
Freq1
MCLK2
Freq0
6.5.1 Master Clock 1 Frequency (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK1 signal. See Table 10 below for the appropriate settings.
Table 10. MCLK1 Frequency
MCLK1 Divider MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0
÷1 000
÷1.5 001
÷2 010
÷3 011
÷4 100
Reserved 101
Reserved 11x
6.5.2 Master Clock 2 Frequency (Bits 2:0)
Function:
Sets the frequency of the supplied MCLK2 signal. See Table 11 below for the appropriate settings.
42
CS4245
Table 11. MCLK2 Frequency
MCLK2 Divider MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0
÷1 000
÷1.5 001
÷2 010
÷3 011
÷4 100
Reserved 101
Reserved 11x
6.6 Signal Selection - Address 06h
76543210
Reserved AOutSel1 AOutSel0 Reserved Reserved Reserved LOOP ASynch
6.6.1 Auxiliary Output Source Select (Bits 6:5)
Function:
These bits are used to select the analog output source. Please refer to Table 12 below.
Table 12. Auxiliary Output Source Selection
AOutSel1 AOutSel0 Auxiliary Output Source
0 0 High Impedance
0 1 DAC Output
1 0 PGA Output
11 Reserved
6.6.2 Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer
to “Internal Digital Loopback” on page 33.
6.6.3 Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent an asynchronous sample
rates derived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at
synchronous sample rates derived from MCLK1.
6.7 Channel A PGA Control - Address 07h
76543210
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
6.7.1 Channel A PGA Gain (Bits 5:0)
Function:
See “Channel B PGA Gain (Bits 5:0)” on page 44.
43
CS4245
6.8 Channel B PGA Control - Address 08h
76543210
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
6.8.1 Channel B PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 13 for
example settings.
Table 13. Example Gain and Attenuation Settings
Gain[5:0] Setting
101000 -12 dB
000000 0 dB
011000 +12 dB
6.9 ADC Input Control - Address 09h
76543210
Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods. See Table 14 on page 45.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 14 on page 45.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel. See Table 14 on page 45.
44
Table 14. PGA Soft Cross or Zero Cross Mode Selection
PGASoft PGAZeroCross Mode
0 0 Changes to affect immediately
0 1 Zero Cross enabled
1 0 Soft Ramp enabled
1 1 Soft Ramp and Zero Cross enabled (default)
6.9.2 Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 15 below.
Table 15. Analog Input Multiplexer Selection
Sel2 Sel1 Sel0 PGA/ADC Input
0 0 0 Microphone Level Inputs (+32 dB Gain Enabled)
0 0 1 Line Level Input Pair 1
0 1 0 Line Level Input Pair 2
0 1 1 Line Level Input Pair 3
1 0 0 Line Level Input Pair 4
1 0 1 Line Level Input Pair 5
1 1 0 Line Level Input Pair 6
1 1 1 Reserved
CS4245
6.10 DAC Channel A Volume Control - Address 0Ah
See 6.11 DAC Channel B Volume Control - Address 0Bh
6.11 DAC Channel B Volume Control - Address 0Bh
76543210
Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0
6.11.1 Volume Control (Bits 7:0)
Function:
The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to
-127 dB. The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The
Vol[7:1] bits activate attenuation equal to their decimal equivalent (in dB). Example volume settings
are decoded as shown in Table Table 16. The volume changes are implemented as dictated by the
DACSoft and DACZeroCross bits in the DAC Control 2 register (see section 6.12.1).
Table 16. Digital Volume Control Example Settings
Binary Code Volume Setting
00000000 0 dB
00000001 -0.5 dB
00101000 -20 dB
00101001 -20.5 dB
11111110 -127 dB
11111111 -127.5 d B
45
CS4245
6.12 DAC Control 2 - Address 0Ch
76543210
DACSoft DACZero InvertDAC Reserved Reserved Reserved Reserved Active_H/L
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods. See Table 17 on page 46.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 17 on page 46.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel. See Table 17 on page 46.
Table 17. DAC Soft Cross or Zero Cross Mode Selection
DACSoft DACZeroCross Mode
0 0 Changes to affect immediately
0 1 Zero Cross enabled
1 0 Soft Ramp enabled
1 1 Soft Ramp and Zero Cross enabled (default)
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC will be inverted.
6.12.3 Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin will function as an active high CMOS driver.
When this bit is cleared, the INT pin will function as an active low open drain driver and will require an
external pull-up resistor for proper operation.
6.13 Interrupt Status - Address 0Dh
76543210
Reserved Reserved Reserved Reserved ADCClkErr DACClkErr ADCOvfl ADCUndrfl
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once
since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred
46
since the last reading of the register. Status bits that are masked off in the associated mask register
will always be ‘0’ in this register. This register defaults to 00h.
6.13.1 ADC Clock Error (Bit 3)
Function:
Indicates the occurrence of an ADC clock error condition.
6.13.2 DAC Clock Error (Bit 2)
Function:
Indicates the occurrence of a DAC clock error condition.
6.13.3 ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4 ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
CS4245
6.14 Interrupt Mask - Address 0Eh
76543210
Reserved Reserved Reserved Reserved ADCClkErrM DACClkErrM ADCOvflM ADCUndrflM
Function:
The bits of this register serve as a mask for the Status sources found in the register “Interrupt Status
- Address 0Dh” on page 46. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the
corresponding bits in the Status register.
6.15 Interrupt Mode MSB - Address 0Fh
6.16 Interrupt Mode LSB - Address 10h
76543210
Reserved Reserved Reserved Reserved ADCClkErr1 DACClkErr1 ADCOvfl1 ADCUndrfl1
Reserved Reserved Reserved Reserved ADCClkErr0 DACClkErr0 ADCOvfl0 ADCUndrfl0
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There
are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge
active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge
active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active
mode, the INT pin remains active during the interrupt condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
47
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
CS4245
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
48
8. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
D1
D
CS4245
E
E1
1
e
∝
B
A
A1
L
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A --- 0.055 0.063 --- 1.40 1.60
A1 0.002 0.004 0.006 0.05 0.10 0.15
B 0.007 0.009 0.011 0.17 0.22 0.27
D 0.343 0.354 0.366 8.70 9.0 BSC 9.30
D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
E 0.343 0.354 0.366 8.70 9.0 BSC 9.30
E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60
L 0.018 0.24 0.030 0.45 0.60 0.75
∝
* Nominal pin pitch is 0.50 mm *Controlling dimension is mm. *JEDEC Designation: MS022
0.000° 4° 7.000° 0.00° 4° 7.00°
9. THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters Symbol Min Typ Max Units
Package Thermal Resistance (Note 31) 48-LQFP θ
Allowable Junction Temperature - - 125 °C
JA
θ
JC
-
-
48
15
-
-
°C/Watt
°C/Watt
Notes: 31. θJA is specified according to JEDEC specifications for multi-layer PCBs.
49
APPENDIX A: DAC FILTER PLOTS
CS4245
50
CS4245
51
APPENDIX B: ADC FILTER PLOTS
CS4245
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Amplitude (dB)
- 110
-120
-130
-140
0.0 0.1 0 .2 0 .3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs )
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Amplitude (dB)
- 110
-120
-130
-140
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs )
Figure 33. ADC Single Speed Stopband Rejection Figure 34. ADC Single Speed Stopband Rejection
0
-1
-2
-3
-4
-5
-6
-7
Amplitude (dB)
-8
-9
-10
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Fr eque ncy (normalized to Fs)
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
Amplitude (dB)
-0.06
-0.08
-0.10
0 0.0 5 0 .1 0.15 0.2 0.2 5 0 .3 0 .35 0 .4 0 .45 0 .5
Freque ncy (nor m alized to Fs)
Figure 35. ADC Single Speed Transition Band (Detail) Figure 36. ADC Single Speed Passband Ripple
Figure 37. ADC Double Speed Stopband Rejection Figure 38. ADC Double Speed Stopband Rejection
52
CS4245
0
-1
-2
-3
-4
-5
-6
-7
Amplitude (dB)
-8
-9
-10
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Fr eque ncy (normalized to Fs)
Figure 39. ADC Double Speed Transition Band (De-
tail)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Amplitude (dB)
- 110
-120
-130
-140
0.0 0.1 0 .2 0 .3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs )
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
Amplitude (dB)
-0.06
-0.08
-0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0 .50
Freque ncy (nor m alized to Fs)
Figure 40. ADC Double Speed Passband Ripple
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Amplitude (dB)
- 110
-120
-130
-140
0.20 0.2 5 0. 30 0.35 0.4 0 0.45 0.5 0 0.55 0.60 0.65 0 .70 0.75 0. 80 0.85
Frequency (normalized to Fs )
Figure 41. ADC Quad Speed Stopband Rejection Figure 42. ADC Quad Speed Stopband Rejection
0
-1
-2
-3
-4
-5
-6
-7
Amplitude (dB)
-8
-9
-10
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Fr eque ncy (normalized to Fs)
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
Amplitude (dB)
-0.06
-0.08
-0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (normalized to Fs )
Figure 43. ADC Quad Speed Transition Band (Detail) Figure 44. ADC Quad Speed Passband Ripple
53
Release Date Changes
A1 May 2004 Initial Advance Release.
PP1 August 2004 Preliminary Release.
– Updated the VA power-down mode supply current specification on
page 19.
Table 18. Revision History
CS4245
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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54
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