CIRRUS LOGIC CS4245 Service Manual

CS4245

105 dB, 24-Bit, 192 kHz Stereo Audio CODEC

D/A Features



Multi-bit Delta Sigma modulator



105 dB dynamic range



-95 dB THD+N



Up to 192 kHz sampling rates



Single-ended analog architecture



Volume control with soft ramp

– 0.5 dB step size – Zero crossing click-free transitions



PopguardTM Technology

– Minimizes the effects of output transients



Filtered line level outputs



Selectable serial audio interface formats

– Left justified up to 24-bit – I²S up to 24-bit – Right justified 16, 18, 20 and 24-bit



Selectable 50/15 µs de-emphasis



Control Output for External Muting

A/D Features



Multi-bit Delta Sigma modulator



105 dB dynamic range



-95 dB THD+N



Stereo 6:1 Input Multiplexer



Programmable Gain Amplifier (PGA)

– +/- 12 dB gain, 0.5 dB step size – Zero crossing, click-free transitions



Stereo microphone inputs

– +32 dB gain stage – Low noise bias supply



Up to 192 kHz sampling rates



Selectable serial audio interface formats

– Left justified up to 24-bit – I²S up to 24-bit



High pass filter or DC offset calibration

3.3 V to 5 V 3.3 V to 5 V

Filter

Serial Audio

Input

I2C/SPI

Control Data

Interrupt

ADC Overflow

Reset

Serial Audio

Output

1.8 V to 5 V

Level

Translator

Level Translator

Level

Translator

PCM Serial InterfacePCM Serial Interface

Volum e

Control

Volume

Control

High Pass

Preliminary Product Information

Cirrus Logic, Inc.

www.cirrus.com

Interpolation

Filter

Interpolation

Filter

Linear Phase

Anti-Alias Filter

Linear Phase

Anti-Alias Filter

Multibit

∆Σ Modulator

Multibit

∆Σ Modulator

Internal Volt age

Oversampling

Reference

Multibit

ADC

Multibit

ADC

Swit ched Capacitor

DAC and Filter

Swit ched Capacitor

DAC and Filter

PGA

MUX

Mute

Control

MUX

+32 dB

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Left DAC Output

Mute Control

Right DAC Output

Left Aux Output Right Aux Output

Stereo Inp ut 1 Stereo Inp ut 2 Stereo Inp ut 3

Stereo Inp ut 4 / Mic Input 1 & 2

Stereo Inp ut 5 Stereo Inp ut 6

AUG ‘04

DS656PP1

CS4245

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................... 5

2. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 8

SPECIFIED OPERATING CONDITIONS................................................................................. 8

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8

DAC ANALOG CHARACTERISTICS ....................................................................................... 9

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 10

ADC ANALOG CHARACTERISTICS ..................................................................................... 12

ADC ANALOG CHARACTERISTICS ..................................................................................... 14

ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 15

AUXILIARY OUTPUT ANALOG CHARACTERISTICS .......................................................... 16

AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT’D) ......................................... 17

AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT’D) ......................................... 18

DC ELECTRICAL CHARACTERISTICS ................................................................................ 19

DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 20

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1.............................................. 21

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2.............................................. 23

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ................................ 26

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 27

3. TYPICAL CONNECTION DIAGRAM .................................................................................... 28

4. APPLICATIONS .................................................................................................................... 29

4.1 Recommended Power-Up Sequence ............................................................................. 29

4.2 System Clocking ............................................................................................................. 29

4.2.1 Synchronous / Asynchronous Mode .................................................................. 29

4.2.2 Master Clock ...................................................................................................... 29

4.2.3 Master Mode ...................................................................................................... 30

4.2.4 Slave Mode ........................................................................................................ 30

4.3 High Pass Filter and DC Offset Calibration .................................................................... 31

4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................ 31

4.5 Input Connections ........................................................................................................... 32

4.6 Output Connections ........................................................................................................32

4.7 Output Transient Control ................................................................................................ 32

4.7.1 Power-up ............................................................................................................ 32

4.7.2 Power-down ....................................................................................................... 32

4.7.3 Serial Interface Clock Changes ......................................................................... 32

4.8 Auxiliary Analog Output .................................................................................................. 32

4.9 De-Emphasis Filter ......................................................................................................... 33

4.10 Internal Digital Loopback .............................................................................................. 33

4.11 Mute Control ................................................................................................................. 33

4.12 Control Port Description and Timing ............................................................................. 34

4.12.1 SPI Mode ......................................................................................................... 34

4.12.2 I²C Mode .......................................................................................................... 35

4.13 Interrupts and Overflow ................................................................................................ 37

4.14 Reset ........................................................................................................................... 37

4.15 Synchronization of Multiple Devices ............................................................................. 37

4.16 Grounding and Power Supply Decoupling .................................................................... 37

5. REGISTER QUICK REFERENCE ......................................................................................... 38

6. REGISTER DESCRIPTION ................................................................................................... 39

6.1 Chip ID - Register 01h ....................................................................................................39

6.2 Power Control - Address 02h ......................................................................................... 39

6.3 DAC Control - Address 03h ............................................................................................ 40

6.4 ADC Control - Address 04h ............................................................................................ 41

6.5 MCLK Frequency - Address 05h .................................................................................... 42

CS4245

6.6 Signal Selection - Address 06h ....................................................................................... 43

6.7 Channel A PGA Control - Address 07h ........................................................................... 43

6.8 Channel B PGA Control - Address 08h ........................................................................... 44

6.9 ADC Input Control - Address 09h ...................................................................................44

6.10 DAC Channel A Volume Control - Address 0Ah ........................................................... 45

6.11 DAC Channel B Volume Control - Address 0Bh ........................................................... 45

6.12 DAC Control 2 - Address 0Ch ....................................................................................... 46

6.13 Interrupt Status - Address 0Dh ..................................................................................... 46

6.14 Interrupt Mask - Address 0Eh ....................................................................................... 47

6.15 Interrupt Mode MSB - Address 0Fh ..............................................................................47

6.16 Interrupt Mode LSB - Address 10h ............................................................................... 47

7. PARAMETER DEFINITIONS .................................................................................................48

8. PACKAGE DIMENSIONS ...................................................................................................... 49

9. THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................. 49

Appendix A: DAC Filter Plots ......................................................................................... 50

Appendix B: ADC Filter Plots .............................................................................................. 52

1. PIN DESCRIPTIONS

SCL/CCLK

AD0/CS

AD1/CDIN

VLC

RESET

AIN3A

AIN3B

AIN2A

AIN2B

AIN1A

AIN1B

OVFL

INT

DGND

MCLK1

LRCK1

SCLK1

SDOUT

48 47 46 45 44 43 42 41 40 39 38 37

CS4245

MCLK2

LRCK2

SCLK2

SDIN

VLSSDA/CDOUT

MUTEC

AOUTB

AOUTA

AGND

AUXOUTB

AUXOUTA

AIN6B

AIN6A

MICBIAS

Pin Name # Pin Description

SDA/CDOUT

SCL/CCLK

AD0/CS

AD1/CDIN

VLC

RESET

AIN3A AIN3B

Serial Control Data (

the control port interface in SPI mode.

Serial Control Port Clock (

Address Bit 0 (I²C) / Control Port Chip Select (SPI)

is the chip select signal for SPI format.

Address Bit 1 (I²C) / Serial Control Data Input (SPI)

CDIN is the input data line for the control port interface in SPI mode.

Control Port Power (

to the Recommended Operating Conditions for appropriate voltages.

Reset (

Input

Stereo Analog Input 3 ( specification table.

) - The device enters a low power mode when this pin is driven low.

13 14 15 16 17 18 19 20 21 22 23 24

AGND

Input/Output

VQ1

VQ2

FILT1+

AFILTA

AFILTB

FILT2+

AIN4A/MICIN1

AIN5A

AIN4B/MICIN2

) - SDA is a data I/O in I²C mode. CDOUT is the output data line for

Input

) - Serial clock for the serial control port.

(Input)

Input

) - Determines the required signal level for the control port interface. Refer

Input

) - The full scale level is specified in the ADC Analog Characteristics

AIN5B

- AD0 is a chip address pin in I²C mode;

- AD1 is a chip address pin in I²C mode;

CS4245

AIN2A AIN2B

AIN1A AIN1B

AGND

AFILTA

AFILTB

VQ1

VQ2

FILT1+

FILT2+

AIN4A/MICIN1 AIN4B/MICIN2

AIN5A AIN5B

MICBIAS

AIN6A AIN6B

Stereo Analog Input 2 ( specification table.

11,

Stereo Analog Input 1 ( specification table.

13 Analog Ground (

Analog Power

Antialias Filter Connection (

Quiescent Voltage 1 (

(Input)

18 Quiescent Voltage 2 (

19 Positive Voltage Reference 1 (

Positive Voltage Reference 2 (

21,

Stereo Analog Input 4 / Microphone Input 1 & 2 ( Analog Characteristics specification table.

23,

Stereo Analog Input 5 ( specification table.

Microphone Bias Supply (

teristics are specified in the DC Electrical Characteristics specification table.

26,

Stereo Analog Input 6 ( specification table.

Input

) - The full scale level is specified in the ADC Analog Characteristics

Input

) - The full scale level is specified in the ADC Analog Characteristics

Input

) - Ground reference for the internal analog section.

- Positive power for the internal analog section.

Output

) - Antialias filter connection for the channel A ADC input.

Output

) - Antialias filter connection for the channel B ADC input.

Output

) - Filter connection for the internal quiescent reference voltage.

Output

) - Filter connection for the internal quiescent reference voltage.

Output

) - Positive reference voltage for the internal sampling circuits.

Output

) - Positive reference voltage for the internal sampling circuits.

Input

) - The full scale level is specified in the ADC

Input

) - The full scale level is specified in the ADC Analog Characteristics

Output

) - Low noise bias supply for external microphone. Electrical charac-

Input

) - The full scale level is specified in the ADC Analog Characteristics

AUXOUTA AUXOUTB

AGND

AOUTA AOUTB

MUTEC

VLS

SDIN

SCLK2

LRCK2

MCLK2

SDOUT

SCLK1

LRCK1

28,

Auxiliary Analog Audio Output ( impedance. See “Auxiliary Output Source Select (Bits 6:5)” on page 43.

Analog Power

31,

Analog Ground (

33,

DAC Analog Audio Output ( acteristics specification table.

Mute Control

clock to left/right clock frequency ratio is incorrect, or power-down.

Serial Audio Interface Power (

face. Refer to the Recommended Operating Conditions for appropriate voltages.

Serial Audio Data Input (

(Input)

Input

(Output)

- Positive power for the internal analog section.

) - Ground reference for the internal analog section.

- This pin is active during power-up initialization, reset, muting, when master

Input

38 Serial Port 2 Serial Bit Clock

Serial Port 2 Left Right Clock

active on the serial audio input data line.

Master Clock 2 (

lators.

Input/Output

41 Serial Audio Data Output (

Serial Port 1 Serial Bit Clock

Serial Port 1 Left Right Clock

active on the serial audio output data line.

Output

) - Analog output from either the DAC, the PGA block, or high

Output

) - The full scale output level is specified in the DAC Analog Char-

Input

) - Determines the required signal level for the serial audio inter-

) - Input for two’s complement serial audio data.

(Input/Output

) -Optional asynchronous clock source for the DAC’s delta-sigma modu-

Output

) - Output for two’s complement serial audio data.

(Input/Output

) - Serial bit clock for serial audio interface 2.

) - Determines which channel, Left or Right, is currently

) - Serial bit clock for serial audio interface 1.

) - Determines which channel, Left or Right, is currently

CS4245

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to

ground.)

ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V All voltages with respect to ground.) (Note

= 25°C.)

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port

Ambient Operating Temperature (Power Applied) T

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port

Input Current (Note 2) I

Analog Input Voltage V

Digital Input Voltage Logic - Serial Port

Logic - Control Port

Ambient Operating Temperature (Power Applied) T

Storage Temperature T

VLS

VLC

VLS VLC

IND-S

IND-C

VA VD

INA

stg

3.1

1.71

-10 - +70 °C

-0.3

AGND-0.3 - VA+0.3 V

-0.3

-20 - +85 °C

-65 - +150 °C

5.0

3.3

--±10 mA

--VLS+0.3

5.25

+6.0 +6.0 +6.0 +6.0

VLC+0.3VV

V V V V

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

CS4245

DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R

= 10 pF (see Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise speci-

= 3 kΩ,

fied.) Synchronous mode.

All Speed Modes

Parameter

Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range (Note 3)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 3)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

THD+N

96 99 87 90

102 105

93 96

-95

-82

-42

-93

-73

-33

-89

-76

-36

-87

-67

-27

dB dB dB dB

dB dB dB dB dB dB

Dynamic Performance for VA = 3.3 V

Dynamic Range (Note 3)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 3)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

THD+N

93 96 85 88

102

90 93

-92

-79

-39

-90

-70

-30

-84

-71

-31

-82

-62

-22

dB dB dB dB

dB dB dB dB dB dB

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 0.25 dB

Gain Drift - 100 - ppm/°C

Analog Output

Full Scale Output Voltage 0.60*VA 0.65*VA 0.70*VA V

DC Current draw from an AOUT pin (Note 4) I

OUT

AC-Load Resistance (Note 5) R

Load Capacitance (Note 5) C

Output Impedance Z

OUT

--10µA

3--kΩ

--100pF

- 100 - Ω

Note: 3. One-half LSB of triangular PDF dither added to data.

4. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors.

5. Guaranteed by design. See Figure 2. R

and CL reflect the recommended minimum resistance and

maximum capacitance required for the internal op-amp’s stability. C internal output amp; increasing C

beyond 100 pF can cause the internal op-amp to become unstable.

affects the dominant pole of the

CS4245

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Parameter (Note 6,9) Symbol Min Typ Max Unit

Combined Digital and On-chip Analog Filter Response Single Speed Mode

Passband (Note 6) to -0.05 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.01 - +.08 dB

StopBand .5465 - - Fs

StopBand Attenuation (Note 7) 50 - - dB

Group Delay tgd - 10/Fs - s

De-emphasis Error (Note 8) Fs = 44.1 kHz - - +.05/-.25 dB

Combined Digital and On-chip Analog Filter Response Double Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.05 - +.2 dB

StopBand .5770 - - Fs

StopBand Attenuation (Note 7) 55 - - dB

Group Delay tgd - 5/Fs - s

Combined Digital and On-chip Analog Filter Response Quad Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB

StopBand 0.7 - - Fs

StopBand Attenuation (Note 7) 51 - - dB

Group Delay tgd - 2.5/Fs - s

0 0

.4780 .4996

.4650 .4982

0.397

0.476

Fs Fs

Notes: 6. Filter response is guaranteed by design.

7. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

8. De-emphasis is available only in Single Speed Mode.

9. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

CS4245

125

3.3µF

AOUTx

AGND

Figure 1. DAC Output Test Load

100

out

Safe Operating

Region

Capacitive Load -- C (pF)

2.5

51015

Resistive Load -- R (kΩ)

Figure 2. Maximum DAC Loading

CS4245

ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): Input test sig-

nal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Fs = 48/96/192 kHz. Synchronous mode.

Line Level Inputs

Parameter Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range

PGA Setting: -12 dB to +6 dB

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

PGA Setting: +12 dB Gain

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to +6 dB

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

THD+N

99 96

93 90

105 102

99 96 93

-95

-82

-42

-92

-89

dB dB dB

dB dB dB dB

PGA Setting: +12 dB Gain

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

Dynamic Performance for VA = 3.3 V

Dynamic Range

PGA Setting: -12 dB to +6 dB

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

PGA Setting: +12 dB Gain

A-weighted

unweighted

(Note 12) 40 kHz bandwidth unweighted

94 91

90 87

-92

-76

-36

-89

102

99 96

96 93 90

-86

dB dB dB dB

dB dB dB

CS4245

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to +6 dB

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

PGA Setting: +12 dB Gain

-1 dB

-20 dB

-60 dB

(Note 12) 40 kHz bandwidth -1 dB

Parameter Symbol Min Typ Max Unit

Interchannel Isolation - 90 - dB

Line Level Input Characteristics

Full-scale Input Voltage 0.53*VA 0.56*VA Input Impedance (Note 10) 6.12 6.8 7.48 kΩ

Maximum Interchannel Input Impedance Mismatch

Line Level and Microphone Level Inputs

Parameter Symbol Min Typ Max Unit

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB Gain Error -

Gain Drift -

Programmable Gain Characteristics

Gain Step Size - 0.5

Absolute Gain Step Error - -

THD+N

Line Level Inputs

-5-%

-92

-79

-39

-84

-89

-73

-33

-81

-86

-83

0.59*VA

±5

dB dB dB dB

±100 - ppm/°C

0.4

10. Valid for the selected input pair.

ADC ANALOG CHARACTERISTICS (cont)

Microphone Level Inputs

Parameter Symbol Min Typ Max Unit

Dynamic Performance for VA = 5 V

Dynamic Range

PGA Setting: -12 dB to 0 dB

A-weighted

unweighted

PGA Setting: +12 dB

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to 0 dB

-1 dB

-20 dB

-60 dB

THD+N

77 74

65 62

CS4245

83 80

71 68

-80

-60

-20

-74

dB dB

dB dB dB

PGA Setting: +12 dB

-1 dB

Dynamic Performance for VA = 3.3 V

Dynamic Range

PGA Setting: -12 dB to 0 dB

A-weighted

unweighted

PGA Setting: +12 dB

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 11)

PGA Setting: -12 dB to 0 dB

-1 dB

-20 dB

-60 dB

PGA Setting: +12 dB

-1 dB

Interchannel Isolation - 30 - dB

Microphone Level Input Characteristics

Full-scale Input Voltage 0.013*VA 0.014*VA 0.015*VA V Input Impedance (Note 13) - 100 - kΩ

THD+N

77 74

65 62

-68

83 80

71 68

-80

-60

-20

-68

-74

dB dB

dB dB dB

11. Referred to the typical line level full-scale input voltage

12. Valid for Double and Quad Speed Modes only.

13. Valid when the microphone level inputs are selected.

CS4245

ADC DIGITAL FILTER CHARACTERISTICS

Parameter (Note 14, 16) Symbol Min Typ Max Unit

Single Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs

Passband Ripple - - 0.035 dB

Stopband 0.5688 - - Fs

Stopband Attenuation 70 - - dB

Total Group Delay (Fs = Output Sample Rate) t

Double Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs

Passband Ripple - - 0.025 dB

Stopband 0.5604 - - Fs

Stopband Attenuation 69 - - dB

Total Group Delay (Fs = Output Sample Rate) t

Quad Speed Mode

Passband (-0.1 dB) 0 - 0.2604 Fs

Passband Ripple - - 0.025 dB

Stopband 0.5000 - - Fs

Stopband Attenuation 60 - - dB

Total Group Delay (Fs = Output Sample Rate) t

High Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 15)

Phase Deviation @ 20Hz (Note 15) - 10 - Deg

Passband Ripple - - 0 dB

Filter Settling Time 10

- 12/Fs - s

-9/Fs - s

-5/Fs - s

-120-

/Fs s

Hz Hz

Note: 14. Filter response is guaranteed by design.

15. Response shown is for Fs equal to 48 kHz.

16. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

CS4245

AUXILIARY OUTPUT ANALOG CHARACTERISTICS Test conditions (unless otherwise

specified): Synchronous mode, Fs = 48/96/192 kHz. Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.

VA = 5 V

Parameter Symbol Min Typ Max Unit

Dynamic Performance with PGA Output Selected, Line Level Input

Dynamic Range (Note 18)

PGA Setting: -12 dB to +6 dB

A-weighted

unweighted

PGA Setting: +12 dB Gain

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 18)

PGA Setting: -12 dB to +12 dB

-1 dB

-20 dB

-60 dB

Dynamic Performance with PGA Output Selected, Mic Level Input

Dynamic Range (Note 18)

PGA Setting: -12 dB to 0 dB

A-weighted

unweighted

THD+N

99 96

93 90

77 74

105 102

99 96

-80

-82

-42

83 80

-74

dB dB

dB dB dB

dB dB

PGA Setting: +12 dB

A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 18)

PGA Setting: -12 dB to 0 dB

-1 dB

-20 dB

-60 dB

PGA Setting: +12 dB

-1 dB

Dynamic Performance with DAC Output Selected

Dynamic Range (Notes 17, 18)

18 to 24-Bit A-Weighted

unweighted

16-Bit A-Weighted

unweighted

Total Harmonic Distortion + Noise (Notes 17, 18)

16 to 24-Bit 0 dB

-20 dB

-60 dB

THD+N

65 62

99 96 90 87

71 68

-74

-60

-20

-68

105 102

96 93

-80

-82

-42

-68

-74

dB dB

dB dB dB

dB dB dB dB

dB dB dB

CS4245

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