CIRRUS LOGIC CS42428 Service Manual
CS42428
114 dB, 192 kHz 8-Ch Codec with PLL
Features
Eight 24-bit D/A, two 24-bit A/D converters
114 dB DAC / 114 dB ADC dynamic range
-100 dB THD+N
System sampling rates up to 192 kHz
Integrated low-jitter PLL for increased system
jitter tolerance
PLL clock or OMCK system clock selection
7 configurable general purpose outputs
ADC high pass filter for DC offset calibration
Expandable ADC channels and one-line
mode support
Digital output volume control with soft ramp
Digital +/-15 dB input gain adjust for ADC
Differential analog architecture
Supports logic levels between 5 V and 1.8 V
Mute
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
REFGND
Internal Voltage
Dig ital Filte r
Dig ital Filte r
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
MUTEC
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
VA AGND
GPO
ADC#1
ADC#2
Analog Filter
VQ
Reference
General Description
The CS42428 CODEC provides two analog-to-digital and eight
digital-to-analog Delta-Sigma converters, as well as an integrated PLL, in a 64-pin LQFP package.
The CS42428 integrated PLL provides a low-jitter system
clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs.
All eight channels of DAC provide digital volume control and
differential analog outputs. The general purpose outputs may
be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.
The CS42428 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V
receivers, DVD receivers, digital speaker and automotive audio
systems.
ORDERING INFORMATION
CS42428-CQZ -10° to 70° C 64-pin LQFP
CS42428-DQZ -40° to 85° C 64-pin LQFP
CDB42428 Evaluation Board
FILT+
OMCK RMCK LPFLT
Gain & Clip
Gain & Clip
Digita l Filter
Volume Control
PLL
ADC
Serial
Audio
Port
Mult/Div
DAC Serial Audio Port
VLC
Control
Port
DGND
VD
INT
RST
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
ADCIN1
ADCIN2
ADC_SDOUT
ADC_LRCK
Level Translator
Leve l Transla tor
ADC_SCLK
VLS
DAC_LRCK
DAC_SCLK
DAC_SDIN1
DAC_SDIN 2
DAC_SDIN 3
DAC_SDIN4
Advance Product Information
Cirrus Logic, Inc.
www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
JUL ‘04
DS605A2
1
TABLE OF CONTENTS
1 PIN DESCRIPTIONS ................................................................................................................. 6
2 TYPICAL CONNECTION DIAGRAMS ..................................................................................... 8
3 APPLICATIONS ....................................................................................................................... 10
3.1 Overview .......................................................................................................................... 10
3.2 Analog Inputs ................................................................................................................... 10
3.2.1 Line Level Inputs ................................................................................................. 10
3.2.2 External Input Filter ............................................................................................. 11
3.2.3 High Pass Filter and DC Offset Calibration ......................................................... 11
3.3 Analog Outputs ................................................................................................................ 11
3.3.1 Line Level Outputs and Filtering .........................................................................11
3.3.2 Interpolation Filter ............................................................................................... 12
3.3.3 Digital Volume and Mute Control ........................................................................ 12
3.3.4 ATAPI Specification ............................................................................................13
3.4 Clock Generation ............................................................................................................. 14
3.4.1 PLL and Jitter Attenuation ................................................................................... 14
3.4.2 OMCK System Clock Mode ................................................................................ 15
3.4.3 Master Mode ....................................................................................................... 15
3.4.4 Slave Mode ......................................................................................................... 15
3.5 Digital Interfaces ..............................................................................................................16
3.5.1 Serial Audio Interface Signals .............................................................................16
3.5.2 Serial Audio Interface Formats ............................................................................18
3.5.3 ADCIN1/ADCIN2 Serial Data Format ..................................................................21
3.5.4 One Line Mode(OLM) Configurations ................................................................. 22
3.6 Control Port Description and Timing ................................................................................ 26
CS42428
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com/
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Log ic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All produ cts are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No
responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items,
or for infringement of patents or other righ ts of third parties. This document is the pro perty of Cirrus and by furnishing this information, Cirrus grants
no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus
owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within
your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described
in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or
quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material
is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE
BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS,
STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES
OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY
CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING
ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phil lips I2C Patent Rights to use
those components in a standard I
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.
2
C system.
2
CS42428
3.6.1 SPI Mode ............................................................................................................ 26
3.6.2 I2C Mode ............................................................................................................ 27
3.7 Interrupts ......................................................................................................................... 28
3.8 Reset and Power-up ....................................................................................................... 29
3.9 Power Supply, Grounding, and PCB layout ..................................................................... 29
4 REGISTER QUICK REFERENCE ........................................................................................... 30
5 REGISTER DESCRIPTION ..................................................................................................... 32
5.1 Memory Address Pointer (MAP)....................................................................................... 32
5.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 32
5.3 Power Control (address 02h)............................................................................................ 33
5.4 Functional Mode (address 03h) ........................................................................................ 33
5.5 Interface Formats (address 04h) ...................................................................................... 34
5.6 Misc Control (address 05h) .............................................................................................. 36
5.7 Clock Control (address 06h)............................................................................................. 37
5.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ......................................................... 39
5.9 Clock Status (address 08h) (Read Only).......................................................................... 39
5.10 Volume Control (address 0Dh) ....................................................................................... 40
5.11 Channel Mute (address 0Eh).......................................................................................... 41
5.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ........................ 42
5.13 Channel Invert (address 17h) ......................................................................................... 42
5.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)
Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) ............................................ 42
5.15 ADC Left Channel Gain (address 1Ch) .......................................................................... 45
5.16 ADC Right Channel Gain (address 1Dh)........................................................................ 45
5.17 Interrupt Control (address 1Eh) ...................................................................................... 45
5.18 Interrupt Status (address 20h) (Read Only) ................................................................... 46
5.19 Interrupt Mask (address 21h) ......................................................................................... 47
5.20 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h)................................................................................ 47
5.21 MuteC Pin Control (address 28h) ................................................................................... 47
5.22 General Purpose Pin Control (addresses 29h to 2Fh) ................................................... 48
6 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 50
SPECIFIED OPERATING CONDITIONS............................................................................... 50
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 50
ANALOG INPUT CHARACTERISTICS.................................................................................. 51
A/D DIGITAL FILTER CHARACTERISTICS .......................................................................... 52
ANALOG OUTPUT CHARACTERISTICS.............................................................................. 55
D/A DIGITAL FILTER CHARACTERISTICS .......................................................................... 56
SWITCHING CHARACTERISTICS ........................................................................................ 61
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT ............................... 62
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 63
DC ELECTRICAL CHARACTERISTICS ................................................................................ 64
DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 64
7 PARAMETER DEFINITIONS ................................................................................................... 65
8 REFERENCES ......................................................................................................................... 66
9 PACKAGE DIMENSIONS .................................................................................................... 67
THERMAL CHARACTERISTICS ........................................................................................... 67
3
LIST OF FIGURES
Figure 1. Typical Connection Diagram............................................................................................8
Figure 2. Typical Connection Diagram using the PLL .....................................................................9
Figure 3. Full-Scale Analog Input .................................................................................................. 10
Figure 4. Full-Scale Output ........................................................................................................... 12
Figure 5. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4)......................................................... 13
Figure 6. Clock Generation ........................................................................................................... 14
Figure 7. Right Justified Serial Audio Formats ..............................................................................18
Figure 8. I
Figure 9. Left Justified Serial Audio Formats ................................................................................ 19
Figure 10. One Line Mode #1 Serial Audio Format....................................................................... 20
Figure 11. One Line Mode #2 Serial Audio Format....................................................................... 20
Figure 12. ADCIN1/ADCIN2 Serial Audio Format.........................................................................21
Figure 13. OLM Configuration #1.................................................................................................. 22
Figure 14. OLM Configuration #2.................................................................................................. 23
Figure 15. OLM Configuration #3.................................................................................................. 24
Figure 16. OLM Configuration #4.................................................................................................. 25
Figure 17. Control Port Timing in SPI Mode.................................................................................. 26
Figure 18. Control Port Timing, I2C Slave Mode Write ................................................................. 27
Figure 19. Control Port Timing, I2C Slave Mode Read ................................................................. 27
Figure 20. Single Speed Mode Stopband Rejection ..................................................................... 53
Figure 21. Single Speed Mode Transition Band............................................................................ 53
Figure 22. Single Speed Mode Transition Band (Detail) ............................................................... 53
Figure 23. Single Speed Mode Passband Ripple.......................................................................... 53
Figure 24. Double Speed Mode Stopband Rejection .................................................................... 53
Figure 25. Double Speed Mode Transition Band .......................................................................... 53
Figure 26. Double Speed Mode Transition Band (Detail).............................................................. 54
Figure 27. Double Speed Mode Passband Ripple ........................................................................ 54
Figure 28. Quad Speed Mode Stopband Rejection....................................................................... 54
Figure 29. Quad Speed Mode Transition Band............................................................................. 54
Figure 30. Quad Speed Mode Transition Band (Detail) ................................................................ 54
Figure 31. Quad Speed Mode Passband Ripple........................................................................... 54
Figure 32. Single Speed (fast) Stopband Rejection ...................................................................... 57
Figure 33. Single Speed (fast) Transition Band ............................................................................ 57
Figure 34. Single Speed (fast) Transition Band (detail) ................................................................ 57
Figure 35. Single Speed (fast) Passband Ripple .......................................................................... 57
Figure 36. Single Speed (slow) Stopband Rejection..................................................................... 57
Figure 37. Single Speed (slow) Transition Band ........................................................................... 57
Figure 38. Single Speed (slow) Transition Band (detail) ............................................................... 58
Figure 39. Single Speed (slow) Passband Ripple......................................................................... 58
Figure 40. Double Speed (fast) Stopband Rejection..................................................................... 58
Figure 41. Double Speed (fast) Transition Band ........................................................................... 58
Figure 42. Double Speed (fast) Transition Band (detail) ............................................................... 58
Figure 43. Double Speed (fast) Passband Ripple......................................................................... 58
Figure 44. Double Speed (slow) Stopband Rejection ................................................................... 59
Figure 45. Double Speed (slow) Transition Band.......................................................................... 59
Figure 46. Double Speed (slow) Transition Band (detail).............................................................. 59
Figure 47. Double Speed (slow) Passband Ripple........................................................................ 59
Figure 48. Quad Speed (fast) Stopband Rejection ....................................................................... 59
Figure 49. Quad Speed (fast) Transition Band.............................................................................. 59
Figure 50. Quad Speed (fast) Transition Band (detail).................................................................. 60
Figure 51. Quad Speed (fast) Passband Ripple............................................................................ 60
2
S Serial Audio Formats................................................................................................ 19
CS42428
4
Figure 52. Quad Speed (slow) Stopband Rejection...................................................................... 60
Figure 53. Quad Speed (slow) Transition Band ............................................................................ 60
Figure 54. Quad Speed (slow) Transition Band (detail) ................................................................ 60
Figure 55. Quad Speed (slow) Passband Ripple.......................................................................... 60
Figure 56. Serial Audio Port Master Mode Timing ........................................................................ 61
Figure 57. Serial Audio Port Slave Mode Timing .......................................................................... 61
Figure 58. Control Port Timing - I2C Format................................................................................. 62
Figure 59. Control Port Timing - SPI Format................................................................................. 63
LIST OF TABLES
Table 1. PLL External Component Values .................................................................................... 15
Table 2. Common OMCK Clock Frequencies .............................................................................. 15
Table 3. Common PLL Output Clock Frequencies....................................................................... 16
Table 4. Slave Mode Clock Ratios ...............................................................................................16
Table 5. Serial Audio Port Channel Allocations ............................................................................ 17
Table 6. DAC De-Emphasis .......................................................................................................... 34
Table 7. Digital Interface Formats ................................................................................................. 35
Table 8. ADC One_Line Mode ......................................................................................................35
Table 9. DAC One_Line Mode ......................................................................................................35
Table 10. RMCK Divider Settings .................................................................................................37
Table 11. OMCK Frequency Settings ........................................................................................... 38
Table 12. Master Clock Source Select.......................................................................................... 38
Table 13. PLL Clock Frequency Detection.................................................................................... 39
Table 14. Example Digital Volume Settings.................................................................................. 42
Table 15. ATAPI Decode .............................................................................................................. 44
Table 16. Example ADC Input Gain Settings ................................................................................ 45
CS42428
5
1 PIN DESCRIPTIONS
CS42428
VD
DGND
VLC
AD0/CS
INT
RST
AINR-
AINR+
AINL+
AINL-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DAC_SDIN1
DAC_SCLK
DAC_LRCK
SCL/CC LK
SDA/CDOUT
AD1/CDIN
Pin Name # Pin Description
DAC Serial Audio Data Input (
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
DAC_SCLK 2 DAC Serial Clock
DAC_LRCK 3 DAC Left Right Clock (
VD 451Digital Power (
1
64
63
62
the DAC serial audio data line.
Input
(Input/Output)
) - Positive power supply for the digital section.
DAC_SDIN2
64 63 6 2 6 1 60 59 58 57 56 5 5 54 53 52 51 50 49
ADCIN2
ADCIN1
OMCK
ADC_SDOUT
ADC_SCLK
ADC_LRCK
DAC_SDIN4
DAC_SDIN3
VLS
RMCK
NC
DGND
NC
VD
CS42428
17 18 19 20 21 22 23 24 25 2 6 27 28 29 30 31 32
VQ
FILT+
REFGND
AOUTB4-
Input
- Serial clock for the DAC serial audio interface.
Input/Output
AOUTB4+
VA
AGND
AOUTA4-
AOUTA4+
AOUTB3-
AOUTA3-
AOUTB3+
AOUTB2-
AOUTA3+
AOUTB2+
) - Input for two’s complement serial audio data.
) - Determines which channel, Left or Right, is currently active on
NC
AOUTA2+
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
VA
AGND
LPFLT
MUTEC
AOUTA1-
AOUTA1+
AOUTB1+
AOUTB1-
AOUTA2-
Input
DGND 552Digital Ground (
VLC 6
Control Port Power (
) - Ground reference. Should be connected to digital ground.
Input
SCL/CCLK 7 Serial Control Port Clock (
resistor to the logic interface voltage in I
SDA/CDOUT 8 Serial Control Data (
Input/Output
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
AD1/CDIN 9 Address Bit 1 (I
2
C)/Serial Control Data (SPI) (
the input data line for the control port interface in SPI mode.
AD0/CS
10
Address Bit 0 (I
2
C)/Control Port Chip Select (SPI)
is the chip select signal in SPI mode.
INT 11 Interrupt
(Output
) - The CS42428 will generate an interrupt condition as per the Interrupt Mask register.
See “Interrupts” on page 28 for more details.
6
) - Determines the required signal level for the control port.
Input
) - Serial clock for the serial control port. Requires an external pull-up
2
C mode as shown in the Typical Connection Diagram.
) - SDA is a data I/O line in I2C mode and requires an external pull-up
Input
) - AD1 is a chip address pin in I2C mode; CDIN is
(Input
) - AD0 is a chip address pin in I2C mode; CS
CS42428
RST 12 Reset (
AINRAINR+
AINL+
AINL-
VQ 17 Quiescent Voltage (
FILT+ 18 Positive Voltage Reference (
REFGND 19 Reference Ground (
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,-
VA 2441Analog Power (
AGND 2540Analog Ground (
MUTEC 38 Mute Control (
LPFLT 39 PLL Loop Filter (
GPO7
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1
VLS 53 Serial Port Interface Power (
RMCK 55 Recovered Master Clock (
ADC_SDOUT
ADCIN1
ADCIN2
OMCK 59 External Reference Clock (
ADC_LRCK 60 ADC Left/Right Clock (
ADC_SCLK 61 ADC Serial Clock
1314Differential Right Channel Analog Input (
1516Differential Left Channel Analog Input (
36,37
35,34
32,33
31,30
28,29
27,26
22,23
21,20
42
43
44
45
46
47
48
56 ADC Serial Data Output (
5857External ADC Serial Input (
Input
) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
modulators via the AINR+/- pins.
modulators via the AINL+/- pins.
Output
) - Filter connection for internal quiescent reference voltage.
Input
) - Ground reference for the internal sampling circuits.
Differential Analog Output (
Analog Characteristics specification table.
Input
) - Positive power supply for the analog section.
Input
) - Ground reference. Should be connected to analog ground.
Output
) - The Mute Control pin outputs high impedance following an initial power-on condition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
Output
) - An RC network should be connected between this pin and ground.
General Purpose Output (
ADC overflow interrupt or Mute Control outputs according to the General Purpose Pin Control registers.
Output
Output
(OMCK, pin 59) or the PLL which is locked to the incoming ADC_LRCK.
Output
of the internal and external ADCs.
converter inputs to provide a maximum of six channels on one serial data output line when the CS42428
is placed in One Line mode.
the register “OMCK Frequency (OMCK Freqx)” on page 38.
Input/Output
the ADC serial audio data line.
(Input/Output)
Input
) - Signals are presented differentially to the delta-sigma
Input
) - Signals are presented differentially to the delta-sigma
Output
) - Positive reference voltage for the internal sampling circuits.
Output
) - The full-scale differential analog output level is specified in the
) - These pins can be configured as general purpose output pins, an
Input
) - Determines the required signal level for the serial port interfaces.
) - Recovered master clock output from the External Clock Reference
) - Output for two’s complement serial audio PCM data from the output
Input
) - The CS42428 provides for up to two external stereo analog to digital
Input
) - External clock reference that must be within the ranges specified in
) - Determines which channel, Left or Right, is currently active on
- Serial clock for the ADC serial audio interface.
7
2 TYPICAL CONNECTION DIAGRAMS
CS42428
+3.3 V to +5 V
+2.5 V
to +5 V
+1.8 V
to +5 V
Note: Resistors are required for
2
I
C control port operation
+
10 µ F
+
10 µ F
CS5361
A/D Converter
CS5361
A/D Converter
Digital Audio
Processor
Micro-
Controller
See
Note
0.1 µ F 0.01 µF
0.1 µ F
0.01 µF
0.1 µ F
OSC
2 kΩ
2 k Ω
0.1 µF
48
47
46
45
44
43
42
53
59
58
57
55
56
60
61
3
2
1
64
63
62
11
12
7
8
9
10
6
VD
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
VLS
OMCK
ADCIN1
ADCIN2
RMCK
51
CS42428
ADC_SDOUT
ADC_LRCK
ADC_SCLK
DAC_LRCK
DAC_ SCLK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
INT
RST
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
VLC
DGND
DGND
5
52 40
25
414
VAVD
24
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
MUTEC
AINL+
AINL-
AINR+
AINR-
FILT+
REFGND
LPFLT
AGNDAGND
VQ
VA
0.01 µF
0.01 µF
36
37
35
34
32
33
31
30
28
29
27
26
22
23
21
20
+VA
38
15
16
14
13
17
18
19
39
***
***
0.1 µF
RFILT**
CFILT**
0.1 µF
+
10 µF
0.1 µF
+
10 µF
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Mute
Drive
*** Pull up or down as required on startup
Analog
2700 pF*
Input
Buffer *
Analog
2700 pF*
Input
Buffer *
* See CDB42428 for a recommended filter.
+
0.1 µF
100 µF
** Refer to Table 1
for proper values
CRIP**
+5 V
Left Analog Input
Right Analog Input
+
4.7 µF
Connect DGND and AGND at single point near Codec
Figure 1. Typical Connection Diagram
8
CS42428
+1.8 V
to +5.0 V
+3.3 V to +5 V
27 MHz
0.1 µF 0.01 µF
+
10 µ F
+
0.1 µF
10 µ F
DVD
Processor
Ω
See
2 k
Note
Note: Resistors are required for
2
I
C control port operation
0.01 µF
0.1 µF
Ω
2 k
0.1 µF
VD
48
GPO1
47
GPO2
46
GPO3
45
GPO4
44
GPO5
43
GPO6
42
GPO7
53
VLS
59
OMCK
58
ADCIN1
57
ADCIN2
CS42428
55
RMCK
56
ADC_SDOUT
60
ADC_L RCK
61
ADC_S CLK
3
DAC_L RCK
2
DAC_S CLK
1
DAC_S DIN1
64
DAC_S DIN2
63
DAC_S DIN3
62
DAC_S DIN4
11
INT
12
RST
7
SCL/ CCLK
8
SDA/ CDOUT
9
AD1/CDIN
10
AD0/CS
6
VLC
DGND
DGND
5
52 40
0.1 µF
+5 V
Left Analog I nput
Right Analog Input
+
4.7 µF
0.1 µF
0.01 µF
0.01 µF
51
25
414
VAVD
24
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
MUTEC
AINL+
AINL -
AINR+
AI NR-
FILT+
REFGND
LPFL T
AGNDAGND
VA
36
37
35
34
32
33
31
30
28
29
27
26
22
23
21
20
+VA
***
38
***
15
16
14
13
17
VQ
18
0.1 µF
19
39
CFI LT**
+
10 µF
0.1 µF
+
10 µF
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Mute
Dri ve
*** Pull up or down as required on start up
Analog
2700 pF*
Input
Buffer *
Analog
2700 pF*
Input
Buffer *
* See CDB42428 for a recommended filter.
+
100 µF
RFI LT**
** Refer to Table 1
for proper val ues
CRIP**
Connect DGND and AGND at single point near Codec
Figure 2. Typical Connection Diagram using the PLL
9
CS42428
3 APPLICATIONS
3.1 Overview
The CS42428 is a highly integrated mixed signal 24-bit audio codec comprised of 2 analog-to-digital converters (ADC), implemented using multi-bit delta-sigma techniques, and 8 digital-to-analog converters
(DAC). Other functions integrated within the codec include independent digital volume controls for each
DAC, digital de-emphasis filters for DAC, digital gain control for ADC channels, ADC high-pass filters,
and an on-chip voltage reference. All serial data is transmitted through one configurable serial audio interface for the ADC with enhanced one line modes of operation allowing up to 6 channels of serial audio data
on one data line. All functions are configured through a serial control port operable in SPI mode or in I2C
mode. Figure 1 shows the recommended connections for the CS42428.
The CS42428 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the FM bits in register “Functional Mode (address 03h)” on page 33. Single-Speed mode
(SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode
(DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed
mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.
Using the integrated PLL, a low jitter clock is recovered from the ADC LRCK input signal. The recovered
clock or an externally supplied clock attached to the OMCK pin can be used as the System Clock.
3.2 Analog Inputs
3.2.1 Line Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line level differential analog inputs. These pins are internally
biased to the DC quiescent reference voltage, VQ, of approximately 2.7 V. The level of the signal can be
adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain Control
Registers on page 45. The ADC output data is in 2’s complement binary format. For inputs above positive
full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause
the ADC Overflow bit in the register “Interrupt Status (address 20h) (Read Only)” on page 46 to be set to
a ‘1’. The GPO pins may also be configured to indicate an overflow condition has occurred in the ADC.
See “General Purpose Pin Control (addresses 29h to 2Fh)” on page 48 for proper configuration. Figure 3
shows the full-scale analog input levels.
4.1 V
2.7 V
1.3 V
4.1 V
2.7 V
1.3 V
AIN+
AIN-
10
Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp
Figure 3. Full-Scale Analog Input
CS42428
3.2.2 External Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter
will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are (n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the CDB42418 for a recommended analog input buffer that will attenuate any noise energy at 6.144 MHz, in addition to providing
the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.
3.2.3 High Pass Filter and DC Offset Calibration
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. The high pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during
normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC
offset will continue to be subtracted from the conversion result. This feature makes it possible to perform
a system DC offset calibration by:
1) Running the CS42428 with the high pass filter enabled until the filter settles. See the Digital Filter
Characteristics for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
The high pass filters are controlled using the HPF_FREEZE bit in the register “Misc Control (address
05h)” on page 36.
3.3 Analog Outputs
3.3.1 Line Level Outputs and Filtering
The CS42428 contains on-chip buffer amplifiers capable of producing line level differential outputs. These
amplifiers are biased to a quiescent DC level of approximately VQ.
The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low pass filter. The recommended output filter configuration is shown in the CDB42418. This
filter configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential
output pins. It also shows an AC coupling configuration which minimizes the number of required AC coupling capacitors.
11
CS42428
The CS42428 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. Figure 4 shows the full-scale analog output levels.
3.95 V
AOUT+
AOUT-
Full-Scale Output Level= (AIN+) - (AIN-)= 5 Vpp
Figure 4. Full-Scale Output
2.7 V
1.45 V
3.95 V
2.7 V
1.45 V
3.3.2 Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS42428 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate
a variety of musical tastes and styles. The FILT_SEL bit found in the register “Misc Control (address 05h)”
on page 36 is used to select which filter is used. Filter response plots can be found in Figures 32 to 55.
3.3.3 Digital Volume and Mute Control
Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to
-127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h,
15h, 16h)” on page 42. Volume control changes are programmable to ramp in increments of 0.125 dB at
the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See “Volume Control (address 0Dh)” on page 40.
Each output can be independently muted via mute control bits in the register “Channel Mute (address
0Eh)” on page 41. When enabled, each XX_MUTE bit attenuates the corresponding DAC to its maximum
value (-127 dB). When the XX_MUTE bit is disabled, the corresponding DAC returns to the attenuation
level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by
the SZC[1:0] bits.
The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The Mute Control pin is tri-stated during power up or in power down mode by setting the PDN bit in the register “Power
Control (address 02h)” on page 33 to a ‘1’. Once out of power-down mode the pin can be controlled by the
user via the control port, or automatically asserted high when zero data is present on all DAC inputs, or
when serial port clock errors are present. To prevent large transients on the output, it is desirable to mute
the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descriptions section for more information.
12
CS42428
Each of the GPO1-GPO7 can be programmed to provide a hardware MUTE signal to individual circuits.
Each pin can be programmed as an output, with specific muting capabilities as defined by the function bits
in the register “General Purpose Pin Control (addresses 29h to 2Fh)” on page 48.
3.3.4 ATAPI Specification
The CS42428 implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 15 on page 44 and Figure 5 for additional information.
DAC_SDINx
Left Channel
Audio Data
Right Channel
Audio Data
Figure 5. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4)
A Channel
Volume
Control
MUTE
AOUTAx
ΣΣ
B Channel
Volume
Control
MUTE
AOUTBx
13
CS42428
3.4 Clock Generation
The clock generation for the CS42428 is shown in the figure below. The internal MCLK is derived from
the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of
PLL lock to the other source input.
OMCK
ADC_LRCK
(slave mode)
PLL_LRCK
PLL (256Fs)
49.152 MHz
bit
8.192 -
Internal
MCLK
00
01
SW_CTRLx
(manual or auto
2
4
X2
Auto D etect
Input Clock
1,1.5, 2, 4
switch)
bits
00
01
10
11
RMCK_DIVx
single
speed
256
double
speed
128
quad
speed
64
single
speed
4
double
speed
2
quad
speed
1
bits
00
01
10
DAC_FMx
00
01
10
00
01
10
ADC_FMx
00
01
10
bits
or
not O LM
128FS
OLM #1
256FS
OLM #2
bits
ADC_OLx
ADC_SP SELx
not O LM
128FS
OLM #1
256FS
OLM #2
DAC_OLx
ADC_OLx
RMCK
DAC_LRCK
bits
DAC_SCLK
ADC_LRCK
and
bits
ADC_SCLK
Figure 6. Clock Generation
3.4.1 PLL and Jitter Attenuation
The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and
generate the required internal master clock frequency. There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to
have good jitter attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register “Clock
Control (address 06h)” on page 37, the PLL will lock to the incoming ADC_LRCK and generate an output
master clock (RMCK) of 256Fs. Table 3 below shows the output of the PLL with typical input Fs values
for ADC_LRCK.
The PLL behavior is affected by the external filter component values. Figure 1 shows the required configuration of the external filter components. The set of component values required for 32 kHz to 192 kHz
14
CS42428
sample rate applications are shown in Table 1. The lock time is the worst case for an Fs transition from unlocked state to locking to 192 kHz.
Fs Range (kHz) RFILT (kΩ) CFILT (pF) CRIP (pF) Settling time
32 to 192 10 2700 680 11 ms
Table 1. PLL External Component Values
It is important to treat the LPFLT pin as a low level analog input. It is suggested that the ground end of the
PLL filter be returned directly to the AGND pin independently of the digital ground plane.
3.4.2 OMCK System Clock Mode
A special clock switching mode is available that allows the clock that is input through the OMCK pin to
be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock
Control (address 06h)” on page 37. An advanced auto switching mode is also implemented to maintain
master clock functionality. The clock auto switching mode allows the clock input through OMCK to be
used as a clock in the system without any disruption when the PLL loses lock, for example, when the
LRCK is removed from ADC_LRCK. This clock switching is done glitch free.
3.4.3 Master Mode
In master mode, the serial interface timings are derived from an external clock attached to OMCK or the
output of the PLL with an input reference to the ADC_LRCK input from the ADC serial port. The DAC
Serial Port and ADC Serial Port can both be masters only when OMCK is used as the clock source. When
using the PLL output, the ADC Serial Port must be slave and the DAC Serial Port can operate in Master
Mode. Master clock selection and operation is configured with the SW_CTRL1:0 and CLK_SEL bits in
the Clock Control Register (See “Clock Control (address 06h)” on page 37).
The sample rate to OMCK ratios and OMCK frequency requirements for Master mode operation are
shown in Table 2.
Sample
Rate
(kHz)
48 12.2880 18.4320 24.5760 -----96 - - - 12.2880 18.4320 24.5760 - - -
192 - - - - - - 12.2880 18.4320 24.5760
Single Speed
(4 to 50 kHz)
256x 384x 512x 128x 192x 256x 64x 96x 128x
Table 2. Common OMCK Clock Frequencies
OMCK (MHz)
Double Speed
(50 to 100 kHz)
Quad Speed
(100 to 192 kHz)
3.4.4 Slave Mode
In Slave mode, DAC_LRCK, DAC_SCLK and/or ADC_LRCK and ADC_SCLK operate as inputs. The
Left/Right clock signal must be equal to the sample rate, Fs and must be synchronously derived from the
supplied master clock, OMCK or must be synchronous to the supplied ADC_LRCK used as the input to
15
CS42428
the PLL. In this latter scenario the PLL output becomes the internal master clock. The supported PLL output frequencies are shown in Table 3 below.
Sample
Rate
(kHz)
32 8.1920 - -
44.1 11.2896 - 48 12.2880 - 64 - 16.3840 -
88.2 - 22.5792 96 - 24.5760 -
176.4 - - 45.1584
192 - - 49.1520
Single Speed
(4 to 50 kHz)
256x 256x 256x
Table 3. Common PLL Output Clock Frequencies
The serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronous to the corresponding
DAC_LRCK/ADC_LRCK and be equal to 128x, 64x, 48x or 32x Fs depending on the interface format
selected and desired speed mode. One Line Mode #1 is supported in Slave Mode. One Line Mode #2 is
not supported. Refer to Table 4 for required clock ratios.
Single Speed Double Speed Quad Speed One Line Mode #1
OMCK/LRCK Ratio 256x, 512x 128x, 256x 128x 256x
SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 64x 32x, 64x 128x
PLL Output (MHz)
Double Speed
(50 to 100 kHz)
Quad Speed
(100 to 192 kHz)
Table 4. Slave Mode Clock Ratios
3.5 Digital Interfaces
3.5.1 Serial Audio Interface Signals
The CS42428 interfaces to an external Digital Audio Processor via two independent serial ports, the
DAC serial port, DAC_SP and the ADC serial port, ADC_SP. The digital output of the internal ADCs use
the ADC_SDOUT pin and can be configured to use either the ADC or DAC serial port timings. These configuration bits and the selection of Single, Double or Quad Speed mode for DAC_SP and ADC_SP are
found in register “Functional Mode (address 03h)” on page 33.
The serial interface clocks, ADC_SCLK for ADC_SP and DAC_SCLK for DAC_SP, are used for transmitting and receiving audio data. Either ADC_SCLK or DAC_SCLK can be generated by the CS42428
(master mode) or it can be input from an external source (slave mode). Master or Slave mode selection is
made using bits DAC_SP M/S and ADC_SP M/S in register “Misc Control (address 05h)” on page 36.
The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the
start of a new sample period. It may be an output of the CS42428 (master mode), or it may be generated
by an external source (slave mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other.
The serial data interface format selection (left/right justified, I2S or one line mode) for the ADC serial port
data out pin, ADC_SDOUT, and the DAC input pins, DAC_SDIN1:4, is configured using the appropriate
16
CS42428
bits in the register “Interface Formats (address 04h)” on page 34. The serial audio data is presented in 2's
complement binary form with the MSB first in all formats.
DAC_SDIN1, DAC_SDIN2, DAC_SDIN3 and DAC_SDIN4 are the serial data input pins supplying the
internal DAC. ADC_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs
and, when configured for one-line mode, up to four additional ADC channels attached externally to the
signals ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One Line Data
Mode, 6 channels of DAC data are input on DAC_SDIN1, two additional DAC channels on DAC_SDIN4,
and 6 channels of ADC data are output on ADC_SDOUT. Table 5 outlines the serial port channel allocations.
Serial Inputs / Outputs
DAC_SDIN1 left channel
right channel
one line mode
DAC_SDIN2 left channel
right channel
one line mode
DAC_SDIN3 left channel
right channel
one line mode
DAC_SDIN4 left channel
right channel
one line mode
ADC_SDOUT left channel
right channel
one line mode
ADCIN1 left channel
right channel
ADCIN2 left channel
right channel
DAC #1
DAC #2
DAC channels 1,2,3,4,5,6
DAC #3
DAC #4
not used
DAC #5
DAC #6
not used
DAC #7
DAC #8
DAC channels 7,8
ADC #1
ADC #2
ADC channels 1,2,3,4,5,6
External ADC #3
External ADC #4
External ADC #5
External ADC #6
Table 5. Serial Audio Port Channel Allocations
17
CS42428
3.5.2 Serial Audio Interface Formats
The DAC_SP and ADC_SP digital audio serial ports support 5 formats with varying bit depths from 16 to
24 as shown in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11. These formats are selected using the
configuration bits in the registers, “Functional Mode (address 03h)” on page 33 and “Interface Formats
(address 04h)” on page 34. For the diagrams below, single-speed mode is equivalent to Fs = 32, 44.1,
48kHz; double-speed mode is for Fs = 64, 88.2, 96 kHz; and quad-speed mode is for Fs = 176.4, 196 kHz.
DAC_LRC K
ADC_LRCK
DAC_SCLK
ADC_SCLK
DAC_SDINx
ADC_SDOUT
Left Channel
15 14 13 12 11 10
Right Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
16 64 Fs 48, 64, 128 Fs single-speed mode
64 Fs 64 Fs double-speed mode
64 Fs 64 Fs quad-speed mode
24 64, 128, 256 Fs 64, 128 Fs single-speed mode
64 Fs 64 Fs double-speed mode
64 Fs 64 Fs quad-speed mode
Figure 7. Right Justified Serial Audio Formats
Right Channel
6543210987
15 14 13 12 11 10
6543210987
18
CS42428
DAC_LRCK
ADC_LR CK
DAC_SCLK
ADC_SCLK
DAC_SDINx
ADC_SDOUT
MSB MSBLSB LSB
-1 -2 -3 -4 -5
Left Channel
+3 +2 +1+5 +4
-1 -2 -3 -4
I2S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
16 64 Fs 48, 64, 128 Fs single-speed mode
64 Fs 64 Fs double-speed mode
64 Fs 64 Fs quad-speed mode
18 to 24 64, 128, 256 Fs 48, 64, 128 Fs single-speed mode
64 Fs 64 Fs double-speed mode
64 Fs 64 Fs quad-speed mode
Figure 8. I2S Serial Audio Formats
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
Left Channel
Right Channel
+3 +2 +1+5 +4
Right Channel
DAC_SDINx
ADC_SDOUT
MSB LSB MSB LSB
-1 -2 -3 -4 -5
+3 +2 +1+5 +4
-1 -2 -3 -4
Left Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
16 64 Fs 32, 48, 64, 128 Fs single-speed mode
64 Fs 32, 64 Fs double-speed mode
64 Fs 32, 64 Fs quad-speed mode
18 to 24 64, 128, 256 Fs 48, 64, 128 Fs single-speed mode
64 Fs 64 Fs double-speed mode
64 Fs 64 Fs quad-speed mode
Figure 9. Left Justified Serial Audio Formats
+3 +2 +1+5 +4
19
CS42428
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
DAC_SDIN1
DAC_SDIN4
ADC_SDOUT
LSBMSB
DAC1 DAC3 DAC5 DAC2 DAC4 DAC6
20 clks
DAC7 DAC8
20 clks
ADC1 ADC3 ADC5 ADC2 ADC4 ADC6
20 clks
64 clks 64 clks
Left Channel Right Channel
LSBMSB LSBMSB LS BMSB LSBMSB LSBMSB MSB
20 clks
20 clks
20 clks 20 clks 20 clks 20 clks
20 clks
20 clks 20 clks 20 clks 20 clks
One Line Data Mode #1, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
20 128 Fs 128 Fs single-speed mode
128 Fs 128Fs double-speed mode
Figure 10. One Line Mode #1 Serial Audio Format
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
DAC_SDIN1
DAC_SDIN4
ADC_SDOUT
LSBMSB
DAC1 DAC3 DAC5 DAC2 DAC4 DAC6
24 clks
DAC7 DAC8
24 clks
ADC1 ADC3 ADC5 ADC2 ADC4 ADC6
24 clks
128 clks
Left Channel Right Channel
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB
24 clks
24 clks
24 clks 24 clks 24 clks 24 clks
24 clks
24 clks 24 clks 24 clks 24 clks
One Line Data Mode #2, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
24 256 Fs not supported single-speed mode
Figure 11. One Line Mode #2 Serial Audio Format
128 clks
20
CS42428
3.5.3 ADCIN1/ADCIN2 Serial Data Format
The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support
only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port
configuration register bit settings. These serial data lines are used when supporting One Line Mode of operation with external ADCs attached. If these signals are not being used, they should be tied together and
wired to GND via a pull-down resistor.
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
ADCIN1/2
MSB LSB MSB LSB
-1 -2 -3 -4 -5
Left Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Left Channel
+3 +2 +1+5 +4
-1 -2 -3 -4
Right Channel
+3 +2 +1+5 +4
24 64, 128 Fs single-speed mode, Fs= 32, 44.1, 48 kHz
64 Fs double-speed mode, Fs= 64, 88.2, 96 kHz
not supported quad-speed mode, Fs= 176.4, 192 kHz
Figure 12. ADCIN1/ADCIN2 Serial Audio Format
For proper operation, the CS42428 must be configured to select which SCLK/LRCK is being used to clock
the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 36, must
be set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the DAC_SP clocks. If the ADCs
are wired to use the ADC_SP clocks, set this bit to ‘0’.
21
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