Cirrus Logic CS4228A User Manual

CS4228A

24-Bit, 96 kHz Surround Sound Codec

Features

! Six 24-bit D/A converters

- 100 dB dynamic range

- -90 dB THD+N

! Two 24-bit A/D converters

- 97 dB dynamic range

- -88 dB THD+N

! Sampleratesupto100kHz ! Pop-free digital output volume controls

- 90.5 dB range, 0.5 dB resolution (182 levels)

- Variable smooth ramp rate, 0.125 dB steps

! Mute control pin for off-chip muting circuits ! On-chip anti-alias and output filters ! De-emphasis filters for 32, 44.1 and 48 kHz

SCL/CCLK SDA/CDIN VD

AD0/CS

Description

The CS4228A codec provides two analog-to-digital and six digital-to-analog Delta-Sigma converters, along with volume controls, in a compact 28-pin SSOP device. Combined with an IEC958 (SPDIF) receiver (like the CS8414) and surround sound decoder (such as one of the CS492x or CS493xx families), it is ideal for use in DVD player, A/V receiver and car audio systems supporting multiple standards such as Dolby Digital AC-3 AAC

,DTS, Dolby ProLogic,THX, and other

multi-channel formats.

A flexible serial audio interface allows operation in Left Justified, Right Justified, I

S, or One Line Data modes.

ORDERING INFORMATION

CS4228A-KS

-10° to +70°C 28-pin SSOP

CDB4228A Evaluation Board

MUTEC

RST

,

LRCK SCLK

SDIN1

SDIN2

SDIN3

SDOUT

www.cirrus.com

CONTROL PORT

SERIAL AUDIO

DATA INTERFACE

CLOCK MANAGER

MCLK

MUTE CONTROL

DIGITAL VOLUME

DIGITAL FILTERS

WITH DE-EMPHASIS

DIGITAL VOLUME

DIGITAL FILTERS

∆Σ

DAC #1

DAC #2

DAC #3

DAC #4

DAC #5

DAC #6

LEFT ADC

RIGHT ADC

DGND

OUTPUT STAGE

ANALOG LOW PASS AND

AGND

FILT

CENTER

SUB

AINL+

AINL-

AINR+ AINR-

MAR ‘03

DS511F1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

SPECIFIED OPERATING CONDITIONS ................................................................................. 4

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4

ANALOG CHARACTERISTICS ................................................................................................ 5

POWER AND THERMAL CHARACTERISTICS....................................................................... 7

DIGITAL CHARACTERISTICS ................................................................................................. 7

SWITCHING CHARACTERISTICS .......................................................................................... 8

SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 10

2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 12

3. FUNCTIONAL DESCRIPTION ............................................................................................... 13

3.1 Overview .......................................................................................................................... 13

3.2 Analog Inputs ................................................................................................................... 13

3.2.1 Line Level Inputs ................................................................................................. 13

3.2.2 High Pass Filter ................................................................................................... 13

3.3 Analog Outputs ................................................................................................................14

3.3.1 Line Level Outputs .............................................................................................. 14

3.3.2 Digital Volume Control ........................................................................................ 14

3.4 Mute Control .................................................................................................................... 15

3.5 Clock Generation ............................................................................................................. 15

3.5.1 Clock Source ....................................................................................................... 15

3.5.2 Synchronization ................................................................................................... 15

3.6 Digital Interfaces .............................................................................................................. 15

3.6.1 Serial Audio Interface Signals ............................................................................. 15

3.6.2 Serial Audio Interface Formats ............................................................................ 16

CS4228A

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC ForeignTrade Law and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys

I a license under the Philips I

DTS is a registered trademark of the Digital Theater Systems, Inc.

Dolby, Dolby Digital, AC-3, AAC, and Pro Logic are registered trademarks of Dolby Laboratories, Inc.

THX is a registered trademark of Lucasfilms Ltd.

C Patent Rights to use those components in a standard I2C system.

CS4228A

3.7 Control Port Signals ......................................................................................................... 18

3.7.1 SPI Mode ............................................................................................................ 18

3.7.2 I2C Mode ............................................................................................................ 18

3.8 Control Port Bit Definitions .............................................................................................. 19

3.9 Power-up/Reset/Power Down Mode ............................................................................... 19

3.10 Power Supply, Layout, and Grounding .......................................................................... 20

4. REGISTER QUICK REFERENCE .......................................................................................... 21

5. REGISTER DESCRIPTIONS .................................................................................................. 22

5.1 Memory Address Pointer (MAP) ..................................................................................... 22

5.2 CODEC Clock Mode ........................................................................................................ 22

5.3 Chip Control ..................................................................................................................... 22

5.4 ADC Control .................................................................................................................... 23

5.5 DAC Mute1 Control ......................................................................................................... 23

5.6 DAC Mute2 Control ......................................................................................................... 24

5.7 DAC De-emphasis Control .............................................................................................. 24

5.8 Digital Volume Control ..................................................................................................... 24

5.9 Serial Port Mode .............................................................................................................. 25

5.10 Chip Status .................................................................................................................... 25

6. PIN DESCRIPTION ................................................................................................................. 26

7. PARAMETER DEFINITIONS .................................................................................................. 29

8. PACKAGE DIMENSIONS ...................................................................................................... 31

LIST OF FIGURES

Figure 1. Serial Audio Port Master Mode Timing ............................................................................ 9

Figure 2. Serial Audio Port Slave Mode Timing .............................................................................. 9

Figure 3. SPI Control Port Timing ................................................................................................. 10

Figure 4. I2C Control Port Timing ................................................................................................. 11

Figure 5. I2C Mode SCL Buffer Example...................................................................................... 11

Figure 6. Recommended Connection Diagram............................................................................. 12

Figure 7. Optional Line Input Buffer .............................................................................................. 13

Figure 8. Passive Output Filter with Mute ..................................................................................... 14

Figure 9. Butterworth Output Filter with Mute ............................................................................... 14

Figure 10. I

Figure 11. Left Justified Serial Audio Formats .............................................................................. 16

Figure 12. Right Justified Serial Audio Formats ............................................................................ 17

Figure 13. One Line Data Serial Audio Format ............................................................................. 17

Figure 14. Control Port Timing, SPI Slave Mode Write................................................................. 18

Figure 15. Control Port Timing, I2C Slave Mode Write ................................................................. 19

Figure 16. Control Port Timing, I2C Slave Mode Read................................................................. 19

S Serial Audio Formats ............................................................................................. 16

LIST OF TABLES

Table 1. Serial Audio Port Input Channel Allocations ................................................................... 16

Table 2. User Registers ................................................................................................................ 21

Table 3. Common Master Clock Frequencies.............................................................................. 27

CS4228A

1. CHARACTERISTICS AND SPECIFICATIONS

(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at T

SPECIFIED OPERATING CONDITIONS ((AGND, DGND = 0V; all voltages with respect to

ground.)

Parameter Symbol Min Typ Max Units

DC Power Supply Digital

Analog

Interface

VD - VL (Note 12)

Specified Temperature Range (-KS) T

VA VL

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to ground.)

Parameter Symbol Min Max Units

DC Power Supply Digital

Analog

Interface

VD - VL

Input Current (Note 1) - ±10 mA

Analog Input Voltage (Note 2) -0.7 VA + 0.7 V

Digital Input Voltage Input Pins

Bidirectional Pins (Notes 2 and 3)

Ambient Temperature (Power Applied) -55 +125 °C

Storage Temperature -65 +150 °C

VA VL

=25°C, VA = 5.0V, VD = 5.0V)

4.75

3.0*

-10 - 70 °C

-0.3

-0.7

5.0

5.25

2.00

6.0

2.0

VL + 2.5 VL + 0.7

V V V V

V V

Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

2. The maximum over or under voltage is limited by the input current.

3. Bidirectional pins configured as inputs.

Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

CS4228A

ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a

997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R

Base Rate Mode High Rate Mode

Parameter Symbol Min Typ Max Min Typ Max Units

Analog Input Characteristics - Minimum gain setting (0 dB) Differential Input; unless otherwise specified.

Dynamic Range, -60 dBFS input (A weighted)

(unweighted)

Total Harmonic Distortion + Noise (Note 4) THD+N - -88 -83 - -88 -83 dB

Interchannel Isolation - 100 - - 100 - dB

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Offset Error (with high pass filter) - - 0 - - 0 LSB

Full Scale Input Voltage (Differential): 5.24 5.66 6.09 5.24 5.66 6.09 Vp-p

Gain Drift - 100 - - 100 - ppm/°C

Input Resistance 10 - - 10 - - kΩ

Input Capacitance - - 15 - - 15 pF

A/D Decimation Filter Characteristics

Passband (Note 5) 0.022 - 21.77 0.022 - 43.54 kHz

Passband Ripple - - 0.01 - - 0.05 dB

Stopband (Note 5) 30.0 - 6114 72.41 - 6071 kHz

Stopband Attenuation (Note 6) 80 - - 45 - - dB

Group Delay t

Group Delay Variation vs. Frequency ∆ t

High Pass Filter Characteristics

Frequency Response: -3 dB (Note 7)

-0.13 dB

Phase Deviation @ 20 Hz (Note 7) - 10 - - 10 - Degree

Passband Ripple - - 0 - - 0 dB

91 97

- 17/Fs - - 17/Fs - s

--0--0µs

3.4

=10kΩ,CL=15pF)

91 97

3.4

dB dB

Hz Hz

Notes: 4. Referenced to typical full-scale differential input voltage (2 Vrms). Tested at -1 dBFS

5. Filter characteristics scale with output sample rate.

6. The analog modulator samples the input at 128 times Fs. For example, to obtain an output sample rate of 48 kHz the input must be sampled at 6.144 MHz. There is no rejection of input signals which are multiples of the sampling frequency (n × 6.144 MHz ±20.0 kHz where n = 0,1,2,3...).

7. High Pass Filter characteristics are specified for Fs=44.1 kHz.

CS4228A

ANALOG CHARACTERISTICS (Continued)

Base Rate Mode High Rate Mode

Parameter Symbol Min Typ Max Min Typ Max Units

Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 10 pF load; unless otherwise specified.

Dynamic Range, -60 dBFS input (A weighted)

(unweighted)

Total Harmonic Distortion + Noise (unweighted) THD+N - -90 -83 - -90 -83 dB

Interchannel Isolation - 95 - - 95 - dB

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Offset Voltage - 10 - - 10 - mV

Full Scale Output Voltage 3.42 3.7 3.98 3.42 3.7 3.98 Vp-p

Gain Drift - 100 - - 100 - ppm/°C

Analog Output Load

Minimum Load Resistance:

Maximum Load Capacitance:

Combined Digital and Analog Filter Characteristics

Frequency Response 10 Hz to 20 kHz ±0.1 ±0.1 dB

Deviation from Linear Phase - ±0.5 - - ±0.5 - Degrees

Passband: to 0.01 dB corner (Notes 8, 9) 0 - 21.77 0 - 43.54 kHz

Passband Ripple (Note 9) - - ±0.01 - - ±0.01 dB

Stopband (Notes 8, 9) 26.2 - - 62.5 - - kHz

Stopband Attenuation (Notes 8, 10) 70 - - 65 - - dB

Group Delay (Fs = Input Word Rate) tgd - 29/Fs - - 17/Fs - s

Analog Loopback Performance

Signal-to-noise Ratio (CCIR-2K weighted, -20 dB FS input)

CCIR-2K - 90 - - 90 - dB

93-100

100

93-100

100

dB dB

kΩ pF

8. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz, the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.

9. Digital filter characteristics.

10. Measurement bandwidth is 10 Hz to 3 Fs.

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, V

A=VD=VL

(Note 11, Note 12) BRM

power-down state (all supplies) (Note 13)

Power Dissipation (Note 11) V

A=VD=VL

= 5V normal operation

power-down (Note 13)

Package Thermal Resistance TSSOP (-KS) θ

Power Supply Rejection Ratio (1 kHz, 10 mV

=5V

BRM

)PSRR - 50 - dB

rms

CS4228A

35 78

0.3

0.2

0.4

0.2

567

56 37

105

0.5

715

12.5

mA mA mA

mW mW

°C/Watt °C/Watt

Notes: 11. Current consumption increases with increasing FS and increasing MCLK. Variance between speed

modesissmall.

12. VD current consumption increases (ID normal and ID_pdn) when VD - VL > 1.5V. When VD - VL = 1.7V, typically increases by 2 mA and when VD - VL = 2V, IDtypically increases by 12 mA.

13. Power down mode is defined as RST

pin = Low with clocks running.

DIGITAL CHARACTERISTICS (AGND, DGND = 0V, all voltages with respect to ground.)

Parameter Symbol Min Max Units

High-level Input Voltage VL=5V Low-level Input Voltage

High-level Input Voltage VL=3.3V Low-level Input Voltage

High-level Output Voltage at VL = 5V I

VL = 3.3V I

=-2.0mA

= -100 µA

=-2.0mA

Low-level Output Voltage at VL = 5V I

VL = 3.3V I

=2.0mA

= 100 µA

=-2.0mA

Input Leakage Current (Digital Inputs) - 10 µA

Output Leakage Current (High-Impedance Digital Outputs) - 10 µA

0.7 x VL

2.2

VL - 1.0 VL - 0.7

2.3

0.3 x VL

1.0

0.4

0.2

0.4

V V

V V V

CS4228A

SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0V, Logic 1 = VL)

Parameter Symbol Min Typ Max Units

Audio ADC's and DAC's Sample Rate BRM

HRM

MCLK Frequency (Note 14) 3.84 - 25.6 MHz

MCLK Duty Cycle BRM

MCLK =128, 384 Fs

MCLK = 256, 512 Fs

HRM

MCLK = 64, 192 Fs

MCLK = 128, 256 Fs

RST

Low Time (Note 15)

Fs 30

40 40

1--ms

50 50

100

60 60

kHz kHz

% %

SCLK Falling Edge to SDOUT Output Valid (Note 16) t

LRCK Edge to MSB Valid t

SDIN Setup Time Before SCLK Rising Edge t

SDIN Hold Time After SCLK Rising Edge t

SCLK Period BRM (Note 17) t

SCLK Period HRM (Note 17) t

dpd

lrpd

sck

---------------------128()Fs

-----------------64()Fs

-50ns

-20ns

-10ns

-30ns

--ns

Master Mode

SCLK Falling to LRCK Edge t

mslr

+10 - ns

SCLK Duty Cycle 50 - %

Slave Mode

SCLK High Time t

SCLK Low Time t

SCLK rising to LRCK Edge t

LRCK Edge to SCLK Rising t

sckh

sckl

lrckd

lrcks

50 - - ns

25 - - ns

Notes: 14. See Cl1:0 register on page 22 for settings.

15. After powering up the CS4228A, RST

should be held low for 1 ms after the power supplies and clocks

are settled.

16. Scales with sample rate Fs. 50 ns valid at 48 kHz, more time at slower Fs and less time at faster Fs.

17. See DCK1:0 register on page 25 for settings.

SCLK (o u tp u t)

LRC K (o u tp u t)

SDOUT

Figure 1. Serial Audio Port Master Mode Timing

CS4228A

mslr

LRCK (input)

SCLK (input)

SDIN1 SDIN2 SDIN3

SDOUT

lrckd

lrp d

lrc k s

sckh

MSB

sckl

Figure 2. Serial Audio Port Slave Mode Timing

dpd

MSB-1

CS4228A

SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL)

Parameter Symbol Min Max Units

SPI Mode (SDOUT > 47 kΩ to GND)

CCLK Clock Frequency f

High Time Between Transmissions t

Falling to CCLK Edge t

CCLK Low Time t

CCLK High Time t

CDIN to CCLK Rising Setup Time t

CCLK Rising to DATA Hold Time (Note 18) t

Rise Time of CCLK and CDIN (Note 19) t

Fall Time of CCLK and CDIN (Note 19) t

sck

csh

css

scl

sch

dsu

Notes: 18. Data must be held for sufficient time to bridge the transition time of CCLK.

19. For F

SCK

<1MHz

-6MHz

1.0 µs

20 ns

66 ns

40 ns

15 ns

30 ns

100 ns

CCLK

CDIN

css

scl

dsu

sch

Figure 3. SPI Control Port Timing

csh

+ 22 hidden pages