Cirrus Logic CS4228 Service Manual

Advance Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

1

Copyright  Cirrus Logic, Inc. 1999

(All Rights Reserved)

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

CS4228

24-Bit, 96 kHz Surround Sound Codec

Features

l Two 24-bit A/D Converters

- 102 dB dynamic range

- 90 dB THD+N

l Six 24-bit D/A Converters

- 103 dB dynamic range and SNR

- 90 dB THD+N

l Sample rates up to 100 kHz
l Pop-free Digital Output Volume Controls

- 90.5 dB range, 0.5 dB resolution (182 levels)

- Variable smooth ramp rate, 0.125 dB steps

l Mute Control pin for off-chip muting circuits
l On-chip Anti-alias and Output Filters
l De-emphasis filters for 32, 44.1 and 48 kHz

Description

The CS4228 codec provides two analog-to-digital and
six digital-to-analog delta- sigma converters, along with
volume controls, in a c ompact +5/+3.3 V, 28-pin SSOP
device. Combined with an IEC958 (SPDIF) receiver (like
the CS8414) and surround sound decoder (such as one
of the CS492x or CS493xx families), it is ideal for use in
DVD player, A/V recei ver and car audio systems sup­porting multiple stan dards such as Dolby Digital A C-3,
AAC, DTS, Dolby ProLogic, THX, and MPEG.

A flexible seri al audio interface allows operation in Left
Justified, Right Justified, I

2

S, or One Line Data modes.

ORDERING INFORMATION

CS4228-KS -10° to +70° C 28-pin SSOP
CDB4228 Evaluation Board

I

SCL/CCLK SDA/CDIN VD

AOUT1

LRCK
SCLK

SDIN1

SDOUT

SERIAL AUDIO

CONTROL PORT

DIGITAL FILTERS

ANALOG LOW PASS AND

OUTPUT STAGE

VA

AOUT2

AINL+
AINL-

SDIN2

MCLK

DGND

AOUT3

AOUT4

AINR+
AINR-

LEFT ADC

SDIN3

MUTECAD0/CS

RST

FILT

AOUT5

AOUT6

DIGITAL FILTERS

DATA INTERFACE

VL

RIGHT ADC

AGND

WITH DE-EMPHASIS

∆Σ

DAC #1

CLOCK MANAGER

MUTE CONTROL

∆Σ

DAC #2

∆Σ

DAC #3

∆Σ

DAC #4

∆Σ

DAC #5

∆Σ

DAC #6

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

DGND AGND

JUL ‘99

DS307PP1

CS4228

2 DS307PP1

TABLE OF CONTENTS

CHARACTERISTICS AND SPECIFICATIONS ................................................... 4

ANALOG CHARACTERISTICS................................................................... 4

DIGITAL CHARACTERISTICS.................................................................... 6

SWITCHING CHARACTERISTICS .................................... ....... ...... ....... ..... 6

SWITCHING CHARACTERISTICS - CONTROL PORT ............................. 8

ABSOLUTE MAXIMUM RATINGS............................................................ 10

RECOMMENDED OPERATING CONDITIONS........................................ 10

TYPICAL CONNECTION DIAGRAM .................................................................11

FUNCTIONAL DESCRIPTION .......................................................................... 12

Overview ......................... ................................ ................................ ..........12

Analog Inputs ............................................................................................ 12

Line Level Inputs ................................................................................ 12

High Pass Filter ..................................................................................12

Analog Outputs .........................................................................................12

Line Level Outputs .............................................................................12

Digital Volume Control ....................................................................... 13

Mute Control .............................................................................................13

Clock Generation ......................................................................................14

Clock Source ......................................................................................14

Synchronization ........ .......................... ......................... ....................... 14

Digital Interfaces ....................................................................................... 14

Serial Audio Interface Signals ............................................................ 14

Serial Audio Interface Formats ...........................................................14

Control Port Signals ..................................................................................14

SPI Mode ........................................................................................... 16

I

2

C Mode ............................................................................................ 16

Control Port Bit Definitions ........................................................................17

Power-up/Reset/Power Down Mode ......................................................... 17

Power Supply, Layout, and Grounding ..................................................... 18

REGISTER DESCRIPTION ................................................................................19

PIN DESCRIPTION............................................................................................. 24

PARAMETER DEFINITIONS ............................................................................. 28

PACKAGE DIMENSIONS .................................................................................. 29

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Dolby, Pro Logic, and AC-3 are trademarks of Dolby Laboratories Licensing Corporation.
Preliminary product info rmation describes products which are in production, but f or which full characteriza ti on data is not yet availab le. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accur ate and reli able. However , the i nformati on is sub ject t o change with out no tice and i s provi ded “AS IS” withou t warranty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or trade secre ts. No part of
this publication may be copied, reproduced , stored in a retr i eval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tten consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be print ed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.

CS4228

DS307PP1 3

LIST OF FIGURES

Figure 1. Serial Audio Port Master Mode Timing ...................................................... 7

Figure 2. Serial Audio Port Slave Mode Timing ........................................................ 7

Figure 3. SPI Control Port Timing ............................................................................. 8

Figure 4. I

2

C Control Port Timing .............................................................................. 9

Figure 5. Recommended Connection Diagram ....................................................... 11

Figure 6. Optional Line Input Buffer ........................................................................ 12

Figure 7. Passive Output Filter with Mute ............................................................... 13

Figure 8. Butterworth Output Filter with Mute .......................................................... 13

Figure 9. Right Justified Serial Audio Formats ........................................................ 15

Figure 10.I

2

S Serial Audio Formats .......................................................................... 15

Figure 11.Left Justified Serial Audio Formats .......................................................... 15

Figure 12.One Line Data Serial Audio Format ......................................................... 16

Figure 13.Control Port Timing, SPI mode ................................................................ 17

Figure 14.Control Port Timing, I

2

C Mode ................................................................. 17

CS4228

4 DS307PP1

CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (Unless otherwise specified T

A

= 25°C; VA = +5V, V D = VL = +3.3V ;
Full Scale Input Sine wave, 1kHz; Fs = 44.1 kHz BRM, 96 kHz HRM; Measurement Bandwidth is 20 Hz to 20 kHz;
Local components as shown in "Recommended Connection Diagram"; SPI control mode, Left Justified serial for­mat, MCLK = 256 Fs BRM, 128 Fs HRM, SCLK = 64 Fs)

Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms).

2. Filter characteristics scale with output sample rate.

3. The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (n × 5.6448 MHz ±20.0 kHz
where n = 0,1,2,3...).

4. Group delay for Fs = 44.1 kHz, t

gd

= 15/44.1 kHz = 340µs. Fs = sample rate.

Specifications are subject to change without notice

Base Rate Mode High Rate Mode

Parameter Symbol Min Typ Max Min Typ Max Units

Analog Input Characteristics

- Minimum gain setting (0 dB) Differential Input; unless otherwise specified.

ADC Resolution Stereo Audio channels

16 - 24 16 24 Bits

Total Harmonic Distortion

THD - 0.003 - - 0.003 - %

Dynamic Range (A weighted)

(unweighted)

TBD-102

99

-

-

TBD
TBD

102

99

-

-

dB
dB

Total Harmonic Distortion + Noise -1dB (Note 1)

THD+N - -90 TBD - -90 TBD dB

Interchannel Isolation

-90- -90- dB

Interchannel Gain Mismatch

- 0.1 - - 0.1 - dB

Offset Error (with high pass filter)

--0--0LSB

Full Scale Input Voltage (Differential):

5.66 5.66 Vp-p

Gain Drift

- 100 - - 100 - ppm/°C

Input Resistance

10--10--k

Ω

Input Capacitance

- - 15 15 pF

A/D Decimation Filter Characteristics

Passband (Note 2)

0.02 - 20.0 0.02 - 40 kHz

Passband Ripple

- - 0.01 - - 0.05 dB

Stopband (Note 2)

27.56 - 5617 66.53 - 5578 kHz

Stopband Attenuation (Note 3)

80--45--dB

Group Delay (Note 4)

t

gd

- 15/Fs - - 15/Fs - s

Group Delay Variation vs. Frequency

∆

t

gd

--0--0µs

High Pass Filter Characteristics

Frequency Response: -3 dB (Note 2)

-0.13 dB

-

-

3.4
20

-

-

-

-

3.4
20

-

-

Hz
Hz

Phase Deviation @ 20 Hz

(Note 2)

-10- -10-Degree

Passband Ripple

--0--0dB

CS4228

DS307PP1 5

ANALOG CHARACTERISTICS (Continued)

Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,

the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.

6. Digital filter characteristics.

7. Measurement bandwidth is 10 Hz to 3 Fs.

Specifications are subject to change without notice

Base Rate Mode High Rate Mode

Parameter Symbol Min Typ Max Min Typ Max Units

Analog Output Characteristics

- Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified.

DAC Resolution

16 - 24 16 24 Bits

Signal-to-Noise/Idle Channel Noise
(DAC muted, A weighted)

TBD 103 - TBD 103 - dB

Dynamic Range (DAC not muted, A weighted)

(DAC not muted, unweighted)

TBD-103

100

-

-

-

-

103
100

-

-

dB
dB

Total Harmonic Distortion

THD - 0.003 - - 0.003 - %

Total Harmonic Distortion + Noise

THD+N - -90 TBD - -90 - dB

Interchannel Isolation

-90- -90- dB

Interchannel Gain Mismatch

- 0.1 - - 0.1 - dB

Attenuation Step Size (All Outputs)

TBD 0.5 TBD TBD 0.5 TBD dB

Programmable Output Attenuation Span

TBD -90.5 - TBD -90.5 - dB

Offset Voltage

-10- -10- mV

Full Scale Output Voltage

TBD 1.3 TBD - 1.3 - Vrms

Gain Drift

- 100 - - 100 - ppm/°C

Analog Output Load

Minimum Load Resistance:

Maximum Load Capacitance:

-

-

10

100

-

-

-

-

10

100

-

-

k

Ω

pF

Combined Digital and Analog Filter Characteristics

Frequency Response 10 Hz to 20 kHz

±0.1 ±0.1 dB

Deviation from Linear Phase

- ±0.5 - - ±0.5 - Degrees

Passband: to 0.01 dB corner (Notes 5, 6)

0 - 20.0 0 - 40 kHz

Passband Ripple (Note 6)

- - ±0.01 - - ±0.01 dB

Stopband (Notes 5, 6)

24.1 - - 56 - - kHz

Stopband Attenuation (Notes 4, 7)

70--65--dB

Group Delay (Fs = Input Word Rate)

tgd - 16/Fs - - 16/Fs - s

Analog Loopback Performance

Signal-to-noise Ratio
(CCIR-2K weighted, -20 dB FS input)

CCIR-2K - TBD - - TBD - dB

CS4228

6 DS307PP1

ANALOG CHARACTERISTICS (Continued)

DIGITAL CHARACTERISTICS Unless otherwise specified (T

A

= 25 °C; VD = VL = +3.3V;

VA =+ 5V)

SWITCHING CHARACTERISTICS (T

A

= 25°C; VD = VL = +3.3V, VA = +5V, outputs loaded with

30 pF)

Power Supply

Symbol Min Ty p Max Min Typ Max Units

Power Supply Current Operating
VA = 5V, VD = VL = 3.3V VA

VL

VD

Power Down

VA
VL

VD

-

-

-

-

-

-

25

2

42

TBD

2

0.1

TBD
TBD
TBD

TBD
TBD
TBD

-

-

-

-

-

-

25

2

48

TBD

2

0.1

TBD
TBD
TBD

TBD
TBD
TBD

mA
mA
mA

mA
mA
mA

Power Supply Re je cti o n (1 kH z, 10 mV

rms

)

- 50 - 50 dB

Parameter Symbol Min Typ Max Units

High-level Input Voltage

V

IH

0.7xVL - - V

Low-level Input Voltage

V

IL

-0.3xVLV

High-level Output Voltage at I

0

= -2.0 mA

V

OH

VL - 1.0 - - V

Low-level Output Voltage at I

0

= 2.0 mA

V

OL

--0.4V

Input Leakage Current (Digital Inputs)

--10µA

Output Leakage Current (High-Impedance Digital Outp uts)

--10µA

Parameter Symbol Min Typ Max Units

Audio ADC's & DAC's Sample Rate BRM

HRM

Fs 30

60

-

-

50

100

kHz
kHz

MCLK Frequency

3.84 - 25.6 MHz

MCLK Duty Cycle BRM

MCLK =128, 384 Fs

MCLK = 256, 512 Fs

HRM

MCLK = 64, 192 Fs

MCLK = 128, 256 Fs

TBD

40

TBD

40

50

50

-

TBD

60

TBD

60

%
%

%
%

MCLK Jitter Tolerance

-500-ps

CS4228

DS307PP1 7

SWITCHING CHARACTERISTICS (Continued)

Notes: 8. After powering up the CS4228, RST

should be held low until the power supplies and clocks are settled.

Parameter Symbol Typ Max Units

RST

Low Time (Note 8)

1- -ms

SCLK Falling Edge to SDOUT Output Valid (DSCK=0)

t

dpd

-TBDns

LRCK Edge to MSB Valid

t

lrpd

-TBDns

SDIN Setup Time Before SCLK Rising Edge

t

ds

-TBDns

SDIN Hold Time After SCLK Rising Edge

t

dh

-TBDns

Master Mode

SCLK Falling to LRCK Edge

t

mslr

+10 - ns

SCLK Duty Cycle

50 - %

Slave Mode

SCLK Period

t

sckw

--ns

SCLK High Time

t

sckh

TBD - - ns

SCLK Low Time

t

sckl

TBD - - ns

SCLK rising to LRCK Edge (DSCK=0)

t

lrckd

TBD - - ns

LRCK Edge to SCLK Rising (DSCK=0)

t

lrcks

TBD - - ns

Figure 1. Serial Audio Port Master Mode Timing

t

mslr

SCLK*
(output)

LRCK
(output)

SDOUT

sckh

sckl

sckw

t

t

t

MSB

MSB-1

*SCLK shown for DSCK = 0.
SCLK inverted for DSCK = 1.

t

dpd

SDOUT

LRCK
(input)

SCLK*
(input)

SDIN1
SDIN2
SDIN3

dh

t

ds

t

lrpd

t

lrcks

t

lrckd

t

Figure 2. Serial Audio Port Slave Mode Timing

CS4228

8 DS307PP1

SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25°C, VD = VL = +3.3V,

VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL+, C

L

= 30 pF)

Notes: 9. Data must be held for sufficient time to bridge the transition time of CCLK.

10. For F

SCK

< 1 MHz

Parameter Symbol Min Max Units

SPI Mode

(SDOUT > 47kΩ to GND)

CCLK Clock Frequency

f

sck

-6MHz

CS

High Time Between Transmissions

t

csh

1.0

µ

s

CS

Falling to CCLK Edge

t

css

20 ns

CCLK Low Time

t

scl

66 ns

CCLK High Time

t

sch

66 ns

CDIN to CCLK Rising Setup Time

t

dsu

40 ns

CCLK Rising to DATA Hold Time (Note 9)

t

dh

15 ns

Rise Time of CCLK and CDIN (Note 10)

t

r2

100 ns

Fall Time of CCLK and CDIN (Note 10)

t

f2

100 ns

t

r2

t

f2

t

dsu

t

dh

t

sch

t

scl

CS

CCLK

CDIN

t

css

t

csh

Figure 3. SPI Control Port Timing

CS4228

DS307PP1 9

SWITCHING CHARACTERISTICS - CONTROL PORT (T

A

= 25°C; VD = VL = +3.3V,

VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL, C

L

= 30 pF)

Notes: 11. Use of the I

2

C bus interface requires a license from Philips. I2C is a registered trademark of Philips

Semiconductors.

12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Parameter Symbol Min Max Units

I2C® Mode

(SDOUT < 47kΩ to ground) (Note 11)

SCL Clock Frequency

f

scl

-100kHz

Bus Free Time Between Transmissions

t

buf

4.7

µ

s

Start Condition Hold Time (prior to first clock pulse)

t

hdst

4.0

µ

s

Clock Low Time

t

low

4.7

µ

s

Clock High Time

t

high

4.0

µ

s

Setup Time for Repeated Start Condition

t

sust

4.7

µ

s

SDA Hold Time from SCL Falling (Note 12)

t

hdd

0

µ

s

SDA Setup Time to SCL Rising

t

sud

250 ns

Rise Time of Both SDA and SCL Lines

t

r

1

µ

s

Fall Time of Both SDA and SCL Lines

t

f

300 ns

Setup Time for Stop Condition

t

susp

4.7

µ

s

t

buf

t

hdst

t

hdst

t

low

t

r

t

f

t

hdd

t

high

t

sud

t

sust

t

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

Figure 4. I2C Control Port Timing

CS4228

10 DS307PP1

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)

Notes: 13. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

14. The maximum over or under voltage is limited by the input current.

Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect

to 0 V.)

Parameter Symbol Min Typ Max Units

Power Supplies Digital

Analog

Interface

VD

VA
VL

-0.3

-0.3

-0.3

-

-

-

6.0

6.0

6.0

V
V
V

Input Current (Note 13)

--±10mA

Analog Input Voltage (Note 14)

-0.7 - VA + 0.7 V

Digital Input Voltage (Note 14)

-0.7 - VL + 0.7 V

Ambient Temperature (Power Applied)

-55 - +125 °C

Storage Temperature

-65 - +150 °C

Parameter Symbol Min Typ Max Units

Power Supplies Digital

Analog

Interface

VD

VA
VL

TBD

4.75

2.7

3.3

5.0

5.0

TBD

5.25

5.25

V
V
V

Operating Ambient Temperature

T

A

-10 25 70 °C

CS4228

DS307PP1 11

TYPICAL CONNECTION DIAGRAM

+5V
Supply

+

1 µF 0.1 µF

+

1

µ

F 0.1 µF

VA VD

AGND DGND

MCLK

External
Clock Input

All unused inputs
should be tied to 0V.

AOUT1

AOUT2

AOUT3

AOUT4

AOUT5

AOUT6

FILT

150

Ω

AINL-

AINL+

AINR-

AINR+

CS4228

ANALOG
FILTER

From Analog Input Stage

MUTEC

+3.3V or 5 V
Supply

VL

+

1 µF

0.1 µF

10

7

22

15

28

27

26

25

24

23

98

21

18

19

17

16

10 µF

Ferrite Bead

ANALOG
FILTER

ANALOG
FILTER

ANALOG
FILTER

ANALOG
FILTER

ANALOG
FILTER

2

* Required for I C
control port mode
only

VL

150

Ω

2.2 nf

2.2 nf

+3.3V
Supply

Ferrite BeadFerrite Bead

Digital Audio

Peripheral

or

DSP

SDIN1

SDIN2

SDIN3

SDOUT

LRCK

SCLK

50

Ω

50

Ω

33 K*

4

1

2

3

5

6

50

Ω

Microcontroller

SCL/CCLK
AD0/CS

RST

14

13

11

SDA/CDIN

12

2.2 K*

VL

22 µF

22 µF

+

+

+

100 µF

100 µF

+

+

0.1µF

20

0.1µF

Figure 5. Recommended Connection Diagram

CS4228

12 DS307PP1

FUNCTIONAL DESCRIPTION
Overview

The CS4228 is a 24-bit audio codec comprised of 2
analog-to-digital converters (ADC) and 6 digital­to-analog converters (DAC), all implemented us­ing single-bit delta-sigma techniques. Other func­tions integrated with the codec include independent
digital volume controls for each DAC, digital DAC
de-emphasis filters, ADC high-pass filters, an on­chip voltage reference, and a flexible serial audio
interface. All functions are configured through a
serial control port operable in SPI and I2C compat­ible modes. Figure 5 shows the recommended con­nections for the CS4228.

Analog Inputs

Line Level Inputs

AINR+, AINR-, AINL+, and AINL- are the line
level analog inputs (See Figure 5). These pins are
internally biased to a DC operating voltage of ap­proximately 2.3 VDC. AC coupling the inputs pre­serves this bias and minimizes signal distortion.
Figure 5 shows operation with a single-ended input
source. This source may be supplied to either the
positive or negative input as long as the unused in­put is connected to ground through capacitors as
shown. When operated with single-ended inputs,
distortion will increase at input levels higher than

-1 dBFS. Figure 6 shows an example of a differen­tial input circuit.

Muting of the stereo ADC is possible through the
ADC Control Byte.

The ADC output data is in 2’s complement binary
format. For inputs above positive full scale or be­low negative full scale, the ADC will output
7FFFFFH or 800000H, respectively.

High Pass Filter

Digital high pass filters in the signal path after the
ADCs remove any DC offsets present on the analog

inputs. This helps to prevent audible "clicks" when
switching the audio in devices downstream from
the ADCs. The high pass filter response, given in
“High Pass Filter Characteristics” on page 4, scales
linearly with sample rate. Thus, for High Rate
Mode, the -3 dB frequency at a 96 kHz sample rate
will be equal to 96/44.1 times that at a sample rate
of 44.1 kHz.

The high pass filters can be disabled by setting the
HPF bit in the ADC Control register. When assert­ed, any DC present at the analog inputs will be rep­resented in the ADC outputs. The high pass filter
may also be “frozen” using the HPFZ bit in the
ADC Control register. In this condition, it will re­member the DC offset present at the ADC inputs at
the moment the HPFZ bit was asserted, and will
continue to remove this DC level from the ADC
outputs. This is useful in cases where it is desirable
to eliminate a fixed DC offset while still maintain­ing full frequency response down to DC.

Analog Outputs

Line Level Outputs

The CS4228 contains on-chip buffer amplifiers ca­pable of producing line level outputs. These ampli­fiers are biased to a quiescent DC level of
approximately 2.3 V. This bias, as well as varia ­tions in offset voltage, are removed using off-chip
AC load coupling.

+

-

0.1µF

10 µf

10 k

+

-

4.7 k

10 k

AIN -

10 µF

VA

+

AIN +

2.2 nf

150

150

10 k

10 k

~ 8.5 k

signal

+

Figure 6. Optional Line Input Buffer

CS4228

DS307PP1 13

High frequency noise beyond the audio passband,
resulting from the delta-sigma conversion process
produces high frequency noise beyond the audio
passband, most of which is removed by the on-chip
analog filters. The remaining out-of-band noise can
be attenuated using an off-chip low pass filter. For
most applications, a simple passive filter as show in
Figure 7 can be used. Note that this circuit also
serves to block the DC present at the outputs. Fig­ure 8 gives an example of a filter which can be used
in applications where greater out of band attenua­tion is desired. The 2-pole Butterworth filter has a

-3 dB frequency of 50 kHz, a passband attenuation
of 0.1 dB at 20 kHz providing optimal out-of-band
filtering for sample rates from 44.1 kHz to 96 kHz.
The filter has and a gain of 1.56 providing a 2 Vrms
output signal.

Digital Volume Control

Each DAC’s output level is controlled via the Dig­ital Volume Control register operating over the
range of 0 to 90.5 dB attenuation with 0.5 dB reso­lution. Volume control changes do not occur in­stantaneously. Instead they ramp in increments of

0.125 dB at a variable rate controlled by the
RMP1:0 bits in the Digital Volume Control regis­ter.

Each output can be independently muted via mute
control bits MUT6-1 in the DAC Mute1 Control
register. When assert ed, MUT attenu ates the corr e­sponding DAC to its maximum value (90.5 dB).
When MUT is deasserted, the corresponding DAC
returns to the attenuation level set in the Digital
Volume Control register. The attenuation is
ramped up and down at the rate specified by the
RMP1:0 bits.

To achieve complete digital attenutation of an in­coming signal, Hard Mute controls are provided.
When asserted, Hard Mute will send zero data to a
corresponding pair of DACs. Hard Mute is not
ramped, so it should only be asserted after setting
the two corresponding MUT bits to prevent high
frequency noise from appearing on the DAC out­puts. Hard Mute is controlled by the
HMUTE56/34/12 bits in the DAC Mute2 Control
register.

Mute Control

The Mute Control pin is typically connected to an
external mute control circuit as shown in Figure 7
and Figure 8. Mute Control is asserted during pow­er up, power down, and when serial port clock er­rors are present. The pin can also be controlled by
the user via the control port, or automatically as­serted when zero data is present on all six DAC in­puts. To prevent large transients on the output, it is
desirable to mute the DAC outputs before the Mute
Control pin is asserted. Please see the MUTEC pin
in the Pin Descriptions section for more informa­tion.

560

2SC2878

2.2 k

MUN2IIIT1

10 k

MUTEC

Line Out

MUTEDRV

10 k

+

22

µ

F

100 k

AOUT

Figure 7. Passive Output Filter with Mute

C=142µF

C

F

s

_

3.16 k
+

A

OUT

3.16 k

MC33078

1nf

GND

1nf

10µf

+

MUTE DRV

Line
Out

MUTE

5
6

7

100 pf

3.16 k

1.78 k

+12

-12

_

3.16 k
+

A

OUT

3.16 k

MC33078

1nf

GND

1nf

10µf

+

MUTE DRV

Line
Out

MUTE

5
6

7

100 pf

3.16 k

1.78 k

+12

-12

Figure 8. Butterworth Output Filter with Mute

CS4228

14 DS307PP1

Clock Generation

The master clock, MCLK, is supplied to the
CS4228 from an external clock source. If MCLK

stops for 10µs, the CS4228 will enter Power Down
Mode in which the supply current is reduced as
specified under “Power Supply” on page 6. In all
modes it is required that the number of MCLK pe­riods per SCLK and LRCK period be constant.

Clock Source

The CS4228 internal logic requires an external
master clock, MCLK, that operates at multiples of
the sample rate frequency, Fs. The MCLK/Fs ratio
is determined by the CI1:0 bits in the CODEC
Clock Mode register.

Synchronization

The serial port is internally synchronized with
MCLK. If from one LRCK cycle to the next, the
number of MCLK cycles per LRCK cycle changes
by more than 32, the CS4228 will undergo an inter­nal reset of its data paths in an attempt to resyn­chronize. Consequently, it is advisable to mute the
DACs when changing from one clock source to an­other to avoid the output of undesirable audio sig­nals as the device resynchronizes.

Digital Interfaces

Serial Audio Interface Signals

The serial audio data is presented in 2's comple­ment binary form with the MSB first in all formats.
The serial interface clock, SCLK, is used for both
transmitting and receiving audio data. SCLK can
be generated by the CS4228 (master mode) or it
can be input from an external source (slave mode).
Mode selection is made with the DMS1:0 bits in
the Serial Port Mode register. The number of
SCLK cycles in one sample period can be set using
the DCK1:0 bits as detailed in the Serial Port Mode
register.

The Left/Right clock (LRCK) is used to indicate
left and right data frames and the start of a new
sample period. It may be an output of the CS4228
(master mode), or it may be generated by an exter­nal source (slave mode). The frequency of LRCK is
the same as the system sample rate, Fs.

SDIN1, SDIN2, and SDIN3 are the data input pins.
SDOUT, the data output pin, carries data from the
two 24-bit ADC's. The serial audio port may also
be operated in One Line Data Mode in which all 6
channels of DAC data is input on SDIN1 and the
stereo ADC data is output on SDOUT. Table 1 out­lines the serial port input to DAC channel alloca­tions.

Serial Audio Interface Formats

The digital audio port supports 6 formats, shown in
Figures 9, 10, 11 and 12. These formats are selected
using the DDF2:0 bits in the Serial Port Mode reg­ister.

In One Line Data Mode, all 6 DAC channels are in­put on SDIN1. One Line Data Mode is only avail­able in BRM. See Figure 12 for channel
allocations.

Control Port Signals

Internal registers are accessed through the control
port. The control port may be operated asynchro­nously with respect to audio sample rate. However,
to avoid potential interference problems, the con­trol port pins should remain static if no register ac­cess is required.

DAC Inputs

SDIN1 left channel

right channel

single line

DAC #1
DAC #2
All 6 DAC channels

SDIN2 left channel

right channel

DAC #3
DAC #4

SDIN3 left channel

right channel

DAC #5
DAC #6

Table 1. Serial Audio Port Input Channel Allocations

CS4228

DS307PP1 15

LRCK

SCLK

Left Channel

Right Channel

SDIN1/2/3
SDOUT

6543210987

15 14 13 12 11 10

6543210987

15 14 13 12 11 10

Figure 9. Right Justified Serial Audio Formats

Right Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
16 32, 48, 64, 128 Fs 48 Fs Slave only
20 48, 64, 128 Fs 48 Fs Slave only
24 48, 64, 128 Fs 48 Fs Slave only

Figure 11. I2S Serial Audio Formats

I2S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
16 32, 48, 64, 128 Fs 48 Fs Slave only
18 to 24 48, 64, 128 Fs 48 Fs Slave only

LRCK

SCLK

Left Channel

Right Channel

SDIN1/2/3
SDOUT

+3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5

+3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

LRCK

SCLK

Left Channel

Right Channel

SDIN1/2/3
SDOUT

+3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5

+3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

Figure 10. Left Justified Serial Audio Formats

Left Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
16 32, 48, 64, 128 Fs 48 Fs Slave only
18 to 24 48, 64, 128 Fs 48 Fs Slave only

CS4228

16 DS307PP1

The control port has 2 operating modes: SPI and
I2C compatible. In both modes the CS4228 oper­ates as a slave device. Mode selection is deter­mined by the state of the SDOUT pin when RST
transitions from low to high: high for SPI, low for
I2C. SDOUT is internally pulled high to VL. A re­sistive load from SDOUT to DGND of less than 47
kΩ will enable I2C Mode after a reset.

SPI Mode

In SPI mode, CS is the CS4228 chip select signal,
CCLK is the control port bit clock input, and CDIN
is the input data line. There is no data output line,
therefore all registers are write-only in SPI mode.
Data is clocked in on the rising edge of CCLK.

Figure 13 shows the operation of the control port in
SPI mode. The first 7 bits on CDIN, after CS goes
low, form the chip address (0010000). The eighth
bit is a read/write indicator (R /W), which should be
low to write. The next 8 bits set the Memory Ad­dress Pointer (MAP) which is the address of the
register that is to be written. The following bytes
contain the data which will be placed into the reg­isters designated by the MAP.

The CS4228 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is zero, then the MAP will stay constant for
successive reads or writes. If INCR is 1, then MAP
will increment after each byte is read or written, al­lowing block reads or writes of successive regis­ters.

I2C Mode

In I2C mode, SDA is a bidirectional data line. Data
is clocked into and out of the port by the SCL clock.
The signal timing is shown in Figure 14. The AD0
pin forms the LSB of the chip address. The upper 6
bits of the 7 bit address field must be 001000. To
communicate with a CS4228, the LSB of the chip
address field, which is the first byte sent to the
CS4228 after a Start condition, should match the
setting of the AD0 pin. The eighth bit of the address
bit is the R/W bit (high for a read, low for a write).
When writing, the next byte is the Memory Ad­dress Pointer (MAP) which selects the register to
be read or written. If the operation is a read, the
contents of the register pointed to by the MAP will
be output. Setting the auto increment bit in the

LRCK
SCLK

SDIN1/2/3

LSBMSB

20 clks

64 clks 64 clks

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB

DAC1 DAC3 DAC5 DAC2 DAC4 DAC6

20 clks

20 clks 20 clks

20 clks 20 clks

20 clks

ADCL ADCR

20 clks

SDOUT

Left Channel Right Channel

Figure 12. One Line Data Serial Audio Format

One Line Data Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
20 128 Fs 6 inputs, 2 outputs, BRM only

CS4228

DS307PP1 17

MAP allows successive reads or writes of consecu­tive registers. Each byte is separated by an ac­knowledge bit.

Control Port Bit Definitions

All registers are read/wri te, exce pt the Chi p Status
register which is read-only. For more detailed in­formation, see the bit definition tables starting on
page 19.

Power-up/Reset/Power Down Mode

Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers are reset to their default
settings, and the device remains in a low power

mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in re­set, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.

The CS4228 will enter a stand-by mode if the mas­ter clock source stops for approximately 10 µs or if
the number of MCLK cycles per LRCK period var­ies by more than 32. Should this occur, the control
registers retain their settings.

MAP

MSB

LSB

DATA

byte 1

byte n

R/W

R/W

MAP = Memory Address Pointer

ADDRESS

CHIP

ADDRESS

CHIP

CDIN

CCLK

CS

0010000

0010000

Figure 13. Control Port Timing, SPI mode

SDA

SCL

AD

0

R/W

Start

ACK ACK ACK

Stop

Note 1: If operation is a write, this by te contains the Memory Address Pointer, MAP.

Note 1

001000

D7:0

D7:0

Figure 14. Control Port Timing, I2C Mode

CS4228

18 DS307PP1

The CS4228 will mute the analog outputs, assert
the MUTEC pin and enter the Power Down Mode
if the supply drops below approximately 4 volts.

Power Supply, Layout, and Grounding

The CS4228 requires careful attention to power
supply and grounding details. VA is normally sup­plied from the system analog supply. VD is from a

3.3VDC supply, and VL should be from the supply
used for the devices digitally interfacing with the
CS4228. The power up sequence of these three
supply pins is not important.

AGND and DGND pins should both be tied to a
solid ground plane surrounding the CS4228. If the
system analog and digital ground planes are sepa­rate, they should be connected at a point near where

the supply currents enter the board. A solid ground
plane underneath the part is recommended.

Decoupling capacitors should be mounted in such a
way as to minimize the circuit p ath length from the
CS4228 supply pin, through the capacitor, to the
applicable CS4228 AGND or DGND pin. The
small value ceramic capacitors should be closest to
the part. In some cases, ferrite beads in the VL, VD
and VA supply lines, and low-value resistances
(~ 50 Ω) in series with the LRCK, SCLK, and SD­OUT lines can help reduce coupling of digital sig­nals into the analog.

The capacitor on the FILT pin should be as close to
the CS4228 as possible. See Crystal’s layout Appli­cations Note, and the CDB4228 evaluation board
data sheet for recommended layout of the decou­pling components.

CS4228

DS307PP1 19

REGISTER DESCRIPTION

All registers are read/write except for Chip Status, which is read only. See the following bit definition tables for bit
assignment information. The default bit state after power-up sequence or reset is listed underneath the bit definition
for that field. Default values are also marked with an asterick.

Memory Address Pointer (MAP) - not a register

INCR memory address pointer auto increment control

0 - MAP is not incremented automatically.
*1 - internal MAP is automatically incremented after each read or write.

MAP4:0 Memory address pointer (MAP). Sets the register address that will be read or written by the con-

trol port.

CODEC Clock Mode

Address 0x01

HRM Sets the sample rate mode for the ADCs and DACs

*0 - Base Rate Mode (BRM) supports sample rates up to 50kHz
1 - High Rate Mode (HRM) supports sample rates up to 100 kHz. Typically used for

96 kHz sample rate.

CI1:0 Specifies the ratio of MCLK to the sample rate of the ADCs and DACs (Fs)

76543210

INCR RESERVED MAP4 MAP3 MAP2 MAP1 MAP0

10000001

76543210

HRM RESERVED CI1 CI0 RESERVED

00000100

CI1:0 BRM (Fs) HRM (Fs)

0 128 64
*1 256 128
2384192
3512256

CS4228

20 DS307PP1

Chip Control

Address 0x02

DIGPDN

Power down the digital portions of the CODEC
0 - Digital power down.
*1 - Normal operation

ADCPDN Power down the analog section of the ADC

*0 - Normal
1 - ADC power down.

DACPDN12 Power down the analog section of DAC 1&2

*0 - Normal
1 - Power down DAC 1&2.

DACPDN34 Power down the analog section of DAC 3&4

*0 - Normal
1 - Power down DAC 3&4.

DACPDN56 Power down the analog section of DAC 5&6

*0 - Normal
1 - Power down DAC 5&6.

ADC Control

Address 0x03

MUTL, MUTR ADC left and right channel mute control

*0 - Normal
1 - Selected ADC output muted

HPF ADC DC offset removal. See “High Pass Filter” on page 12 for more information

*0 - Enabled
1 - Disabled

HPFZ ADC DC offset averaging freeze. See “High Pass Filter” on page 12 for more information

*0 - Normal. The DC offset average is dynamically calculated and subtracted from incoming

ADC data.

1 - Freeze. The DC offset average is frozen at the current value and subtracted from

incoming ADC data. Allows passthru of DC information.

7 6543210

DIGPDN RESERVED ADCPDN DACPDN56 DACPDN34 DACPDN12 RESERVED

1 0000000

76543210

MUTL MUTR HPF HPFZ RESERVED

00000000

CS4228

DS307PP1 21

DAC Mute1 Control

Address 0x04

MUT6 - MUT1 Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally

attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenu­tation value returns to the value stored in the corresponding Digital Volume Control register. The
attenuation value is ramped up and down at the rate specified by RMP1:0.
0 - Normal output level
*1 - Selected DAC output fully attenuated.

RMP1:0 Attenuation ramp rate.

*0 - 0.5dB change per 4 LRCKs
1 - 0.5dB change per 8 LRCKs
2 - 0.5dB change per 16 LRCKs
3 - 0.5dB change per 32 LRCKs

DAC Mute2 Control

Address 0x05

MUTEC Controls the MUTEC

pin
*0 - Normal operation
1 - MUTEC

pin asserted low

MUTCZ Automatically asserts the MUTEC

pin on consecutive zeros. When enabled, 512 consecutive

zeros on all six DAC inputs will cause the MUTEC

pin to be asserted low. A single non-zero

value on any DAC input will cause the MUTEC

pin to deassert.
*0 - Disabled
1 - Enabled

HMUTE56/34/12 Hard mute the corresponding DAC pair. When asserted, zero data is sent to the corresponding

DAC pair causing an instantaneous mute. To prevent high frequency transients on the outputs,
a DAC pair should be fully attenuated by asserting the corresponding MUT6-MUT1 bits in the
DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control reg­isters before asserting HMUTE.
*0 - Normal operation
1 - DAC pair is muted

76543210

MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 RMP1 RMP0

11111100

76543210

MUTEC MUTCZ RESERVED HMUTE56 HMUTE34 HMUTE12 RESERVED

00000000

CS4228

22 DS307PP1

DAC De-emphasis Control

Address 0x06

DEMS1:0 Selects the DAC de-emphasis response curve.

0 - Reserved
1 - De-emphasis for 48 kHz
*2 - De-emphasis for 44.1 kHz
3 - De-emphasis for 32 kHz

DEM6 - DEM1 De-emphasis control for DAC6 - DAC1 respectively

*0 - De-emphasis off
1 - De-emphasis on

Digital Volume Control

Addresses 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C

VOL6 - VOL1 Address 0x0C - 0x07 sets the attenuation level for DAC 6 - DAC1 respectively. The attenutation

level is ramped up and down at the rate specified by RMP1:0 in the DAC Volume Control Setup
register.
0 - 181 represents 0 to 90.5 dB of attenuation in 0.5 dB steps.

76543210

DEMS1 DEMS0 DEM6 DEM5 DEM4 DEM3 DEM2 DEM1

10000000

76543210

VOLn

00000000

CS4228

DS307PP1 23

Serial Port Mode

Address 0x0D

DCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)

DMS1:0 Sets the master/slave mode of the serial audio port

*0 - Slave (External LRCLK, SCLK)
1 - Reserved
2 - Reserved
3 - Master (No 48 Fs SCLK in BRM, no 24 Fs SCLK in HRM)

DDF2:0 Serial Port Data Format

0 - Right Justified, 24-bit
1 - Right Justified, 20-bit
2 - Right Justified, 16-bit
3 - Left Justified, maximum 24-bit
*4 - I

2

S compatible, maximum 24-bit
5 - One-line Data Mode, available in BRM only
6 - Reserved
7 - Reserved

Chip Status

Address 0x0E

CLKERR Clocking system status, read only

0 - No Error
1 - No MCLK is present, or a request for clock change is in progress

ADCOVL ADC overflow bit, read only

0 - No overflow
1 - ADC overflow has occurred

76543210

DCK1 DCK0 DMS1 DMS0 RESERVED DDF2 DDF1 DFF0

10000100

DCK1:0 BRM (Fs) HRM (Fs)

0 32 (1) 16 (3)
1 48 (2) 24 (4)
2 *64 32 (1)
3 128 64

Notes: 1. All formats will default to 16 bits

2. External Slave mode only

3. Only valid for left justified and I

2

S modes

4. Only valid for left justified and I

2

S, External Slave mode only

76543210

CLKERR ADCOVL RESERVED

XX000000

CS4228

24 DS307PP1

PIN DESCRIPTION

Serial Audio Data In - SDIN3, SDIN2, SDIN1

Pin 1, 2, 3, Input
Function:

Two’s complement MSB-first serial audio data is input on this pin. The data is clocked into SDIN1, SDIN2,
SDIN3 via the serial clock and the channel is determined by the Left/Right clock. The required relationship
between the Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The op­tions are detailed in Figures 9, 10, 11 and 12.

Serial Audio Data Out - SDOUT

Pin 4, Output
Function:

Two’s complement MSB-first serial data is output on this pin. The data is clocked out of SDOUT via the
serial clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are de­tailed in Figures 9, 10, 11 and 12.

The state of the SDOUT pin during reset is used to set the Control Port Mode (I2C or SPI). When RST

is

low, SDOUT is configured as an input, and the rising edge of RST

latches the state of the pin. A weak
internal pull up is present such that a resistive load less than 47 kΩ will pull the pin low, and the control
port mode is I2C. When the resistive load on SDOUT is greater than 47 kΩ during reset, the control port
mode is SPI.

Serial Audio Data In 3 SDIN3 AOUT6 Analog Output 6
Serial Audio Data In 2 SDIN2 AOUT5 Analog Output 5
Serial Audio Data In 1 SDIN1 AOUT4 Analog Output 4

Serial Audio Data Out SDOUT AOUT3 Analog Output 3

Serial Clock SCLK AOUT2 Analog Output 2

Left/Right Clock LRCK AOUT1 Analog Output 1

Digital Ground DGND AGND Analog Ground

Digital Power VD VA Analog Power

Digital Interface Power VL AINL+ Left Channel Analog Input+

Master Clock MCLK AINL- Left Channel Analog Input-

SCL/CCLK SCL/CCLK FILT Internal Voltage Filter

SDA/CDIN SDA/CDIN AINR- Right Channel Analog Input-

AD0/CS

AD0/CS AINR+ Right Channel Analog Input+

Reset RST

MUTEC Mute Control

1
2
3
4
5
6
7
8
9
10
11
12

5

1
2

6

24
23
22
21
20
19
18
17
16
1514

13

25

26

27

28

CS4228

DS307PP1 25

Serial Clock — SCLK

Pin 5, Bidirectional
Function:

Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins, and out of the SDOUT pin. The pin is an output
in master mode, and an input in slave mode.

In master mode, SCLK is configured as an output. MCLK is divided internally to generate SCLK at the
desired multiple of the sample rate.

In slave mode, SCLK is configured as an input. The serial clock can be provided externally, or the pin can
be grounded and the serial clock derived internally from MCLK.

The required relationship between the Left/Right clock, serial clock and serial audio data is defined by the
Serial Port Mode register. The options are detailed in Figures 9, 10, 11 and 12.

Left/Right Clock — LRCK

Pin 6, Bidirectional
Function:

The Left/Right clock determines which channel is currently being input or output on the serial audio data
output, SDOUT. The frequency of the Left/Right clock must be at the output sample rate, Fs. In Master
mode, LRCK is an output, in Slave Mode, LRCK is an input whose frequency must be equal to Fs and
synchronous to the Master clock.

Audio samples in Left/Right pairs represent simultaneously sampled analog inputs whereas Right/Left
pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock,
serial clock and serial data is defined by the Serial Port Mode register. The options are detailed in Figures
9, 10, 11 and 12.

Digital Ground - DGND

Pin 7, Inputs
Function:

Digital ground reference.

Digital Power - VD

Pin 8, Input
Function:

Digital power supply. Typically 3.3 VDC.

Digital Interface Power - VL

Pin 9, Input
Function:

Digital interface power supply. Typically 3.3 or 5.0 VDC. All digital output voltages and input thresholds
scale with VL.

CS4228

26 DS307PP1

Master Clock - MCLK

Pin 10, Input
Function:

The master clock frequency must be either 128x, 256x, 384x or 512x the input sample rate in Base Rate
Mode (BRM) and either 64x, 128x, 192x, or 256x the input sample rate in High Rate Mode (HRM). Table
2 illustrates several standard audio sample rates and the required master clock frequencies. The
MCLK/Fs ration is set by the CI1:0 bits in the CODEC Clock Mode register

Serial Control Interface Clock - SCL/CCLK

Pin 11, Input
Function:

Clocks serial control data into or out of SDA/CDIN.

Serial Control Data I/O - SDA/CDIN

Pin 12, Bidirectional/Input
Function:

In I2C mode, SDA is a bidirectional control port data line. A pull up resistor must be provided for proper
open drain output operation. In SPI mode, CDIN is the control port data input line. The state of the SDOUT
pin during reset is used to set the control port mode.

Address Bit 0 / Chip Select - ADO/CS

Pin 13, Input
Function:

In I2C mode, AD0 is the LSB of the chip address. In SPI mode, CS is used as a enable for the control port
interface.

Reset - RST

Pin 14, Input
Function:

When low, the device enters a low power mode and all internal registers are reset to the default settings,
including the control port. The control port can not be accessed when reset is low.

When high, the control port and the CODEC become operational.

Sample

Rate

(kHz)

MCLK (MHz)

HRM BRM

64x 128x 192x 256x 128x 256x 384x 512x

32----4.09608.192012.288016.3840

44.1----5.644811.289616.934422.5792
48----6.144012.288018.432024.5760
64 4.0960 8.1920 12.2880 16.3840 - - - -

88.2 5.6448 11.2896 16.9344 22.5792 - - - ­96 6.1440 12.2880 18.4320 24.5760 - - - -

Table 2. Common Master Clock Frequencies

CS4228

DS307PP1 27

Mute Control - MUTEC

Pin 15, Output
Function:

The Mute Control pin goes low during the following conditions: power-up initialization, power-down, reset,
no master clock present, or if the master clock to left/right clock frequency ratio is incorrect. The Mute Con­trol pin can also be user controlled by the MUTEC bit in the DAC Mute2 Control register. Mute Control can
be automatically asserted when 512 consecutive zeros are detected on all six DAC inputs, and automat­ically deasserted when a single non-zero value is sent to any of the six DACs. The mute on zero function
is controlled by the MUTCZ bit in the DAC Mute2 Control register. The MUTEC

pin is intended to be used
as a control for an external mute circuit to achieve a very low noise floor during periods when no audio is
present on the DAC outputs, and to prevent the clicks and pops that can occur in any single supply sys­tem. Use of the Mute Control pin is not mandatory but recommended.

Differential Analog Inputs — AINR+, AINR- and AINL+, AINL-

Pins 16, 17 and 19, 20, Inputs
Function:

The analog signal inputs are presented deferentially to the modulators via the AINR+/- and AINL+/- pins.

The + and - input signals are 180° out of phase resulting in a nominal differential input voltage of twice the
input pin voltage. These pins are biased to the internal reference voltage of approximately 2.3 V. A pas­sive anti-aliasing filter is required for best performance, as shown in Figure 5. The inputs can be driven at

-1dB FS single-ended if the unused input is connected to ground through a large value capacitor. A single
ended to differential converter circuit can also be used for slightly better performance.

Internal Voltage Filter - FILT

Pin 18, Output
Function:

Filter for internal circuits. An external capacitor is required from FILT to analog ground, as shown in Figure

5. FILT is not intended to supply external current. FILT+ has a typical source impedance of 250 kΩ and
any current drawn from this pin will alter device performance. Care should be taken during board layout
to keep dynamic signal traces away from this pin.

Analog Power - VA

Pin 21, Input
Function:

Power for the analog and reference circuits. Typically 5.0 VDC.

Analog Ground - AGND

Pin 22, Input
Function:

Analog ground reference.

Analog Output - AOUT1, AOUT2, AOUT3, AOUT4, AOUT5 and AOUT6

Pins 23, 24, 25, 26, 27, 28, Outputs
Function:

Analog outputs from the DACs. The full scale analog output level is specified in the Analog Characteristics
specifications table. The amplitude of the outputs is controlled by the Digital Volume Control registers
VOL6 - VOL1.

CS4228

28 DS307PP1

PARAMETER DEFINITIONS

Dynamic Range

The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral
components over the specified bandwidth. Dynamic range is a signal-to-noise measurement
over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting
measurement to refer the measurement to full scale. This technique ensures that the distortion
components are below the noise level and do not effect the measurement. This measurement
technique has been accepted by the Audio Engineering Society, AES17-1991, and the
Electronic Industries Association of Japan, EIAJ CP-307.

Total Harmonic Distortion + Noise

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over
the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components.
Expressed in decibels. ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A.

Idle Channel Noise / Signal-to-Noise-Ratio

The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog
output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz
bandwidth. Units in decibels. This specification has been standardized by the Audio
Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has
also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and
referred to as Signal-to-Noise-Ratio.

Total Harmonic Distortion (THD)

THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of
the test signal. Units in decibels.

Interchannel Isolation

A measure of crosstalk between channels. Measured for each channel at the converter’s output with
no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Frequency Response

A measure of the amplitude response variation from 20Hz to 20 kHz relative to the amplitude
response at 1 kHz. Units in decibels.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units are in decibels.

Gain Error

The deviation from the nominal full scale output for a full scale input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid­scale input code. Units are in volts.

CS4228

DS307PP1 29

PACKAGE DIMENSIONS

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN MAX MIN MAX

A -- 0.084 -- 2.13
A1 0.002 0.010 0.05 0.25
A2 0.064 0.074 1.62 1.88

b 0.009 0.015 0.22 0.38 2,3

D 0.390 0.413 9.90 10.50 1
E 0.291 0.323 7.40 8.20

E1 0.197 0.220 5.00 5.60 1

e 0.022 0.030 0.55 0.75

L 0.025 0.041 0.63 1.03

∝ 0° 8° 0° 8°

28L SSOP PACKAGE DRAWING

E

N

1

23

e

b

2

A1

A2

A

D

SEATING

PLANE

E1

1

L

SIDE VIEW

END VIEW

TOP VIEW