l Stereo 20-bit A/D Converters
l Six 20-bit D/A Converters
l 108 dB DAC Signal-to-Noise Ratio (EIAJ)
l Mono 20-bit A/D Converter
l Programmable Input Gain & Output
Attenuation
l On-chip Anti-aliasing and Output Smoothing
Filters
l De-emphasis for 32 kHz, 44.1 kHz, 48 kHz
I
PDN
LRCK
SCLK
SDIN1
SDIN2
SDIN3
SDOUT1
SDOUT2
OVL
DEM
SCL/CCLK
DEM
CLKOUT XTI XTO
Serial Audio Data Interface
Clock Osc/
SDA/CDOUT
Control Port
MUX
Divider
AD1/CDIN AD0/CS SPI/I2C
DAC#1
DAC#2
DAC#3
DAC#4
Digital Filters
DAC#5
DAC#6
Mono
ADC
Left
ADC
Digital Filters
HOLD
Right
ADC
DATAUX
Description
The CS4227 is a si ng le- c hi p codec providing st ereo analog-to-digital and six digital-to-anal og converters us ing
delta-sigma conversion techniques. This +5 V device
also contains volume controls that are independently selectable for each of the six D/A chan nels. Applications
include Dolby
3™ home theater syste ms, DSP based car audio sy stems, and other multi-channel applications.
ORDERING INFORMATION
CS4227-KQ-10° to +70° C 44-pin TQFP
CS4227-BQ-40° to +85° C 44-pin TQFP
CDB4227Evaluation Board
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Dolby is a registered trademark of Dolby Labratories Licensing Corporation.
Pro Logic, and AC-3 are trademarks of Dolby Labratories Licensing Corporation.
THX is a registered trademark of LucasArts Entertainment Company.
Preliminary product info rmation describes products which are i n p r od ucti on, b ut for which full characteriza ti on da t a i s not yet available. Advance produ ct i nf or -
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logic websi t e or di sk may be pri nted for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2DS281PP2
2.11 Power Supply, Layout, and Grounding .......................................................................... 19
2.12 ADC and DAC Filter Response Plots ............................................................................ 20
Interchannel Isolation-90--90-dB
Interchannel Gain Mismatch-0.1--0.1-dB
Programmable Input Gain Span89108910dB
Gain Step Size2.733.32.733.3dB
Offset Error (with high pass filter)--0--0LSB
Full Scale Input Voltage (Single Ended):0.901.01.100.901.01.10Vrms
Gain Drift-100--100-
Notes: 1. Referenced to typical full-scale differential input voltage (2Vrms).
2. Input resistance is for the input selected. Non-selected inputs have a very high (>1MΩ) input resistance.
The input resistance will vary with gain value selected, but will always be greater than the min. value
specified.
3. Filter characteristics scale with output sample rate.
4. The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (n x 5.6448 MHz ±20.0 kHz
where n = 0,1,2,3...).
5. Group delay for Fs = 44.1 kHz, t
4DS281PP2
= 15/44.1 kHz = 340 µs
gd
CS4227
ANALOG CHARACTERISTICS (Continued)
CS4227-KQCS4227-BQ
ParameterSymbol
High Pass Filter Characteristics
Frequency Response:-3 dB(Note 3)
-0.13 dB
Phase Deviation @ 20 Hz(Note 3)-10--10-Deg.
Passband Ripple--0--0dB
Analog Output Characteristics
DAC Resolution16-2016-20Bits
Signal-to-Noise/Idle (DAC muted, A weighted)
Channel Noise
Dynamic Range(DAC not muted, A weighted)
(DAC not muted, unweighted)
Total Harmonic DistortionTHD-0.003--0.003-%
Total Harmonic Distortion + Noise(Stereo) THD+N--88-83--86-81dB
Interchannel Isolation-90--90-dB
Interchannel Gain Mismatch-0.1--0.1-dB
Attenuation Step Size(All Outputs)0.711.30.711.3dB
Programmable Output Attenuation Span-84-86--84-86-dB
Offset Voltage(relative to CMOUT)-±15--±15-mV
Full Scale Output Voltage0.921.01.080.921.01.08Vrms
Gain Drift-100--1 00-
Out-of-Band Energy(Fs/2 to 2Fs)--60---60-dBFs
Analog Output LoadResistance:
Combined Digital and Analog Filter Characteristics
Frequency Response 10 Hz to 20 kHz-±0.1--±0.1-dB
Deviation from Linear Phase-±0.5--±0.5-Deg.
Passband: to 0.01 dB corner(Notes 6, 7)0-20.00-20.0kHz
Passband Ripple(Note 7)--±0.01--±0.01dB
Stopband(Notes 6 ,7)24.1--24.1--kHz
Stopband Attenuation(Note 8)70--70--dB
Group Delay (Fs = Input Word Rate)(Note 5)tgd-16/Fs--16/Fs-s
Analog Loopback Performance
Signal-to-noise Ratio (CCIR-2K weighted, -20 dB input)
CCIR-2K
-71- -71-dB
Power Supply
Power Supply CurrentOperating
Power Down
Power Supply Rejection(1 kHz, 10 mV
Notes: 6. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,
the 0.05 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs.
7. Digital filter characteristics.
8. Measurement bandwidth is 10 H z to 3Fs.
Specifications are subject to change without notice
)-45--45-dB
rms
-
-
901113
3
-
9011153mA
-
-
-
-
-
-
UnitsMinTypMaxMinTypMax
Hz
Hz
dB
dB
ppm/°C
Ω
k
pF
mA
DS281PP25
CS4227
1
384
()
Fs
---------------------20+
SWITCHING CHARACTERISTICS (T
= 25 °C; VA+, VD+ = +5 V ±5%; outputs loaded with 30 pF.)
Low Time(Note 11)
SCLK Falling Edge to SDOUT Output ValidDSCK = 0t
LRCK edge to MSB validt
SDIN Setup Time Before SCLK Rising EdgeDSCK = 0t
SDIN Hold Time After SCLK Rising EdgeDSCK = 0t
SCLK Periodt
SCLK High Timet
SCLK Low Timet
SCLK Rising to LRCK EdgeDSCK = 0t
LRCK Edge to SCLK RisingDSCK = 0t
sckw
sckh
sckl
lrckd
lrcks
Note 13--ns
40--ns
40--ns
20--ns
40--ns
Notes: 9. CLKOUT Jitter is for 256x Fs selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384x Fs and 512x Fs as selected output frequency.
10. For CLKOUT frequency equal to 1x Fs, 384x Fs, and 512x Fs. See Master Clock Output section.
11. After powering up the CS4227, PDN
should be held low for 1 ms to allow the power supply to settle.
12.
13.
14.
1
---------------------
()
128
Fs
1
-------------------
256()
Fs
6DS281PP2
SCLK*
SCLKAUX*
(output)
LRCK
LRCKAUX
(output)
SDOUT1
SDOUT2
Figure 1. Audio Ports Master Mode Timing
LRCK
LRCKAUX
(input)
t
lrckd
t
lrcks
t
sckh
t
mslr
t
sckl
CS4227
SCLK*
SCLKAUX*
(input)
SDIN1
SDIN2
SDIN3
DATAUX
SDOUT1
SDOUT2
*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0.
SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.
t
lrpd
t
ds
MSB
t
sckw
t
dh
t
dpd
MSB-1
Figure 2. Audio Ports Slave Mode and Data I/O Timing
DS281PP27
CS4227
SWITCHING CHARACTERISTICS - CONTROL PORT (T
Inputs: logic 0 = DGND, logic 1 = VD+; C
= 30 pF)
L
= 25 °C; VA +, VD+ = +5 V ± 5 %;
A
ParameterSymbolMinMaxUnit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequencyf
CS
High Time Between Transmissions
CS
Falling to CCLK Edge
CCLK Low Timet
CCLK High Timet
CDIN to CCL Rising Setup Timet
CCLK Rising to DATA Hold Time(Note 15)t
CCLK Falling to CDOUT stablet
Rise Time of CDOUTt
Fall Time of CDOUTt
Rise Time of CCLK and CDIN(Note 16)t
Fall Time of CCLK and CDIN(Note 16)t
t
t
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
-6MHz
1.0-µs
20-ns
66-ns
66-ns
40-ns
15-ns
-45ns
-25ns
-25ns
-100ns
-100ns
Notes: 15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For F
< 1 MHz.
SCK
CS
CCLK
CDIN
CDOUT
t
css
t
r2
t
t
scl
sch
t
f2
t
t
dsu
dh
Figure 3. Control Port SPI Mode
t
csh
t
pd
8DS281PP2
CS4227
SWITCHING CHARACTERISTICS - CONTROL PORT (T
Inputs: logic 0 = DGND, logic 1 = VD+; C
ParameterSymbolMinMaxUnit
I2C® Mode (SPI/I2C = 1)(Note 17)
SCL Clock Frequencyf
Bus Free Time Between Transmissionst
Start Condition Hold Time (prior to first clock pulse)t
Clock Low Timet
Clock High Timet
Setup Time for Repeated Start Conditiont
SDA Hold Time for SCL Falling(Note 18)t
SDA Setup Time to SCL Risingt
Rise Time of Both SDA and SCL Linest
Fall Time of Both SDA and SCL Linest
Setup Time for Stop Conditiont
2C®
Notes: 17. I
is a registered trademark of Philips Semiconductors.
18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
StopStart
= 30 pF)
L
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
Repeated
Start
= 25 °C; VA+, VD+ = +5 V ± 5 %;
A
-100kHz
4.7-µs
4.0-µs
4.7-µs
4.0-µs
4.7-µs
0-µs
250-ns
-1µs
-300ns
4.7-µs
Stop
SDA
SCL
t
buf
t
hdst
t
low
t
high
t
hdd
t
sud
t
sust
t
hdst
t
f
t
r
t
susp
Figure 4. Control Port I2C Mode
DS281PP29
CS4227
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltage with respect to 0 V.)
ParameterSymbolMinMaxUnit
Power SuppliesDigital
Analog
Input Current(Note 19)-±10mA
Analog Input Voltage(Note 20)-0.7(VA+) + 0.7V
Digital Input Voltage(Note 20)-0.7(VD+) + 0.7V
Ambient Temperature(Power Applied)-55+125°C
Storage Temperature-65+150°C
Notes: 19. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
20. The maximum over or under voltage is limited by the input current.
WARNING: WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltage with respect to
0 V.)
VD+
VA+
-0.3
-0.3
6.0
6.0
V
ParameterSymbol Min TypMaxUnit
Power SuppliesDigital
|VA+ - VD+| < 0.4 VAnalog
Operating Ambient TemperatureT
DIGITAL CHARACTERISTICS (T
ParameterSymbolMinMaxUnit
High-level Input Voltage(Except XTI)V
Low-level Input Voltage(Except XTI)V
High-level Output Voltage(Except XTO)V
Low-level Out put Voltage(Except XTO)V
Input Leakage Current(Digital Inputs)-10µA
Output Leakage Current(High-Impedance Digital Outputs)-10µA
= 25 °C; VA+, VD+ = +5 V ±5%)
A
VD+
VA+
A
IH
IL
OH
OL
4.75
4.75
-102570°C
2.8(VD+) + 0.3V
-0.30.8V
(VD+) - 1.0-V
5.0
5.0
-0.4V
5.25
5.25
V
10DS281PP2
CS4227
+5V
Supply
To Optional
Input and
Output Buffers
From Optional Input Buffer
Digital
Audio
Source
Ferrite Bead
1
F
µ
10 µF
10 µF
10 µF
10 µF
10 µF
µ
10
10 µF
R
R
1 µF0.1 µF
+
+
*
*
*
*
*
F
*
*
S
S
16
14
13
11
12
10
9
15
27
2
1
44
43
2.0
Ω
+
19
VA+VD+
CMOUT
AIN1L
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
AINAUX
DEM
HOLD
DATAUX
LRCKAUX
SCLKAUX
1 µF0.1 µF
CS4227
40
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
21
ANALOG
FILTER
22
ANALOG
FILTER
23
ANALOG
FILTER
24
ANALOG
FILTER
25
ANALOG
FILTER
26
ANALOG
FILTER
3
4
6
5
Microcontroller
8
Mode
Setting
R = 50
Ω
S
All unused digital inputs
should be tied to 0V.
Unused analog inputs
should be left unconnected.
* Optional if analog inputs biased
to within 1% of CMOUT
PDN
7
SPI/I2C
AGND1, 2 DGND1, 2NCXTOXTI
39412018
17
2928
SDIN1
SDIN2
SDIN3
SDOUT1
SDOUT2
LRCK
SCLK
CLKOUT
OVL
C1**C2**
34
33
32
36
35
37
38
31
30
External
Clock Input
Audio
R
R
DSP
S
S
Figure 5. Recommended Connection Diagram
(Also see recommended layout diagrams, Figure 14)
DS281PP211
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