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CS4224-KS
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Cirrus Logic CS4224-KS, CS4224-BS, CS4223-KS, CDB4224, CDB4223 Datasheet

( )
CS4223 CS4224
24-Bit 105 dB Audio Codec with Volume Control

Features

l 105 dB Dynamic Range A/D Converters l 105 dB Dynamic Range D/A Converters l 110 dB DAC Signal-to-Noise Ratio (EIAJ) l Analog Volume Control (CS4224 only) l Differential Inputs / Outputs l On-chip Anti-aliasing and Output Smoothing
Filters
l De-emphasis for 32, 44.1 and 48 kHz l Supports Master and Slave Modes l Single +5 V powe r supp l y l On-Chip Crystal Oscillator l 3 - 5 V Digital Interface
I

Description

The CS4223/4 is a hig hly integ rated , high p erforma nce, 24-bit, audio codec providing stereo analog-to-digital and stereo digital-to -analog converters using del ta-sig­ma conversion te chniques. The de vice opera tes from a single +5 V power supply, and features low power con­sumption. Selectable de-emphasis filter for 32, 44.1, and 48 kHz sample rates is also included.
The CS4224 includes an analog volume control capable of 113.5 dB attenuation in 0.5 dB steps. The analog vol­ume control architecture preserves dynamic range during attenuation. V olume control changes are i mple-
mented using a “soft” ramping or zero crossing technique.
Applications include digital effects processors, DAT, and multitrack recorders.
ORDERING INFORMATION
CS4223-KS -10 to +70 °C 28-pin SSOP CS4223-BS -40 to +85 °C 28-pin SSOP CS4224-KS -10 to +70 °C 28-pin SSOP CS4224-BS -40 to +85 °C 28-pin SSOP CDB4223/4 Evaluation Board
(
)(
DIF1
SCL/CCLK SDA/CDIN AD0/CS MCLK VD VA
RST
LRCK
SCLK
SDIN
SDOUT
Serial Audio Data Interface
Preliminary Product Information
)(
DIF0
Control Port
Digital Filters
with De-Emphasis
Digital Filters
Clock OSC
XTI XTO
DEM0
= CS4223
)
Left
DAC
Right
DAC
Left
ADC
Right
ADC
(
DEM1
2
I C/SPI
)
*
Volume
Control
Volume
Control
= CS4224
V
L
DGND
*
*
Voltage
Reference
Analog Low Pass
AGND
AOUTL+ AOUTL-
AOUTR+
and Output Stage
AOUTR-
AINL­AINL+
AINR­AINR+
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
APR ‘00
DS290PP3
1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS...........................................................4
ANALOG CHARACTERISTICS..........................................................................4
SWITCHING CHARACTERISTICS .................................... ....... ...... ....... ...... ......6
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE................7
SWITCHING CHARACTERISTICS - CONTROL PORT - I
ABSOLUTE MAXIMUM RATINGS.....................................................................9
RECOMMENDED OPERATING CONDITIONS.................................................9
DIGITAL CHARACTERISTICS...........................................................................9
2. TYPICAL CONNECTION DIAGRAM — CS4223......................................................10
3. TYPICAL CONNECTION DIAGRAM — CS4224......................................................11
3.1 Overview ..........................................................................................................12
3.2 Analog Inputs ...................................................................................................12
3.2.1 Line Level Inputs ...................................................................................12
3.2.2 Input Level Monitoring (CS4224 only) ...................................................12
3.2.3 High Pass Filter .....................................................................................12
3.3 Analog Outputs ................................................................................................14
3.3.1 Line Level Outputs .................................................................................14
3.3.2 Analog/Digital Volume Control (CS4224 only) .......................................14
3.3.3 Soft Mute/Mute on Zero Input Data (CS4224 only) ...............................16
3.4 Master Clock Generation .................................................................................16
3.5 Master vs. Slave Mode ....................................................................................16
3.6 Serial Audio Data Interface ..............................................................................17
3.6.1 Serial Audio Interface Signals ................................................................17
3.6.2 Serial Audio Interface Formats ..............................................................17
3.7 Control Port Interface (CS4224 only) ...............................................................17
3.7.1 SPI Mode ...............................................................................................18
3.7.2 I
3.7.3 Control Port Bit Definitions .....................................................................19
3.8 De-Emphasis ...................................................................................................19
3.9 Power-up / Reset / Power Down / Calibration .................................................19
3.10 Power Supply, Layout and Grounding .............................................................19
3.11 ADC and DAC Filter Response Plots ..............................................................21
4. REGISTER DESCRIPTIONS.....................................................................................22
Memory Address Pointer (MAP).......................................................................22
Reserved Byte (0).............................................................................................22
ADC Control Byte (1)........................................................................................22
2
CS4223 CS4224
2
C MODE................8
C Mode ...............................................................................................18
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I2C is a registered trademark of Ph ilips Semiconductor. SPI is a registered trademark of International Business Machines Corporation.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor­mation describes pr oducts which are in development and subj ect t o devel opment changes. Ci rrus Logic, Inc. has made best efforts to e nsure that the infor­mation contained i n this document is accurate and reli able. However, the information i s subject to chang e without notice an d is provided “AS IS” without
warranty of any kind (ex p res s or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this in for mation, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reprod uced, stor ed i n a retr i eval system, or transmitted, in any form or by any means (electronic, mechanical, pho­tographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (elec­tronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of an y item s witho ut the pri o r wr it ten consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in so me ju ris diction s. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS290PP3
CS4223 CS4224
DAC Control Byte (2)........................................................................................ 23
Output Attenuator Data Byte (3, 4)................................................................... 23
DSP Port Mode Byte (5)...................................................................................24
Converter Status Report Byte (Read Only) (6).................................................24
Clock/Output Control Byte (7) .......................................................................... 25
5. PIN DESCRIPTIONS — CS4223............................................................................... 26
Power Supply ................................................................................................... 26
Analog Inputs ...................................................................................................27
Analog Outputs................................................................................................. 27
Digital Inputs..................................................................................................... 27
Digital Outputs..................................................................................................28
Miscellaneous Pins....................... ...... ....... ...................................... ....... ...... .... 28
6. PIN DESCRIPTIONS — CS4224............................................................................... 29
Power Supply ................................................................................................... 29
Analog Inputs ...................................................................................................30
Analog Outputs................................................................................................. 30
Digital Inputs..................................................................................................... 30
Digital Outputs..................................................................................................31
Control Port Signals .........................................................................................31
Miscellaneous Pins....................... ...... ....... ...................................... ....... ...... .... 32
7. PARAMETER DEFINITIONS..................................................................................... 33
8. PACKAGE DIMENSIONS ......................................................................................... 34

LIST OF FIGURES

Figure 1. Serial Audio Port Data I/O Timing .....................................................................6
Figure 2. SPI Control Port Timing .....................................................................................7
Figure 3. I
Figure 4. CS4223 Recommended Connection Diagram ................................................10
Figure 5. CS4224 Recommended Connection Diagram ................................................11
Figure 6. Optional Line Input Buffer ................................................................................13
Figure 7. Single-ended Input Application ........................................................................13
Figure 8. Full Scale Input/Output Voltage .......................................................................14
Figure 9. Hybrid Analog/Digital Attenuation ......................... ....................................... ....15
Figure 10. 2- and 3-Pole Butterworth Filters ...................................................................15
Figure 11. Audio DSP Data Input Formats. ....................................................................17
Figure 12. Control Port Timing, SPI mode ......................................................................18
Figure 13. Control Port Timing, I
Figure 14. De-emphasis Curve. ......................................................................................19
Figure 15. Suggested Layout Guideline (See CDB4223/4 Data Sheet) .........................20
Figure 16. ADC Filter Response .....................................................................................21
Figure 17. ADC Passband Ripplee .................................................................................21
Figure 18. ADC Transition Band .....................................................................................21
Figure 19. DAC Filter Response .....................................................................................21
Figure 20. DAC Passband Ripple ...................................................................................21
Figure 21. DAC Transition Band .....................................................................................21
2

LIST OF TABLES

C Control Port Timing .....................................................................................8
2
C mode ......................................................................18
Table 1. CS4224 vs. CS4223 ...........................................................................................12
Table 2. High Pass Filter Characteristics .........................................................................14
Table 4. Master Mode vs. Slave Mode Clocking. .............................................................16
Table 3. Common Clock Frequencies ..............................................................................16
Table 5. CS4223 De-Emphasis filter control ....................................................................19
DS290PP3 3

1. CHARACTERISTICS AND SPECIFICATIONS

CS4223 CS4224

ANALOG CHARACTERISTICS (T

Fs = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figures 4 and 5; SPI mode, Format 0, unless otherwise specified.)
Parameter Symbol
= 25° C; VA, VD = +5 V; Full Scale Input Sine wave, 997 Hz;
A
CS4223/4 - KS CS4223/4 - BS
UnitMin Typ Max Min Typ Max
Analog Input Characteristics
ADC Resolution --24--24Bits Total Harmonic Distortion THD - 0.0014 - - 0.0014 - % Dynamic Range A-weight ed
unweighted Total Harmonic Distortion + Noise (Note 1) THD+N - -97 -92 - -97 -87 dB Interchannel Isolation (1 kHz) - 90 - - 90 - dB Interchannel Gain Mismatch - - 0.1 - - 0.1 dB Offset Error with High Pass Filter - - 0 - - 0 LSB Full Scale Input Voltage (Differential) 1.9 2.0 2.1 1.9 2.0 2.1 Vrms Gain Drift - 100 - - 100 - ppm/°C Input Resistance 10 - - 10 - - kΩ Input Capacitance - - 15 - - 15 pF Common Mode Input Voltage - 2.3 - - 2.3 - V
10097105
102
-
-
95 92
105 102
-
-
dB dB
A/D Decimation Filter Characteristics
Passband (Note 2) 0 - 21.8 0 - 21.8 kHz Passband Ripple - - ±0.01 - - ±0.01 dB Stopband (Note 2) 30 - 6114 30 - 6114 kHz Stopband Attenuation (Note 3) 80 - - 80 - - dB Group Delay (Fs = Output Sampl e Rate)
(Note 4)
Group Delay Variation vs. Frequency ∆t
t
gd
gd
-15/Fs- -15/Fs- s
--0--0µs
High Pass Filter Characteristics
Frequency Response -3 dB (Note 2)
-0.1 dB Phase Deviation @ 20 Hz (Note 2) - 10 - - 10 - Degree Passband Ripple - - 0 - - 0 dB
-
-
3.7 20
-
-
-
-
3.7 20
-
-
Hz Hz
Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms).
2. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the
0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.
3. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...).
4. Group delay for Fs = 48 kHz, t
4 DS290PP3
= 15/48 kHz = 312 µs.
gd
CS4223 CS4224
ANALOG CHARACTERISTICS (CONTINUED)
CS4223/4 - KS CS4223/4 - BS
Parameter Symbol
Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified.
DAC Resolution - - 24 - - 24 Bits Signal-to-Noise, Idle-Channel Noise
(CS4224 only) DAC muted, A-weighted Dynamic Range DAC not muted, A-weighted
DAC not muted, unweighted Total Harmonic Distortion THD - 0.0014 - - 0.0014 - % Total Harmonic Distortion + Noise THD+N - -97 -92 - -97 -87 dB Interchannel Isolation (1 kHz) - 90 - - 90 - dB Interchannel Gain Mismatch - - 0.1 - - 0.1 dB Attenuation Step Size All Outputs 0.35 0.5 0.65 0.35 0.5 0.65 dB Programmable Output Attenuation Span 110 113.5 - 110 113.5 - dB Differential Offset Voltage - ±10 - - ±10 - mV
Common Mode Output Voltage - 2.4 - - 2.4 - V Full Scale Output Voltage 1.8 1.9 2.0 1.8 1.9 2.0 Vrms Gain Drift - 100 - - 100 - ppm/°
Out-of-Band Energy Fs/2 to 2 Fs - -60 - - -60 - dBFs Analog Output Load Resistance
Capacitance
102 110 - 97 110 - dB
100
97
10
-
105 102
-
-
-
-
-
100
95 92
10
105 102
-
-
-
100
Combined Digital and Analog Filter Characteristics
Frequency Response10 Hz to 20 kHz - ±0.1 - - ±0.1 - dB Deviation from Linear Phase - ±0.5 - - ±0.5 - Degree Passband: to 0.01 dB corner (Notes 5 and 6) 0 - 21.8 0 - 21.8 kHz Passband Ripple (Note 6) - - ±0.01 - - ±0.01 dB Stopband (Notes 5 and 6) 26.2 - - 26.2 - - kHz Stopband Attenuation (Note 7) 70 - - 70 - - dB Group Delay (Fs = Input Word Rate) t
gd
-16/Fs- -16/Fs- s
Power Supply
Power Supply Current VA
VD
VL
Total Power Down
Power Supply Rejection Ratio 1 kHz - 65 - - 65 - dB
-
-
-
-
46
9 3
0.4
60 20
5
-
-
-
-
-
46
9 3
0.4
60 20
UnitMin Typ Max Min Typ Max
-
-
-
5
-
dB dB
C
kΩ pF
mA mA mA mA
Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 48 kHz,
the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.5465x Fs.
6. Digital filter characteristics.
7. Measurement bandwidth is 10 Hz to 3 Fs.
DS290PP3 5
CS4223 CS4224
DIGITAL CHARACTERISTICS (T
= 25° C; VA, VD = 4.75V - 5.25V)
A
Parameter Symbol Min Max Unit
High-level Input Voltage VL = 5V
VL = 3V Low-level Input Voltage V High-level Output Voltage at I
Low-level Output Voltage at I
= -2.0 mA V
O
= 2.0 mA V
O
V
IH
V
IH IL
OH OL
2.8
2.0
VL + 0.3 VL + 0.3
-0.3 0.8 V
VL - 1.0 - V
-0.5V
Input Leakage Current Digital Inputs - 10 µA Output Leakage Current High Impedance Digital Outputs - 10 µA

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)

Parameter Symbol Min Max Unit
Power Supplies Digital
Analog Input Current (Note 8) - ±10 mA Analog Input Voltage (Note 9) -0.7 VA + 0.7 V Digital Input Voltage (Note 9) -0.7 VD + 0.7 V Ambient Temperature Power Applied -55 +125 °C Storage Temperature -65 +150 °C
VD
VA
-0.3
-0.3
6.0
6.0
V V
V V

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0 V, all voltages with respect to 0 V.)
Parameter Symbol Min Typ Max Unit
Power Supplies Digital
Analog
Digital
| VA - VD |
Ambient Operating Temperature Commercial (KS)
Industrial (BS)
Notes: 8. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR
latch-up .
9. The maximum over or under voltage is limited by the input current.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
VD
VA VL
T
T
AC
AI
4.75
4.75
2.7
-
-10
-40
5.0
5.0
5.0
-
25 25
5.25
5.25
5.25
0.4 70
85
V V V V
°C °C
6 DS290PP3
CS4223 CS4224

SWITCHING CHARACTERISTICS (T

= 25° C; VA, VD = 4.75 V - 5.25 V; outputs loaded with
A
30 pF)
Parameter Symbol Min Typ Max Unit
Audio ADC’s and DAC’s Sample Rate Fs 4 - 50 kHz XTI Frequency XTI = 256, 384, or 512 Fs 1.024 - 26 MHz XTI Pulse Width High XTI = 512 Fs
XTI = 384 Fs XTI = 256 Fs
XTI Pulse Width Low XTI = 512 Fs
XTI = 384 Fs XTI = 256 Fs
13 21 31
13 21 31
-
-
-
-
-
-
-
-
-
-
-
-
ns ns ns
ns ns ns
XTI Jitter Tolerance - 500 - psRMS
Low Time (Note 10) 10 - - ms
RST
1
SCLK falling edge to SDOUT output valid DSCK = 0 t LRCK edge to MSB valid t SDIN setup time before SCLK rising edge DSCK = 0 t SDIN hold time after SCLK rising edge DSCK = 0 t SCLK Period t SCLK High Time t SCLK Low Time t SCLK rising to LRCK edge DSCK = 0 t LRCK edge to SCLK rising DSCK = 0 t
dpd lrpd
ds
dh sckw sckh
sckl lrckd lrcks
-- ns
- - 45 ns 25 - - ns 25 - - ns
1
------------------- --­(128) Fs
40 - - ns 40 - - ns 35 - - ns 40 - - ns
------------------- ---20+ (384) Fs
--ns
Notes: 10. After powering up the CS4223/4, PDN should be held low for 10 ms to allow the power supply to settle.
LRCK
t
lrckd
SCLK*
SDIN
SDOUT
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
t
lrpd
t
lrcks
t
sckh
t
ds
t
dh
MSB MSB-1
t
sckw
t
sckl
t
dpd

Figure 1. Serial Audio Port Data I/O Timing

DS290PP3 7
CS4223 CS4224

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224)

(TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)
Parameter Symbol Min Max Unit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency f
rising edge to CS falling (Note 11) t
RST CCLK edge to CS
High Time between transmissions t
CS
falling to CCLK edge t
CS
falling (Note 12) t
CCLK Low Time t CCLK High Time t CDIN to CCLK rising setup time t CCLK rising to DATA hold time (Note 13) t Rise time of CCLK and CDIN (Note 14) t Fall time of CCLK and CDIN (Note 14) t
Notes: 11. Not tested but guaranteed by design .
12. t
only needed before first falling edge of CS after RST rising edge. t
spi
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
< 1 MHz.
SCK
sck srs
spi csh css
scl
sch dsu
dh
r2 f2
-6MHz
41 - µs
500 - ns
1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns
-100ns
-100ns
= 0 at all other times.
spi
RST
CS
CCLK
CDIN
t
srs
t
t
css
spi
tr2t
t
t
scl
t
f2
dsu
sch
t
dh
t
csh

Figure 2. SPI Control Port Timing

8 DS290PP3
CS4223 CS4224

SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE (CS4224)

(TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)
Parameter Symbol Min Max Unit
I2C® Mode (SPI/I2C = 1)
SCL Clock Frequency f
rising edge to Start (Note 15)
RST
Bus Free Time between transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low Time t Clock High Time t Setup time for repeated Start Condition t SDA hold time for SCL falling (Note 16) t SDA setup time to SCL rising t Rise time of SCL t Fall time of SCL t Rise time of SDA t Fall time of SDA t Setup time for Stop Condition t
scl
t
irs
buf
hdst
low high sust
hdd
sud
rc
fc rd fd
susp
-100kHz
50 - µs
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs 0-µs
250 - ns
-25ns
-25ns
-1µs
-300ns
4.7 - µs
Notes: 15. Not tested but guaranteed by design .
16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
irs
Stop Start
SDA
SCL
t
buf
t
t
hdst
low
t
hdd
t
high
t
sud
Repeated
Start
t
sust
t
hdst
t
rd
t
fc
t
rc
Stop
t
fd
t
susp

Figure 3. I2C Control Port Timing

DS290PP3 9

2. TYPICAL CONNECTION DIAGRAM — CS4223

CS4223 CS4224
+5V
Supply
Ferrite Bead
+ 0.1 µF
150
150
150
150
Mode Selecti on
1 µF
Ω
Ω
Ω
Ω
20
2.2 nF
19
17
2.2 nF
16
10 11 27
21 6
VA VD
AINL+
AINL-
AINR+
AINR-
DIF1
DIF0
RST
CS4223
2
Ω
VL
AOUTL+
AOUTL-
AOUTR+
AOUTR-
DEM1
DEM0
XTI
XTO
0.1 µF + 1 µF
13
25 26
24 23
18 12
3
2
Analog Filter
Analog Filter
Digital Audio
40 pF
0.1 µF + 1 µF
Source
40 pF
Eliminate the crystal and capacitors when using an external clock input
+2.7 - 5V
External Clock Input
R
* 47 k
s
R
s
R
s
R
s
Audio
DSP
Ω
R = 500
s
* Required for Master Mode only
Ω
1
14 15
28
NC NC
NC NC
AGND
22
SCLK LRCK
SDOUT
DGND
7
SDIN
5 4 9 8

Figure 4. CS4223 Recommended Connection Diagram

(Also see
Recommended Layout Diagram
)
10 DS290PP3
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