Cirrus Logic CS4205 User Manual

CS4205

CrystalClear® Audio Codec ’97 for Portable Computing

Features

! Integrated Asynchronous I

(ZV Port)

! Integrated High-Performance Microphone

Pre-Amplifier

! Integrated Digital Effects Processing for Bass

and Treble Response

! Digital Docking Including an I

Synchronous I

! Performance Oriented Digital Mixer ! SRS ! On-chip PLL for use with External Clock

3D Stereo Enhancement

S Inputs

Sources

! Dedicated Microphone Analog-to-Digital

Converter

! Sample Rate Converters ! S/PDIF Digital Audio Output ! AC ’97 2.1 Compliant ! PC Beep Bypass ! 20-bit Stereo Digital-to-Analog Converters

S Input Port

S Output, 3

! Three Analog Line-level Stereo Inputs for

LINE IN, VIDEO, and AUX

! High Quality Pseudo-Differential CD Input ! Extensive Power Management Support ! Meets or Exceeds the Microsoft

PC 99 and

PC 2001 Audio Performance Requirements

Description

The CS4205 is an AC ’97 2.1 compliant stereo audio codec designed for PC multimedia systems. It uses industry leading CrystalClear signal technology. The CS405 is the first Cirrus AC ’97 audio codec to feature digital centric mixing and digital effects. This advanced technology and these features are designed to help enable the design of PC 99 and PC 2001 compliant high-quality audio systems for desktop, portable, and entertainment PCs.

Coupling the CS4205 with a PCI audio accelerator or core logic supporting the AC ’97 interface implements a cost effective, superior quality audio solution. The CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 audio quality standards.

ORDERING INFO

delta-sigma and mixed

! 18-bit Stereo Analog-to-Digital Converters

AC-LINK AND AC '97

REGISTERS

PWR

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

ID0# ID1#

GPIO0/LRCLK

GPIO1/SDOUT

EAPD/SCLK

SPDO/SDO2

GPIO[2:4]/SDI[1:3]

ZSCLK,ZSDATA,ZLRCLK

Preliminary Product Information

http://www.cirrus.com

TEST

MGT

AC-

'97

LINK

REG

SIGNAL

PROCESSING

ENGINE

GPIO

S/PDIF

SERIAL DATA PORT

ZV PORT

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

CS4205-KQZ, Lead Free 48-pin TQFP 9x9x1.4 mm

ANALOG INPUT MUX AND OUTPUT MIXER

18 bit

SRC

GAIN / MUTE CONTROLS

MIXER / MUX SELECTS

SRC

PCM_DATA

MIC_PCM_DATA

PCM_DATA

ADC

(2ch)

18 bit

ADC

(1ch)

20 bit DAC (2ch)

INPUT

MUX

INPUT MIXER

OUTPUT

MIXER

LINE CD AUX VIDEO

MIC1 MIC2

PHONE PC_BEEP

LINE_OUT MONO_OUT

JULY '05

DS489PP4

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 6

ANALOG CHARACTERISTICS................................................................................................6

ABSOLUTE MAXIMUM RATINGS ...........................................................................................7

RECOMMENDED OPERATING CONDITIONS .......................................................................7

AC ’97 SERIAL PORT TIMING.................................................................................................9

2. GENERAL DESCRIPTION .....................................................................................................12

2.1 AC-Link ............................... ... .... .......................................... ............................................ 12

2.2 Control Registers .......................... ... .......................................... ...................................... 13

2.3 Sample Rate Converters ........................ .... ... ... ... .... ... ... ....................................... ... ... ... ... 13

2.4 Mixers ........................................................ ... ....................................... ... ... ... .... ... ............ 13

2.5 Input Mux ................................... ... ... .......................................... ...................................... 13

2.6 Volume Control ............................. ... ... .......................................... ................................... 13

2.7 Dedicated Mic Record Path ............................................................................................. 13

3. DIGITAL SIGNAL PATHS ......................................................................................................15

3.1 Analog Centric Mode .... ... .......................................... ... ... .... ... ... ... ... ................................15

3.2 Digital Centric Mode ............................... .... ... .......................................... .........................16

3.3 Host Processing Mode ............................................ ... ... ... .......................................... ... ... 16

3.4 Multi-Channel Mode .........................................................................................................16

4. AC-LINK FRAME DEFINITION .............................................................................................. 18

4.1 AC-Link Serial Data Output Frame .................................................................................. 19

4.1.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 19

4.1.2 Command Address Port (Slot 1)....................................................................................19

4.1.3 Command Data Port (Slot 2).......................................................................................... 20

4.1.4 PCM Playback Data (Slots 3-11)................................................................................... 20

4.1.5 GPIO Pin Control (Slot12)........................... ... ... .... ... ... .......................................... ... ... ... 20

4.2 AC-Link Serial Data Input Frame ..................... ............................................................. ... 21

4.2.1 Serial Data Input Slot Tag Bits (Slot 0) ........................................................................ 21

4.2.2 Status Address Port (Slot 1) .......................................................................................... 21

4.2.3 Status Data Port (Slot 2)................................................................................................22

4.2.4 PCM Capture Data (Slot 3-8,11)....................................................................................22

CS4205

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its

subsidiaries ("Cirr us") belie ve that the i nformation contained i n this document i s accurate a nd reliabl e. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowle dgme nt, inclu ding those p ertain ing to w arranty, ind emni ficatio n, and lim itatio n of liab ility. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Thi s document is the prop erty of Cirrus and by furnish ing thi s inform ation, Cir rus gran ts no lic ense, expr ess or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be m ad e of th e information only for use within your orga ni zatio n with respect to Cirrus integrated circuits or other pr od ucts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CU ST OMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRU S P RO D UCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FR OM ANY AND ALL LI ABILI TY, INCL UDING AT TORNEYS ’ FEES AND COSTS, THA T MAY RE SULT F ROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

2 DS489PP4

CS4205

4.2.5 GPIO Pin Status (Slot 12) ............. ... ... .... .......................................... ... ... ... .... ............... 22

4.3 AC-Link Protocol Violation - Loss of SYNC ..................................... .... ... ... ... .... ... ... ... ... ... 23

5. REGISTER INTERFACE .................................................................................................... 24

5.1 Reset Register (Index 00h) .............. ... ... .... ... .......................................... ... ... .... ... ... ... ... ... 26

5.2 Master Volume Register (Index 02h) ............................................................................... 26

5.3 Mono Volume Register (Index 06h)..................... .... ... ... ... .... ... ... ... ... .... ... ... ...................... 28

5.4 Master Tone Control Register (Index 08h) ....................................................................... 28

5.5 PC_BEEP Volume Register (Index 0Ah).......................................................................... 29

5.6 Phone Volume Register (Index 0Ch).......................... ............................................. ......... 29

5.7 Microphone Volume Register (Index 0Eh)........................................................................ 30

5.8 Analog Mixer Input Gain Registers (Index 10h - 18h) ...................................................... 31

5.9 Input Mux Select Register (Index 1Ah)............................................................................. 32

5.10 Record Gain Register (Index 1Ch) ................................................................................. 33

5.11 Record Gain Mic Register (Index 1Eh)........................................................................... 33

5.12 General Purpose Register (Index 20h) ......... ... .... ... ... ... .... ... ... ... ... ................................ 34

5.13 3D Control Register (Index 22h)..................................................................................... 34

5.14 Powerdown Control/Status Register (Index 26h) ........................................................... 35

5.15 Extended Audio ID Register (Index 28h)........................................................................ 36

5.16 Extended Audio Status/Control Register (Index 2Ah) .................................................... 37

5.17 Audio Sample Rate Control Registers (Index 2Ch - 34h)......... ... ... .... ... ... ...................... 38

5.18 Extended Modem ID Register (Index 3Ch) .................................................................... 39

5.19 Extended Modem Status/Control Register (Index 3Eh) ................................................. 39

5.20 GPIO Pin Configuration Register (Index 4Ch)................................................................ 39

5.21 GPIO Pin Polarity/Type Configuration Register (Index 4Eh).......................................... 40

5.22 GPIO Pin Sticky Register (Index 50h) ............................................................................ 40

5.23 GPIO Pin Wakeup Mask Register (Index 52h)............................................................... 41

5.24 GPIO Pin Status Register (Index 54h)............................................................................ 41

5.25 AC Mode Control Register (Index 5Eh).......................................................................... 41

5.26 Misc. Crystal Control Register (Index 60h)..................................................................... 44

5.27 S/PDIF Control Register (Index 68h).............................................................................. 45

5.28 Serial Port Control Register (Index 6Ah) ........................................................................ 46

5.29 Special Feature Address Register (Index 6Ch).............................................................. 47

5.30 Special Feature Data Register (Index 6Eh) ................... ................................................ 47

5.31 Digital Mixer Input Volume Registers (Index 6Eh, Address 00h - 05h) .......................... 47

5.32 Serial Data Port Volume Control Registers (Index 6Eh, Address 06h - 07h)................. 48

5.33 Signal Processing Engine Control Register (Index 6Eh, Address 08h).......................... 49

5.34 Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh)....... 50

5.35 BIOS-Driver Interface Control Registers (Index 6Eh, Address 0Ch - 0Dh) .................... 51

5.36 ZV Port Control/Status Registers (Index 6Eh, Address 0Eh - 0Fh)................................ 51

5.37 BIOS-Driver Interface Status Register (Index 7Ah)........................................................ 51

5.38 Vendor ID1 Register (Index 7Ch) ................................................................................... 53

5.39 Vendor ID2 Register (Index 7Eh) ................................................................................... 53

6. SERIAL DATA PORTS ........................................................................................................... 54

6.1 Overview ............. .......................................... .......................................... ... ...................... 54

6.2 Multi-Channel Expansion ........... ... ... ... ... .... ... ... ... .... ... ... ... .......................................... ... ... 54

6.3 Digital Docking .............. ... .......................................... .......................................... ... ......... 55

6.4 Serial Data Formats ............... .... .......................................... ... ... ... ................................... 55

7. ZV PORT ................................................................................................................................. 57

8. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 58

9. EXCLUSIVE FUNCTIONS ...................................................................................................... 58

10. POWER MANAGEMENT .................................................. ... .... ... ... ... ... .... ... ... ... .... ............... 59

10.1 AC ’97 Reset Modes ...................................................................................................... 59

10.1.1 Cold Reset ........................................................................................................ 59

10.1.2 Warm Reset ...................................................................................................... 59

DS489PP4 3

CS4205

10.1.3 New Warm Reset ........................... ................................................................... 59

10.1.4 Register Reset ..................................................................................................59

10.2 Powerdown Controls ......................................................................................................60

11. CLOCKING ........................................................ .......................................... ... ......................62

11.1 PLL Operation (External Clock) ..................................................................................... 62

11.2 24.576 MHz Crystal Operation .......................................................................................62

11.3 Secondary Codec Operation ................................. ... ... .......................................... .........62

12. ANALOG HARDWARE DESCRIPTION ............................................................................... 64

12.1 Analog Inputs .................................................................................................................64

12.1.1 Line Inputs .........................................................................................................64

12.1.2 CD Input ............................................................................................................ 64

12.1.3 Microphone Inputs ............................................................................................. 65

12.1.4 PC Beep Input ................................................................................................... 65

12.1.5 Phone Input ....................................................................................................... 65

12.2 Analog Outputs .............................................................................................................. 65

12.2.1 Stereo Output ....................................................................................................66

12.2.2 Mono Output .....................................................................................................66

12.3 Miscellaneous Analog Signals ....................................................................................... 66

12.4 Power Supplies ..............................................................................................................66

12.5 Reference Design ..........................................................................................................67

13. GROUNDING AND LAYOUT .............................................................................................. 68

14. PIN DESCRIPTIONS ....................................................................................................... 70

15. PARAMETER AND TERM DEFINITIONS ............................................................................ 77

16. REFERENCE DESIGN .................................................. ... .... ... ... ... ... .... ... ... ... ...................79

17. REFERENCES ................................ ... ... ... ... .... ... ... ... .......................................... .... ... ... ......... 80

18. PACKAGE DIMENSIONS .....................................................................................................81

LIST OF FIGURES

Figure 1. Power Up Timing............................................................................................................10

Figure 2. Codec Ready from Start-up or Fault Condition.............................................................. 10

Figure 3. Clocks ............................................................................................................................10

Figure 4. Data Setup and Hold...................................................................................................... 11

Figure 5. PR4 Powerdown and Warm Reset ................................................................................11

Figure 6. Test Mode......................................................................................................................11

Figure 7. AC-link Connections.......................................................................................................12

Figure 8. CS4205 Mixer Diagram..................................................................................................14

Figure 9. Digital Signal Path Overview..........................................................................................15

Figure 10. Analog Centric Mode....................................................................................................17

Figure 11. Digital Centric Mode..................................................................................................... 17

Figure 12. Host Processing Mode.................................................................................................17

Figure 13. Multi-Channel Mode.....................................................................................................17

Figure 14. AC-link Input and Output Framing................................................................................18

Figure 15. Serial Data Port: Six Channel Circuit ...........................................................................54

Figure 16. Digital Docking Connection Diagram ........................................................................... 55

Figure 17. Serial Data Format 0 (I2S)...........................................................................................56

Figure 18. Serial Data Format 1 (Left Justified) ............................................................................56

Figure 19. Serial Data Format 2 (Right Justified, 20-bit data).......................................................56

Figure 20. Serial Data Format 3 (Right Justified, 16-bit data).......................................................56

Figure 21. ZV Port Format (I2S, 16-bit data)................................................................................. 57

Figure 22. S/PDIF Output..............................................................................................................58

Figure 23. PLL External Loop Filter............................................................................................... 62

Figure 24. External Crystal............................................................................................................63

4 DS489PP4

CS4205

Figure 25. Line Input (Replicate for Video and AUX).................................................................... 64

Figure 26. Differential 2 VRMS CD Input...................................................................................... 64

Figure 27. Differential 1 VRMS CD Input...................................................................................... 64

Figure 28. Microphone Input......................................................................................................... 65

Figure 29. PC_BEEP Input ........................................................................................................... 65

Figure 30. Modem Connection...................................................................................................... 65

Figure 31. Stereo Output............................................................................................................... 66

Figure 32. +5V Analog Voltage Regulator .................................................................................... 66

Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes............... 69

Figure 34. Pin Locations for the CS4205...................................................................................... 70

Figure 35. CS4205 Reference Design.......................................................................................... 79

DS489PP4 5

LIST OF TABLES

Table 1. AC Mode Control Configurations........................... ... .... ... ... ... ... .... ... ... ... .... ... ... ...16

Table 2. Register Overview for the CS4205 .....................................................................24

Table 3. Indirectly Addressed Register Overview.............................................................25

Table 4. Analog Mixer Output Attenuation........................................................................26

Table 5. Tone Control Values...........................................................................................28

Table 6. Microphone Input Gain Values............................................................................30

Table 7. Analog Mixer Input Gain Values .........................................................................31

Table 8. Analog Mixer Input Gain Register Index .............................................................31

Table 9. Input Mux Selection ............................................................................................32

Table 10. Record Gain Values..........................................................................................33

Table 11. Audio Sample Rate Control Register Index................ ... ... ... ... .... ... ... ................38

Table 12. Directly Supported SRC Sample Rates for the CS4205...................................38

Table 13. GPIO Input/Output Configurations....................................................................40

Table 14. Slot Mapping for the CS4205...........................................................................43

Table 15. Digital Signal Source Selects............................................................................43

Table 16. Serial Data Format Selection............................................................................46

Table 17. Digital Mixer Input Volume Register Index........................................................47

Table 18. Serial Port Volume Control Register Index.................... ... ... ... .... ... ... ... .... ... ... ...48

Table 19. Volume Change Modes and EQ Filter Selects .................................................49

Table 20. Internal Error Sources and Correction Methods ...............................................50

Table 21. ZV Port Control/Status Register Index..............................................................51

Table 22. Device ID with Corresponding Part Number.....................................................53

Table 23. Serial Data Formats and Compatible DACs/ADC’s for the CS4205................56

Table 24. Powerdown PR Bit Functions ........................................................... ... .... ... ... ...60

Table 25. Powerdown PR Function Matrix for the CS4205 ..............................................61

Table 26. Power Consumption by Powerdown Mode for the CS4205..............................61

Table 27. Clocking Configurations for the CS4205...........................................................63

CS4205

6 DS489PP4

1. CHARACTERISTICS AND SPECIFICATIONS

CS4205

ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted: T

AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; Z 1000 pF load for Mono and Line Outputs; C

= 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz,

ambient

=100 kΩ/

= 25° C,

18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.

Parameter

(Note 2)

Symbol Path

(Note 3)

CS4205-KQZ

Min Typ Max

Unit

Full Scale Input Voltage Line Inputs Mic Inputs (10dB = 0, 20dB = 0) Mic Inputs (10dB = 1, 20dB = 0) Mic Inputs (10dB = 0, 20dB = 1) Mic Inputs (10dB = 1, 20dB = 1)

A-D A-D A-D A-D A-D

0.91

0.283

0.091

0.0283

1.00

0.315

0.10

0.0315

V V V V V

RMS RMS RMS RMS RMS

Full Scale Output Voltage Line and Mono Outputs D-A 0.91 1.0 1.13 V

Frequency Response (Note 4) Analog Ac = ± 0.25 dB DAC Ac = ± 0.25 dB ADC Ac = ± 0.25 dB

Dynamic Range Stereo Analog Input s to LINE_OUT Mono Analog Input to LINE_OUT DAC Dynamic Range ADC Dynamic Range

DAC SNR (-20 dB FS input w/ CCIR-RMS filter on output)

Total Harmonic Distortion + Noise

SNR

THD+N

A-A D-A A-D

A-A A-A D-A A-D

20 20 20

90 85 85 85

95 90 90 90

20,000 20,000 20,000

D-A - 70 - dB

RMS

Hz Hz Hz

dB FS A dB FS A dB FS A dB FS A

(-3 dB FS input signal): Line Output DAC ADC (all inputs)

A-A D-A A-D

-90

-87

-84

-80

dB FS dB FS dB FS

Power Supply Rejection Ratio (1 kHz, 0.5 V

w/ 5 V DC offset) (Note 4) 40 60 - dB

RMS

Interchannel Isolation 70 87 - dB Spurious Tone (Note 4) - -100 - dB FS Input Impedance (Note 4) 10 - - kΩ

Notes: 1. Z

refers to the analog output pin loading and CDL refers to the digital output pin loading.

2. Parameter definitions are given in Section 15, Parameter and Term Definitions.

3. Path refers to the signal path used to generate this data. These paths are defined in Section 15, Parameter and Term Definitions.

4. This specification is guaranteed by silicon characterization; it is not production tested.

DS489PP4 7

ANALOG CHARACTERISTICS (Continued)

CS4205

Parameter

(Note 2)

External Load Impedance Line Output, Mono Output 10 - - kΩ

Output Impedance Line Output, Mono Output (Note 4) - 730 - Ω

Input Capacitance (Note 4) - 5 - pF Vrefout 2.3 2.4 2.5 V

Symbol Path

(Note 3)

CS4205-KQZ

Min Typ Max

Unit

MIXER CHARACTERISTICS

Parameter Min Typ Max Unit

Mixer Gain Range Span PC Beep Line In, Aux, CD, Video, Mic1, Mic2, Phone Mono Out, Line Out ADC Gain

Step Size All volume controls except PC Beep PC Beep

45.0

46.5

22.5

1.5

3.0

dB dB dB dB

dB dB

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog Total Power Dissipation (Supplies, Inputs, Outputs) - - 1.25 W Input Current per Pin (Except Supply Pins) -10 - 10 mA Output Current per Pin (Except Supply Pins) -15 - 15 mA Analog Input voltage -0.3 - AVdd+

Digital Input voltage -0.3 - DVdd +

Ambient Temperature (Power Applied) 0 - 70 °C Storage Temperature -65 - 150 °C

-0.3

5.5

0.3

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog

Operating Ambient Temperature 0 - 70 °C

DVdd1, DVdd2 DVdd1, DVdd2

AVdd1, AVdd2

3.135

4.75

3.3 5 5

3.465

5.25

V V V

8 DS489PP4

CS4205

DIGITAL CHARACTERISTICS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

DVdd = 3.3V

Low level input voltage V High level input voltage V High level output voltage V Low level output voltage V

Input Leakage Current (AC-link inputs) -10 - 10 µA Output Leakage Current (Tr i-stated AC-link outputs) -10 - 10 µA Output buffer drive current

BIT_CLK, SPDO/SDO2 SDATA_IN, EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT, GPIO2/SDI1, GPIO3/SDI2, GPIO4/SDI3 (Note 4)

DVdd = 5.0 V

Low level input voltage V High level input voltage V High level output voltage V Low level output voltage V

Input Leakage Current (AC-link inputs) -10 - 10 µA Output Leakage Current (Tr i-stated AC-link outputs) -10 - 10 µA Output buffer drive current

BIT_CLK, SPDO/SDO2 SDATA_IN, EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT, GPIO2/SDI1, GPIO3/SDI2, GPIO4/SDI3 (Note 4)

- - 0.80 V

2.15 - - V

3.00 3.25 - V

-0.030.35V

- - 0.80 V

3.25 - - V

4.50 4.95 - V

- 0.03 0.35 V

DS489PP4 9

CS4205

AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T

AVdd = 5.0 V, DVdd = 3.3 V; C

= 55 pF load.

ambient

= 25° C,

Parameter Symbol Min Typ Max Unit

RESET Timing

RESET# active low pulse width T RESET# inactive to BIT_CLK start-up delay (XTL mode)

(OSC mode)

(PLL mode) 1st SYNC active to CODEC READY ‘set’ T Vdd stable to RESET# inactive T

rst_low

rst2clk

sync2crd

vdd2rst#

1.0 - - µs

4.0

2.5

-62.5-µs

100 - - µs

Clocks

BIT_CLK frequency F BIT_CLK period T

clk_period

clk

- 12.288 - MHz

- 81.4 - ns BIT_CLK output jitter (depends on XTL_IN source) - - 750 ps BIT_CLK high pulse width T BIT_CLK low pulse width T SYNC frequency F SYNC period T SYNC high pulse width T SYNC low pulse width T

sync_period

sync_high

sync_low

clk_high

clk_low

sync

36 40.7 45 ns 36 40.7 45 ns

- 48 - kHz

-20.8-µs

-1.3-µs

-19.5-µs

Data Setup and Hold

Output propagation delay from rising edge of BIT_CLK T Input setup time from falling edge of BIT_CLK T Input hold time from falling edge of BIT_CLK T Input signal rise time T Input signal fall time T Output signal rise time (Note 4) T Output signal fall time (Note 4) T

isetup

ihold

irise

ifall

orise

ofall

81012ns

10 - - ns

0--ns 2-6ns 2-6ns 246ns 246ns

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T SYNC pulse width (PR4) Warm Reset T SYNC inactive (PR4) to BIT_CLK start-up delay T Setup to trailing edge of RESET# (ATE test mode) (Note 4) T

s2_pdown

sync_pr4 sync2clk

setup2rst

Rising edge of RESET# to Hi-Z delay (Note 4) T

off

-0.21.0µs

1.0 - - µs

162.8 285 - ns 15 - - ns

- - 25 ns

µs µs

10 DS489PP4

BIT_CLK

RESET#

Vdd

BIT_CLK

rst_low

vdd2rst#

Figure 1. Power Up Timing

rst2clk

CS4205

SYNC

CODEC_READY

Figure 2. Codec Ready from Start-up or Fault Condition

BIT_CLK

orise

SYNC

irise

clk_highTclk_low

sync_high

sync2crd

ifall

sync_period

clk_period

sync_low

ifall

Figure 3. Clocks

DS489PP4 11

BIT_CLK

SDATA_IN

SDATA_OUT, SYNC

Slot 1 Slot 2

isetup

Figure 4. Data Setup and Hold

CS4205

ihold

SDATA_OUT

SDATA_IN

SYNC

Write to 0x20 Data PR4 Don't Care

s2_pdown

Figure 5. PR4 Powerdown and Warm Reset

RESET#

setup2rst

SDATA_OUT, SYNC

off

sync_pr4

sync2clk

SDATA_IN, BIT_CLK

Hi-Z

Figure 6. Test Mode

12 DS489PP4

CS4205

2. GENERAL DESCRIPTION

The CS4205 is a mixed-signal serial audio codec compliant with the Intel® Audio Codec ’97 Specifi- cation, revision 2.1 [6] (referred to as AC ’97). It is designed to be paired with a digital controller, typically located on the PCI bus or integrated within the system core logic chip set. The controller is responsible for all communications between the CS4205 and the remainder of the system. The CS4205 contains two distinct functional sections: digital and analog. The digital section includes the AC-link interface, S/PDIF interface, serial data port, GPIO, signal processing engine, ZV Port, power management support, and Sample Rate Converters (SRCs). The analog section includes the analog input multiplexer (mux), stereo input mixer, stereo output mixer, mono output mixer, stereo Analog-to-Digital Converters (ADCs), stereo Digital-to-Analog Converters (DACs), dedicated mono microphone ADC, and their associated volume controls.

2.1 AC-Link

All communication with the CS4205 is established with a 5-wire digital interface to the controller called the AC-link. This interface is shown in Figure 7. All clocking for the serial communication is synchronous to the BIT_CLK signal. BIT_CLK is generated by the primary audio codec and is used to clock the controller and any secondary audio codecs. Both input and output AC-link audio frames are organized as a sequence of 256 serial bits forming 13 groups referred to as ‘slots’. During each audio frame, data is passed bi-directionally between the CS4205 and the controller. The input frame is driven from the CS4205 on the SDATA_IN line. The output frame is driven from the controller on the SDATA_OUT line. The controller is also responsible for issuing reset commands via the RESET# signal. Following a Cold Reset, the CS4205 is responsible for notifying the controller that it is ready for operation after synchronizing its internal functions. The CS4205 AC-link signals must use the same digital supply voltage as the controller, either +5 V or +3.3 V. See Section 4, AC-Link Frame Definition, for detailed AC-link information.

Digital AC'97

Controller

Figure 7. AC-link Connections

DS489PP4 13

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

AC'97

CODEC

CS4205

2.2 Control Registers

The CS4205 contains a set of AC ’97 compliant control registers, and a set of Cirrus Logic defined control registers. These registers control the basic functions and features of the CS4205. Read accesses of the control registers by the AC ’97 controller are accomplished with the requested register index in Slot 1 of a SDATA_OUT frame. The following SDATA_IN frame will contain the read data in Slot

2. Write operations are similar, with the register index in Slot 1 and the write data in Slot 2 of a SDATA_OUT frame. The function of each input and output frame is detailed in Section 4, AC-Link Frame Definition. Individual register descriptions are found in Section 5, Register Interface.

2.3 Sample Rate Converters

The sample rate converters (SRC) provide high accuracy digital filters supporting sample frequencies other than 48 kHz to be captured from the CS4205 or played from the controller. AC ’97 requires support for two audio rates (44.1 and 48 kHz) and four modem rates (8, 9.6, 13.714, and 16 kHz). In addition, the Intel® I/O Controller Hub (ICHx) specification [9] requires support for five more audio rates (8, 11.025, 16, 22.05, and 32 kHz) and specifies two optional modem rates (24, 48kHz). The CS4205 supports all these rates, as shown in Table 12 on page 38.

2.4 Mixers

The CS4205 input and output mixers are illustrated in Figure 8. The stereo input mixer sums together the analog inputs to the CS4205 according to the settings in the volume control registers. The stereo output mixer sums the output of the stereo input

mixer with the PC_BEEP and PHONE signals. The stereo output mix is then sent to the LINE_OUT pins of the CS4205. The mono output mixer generates a monophonic sum of the left and right audio channels from the stereo input mixer. The mono output mix is then sent to the MONO_OUT pin on the CS4205.

2.5 Input Mux

The input multiplexer controls which analog input is sent to the ADCs. The output of the input mux is converted to stereo 18-bit digital PCM data and transmitted to the controller by means of the AC-link SDATA_IN signal.

2.6 Volume Control

The CS4205 volume registers control analog input levels to the input mixer and analog output levels, including the master volume level. The PC_BEEP volume control uses 3 dB steps with a range of 0 dB to -45 dB attenuation. All other analog volume controls use 1.5 dB steps. The analog inputs have a mixing range of +12 dB signal gain to -34.5 dB signal attenuation. The analog output volume controls have a range of 0 dB to -46.5 dB attenuation for LINE_OUT and MONO_OUT.

2.7 Dedicated Mic Record Path

The CS4205 includes a dedicated microphone ADC that supports advanced functions such as speech recognition and internet telephony. The dedicated ADC allows recording of a microphone input independent of the input mux settings. This enables simultaneous capture of microphone and independent stereo sources.

14 DS489PP4

CS4205

PC_BEEP

PHONE

PCM_OUT

MIC1

MIC2

LINE

VIDEO

AUX

MIC

SELECT

Front D/A

CONVERTERS

DAC

BOOST

MUTE

PC BEEP BYPASS

ANALOG STEREO

INPUT MIXER

MONO MIX

SELECT

STEREO TO

MONO MIXER

ANALOG STEREO

OUTPUT MIXER

STEREO TO

MONO MIXER

1/2

DAC DIRECT

MODE

MONO OUT

SELECT

ADC

INPUT

MUX

MASTER VOLUME

VOL

MONO

VOLUME

VOL

L/R ADC

GAIN

VOL

MUTE

OUTPUT BUFFER

L/R A/D

CONVERTERS

ADCMUTE

LINE OUT

MONO OUT

PCM_IN

VOL

VOL VOL

VOL VOL VOL

MIC ADC

GAIN

VOL

MIC A/D

CONVERTER

ADCMUTE

MIC_PCM_IN

Figure 8. CS4205 Mixer Diagram

DS489PP4 15

CS4205

3. DIGITAL SIGNAL PATHS

The CS4205 includes a number of internal digital signal path options. Figure 9 shows the principal signal flow options through one channel of the device. Four commonly used signal flow modes are detailed in the following sections. The signal flow modes are controlled through the bits in the AC Mode Control Register (Index 5Eh). The bit configuration for each detailed mode is listed in Table 1 on page 17.

front

surr

c+lfe

SRC

DAC LINE_OUT

DACS

3.1 Analog Centric Mode

Analog centric mode is detailed in Figure 10 on page 18. In this mode, all the digital sources are pre-mixed in the digital mixer and sent to the DACs. The DAC outputs are mixed with the analog sources in the analog mixer. The ADCs send captured data directly to the host. The ADC mux is used to select a single source or the output of the input mixer for capture. In the analog centric mode, effects processing is only available on digital sources.

LINE

MIXER

mux out

ADC ½ ADC

AUX

VIDEO

mic out

MIC

mix out

DDM

MONO_OUT

L/R cap

mic cap

SRC

½ SRC

AC-Link

IN1

IN2

IN3

CAPS

MICS

I²S

ZV ASRC VOL

VOL

Figure 9. Digital Signal Path Overview

VOL VOL

Signal Processing Engine

DIG

EFX

SDOS

SPDS

VOL

I²S

OUT1

I²S

OUT2

S/PDIF

OUT

16 DS489PP4

CS4205

3.2 Digital Centric Mode

Digital centric mode is detailed in Figure 11. In this mode, the analog sources are first mixed in the analog mixer and sent to the ADCs. The ADC outputs are then mixed with the digital sources in the digital mixer. This allows effects processing on all sources and supports a “what you hear is what you record” model. The processed digital signal is sent to the DACs, bypassing the analog mixer using DAC direct mode. The ADC mux must be set to stereo mix to support this model. Consequently, only the mix can be captured by the host, rather than the individual sources.

3.3 Host Processing Mode

Host processing mode is detailed in Figure 12. This mode is similar to digital centric mode, except the

output of the digital mixer is captured by the host. Any mixing with host sources and effects processing is done on the host. The processed signal is sent to the DACs, bypassing the analog mixer using DAC direct mode. In host processing mode, the playback and capture paths are completely separate inside the CS4205.

3.4 Multi-Channel Mode

Multi-channel mode is detailed in Figure 13. This mode is an extension of any of the other three modes, with the distinguishing feature that one or two additional slot pairs are routed to the serial data output ports. This allows for a complete multi-channel solution with a single AC ’97 audio codec and external DACs.

AC Mode

Control Bits

DACS 1 1 0 0 or 1

CAPS[1:0] 00 10 10 00,10 or 11

MICS 0 or 1 0 or 1 0 or 1 0 or 1

DDM 0 1 1 0 or 1 SDOS[1:0] 10 or 11 11 - 00 SPDS[1:0] 00, 01, 10 or 11 00, 01, 10 or 11 00 or 01 N/A

Analog Centric

Mode

Ta ble 1. AC Mode Control Configurations

Digital Centric

Mode

Host Processing

Mode

Multi-Channel

Mode

DS489PP4 17

CS4205

front

SRC

surr

c+lfe

L/R

SRC

cap

mic

½ SRC

cap

AC-Link

front

SRC

surr

c+lfe

L/R

SRC

cap

mic

½ SRC

cap

AC-Link

MIC

AUX

LINE

VIDEO

DAC MIXER LINE_OUT

MICS

I²S IN1

I²S IN2

I²S IN3

ZV ASRC VOL

VOL

mux out

ADC ½ ADC

Signal Processing Engine

VOL

mic out

EFX

mix out

DIG

Figure 10. Analog Centric Mode

MIC

AUX

LINE

VIDEO

DAC LINE_OUT

MICS

I²S IN1

I²S IN2

I²S IN3

ZV ASRC VOL

VOL

MIXER

mux out

mic out

ADC ½ ADC

VOL VOL

Signal Processing Engine

EFX

mix out

DIG

SDOS

SPDS

MONO_OUT

VOL

MONO_OUT

VOL

I²S

OUT1

S/PDIF

OUT

I²S

OUT1

S/PDIF

OUT

front

SRC

surr

c+lfe

L/R

SRC

cap

mic

½ SRC

cap

AC-Link

front

SRC

surr

c+lfe

L/R

SRC

cap

mic

½ SRC

cap

AC-Link

MIC

AUX

LINE

VIDEO

DAC LINE_OUT

MICS

I²S

IN1

I²S

IN2

I²S

IN3

ZV ASRC VOL

VOL

MIXER

mux out

mic out

ADC ½ ADC

VOL

Signal Processing Engine

mix out

Figure 12. Host Processing Mode

MIC

AUX

LINE

VIDEO

DAC LINE_OUT

DACS

CAPS

MICS

I²S

IN1

I²S

IN2

I²S

IN3

ZV ASRC VOL

VOL

MIXER

mux out

mic out

ADC ½ ADC

VOL VOL

Signal Processing Engine

DIG EFX

mix out

DDM

SPDS

MONO_OUT

VOL

S/PDIF

OUT

I²S

OUT1

I²S

OUT2

Figure 11. Digital Centric Mode

Figure 13. Multi-Channel Mode

18 DS489PP4

CS4205

4. AC-LINK FRAME DEFINITION

The AC-link is a bi-directional serial port with data organized into frames consisting of one 16-bit and twelve 20-bit time-division multiplexed slots. Slot 0 is a special reserved time slot containing 16-bits which are used for AC-link protocol infrastructure. Slots 1 through 12 contain audio or control/status data. Both the serial data output and input frames are defined from the controller perspective, not from the CS4205 perspective.

The controller synchronizes the beginning of a frame with the assertion of the SYNC signal. Figure 14 shows the position of each bit location

Tag Phase Data Phase

within the frame. The first bit position in a new serial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sampled active by the CS4205 (on the falling edge of BIT_CLK), both devices are synchronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame’s serial data. On the next rising edge of BIT_CLK, the first bit of Slot 0 is driven by the controller on the SDATA_OUT pin. On the next falling edge of BIT_CLK, the CS4205 latches this data in as the first bit of the frame.

20.8 µs

(48 kHz)

SYNC

BIT_CLK

Bit Frame Position:

SDATA_OUT

Bit Frame Position:

SDATA_IN

81.4 ns

F255

GPIO

12.288 MHz

F0 F1 F2 F16F15F14F13F12 Valid

Frame

F0 F1 F2 F16F15F14F13F12 F35 F56 F76F255

Codec Ready

Slot 1

Valid

Slot 1 Valid

INT

Slot 2

Valid

Slot 2

Valid

Slot 12

Valid

Slot 12

Valid

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slots 5-12

Codec

ID1

R/W 0 WD15

ID0

0000

F35

Figure 14. AC-link Input and Output Framing

F36 F57

F36

F56

D19 D18

F57

D19 D18 D19RD15

F76

D19

F96

D19

F96

D19

F255

GPIO

INT

DS489PP4 19

CS4205

4.1 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4205 from the AC ’97 controller. Figure 14 illustrates the serial port timing.

The PCM playback data being passed to the CS4205 is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified in its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.

4.1.1 Serial Data Output Slot Tags (Slot 0)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Valid

Slot 1

Frame

Valid

Valid Frame The Valid Frame bit determines if any of the following slots contain either valid playback data

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 1 1

Valid

Slot 12

Valid

Res

Codec

ID1

Codec

ID0

for the CS4205 or data for read/write operatio ns. When ‘set’, at least one of th e other AC-link

slots contains valid data. If this bit is ‘clear’, the remainde r of the fr am e is ignor ed . Slot 1 Valid The Slot 1 Valid bit indicates a valid register read/write address for a primary codec. Slot 2 Valid The Slot 2 Valid bit indicates valid register write data for a primary codec. Slot [3:11] Valid The Slot [3:11] Valid bits indicate the validity of data in their corresponding serial data output

slots. If a bit is ‘set’, the corresponding output slot contains valid data . If a bit is ‘cleared’, the

corresponding slot will be ignored. Slot 12 Valid The Slot 12 Valid bit indicates if output Slot 12 contains valid GPIO control data. Codec ID[1:0] The Codec ID[1:0] bits determine which codec is being accessed during the current AC-link

frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01,

10, or 11 indicates one of three possible secondary codecs is being accessed. A Codec ID

value of 01, 10, or 11 also indicates a valid read/write add ress and/or valid register write data

for a secondary codec.

4.1.2 Command Address Port (Slot 1)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W

R/W Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index

RI6 RI5 RI4 RI3 RI2 RI1 RI0 Reserved

bits will occur in the AC ’97 2.x audio codec. When the bit is ‘cleared’, a write will occur. For

any read or write access to occur, the Valid Frame bit (F0) must be ‘set’ and the Codec ID[1:0]

bits (F[14:15]) must match the Codec ID of the AC ’97 2.x audio codec being accessed. Ad-

ditionally, for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and

both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For

a secondary codec, both the Slot 1 Valid bit (F1) and th e Slot 2 Valid bit (F2) must be ‘cleared’

for read and write accesses. See Figure 14 for bit frame positions. RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the

CS4205. All registers are defined at word addressable boundaries. The RI0 b it must be ‘clear’

to access CS4205 registers.

20 DS489PP4

CS4205

4.1.3 Command Data Port (Slot 2)

Bit 191817161514131211109876543210

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved

WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an ac-

cess is a read, this slot is ignored.

NOTE: For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means

that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output Slot 0 should always be ‘set’ during the same audio frame. No write access may be split across 2 frames.

4.1.4 PCM Playback Data (Slots 3-11)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PD[19:0] Playback Data. The PD[19:0] bits contain the 20-bit PCM (2’s complement) pl ayback data for

the left and right DACs, serial data ports, and/or the S/PDIF transmitter. Table 14 on page 43 lists a cross reference for each function and its respective slot. The mapping of a given slot to the DAC, serial data port, or S/PDIF transmitter is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0] and AMAP bits in the

AC Mode Control Register (Index 5Eh).

4.1.5 GPIO Pin Control (Slot12)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Not Implemented GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Reserved

GPIO[4:0] GPIO Pin Control. The GPIO[4:0] bits control the CS4205 GPIO pins configured as outputs.

Write accesses using GPIO pin control bits configured as outputs will be reflected on the GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits configured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Con- trol Register (Index 60h) is ‘set’, the bits in output Slot 12 are ignored and GPIO pins configured as outputs are controlled through the GPIO Pin Status Register (Index 54h).

DS489PP4 21

CS4205

4.2 AC-Link Serial Data Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4205 to the AC ’97 controller. The data format for the input frame is very similar to the output frame. Figure 14 on page 19 illustrates the serial port timing.

The PCM capture data from the CS4205 is shifted out MSB first in the most significant 18 bits of each slot. The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’97 Controller that is less than 18 bits wide, the controller should dither and round or just round (but not truncate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4205 will always be returned ‘cleared’.

4.2.1 Serial Data Input Slot Tag Bits (Slot 0)

Bit 1514131211109876543210

Codec Ready

Codec Ready Codec Ready. The Codec Ready bit indicates the readiness of the CS4205 AC-link. Immedi-

Slot 1

Valid

Slot 2

Valid

Slot 3

ately after a Cold Reset this bit will be ‘clear’. Once the CS4205 clocks and voltages are stable, this bit will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Con- trol/Status Register (Index 26h) by the controller before any access is ma de to the mixer registers. Any accesses to the CS4205 while Codec Ready is ‘clear’ are ignored.

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

0 0

Slot 1 1

Valid

Slot 12

Valid

Reserved

Slot 1 Valid The Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid The Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:8,11] Valid The Slot [3:8,11] Valid bits indicate Slot [3:8,11] contains valid captur e data from the CS4205

ADCs. If a bit is ‘set’, the corresponding input slot contains valid data. If a bit is ‘cleared’, the

corresponding slot will be ignored.

Slot 12 Valid The Slot 12 Valid bit indicates Slot 12 contains valid GPIO status data.

4.2.2 Status Address Port (Slot 1)

Bit 191817161514131211109876543210

Res RI6 RI5 RI4 RI3 RI2 RI1 RI0 SR3 SR4 SR5 SR6 SR7 SR8 SR9 0 SR11 0 Reserved

RI[6:0] Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has

been requested in the previous frame. The CS4205 will only echo the register index for a read access. Write accesses will not return valid data in Slot 1.

SR[3:9,11] Slot Request. If SRx is ‘set’, this indicates the CS4205 SRC does not need a new sample on

the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample is needed on the following frame. If the VRA bit in the Extended Audio Stat us/Control Register

(Index 2Ah)

and the SR[3:9,11] bits are used to request data.

is ‘clear’, the SR[3:9,11] bits are always 0. When VRA is ‘set’, the SRC is enabled

22 DS489PP4

CS4205

4.2.3 Status Data Port (Slot 2)

Bit 1918 17 16 15 14 13121110 9 8 7 6 5 4 3210

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Reserved

RD[15:0] Read Data. The RD[15:0] bits contain the register data requested by the controller from the

previous read request. All read requests will return the read address in the input Slot 1 and the register data in the input Slot 2 on the following ser ial data frame.

4.2.4 PCM Capture Data (Slot 3-8,11)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CD17 CD16CD15 CD14CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 0 0

CD[17:0] Capture Data. The CD [17:0] bits contain 18-bit PCM (2’s complement) capture data. The

data will only be valid when the respective slot valid bit is ‘set’ in input Slot 0. The mapping of a given slot to an ADC is determined by the state of the ID[1:0] bits in the Extended Audio ID

Register (Index 28h) and the SM[1:0] and AMAP bits in the AC Mode Control Regi ster (Index 5Eh). The definition of each slot can be found in Table 14 on page 43.

4.2.5 GPIO Pin Status (Slot 12)

Bit 191817161514131211109876543210

0 0 0 0 0 0 0 0 0 0 0 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Res BDI IEC

GPIO[4:0] GPIO Pin Status. The GPIO[4:0] bits reflect the status of the CS4205 GPIO pins configured

as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the GPIO[4:0] pin control bits in output Slot 12.

BDI BIOS-Driver Interface. The BDI bit indicates that a BIOS event has occurred. This bit is a logic

OR of all bits in the BDI Status Register (Index 7Ah) ANDed with their corresponding bit in the BDI Config Register (Index 6Eh, Address 0Ch).

IEC Internal Error Condition. The IEC bit indicates that an internal error, such as an ADC over-

range or a digital data overflow has occurred. This bit is a logic OR of all bits in the IEC Status Register (Index 6Eh, Address 0Bh).

GPIO_INT GPIO Interrupt. The GPIO_INT bit indicates that a GPIO, BDI, or IEC interrupt event has oc-

curred. The occurrence of a GPIO interrupt is determined by the GPIO interrup t requirements as outlined in the GPIO Pin Wakeup Mask Register (Index 52h) description. In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the GPIO Pin Status Register (Index 54h) corresponding to the GPIO pin which generated the interrupt.

The occurrence of a BDI interrupt is determined by the BDI interrupt requirements as outlined

in the BDI Control Registers (Index 6Eh, Address 0Ch - 0Dh). In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the BDI Status Register (Index 7Ah) that generated the interrupt.

GPIO

_INT

The occurrence of an IEC interrupt is determined by the IEC interrupt requirements as out-

lined in the Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh). In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the IEC Status Register (Index 6Eh, Address 0Bh) corresponding to the IEC source which generated the interrupt.

DS489PP4 23

CS4205

4.3 AC-Link Protocol Violation - Loss of

SYNC

The CS4205 is designed to handle SYNC protocol violations. The following are situations where the SYNC protocol has been violated:

• The SYNC signal is not sampled high for exact-

ly 16 BIT_CLK clock cycles at the start of an audio frame.

• The SYNC signal is not sampled high on the

256th BIT_CLK clock period after the previous SYNC assertion.

• The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous SYNC assertion.

Upon loss of synchronization with the controller, the CS4205 will ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4205 will ignore all register reads and writes and will discontinue the transmission of PCM capture data. In addition, if the LOSM bit in the Misc. Crystal Control Register (Index 60h) is ‘set’ (default), the CS4205 will mute all analog outputs. If the LOSM bit is ‘clear’, the analog outputs will not be muted.

24 DS489PP4

CS4205

5. REGISTER INTERFACE

Reg Regis ter Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

Reset 0 SE4 SE3 SE2 SE1 SE0 0 ID8 ID7 0 ID5 0 ID3 ID2 0 ID0

00h

Master Volume Mute 0 ML5 ML4 ML3 ML2 ML1 ML0 0 0 MR5 MR4 MR3 MR2 MR1 MR0

02h

Mono Volume Mute 0 0 0 0 0 0 0 0 0 MM5 MM4 MM3 MM2 MM1 MM0

06h

Master Tone Control 0 0 0 0 BA3 BA2 BA1 BA0 0 0 0 0 TR3 TR2 TR1 TR0

08h

PC_BEEP Volume Mute 0 0 0 0 0 0 0 0 0 0 PV3 PV2 PV1 PV0 0

0Ah

Phone Volume Mute 0 0 0 0 0 0 0 0 0 0 GN4 GN3 GN2 GN1 GN0

0Ch

Mic Volume Mute 0 0 0 0 0 0 0 0 20dB 0 GN4 GN3 GN2 GN1 GN0

0Eh

Line In Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0

10h

CD Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0

12h

Video Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0

14h

Aux Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0

16h

PCM Out Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 G R3 GR2 GR1 GR0

18h

Record Select 0 0 0 0 0 SL2 SL1 SL0 0 0 0 0 0 SR2 SR1 SR0

1Ah

Record Gain Mute 0 0 0 GL3 GL2 GL1 GL0 0 0 0 0 GR3 GR2 GR1 GR0

1Ch

Record Gain Mic Mute 0 0 0 0 0 0 0 0 0 0 0 GM3 GM2 GM1 GM0

1Eh

General Purpose POP ST 3D LD 0 0 MIX MS

20h

3D Control 0 0 0 0 CR3 CR2 CR1 CR0 0 0 0 0 DP3 DP2 DP1 DP0

22h

Powerdown Ctrl/Stat

26h

Ext’d Audio ID ID1 ID0 0 0 0 0

28h

Ext’d Audio Stat/Ctrl 0 PRL 0 0 0 0

2Ah

PCM Fr o n t DAC Ra t e SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

2Ch

PCM L/ R A D C Rate SR15 SR14 SR13 SR12 SR1 1 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

32h

Mic ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

34h

Ext’d Modem ID ID1ID00 0 000000 0 0 0 0 0 0

3Ch

Ext’d Modem Stat/Ctrl 0 0 0 0 0 0 0 PRA 0 0 0 0 0 0 0 GPIO

3Eh

GPIO Pin Con f ig. 0 0 0 0 0 0 0 0 0 0 0 GC4 GC3 GC2 GC1 GC0

4Ch

GPIO Pin Polarity/Type 1 1 1 1 1 1 1 1 1 1 1 GP4 GP3 GP2 GP1 GP0

4Eh

GPIO Pin Sticky 0 0 0 0 0 0 0 0 0 0 0 GS4 GS3 GS2 GS1 GS0

50h

GPIO Pin Wakeup 0 0 0 0 0 0 0 0 0 0 0 GW4 GW3 GW2 GW1 GW0

52h

GPIO Pin St at u s 0 0 0 0 0 0 0 0 0 0 0 GI4 GI3 GI2 GI1 GI0

54h

EAPD

0 PR5 PR4 PR3 PR2 PR1 PR0 0 0 0 0 REF ANL DAC ADC

AMAP MADC

LPBK

00 0 0 0 0 0

000 0 0VRM0 0VRA 000 0 0VRM0 0VRA

Cirrus Logic Defined Registers:

AC Mode Control

5Eh

Misc. Crystal Control 0 0 Res DPC 0 0 Reserved 10dB

60h

S/PDIF Control

68h

Serial Port Control

6Ah

Special Feature Addr 0 0 0 0 0 0 0 0 0 0 0 0 A3 A2 A1 A0

6Ch

Special Feature Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

6Eh

BDI Status E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0

7Ah

Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0

7Ch

Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 0 DID2 DID1 DID0 1 REV2 REV1 REV0

7Eh

DACS CAPS1 CAPS0

SPEN

Val 0 Fs L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Emph Copy /Audio Pro

SDEN

0 0 0 0 0 0 0 0 SDI3 SDI2 SDI1 SDO2 SDSC SDF1 SDF0

MICS 0 0 TMM DDM

AMAP

0SM1SM0

CRST

SDOS1 SDOS0 SPDS1 SPDS0

Reserved GPOC Reserved LOSM

Table 2. Register Overview for the CS4205

25ADh

8000h 8000h 0F0Fh 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 8000h 0000h 0000h 000Fh x209h

4000h BB80h BB80h BB80h

x000h

0100h

001Fh FFFFh

0000h

0080h

0003h

0000h

8000h

0000h

4352h

5959h

DS489PP4 25

+ 56 hidden pages

Cirrus Logic CS4205 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. CHARACTERISTICS AND SPECIFICATIONS

Figure 1. Power Up Timing

Figure 2. Codec Ready from Start-up or Fault Condition

Figure 3. Clocks

Figure 4. Data Setup and Hold

Figure 5. PR4 Powerdown and Warm Reset

Figure 6. Test Mode

2. GENERAL DESCRIPTION

2.1 AC-Link

Figure 7. AC-link Connections

2.2 Control Registers

2.3 Sample Rate Converters

2.4 Mixers

2.5 Input Mux

2.6 Volume Control

2.7 Dedicated Mic Record Path

Figure 8. CS4205 Mixer Diagram

3. DIGITAL SIGNAL PATHS

3.1 Analog Centric Mode

Figure 9. Digital Signal Path Overview

3.2 Digital Centric Mode

3.3 Host Processing Mode

3.4 Multi-Channel Mode

Ta ble 1. AC Mode Control Configurations

Figure 10. Analog Centric Mode

Figure 12. Host Processing Mode

Figure 11. Digital Centric Mode

Figure 13. Multi-Channel Mode

4. AC-LINK FRAME DEFINITION

Figure 14. AC-link Input and Output Framing

4.1 AC-Link Serial Data Output Frame

4.2 AC-Link Serial Data Input Frame

5. REGISTER INTERFACE

Table 2. Register Overview for the CS4205