Cirrus Logic CS35L32 User Manual

Class D Power Stage

SPKR SU PPLY

GNDPLED

Current Mode Synchronous Boost Controller

VCOM

Range

Scaling

Class D Front End

Short C ircuit Prot ection

∆Σ Class D Modulator

REF

Generation

Bandgap

Voltage

Generation

FILT+

VREF

ISENSE+ ISENSE–/

VSENSE+

GNDA

SCLKLRC K

Soft Ramp

Level Shifters

I²C Control Port

SDASCLSCLK LRCK SDOUT

MCLK

IN–

–

9 ,12 ,15, or 18 dB + Mute

IN+

Flash LED Current Driver

Control,

Sensing,

and Fault

Protection

FLOUT1 FLOUT2/AD0FLEN FLINH

SPKOUT+ SPKOUT–/

VSENSE–

I2C Class G Ov erride

Wat chdog

Error

GNDP

VSENSE–

VSENSE+

ISENSE–

ISENSE+

SPKR

SUPPLY



ADC

Serial Audio/Data Port

Serial Port

Cloc k Generation

RESET INT

VMON ADC

Front End

IMON ADC

Front End

Low Bat tery M anagement

Class G

VBST

Current

Sense

IREF+SW

Power

Budgeting

Temperature

Sensor

Overt emp Protect ion



ADC



ADC

CS35L32

Boosted Class D Amplifier with Speaker-Protection Monitoring

and Flash LED Drivers

Mono Class D Speaker Amplifier

• Two-level Class G operation:

• Boosted: 5 V nominal

• Bypassed: battery voltage is supplied directly

• 2.5-mA quiescent current, monitors powered down

• 1.7 W into 8 (@ 10% THD+N)

• 102-dB signal-to-noise ratio (SNR, A-weighted)

• Idle channel noise 25 Vrms (A-weighted)

• 90% efficiency

Audio Input and Gain

• One differential analog input

• Speaker gain:

• 9, 12, 15, and 18 dB and mute

• Pop suppression, zero-crossing detect transitions

Flash LED Drivers

• Integrated dual LED drivers using the following:

• Boost supply output voltage

• Dual matched current regulators, 750 mA max each

• Programmable setting for Flash Mode current: 50–750 mA, in 50-mA steps

• Programmable setting for Flash-Inhibit Mode current: 50–350 mA, in 50-mA steps

• Programmable setting for Movie Mode current: 150, 120, 100, 80, 60, 40, 20 mA

• Programmable flash timer setting: 50–500 ms, in 25-ms steps

• Dedicated pin for flash trigger (FLEN)

• Dedicated pin for flash inhibit (FLINH)

• Thermally managed through boost-voltage regulation

(Features continue on page 2)

http://www.cirrus.com

JUL ‘14

DS963F4

CS35L32

Monitors and Protection

•Protection:

• Latched overtemperature shutdown

• Latched amplifier output short circuit shutdown

• LED short or open detection and LED driver shutdown

• Flash inhibit LED current reduction

• Low battery flash LED current reduction

• VP undervoltage lockout (UVLO) shutdown

• Programmable boost inductor current limiting

• Audio and LED shutdown upon stopped MCLK, with autorecovery

• Interrupt driven error reporting

• Speaker current and voltage monitoring:

• 16-bit resolution

• 60-dB dynamic range (unweighted) for voltage

• 56-dB dynamic range (unweighted) for current

• Bused over I

• Battery voltage monitoring:

• 7-bit resolution

• Bused over I

• System reset

S bus

S and I2C bus

I2C Control Settings and Registers

• Low-power standby

• LED and audio power budgeting programmable settings

• Boost inductor current limit programmable setting

• Speaker programmable settings:

• Pop suppression through zero-crossing transitions

• Gain and mute

• Battery voltage monitor register, 8 bits

• LED driver programmable settings:

• Flash current register

• Flash inhibit current register

• Movie Mode current register

• Flash timer register

• Error status bit, including the following:

• Stopped MCLK error

• Low battery detection with programmable thresholds

• VP UVLO error

• Overtemperature warning

• Overtemperature error

• Boost converter overvoltage error

• Boost inductor current-limiting error

• Amplifier short-circuit error

• Shorted or open LED error

I2S Reporting

• Monitoring:

• Speaker voltage monitor

• Speaker current monitor

• Battery voltage monitor

• Error reporting:

• VP UVLO shutdown error

• Overtemperature warning

• Overtemperature error

• Boost converter overvoltage error

• Boost inductor current limiting error

• Amplifier short-circuit error

• Speaker voltage monitor overflow error

• Speaker current monitor overflow error

• Battery voltage monitor overflow error

• Status reporting:

• Power-down done

• LED flash event

• LED Movie Mode event

• Flash timer on

Package

• 30-ball WLCSP

Applications

• Smart phones

•Tablets

General Description

The CS35L32 is a low-quiescent power-integrated audio IC, with a mono full-bridge Class D speaker amplifier operating with a self-boosted Class G supply. Audio input is received differentially. Pop-and-click reduction is achieved with zerocrossing transitions at turn-on, turn-off and upon gain changes. Communication with the host processor is done using an

interface. In addition, an I2S bus is used to send monitor and status data.

When two CS35L32 devices are available on the same board, each is identified by its I or upon deasserting RESET

The speaker amplifier, using closed-loop  modulation, achieves low levels of distortion. Class D amplifier efficiency allows operation at higher speaker power levels without generating excessive heat and without wasting power. Automatic Class G operation using a boosted supply to the speaker allows for even higher powers and higher crest factor. With a boosted speaker supply, operation at a fixed 5 V is achieved independently of line supplied battery voltage. The user can disable Class G operation.

2 DS963F4

, each CS35L32 reads the AD0 pin logic level and configures its I2C device address.

C chip address. Upon power-up

CS35L32

The battery voltage, speaker voltage, and speaker current signals are monitored, digitized using  converters, and serialized over an I externally to the CS35L32. Outgoing data is sent over I monitor data is accessible through I

S bus. The speaker monitoring signals are part of a speaker-protection algorithm that is managed

S with the CS35L32 in Slave or Master Mode. Battery voltage

An integrated dual LED driver operates up to two LEDs in Flash Mode or Movie Mode. A flash event is triggered by an external signal. A flash-inhibit event is triggered by an external signal, and causes a reduction in flash current. A timer is provided for flash and flash inhibit events. Movie Mode operation has no timer and starts and ends via an I Flash and Movie Mode current levels, as well as the flash timer are I

C programmable.

C command.

Total power consumption when powering LEDs in Flash Mode or Movie Mode, and powering audio simultaneously, is managed by the user’s choices in programming the current limit and in power budgeting. The primary goal is to manage audio and LED loads so the boost converter is not current limited and so the CS35L32 does not shut down due to overheating.

A latched shutdown of the audio amplifier occurs in the event of an output short pin to ground, pin to supply, or pin to pin. A latched shutdown of the CS35L32 also occurs on overtemperature. An LED driver shutdown occurs in the event of a shorted or open LED. The CS35L32 shuts down in the event of a battery (VP) undervoltage and autorecovers when the battery voltage recovers. The CS35L32 shuts down in the event of a stopped MCLK and autorecovers when MCLK recovers.

The CS35L32 responds to detection of a low battery in the presence of a flash event by reducing flash current and autorecovers when the battery voltage recovers.

The CS35L32 is reset by asserting RESET

. CS35L32 power up and power down are managed through the RESET pin.

The CS35L32 is available in a 30-ball WLCSP package in the temperature range –10 to +70°C.

DS963F4 3

Table of Contents

Table 3-1. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 8

Table 3-2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3-3. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3-4. Boost Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . 9

Table 3-5. LED Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3-6. Speaker Amplifier Output Characteristics . . . . . . . . . . . . . . 10

Table 3-7. Signal Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . 11

Table 3-8. Digital Interface Specifications and Characteristics . . . . . . . 11

Table 3-9. PSRR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3-10. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3-11. Switching Specifications: Power, Reset, Master Clocks . . 12 Table 3-12. Switching Specifications: ADSP in I

S Mode . . . . . . . . . . . 13

Table 3-13. Switching Specifications: I²C Control Port . . . . . . . . . . . . . 14

4.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3 Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.4 Low-Battery Management . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . 18

4.6 Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.7 Die Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.8 Signal Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.9 LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.10 Power Budgeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.11 Audio/Data Serial Port (ADSP) . . . . . . . . . . . . . . . . . . . . . . 24

4.12 Signaling Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.13 Device Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.14 Control Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 Required Reserved Register Configuration . . . . . . . . . . . . . 32

5.2 Avoiding Current Transients when Issuing a Flash Event . . 32

5.3 External Component and PCB Design Considerations—EMI Out-

put Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4 PCB Routing Considerations for Thermal Relief . . . . . . . . . 33

5.5 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Register Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 Device ID A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Device ID C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 Device ID E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.4 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.5 Power Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.6 Power Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.7 Clocking Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.8 Low Battery Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.9 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.10 Boost Converter Peak Current Protection Control . . . . . . . 38

7.11 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.12 LED and Audio Power-Budget Management . . . . . . . . . . . 38

7.13 ADSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.14 Class D Amplifier Control . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.15 Protection Release Control . . . . . . . . . . . . . . . . . . . . . . . . 39

7.16 Interrupt Mask 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.17 Interrupt Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.18 Interrupt Mask 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.19 Interrupt Status 1 (Audio) . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.20 Interrupt Status 2 (Monitors) . . . . . . . . . . . . . . . . . . . . . . . . 42

7.21 Interrupt Status 3 (LEDs and Boost Converter) . . . . . . . . . 42

7.22 LED Lighting Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.23 LED Flash Mode Current . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.24 LED Movie Mode Current . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.25 LED Flash Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.26 LED Flash Inhibit Current . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8 Typical Performance Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1 System-Level Efficiency and Power-Consumption Plots . . . 45

8.2 Audio Output Typical Performance Plots . . . . . . . . . . . . . . . 46

8.3 Monitoring Typical Performance Plots . . . . . . . . . . . . . . . . . 47

9 Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

CS35L32

4 DS963F4

1 Pin Descriptions

A1A2A3

A4A5A6B1B2B3B4B5B6

C1C2C3C4C5C6D1D2D3D4D5D6E1E2E3E4E5

General Ground

LED Digital I/O

Power Supply

Boost Converter

Audio

Digital I/O

CS35L32

1 Pin Descriptions

‘‘‘

‘

SDA SCL SDOUT SCLK MCLK FLOUT2/

‘‘‘‘‘

AD0

VP INT RESET LRCK GNDPLED FLOUT1

‘‘‘‘‘

SW GNDP GNDP FLINH GNDA VA

‘‘‘‘‘

SW SPKOUT+ SPKOUT–/

‘‘‘‘‘

VSENSE–

FLEN IREF+ FILT+

VBST SPKRSUPPLY IN– IN+ ISENSE–/

VSENSE+

Figure 1-1. Top-Down (Through-Package) View—30-Ball WLCSP Package

Table 1-1. Pin Descriptions

Ball Name

Ball

Number

SDA A1 VA I/O I

Power

Supply

I/O Ball Description

Serial Data Input. Serial data for the I2C

serial port

SCL A2 VA I I

Clock Input. Serial clock for the I2C serial

port

MCLK A5 VA I Master Clock Source. Clock source for A/D

converters and audio/data serial port (ADSP). MCLK blocks (see Section 4.13 and Section 7.7).

, derived from MCLK, is used for other

INT

SCLK A4 VA I/O Serial Clock. Serial shift clock for the serial

audio interface

LRCK B4 VA I/O Left Right Clock. Determines which channel,

left or right, is currently active on the serial audio/data lines

SDOUT A3 VA O Serial Audio/Data Output. I²S serial data

output used to monitor voltage and current of SPKOUT signal and VP levels

INT

B2 VA O Interrupt. Programmable, open-drain, active-

low programmable interrupt output

Internal

Connection

Weak pulldown (~1 M

Weak pull-down (~1 M

ISENSE+

Driver Receiver

—CMOS

open-drain output

Hysteresis on CMOS input

——Hysteresis

State at

Reset

Hi-Z

Hi-Z on CMOS input

— Hysteresis

on CMOS

Pulled

down input

CMOS output

Hysteresis on CMOS

Pulled

down input

CMOS output

Hysteresis on CMOS

Pulled

down input

CMOS output

—CMOS

— Pulled

down

—Hi-Z open-drain output

DS963F4 5

RESET

LED

Boost Converter

Audio

Power Supply

General Ground

Ball Name

Table 1-1. Pin Descriptions (Cont.)

Ball

Number

Power

Supply

B3 VA I Reset. When asserted, the device enters a

I/O Ball Description

low-power mode, outputs are set to Hi-Z, and I²C register values are set to defaults. Outputs are Hi-Z except those with weak pull-ups or pull-downs as mentioned.

1 Pin Descriptions

Internal

Connection

— — Hysteresis

Driver Receiver

CS35L32

State at

Reset

Low

on CMOS

input

FLEN D4 VA I Flash Enable. Input signal commanding a

FLINH C4 VA I Flash Inhibit. Input signal determining

FLOUT1 B6 SPKR

SUPPLY

FLOUT2/AD0 A6 SPKR

SUPPLY

VBST E1 — O Boost Converter Output. Output of boosted

SPKRSUPPLY E2 — I Speaker Supply. Full-bridge Class D speaker

SW C1, D1 VBST I Boost Converter Switch Node. Connects the

IREF+ D5 VA I Current Reference Resistor. Connection for

flash event into both LEDs. It is asserted high.

whether the LEDs are in Flash Mode (logic low) or Flash-Inhibit Mode (logic high, LED current reduced).

O LED Driver 1. Output driving LED 1 by sinking

current from the LED cathode

I/O LED Driver 2/Address Zero. Output driving

LED 2 by sinking current from the LED cathode. AD0 programs the chip address when RESET tying the pin to ground clears the chip address LSB. Otherwise, the LSB is set.

supply. This pin cannot be used to drive any external loads other than the on chip Class D Amplifier and Flash LEDs.

amplifier power supply.

inductor to the rectifying switch.

an external resistor to be used for generating the CS35L32’s internal main current reference. See Fig. 2-1 for required resistor value.

is deasserted. If no LED is used,

Weak pulldown (~1 M

Weak pull-up (~1 M

————

——

————

— Hysteresis

on CMOS

input

— Hysteresis

on CMOS

input

— — SPKR

Pulled down

SUPPLY

IN+ E4 SPKR

IN– E3 SPKR

SPKOUT+ SPKOUT–/VSENSE–D2D3

ISENSE+ ISENSE–/VSENSE+E6E5

FILT+ D6 VA O Positive Voltage Reference. Positive

VA C6 — I Analog Input Power. Power supply for

VP B1 — I Boost Converter Input Power. Power supply

GNDA C5 — Analog Ground. Ground reference for the

GNDP C2, C3 — Power Ground. Ground reference for boost

GNDPLED B5 — LED Power Ground. Ground reference for

SUPPLY

SPKR

SUPPLY

SPKR

SUPPLY

I Input 1 Differential Positive Line. Positive

analog input

I Input 1 Differential Negative Line. Negative

analog input

O Speaker Differential Audio Output. Internal

Class D speaker amplifier output. SPKOUT– serves as voltage monitor negative sense pin (VSENSE–).

I Current Sense Inputs. Sense voltage across

an external resistor in series with SPKOUT+. ISENSE– serves as voltage monitor positive sense pin (VSENSE+).

reference for internal circuits

internal analog section

or battery voltage powering boost converter

internal analog section of the IC

converter and Class D amplifier’s output stage

LED current return. Should be tied to ground plane.

————

———Hi-Z

————

6 DS963F4

2 Typical Connection Diagram

Batter y

1 H

OUT

0.1 

0.1 F

BST

44.2 k

BST_SNS

8 

OUT

Applications

Processor

0.1 F

10 F

BST

RPRPRP_

PMU

10 F

0.1 F

4.7 F

Line Input 1

CS35L32

ISENSE–/

VSENSE +

SPKOUT+

ISENSE+

IREF+

SPKOUT–/

VSENSE–

VBST

GNDP

FLOUT1

FLOUT2 / AD0

GNDPLED

SPKRSUPPLY

SDOUT

LRCK

SCLK

MCLK

FLEN

FLINH

SCL

SDA

INT

RESET

FILT+

GNDA

IN+

IN–

VP SW

3.0–5.25 V

1.71–1.89 V

10 F

Notes:

• All external passive component values are nominal values. Key for capacitor types required: * Use low ESR, X7R/X5R capacitors. ** Use low ESR, X7R capacitors. If no type symbol is shown next to a capacitor, any type may be used.

• As required, add protection circuitry to ensure compliance with the absolute maximum ratings in Tab le 3 -2 .

1. C

BST

is a ceramic capacitor and derates at DC voltages higher than 0 V. In this application, the capacitor should not derate to a value lower

than 4 F across the specified boost output voltage in Tab le 3 -4 . Capacitor tolerance and the temperature coefficient should also be taken into account to guarantee the 4-F value.

2. Minimum pull-up resistor values are selected in accordance with the Table 3-8 V

specification. Maximum pull-up resistances are selected

based on load capacitance and relevant switching specs (Table 3-13).

3. Select each capacitor to be 0.22 F for an 18-Hz passband @ 12-dB amplifier gain, for a 3-dB roll-off. The equation for calculating the capacitance for a given passband is C = 1/( * f * R

INDIF

), where C is in F, R

INDIF

is the differential input resistance in and f is in Hz (see

the differential input resistance specification in Tab l e 3- 3). Signals IN+ and IN– are subject to the recommended ranges in Table 3-1.

4. R

BST_SNS

is inherently tied to the accuracy of the BST_IPK current limit. A resistor with a 0.1% tolerance is required for this component to

meet the specified IMAX(B) max and min values in Table 3-4.

5. The required tolerance on the 0.1- ISENSE resistor is 1%. The required temperature coefficient is ±200 ppm/°C.

6. C

OUT

capacitors are optional EMI suppressors used with CS35L32 edge-rate control, depending on application requirements. Because

switching losses increase linearly with increases to these capacitances, it is recommended that C

OUT

values not exceed 2 nF. The

recommended value is 470 pF.

7. LED and I

C addressing options:

VBST VBST

c) AD0 = 1 d) AD0 = 0b) AD0 = 1a) AD0 = 1

VBST VBST

FLOUT1 FLOUT2 FLOUT1 FLOUT2 FLOUT1 FLOUT2FLOUT1 FLOUT2

See Note 7 for LED and I

C addressing

options.

Note 1

Note 3

Note 2

Note 5

Note 4

Note 6

CS35L32

2 Typical Connection Diagram

Figure 2-1. Typical Connection Diagram

DS963F4 7

CS35L32

3 Characteristics and Specifications

Table 3-1. Recommended Operating Conditions

GNDA = GNDP = 0 V, all voltages with respect to ground. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.

Parameters Test Conditions Symbol Min Max Units

DC power supply Analog (and digital I/O and core) — VA 1.71 1.89 V

Battery — VP 3.0 5.25 V External voltage applied to analog inputs powered by VA (IREF+, FILT+) External voltage applied to analog inputs powered by SPKRSUPPLY (IN+,

IN–, ISENSE+, ISENSE–,VSENSE+, VSENSE–) External voltage applied to digital inputs — V Ambient temperature — TA –10 +70 °C

1.The maximum overvoltage/undervoltage is limited by the input current.

Table 3-2. Absolute Maximum Ratings

GNDA = GNDP = 0 V; all voltages with respect to ground. Operation at or beyond these limits may permanently damage the device.

Parameters Test Conditions Symbol Min Max Units

DC power supply Analog — VA –0.3 2.22 V

Input current

Ambient operating temperature (local to device, power applied) — T Junction operating temperature (power applied) — T Storage temperature — T

1.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins do not cause SCR latch up.

Table 3-3. DC Characteristics

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, GNDA = GNDP = 0 V, TA = +25°C.

Parameters Symbol Test Conditions Min Typical Max Units

Differential Input resistance (IN+ to IN–) R

FILT+ voltage — — — VA — — Overtemperature shutdown threshold T Overtemperature warning threshold T Overtemperature warning threshold deviation — — — ±10 — °C Low battery threshold — LOWBAT_TH = 00

Low-battery recovery threshold — LOWBAT_RECOV = 001

VP undervoltage lockout threshold (VP falling) UVLO — — 2 — V VP undervoltage lockout hysteresis — — — 100 — mV

—V —V

INAS

INSS

INDI

–0.3 VA + 0.3 V –0.3 SPKRSUPPLY + 0.3 V

–0.3 VA + 0.3 V

Battery — VP –0.3 6.0 V

—IIN—±10mA

–40 +115 °C –40 +150 °C –65 +150 °C

— — — —

63 51 40 31

— — 150 — °C — — 135 — °C

—

3.10

—

3.20

—

3.30

—

3.40

—

3.20

—

3.30

—

3.40

—

3.50

—

3.60

INDIF

WRN

STG

Amp gain = 9 dB Amp gain = 12 dB Amp gain = 15 dB Amp gain = 18 dB

LOWBAT_TH = 01 LOWBAT_TH = 10 LOWBAT_TH = 11

LOWBAT_RECOV = 010 LOWBAT_RECOV = 011 LOWBAT_RECOV = 100

LOWBAT_RECOV = 101–11x

— — — —

— — — — —

k k k k

V V V V

V V V V V

8 DS963F4

CS35L32

3 Characteristics and Specifications

Table 3-4. Boost Converter Characteristics

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, amp gain = 12 dB, GNDA = GNDP = 0 V, TA = +25°C, MCLK = 6 MHz. MCLK

is explained in Section 4.13.1 and Section 7.7.

INT

Parameters Symbol Test Conditions Min Typical Max Units

Boost output voltage VBST Boosting

Bypass

Boost output voltage tolerance VBST No load: I Load regulation V Line regulation V Boost FET peak-current limit

(See Section 7.10.)

MAX(B)

3.0 V < VP < 4.2 V; I

(Load)

(Line)

3.0 V< VP < 4.2 V; I

LOAD

BST_IPK = 0000 0000 BST_IPK = 0010 0000 BST_IPK = 0100 0000

LOAD

= 0.25A to1.5 A — 60 — mV/A

= 0 A, 500 mA — 40 — mV/V

LOAD

BST_IPK = 0110 0000 BST_IPK = 1000 0000

Output switching frequency

Boost FET ON resistance R Boost FET ON resistance temp coefficient — I Rectifying FET ON resistance R Rectifying FET ON resistance temp coefficient I Overvoltage detection threshold V Threshold Class G On, IN+ to IN– V Threshold Class G Off, IN+ to IN– V

SW(B)

DS(ON)B

DS(ON)R

OVTH

IN1THON

IN1THOF

OUT(B)

Boost enabled — 5.5 5.7 V

VBST = VP = 3.6 V — 0.60 — V

VP = 3.6 V, VBST = 5 V — 0.33 — V Minimum Class G boost ON hold-off time — VP = 3.6 V, VBST = 5 V — 800 Operating efficiency

1.MCLKDIV2 (see p. 37) should be configured so MCLK

2.Minimum Class G boost ON hold-off time is determined from when the low audio detection is latched until when the boost is turned off. The latching mechanism occurs in 800-ms intervals. If the audio level is detected as low between two sequential latches, the hold-off time is extended by the difference between when the detection occurs and the subsequent latch pulse. This may extend the hold-off time up to 1.6 s in extreme cases.

3.Efficiency specified here assumes the boost converter drives an external resistive load via the VBST pin, instead of the onboard Class D amplifier.

Table 3-5. LED Drive Characteristics

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, GNDA = GNDP = GNDPLED = 0 V, TA = +25°C.



is 6 or 6.1440 MHz (see Table 4-14) for boost-converter operation at 2 or 2.05 MHz.

INT

VBST = 5 V, I

OUT(B)

= 500 mA

=1.5 A——

VP*1.15

—

5.4 —

=0 mA –5 — +5 %

— — — — —

—— MCLK

2.89

3.30

3.72

4.14

4.56 /3 — MHz

INT

— — — — —

= 1 A — 80 — m = 1 A — 0.2 — %/oC = 1 A — 150 — m = 1 A — 0.2 — %/oC

90 85

—ms —

—

Parameters Min Typical Max Units

Flash Mode current settings, per LED (Step size = 50 mA)

Flash Inhibit Mode current settings, per LED (Step size = 50 mA)

Movie Mode current settings, per LED

LED_FLCUR = 1111

…

LED_FLCUR = 0001

LED_FLINHCUR = 0111

…

LED_FLINHCUR = 0001

LED_MVCUR = 111 LED_MVCUR = 110 LED_MVCUR = 101 LED_MVCUR = 100 LED_MVCUR = 011 LED_MVCUR = 010 LED_MVCUR = 001

— … —

— — — — — — —

750

… 50

350

… 50

150 120 100

80 60 40 20

— … —

— — — — — —

— LED current accuracy –10 — +10 % LED current matching —10—% Flash timer (t

) MCLK

flash

MCLK

= 6 MHz 2; TIMER = 1 0010–1 1111

INT

TIMER = 0 0001 TIMER = 0 0000

= 6.144 MHz; TIMER = 1 0010–1 1111

INT

TIMER = 0 0001 TIMER = 0 0000

— — — — — —

500

75 50

488.3

73.2

48.8

—

— LED flash timer accuracy 0—+1ms LED flash inhibit time (FLINH high to LED current 3% settling) — 40 — s

1.Flash or Movie Mode current is delivered from the boost converter’s output, which provides a voltage higher than the LED voltage. Depending on the LED voltage requirement and on VP supply voltage, the boost converter is internally controlled to boost or be in bypass (rectifying FET fully on).

2.The flash time setting is generated from MCLK

. MCLKDIV2 (see p. 37) should be configured so MCLK

INT

is 6 or 6.1440 MHz. See Table 4-14.

INT

V V

A A A A A

% %

…

mA mA

…

mA mA

mA mA mA mA mA mA

ms ms ms ms ms ms

INT

DS963F4 9

CS35L32

Generic Simulated

Speaker Load

SENSE

0.1 

Audio Precision AP2700

Audio Analyzer

Audio Precision AUX-0025 Filter

SPKOUT+

ISENSE+

SPKOUT–

ISENSE–/ VSENSE+

VSENSE–

SPKRSUPPLY

5 V

3.6 V

1.8 V

8 

33 H

3 Characteristics and Specifications

Table 3-6. Speaker Amplifier Output Characteristics

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, 1-kHz input, amp gain = 12 dB, GNDA = GNDP = 0 V, TA = +25°C, measurement bandwidth is 20 Hz to 20 kHz, Fs = 48 kHz, MCLK

Parameters Symbol Test Conditions Min Typical Max Units

Continuous average power delivered to load

Po 8- load, THD 10%

THD+N THD+N 8- load, 1.0 W — 0.02 — % Input voltage @ 1% THD+N V

ICLIP

Signal to noise ratio SNR Referenced to output voltage @1% THD+N, A-weighted — 102 — dB Idle channel noise ICN VBST = VP, A-weighted — 25 — Vrms Common-mode rejection ratio CMRR V Frequency response FR 20 Hz to 20 kHz, No input DC blocking caps –0.1 0 0.1 dB Efficiency



Class D amplifier gain — AMP_GAIN = 000 (mute)

N-FET ON resistance R P-FET ON resistance R Output DC offset voltage V Time from shutdown to audio out t

DS ON,N

DS ON,P

OFFSET

SD RESET

1.Power delivered to the speaker from the 0.1- load side terminal (refer to Fig. 2-1).

2.Efficiency collected using a 5-V external supply, as shown in the drawing. For this test, the VBST pin should not be connected to the SPKRSUPPLY pin.

= 6 MHz. MCLK

INT

is explained in Section 4.13.1 and Section 7.7.

INT

1.75

8- load, THD 1%——

1.45——WW

8- load — 0.84 — Vrms

ripple

= 1 VPP, f

= 217 Hz — 55 — dB

ripple

8- load 33 H, 1.7 W — 91 — %

AMP_GAIN = 001 AMP_GAIN = 010 AMP_GAIN = 011 AMP_GAIN = 100

= 0.5 A — 185 — m

FET

= 0.5 A — 205 — m

FET

–80 — — — —

12 15 18

— — — — —

dB dB dB dB dB

—

Inputs AC coupled to ground — ±5 — mV

deasserted, zero-crossing disabled — 15 — ms

10 DS963F4

CS35L32

VSENSE+

217 Hz

500 mV

DC Offset = 0

VSENSE–

3 Characteristics and Specifications

Table 3-7. Signal Monitoring Characteristics

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, amp gain = 12 dB, 0.1- sense resistor, GNDA = GNDP = 0 V, T

= +25°C. Measurement bandwidth is 20 Hz to 20 kHz, Fs = 48 kHz, Input Signal = 1 kHz, MCLK

and Section 7.7.

Parameters Min Typical Max Units

General ADC characteristics Power-up time: t VSENSE± monitoring

characteristics (VMON)

Dynamic range (unweighted), VSENSE± = ±5.0 V (10 V

Total harmonic distortion + noise, –3.8 dBFS

Full-scale signal input voltage 6.59•VA 6.94•VA 7.29•VA V

Common-mode rejection ratio (217 Hz @ 500 mVPP)

ISENSE± monitoring characteristics (IMON)

Dynamic range (unweighted), ISENSE± = ±0.625 A (1.25 A

Total harmonic distortion, –29.5 dBFS

Full-scale signal input voltage 1.56•VA 1.64•VA 1.72•VA V

VMON-to-IMON isolation

VP monitoring characteristics Data width — 8 — Bits

Voltage resolution (See the equation in Section 4.8.4.) — 35.3 — mV

(FF code) signal input voltage (VP) 2.89•VA 3.05•VA 3.20•VA V

VPMON = 1011 0011 VPMON = 1011 0100

VPMON = 1111 1111 VPMON = 0000 0000

1.Typical value is specified with PDN_AMP and PDN_xMON bits initially set. Maximum power-up time is affected by the actual MCLK

2.Parameters given in dB are referred to the applicable typical full-scale voltages. Applies to all THD+N and resolution values in the table

3.VSENSE± THD is measured with the Class D amplifier as the audio source connected to an 8- + 33H speaker load, supplied by a 6.3-VPP, 1-kHz

sine wave, operating under the typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –3.8-dBFS VMON output. Larger Class D amplifier amplitudes begin to exhibit clipping behavior, increasing distortion of the signal supplied to VSENSE±

4.CMRR test setup for VSENSE±:

= 6 MHz, MCLK

INT

PUP(ADC)

is explained in Section 4.13.1

INT

—8.5

[1]

Data width — 16 — Bits

)— 60 — dB

— –60 — dB

—60—dB

Group delay

—7.6/Fs— s

Data width — 16 — Bits

)— 56 — dB

— –45 — dB

—56—dB

Group delay

—7.6/Fs— s

…

— — … — —

2.8

2.835 …

5.482

5.518

— — … — —

frequency.

INT

V V

…

V V

5.VMON group delay is measured from the time a signal is presented on the VSENSE± and pins until the MSB of the digitized signal exits the serial port. Fs is the LRCK rate.

6.For reference, injecting a 125-mVpp fully differential sine wave into the ISENSE± pins (equivalent to a ±0.625 A current with a 0.1- ISENSE resistor) produces an IMON output of –29.5 dBFS (since typical full-scale is 1.64*VA, in V

amplifier as the audio source, which is connected to an 8- + 33-H speaker load, supplied by a 7.0-V

). ISENSE± monitoring THD is measured using the Class D

, 1-kHz sine wave, operating under the

typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –29.5-dBFS amplitude IMON output. Larger Class D amplifier amplitudes begin to exhibit clipping behavior, increasing the distortion of the signal supplied to ISENSE±.

7.VMON-to-IMON isolation is the error in the current sense due to VMON, expressed relative to full-scale sense current in decibels.

8.IMON group delay is measured from when a signal is presented on the ISENSE± pins until the MSB of the digitized signal exits the serial port. Fs is the LRCK rate.

Table 3-8. Digital Interface Specifications and Characteristics

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, GNDA = GNDP = 0 V, TA = +25°C.

Parameters Symbol Test Conditions Min Max Units

Input leakage current (per pin)

1,2

MCLK, SCLK, SDOUT

SCL, SDA, Input capacitance I VA logic I/Os High-level output voltage V

Low-level output voltage V

High-level input voltage V

Low-level input voltage V

1.Specification includes current through internal pull up/down resistors, where applicable (as defined in Section 1).

2.Leakage current is measured with VA = 1.80 V, VP = 3.60 V, VBST = 3.60 V, and RESET

3.For the ADSP output SDOUT and potential outputs SCLK and LRCK (if M/S = 1), if ADSP_DRIVE = 0 see Section 7.13, IOH and I

+100 A. If ADSP_DRIVE = 1, I

and I

FLOUT2/AD0

FLEN, FLINH, LRCK

, RESET

INT

All outputs, IOL = 67/100 A

IOH = –67/–100 A

, SDA, IOL = 3 mA——

INT

— — — —

±7.5 ±4.5 ±4.5 ±0.1

A A A A

— — 10 pF

VA– 0.2 — V

0.20

0.4

V —0.70•VA — V — — 0.30•VA V

asserted. Each pin is tested while driven high and low.

are –100 and

are –67 and +67 A. For other, non-ADSP_DRIVE-affected outputs, IOH and IOLare –100 and +100 A.

DS963F4 11

CS35L32

MIN

GND

Internal supplies stable

OPERATING

RH(PWR-RH)tIRS

Control po rt active

RS(RL-PWR)

RESET

PWR-RUD

PWR-

RUD

PWR-RUD

Suppl y

Last

Suppl y

Supply

Down

Last

Supply

Down

3 Characteristics and Specifications

Table 3-9. PSRR Characteristics

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = VP, amp gain = 12 dB, GNDA = GNDP = 0 V, TA = +25°C.

Parameters Conditions

Speaker amplifier

VBST = VP VA SPKOUT± 100 217

Noise

Injected Into

PSRR

VP SPKOUT± 100 217

VPMON PSRR VBST = VP VA SDOUT 100 217

VSENSE± PSRR

VBST = VP VA SDOUT 100 217

ISENSE± PSRR VBST = VP VA SDOUT 100 217

1.The speaker voltage monitor has a lower PSRR because its input path has an attenuation of 16.6 dB. The PSRR specification is referred to the input signal and, as such, includes the loss of 16.6 dB.

Table 3-10. Power Consumption

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = VP, GNDA = GNDP = 0 V, TA = +25°C.

Use Configuration

Powered up

PDN_BST = 00)

(

RESET asserted, MCLK, SCLK, LRCK inactive

IN+ IN– shorted to ground, LEDs off, monitors powered down IN+ IN– shorted to ground, LEDs off, monitors powered down IN+ IN– shorted to ground, LEDs off, monitors powered up IN+ IN– shorted to ground, LEDs off, monitors powered up

Boost Mode bypass

PDN_BST = 01)

( .

RESET

asserted, MCLK, SCLK, LRCK inactive

1.Refer to Section 7.6 for configuring monitor power down

Table 3-11. Switching Specifications: Power, Reset, Master Clocks

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, TA = +25°C, GNDA = GNDP = 0 V. Fig. 2-1 shows typical connections; GNDA = GNDP = 0 V. Section 9 describes some parameters in detail; input timings are measured at V are measured at V

Power supplies

Reset

Master clocks MCLK frequency

1.Power and reset sequencing

and VOH thresholds (see Table 3-8).

Parameters Symbol

Power supply ramp up/down t

RESET low (logic 0) pulse width

RESET

MCLK duty cycle D

hold time after power supplies ramp up

setup time before power supplies ramp down

rising edge to control-port active

Noise

Measured On

Noise

Amplitude (mV)

OUT

Noise

Frequency (Hz)

20k

Min Typical Max Units

— — — — — — — — — — — — — — —

75 75 70 70 70 55 36 36 33 60 60 50 60 60 60

— — — — — — — — — — — — — — —

Typical Current

11A

No C

3270 390 A

OUT

= 470 pF (See Fig. 2-1) 4275 390 A

No C

= 470 pF See Fig. 2-1) 4360 1435 A

OUT

3360 1435 A

OUT

11A

No C

1983 390 A

OUT

= 470 pF (See Fig. 2-1) 3093 390 A

No C

= 470 pF See Fig. 2-1) 3185 1435 A

OUT

PWR-RUD

RLPW

RH(PWR-RH)

RS(RL-PWR)

IRS

MCLK

2074 1435 A

OUT

and VIH thresholds; output timings

Min Max Units

— 100 ms

1—ms

[3]

—ns

— 12.3 MHz

45 55 %

dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB

Units

2.VP supply may be applied or removed independently of RESET and the other power rails. See Section 4.1 for additional details.

3.The RESET rising-edge-to-control-port-active timing, t

4.Maximum frequency for highest supported nominal rate is indicated. The supported nominal serial port sample rates are found in Section 4.11.2.

, is specified in Table 3-13.

irs

12 DS963F4

CS35L32

LRCK

SCLK

SDOUT

P

Note:

 = “S” or “M”

S(LK-SK)

H(SK-LK)

DataValidStrt

DataValidEnd

DataValidWind

3 Characteristics and Specifications

Table 3-12. Switching Specifications: ADSP in I2S Mode

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, TA = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 = VA; C at V

Slave Mode Input sample rate (LRCK)

Master Mode OUTPUT sample rate (LRCK)

1.ADSP timing in I2S Mode

= 30 pF. Section 9 describes some parameters in detail; input timings are measured at VIL and VIH thresholds; output timings are measured

LOAD

and VOH thresholds (see Table 3-8).

Parameters Symbol

Min Max Units

Fs — 49 kHz LRCK duty cycle — 45 55 % SCLK frequency 1/t

— 64•Fs Hz SCLK duty cycle — 45 55 % LRCK setup time before SCLK rising edge t LRCK hold time after SCLK rising edge t SDOUT time from SCLK to data valid start SDOUT time from SCLK to data valid end

SS(LK–SK)

HS(SK–LK)

DataValidStrt

DataValidEnd

Fs —

40 — ns

20 — ns

— 300 ns

155 — ns

[4]

LRCK duty cycle — 45 55 % SCLK frequency 1/t SCLK duty cycle RATIO = 0

RATIO = 1 LRCK setup time before SCLK rising edge t LRCK hold time after SCLK rising edge t SDOUT time from SCLK to data valid start SDOUT time from SCLK to data valid end

[5]

SM(LK–SK)

HM(SK–LK)

DataValidStrt

DataValidEnd

— —

— 64•Fs Hz 45

67 35 — ns 20 — ns — 300 ns

155 — ns

kHz

% %

2.Clock rates should be stable when the CS35L32 is powered up.

3.Minimum data valid window, as shown in signal diagram, is (SCLKperiod – 300 + 155) ns. For SCLK = 64*Fs =64*48 = 3072 kHz, this is 180 ns.

4.In Master Mode, the output sample rate follows MCLK rate divided down per Table 4-14 and Section 7.7. Any deviation in internal MCLK from the nominal supported rates is directly imparted to the output sample rate by the same factor (e.g., +100-ppm offset in the frequency of MCLK becomes a +100-ppm offset in LRCK).

5.If RATIO = 1, the MCLK(INT)-to-LRCK ratio is 125. The device periodically extends SCLK high time to compensate for a fractional MCLK/SCLK ratio

DS963F4 13

CS35L32

BUF

LOW

Stop Start

Start

Stop

Repeated

SDA

SCL

IRS

RESET

HDDI,

HDDO

SUD

SUST

HDST

HIGH

HDST

SUSP

3 Characteristics and Specifications

Table 3-13. Switching Specifications: I²C Control Port

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, TA = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 = VA; SDA load capacitance equal to maximum value of C parameters in detail. All specifications are valid for the signals at the pins of the CS35L32 with the specified load capacitance; input timings are measured at V

and VIH thresholds; output timings are measured at VOL and VOH thresholds (see Table 3-8).

Parameter Symbol

RESET

rising edge to start

SCL clock frequency f Start condition hold time (before first clock pulse) t Clock low time t Clock high time t Setup time for repeated start condition t SDA input hold time from SCL falling

SDA output hold time from SCL falling t SDA setup time to SCL rising t Rise time of SCL and SDA t Fall time of SCL and SDA t Setup time for stop condition t Bus free time between transmissions t SDA bus capacitance C

1.The minimum R

and R

values (resistors shown in Fig. 2-1) are determined using the maximum level of VA, the minimum sink current strength of

P_I

their respective output, and the maximum low-level output voltage V by how fast their associated signals must transition (e.g., the lower the value of R capacitance). See the I²C switching specifications in Table 3-13 and the I²C bus specification referenced in Section 13.

2.I²C control-port timing.

specified below; minimum SDA pull-up resistance, R

IRS

SCL

HDST

LOW

HIGH

SUST

HDDI

HDDO

SUD

SUSP

BUF

(specified in Table 3-8). The maximum RP and R

, the faster the I2C bus is able to operate for a given bus load

.1 Section 9 describes some

P(min)

Min Max Units

500 — ns

— 400 kHz

0.6 — µs

1.3 — µs

0.6 — µs

00.9µs

0.2 0.9 µs

100 — ns

— 300 ns — 300 ns

0.6 — µs

1.3 — µs — 400 pF

values may be determined

P_I

3.Data must be held long enough to bridge the transition time, tF, of SCL.

14 DS963F4

4 Functional Description

Class D Power Stage

SPKR SU PPLY

GNDPLED

Current Mode Synchronous Boost Controller

VCOM

Range

Scaling

Class D F r ont End

Short C ircuit Prot ection

∆Σ Class D M odulator

REF

Gener ation

Bandgap

Voltage

Gener ation

FILT+

VREF

ISENSE+ ISENSE–/

VSENSE+

SCLKLRC K

Soft Ramp

Level Shifters

I²C Control Port

SDASCLSCLK LRCK SDOUT

MCLK

IN–

–

9,12,15 , or 18 dB + Mute

IN+

Flash LED Current Driver

Control,

Sensing,

and Fault

Protection

FLOUT1 FLOUT2/AD0FLEN FLINH

SPKOUT+ SPKOUT–/

VSENSE–

I2C Class G Override

Watchdog

Error

GNDP

VSENSE–

VSENSE+

ISENSE–

ISENSE+

SPKR

SUPPLY



ADC

Serial Audio /Data Por t

Serial Port

Clock Generation

RESET INT

VMON ADC

Front End

IMON ADC

Front End

Low Battery Management

Class G

VBST

Current

Sense

IREF+SW

Power

Budgeting

Temperature

Sensor

Overtemp Protec tion



ADC



ADC

See Section 4.9 “LED Driver.”

See Section 4.4.

See

Section 4.11

“Audio/Data

Serial Port (ADSP).”

See Section 4.8, “Signal Monitoring.”

See

Section 4.10,

“Power

Budgeting.”

See

Section 4.7.

See Section 4.3.

See Section 4.6 “Boost Converter.”

See Section 4.11.

See Section 4.14.

See Section 4.2.

See Section 4.13, “Device Clocking.”

CS35L32

4 Functional Description

4.1 Power Supplies

The VA and VP supplies are required for proper operation of the CS35L32. Before either supply is powered down, RESET must be asserted. RESET Timing requirement for RESET generated internally (as described in Section 7.12) and connected to the high-power output stage of the Class D amplifier through two balls: VBST and SPKRSUPPLY. By so doing, the speaker amplifier benefits from the proximity of the external decoupling capacitor that is connected to the boosted supply.

4.2 Interrupts

Events that require special attention, such as when a threshold is exceeded or an error occurs, are reported through the assertion of the interrupt output pin, INT individually masked by setting corresponding bits in the interrupt mask registers. Table 4-1 lists interrupt status and mask registers. The configuration of mask bits determines which events cause the immediate assertion of INT

• When an unmasked interrupt status event is detected, the status bit is set and INT

• When a masked interrupt status event is detected, the interrupt status bit is set, but INT

Once INT are sticky and read-to-clear: Once set, they remain set until the register is read and the associated interrupt condition is not present. If a condition is still present and the status bit is read, although INT

is asserted, it remains asserted until all unmasked status bits that are set have been read. Interrupt status bits

must be held in the asserted state until all supplies are up and within the recommended range.

during supply power up and power down is described in Table 3-11. The VBST supply is

Figure 4-1. CS35L32 Block Diagram

. These events are captured within the interrupt status registers. Events can be

is deasserted, the status bit remains set.

is asserted.

is not affected.

DS963F4 15

CS35L32

Hybrid Class D A udio Am plifier

(PDN_AMP = 0)

Hybrid Class D Modulator

-Class D

Modulator

9–18 dB

Short

Circuit

Protec tion

SPKOUT+ SPKOUT–

Hybrid Class D

Power Stage

VBST

IN+ IN–

AMP_GAIN p. 39 GAIN_CHG_ZC p. 39

AUDIOGAIN_MNG p. 38

IN1THOF

------ K





VBST

Gain

-----------------





=

IN1THON

2 3

---





VBST

Gain

-----------------





=

4.3 Speaker Amplifier

To clear any status bits set due to the initiation of a path or block, all interrupt status bits should be read after reset and before normal operation begins. Otherwise, unmasking these previously set status bits causes INT

Table 4-1. Interrupt Status Registers and Corresponding Mask Registers

Status Registers Mask Registers

Interrupt Status 1 (Audio) (Section 7.19) Interrupt Status 2 (Monitors) (Section 7.20) Interrupt Status 3 (LEDs and Boost Converter) (Section 7.21)

Interrupt Mask 1 (Section 7.16) Interrupt Mask 2 (Section 7.17) Interrupt Mask 3 (Section 7.18)

4.3 Speaker Amplifier

The CS35L32 features a high-efficiency mono Class D audio amplifier, shown in Fig. 4-2, with an advanced closed-loop architecture that achieves low levels of output distortion. Automatic Class G operation, using a boosted supply to the amplifier, allows louder speaker performance with high crest factor.

to assert.

Figure 4-2. Speaker Amplifier Block Diagram

4.3.1 Class G Operation with LEDs Off

The boost converter output is the supply to the speaker amplifier. Audio operation can be programmed to have one of the following supply modes (See Section 7.12 for programming details.):

• Class G where the boost converter is in Bypass Mode for audio input signals below a threshold V 5-V Boost Mode for audio signal inputs above a threshold V

IN1THOFF

. These thresholds are specified in Table 3-4

IN1THON

for the given conditions. The corresponding equations are shown below.

• Class G disabled, boost converter is in Bypass Mode, and VBST = VP. In this mode, thresholds are ignored.

• Class G disabled, boost converter is in Boost Mode, and VBST = 5 V. In this mode, thresholds are ignored.

The Class G equations for the audio input signal thresholds are as follows:

VBST is the boost converter output voltage (whether in Bypass or Boost Mode), and gain is audio gain expressed as a unitless real ratio (nonlogarithmic). K = 1 if MCLK is 6 or 12 MHz; K = 1.024 if MCLK is 6.144 or 12.288 MHz. MCLK should be configured as described in Section 4.13.1 and Section 7.7.

and

16 DS963F4

and in

INT

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