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CAT93C56/57 (Die Rev. E)
N
E
G
F
O
R
L
A
H
E
E
2K-Bit Microwire Serial EEPROM
FEATURES
■ High speed operation: 1MHz
■ Low power CMOS technology
■ 1.8 to 5.5 volt operation
■ Selectable x8 or x16 memory organization
■ Self-timed write cycle with auto-clear
■ Software write protection
DESCRIPTION
The CAT93C56/57 are 2K-bit Serial EEPROM memory
devices which are configured as either registers of 16
bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C56/57 are manufactured
PIN CONFIGURATION
L
E
A
E
E
R
D
F
■ Sequential read
■ Power-up inadvertant write protection
■ 1,000,000 Program/erase cycles
■ 100 year data retention
■ Commercial, industrial and automotive
temperature ranges
■ RoHS-compliant packages
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The devices are designed to endure
1,000,000 program/erase cycles and has a data retention of 100 years. The devices are available in 8-pin DIP,
SOIC, TSSOP and 8-pad TDFN packages.
FUNCTIONAL SYMBOL
TM
DIP Package (L)
1
CS
SK
DI
DO
8
2
7
3
6
5
4
SOIC Package (V)
1
CS
SK
DI
DO
8
2
7
3
6
4
5
V
CC
NC
ORG
GND
V
CC
NC NC
ORG
GND
SOIC Package (W)
1
NC
CC
CS
SK
2
3
4
V
SOIC Package (X)
1
CS
2
SK
3
DI
4
DO
8
7
6
5
8
7
6
5
TSSOP Package (Y) TDFN Package (ZD4)
CS
SK
DO
1
2
3
DI
4
8
7
6
5
V
CC
NC
ORG
GND
V
CC
NC
ORG
GND
8
7
6
5
Bottom View
For Ordering Information details, see page 8.
ORG
GND
DO
DI
V
ORG
GND
CC
1
2
3
4
CS
SK
DI
DO
V
CC
ORG
CS
SK
DI
GND
DO
PIN FUNCTIONS
Pin Name Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
V
CC
GND Ground
ORG Memory Organization
NC No Connection
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
Power Supply
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1088, Rev. O
CAT93C56/57
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
(1)
............. -2.0V to +VCC +2.0V
= 25°C) ................................... 1.0W
A
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Typ Max Units
(3)
I
N
T
V
LTH
END
DR
ZAP
(3)
(3)
(3)(4)
Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte
Data Retention MIL-STD-883, Test Method 1008 100 Years
ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
Latch-Up JEDEC Standard 17 100 mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol Parameter Test Conditions Min Typ Max Units
V
V
V
V
I
CC1
I
CC2
I
SB1
I
I
V
V
V
V
SB2
I
LI
LO
IL1
IH1
IL2
IH2
OL1
OH1
OL2
OH2
Power Supply Current fSK = 1MHz 3 mA
(Write) VCC = 5.0V
Power Supply Current fSK = 1MHz 500 µA
(Read) VCC = 5.0V
Power Supply Current CS = 0V 10 µA
(Standby) (x8 Mode) ORG=GND
Power Supply Current CS=0V 0 10 µA
(Standby) (x16Mode) ORG=Float or V
Input Leakage Current VIN = 0V to V
Output Leakage Current V
= 0V to VCC,1µA
OUT
CC
CC
1 µA
(Including ORG pin) CS = 0V
Input Low Voltage 4.5V ≤ V
Input High Voltage 4.5V ≤ V
Input Low Voltage 1.8V ≤ V
Input High Voltage 1.8V ≤ V
Output Low Voltage 4.5V ≤ V
< 5.5V -0.1 0.8 V
CC
< 5.5V 2 V
CC
< 4.5V 0 V
CC
< 4.5V V
CC
< 5.5V 0.4 V
CC
x 0.7 VCC+1 V
CC
+ 1 V
CC
x 0.2 V
CC
IOL = 2.1mA
Output High Voltage 4.5V ≤ V
< 5.5V 2.4 V
CC
IOH = -400µA
Output Low Voltage 1.8V ≤ V
< 4.5V 0.2 V
CC
IOL = 1mA
Output High Voltage 1.8V ≤ V
< 4.5V V
CC
- 0.2 V
CC
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 1088, Rev. O
2
CAT93C56/57
PIN CAPACITANCE
Symbol Test Conditions Min Typ Max Units
(2)
C
OUT
(2)
C
IN
INSTRUCTION SET
Output Capacitance (DO) V
=0V 5 pF
OUT
Input Capacitance (CS, SK, DI, ORG) VIN=0V 5 pF
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A.C. CHARACTERISTICS
Limits
VCC =V
=V
CC
CC
=
1.8V-5.5V 2.5V-5.5V 4.5V-5.5V
Test
Symbol Parameter Conditions Min Max Min Max Min Max Units
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
(1)
t
HZ
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
CS Setup Time 200 100 50 ns
CS Hold Time 0 0 0 ns
DI Setup Time 400 200 100 ns
DI Hold Time 400 200 100 ns
Output Delay to 1 1 0.5 0.25 µs
Output Delay to 0 1 0.5 0.25 µs
Output Delay to High-Z 400 200 100 ns
CL = 100pF
(3)
Program/Erase Pulse Width 10 10 10 ms
Minimum CS Low Time 1 0.5 0.25 µs
Minimum SK High Time 1 0.5 0.25 µs
Minimum SK Low Time 1 0.5 0.25 µs
Output Delay to Status Valid 1 0.5 0.25 µs
Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz
3
Doc. No. 1088, Rev. O
CAT93C56/57
POWER-UP TIMING
(1)(2)
Symbol Parameter Max Units
t
PUR
t
PUW
Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms
A.C. TEST CONDITIONS
Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V
Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V
Input Pulse Voltages 0.2VCC to 0.7V
Timing Reference Voltages 0.5V
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
PUR
and t
are the delays required from the time VCC is stable until the specified operation can be initiated.
PUW
CC
CC
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard microprocessors. The CAT93C56/57 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 10-bit instructions for 93C57; seven 11-bit
instructions for 93C56 control the reading, writing and
erase operations of the device. When organized as X8,
seven 11-bit instructions for 93C57; seven 12-bit instructions for 93C56 control the reading, writing and
erase operations of the device. The CAT93C56/57
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high)
and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high indicates that the device is ready for the next instruction. If
necessary, the DO pin may be placed back into a high
impedance state during chip select by shifting a dummy
“1” into the DI pin. The DO pin will enter the high
impedance state on the falling edge of the clock (SK).
Placing the DO pin into the high impedance state is
recommended in applications where the DI pin and the
DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address
(93C57)/ 8-bit address (93C56) (an additional bit when
organized X8) and for write operations a 16-bit data field
(8-bit for X8 organizations).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/
57 will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (t
PD0
or t
PD1
).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
. The falling edge of CS will start the
CSMIN
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Since this device features AutoClear before write, it is NOT necessary to erase a
memory location before it is written into.
Doc. No. 1088, Rev. O
4
Figure 1. Sychronous Data Timing
SK
CS
DI
DO
t
CSMIN
STANDBY
HIGH-Z
HIGH-Z
101
ANA
N-1
A
0
D
N
D
0
BUSY
READY
STATUS
VERIFY
t
SV
t
HZ
t
EW
CAT93C56/57
SK
t
DIS
VALID VALID
CS
DO
DI
t
CSS
Figure 2. Read Instruction Timing
SK
1 11 1 111 11111111
CS
ANA
DI
11 0
N–1
t
SKHI
t
SKLOW
t
DIS
A
0
t
DIH
t
PD0,tPD1
DATA VALID
Don't Care
t
CSH
t
CSMIN
DO
HIGH-Z
Figure 3. Write Instruction Timing
Dummy 0
D
15 . . . D0
or
D
7 . . . D0
Address + 1
D
15 . . . D0
or
D
7 . . . D0
Address + 2
D
15 . . . D0
or
D
7 . . . D0
Address + n
D
15 . . .
or
D
7 . . .
5
Doc. No. 1088, Rev. O
CAT93C56/57
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
. The falling edge of CS will start the self clocking
CSMIN
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C56/57 can be determined by selecting the
device and polling the DO pin. Once cleared, the content
of a cleared location returns to a logical “1” state.
Erase/Write Enable and Disable
The CAT93C56/57 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C56/57
write and clear instructions, and will prevent any
accidental writing or clearing of the device. Data can be
read normally from the device regardless of the write
enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
CSMIN
. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
. The falling edge of CS will start the self clocking
t
CSMIN
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C56/57 can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Figure 4. Erase Instruction Timing
SK
CS
A
N
DO
DI
11
1
A
N-1
HIGH-Z
STATUS VERIFY
t
A
0
t
SV
CS
BUSY READY
t
EW
STANDBY
t
HZ
HIGH-Z
Doc. No. 1088, Rev. O
6
Figure 5. EWEN/EWDS Instruction Timing
SK
CAT93C56/57
CS
DI
100
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
DI
DO
10 1
00
HIGH-Z
STANDBY
*
t
SV
STATUS VERIFY
t
CS
BUSY READY
t
EW
STANDBY
t
HZ
HIGH-Z
Figure 7. WRAL Instruction Timing
SK
CS
DI
DO
10 1
00
STATUS VERIFY
t
CSMIN
D
N
D
0
t
SV
BUSY READY
t
EW
7
STANDBY
t
HZ
HIGH-Z
Doc. No. 1088, Rev. O
CAT93C56/57
ORDERING INFORMATION
Prefix Device # Suffix
Company ID
93C56 V
Product Number
93C56: 2K
93C57: 2K
I T3-1.8CAT Rev E
Temperature Range
I = Industrial (-40°C - 85°C)
A = Automotive (-40°C - 105°C)
– G
Die Revision
93C56: E
93C57: E
E = Extended (-40°C to + 125°C)
Tape & Reel
Package
L = PDIP
V = SOIC, JEDEC
Operating Voltage
Blank (V
1.8 (V
= 2.5V to 5.5V)
cc
= 1.8V to 5.5V)
cc
T: Tape & Reel
2: 2000/Reel
(5)
3: 3000/Reel
W = SOIC, JEDEC
X = SOIC, EIAJ
Y = TSSOP
ZD4 = TDFN (3x3mm)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard finish is NiPdAu.
(3) The device used in the above example is a CAT93C56VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage,
NiPdAu, Tape & Reel).
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional
information, please contact your Catalyst sales office.
(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C56XI-T2.
(6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(5)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
(4)
Doc. No. 1088, Rev. O
8
REVISION HISTORY
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Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
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Phone: 408.542.1000
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www.catalyst-semiconductor.com
Publication #: 1088
Revison: O
Issue date: 10/13/06
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