CATALYST CAT5251 Service Manual
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CAT5251
Quad Digitally Programmable Potentiometer (DPP™) with
256 Taps and SPI Interface
FEATURES
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■ Four linear-taper digitally programmable
potentiometers
■ 256 resistor taps per potentiometer
■ End to end resistance 50kΩ or 100kΩ
■ Potentiometer control and memory access via
SPI interface
■ Low wiper resistance, typically 100
■ Nonvolatile memory storage for up to four wiper
ΩΩ
Ω
ΩΩ
settings for each potentiometer
DESCRIPTION
The CAT5251 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 8-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 8-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
■ Automatic recall of saved wiper settings at
power up
■ 2.5 to 6.0 volt operation
■ Standby current less than 1µA
■ 1,000,000 nonvolatile WRITE cycles
■ 100 year nonvolatile memory data retention
■ 24-lead SOIC and 24-lead TSSOP
■ Industrial temperature range
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register.
The CAT5251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C industrial
operating temperature range and offered in a 24-lead
SOIC and TSSOP package.
PIN CONFIGURATION
SOIC/TSSOP Package (J, W/U, Y)
CAT
5251
24
23
22
21
20
19
18
17
16
15
14
13
1
SO
2
A0
W3
H3
L3
NC
CC
L0
H0
W0
CS
3
4
5
6
7
8
9
10
11
12
R
R
R
V
R
R
R
WP
HOLD
SCK
R
L2
R
H2
R
W2
NC
GND
R
W1
R
H1
R
L1
A1
SI
FUNCTIONAL DIAGRAM
CS
SCK
S
WP
A0
A1
HOLD
SI
O
SPI BUS
INTERFACE
CONTROL
LOGIC
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
R
H0
R
L0
R
H1
R
L1
R
R
H2
H3
R
W0
R
W1
R
W2
R
W3
R
R
L2
L3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2017, Rev. D
CAT5251
PIN DESCRIPTION
Pin
(SOIC/TSSOP) Name Function
1 SO Serial Data Output
2 A0 Device Address, LSB
3RW3Wiper Terminal for Potentiometer 3
4RH3High Reference Terminal
for Potentiometer 3
5RL3Low Reference Terminal
for Potentiometer 3
6 NC No Connect
7 VCC Supply Voltage
8R
9R
10 R
11 CS Chip Select
12 WP Write Protection
13 SI Serial Input
14 A1 Device Address
15 R
16 R
17 R
18 GND Ground
19 NC No Connect
20 R
21 R
22 R
23 SCK Bus Serial Clock
24 HOLD Hold
L0
H0
W0
L1
H1
W1
W2
H2
L2
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for Potentiometer 0
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for Potentiometer 1
Wiper Terminal for
Potentiometer 2
High Reference Terminal
for Potentiometer 2
Low Reference Terminal
for Potentiometer 2
PIN DESCRIPTIONS
SI: Serial Input
SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5251. Input data is latched on the
rising edge of the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5251. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5251. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in
order to initiate communication with the CAT5251.
, RL: Resistor End Points
R
H
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
: Wiper
W
The four RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
CSCS
CS: Chip Select
CSCS
CS is the Chip select pin. CS low enables the
CAT5251 and CS high disables the CAT5251. CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5251
draws ZERO current in the Standby mode. A high to
low transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle.
WPWP
WP: Write Protect
WPWP
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all
non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while
CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no
effect on any write operation.
HOLDHOLD
HOLD: Hold
HOLDHOLD
The HOLD pin is used to pause transmission to the CAT5251 while in the middle of a serial sequence without having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high
directly to VCC or tied to VCC through a resistor.
Document No. 2017, Rev. D
2
SERIAL BUS PROTOCOL
CAT5251
The CAT5251 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5251 to interface directly with many
of today's popular microcontrollers. The CAT5251
contains an 8-bit instruction register .The instruction set
and the operation codes are detailed in the instruction
set table 3 on page 9.
DEVICE OPERATION
The CAT5251 is four resistor arrays integrated with an
SPI serial interface logic, four 8-bit wiper control registers
and sixteen 8-bit, non-volatile memory data registers.
Each resistor array contains 255 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL). RH and RL are
symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (RW) by a
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK. The
first byte contains one of the six op-codes that define the
operation to be performed.
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the SPI bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
3
Document No. 2017, Rev. D
CAT5251
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ..................-55°C to +125°C
Storage Temperature........................-65°C to +150°C
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Voltage on any Pin with
Respect to V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
(1)(2)
................ -2.0V to +VCC +2.0V
SS
= 25°C) ................................... 1.0W
A
Recommended Operating Conditions:
V
= +2.5V to +6.0V
CC
Temperature Min Max
Industrial -40°C85°C
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current....................................................
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output
pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
+6mA
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter Test Conditions Min Typ Max Units
R
POT
R
POT
I
W
R
W
R
W
V
TERM
V
N
TC
RPOT
TC
RATIO
CH/CL/C
fc Frequency Response R
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = R
(5) n = 0, 1, 2, ..., 255
Potentiometer Resistance (-00) 100 kΩ
Potentiometer Resistance (-50) 50 kΩ
Potentiometer Resistance +20 %
Tolerance
R
Matching 1 %
POT
Power Rating 25°C, each pot 50 mW
Wiper Current +3 mA
Wiper Resistance IW = +3mA @ VCC =3V 200 300 Ω
Wiper Resistance IW = +3mA @ VCC = 5V 100 150 Ω
Voltage on any RH or RL Pin VSS = 0V GND V
Noise (1) nV/ Hz
Resolution 0.4 %
Absolute Linearity
Relative Linearity
(2)
(3)
Temperature Coefficient of R
POT
R
w(n)(actual)-R(n)(expected)
R
-[R
w(n+1)
w(n)+LSB
(1) +300 ppm/°C
(5)
(5)
]
+0.5 LSB
Ratiometric Temp. Coefficient (1) 20 ppm/°C
W
Potentiometer Capacitances (1) 10/10/25 pF
(1)
0.4 MHz
/ 255 or (RH - RL) / 255, single pot
TOT
POT
= 50kΩ
CC
V
+1 LSB
(4)
(4)
Document No. 2017, Rev. D
4
CAT5251
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter Test Conditions Min Typ Max Units
V
V
I
CC1
I
CC2
I
I
I
V
V
SB
LI
LO
IL
IH
OL1
OH1
Power Supply Current f
= 2.5 MHz, SO Open 1 mA
SCK
VCC = 6 V Inputs = GND
Power Supply Current fsck = 2.5 MHz, SO = Open 5 mA
Non-volatile Write VCC = 6 V Inputs = GND
Standby Current (VCC = 5.0V) VIN = GND or V
Input Leakage Current VIN = GND to V
Output Leakage Current V
= GND to V
OUT
SO Open 1 µA
CC;
CC
CC
10 µA
10 µA
Input Low Voltage -1 VCC x 0.3 V
Input High Voltage VCC x 0.7 V
+ 1.0 V
CC
Output Low Voltage (VCC = 3 V) IOL = 3 mA 0.4 V
Output High Voltage (VCC = 6 V) I
= -1.6mA VCC-0.8 V
OH
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
(1)
Symbol Test Conditions Min Typ Max Units Conditions
C
OUT
C
IN
Output Capacitance (SO) 8 pF V
Input Capacitance (CS, SCK, SI, WP, HOLD,6pFV
OUT
=0V
IN
=0V
A0, A1)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
5
Document No. 2017, Rev. D
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