CAT1320, CAT1321
T
T
T
T
Supervisory Circuits with I2C Serial 32K CMOS EEPROM
FEATURES
N
E
G
F
O
R
L
E
A
E
H
L
E
E
E
A
TM
R
D
F
■ Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
- +5.0V (+/- 5%, +/- 10%)
- +3.3V (+/- 5%, +/- 10%)
- +3.0V (+/- 10%)
■ Active low reset, CAT1320
■ Active high reset, CAT1321
■ Valid reset guaranteed at V
■ 400kHz I
2
C bus
CC
=1V
DESCRIPTION
The CAT1320 and CAT1321 are complete memory and
supervisory solutions for microcontroller-based systems.
A 32kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I2C bus.
The CAT1320 provides a precision VCC sense circuit
and drives an open drain output, RESET low whenever
VCC falls below the reset threshold voltage.
The CAT1321 provides a precision VCC sense circuit
that drives an open drain output, RESET high whenever
VCC falls below the reset threshold voltage.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals become
■ 3.0V to 5.5V operation
■ Low power CMOS technology
■ 64-Byte page write buffer
■ 1,000,000 Program/Erase cycles
■ 100 year data retention
■ 8-pin DIP, SOIC, TSSOP and TDFN packages
■ Industrial temperature range
active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset options,
interface to microcontrollers and other ICs is simple. In
addition, the RESET (CAT1320) pin can be used as an
input for push-button manual reset capability.
The CAT1320/21 memory features a 64-byte page. In
addition, hardware data protection is provided by a V
sense circuit that prevents writes to memory whenever V
CC
CC
falls below the reset threshold or until VCC reaches the reset
threshold during power up.
Available packages include an 8-pin DIP, SOIC, TSSOP
and 4.9 x 3mm TDFN.
PIN CONFIGURATION
PDIP (P, L) SOIC (J, W)
1
A0 V
A1
2
CAT1320
A2
3
V
4
SS
1
A0
A1
2
CAT1321
A2
3
V
4
SS
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8
7
6
5
8
7
6
5
CC
RESE
SCL
SDA
V
CC
RESET
SCL
SDA
TSSOP (U, Y)
1
A0 V
A1
2
CAT1320
A2
3
V
4
SS
1
A0
A1
2
CAT1321
A2
3
V
4
SS
1
8
7
6
5
8
V
RESET
7
SCL
6
SDA
5
CC
RESE
SCL
SDA
CC
TDFN PACKAGE: 4.9MM X 3MM
(RD2, ZD2)
1
A0
2
A1
A2
V
SS
A0
A1
A2
V
SS
3
4
1
2
3
4
CAT1320
CAT1321
8
V
CC
7
RESE
6
SCL
5
SDA
8
V
CC
7
RESE
6
SCL
5
SDA
Doc. No. 20585, Rev. 00
CAT1320, CAT1321 Advance Information
L
BLOCK DIAGRAM — CAT1320, CAT1321
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
32kbit
EEPROM
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
V
CC
V
SS
SDA
D
ACK
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
CONTROL
LOGIC
RESET Controller
Precision
Vcc Monitor
OUT
XDEC
Threshold Voltage Options
Part Dash Minimum Maximum
Number Threshold Threshold
-45 4.50 4.75
-42 4.25 4.50
-30 3.00 3.15
-28 2.85 3.00
-25 2.55 2.70
OPERATING TEMPERATURE RANGE
Industrial -40˚C to 85˚C
SC
A0
A1
A2
RESET (CAT1320)
RESET (CAT1321)
PIN FUNCTIONS
Pin Name Function
RESET Active Low Reset Input/Output (CAT1320)
V
SS
SDA Serial Data/Address
SCL Clock Input
RESET Active High Reset Output (CAT1321)
V
CC
Ground
Power Supply
PIN DESCRIPTION
RESET/
These are open-drain pins and RESET can also be used
as a manual reset trigger input. By forcing a reset condition
on the pin the device will initiate and maintain a reset
condition. The RESET pin must be connected through a
pull-down resistor and the RESET pin must be connected
through a pull-up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an
open drain output and can be wire-ORed with other open
drain or open collector outputs.
RESETRESET
RESET: RESET OUTPUTS
RESETRESET
SCL: SERIAL CLOCK
Serial clock input.
A0, A1, A2: DEVICE ADDRESS INPUTS
When hardwired, up to eight CAT1320/21 devices may
be addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the
default values are zeros.
Doc. No. 25085, Rev. 00
2
Advance Information CAT1320, CAT1321
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .................... -40°C to +85°C
Storage Temperature ........................ -65°C to +105°C
Voltage on any Pin with
Respect to Ground
with Respect to Ground ................ -0.5V to +7.0V
V
CC
(1)
............. -0.5V to +VCC +2.0V
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Note:
(1) Output shorted for no more than one second. No more than
one output shorted at a time.
Package Power Dissipation
Capability (T
= 25°C) ................................... 1.0W
A
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(1)
........................ 100 mA
D.C. OPERATING CHARACTERISTICS
VCC = +3.0V to +5.5V and over the recommended temperature conditions unless otherwise specified.
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Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
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Doc No. 25085, Rev. 00
CAT1320, CAT1321 Advance Information
CAPACITANCE
TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Test Conditions Max Units
(1)
C
C
OUT
(1)
IN
Output Capacitance V
= 0V 8 pF
OUT
Input Capacitance VIN = 0V 6 pF
A.C. CHARACTERISTICS
V
= 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
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1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
Doc. No. 25085, Rev. 00
4
Advance Information CAT1320, CAT1321
RESET CIRCUIT A.C. CHARACTERISTICS
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Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. VCC Glitch Reference Voltage = V
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t
PUR
and t
are the delays required from the time VCC is stable until the specified memory operation can be initiated.
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AC TEST CONDITIONS
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RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Max Units
(1)
N
END
(1)
T
DR
(1)
V
ZAP
(1)(2)
I
LTH
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte
Data Retention MIL-STD-883, Test Method 1008 100 Years
ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
Latch-Up JEDEC Standard 17 100 mA
5
Doc No. 25085, Rev. 00
CAT1320, CAT1321 Advance Information
DEVICE OPERATION
Reset Controller Description
The CAT1320/21 precision Reset controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with opendrain RESET/RESET outputs.
During power-up, the RESET/RESET output remains
active until VCC reaches the VTH threshold and will
continue driving the outputs for approximately 200ms
(t
) after reaching VTH. After the t
PURST
PURST
timeout
interval, the device will cease to drive the reset output.
At this point the reset output will be pulled up or down by
their respective pull up/down resistors.
During power-down, the RESET/RESET output will be
active when V
output will be valid so long as VCC is >1.0V (V
falls below VTH. The RESET/RESET
CC
RVALID
The device is designed to ignore the fast negative going
VCC transient pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
When RESET I/O is driven to the active state, the 200
msec timer will begin to time the reset interval. If external
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
Hardware Data Protection
The CAT1320/21 family has been designed to solve
many of the data corruption issues that have long been
associated with serial EEPROMs. Data corruption occurs
when incorrect data is stored in a memory location which
is assumed to hold correct data.
).
Whenever the device is in a Reset condition, the embedded
EEPROM is disabled for all operations, including write
operations. If the Reset output is active, in progress
communications to the EEPROM are aborted and no new
communications are allowed. In this condition an internal
write cycle to the memory can not be started, but an in
progress internal non-volatile memory write cycle can not
be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum
value of 2V.
Figure 1. RESET/RESET Output Timing
V
TH
V
RVALID
V
CC
RESET
RESET
Doc. No. 25085, Rev. 00
t
PURST
t
GLITCH
t
6
RPD
t
PURST
t
RPD
Advance Information CAT1320, CAT1321
Figure 2.
RESETRESET
RESET as Manual Reset Input Operation and Timing
RESETRESET
RESET
(Input)
(Output)
Figure 3. Bus Timing
SCL
t
SDA IN
SDA OUT
RESET
SU:STA
t
MRW
t
PURST
t
F
t
LOW
t
HD:STA
t
AA
t
HIGH
t
HD:DAT
t
LOW
t
DH
t
R
t
SU:DAT
t
SU:STO
t
BUF
7
Doc No. 25085, Rev. 00
CAT1320, CAT1321 Advance Information
EMBEDDED EEPROM OPERATION
SDA when SCL is HIGH. The CAT1320/21 monitors the
The CAT1320 and CAT1321 feature a 32kbit
embedded serial EEPROM that supports the I2C Bus
data transmission protocol. This Inter-Integrated
Circuit Bus protocol defines any device that sends
data to the bus to be a transmitter and any device
receiving data to be a receiver. The transfer is
controlled by the Master device which generates the
serial clock and all START and STOP conditions for
bus access. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant
bits of the 8-bit slave address are programmable in metal
and the default is 1010.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this bit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1320/21 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1320/21 then performs a Read or Write operation
depending on the R/W bit.
Figure 4. Write Cycle Timing
SCL
SDA
BYTE n
ACK8TH BIT
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc. No. 25085, Rev. 00
8
Advance Information CAT1320, CAT1321
ACKNOWLEDGE
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT1320/21 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
When the CAT1320/21 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1320/21 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 5. Start/Stop Timing
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8-bit
address bytes that are to be written into the address
pointers of the device. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the addressed memory location. The CAT1320/
21 acknowledges once more and the Master generates
the STOP condition. At this time, the device begins an
internal programming cycle to non-volatile memory. While
the cycle is in progress, the device will not respond to any
request from the Master device.
SDA
SCL
Figure 6. Acknowledge Timing
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 7. Slave Address Bits
START BIT
START
STOP BIT
1
89
ACKNOWLEDGE
Default Configuration
CAT
1010A2A1A0R/W
9
Doc No. 25085, Rev. 00
CAT1320, CAT1321 Advance Information
Page Write
The CAT1320/21 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the byte
write operation, however instead of terminating after the
initial byte is transmitted, the Master is allowed to send up
to additional 63 bytes. After each byte has been
transmitted, the CAT1320/21 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
Figure 8. Byte Write Timing
S
T
A
BUS ACTIVITY:
MASTER
SDA LINE
R
T
S
SLAVE
ADDRESS
BYTE ADDRESS
A15–A
*
*
*
*
A
C
K
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1320/21 in a single write cycle.
S
T
8
A7–A
0
A
C
K
DATA
A
C
K
O
P
P
A
C
K
*=Don’t Care Bit
Figure 9. Page Write Timing
S
T
A
BUS ACTIVITY:
MASTER
SDA LINE
*=Don’t Care Bit
R
T
S
SLAVE
ADDRESS
S
BYTE ADDRESS
A15–A
8
**
*
*
A
C
K
A7–A
0
A
C
K
A
C
K
DATA n
A
C
K
A
C
K
DATA n+63DATA
A
C
K
T
O
P
P
A
C
K
Doc. No. 25085, Rev. 00
10
Advance Information CAT1320, CAT1321
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write opration, the
CAT1320/21 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
Figure 10. Immediate Address Read Timing
S
T
BUS ACTIVITY:
MASTER
A
R
T
SLAVE
ADDRESS
Read Operations
The READ operation for the CAT1320/21 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
S
T
O
P
SDA LINE
SCL
SDA 8TH BIT
S
89
P
A
C
K
DATA
N
O
A
C
K
STOPNO ACKDATA OUT
11
Doc No. 25085, Rev. 00
CAT1320, CAT1321 Advance Information
Immediate/Current Address Read
The CAT1320 and CAT1321 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=4,095. The counter will wrap around to Zero and
continue to clock out valid data. After the CAT1320 and
CAT1321 receives its slave address information (with
the R/W bit set to one), it issues an acknowledge, then
transmits the 8-bit byte requested. The master device
does not send an acknowledge, but will generate a
STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1320 and CAT1321
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1320 and CAT1321 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1320 and CAT1321 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1320 and CAT1321 will continue to output
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1320 and
CAT1321 is sent sequentially with the data from address
N followed by data from address N+1. The READ
operation address counter increments all of the CAT1320
and CAT1321 address bits so that the entire memory
array can be read during one operation.
Figure 11. Selective Read Timing
S
T
A
BUS ACTIVITY:
MASTER
SDA LINE
*=Don’t Care Bit
R
T
S
SLAVE
ADDRESS
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
A
C
K
S
T
A
C
K
A
R
T
S
A
C
K
DATA n+2
ADDRESS
A
C
K
DATA
A
C
K
DATA n+xDATA n
BYTE ADDRESS SLAVE
A15–A
8
*
*
*
*
A
C
K
A
C
K
A7–A
A
C
K
DATA n+1
0
S
T
O
P
P
N
O
A
C
K
S
T
O
P
P
N
O
A
C
K
Doc. No. 25085, Rev. 00
12
Advance Information CAT1320, CAT1321
PACKAGE OUTLINES
8-LEAD PDIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
D
0.120 (3.05)
0.150 (3.81)
0.180 (4.57) MAX
0.325 (8.26)
0.100 (2.54)
BSC
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
0.015 (0.38)
—
0.110 (2.79)
0.150 (3.81)
Dimension D
Pkg Min Max
8L 0.355 (9.02) 0.400 (10.16)
0.310 (7.87)
0.380 (9.65)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
13
Doc No. 25085, Rev. 00
CAT1320, CAT1321 Advance Information
PACKAGE OUTLINES
8-LEAD SOIC (J, W)
0.050 (1.27) BSC
0.1890 (4.80)
0.1968 (5.00)
0.013 (0.33)
0.020 (0.51)
0.0099 (0.25)
0.0196 (0.50)
0.1497 (3.80)
0.1574 (4.00)
0.0532 (1.35)
0.0688 (1.75)
0.0040 (0.10)
0.0098 (0.25)
x 46
°
0.0075 (0.19)
0.0098 (0.25)
0.2284 (5.80)
0.2440 (6.20)
0° - 8
°
0.016 (0.40)
0.050 (1.27)
Dimension D
Pkg Min Max
8L 0.1890(4.80) 0.1968(5.00)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc. No. 25085, Rev. 00
14
Advance Information CAT1320, CAT1321
PACKAGE OUTLINES
8-LEAD TSSOP (U, Y)
15
Doc No. 25085, Rev. 00
CAT1320, CAT1321 Advance Information
PACKAGE OUTLINES
8-PAD TDFN 4.9X3MM PACKAGE (RD2, ZD2)
8
(5)
4.90 + 0.10
1
PIN 1 INDEX AREA
3.00 + 0.10
(S)
5
A
B
5
3.00 + 0.15
8
2.00 + 0.15
0.15
0.10
0.20
0.25
0.60 + 0.10 (8X)
2x
0.15 c
d
4
2x
0.15
c
d
0.30 + 0.05 (8X)
8x
j
0.10m C A B
4
1.95 REF. (2x)
PIN 1 ID
1
0.65 TYP. (6x)
f 0.10 c
8x
0.20 REF.
d 0.08 c
C
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
COPLANARITY SHALL NOT EXCEED 0.08mm.
3. WARPAGE SHALL NOT EXCEED 0.10mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL
CHARACTERISTIC(S).
5. REFER TO JEDEC MO-229, FOOTPRINTS ARE COMPATIBLE TO 8 MSOP.
0.75 + 0.05
0.0-0.05
Doc. No. 25085, Rev. 00
16
Advance Information CAT1320, CAT1321
Ordering Information
Prefix Device # Suffix
CAT
Optional
Company ID
1320
Product
Number
1320: 32K
1321: 32K
J
I TE13
Temperature Range
I = Industrial (-40˚C to 85˚C)
-30
Tape & Reel
TE13: 2000/Reel
SOIC: 2000/Reel
TSSOP: 2000/Reel
TDFN: 2000/Reel
Package
P: PDIP
J: SOIC
U: TSSOP
RD2: 8-pad TDFN (4.9mmx3mm)
L: PDIP (Lead free, Halogen free)
W: SOIC, JEDEC (Lead free, Halogen free)
Reset Threshold
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
Y: TSSOP (Lead free, Halogen free)
ZD2: TDFN 4.9x3mm (Lead free, Halogen free)
Note:
(1) The device used in the above example is a CAT1320JI-30TE13 (Supervisory circuit with I2C serial 32k CMOS EEPROM, SOIC, Industrial
Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).
17
Doc No. 25085, Rev. 00
REVISION HISTORY
Date Rev. Reason
1/25/2005 00 Initial issue
Copyrights, Trademarks and Patents
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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #: 25085
Revison: 00
Issue date: 1/25/05
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