CATALYST CAT1021, CAT1022, CAT1023 Service Manual

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CAT1021, CAT1022, CAT1023

Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset
and Watchdog Timer

FEATURES

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■ Precision power supply voltage monitor

— 5V, 3.3V and 3V systems
— Five threshold voltage options

■ Watchdog timer

■ Active high or low reset

— Valid reset guaranteed at V

■ 400kHz I

■ 3.0V to 5.5V operation

■ Low power CMOS technology

■ 16-Byte page write buffer

2

C bus

CC

= 1 V

DESCRIPTION

The CAT1021, CAT1022 and CAT1023 are complete
memory and supervisory solutions for microcontroller­based systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection are
integrated together in low power CMOS technology.
Memory interface is via a 400kHz I2C bus.

The CAT1021 and CAT1023 provide a precision V
sense circuit and two open drain outputs: one (RESET)
drives high and the other (RESET) drives low whenever
VCC falls below the reset threshold voltage. The CAT1022
has only a RESET output and does not have a Write
Protect input. The CAT1021 also has a Write Protect
input (WP). Write operations are disabled if WP is
connected to a logic high.

All supervisors have a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. For the
CAT1021 and CAT1022, the watchdog timer monitors
the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.

CC

■ Built-in inadvertent write protection

— WP pin (CAT1021)

■ 1,000,000 Program/Erase cycles

■ Manual reset input

■ 100 year data retention

■ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN

(3 x 3 mm foot-print) packages
— TDFN max height is 0.8mm

■ Industrial and extended temperature ranges

The power supply monitor and reset circuit protect memory
and system controllers during power up/down and against
brownout conditions. Five reset threshold voltages support
5V, 3.3V and 3V systems. If power supply voltages are out
of tolerance reset signals become active, preventing the
system microcontroller, ASIC or peripherals from operating.
Reset signals become inactive typically 200 ms after the
supply voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, the RESET pin or a
separate input, MR, can be used as an input for push-button
manual reset capability.

The on-chip, 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided by a
VCC sense circuit that prevents writes to memory whenever
VCC falls below the reset threshold or until VCC reaches the
reset threshold during power up.

Available packages include an 8-pin DIP, 8-pin SOIC, 8-pin
TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN package
thickness is 0.8mm maximum. TDFN footprint options are
3x3mm.

© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

Doc No. 3009, Rev. K

CAT1021, CAT1022, CAT1023

T

T

T

L

BLOCK DIAGRAM

EXTERNAL LOAD

D

OUT

ACK

V

CC

V

SS

SDA

WP

(CAT1021)

MR

WORD ADDRESS

BUFFERS

START/STOP

LOGIC

CONTROL

LOGIC

RESET Controller

Precision

Vcc Monitor

XDEC

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

2kbit

EEPROM

DATA IN STORAGE

HIGH VOLTAGE/

TIMING CONTROL

STATE COUNTERS

SLAVE
ADDRESS
COMPARATORS

Threshold Voltage Options

Part Dash Minimum Maximum
Number Threshold Threshold

-45 4.50 4.75

-42 4.25 4.50

-30 3.00 3.15

-28 2.85 3.00

-25 2.55 2.70

SC

RESET

(CAT1021/23)

RESET

PIN CONFIGURATION

DIP Package (P, L)

SOIC Package (J, W)

TSSOP Package (U, Y)

MSOP Package (R, Z)

1

MR V

RESET

RESET

RESET

RESET

2

CAT1021

WP

3

V

4

SS

1

MR V

2

CAT1022

NC

3

V

4

SS

1

MR V

2

CAT1023

3

V

4

SS

8
7
6
5

8
7
6
5

8
7
6
5

CC

RESET
SCL
SDA

CC

NC
SCL
SDA

V

CC

CC

WDI
SCL
SDA

WDI
(CAT1023)

(Bottom View)

TDFN Package: 3mm x 3mm

0.8mm maximum height - (RD4, ZD4)

1

2

3

4

1

2

3

4

MR

1

2

RESE

3

WP

4

V

MR

RESE

NC

V

SS

MR

RESE

RESET

V

SS

SS

V

CC

RESET

SCL

SDA

V

CC

NC

SCL

SDA

V

CC

WDI

SCL

SDA

8

7

6

5

8

7

6

5

8

7

6

5

CAT1021

CAT1022

CAT1023

Doc. No. 3009, Rev. K

2

PIN DESCRIPTION

RESET/
(RESET CAT1021/23 Only)

These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-down
resistor, and the RESET pin must be connected through a
pull-up resistor.

SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.

SCL: SERIAL CLOCK
Serial clock input.

RESETRESET

RESET: RESET OUTPUTS

RESETRESET

CAT1021, CAT1022, CAT1023

MR:MR:

MR: MANUAL RESET INPUT

MR:MR:

Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset condition.
Reset outputs are active while MR input is low and for
the reset timeout period after MR returns to high. The
input has an internal pull up resistor.

WP (CAT1021 Only): WRITE PROTECT INPUT
When WP input is tied to V
operations to the entire array are allowed. When tied to
VCC, the entire array is protected. This input has an
internal pull down resistor.

WDI (CAT1023 Only): WA TCHDOG TIMER INTERRUPT

Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET
outputs will be driven active.

or left unconnected write

SS

PIN FUNCTIONS

Pin Name Function

NC No Connect

RESET Active Low Reset Input/Output

V

SS

SDA Serial Data/Address
SCL Clock Input

RESET Active High Reset Output (CAT1021/23)

V

CC

WP Write Protect (CAT1021 only)
MR Manual Reset Input

WDI Watchdog Timer Interrupt (CAT1023)

Ground

Power Supply

CAT102X FAMILY OVERVIEW

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OPERATING TEMPERATURE RANGE

Industrial -40˚C to 85˚C
Extended -40˚C to 125˚C

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For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.

3

Doc No. 3009, Rev. K

CAT1021, CAT1022, CAT1023

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to Ground

with Respect to Ground ................ –2.0V to 7.0 V

V

CC

Package Power Dissipation

Capability (T

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(1)

........... –2.0 V to VCC + 2.0 V

= 25°C)..................................1.0 W

A

(2)

........................ 100 mA

Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.

Note:
(1) The minimum DC input voltage is –0.5V. During transitions,

inputs may undershoot to
–2.0V for periods of less than 20 ns. Maximum DC voltage on
output pins is VCC +0.5V, which may overshoot to VCC +2.0V
for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than

one output shorted at a time.

DC OPERATING CHARACTERISTICS

VCC = 3.0V to 5.5V and over the recommended temperature conditions unless otherwise specified.

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Notes:

1. VIL min and VIH max are reference values only and are not tested.

2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.

Doc. No. 3009, Rev. K

4

CAT1021, CAT1022, CAT1023

CAPACITANCE

TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Test Conditions Max Units

(1)

C

OUT

(1)

C

IN

Output Capacitance V

= 0V 8 pF

OUT

Input Capacitance VIN = 0V 6 pF

AC CHARACTERISTICS

V

= 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.

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Notes:

1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

2. Test Conditions according to “AC Test Conditions” table.

3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

5

Doc No. 3009, Rev. K

CAT1021, CAT1022, CAT1023

RESET CIRCUIT AC CHARACTERISTICS

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RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units

(5)

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END

(5)

T

DR

(5)

V

ZAP

(5)(7)

I

LTH

Notes:

1. Test Conditions according to “AC Test Conditions” table.

2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

4. VCC Glitch Reference Voltage = V

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. t

7. Latch-up protection is provided for stresses up to 100 mA on input and output pins from -1 V to VCC + 1 V.

PUR

and t

Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte
Data Retention MIL-STD-883, Test Method 1008 100 Years
ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
Latch-Up JEDEC Standard 17 100 mA

; Based on characterization data

THmin

are the delays required from the time VCC is stable until the specified memory operation can be initiated.

PUW

Doc. No. 3009, Rev. K

6