2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES) DEVICES
3. PRECAUTION OF LASTER DIODE
4. GENERAL DESCRIPTION
5. PREVENTION OF STATIC ELECTRICITY DISCHARGE
5.1 GROUNDING FOR ELECTROSTATIC BREAKDOWN PREVENTION
5.1.1 WORKTABLE GROUNDING
5.1.2 HUMAN BODY GROUNDING
5.1.3 HANDING OF OPTICAL PICKUP
5.2 HANDING PRECAUTIONS FOR TRAVERSE UNIT(OPTICAL PICKUP)
6. ASSENBLING AND DISASSEMBLING THE MECHANISM UNIT
6.1 DISASSEMBLY PROCEDURE
6.2 TERMINAL PCB
6.3 CLAMP PLATE UNIT
6.4 TRAY
2
2
2
3
4
6
6
6
6
6
6
7
7
7
8
8
6.5 TRAVERSE BLOCK
6.6 TRAVERSE GEAR
6.7 OPTICAL PICKUP UNIT
6.7.1 PRECAUTIONS IN OPTICAL PICKUP REPLACEMENT
6.8 DISASSEMBLING THE MIDDLE CHASSIS
6.9 DISASSENBLING THE TRAVERSE GRAR A
6.10 DISASSEMBLING THE SPINDLE MOTOR UNIT
7. ELECTRICAL CONFIRMATION
7.1 VIDEO OUTPUT(LUMINANCE SIGNAL)CONFIRMATION
7.2 VIDEO OUTPUT(CHROMINANCE SIGNAL)CONFIRMATION
8. MPEG CHECK WAVEFORM
9. IC BLOCK DIAGRAM & DESCRIPTION
10. SCHEMATIC & PCB WIRING DIAGRAM
11. SPARE PARTS LIST
9
9
10
10
12
12
13
13
13
14
15
16
32
45
1
Page 3
1.SAFETY PRICAUTIONS
1.1 GENERAL GUIDELINES
1.When servicing,observe the original lead dress.ifa short circuit is found,replace all parts which have
been overheated or damaged by the short circuit.
2.After servicing,see to it that all the protective devices such as insulation bamiers,insulation papers
shields are properly installed.
3.After servicing,make the following leakage current checks to prevent the customer from being exposed
to thock hazards.
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD) TO ELECTROSTATECALLY
SENSITIVE(ES) DEVICES
Some semiconductor(solid state)devices can be damaged easily by static electricity.Such components
commonly are called Electrostatically Sensitive(ES)Devices.Examples of typical ES devices are integrated
circuits and some field-effect transistorsand semiconductor chip components.The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1.Immediately before handling any semiconductor component or semiconductor-equipped assembly,drain
off any ESDon your body by touching a known earth ground.Alteatively,obtain and wear a commercially
availabel discharging ESD wrist strap,which should be removed for potential shock reasons prior to
applying power to the unit under test.
2.After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil,to prevent electrostatic charge buildup or exposure of the assembly.
3.Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4.Use only an anti-static solder removal device.Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5.Do not use freon-propelled chemicals.These can generate electrical charges sufficient to damage ES
devices.
6.Do not remove a replacement ES device from its protective package until immediately before you are
ready to install if.(Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam,alminum foil or comparable conductive material).
7.Immediately before removing the protective material from the leads of a aeplacement ES device,touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit,and observe all other safety precautions.
8.Minimize bodily motions when handling unpackaged replacement ES devices.(Otherwise hamless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD)
notice (1885x323x2 tiff)
2
Page 4
3. Precaution of L aster Diode
3
Page 5
4
Page 6
5
Page 7
5.PREVERTION OF STATIC ELECTRICITY DISCHARGE
The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
1.Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground thesheet.
3.The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
6
body.Use due caution to electrostatic breakdown when servicing and handling the laser diode.
5.1.Grounding for electrostatic breakdown prevention
grounding works is completed.
5.1.1. Worktable grounding
5.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity form your body.
safety_3 (1577x409x2 tiff)
5.1.3.Handing of optical pickup
1.To keep the good quality of the optical pickup maintenance parts during transportation and before
installation,the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure.(See this Technical Guide).
2.Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
5.2.Handing precautions for Traverse Unit (Optical Pickup)
1.Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2.When replacing the optical pickup,install the flexible cable and cut is short land with a nipper.See the
optical pickup replacement procedure in this Technical Guide.Before replacing the traverse unit,remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
4.The half-fixed resistor for laser power adjustment cannot be adjusted.Do not turn the resistor.
Page 8
6.ASSEMBLING AND DISASSENBLING THE MECHANISM UNIT
7
6.1Disassembly Procedure
6.2 Terminal P.C.B.
1.Unscrew the screws.
2.Remove the solders.
3.Remove the connectors
5
Page 9
6.3 Clamp Plate Unit
8
1.Spread the stopper with hand to silde the tabs and remove the clamp plate unit.
6.4 Tray
1.Lift the tray.
6
Page 10
6.5 Traverse Block
9
1.Lift the traverse block while spreading the hook of the mechanical chassis chassis unit.
2.Disengage the tabs from the holes of the mechanical chassis unit.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
SAM0400-100401 ESS Technology, Inc.
Page 20
ES6008/18/28/38 DAT A SHEET
19
ES60X8 PIN DESCRIPTION
PRELIMINARY
Table 1 ES60x8 Pin Description (Continued)
NameNumberI/ODefinition
YUV1107OYUV1 pixel output data.
VREFIInternal voltage reference to video DAC. Bypass to ground with 0.1 µF capacitor.
YUV2
CDACOVideo DAC output. Refer to description and matrix for UDAC pin 106.
YUV3109OYUV3 pixel output data.
COMPICompensation input. Bypass to ADVEE with 0.1 µF capacitor.
YUV4110OYUV4 pixel output data.
RSETIDAC current adjustment resistor input.
ADVEE111IAnalog power for video DAC.
YUV5113OYUV5 pixel output data.
YDACOVideo DAC output. Refer to description and matrix for UDAC pin 106.
YUV6114OYUV6 pixel output data.
VDACOVideo DAC output. Refer to description and matrix for UDAC pin 106.
YUV7115OYUV7 pixel output data.
CAMIN3ICamera YUV 3.
PCLK2XSCN116I/O27-MHz video output pixel clock.
CAMIN4ICamera YUV 4.
PCLKQSCN1 17O13.5-MHz video output pixel clock.
CAMIN5ICamera YUV 5.
VSYNC#118I/OVertical sync, active low.
CAMIN6ICamera YUV 6.
HSYNC#119I/OHorizontal sync, active low.
CAMIN7ICamera YUV 7.
HD[5:0]
DCI[5:0]I/ODVD channel data I/O [5:0].
AUX1[5:0]I/OAux1 data I/O [5:0].
HD[6]
DCI[6]I/ODVD channel data I/O [6].
AUX1[6]I/OAux1 data I/O [6].
VFD_DOUTIVFD data output.
HD[7]
DCI[7]I/ODVD channel data I/O [7].
AUX1[7]I/OAux1 data I/O [7:0].
VFD_DINIVFD data input.
HD[8]
DCI_FDS#I/ODVD input sector start.
AUX2[0]I/OAux2 data I/O 0.
VFD_CLKIVFD clock input.
HD[9]
AUX2[1]I/OAux2 data I/O [1] when selected.
SQSQISubcode-Q data.
HD[10]
AUX2[2]I/OAux2 data I/O [2] when selected.
SQSKISubcode-Q clock.
108
127:122
128
131
132
133
134
OYUV2 pixel output data.
I/OHost data I/O [5:0].
I/OHost data I/O [6].
I/OHost data I/O [7].
I/OHost data bus 8.
I/OHost data bus line 9.
I/OHost data bus line10.
ESS Technology, Inc. SAM0400-100401
Page 21
PRELIMINARY
20
Table 1 ES60x8 Pin Description (Continued)
NameNumberI/ODefinition
HD[11]
AUX2[3]I/OAux2 data I/O [3] when selected.
IRQOIRQ output.
HD[12]
AUX2[4]I/OAux2 data I/O [4] when selected.
C2POIC2PO error correction flag from CD-ROM.
HD[13]
AUX2[5]I/OAux2 data I/O [5] when selected.
SPI16550 UART serial port input.
HD[14]
AUX2[6]I/OAux2 data I/O [6] when selected.
SQSIISubcode-Q sync.
HD[15]
AUX2[7]I/OAux2 data I/O [7] when selected.
IRIIR remote control input.
HWRQ#
DCI_REQ#ODVD control interface request.
AUX4[1]I/OAux4 data I/O 1.
HRRQ#143OHost read request.
AUX4[0]I/OAux4 data I/O 0.
HIRQ
DCI_ERR#I/ODVD channel data error.
AUX4[7]I/OAux4 data I/O 7.
HRST#145OHost reset.
AUX3[5]I/OAux3 data I/O 5.
HIORDY146IHost I/O ready.
AUX3[3]I/OAux3 data I/O 3.
HWR#
DCI_CLKI/ODVD channel data clock.
AUX4[5]I/OAux4 data I/O 5.
HRD#
DCI_ACK#ODVD channel data valid.
AUX4[6]I/OAux4 data I/O 6.
HIOCS16#
CAMCLKICamera port pixel clock input.
AUX3[4]I/OAux3 data I/O 4.
HCS1FX#152OHost select 1.
AUX3[7]I/OAux3 data I/O 7.
HCS3FX#153OHost select 3.
AUX3[6]I/OAux3 data I/O 6.
HA[2:0]158, 155:154I/OHost address bus.
AUX4[4:2]I/OAux4 data I/Os [4:2].
AUX[1:0]160I/OAuxiliary ports 1:0.
135
136
137
140
141
142
144
149
150
151
I/OHost data bus line11.
I/OHost data bus line12.
I/OHost data bus line13.
I/OHost data bus line14.
I/OHost data bus line15.
OHost write request.
I/OHost interrupt.
I/OHost write.
OHost read.
IDevice 16-bit data transfer.
ES6008/18/28/38 DATA SHEET
ES60X8 PIN DESCRIPTION
SAM0400-100401 ESS Technology, Inc.
Page 22
ES6008/18/28/38 DAT A SHEET
21
LICENSING REQUIREMENTS
PRELIMINARY
Table 1 ES60x8 Pin Description (Continued)
NameNumberI/ODefinition
AUX[2]162I/OAuxiliary port 2.
IOW#OI/O Write strobe.
AUX[3]165I/OAuxiliary port 3.
IOR#OI/O Read strobe.
AUX[7:3]169:166I/OAuxiliary ports 7:3.
LOE#170ODevice output enabl e.
LCS[3:0]#176:173OChip select [3:0].
LD[15:0]197:194,
Dolby Digital audio enabling softwa re is provid ed with the
Vibrat to seri es of DVD proc essors. Dolby is a tra demark of
the Dolby Labora tories. Supply of th is implementation of
Dolby Technology does not convey a license or imply a
right under any patent, or any other Industrial or
Intellectual Property Ri ght of Dolby Laboratories, to use
this implementation i n any end-user or ready-to -use final
product. Companies planning to us e this implementation
in products must obtain a license from Dolby Laboratories
Licensing Corporation before designing such products.
Additional per-chip royalties may be required and are to be
paid by the purchaser to Dolby Labor atories, Inc. Details
of the OEM Dolby Digital license may be obtained by
writing to:
Dolby Laboratories Inc.
Dolby Laboratories Licensing Corporation
Attn.: Intellectual Property Manager
100 Potrero Avenue
San Francisco, CA 94103-4813
Macrovision Licensing
Macrovision Copy Protection is su pported in the Vibratto
series of DVD processors. The use of Macrovision’s Copy
Protection technology in the device must be authorized by
Macrovision and is intended for home and other limited
pay-per-view uses only, unless otherwise authorized in
writing by Macrovision.
Reverse engineering or disassembly is prohibited. A valid
Macrovision license must be in effect between the Vibratto
purchaser and Macrovision Corporation. Additional perchip royalties ma y be required and are to be paid by th e
purchaser to Macrovision Corporation. Details of the
Macrovision license may be obtained by writing to:
Macrovision Corporation
1341 Orleans Avenue
Sunnyvale, CA 94089
ESS Technology, Inc. SAM0400-100401
Page 23
PRELIMINARY
22
FUNCTIONAL DESCRIPTION
Figure 3 shows the internal block diagram for the basic Vibratto DVD processor.
The Vibratto device architecture includes a RISC
processor, CRT controller, transport mechanism, video
encoder, memory controller, on-screen display (OSD)
controller and video processor.
ESS RISC Processor
Embedded in the Vibratto is a 32-bit data pipelin ed RISC
processor, with a combined 16 kb instruction and data
done mostly in C. Fo r applications involving an external
host processor the communication between a host
processor and the Vibratto is ha ndled by a host inte rface
module. The host interface can also be used for high
speed data input and output.
The ESS RISC processor instruction and data cache
subsystem is organ iz ed as a t wo- way s et a ss ocia tiv e. O n
a cache load-miss and write-miss, the cache lines are
allocated into the cache memory.
cache subsystem. Programming of the RISC processor is
SAM0400-100401 ESS Technology, Inc.
Page 24
2 Megabit (256 K x 8-Bit)
IC BLOCK DIAGRAM & DESCRIPTION
IC U214 Am29F002B/Am29F002NB
23
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F002 device
■ High performanc e
— Access times as fast as 55 ns
■ Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 20 mA read current
— 30 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be loc k ed v ia pr ogr ammi ng eq uipme nt
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bot tom boot blo ck co nfigurations a vaila ble
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycle guarantee per
sector
■ 20-year data retention at 125°C
— R eliable operation for the life of the system
■ Package option
— 32-pin PDIP
— 32-pin TSOP
— 32-pin PLCC
■ Compatibility with JEDEC standards
— Pinout and software compatible with
single-power supply Flash
— Super ior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data (not available on Am29F002NB)
Page 25
PRODUCT SELECTOR GUIDE
IC BLOCK DIAGRAM & DESCRIPTION
24
Family Part NumberAm29F002B/Am29F002NB
= 5.0 V ± 5%-55
V
Speed Option
Max access time, ns (t
Max CE# access time, ns (t
Max OE# access time, ns (t
CC
= 5.0 V ± 10%-70-90-120
V
CC
)557090120
ACC
)557090120
CE
)30303550
OE
Note: See “AC Characteristics” for full specifications.
WE#= Write enable
RESET#= Hardware reset pin, active low
(not available on Am29F002NB)
=+5.0 V single power supply
V
CC
V
SS
NC= Pin not connected internally
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
= Device ground
CE#
OE#
WE#
RESET#
N/C on Am29F002NB
Page 28
4 Banks x 1M x 16Bit Synchronous DRAM
IC BLOCK DIAGRAM & DESCRIPTION
IC U206 SDRAM-HY57V65162B
27
DESCRIPTION
The Hyundai HY57V651620B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. HY57V651620B is organized as 4banks
of 1,048,576x16.
HY57V651620B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•Single 3.3V ± 10% power supply
•All device pins are compatible with LVTTL interface
•JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•All inputs and outputs referenced to positive edge of
system clock
•Data mask function by UDQM or LDQM
•Internal four banks operation
ORDERING INFORMATION
Part No.Clock FrequencyPowerOrganizationInterfacePackage
HY57V651620BTC-7I143MHz
HY57V651620BTC-75I133MHz
HY57V651620BTC-10SI100MHz
HY57V651620BLTC-7I143MHz
HY57V651620BLTC-75I133MHz
HY57V651620BLTC-10SI100Mhz
Normal
•Auto refresh and self refresh
•4096 refresh cycles / 64ms
•Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•Programmable CAS Latency ; 2, 3 Clocks
power
4Banks x 1Mbits
x16
Lower
Power
LVTTL400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
RAS, CAS and WE define the operation
Refer function truth table for details
Page 30
FUNCTIONAL BLOCK DIAGRAM
I/O Buffer & Logic
IC BLOCK DIAGRAM & DESCRIPTION
29
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
& timer
Row active
State Machine
refresh
Column
Active
Internal Row
counter
Row
Pre
Decoders
Column
Pre
Decoders
1Mx16 Bank 3
X decoders
1Mx16 Bank 2
X decoders
X decoders
1Mx16 Bank 1
1Mx16 Bank 0
X decoders
Memory
Y decoders
Cell
Array
Sense AMP & I/O Gate
DQ0
DQ1
DQ14
DQ15
Bank Select
A0
A1
A11
BA0
BA1
Address buffers
Address
Registers
Mode Registers
Column Add
Counter
Burst
Counter
CAS Latency
Data Out Control
Pipe Line Control
Page 31
ABSOLUTE MAXIMUM RATINGS
IC BLOCK DIAGRAM & DESCRIPTION
30
ParameterSymbolRatingUnit
Ambient TemperatureTA-40 ~ 85°C
Storage TemperatureTSTG-55 ~ 125°C
Voltage on Any Pin relative to VSSVIN, VOUT-1.0 ~ 4.6V
Voltage on VDD relative to VSSVDD, VDDQ-1.0 ~ 4.6V
Short Circuit Output CurrentIOS50mA
Power DissipationPD1W
Soldering Temperature ⋅ TimeTSOLDER260 ⋅ 10°C⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA= -40 to 85°C)
ParameterSymbolMinTyp.MaxUnitNote
Power Supply VoltageVDD, VDDQ3.03.33.6V1
Input High VoltageVIH2.03.0VDDQ + 2.0V1,2
Input Low VoltageVILVSSQ - 2.000.8V1,3
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 4.7V AC pulse width with ≤3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA= -40 to 85°C, VDD=3.3V ± 0.3V, VSS=0V)
ParameterSymbolValueUnitNote
AC Input High / Low Level VoltageVIH / VIL2.4/0.4V
Input Timing Measurement Reference Level VoltageVtrip1.4V
Input Rise / Fall TimetR / tF1ns
Output Timing Measurement Reference LevelVoutref1.4V
Output Load Capacitance for Access Time MeasurementCL50pF1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Page 32
! 3-Termainal Regulators
IC WS7805
POSITIVE-VOLTAGE REGULATORS
25
V
)
WS7805DP
TO-220
WS7805CV
O
C
I
TO-252
IC BLOCK DIAGRAM & DESCRIPTION
31
! Output Current Up to 1.5 A
! No External Components
! Internal Thermal Overload Protection
! High Power Dissipation Capability
! Internal Shot-Circuit Current Limiting
! Output Transistor Safe-Area
Compensation
DESCRIPTION
This series of fixed-voltage monolithic integrated-circuit
voltage regulators designed for a wide range of
applications. These applications include on-card
regulation for elimination of noise and distribution
problems associated with single-point regulation. Each
of these regulators can deliver up to 1.5 amperes of
output current. The internal current limiting and thermal
shutdown features of these regulators make them
O
C
I
(TO-252)
essentially immune to overload.
ABSOLUTE MAXIMUM RATINGS OVER OPERATING TENPERATURE
RANGE (UNLESS OTHERWISE NOTE
WS7805PARAMETERUNIT
Input voltage, V
Continuous total dissipati on at 25℃ free-air temperature
Lead temperature 1.6mm (1/16 inch) from case 10 seconds260
Storage temperature range, T
I
stg
RECOMMEMDED OPERATING CONDITIONS
Input voltage, V
Output current, I
Operating virtual junction temperature, T