AUSTN AS5C4009LLDG-70-883C, AS5C4009LLDG-55-XT, AS5C4009LLDG-55-IT, AS5C4009LLDG-55-883C, AS5C4009LLDG-100-XT Datasheet

SRAM

Austin Semiconductor, Inc.

AS5C4009LL

512K x 8 SRAM

Ultra Low Power SRAM

PIN ASSIGNMENT

AVAILABLE AS MILITARY

(Top View)

SPECIFICATION

32-Pin DIP, 32-Pin SOJ

• SMD 5962-95613 1,2

& 32-Pin TSOP

• MIL STD-883 1

FEATURES

A18

1

32

Vcc

•

Ultra Low Power with 2V Data Retention

A16

2

31

A15

(0.2mW MAX worst case Power-down standby)

A14

3

30

A17

•

Fully Static, No Clocks

A12

4

29

WE\

•

Single +5V ±10% power supply

A7

5

28

A13

•

Easy memory expansion with CE\ and OE\ options

A6

6

27

A8

•

All inputs and outputs are TTL-compatible

A5

7

26

A9

•

Three state outputs

•

Operating temperature range:

A4

8

25

A11

Ceramic

-55oC to +125oC & -40oC to +85oC

A3

9

24

OE\

Plastic

-40oC to +85oC3

A2

10

23

A10

1. Not applicable to plastic package

A1

11

22

CE\

2. Applies to CW package only.

3. Contact factory for -55oC to +125oC

A0

12

21

I/08

OPTIONS

MARKING

I/01

13

20

I/07

•

Timing

I/02

14

19

I/06

55ns access

-554

I/03

15

18

I/05

70ns access

-70

Vss

16

17

I/04

85ns access

-85

100ns access

-100

•

Packages

Ceramic Dip (600 mil)

CW

No. 112

Ceramic SOJ5

ECJ

No. 502

Plastic TSOP

DG

No. 1002

4.For DG package, contact factory

5.Contact Factory

NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specific part number

combinations.

GENERAL DESCRIPTION

The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. ASI’s pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design.

For flexibility in memory applications, ASI offers chip enable (CE\) and output enable (OE\) capabilities. These features can place the outputs in High-Z for additional flexibility in system design.

This devices operates from a single +5V power supply and all inputs and outputs are fully TTL-compatible.

Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled, by lowering VCC to 2V and maintaining CE\ = 2V. This allows system designers to meet ultra low standby power requirements.

Pin Name	Function
WE\	Write Enable Input
CE\	Chip Select Input
OE\	Output Enable Input
A0 - A18	Address Inputs
I/O1 - I/O8	Data Inputs/Outputs
Vcc	Power
Vss	Ground

For more products and information please visit our web site at www.austinsemiconductor.com

AS5C4009LL	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 4.0 2/01	1

SRAM

AS5C4009LL

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

		Clk. gen.	Precharge circuit
	A18
	A16
	A14
	A12		Memory Array
		Row	1024 rows
	A7	select	512 x 8 columns
	A6
	A5
	A4
	A1
	A0

	I/O1	Data			I/O Circuit
	I/O8	cont			Column Select
		Data
		cont
		A9	A8	A13	A17	A15	A10	A11	A3	A2
CE\
WE\		Control
		logic
OE\

AS5C4009LL	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 4.0 2/01	2

SRAM

AS5C4009LL

Austin Semiconductor, Inc.

ABSOLUTEMAXIMUMRATINGS*
Voltage on Vcc Supply Relative to Vss...................	-.5V to +7.0V
Voltage on any pin Relative to Vss..........................	-.5V to +7.0V
Storage Temperature ....................................	-65°C to +150°C
Operating Temperature Range.............................	-55oC to +125oC
Soldering Temperature Range...............................................	260oC
Maximum Junction Temperature**....................................	+150°C
Power Dissipation...................................................................	1.0W

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < TA < 125oC; Vcc = 5V +10%)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input Leakage Current (VIN = VSS to VCC)

ILI

-5

5

μΑ

Output Leakage Current

ILO

-5

5

μΑ

(CE\=VIH or OE\=VIH or WE\=VIL, VIO=VSS to VCC)

Output Low Voltage (IOL = 2.1mA)

VOL

--

0.4

V

15

Output High Voltage (IOH = -1.0 mA)

VOH

2.4

--

V

15

Supply Voltage

VCC

4.5

5.5

V

15

Input High (Logic 1) Voltage

VIH

2.2

Vcc +0.5

V

1, 15

Input Low (Logic 0) Voltage

VIL

-0.5

0.8

V

2, 15

MAX

PARAMETER

CONDITIONS

SYM

-55

-70

-85

-100

UNITS

NOTES

Power Supply Current:

Cycle Time = Min., 100%

Duty Cycle, IIO = 0mA,

Icc1

100

90

80

70

mA

3

Operating

CE\ = VIL, VIN = VIH or VIL

TTL

CE\ = VIH,

ISB

6

6

6

6

mA

Other inputs = VIL or VIH

Power Supply Current:

Standby

CMOS

CE\ = Vcc -0.2V,

ISB1

0.75

0.75

0.75

0.75

mA

Other inputs = 0 ~ Vcc

AS5C4009LL	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 4.0 2/01	3

																				SRAM
		Austin Semiconductor, Inc.																AS5C4009LL
	CAPACITANCE
	PARAMETER			CONDITIONS								SYMBOL		MAXIMUM					UNITS			NOTES
	Input Capacitance			TA = 25oC, f = 1MHz					VIN=0V			CIN		8					pF			4
	Input/Output Capactiance			VCC = 5V					VIO=0V			CIO		10					pF			4
	ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
	(-55oC < T < 125oC; Vcc = 5V +10%)
	A
	DESCRIPTION					-55				-70				-85		-100
				SYM		MIN	MAX			MIN		MAX	MIN		MAX	MIN			MAX	UNITS			NOTES
	READ Cycle
	READ cycle Time			t RC		55				70			85			100				ns
	Address access time			t AA			55					70			85				100	ns
	Chip Enable access time			t ACE			55					70			85				100	ns
	Output hold from address change			t OH		10				10			10			10				ns
	Chip Enable to output in Low-Z			t LZCE		10				10			10			10				ns			4,6
	Chip disable to output in High-Z			t HZCE			20					25			30				30	ns			4,6
	Chip Enable to power-up time			t PU		0				0			0			0				ns			4
	Chip disable to power-down time			t PD			55					70			85				100	ns			4
	Output Enable access time			t AOE			30					35			40				45	ns
	Output Enable to output in Low-Z			t LZOE		5				5			5			5				ns			4,6
	Output disable to output in High-Z			t HZOE			20					25			30				30	ns			4,6
	WRITE Cycle
	WRITE cycle time			t WC		55				70			85			100				ns
	Chip Enable to end of write			t CW		50				60			70			80				ns
	Address valid to end of write			t AW		50				60			70			80				ns
	Address setup time			t AS		0				0			0			0				ns
	Address hold from end of write			t AH		0				0			0			0				ns
	WRITE pulse width			t WP1		50				60			70			80				ns
	Data setup time			t DS		30				30			35			40				ns
	Data hold time			t DH		0				0			0			0				ns
	Write disable to output in Low-Z			t LZWE		5				5			5			5				ns			4,6
	Write Enable to output in High-Z			t HZWE			25					25			30				30	ns			4,6

AS5C4009LL	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 4.0 2/01	4