AudioCodes AC48302C-C, AC48301C-C Data Book

AC4830xC-C VoPP
Data Book
Revision 1.0
Catalog Number LTRT-00060
US: AudioCodes Inc, 2841 Junction Ave, Suite 114, San Jose, CA 95134.
International: AudioCodes Ltd, 4 HaHoresh Rd, PO Box 14, Yehud 56470, Israel.
Tel: 408-577-0488 –- Fax: 408-577-0492
Tel: +972-3-539 4000 –- Fax: +972-3-539 4061 Technical Support: support@audiocodes.com
AC4830xC-C Data Book General
About this Data Book
Purpose and Scope
This Data Book describes the hardware and timing characteristics, applications and use of the AC4830xC-C VoPP, Voice over Packet Processors, from AudioCodes Ltd. It is designed for reading by any regular User without specialist skills but familiar with the applications, products and services of AudioCodes Ltd.
Structure of this Manual
The Data Book has the following sections, which will help you to find the information you need:
For Information on: Look at Chapter:
Release Notes, Notices and Warranty Contents, Figures and Tables Overview and Features
The Interfaces of the AC4830xC-C Specification of the AC4830xC-C.
Applications, Evaluation System and Testing PCM Highway Interface
Full Index of the Data Book
General Contents
1. Introduction
2. Functional Interfaces
3. Chip Data and Timing
4. Application Notes
5. PCM Highway Interface Index
Abbreviations and Terminology
Each abbreviation, unless widely used, is spelled out in full when first used, and only Industry standard terms are used throughout this manual. The $ symbol indicates hexadecimal notation.
Data Book Revision 1.0 - Release Note
This Data Book describes the latest Hardware and timing specifications for the AC4830xC-C. The Software specifications are described in “AC4830xC-C Designer’s Manual”, Catalog Number LTRT-00066.
Acknowledgements
NetFax® and NetCoder® are registered by AudioCodes Ltd.
AudioCodes acknowledges that various products referred to in this manual are subject to copyright and/or trademark by their respective registered holders.
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AudioCodes Ltd.
Notice
This Data Book describes the AC4830xC-C VoPP (Voice over Packet Processors) from AudioCodes Ltd.
Information contained in this document is believed to be accurate and reliable at the time of printing. However, due to ongoing product improvements and revisions, AudioCodes Ltd. cannot guarantee accuracy of printed material after the Date Published nor can it accept responsibility for errors or omissions.
For
Technical Support
e-mail: support@audiocodes.com
please contact:
In the US, fax 408-577-0492
In other countries, fax +972-3-539-4041
© Copyright 2000 AudioCodes Ltd.
This document is subject to change without notice.
Date Published: Mar-22-2000 Date Printed: Mar-22-2000
General Warranty.
AudioCodes Ltd. (hereinafter "AudioCodes") warrants that its Products (hereinafter "Products") shall conform to Aud ioCodes’ published specificat ions for a peri od of one (1) year. The foregoing warrant y does not apply to any Products which have been subject to misuse, neglect, accident, or modification or which have been alt ered and ar e not capable of being tested by AudioCodes under its normal test conditions. AudioCodes’ sole obligati on to the Purchaser (hereinaft er "Buyer") hereunder for Products failing to meet the aforesaid warranty shall be, at AudioCodes' discretion, to replace the non-conforming Products or issue t he Buyer credit for the purchase price of the non-conforming Products, where wi thin the warrant y period: 1) AudioCodes has received written notice of any nonconformity; and 2) After AudioCodes' writ ten authorization to do so the Buyer has returned the non-conformi ng Products to AudioCodes, freight prepaid; and 3) AudioCodes has determined that the Products are non-conforming and that such nonconformity is not a result of the Buyer’s conduct . No Products may be used in a life support application. AudioCodes warrants that the Products sold hereund er shall at the t ime of shipmen t be free and clear of liens and encumbrances. This warranty extends to t he Buyer only and may be invoked by the Buyer for its customers. AudioCodes shall not accept warranty returns directly from the Buyer’s customers or users of the Buyer’s products or devices. This warranty is in lieu of all othe r warranti es whether express, impl ied or statutory i ncluding implie d warrant ies of merchantability or fitness for particular purpose. AudioCodes shall not be l iabl e for damages due to delays in deliveries or use. In no event shall AudioCodes be liable for any incidental or consequential damages due to breach of this warranty or f or any infringement action initiated by a t hird part y. The Buyer’s sole remedy for any brea ch shall be limited to the remedies set forth herein and shall not exceed the sale price for the Products.
AC4830xC-C VoPP
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Catalog Number: LTRT-00060
AC4830xC-C Data Book Contents
Table of Contents
1
Introduction 7
1.1 Overview.....................................................................................................................7
1.2 Features.......................................................................................................................8
2
Functional Description 11
2.1 Overview...................................................................................................................11
2.2 Interfaces...................................................................................................................13
2.2.1 Voice Interface................................................................................................14
2.2.2 PCM Clock Generator..................................................................................... 15
2.2.2.1 Examples of External Crystal Use:........................................................ 16
2.2.3 Host Port Interface ..........................................................................................17
2.2.4 Memory, I/O and CAS Interface......................................................................19
2.2.5 Channel Associated Signaling Port..................................................................21
2.2.6 Test Access Port.............................................................................................. 23
2.3 HPI on-chip Memory Map .........................................................................................24
2.4 Pin Description .......................................................................................................... 25
2.4.1 Signals and Pin-out 144-pin TQFP package ..................................................... 25
3
Chip Data and Timing 31
3.1 General Specifications ............................................................................................... 31
3.2 Electrical Characteristics and Operating Conditions....................................................32
3.2.1 Absolute Maximum Ratings over Specified Temp. Range................................32
3.2.2 Electrical Characteristics.................................................................................34
3.3 Timing Characteristics ............................................................................................... 35
3.3.1 Memory and I/O Interface Timing...................................................................35
3.3.1.1 Memory Read....................................................................................... 35
3.3.1.2 Memory Write......................................................................................37
3.3.1.3 General I/O Read Timing .....................................................................38
3.3.1.4 I/O Write Timing.................................................................................. 39
3.3.2 PCM Port Timing when External Codec Used .................................................40
3.3.2.1 PCM Port Receive Timing (using Codec) .............................................40
3.3.2.2 PCM Port Transmit Timing (using Codec) ............................................ 41
3.3.3 PCM Port Timing with Clock from PCM Framer............................................. 43
3.3.3.1 PCM Port Receive Timing (using PCM Framer) ................................... 43
3.3.3.2 PCM Port Transmit Timing (using PCM Framer) ....................................44
3.3.4 Host Port Interface Timing..............................................................................45
3.3.4.1 Host Port Interface Switching Characteristics........................................45
3.3.4.2 Host Port Interface Timing Requirements .............................................46
3.3.5 Reset Timing ..................................................................................................50
3.3.6 External Crystal Option................................................................................... 51
3.4 Packaging Specifications............................................................................................52
4
Applications 53
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4.1 Interface Application Using PCM Framer/Codec ........................................................53
54
4.2 Interface Application Using Codec .............................................................................55
5
PCM Highway Interface 57
5.1 E1 PCM Highway......................................................................................................57
Index....... 59
AC4830xC-C VoPP
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Catalog Number: LTRT-00060
AC4830xC-C Data Book Contents .
IST OF FIGURES
L
Figure 1-1: AC4830xC-C Chip.................................................................................................................... 7
Figure 2-1: AC4830xC-C Application Diagram for Each Channel ..............................................................12
Figure 2-2: AC4830xC-C Interface Diagram..............................................................................................13
Figure 2-3: AC4830xC-C Voice and Signaling Interface ............................................................................14
Figure 2-4: PLLMUL Register Contents.................................................................................................... 15
Figure 2-5: AC4830xC-C Host Port Interface (HPI) Signals ....................................................................... 17
Figure 2-6: AC4830xC-C Memory & I/O Interface Signals ........................................................................ 19
Figure 2-7: AC4830xC-C CAS Port Interface ............................................................................................ 21
Figure 2-8: E&M AB Signaling................................................................................................................. 21
Figure 2-9: AC4830xC-C Test Access Port Interface.................................................................................. 23
Figure 2-10: AC4830xC-C HPI Memory Map............................................................................................ 24
Figure 3-1: Memory Read Timing ............................................................................................................. 36
Figure 3-2: Memory Write Timing............................................................................................................. 37
Figure 3-3: I/O Read Timing ..................................................................................................................... 38
Figure 3-4: I/O Write Timing .................................................................................................................... 39
Figure 3-5: PCM Port Receive Timing Requirements (using Codec)........................................................... 41
Figure 3-6: PCM Port Transmit Timing Requirements (using Codec).......................................................... 42
Figure 3-7: PCM Port Receive Timing (using PCM Framer)....................................................................... 43
Figure 3-8: PCM Port Transmit Timing (using PCM Framer) ..................................................................... 44
Figure 3-9: Read/Write Access Without HRDY or HAS-............................................................................ 47
Figure 3-10: Read/Write Access Using HAS- Without HRDY.................................................................... 48
Figure 3-11: Read/Write Access with HRDY............................................................................................. 49
Figure 3-12: HRDY Signal when HCS- is Always Low.............................................................................. 50
Figure 3-13: Reset Timing......................................................................................................................... 51
Figure 3-14: Internal Clock Option............................................................................................................ 51
Figure 3-15: TQFP Packaging Specifications............................................................................................. 52
Figure 4-1: Typical Interface Application (Framer/Codec).......................................................................... 54
Figure 4-2: Typical Interface Application (Codec)...................................................................................... 56
Figure 5-1: E1 Timing............................................................................................................................... 57
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List of Tables
Table 1-1: Available Features ..................................................................................................................... 9
Table 2-1: External Crystal Examples.........................................................................................................16
Table 2-2: HPI On-chip DPR Registers ......................................................................................................25
Table 2-3: AC4830xC-C Signals and Pin-out TQFP Package (continues on 6 pages) ...................................25
Table 3-1: General Specifications (continues on 2 pages)............................................................................31
Table 3-2: Characteristics over Recommended Operating Conditions..........................................................33
Table 3-3: Electrical Characteristics...........................................................................................................34
Table 3-4: Memory Read Timing Requirements .........................................................................................35
Table 3-5: Memory Write Timing Requirements.........................................................................................37
Table 3-6: I/O Read Timing Parameters .....................................................................................................38
Table 3-7: I/O Write Timing Parameters.....................................................................................................39
Table 3-8: PCM Port Receive Timing Requirements (using Codec).............................................................40
Table 3-9: PCM Port Transmit Switching Characteristics (using Codec)......................................................41
Table 3-10: PCM Port Transmit Timing Requirements (using Codec) .........................................................41
Table 3-11: PCM Port Receive Timing (using PCM Framer).......................................................................43
Table 3-12: PCM Port Transmit Switching Characteristics (using PCM Framer)..........................................44
Table 3-13: PCM Port Transmit Timing (using PCM Framer).....................................................................44
Table 3-14: Host Port Interface Switching Characteristics...........................................................................45
Table 3-15: Host Port Interface Timing Requirements.................................................................................46
Table 3-16: Timing Parameters for Reset....................................................................................................50
Table 3-17: TQFP Thermal Resistance Characteristics................................................................................52
AC4830xC-C VoPP
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Catalog Number: LTRT-00060
AC4830xC-C Data Book Chapter 1. Introduction
1 INTRODUCTION
1.1 Overview
The AC4830xC-C Voice over Packet Processors are state-of-the-art systems on a single chip. They provide configurable, low-bit-rate voice compression and fax relay functions for one or two independent voice and fax channels.
There are currently two members of the AC4830xC-C family:
AC48302C-C - dual channels for client applications
AC48301C-C - single channel for client applications.
Figure 1-1: AC4830xC-C Chip
Revision 1.0
ADVANTAGES
Low cost
Independent channel operation
Toll quality voi ce compr ession
Robust bandwidth-saving fax relay
Small foot pr int
Low power consumption
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APPLICATIONS
Cable telephony access devices
SOHO voice/data access devices
DSL access devices
Voice enabled set-top boxes
1.2 Features
1 or 2 channels of G.729A, G.723.1, G.727, G.726, G.711 and NetCoder
codecs
T.38 or FRF.11 compliant fax relay at 2.4 – 14.4 kbps
Caller ID generation and detection
Automatic switching to PCM or ADPCM upon fax/data detection
G.168-compliant 25 ms length, adaptive Echo Canceler
High performance Voice Activity Detector (VAD) and Comfort Noise Generator
(CNG)
DTMF detection and generation
Call Progress and User-defined tones detection and generation
Clock and Frame Synchronization outputs to an external codec
Parallel host processor interface
Selectable µ-law/A-law PCM codec interface
PCM highway interface for voice, fax and data
Input and output gain control
E&M and AB signaling options
®
voice
AC4830xC-C VoPP
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Catalog Number: LTRT-00060
AC4830xC-C Data Book Chapter 1. Introduction
Table 1-1: Available Features
Feature AC48301C-C AC48302C-C
Number of Channels 1 2 G.711, G.726, G.727 G.723.1 G.729A NetCoder VAD and CNG G.168 Echo Canceler
√√√√ √ √√√√ √ √√√√ √ √√√√ √ √√√√ √ √√√√ √
√√√ √√√ √√√ √√√ √√√ √√√
Echo Canceler Tail length (ms) 25 25 DTMF TIA 464B MF-R1, MF-R2, SS-4, SS-5, AC15 Call progress, User defined Bellcore Std. Caller ID generation &
√√√√ √ √√√√ √ √√√√ √ √√√√ √
√√√ √√√ √√√ √√√
detection CAS E&M signaling Input and output gain control G3 Fax relay (T.38-compliant) G3 Fax relay (FRF.11-compliant) Automatic voice/fax/data switching Bad Frame Interpolation (BFI) µ/A-Law - PCM companding Parallel Host Interface (8-bit)
√√√√ √ √√√√ √ √√√√ √ √√√√ √ √√√√ √ √√√√ √ √√√√ √ √√√√ √
√√√ √√√ √√√ √√√ √√√ √√√ √√√ √√√
Power supply - core (V) 1.8 1.8 Power supply - I/O (V) 3.3 3.3 ANSI-C source code driver TQFP Package, 144 pins
√√√√ √ √√√√ √
√√√ √√√
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Reader’s Notes
AC4830xC-C VoPP
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Catalog Number: LTRT-00060
AC4830xC-C Data Book Chapter 2. Functional Description
2 FUNCTIONAL DESCRIPTION
2.1 Overview
The AC4830xC-C voice processor family supports one or two low-bit-rate voice, fax or data transmission channels. For voice transmission, the analog input is digitized using an external PCM codec, input through the AC4830xC-C PCM interface, and compressed to one of the supported bit rates. Fax transmissions are automatically detected and demodulated by the integrated NetFax detected and cause the AC4830xC-C to switch to PCM mode. The AC4830xC-C transfers the resultant bit-stream (compressed voice or demodulated fax for all the channels) in packets to the Host processor through the integral Host Port Interface.
The AC4830xC-C performs receive and transmit operations simultaneously. It receives compressed, packetized speech data from a remote AC4830xC-C unit, through the Host Port Interface. It decompresses speech data and transmits it through the PCM voice interface. It also remodulates and transmits fax signals to the fax machine in analog form. The fax relay process is transparent for the transmitting and the receiving fax machines.
Many other built-in features support use of the AC4830xC-C in a wide range of integrated voice, fax and data access, transmission and switching systems.
The features include voice activity detector (VAD), comfort noise generator (CNG) and adaptive Echo Canceler. Additionally, both In-band Signaling (Detection and Generation of: MF-R1, MF-R2, SS-4, SS-5, DTMF tones, Call Progress tones, User­defined tones) and Channel Associated Signaling (E&M: A and AB) are provided.
2-1 on page 12 is a simplified Application Diagram for each of the AC4830xC-C
Figure channels.
®
Engine. Data transmissions are
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Figure 2-1: AC4830xC-C Application Diagram for Each Channel
Voice Compression
· G.729A CS-ACELP @ 8.0 kbps
· G.723.1 MP-MLQ @ 6.3 / 5 . 3 kbps
· G.726 ADPCM @ 16-40 kbps
· G.727 E-ADPCM @ 16-40 kbps
· G.711 PCM @ 64 kbps
· NetCoder @ 6.4-9.6 kbps
G3 FAX Relay
@2400-14400
Voice/Fax/Data Discriminator/
MUX
Codec/
PCM Highway
Interface
Voice
Data ByPass
Baseband Processing
· VAD/CNG
· G.168 Echo Cancellation
· Call Progress
· DTMF Detection/Generation
· Bad Frame Interpolation
· User-defined Tones
· IBS / CAS / TAP
bps
Voice/Fax/Data
Packetizer/
MUX
Host I/F
Host
Processor
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Catalog Number: LTRT-00060
AC4830xC-C Data Book Chapter 2. Functional Description
2.2 Interfaces
The various interfaces are shown below in Figure 2-2, and are described individually in the following pages.
Figure 2-2: AC4830xC-C Interface Diagram
PCM
Crystal
Test I/F
Voice
Interface
PCM Clock
Generator
Test
Access
Port
AC4830xC-C
Host Port Interface
8-bit
Control
HOST
Memory &
I/O Interface
SIGEN-
IOS-
R/W-
MS-
16-bit
16-bit
Data
Address
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2.2.1 Voice Interface
The AC4830xC-C uses the Voice Interface for input and output of uncompressed voice, data and fax. It performs voice input and output as a 64 kbps companded A-Law or µ­Law PCM.
The voice input is received through PCMIN, and the voice output is sent through PCMOUT.
PCMCLK is a 2.048 MHz clock that can be generated internally from the AC4830xC­C, or externally from a codec.
PCMFS is the PCM Frame Sync, that is generated every 125 µsec to comply with the
E1 transmission rate of 8,000 frames per sec. PCMFS can be generated internally from the AC4830xC-C, or externally from a codec.
The User can attach the AC4830xC-C directly to a PCM highway.
Figure
PCM OUT
PCM IN
PCMCLK
PCMFS
2-3: AC4830xC-C Voice and Signaling Interface
Voice
Interface
Memory
& I/O
PCM Clock
Generator
AC4830xC-C
Interface
AC4830xC-C VoPP
TAP
HPI
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Catalog Number: LTRT-00060
AC4830xC-C Data Book Chapter 2. Functional Description
2.2.2 PCM Clock Generator
A built-in PCM Clock Generator enables the sourcing of an external codec device, with the PCM Clock and PCM Frame Sync from the AC4830xC-C. The operation of the PCM Clock Generator is fully controlled by the PCM Command Sequence, using the PCMCLK control.
The PCM Clock Generator can use a wide range of CLKIN-Crystal clock inputs, providing the User with a cost-effective solution. See Table 2-1 for some examples of external crystals. The internal circuitry derives the AC4830xC-C working clock (CLKOUT) from the AC4830xC-C clock input, and also the PCM Clock and the Frame Sync characteristics.
The setting of the AC4830xC-C working clock is made by modifying the PLLMUL field of the last word of the Kernel File, which is the PLLMUL Register, as shown in Figure 2-4. The PLLMUL range is $00 to $0E. The working clock is indicated by the CLKOUT signal.
Figure 2-4
:
PLLMUL Register Contents
Bit Number
Contents
Special care must be taken while modifying the file to avoid damaging its content and to follow up the required working clock. The working clock range must be in the limits
98.304 to 100.00 MHz. The following section shows some examples of the use of external crystals, based on the formula:
Please refer to AC4830xC-C Designer’s Manual, Catalog Number LTRT-00066, for details of the PCM Command sequence.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLMUL $07 $FE
CLKOUT
[98.304 to 100.00]
=
CLKIN
x (PLLMUL+1)
[MHz]
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2.2.2.1 Examples of External Crystal Use:
Table 2-1: External Crystal Examples
Crystal
Frequency MHz
20
25
16.384
12.288
8.192
2.048
PLLMUL
4 100
3 100
5 98.304
7 98.304
11 98.304
47 98.304
CLKOUT
MHz
Source for
2.048 MHz
Do Not Use
Do Not Use
Yes
Yes
Yes
Do Not Use
Notes
Default Value in Kernel File
See Section
PLLMUL must be <15
3.3.1 on page 35
-
-
-
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AC4830xC-C Data Book Chapter 2. Functional Description
2.2.3 Host Port Interface
The Host Port Interface (HPI) is an 8-bit parallel port used for communications between the Host processor and AC4830xC-C. Both the Host processor and AC4830xC-C can access and exchange information through the on-chip shared memory of the
AC4830xC-C. Please refer to the HPI on-chip Memory Map in Figure
An 8-bit data bus (HD0 to HD7) exchanges information with the Host. Because of its 16-bit word structure, the AC4830xC-C expects all transfers to consist of two consecutive bytes. A dedicated pin (HI/LO) indicates whether the first or second byte is being transferred.
Two control pins, HRS0 and HRS1, control Host access to the HPI. The Host can access the internal control register and address the internal memory.
The Host can also interrupt the AC4830xC-C by writing to its internal control register. Conversely, the AC4830xC-C can interrupt the Host with the HINT- signal, which the Host can acknowledge and clear.
Figure
2-5 illustrates the signals of the Host Port Interface.
Figure 2-5: AC4830xC-C Host Port Interface (HPI) Signals
VOICE
Interface
2-10 on page 24.
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TAP
HI/LO-
HPISEL-
AC4830xC-C
Host Port Interface
HR/W-
HRD-
HOST
HWR-
17
CS-
HAS-
MEMORY & I/O
Interface
HINT-
HRDY
HRS0-1
HD0-HD7
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The AC4830xC-C has 2 data strobes (HRD- and HWR-), a read/write strobe (HR/W-), and an address strobe (HAS-). These strobes establish a “glueless” interface with a variety of industry-standard Host processors. The HPI is easily connected to the Host with a multiplexed address/data bus, individual address/data buses, a data strobe, and either one read/write strobe or two separate strobes for read and write.
An HPI ready pin (HRDY) is provided for Hosts that support an asynchronous input to insert wait states. This is useful if the Host is capable of accessing data at a faster rate than the maximum HPI access rate. The HRDY pin provides a convenient way to automatically adjust the Host access rate (no software handshake is necessary).
Note: During Kernel Download, access timing to HPI is very different from the
access timing in other modes of operation.
AC4830xC-C VoPP
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Catalog Number: LTRT-00060
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