ATMEL TS80C31X2, AT80C31X2 User Manual
1. Features
• 80C31 Compatible
• 8031 pin and instruction compatible
• Four 8-bit I/O ports
• Two 16-bit timer/counters
• 128 bytes scratchpad RAM
• High-Speed Architecture
• 40 MHz @ 5V, 30MHz @ 3V
• X2 Speed Improvement capability (6 clocks/machine cycle)
• 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)
• Dual Data Pointer
• Asynchronous port reset
• Interrupt Structure with
• 5 Interrupt sources,
• 4 priority level interrupt system
• Full duplex Enhanced UART
• Framing error detection
• Automatic address recognition
• Power Control modes
• Idle mode
• Power-down mode
• Power-off Flag
• Once mode (On-chip Emulation)
• Power supply: 4.5-5.5V, 2.7-5.5V
• Temperature ranges: Commercial (0 to 70
• Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)
o
C) and Industrial (-40 to 85oC)
8-bit CMOS
Microcontroller
ROMless
TS80C31X2
AT80C31X2
2. Description
TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS
single chip 8-bit microcontroller.
The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM,
a 5-source, 4 priority level interrupt system, an on-chip oscilator and two
timer/counters.
In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and a X2 speed improvement
mechanism.
The fully static design of the TS80C31X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C31X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
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3. Block Diagram
RxD
(1)(1)
TxD
ALE/
XTAL1
XTAL2
PROG
PSEN
EA
RD
WR
(1)
(1)
CPU
RESET
EUART
Timer 0
Timer 1
(1)(1) (1)(1)
T0
RAM
128x8
C51
CORE
INT
Ctrl
T1
INT0
(1): Alternate function of Port 3
IB-bus
Parallel I/O Ports & Ext. Bus
Port 0
INT1
P0
Port 1
P1
Port 2
P2
Port 3
P3
2
AT/TS80C31X2
4428D–8051–08/05
AT/TS80C31X2
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• Interrupt system registers: IE, IP, IPH
• Others: CKCON
Table 4-1. All SFRs with their address and their reset value
Bit
addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h FFh
F0h
E8h EFh
E0h
D8h DFh
D0h
C8h CFh
C0h
B
0000 0000
ACC
0000 0000
PSW
0000 0000
Non Bit addressable
F7h
E7h
D7h
C7h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
IP
XXX0 0000
P3
1111 1111
0XX0 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Reserved
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SADEN
0000 0000
IPH
XXX0 0000
IE
SADDR
0000 0000
SBUF
XXXX XXXX
TMOD
0000 0000
SP
0000 0111
AUXR1
XXXX XXX0
TL0
0000 0000
DPL
0000 0000
TL1
0000 0000
DPH
0000 0000
TH0
0000 0000
TH1
0000 0000
CKCON
XXXX XXX0
PCON
00X1 0000
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
3
5. Pin Configuration
P1.0 / T2
P1.1 / T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PDIL/
CDIL40
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
40
VCC
39
P0.0 / A0
38
P0.1 / A1
P0.2 / A2
37
P0.3 / A3
36
P0.4 / A4
35
P0.5 / A5
34
P0.6 / A6
33
P0.7 / A7
32
EA/VPP
31
ALE/PROG
1
2
3
4
5
6
7
8
9
10
11
30
29
28
27
26
25
24
23
22
21
P1.4
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
P1.0
P1.1
P1.3
P1.2
43 42 41 40 3944
PQFP44
VQFP44VQFP44
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
VSS1/NIC*
VCC
P0.0/AD0
P0.1/AD1
38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
P1.5
P1.6
P1.7
RST
NIC*
P0.2/AD2
7
8
9
10
11
12
13
14
15
16
17
P1.4
P1.3
5 4 3 2 1 6
P1.1
P1.2
PLCC44
P1.0
VSS1/NIC*
44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
NIC*
VSS
XTAL2
XTAL1
P3.7/RD
P3.6/WR
P0.3/AD3
P0.4/AD4
33
32
P0.5/AD5
31
P0.6/AD6
30
P0.7/AD7
29
EA
28
NIC*
27
ALE
26
PSEN
25
P2.7/A15
24
P2.6/A14
23
P2.5/A13
VCC
P2.0/A8
P0.0/AD0
P2.1/A9
P0.1/AD1
P2.2/A10
P0.2/AD2
P2.3/A11
P0.3/AD3
39
38
37
36
35
34
33
32
31
30
29
P2.4/A12
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
*NIC: No Internal Connection
4
AT/TS80C31X2
P3.7/RD
P3.6/WR
XTAL2
VSS
NIC*
XTAL1
P2.0/A8
P2.1/A9
P2.3/A11
P2.2/A10
P2.4/A12
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AT/TS80C31X2
Pin Number
Mnemonic
V
SS
Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
V
CC
P0.0-P0.7
P1.0-P1.7 1-8 2-9 40-44
P2.0-P2.7
P3.0-P3.7
Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running,
ALE 30 33 27 O (I) Address Latch Enable: Output pulse for latching the low byte of the address during
PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When
20 22 16 I Ground: 0V reference
40 44 38 I
39-
32
21-
28
10-
17
10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR
17 19 13 O RD
43-36 37-30 I/O
1-3
24-31 18-25 I/O
11,
13-19
5,
7-13
Type Name And FunctionDIL LCC VQFP 1.4
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. Port 0 pins must be
polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
(P3.2): External interrupt 0
(P3.6): External data memory write strobe
(P3.7): External data memory read strobe
resets the device. An internal diffused resistor to V
only an external capacitor to V
an access to external memory. In normal operation, ALE is emitted at a constant
rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory.
executing code from the external program memory, PSEN
machine cycle, except that two PSEN
external data memory. PSEN
memory.
CC.
activations are skipped during each access to
is not activated during fetches from internal program
permits a power-on reset using
SS
is activated twice each
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5
EA 31 35 29 I
External Access Enable: EA
fetch code from external program memory locations.
must be externally held low to enable the device to
XTAL1 19 21 15 I
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
6
AT/TS80C31X2
4428D–8051–08/05
6. TS80C31X2 Enhanced Features
In comparison to the original 80C31, the TS80C31X2 implements some new features, which
are
:
• The X2 option.
• The Dual Data Pointer.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• Enhanced UART
6.1 X2 Feature
The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2”
provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically operating frequency by 2 in operating and
idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by
software.
AT/TS80C31X2
6.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the
CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2
mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to
60%. Figure 6-1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode
switching waveforms.
Figure 6-1. Clock Generation Diagram
XTAL1
F
XTAL
2
XTAL1:2
0
1
X2
CKCON reg
state machine: 6 clock cycles.
CPU control
F
OSC
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7
Figure 6-2. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
CPU clock
The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per
instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD
mode). Setting this bit activates the X2 feature (X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that
all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
Table 6-1. CKCON Register
CKCON - Clock Control Register (8Fh)
7 6 5 4 3 2 1 0
- - - - - - - X2
X2 ModeSTD Mode STD Mode
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 X2
Bit
Mnemonic
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel-wm.com)
Description
OSC=FXTAL
OSC=FXTAL
).
/2).
8
AT/TS80C31X2
4428D–8051–08/05
7. Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a
number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer
to Figure 7-1).
Figure 7-1. Use of Dual Pointer
07
DPS
AUXR1(A2H)
DPH(83H) DPL(82H)
DPTR1
AT/TS80C31X2
External Data Memory
DPTR0
Table 7-1. AUXR1: Auxiliary Register 1
76543210
--3-----DPS
Bit
Number
7-
6-
5-
4-
3-
2-
1-
0DPS
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XXX0
Not bit addressable
4428D–8051–08/05
9
8. Application
Software can take advantage of the additional data pointers to both increase speed and reduce
code size, for example, block operations (copy, compare, search ...) are well served by using
one data pointer as a ’source’ pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000 MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6 JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.
However, note that the INC instruction does not directly force the DPS bit to a particular state,
but simply toggles it. In simple routines, such as the block move example, only the fact that DPS
is toggled in the proper sequence matters, not its actual value. In other words, the block move
routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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AT/TS80C31X2
4428D–8051–08/05
9. TS80C31X2 Serial I/O Port
The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
9.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).
Figure 9-1. Framing Error Block Diagram
RITIRB8TB8RENSM2SM1SM0/FE
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
AT/TS80C31X2
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
9-3.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-
2. and Figure 9-3.).
Figure 9-2. UART Timings in Mode 1
RXD
RI
SMOD0=X
FE
SMOD0=1
Start
bit
SM0 to UART mode control (SMOD = 0)
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
Data byte
PCON (87h)
D7D6D5D4D3D2D1D0
Stop
bit
4428D–8051–08/05
11
Figure 9-3. UART Timings in Modes 2 and 3
RXD
D8D7D6D5D4D3D2D1D0
Start
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
9.2 Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
Data byte Ninth
bit
Stop
bit
9.3 Given Address
12
AT/TS80C31X2
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2
bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR 0101 0110b
SADEN 1111 1100b
Given 0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A: SADDR 1111 0001b
SADEN 1111 1010b
Given 1111 0X0Xb
Slave B: SADDR 1111 0011b
SADEN 1111 1001b
Given 1111 0XX1b
4428D–8051–08/05
AT/TS80C31X2
Slave C: SADDR 1111 0010b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate
with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111
0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g. 1111 0001b).
9.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t-care bits, e.g.:
Broadcast =SADDR OR SADEN 1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most
applications, a broadcast address is FFh. The following is an example of using broadcast
addresses:
Slave A: SADDR 1111 0001b
SADEN 1111 1101b
Given 1111 00X1b
SADDR 0101 0110b
SADEN 1111 1100b
SADEN 1111 1010b
Broadcast 1111 1X11b,
Slave B: SADDR 1111 0011b
Slave C: SADDR= 1111 0010b
SADEN 1111 1001b
Broadcast 1111 1X11B,
SADEN 1111 1101b
Broadcast 1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not
slave C, the master can send and address FBh.
9.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
Table 9-1. SADEN - Slave Address Mask Register (B9h)
76543210
Reset Value = 0000 0000b
Not bit addressable
4428D–8051–08/05
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