1. Features
• 80C31 Compatible
• 8031 pin and instruction compatible
• Four 8-bit I/O ports
• Two 16-bit timer/counters
• 128 bytes scratchpad RAM
• High-Speed Architecture
• 40 MHz @ 5V, 30MHz @ 3V
• X2 Speed Improvement capability (6 clocks/machine cycle)
• 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)
• Dual Data Pointer
• Asynchronous port reset
• Interrupt Structure with
• 5 Interrupt sources,
• 4 priority level interrupt system
• Full duplex Enhanced UART
• Framing error detection
• Automatic address recognition
• Power Control modes
• Idle mode
• Power-down mode
• Power-off Flag
• Once mode (On-chip Emulation)
• Power supply: 4.5-5.5V, 2.7-5.5V
• Temperature ranges: Commercial (0 to 70
• Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)
o
C) and Industrial (-40 to 85oC)
8-bit CMOS
Microcontroller
ROMless
TS80C31X2
AT80C31X2
2. Description
TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS
single chip 8-bit microcontroller.
The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM,
a 5-source, 4 priority level interrupt system, an on-chip oscilator and two
timer/counters.
In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and a X2 speed improvement
mechanism.
The fully static design of the TS80C31X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C31X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
4428D–8051–08/05
3. Block Diagram
RxD
(1)(1)
TxD
ALE/
XTAL1
XTAL2
PROG
PSEN
EA
RD
WR
(1)
(1)
CPU
RESET
EUART
Timer 0
Timer 1
(1)(1) (1)(1)
T0
RAM
128x8
C51
CORE
INT
Ctrl
T1
INT0
(1): Alternate function of Port 3
IB-bus
Parallel I/O Ports & Ext. Bus
Port 0
INT1
P0
Port 1
P1
Port 2
P2
Port 3
P3
2
AT/TS80C31X2
4428D–8051–08/05
AT/TS80C31X2
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• Interrupt system registers: IE, IP, IPH
• Others: CKCON
Table 4-1. All SFRs with their address and their reset value
Bit
addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h FFh
F0h
E8h EFh
E0h
D8h DFh
D0h
C8h CFh
C0h
B
0000 0000
ACC
0000 0000
PSW
0000 0000
Non Bit addressable
F7h
E7h
D7h
C7h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
IP
XXX0 0000
P3
1111 1111
0XX0 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Reserved
4428D–8051–08/05
SADEN
0000 0000
IPH
XXX0 0000
IE
SADDR
0000 0000
SBUF
XXXX XXXX
TMOD
0000 0000
SP
0000 0111
AUXR1
XXXX XXX0
TL0
0000 0000
DPL
0000 0000
TL1
0000 0000
DPH
0000 0000
TH0
0000 0000
TH1
0000 0000
CKCON
XXXX XXX0
PCON
00X1 0000
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
3
5. Pin Configuration
P1.0 / T2
P1.1 / T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PDIL/
CDIL40
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
40
VCC
39
P0.0 / A0
38
P0.1 / A1
P0.2 / A2
37
P0.3 / A3
36
P0.4 / A4
35
P0.5 / A5
34
P0.6 / A6
33
P0.7 / A7
32
EA/VPP
31
ALE/PROG
1
2
3
4
5
6
7
8
9
10
11
30
29
28
27
26
25
24
23
22
21
P1.4
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
P1.0
P1.1
P1.3
P1.2
43 42 41 40 3944
PQFP44
VQFP44VQFP44
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
VSS1/NIC*
VCC
P0.0/AD0
P0.1/AD1
38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
P1.5
P1.6
P1.7
RST
NIC*
P0.2/AD2
7
8
9
10
11
12
13
14
15
16
17
P1.4
P1.3
5 4 3 2 1 6
P1.1
P1.2
PLCC44
P1.0
VSS1/NIC*
44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
NIC*
VSS
XTAL2
XTAL1
P3.7/RD
P3.6/WR
P0.3/AD3
P0.4/AD4
33
32
P0.5/AD5
31
P0.6/AD6
30
P0.7/AD7
29
EA
28
NIC*
27
ALE
26
PSEN
25
P2.7/A15
24
P2.6/A14
23
P2.5/A13
VCC
P2.0/A8
P0.0/AD0
P2.1/A9
P0.1/AD1
P2.2/A10
P0.2/AD2
P2.3/A11
P0.3/AD3
39
38
37
36
35
34
33
32
31
30
29
P2.4/A12
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
*NIC: No Internal Connection
4
AT/TS80C31X2
P3.7/RD
P3.6/WR
XTAL2
VSS
NIC*
XTAL1
P2.0/A8
P2.1/A9
P2.3/A11
P2.2/A10
P2.4/A12
4428D–8051–08/05
AT/TS80C31X2
Pin Number
Mnemonic
V
SS
Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
V
CC
P0.0-P0.7
P1.0-P1.7 1-8 2-9 40-44
P2.0-P2.7
P3.0-P3.7
Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running,
ALE 30 33 27 O (I) Address Latch Enable: Output pulse for latching the low byte of the address during
PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When
20 22 16 I Ground: 0V reference
40 44 38 I
39-
32
21-
28
10-
17
10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR
17 19 13 O RD
43-36 37-30 I/O
1-3
24-31 18-25 I/O
11,
13-19
5,
7-13
Type Name And FunctionDIL LCC VQFP 1.4
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. Port 0 pins must be
polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
(P3.2): External interrupt 0
(P3.6): External data memory write strobe
(P3.7): External data memory read strobe
resets the device. An internal diffused resistor to V
only an external capacitor to V
an access to external memory. In normal operation, ALE is emitted at a constant
rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory.
executing code from the external program memory, PSEN
machine cycle, except that two PSEN
external data memory. PSEN
memory.
CC.
activations are skipped during each access to
is not activated during fetches from internal program
permits a power-on reset using
SS
is activated twice each
4428D–8051–08/05
5
EA 31 35 29 I
External Access Enable: EA
fetch code from external program memory locations.
must be externally held low to enable the device to
XTAL1 19 21 15 I
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
6
AT/TS80C31X2
4428D–8051–08/05
6. TS80C31X2 Enhanced Features
In comparison to the original 80C31, the TS80C31X2 implements some new features, which
are
:
• The X2 option.
• The Dual Data Pointer.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• Enhanced UART
6.1 X2 Feature
The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2”
provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically operating frequency by 2 in operating and
idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by
software.
AT/TS80C31X2
6.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the
CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2
mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to
60%. Figure 6-1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode
switching waveforms.
Figure 6-1. Clock Generation Diagram
XTAL1
F
XTAL
2
XTAL1:2
0
1
X2
CKCON reg
state machine: 6 clock cycles.
CPU control
F
OSC
4428D–8051–08/05
7
Figure 6-2. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
CPU clock
The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per
instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD
mode). Setting this bit activates the X2 feature (X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that
all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
Table 6-1. CKCON Register
CKCON - Clock Control Register (8Fh)
7 6 5 4 3 2 1 0
- - - - - - - X2
X2 ModeSTD Mode STD Mode
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 X2
Bit
Mnemonic
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel-wm.com)
Description
OSC=FXTAL
OSC=FXTAL
).
/2).
8
AT/TS80C31X2
4428D–8051–08/05
7. Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a
number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer
to Figure 7-1).
Figure 7-1. Use of Dual Pointer
07
DPS
AUXR1(A2H)
DPH(83H) DPL(82H)
DPTR1
AT/TS80C31X2
External Data Memory
DPTR0
Table 7-1. AUXR1: Auxiliary Register 1
76543210
--3-----DPS
Bit
Number
7-
6-
5-
4-
3-
2-
1-
0DPS
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XXX0
Not bit addressable
4428D–8051–08/05
9
8. Application
Software can take advantage of the additional data pointers to both increase speed and reduce
code size, for example, block operations (copy, compare, search ...) are well served by using
one data pointer as a ’source’ pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000 MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6 JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.
However, note that the INC instruction does not directly force the DPS bit to a particular state,
but simply toggles it. In simple routines, such as the block move example, only the fact that DPS
is toggled in the proper sequence matters, not its actual value. In other words, the block move
routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
10
AT/TS80C31X2
4428D–8051–08/05
9. TS80C31X2 Serial I/O Port
The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
9.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).
Figure 9-1. Framing Error Block Diagram
RITIRB8TB8RENSM2SM1SM0/FE
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
AT/TS80C31X2
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
9-3.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-
2. and Figure 9-3.).
Figure 9-2. UART Timings in Mode 1
RXD
RI
SMOD0=X
FE
SMOD0=1
Start
bit
SM0 to UART mode control (SMOD = 0)
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
Data byte
PCON (87h)
D7D6D5D4D3D2D1D0
Stop
bit
4428D–8051–08/05
11
Figure 9-3. UART Timings in Modes 2 and 3
RXD
D8D7D6D5D4D3D2D1D0
Start
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
9.2 Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
Data byte Ninth
bit
Stop
bit
9.3 Given Address
12
AT/TS80C31X2
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2
bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR 0101 0110b
SADEN 1111 1100b
Given 0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A: SADDR 1111 0001b
SADEN 1111 1010b
Given 1111 0X0Xb
Slave B: SADDR 1111 0011b
SADEN 1111 1001b
Given 1111 0XX1b
4428D–8051–08/05
AT/TS80C31X2
Slave C: SADDR 1111 0010b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate
with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111
0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g. 1111 0001b).
9.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t-care bits, e.g.:
Broadcast =SADDR OR SADEN 1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most
applications, a broadcast address is FFh. The following is an example of using broadcast
addresses:
Slave A: SADDR 1111 0001b
SADEN 1111 1101b
Given 1111 00X1b
SADDR 0101 0110b
SADEN 1111 1100b
SADEN 1111 1010b
Broadcast 1111 1X11b,
Slave B: SADDR 1111 0011b
Slave C: SADDR= 1111 0010b
SADEN 1111 1001b
Broadcast 1111 1X11B,
SADEN 1111 1101b
Broadcast 1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not
slave C, the master can send and address FBh.
9.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
Table 9-1. SADEN - Slave Address Mask Register (B9h)
76543210
Reset Value = 0000 0000b
Not bit addressable
4428D–8051–08/05
13
Table 9-2. SADDR - Slave Address Register (A9h)
76543210
Reset Value = 0000 0000b
Not bit addressable
14
AT/TS80C31X2
4428D–8051–08/05
AT/TS80C31X2
Table 9-3. SCON Register -- SCON - Serial Control Register (98h)
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number
7FE
6SM1
5SM2
4REN
3TB8
Bit
Mnemonic Description
SM0
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM0
0 0 0 Shift Register F
01 1 8-bit UART Variable
10 2 9-bit UART F
11 3 9-bit UART Variable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be
cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
SM1 Mode Description Baud Rate
/12 (/6 in X2 mode)
XTAL
/64 or F
XTAL
/32 (/32, /16 in X2 mode)
XTAL
2RB8
1TI
0RI
Reset Value = 0000 0000b
Bit addressable
4428D–8051–08/05
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in the other modes.
15
Table 9-4. PCON Register -- PCON - Power Control Register (87h)
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
16
AT/TS80C31X2
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect
the value of this bit.
4428D–8051–08/05
10. Interrupt System
The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two
timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Figure 10-1.
Figure 10-1. Interrupt Control System
AT/TS80C31X2
INT0
TF0
INT1
TF1
RI
IPH, IP
IE0
IE1
TI
3
0
3
0
3
0
3
0
3
0
High priority
interrupt
Interrupt
polling
sequence, decreasing
from high to low priority
Low priority
Individual Enable
Global Disable
interrupt
4428D–8051–08/05
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (See Table 10-2.Table 10-3.). This register also contains a global
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Priority High register (See Table 10-4.). shows the bit values and priority levels associated with
each combination.
Table 10-1. Priority Level Bit Values
IPH.x IP.x Interrupt Level Priority
0 0 0 (Lowest)
011
102
1 1 3 (Highest)
17
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
Table 10-2. IE Register -- IE - Interrupt Enable Register (A8h)
76543210
EA - - ES ET1 EX1 ET0 EX0
Bit
Number
7EA
6-
5-
4ES
3ET1
2 EX1
1ET0
Bit
Mnemonic Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its
own interrupt enable bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
18
0 EX0
Reset Value = 0XX0 0000b
Bit addressable
AT/TS80C31X2
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
4428D–8051–08/05
AT/TS80C31X2
Table 10-3. IP Register -- IP - Interrupt Priority Register (B8h)
7 6 5 4 3 2 1 0
- - - PS PT1 PX1 PT0 PX0
Bit
Number
7 -
6 -
5 -
4 PS
3 PT1
2 PX1
1 PT0
0 PX0
Bit
Mnemonic
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority bit
Refer to PSH for priority level.
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
External interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = XXX0 0000b
Bit addressable
Description
4428D–8051–08/05
19
Table 10-4. IPH Register -- IPH - Interrupt Priority High Register (B7h)
7 6 5 4 3 2 1 0
- - - PSH PT1H PX1H PT0H PX0H
Bit
Number
7 -
6 -
5 -
4 PSH
3 PT1H
2 PX1H
1 PT0H
0 PX0H
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority High bit
PSH
Timer 1 overflow interrupt Priority High bit
PT1H
External interrupt 1 Priority High bit
PX1H
Timer 0 overflow interrupt Priority High bit
PT0H
External interrupt 0 Priority High bit
PX0H
PS Priority Level
0 0 Lowest
01
10
1 1 Highest
PT1 Priority Level
0 0 Lowest
01
10
1 1 Highest
PX1 Priority Level
0 0 Lowest
01
10
1 1 Highest
PT0 Priority Level
0 0 Lowest
01
10
1 1 Highest
PX0 Priority Level
0 0 Lowest
01
10
1 1 Highest
20
Reset Value = XXX0 0000b
Not bit addressable
AT/TS80C31X2
4428D–8051–08/05
11. Idle mode
AT/TS80C31X2
An instruction that sets PCON.0 causes that to be the last instruction executed before going into
the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the
interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack
Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain
their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0
to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the
device into idle.
The flag bits GF0 and GF1 can be used to give and indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one
or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
The over way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is
still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
11.1 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4.,
PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down
mode is the last instruction executed. The internal RAM and SFRs retain their value until the
power-down mode is terminated. V
reset or an external interrupt can cause an exit from power-down. To properly terminate powerdown, the reset or external interrupt should not be executed before V
operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0
must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed
in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the
two inputs is held low and power down exit will be completed when the first input will be
released. In this case the higher priority interrupt service routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C31X2 into power-down mode.
can be lowered to save further power. Either a hardware
CC
is restored to its normal
CC
and INT1 are useful to exit from power-down. For that, interrupt
4428D–8051–08/05
21
Figure 11-1. Power-Down Exit Waveform
INT0
INT1
XTAL1
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM
content.
Note: NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is
unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is
not entered.
Table 11 - 1. The state of ports during idle and power-down modes
Program
Mode
Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Power-down phase Oscillator restart phase Active phaseActive phase
Idle External 1 1 Floating Port Data Address Port Data
Power Down External 0 0 Floating Port Data Port Data Port Data
22
AT/TS80C31X2
4428D–8051–08/05
12. ONCETM Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the
TS80C31X2; the following sequence must be exercised:
AT/TS80C31X2
• Pull ALE low while the device is in reset (RST high) and PSEN
• Hold ALE low as RST is deactivated.
While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 12-1. External Pin Status during ONCE Mode
ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2
Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active
is high.
4428D–8051–08/05
23
13. Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
switch-on. A warm start reset occurs while VCC is still
CC
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 13-1.). POF is set by hardware
when V
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
CC
ing the user to determine the type of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading
POF bit will return indeterminate value.
Table 13-1. PCON Register -- PCON - Power Control Register (87h)
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
7SMOD1
6SMOD0
5-
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
4POF
3GF1
2GF0
1PD
0IDL
Clear to recognize next reset type.
Set by hardware when V
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
rises from 0 to its nominal voltage. Can also be set by software.
CC
24
AT/TS80C31X2
4428D–8051–08/05
14. Electrical Characteristics
AT/TS80C31X2
14.1 Absolute Maximum Ratings
(1)
Ambiant Temperature Under Bias:
C = commercial0°C to 70°C
I = industrial -40°C to 85°C
Storage Temperature-65°C to + 150°C
Voltage on V
Voltage on V
Voltage on Any Pin to V
Power Dissipation1 W
Note: 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent
2. This value is based on the maximum allowable die temperature and the thermal resistance of
to VSS-0.5 V to + 7 V
CC
to VSS-0.5 V to + 13 V
PP
SS
(2)
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device
reliability.
the package.
14.2 Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In
Atmel Wireless & Microcontrollers new devices, the CPU is no more active during reset, so the
power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, Atmel Wireless &
Microcontrollers presents a new way to measure the operating Icc:
-0.5 V to VCC + 0.5 V
Using an internal test ROM, the following code is executed:
Label: SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock.
This is much more representative of the real operating Icc.
4428D–8051–08/05
25
14.3 DC Parameters for Standard Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
T
A = -40°C to +85°C; V
Table 14-1. DC Parameters in Standard Voltage
Symbol Parameter Min Typ Max Unit Test Conditions
= 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
SS
V
IL
V
IH
V
IH1
V
OL
V
OL1
V
OL2
V
OH
V
OH1
V
OH2
R
RST
I
IL
I
LI
I
TL
C
IO
I
PD
I
CC
under
RESET
Input Low Voltage -0.5 0.2 VCC - 0.1 V
Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V
Input High Voltage, XTAL1, RST 0.7 V
Output Low Voltage, ports 1, 2, 3
Output Low Voltage, port 0
(6)
(6)
CC
Output Low Voltage, ALE, PSEN
V
- 0.3
Output High Voltage, ports 1, 2, 3
Output High Voltage, port 0
CC
- 0.7
V
CC
- 1.5
V
CC
V
- 0.3
CC
- 0.7
V
CC
- 1.5
V
CC
VCC - 0.3
Output High Voltage,ALE, PSEN
- 0.7
V
CC
- 1.5
V
CC
RST Pulldown Resistor 50 90
(5)
VCC + 0.5 V
0.3
0.45
1.0
0.3
0.45
1.0
0.3
0.45
1.0
200 kΩ
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 100 μA
I
OL
IOL = 1.6 mA
IOL = 3.5 mA
= 200 μA
I
OL
IOL = 3.2 mA
IOL = 7.0 mA
= 100 μA
I
OL
IOL = 1.6 mA
IOL = 3.5 mA
I
OH
I
OH
I
OH
= 5 V ± 10%
V
CC
= -200 μA
I
OH
= -3.2 mA
I
OH
= -7.0 mA
I
OH
= 5 V ± 10%
V
CC
= -100 μA
I
OH
= -1.6 mA
I
OH
= -3.5 mA
I
OH
= 5 V ± 10%
V
CC
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
= -10 μA
= -30 μA
= -60 μA
Logical 0 Input Current ports 1, 2 and 3 -50 μA Vin = 0.45 V
Input Leakage Current ±10 μA 0.45 V < Vin < V
CC
Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 μAVin = 2.0 V
Capacitance of I/O Buffer 10 pF
Power Down Current 20
(5)
50 μA2.0 V < V
Fc = 1 MHz
T
A = 25°C
5.5 V
CC <
(3)
1 + 0.4 Freq
Power Supply Current Maximum values, X1
(7)
mode:
(MHz)
@12MHz 5.8
@16MHz 7.4
mA
V
CC
= 5.5 V
(1)
operating
26
I
CC
Power Supply Current Maximum values, X1
(7)
mode:
AT/TS80C31X2
3 + 0.6 Freq
(MHz)
@12MHz 10.2
@16MHz 12.6
mA V
(8)
= 5.5 V
CC
4428D–8051–08/05
AT/TS80C31X2
Symbol Parameter Min Typ Max Unit Test Conditions
0.25+0.3 Freq
I
CC
idle
Power Supply Current Maximum values, X1
(7)
mode:
14.4 DC Parameters for Low Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
T
A = -40°C to +85°C; V
Table 14-2. DC Parameters for Low Voltage
Symbol Parameter Min Typ Max Unit Test Conditions
= 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
SS
(MHz)
@12MHz 3.9
@16MHz 5.1
mA
V
CC
= 5.5 V
(2)
V
V
V
IH1
V
OL
V
OL1
V
OH
V
OH1
I
IL
I
LI
I
TL
R
RST
Input Low Voltage -0.5 0.2 VCC - 0.1 V
IL
Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V
IH
Input High Voltage, XTAL1, RST 0.7 V
Output Low Voltage, ports 1, 2, 3
Output Low Voltage, port 0, ALE, PSEN
(6)
(6)
Output High Voltage, ports 1, 2, 3 0.9 V
Output High Voltage, port 0, ALE, PSEN 0.9 V
CC
CC
CC
VCC + 0.5 V
0.45 V IOL = 0.8 mA
0.45 V IOL = 1.6 mA
Logical 0 Input Current ports 1, 2 and 3 -50 μA Vin = 0.45 V
Input Leakage Current ±10 μA 0.45 V < Vin < V
Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 μA Vin = 2.0 V
RST Pulldown Resistor 50 90
(5)
200 kΩ
CIO Capacitance of I/O Buffer 10 pF
(5)
I
PD
I
CC
under
RESET
Power Down Current
Power Supply Current Maximum values, X1
(7)
mode:
20
10
(5)
50
30
1 + 0.2 Freq
(MHz)
@12MHz 3.4
@16MHz 4.2
VI
VI
= -10 μA
OH
= -40 μA
OH
Fc = 1 MHz
T
A = 25°C
μA
mA
VCC = 2.0 V to 5.5 V
VCC = 2.0 V to 3.3 V
= 3.3 V
V
CC
(4)
(4)
CC
(3)
(3)
(1)
I
CC
operating
I
CC
idle
4428D–8051–08/05
Power Supply Current Maximum values, X1
(7)
mode:
Power Supply Current Maximum values, X1
(7)
mode:
Note: 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with T
= 5 ns (see Figure 14-5.), VIL = VSS + 0.5 V,
1 + 0.3 Freq
(MHz)
@12MHz 4.6
@16MHz 5.8
0.15 Freq
(MHz) + 0.2
@12MHz 2
@16MHz 2.6
mA
mA V
V
CC
CC
= 3.3 V
= 3.3 V
CLCH
(8)
(2)
, T
CHCL
27
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal
oscillator used..
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with T
VIL = VSS + 0.5 V, VIH = V
- 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 14-
CC
CLCH
, T
CHCL
= 5 ns,
3.).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC;
XTAL2 NC.; RST = VSS (see Figure 14-4.).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed
on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus
operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may
exceed 0.45V with maxi V
peak 0.6V. A Schmitt Trigger use is not necessary.
OL
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature and 5V.
6. Under steady state (non-transient) conditions, I
must be externally limited as follows:
OL
Maximum IOL per port pin: 10 mA
Maximum I
per 8-bit port:
OL
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
for all output pins: 71 mA
OL
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating I
is measured with all output pins disconnected; XTAL1 driven with T
CC
CLCH
, T
CHCL
=
5 ns (see Figure 14-5.), VIL = VSS + 0.5 V,
= VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code
V
IH
80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
V
I
CC
V
CC
P0
EA
(NC)
CLOCK
SIGNAL
V
CC
RST
XTAL2
XTAL1
V
SS
Figure 14-1. ICC Test Condition, under reset
CC
V
CC
All other pins are disconnected.
28
AT/TS80C31X2
4428D–8051–08/05
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
AT/TS80C31X2
V
CC
I
CC
V
CC
V
CC
P0
EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
V
SS
Figure 14-2. Operating ICC Test Condition
I
CC
V
CC
Reset = Vss after a high pulse
during at least 24 clock cycles
Figure 14-3. I
RST
(NC)
CLOCK
SIGNAL
Test Condition, Idle Mode
CC
XTAL2
XTAL1
V
P0
EA
SS
All other pins are disconnected.
V
CC
V
CC
All other pins are disconnected.
4428D–8051–08/05
Reset = Vss after a high pulse
during at least 24 clock cycles
Figure 14-4. I
CC
V
CC
I
CC
V
CC
V
CC
P0
RST
EA
(NC)
XTAL2
XTAL1
V
SS
Test Condition, Power-Down Mode
All other pins are disconnected.
29
VCC-0.5V
Figure 14-5. Clock Signal Waveform for ICC Tests in Active and Idle Modes
14.5 AC Parameters
14.5.1 Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The
other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.
0.45V
T
CHCL
T
CLCH
= T
CHCL
T
CLCH
= 5ns.
0.7V
CC
0.2VCC-0.1
Example:T
T
LLPL
T
A = 0 to +70°C (commercial temperature range); V
T
A = -40°C to +85°C (industrial temperature range); V
= Time for Address Valid to ALE Low.
AVLL
= Time for ALE Low to PSEN Low.
= 0 V; VCC = 5 V ± 10%; -M and -V ranges.
SS
= 0 V; VCC = 5 V ± 10%; -M and -V
SS
ranges.
T
A = 0 to +70°C (commercial temperature range); V
T
A = -40°C to +85°C (industrial temperature range); V
= 0 V; 2.7 V < V
SS
= 0 V; 2.7 V < V
SS
5.5 V; -L range.
CC <
5.5 V; -L range.
CC <
Table 14-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE
and PSEN
signals. Timings will be guaranteed if these capacitances are respected. Higher
capacitance values can be used, but timings will then be degraded.
Table 14-3. Load Capacitance versus speed range, in pF
-M -V -L
Port 0 100 50 100
Port 1, 2, 3 80 50 80
ALE / PSEN 100 30 100
Table 8-5., Table 8-8. and Table 8-11. give the description of each AC symbols.
Table 14-6., Table 14-9. and Table 14-12. give for each range the AC parameter.
30
AT/TS80C31X2
4428D–8051–08/05
Table 14-7., Table 14-10. and Table 14-13. give the frequency derating formula of the AC
parameter. To calculate each AC symbols, take the x value corresponding to the speed grade
you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be
limited to the corresponding speed grade:
Table 14-4. Max frequency for derating formula regarding the speed grade
-M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode
Freq (MHz) 40 20 40 30 30 20
T (ns) 25 50 25 33.3 33.3 50
Example:
T
in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns):
LLIV
x= 25 (Table 14-7.)
T= 50ns
T
= 2T - x = 2 x 50 - 25 = 75ns
LLIV
Table 14-5. External Program Memory Characteristics
Symbol Parameter
AT/TS80C31X2
T Oscillator clock period
T
T
T
T
T
T
T
T
T
T
T
T
LHLL
AVL L
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
PXAV
AVI V
PLAZ
ALE pulse width
Address Valid to ALE
Address Hold After ALE
ALE to Valid Instruction In
ALE to PSEN
PSEN Pulse Width
PSEN to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction FloatAfter PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
4428D–8051–08/05
31
Table 14-6. AC Parameters for Fix Clock
Speed
-M
40 MHz
-V
X2 mode
30 MHz
60 MHz equiv.
-V
standard mode 40
MHz
-L
X2 mode
20 MHz
40 MHz equiv.
-L
standard mode
30 MHz
Units
Symbol Min Max Min Max Min Max Min Max Min Max
T2533255033 ns
T
T
T
T
T
T
T
T
T
T
T
LHLL
AVL L
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVI V
PLAZ
40 25 42 35 52 ns
10412513 ns
10412513 ns
70 45 78 65 98 ns
15 9 171018 ns
55 35 60 50 75 ns
35 25 50 30 55 ns
00000 ns
18 12 20 10 18 ns
85 53 95 80 122 ns
10 10 10 10 10 ns
Table 14-7. AC Parameters for a Variable Clock: derating formula
Symbol Type
T
T
T
T
T
T
T
T
T
T
T
LHLL
AVL L
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVI V
PLAZ
Min2 T - xT - x10815 ns
Min T - x 0.5 T - x 15 13 20 ns
Min T - x 0.5 T - x 15 13 20 ns
Max 4 T - x 2 T - x 30 22 35 ns
Min T - x 0.5 T - x 10 8 15 ns
Min 3 T - x 1.5 T - x 20 15 25 ns
Max 3 T - x 1.5 T - x 40 25 45 ns
Minxx000 ns
Max T - x 0.5 T - x 7 5 15 ns
Max 5 T - x 2.5 T - x 40 30 45 ns
Maxx x 101010 ns
Standard
Clock X2 Clock -M -V -L Units
32
AT/TS80C31X2
4428D–8051–08/05
14.5.2 External Program Memory Read Cycle
T
LHLL
ALE
PSEN
T
LLAX
T
AVL L
PORT 0
T
AVI V
PORT 2
ADDRESS
OR SFR-P2
Figure 14-6. External Program Memory Read Cycle
Table 14-8. External Data Memory Characteristics
T
LLIV
T
LLPL
T
PLIV
TPLAZ
T
PLPH
AT/TS80C31X2
12 T
CLCL
T
PXAV
T
T
PXIX
PXIZ
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS A8-A15ADDRESS A8-A15
Symbol Parameter
T
RLRH
T
WLWH
T
T
RHDX
T
RHDZ
T
T
AVD V
T
T
AVW L
T
QVWX
T
QVWH
T
WHQX
T
T
WHLH
RLDV
LLDV
LLWL
RLAZ
RD Pulse Width
WR Pulse Width
RD to Valid Data In
Data Hold After RD
Data Float After RD
ALE to Valid Data In
Address to Valid Data In
ALE to WR or RD
Address to WR or RD
Data Valid to WR Transition
Data set-up to WR High
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE high
4428D–8051–08/05
33
Table 14-9. AC Parameters for a Fix Clock
Speed -M
40 MHz
-V
X2 mode
30 MHz
60 MHz equiv.
-V
standard mode 40
MHz
-L
X2 mode
20 MHz
40 MHz equiv.
-L
standard mode
30 MHz Units
Symbol Min Max Min Max Min Max Min Max Min Max
T
RLRH
T
WLWH
T
T
RHDX
T
RHDZ
T
T
AVD V
T
T
AVW L
T
QVWX
T
QVWH
T
WHQX
T
T
WHLH
RLDV
LLDV
LLWL
RLAZ
130 85 135 125 175 ns
130 85 135 125 175 ns
100 60 102 95 137 ns
00000 ns
30 18 35 25 42 ns
160 98 165 155 222 ns
165 100 175 160 235 ns
50 100 30 70 55 95 45 105 70 130 ns
75 47 80 70 103 ns
10715513 ns
160 107 165 155 213 ns
15 9 171018 ns
00000ns
10 40 7 27 15 35 5 45 13 53 ns
34
AT/TS80C31X2
4428D–8051–08/05
Table 14-10. AC Parameters for a Variable Clock: derating formula
Symbol Type
AT/TS80C31X2
Standard
Clock X2 Clock -M -V -L Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVD V
LLWL
LLWL
AVW L
QVWX
QVWH
WHQX
RLAZ
WHLH
WHLH
Min 6 T - x 3 T - x 20 15 25 ns
Min 6 T - x 3 T - x 20 15 25 ns
Max 5 T - x 2.5 T - x 25 23 30 ns
Minxx000 ns
Max2 T - xT - x201525 ns
Max 8 T - x 4T -x 40 35 45 ns
Max 9 T - x 4.5 T - x 60 50 65 ns
Min 3 T - x 1.5 T - x 25 20 30 ns
Max 3 T + x 1.5 T + x 25 20 30 ns
Min 4 T - x 2 T - x 25 20 30 ns
Min T - x 0.5 T - x 15 10 20 ns
Min 7 T - x 3.5 T - x 15 10 20 ns
Min T - x 0.5 T - x 10 8 15 ns
Maxx x000 ns
Min T - x 0.5 T - x 15 10 20 ns
Max T + x 0.5 T + x 15 10 20 ns
14.5.3 External Data Memory Write Cycle
ALE
PSEN
WR
PORT 0
PORT 2
ADDRESS
OR SFR-P2
Figure 14-7. External Data Memory Write Cycle
T
LLAX
T
LLWL
T
QVWX
T
T
QVWH
WLWH
A0-A7 DATA OUT
T
AVW L
ADDRESS A8-A15 OR SFR P2
T
WHLH
T
WHQX
4428D–8051–08/05
35
14.5.4 External Data Memory Read Cycle
ALE
T
LLDV
T
WHLH
T
T
T
T
T
XLXL
QVHX
XHQX
XHDX
XHDV
PSEN
RD
PORT 0
PORT 2
T
LLAX
T
LLWL
T
AVD V
T
RLDV
T
RLRH
A0-A7 DATA IN
T
RLAZ
ADDRESS A8-A15 OR SFR P2
ADDRESS
OR SFR-P2
T
AVW L
Figure 14-8. External Data Memory Read Cycle
Table 14-11. Serial Port Timing - Shift Register Mode
Symbol Parameter
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
T
RHDX
T
RHDZ
Table 14-12. AC Parameters for a Fix Clock
Speed
-M
40 MHz
-V
X2 mode
30 MHz
60 MHz equiv.
standard mode 40
-V
MHz
Symbol Min Max Min Max Min Max Min Max Min Max
300 200 300 300 400 ns
200 117 200 200 283 ns
30 13 30 30 47 ns
00000 ns
117 34 117 117 200 ns
36
T
XLXL
T
QVHX
T
XHQX
T
XHDX
T
XHDV
AT/TS80C31X2
-L
X2 mode
20 MHz
40 MHz equiv.
-L
standard mode
30 MHz Units
4428D–8051–08/05
Table 14-13. AC Parameters for a Variable Clock: derating formula
Symbol Type
AT/TS80C31X2
Standard
Clock X2 Clock -M -V -L Units
T
T
T
T
T
XLXL
QVHX
XHQX
XHDX
XHDV
Min 12 T 6 T ns
Min 10 T - x 5 T - x 50 50 50 ns
Min2 T - xT - x202020 ns
Minxx000 ns
Max 10 T - x 5 T- x 133 133 133 ns
14.5.5 Shift Register Timing Waveforms
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE to SBUF
INPUT DATA
CLEAR RI
0123456 87
T
XLXL
T
QVXH
01234567
T
XHDV
T
XHQX
T
XHDX
VA L I DVAL I D
VA L I DVA L I D
VA L I D VA L I D VA L I D VA L I D
SET TI
SET RI
Figure 14-9. Shift Register Timing Waveforms
Table 14-14. External Clock Drive Characteristics (XTAL1)
Symbol Parameter Min Max Units
T
CLCL
T
CHCX
T
CLCX
T
CLCH
T
CHCL
T
CHCX/TCLCX
Oscillator Period 25 ns
High Time 5 ns
Low Time 5 ns
Rise Time 5 ns
Fall Time 5 ns
Cyclic ratio in X2 mode 40 60 %
4428D–8051–08/05
37
14.5.6 External Clock Drive Waveforms
VCC-0.5 V
0.45
V
Figure 14-10. External Clock Drive Waveforms
14.5.7 AC Testing Input/Output Waveforms
-0.5 V
V
CC
INPUT/OUTPUT
0.45 V
Figure 14-11. AC Testing Input/Output Waveforms
AC inputs during testing are driven at V
measurement are made at V
0.7V
CC
0.2VCC-0.1 V
T
CHCL
min for a logic “1” and VIL max for a logic “0”.
IH
0.2V
0.2V
T
CHCX
T
CLCL
T
CLCH
T
CLCX
+0.9
CC
-0.1
CC
- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing
CC
14.5.8 Float Waveforms
Figure 14-12. Float Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded V
≥ ± 20mA.
14.5.9 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by
two.
-0.1 V
V
OH
VOL+0.1 V
FLOAT
V
LOAD
V
V
LOAD
LOAD
+0.1 V
-0.1 V
level occurs. IOL/I
OH/VOL
OH
38
AT/TS80C31X2
4428D–8051–08/05
Figure 14-13. Clock Waveforms
AT/TS80C31X2
INTERNAL
CLOCK
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
P2 (EXT)
READ CYCLE
RD
P0
P2
WRITE CYCLE
WR
P0
STATE4 STATE5
P1P2 P1P2
DATA
SAMPLE
FLOAT FLOAT
PCL OUT
INDICATES ADDRESS
DPL OR Rt
DPL OR Rt
STATE6
P1P2
INDICATES DPH OR P2 SFR TO PCH
STATE1 STATE2 STATE3 STATE4
P1P2 P1P2 P1P2
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
DATA
SAMPLE
PCL OUT
SAMPLE
FLOAT
FLOAT
STATE5
P1P2 P1P2
DATA
PCL OUT (EVEN IF
MEMORY IS INTERNAL)
PCL OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P2
PORT OPERATION
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1, P2,
(INCLUDES INT0, INT1, TO, T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on
variables such as temperature and pin loading. Propagation also varies from output to output
and component. Typically though (T
approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated
in the AC specifications.
DATA OUT
INDICATES DPH OR P2 SFR TO PCH
OLD DATA
P1, P2, P3 PINS
RXD SAMPLED RXD SAMPLED
NEW DATA
P1, P2, P3 PINS
=25°C fully loaded) RD and WR propagation delays are
A
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0 PINS SAMPLED
4428D–8051–08/05
39
15. Ordering Information
Part Number
(3)
Memory Size Supply Voltage
TS80C31X2-MCA ROMLess 5V ±
TS80C31X2-MCB ROMLess 5V ±
TS80C31X2-MCC ROMLess 5V ±
TS80C31X2-MCE ROMLess 5V ±
10% Commercial 40 MHz
10% Commercial 40 MHz
10% Commercial 40 MHz
10% Commercial 40 MHz
Temperature
Range Max Frequency Package Packing
TS80C31X2-LCA ROMLess 2.7 to 5.5V Commercial 30 MHz
TS80C31X2-LCB ROMLess 2.7 to 5.5V Commercial 30 MHz
TS80C31X2-LCC ROMLess 2.7 to 5.5V Commercial 30 MHz
TS80C31X2-LCE ROMLess 2.7 to 5.5V Commercial 30 MHz
TS80C31X2-VCA ROMLess 5V ±
TS80C31X2-VCB ROMLess 5V ±
TS80C31X2-VCC ROMLess 5V ±
TS80C31X2-VCE ROMLess 5V ±
TS80C31X2-MIA ROMLess 5V ±
TS80C31X2-MIB ROMLess 5V ±
TS80C31X2-MIC ROMLess 5V ±
TS80C31X2-MIE ROMLess 5V ±
10% Commercial 60 MHz
10% Commercial 60 MHz
10% Commercial 60 MHz
10% Commercial 60 MHz
10% Industrial 40 MHz
10% Industrial 40 MHz
10% Industrial 40 MHz
10% Industrial 40 MHz
TS80C31X2-LIA ROMLess 2.7 to 5.5V Industrial 30 MHz
TS80C31X2-LIB ROMLess 2.7 to 5.5V Industrial 30 MHz
TS80C31X2-LIC ROMLess 2.7 to 5.5V Industrial 30 MHz
TS80C31X2-LIE ROMLess 2.7 to 5.5V Industrial 30 MHz
TS80C31X2-VIA ROMLess 5V ±
TS80C31X2-VIB ROMLess 5V ±
TS80C31X2-VIC ROMLess 5V ±
TS80C31X2-VIE ROMLess 5V ±
10% Industrial 60 MHz
10% Industrial 60 MHz
10% Industrial 60 MHz
10% Industrial 60 MHz
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(3)
PDIL40 Stick
PLCC44 Stick
PQFP44 Tray
VQFP44 Tray
PDIL40 Stick
PLCC44 Stick
PQFP44 Tray
VQFP44 Tray
PDIL40 Stick
PLCC44 Stick
PQFP44 Tray
VQFP44 Tray
PDIL40 Stick
PLCC44 Stick
PQFP44 Tray
VQFP44 Tray
PDIL40 Stick
PLCC44 Stick
PQFP44 Tray
VQFP44 Tray
PDIL40 Stick
PLCC44 Stick
PQFP44 Tray
VQFP44 Tray
AT80C31X2-3CSUM ROMLess 5V ±10% Industrial & Green 40 MHz
AT80C31X2-SLSUM ROMLess 5V ±10% Industrial & Green 40 MHz
AT80C31X2-RLTUM ROMLess 5V ±10% Industrial & Green 40 MHz
AT80C31X2-3CSUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz
AT80C31X2-SLSUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz
AT80C31X2-RLTUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz
40
AT/TS80C31X2
(1)
(1)
(1)
(1)
(1)
(1)
PDIL40 Stick
PLCC44 Stick
VQFP44 Tray
PDIL40 Stick
PLCC44 Stick
VQFP44 Tray
4428D–8051–08/05
AT/TS80C31X2
Part Number
AT80C31X2-3CSUV ROMLess 5V ±10% Industrial & Green 60 MHz
AT80C31X2-SLSUV ROMLess 5V ±10% Industrial & Green 60 MHz
AT80C31X2-RLTUV ROMLess 5V ±10% Industrial & Green 60 MHz
(3)
Memory Size Supply Voltage
Temperature
Range Max Frequency Package Packing
Notes: 1. 20 MHz in X2 Mode.
2. Tape and Reel available for SL, PQFP and RL packages.
3. 30 MHz in X2 Mode.
(3)
(3)
(3)
PDIL40 Stick
PLCC44 Stick
VQFP44 Tray
4428D–8051–08/05
41
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