ATMEL TS68040 User Manual

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Features

• 26-42 MIPS Integer Performance

• 3.5-5.6 MFLOPS Floating-Point-Performance

• IEEE 754-Compatible FPU

• Independent Instruction and Data MMUs

• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed

Simultaneously

• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors

• Multimaster/Multiprocessor Support via Bus Snooping

• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize

Throughput

• 4G bytes Direct Addressing Range

• Software Support Including Optimizing C Compiler and UNIX

• IEEE P 1149-1 Test Mode (JTAG)

• f = 25 MHz, 33 MHz; V

• The Use of the TS88915T Clock Driver is Suggested

=5V±5%;PD=7W

System V Port

Description

ThirdGeneration 32-bit Microprocessor

The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device. On a single chip, the TS68040 integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit (FPU), and fully independent instruction and data demand-paged memory management units (MMUs), including 4K bytes independent instruction and data caches. A high degree of instruction execution parallelism is achieved through the use of multiple independent execution pipelines, multiple internal buses, and a full internal Harvard architecture, including separate physical caches for both instruction and data accesses. The TS68040 also directly supports cache coherency in multimaster applications with dedicated on-chip bus snooping logic.

The TS68040 is user-object-code compatible with previous members of the TS68000 Family and is specifically optimized to reduce the execution time of compiler-generated code. The 68040 HCMOS technology, provides an ideal balance between speed, power, and physical device size.

Figure 1 is a simplified block diagram of the TS68040. Instruction execution is pipelined in both the integer unit and FPU. Independent data and instruction MMUs control the main caches and the address translation caches (ATCs). The ATCs speed up logical-to-physical address translations by storing recently used translations. The bus snooper circuit ensures cache coherency in multimaster and multiprocessing applications.

Screening

TS68040

• MIL-STD-883

• DESC. Drawing 5962-93143

• Atmel Standards

Rev. 2116A–HIREL–09/0 2

Figure 1. Block Diagram

R suffix

PGA 179

Ceramic Pin Grid Array

Cavity Down

F suffix

CQFP 196

Gullwing Shape Lead

Ceramic Quad Fla Pack

INSTRUCTION DATA BUS

CONVERT

EXECUTE

WRITE

BACK

FLOATING-

POINT

UNIT

INSTRUCTION

FETCH

DECODE

EFFECTIVE

ADDRESS

CALCULATE

EFFECTIVE

ADDRESS

FETCH

EXECUTE

WRITE

BACK

INTEGER

UNIT

INSTRUCTION

ATC

INSTRUCTION

MMU/CACHE/SNOOP

CONTROLLER

INSTRUCTION

CACHE

INSTRUCTION MEMORY UNIT

DATA MEMORY UNIT

DATA

MMU/CACHE/SNOOP

CONTROLLER

DATA

ATC

OPERAND DATA BUS

DATA

CACHE

INSTRUCTION

ADDRESS

DATA

ADDRESS

B U S

C O N T R O L L E R

ADDRESS

BUS

DATA

BUS

CONTROL

SIGNALS

TS68040

2116A–HIREL–09/02

TS68040

Introduction The TS68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the inte-

ger unit processing capabilities of the TS68030 microprocessor with independent 4K bytes data and instruction caches and an on-chip FPU. The TS68040 maintains the 32-bit registers available with the entire TS68000 Family as well as the 32-bit address and data paths, rich instruction set, and versatile addressing modes. Instruction execution proceeds in parallel with accesses to the internal caches, MMU operations, and bus controller activity. Additionally, the integer unit is optimized for high-level language environments.

The TS68040 FPU is user-object-code compatible with the TS68882 floating-point coprocessor and conforms to the ANSI/IEEE Standard 754 for binary floating-point arithmetic. The FPU has been optimized to execute the most commonly used subset of the TS68882 instruction set, and includes additional instruction formats for single and double-precision rounding of results. Floating-point instructions in the FPU execute concurrently with integer instructions in the integer unit.

The MMUs support multiprocessing, virtual memory systems by translating logical addresses to physical addresses using translation tables stored in memory. The MMUs store recently used address mappings in two separate ATCs-on-chip. When an ATC contains the physical address for a bus cycle requested by the processor, a translation table search is avoided and the physical address is supplied immediately, incurring no delay for address translation. Each MMU has two transparent translation registers available that define a one-to-one mapping for address space segments ranging in size from 16M bytes to 4G bytes each.

Each MMU provides read-only and supervisor-only protections on a page basis. Also, processes can be given isolated address spaces by assigning each a unique table structure and updating the root pointer upon a task swap. Isolated address spaces protect the integrity of independent processes.

The instruction and data caches operate independently from the rest of the machine, storing information for fast access by the execution units. Each cache resides on its own internal address bus and internal data bus, allowing simultaneous access to both. The data cache provides write through or copyback write modes that can be configured on a page-by-page basis.

The TS68040 bus controller supports a high-speed, non multiplexed, synchronous external bus interface, which allows the following transfer sizes: byte, word (2 bytes), long word (4 bytes), and line (16 bytes). Line accesses are performed using burst transfers for both reads and writes to provide high data transfer rates.

2116A–HIREL–09/02

Pin Assignments

PGA 179

Figure 2. Bottom View

Table 1 . Power Supply Affectation to PGA Body

GND V

PLL S8

Internal Logic C6, C7, C9, C11,C13, K3, K16, L3, M16, R4, R11, R13,

S10,T4,S9,R6,R10

Output Drivers B2, B4, B6, B8, B10, B13, B15, B17, D2, D17, F2, F17,

H2, H17, L2, L17, N2, N17, Q2, Q17, S2, S15, S17

TS68040

C5, C8, C10, C12, C14, H3, H16, J3, J16, L16, M3, R5, R12, R8

B5, B9, B14, C2, C17, G2, G17, M2, M17, R2, R17, S16

2116A–HIREL–09/02

CQFP 196

Figure 3. Pin Assignments

TS68040

Table 2 . Power Supply Affectation to CQFP Body

GND V

PLL 127

Internal Logic 4, 9, 10, 19, 32, 45, 73, 88, 113, 119, 121, 122, 124,

125, 129, 130, 141, 159, 172

Output Drivers 7, 15, 22, 28, 35, 42, 49, 50, 51, 57, 63, 69, 76, 77, 83,

84, 91, 97, 98, 99, 105, 106, 146, 147, 148, 149, 155, 162, 163, 169, 176, 182, 183, 189, 195, 196

2116A–HIREL–09/02

3, 18, 31, 40, 46, 60, 72, 87, 114, 126, 137, 158, 173, 186

12, 25, 38, 54, 66, 80, 94, 102, 152, 166, 179, 192

Signal Description Figure 4 and Table 3 describe the signals on the TS68040 and indicate signal functions.

The test signals, TRST IEEE testability bus standard.

Figure 4. Functional Signal Groups

, TMS, TCK, TDI, and TDO, comply with subset P-1149.1 of the

TS68040

2116A–HIREL–09/02

Table 3 . Signal Index

Signal Name Mnemonic Function

Address Bus A31-A0 32-bit address bus used to address any of 4G bytes

Data Bus D31-D0 32-bit data bus used to transfer up to 32 bits of data per bus transfer

TS68040

Transfer Type TT1, TT0

Transfer Modifier TM2, TM0 Indicates supplemental information about the access

Transfer Line Number TLN1, TLN0

User Programmable Attributes

Read Write R/W

Transfer Size SIZ1, SIZ0

Bus Lock LOCK

BusLockEnd LOCKE

Cache Inhibit Out CIOUT

Transfer Start TS

Transfer in Progress TIP

Transfer Acknowledge TA

Transfer Error Acknowledge TEA

Transfer Cache Inhibit TCI

UPA1,

UPA0

Indicates the general transfer type: normal, MOVE 16, alternate logical function code, and acknowledge

Indicates which cache line in a set is being pushed or loaded by the current line transfer

User-defined signals, controlled by the corresponding user attribute bits from the address translation entry

Identifies the transfer as a read or write

Indicates the data transfer size. These signals, together with A0 and A1, define the active sections of the data bus

Indicates a bus transfer is part of a read-modify-write operation, and that the sequence of transfers should not be interrupted

Indicates the current transfer is the last in a locked sequence of transfer

Indicates the processor will not cache the current bus transfer

Indicates the beginning of a bus transfer

Asserted for the duration of a bus transfer

Asserted to acknowledge a bus transfer

Indicates an error condition exists for a bus transfer

Indicates the current bus transfer should not be cached

Transfer Burst Inhibit TBI

Data Latch Enable DLE

Snoop Control SC1, SC0 Indicates the snooping operation required during an alternate master access

Memory Inhibit MI

Bus Request BR

Bus Grant BG

Bus Busy BB

Cache Disable CDIS

MMU Disable MDIS

Reset In RSTI

Reset Out RSTO

Interrupt Priority Level IPL2

Interrupt Pending IPEND

Autovector AVEC

Processor Status PST3-PST0 Indicates internal processor status

-IPL0 Provides an encoded interrupt level to the processor

Indicates the slave cannot handle a line burst access

Alternate clock input used to latch input data when the processor is operating in DLE mode

Inhibits memory devices from responding to an alternate master access during snooping operations

Asserted by the processor to request bus mastership

Asserted by an arbiter to grant bus mastership to the processor

Asserted by the current bus master to indicate it has assumed ownership of the bus

Dynamically disables the internal caches to assist emulator support

Disables the translation mechanism of the MMUs

Processor reset

Asserted during execution of the RESET instruction to reset external devices

Indicates an interrupt is pending

Used during an interrupt acknowledge transfer to request internal generation of the vector number

2116A–HIREL–09/02

Table 3 . Signal Index (Continued)

Signal Name Mnemonic Function

Bus Clock BCLK Clock input used to derive all bus signal timing

Processor Clock PCLK

Test Clock TCK Clock signal for the IEEE P1149.1 test access port (TAP)

Test Mode Select TMS Selects the principle operations of the test-support circuitry

Test Data Input TDI Serial data input for the TAP

Test Data Output TDO Serial data output for the TAP

Test Reset TRST

Power Supply V

Ground GND Ground connection

Clock input used for internal logic timing. The PCLK frequency is exactly 2X the BCLK frequency

Provides an asynchronous reset of the TAP controller

Power supply

Scope This drawing describes the specific requirements for the microprocessor TS68040 -

25 MHz and 33 MHz, in compliance with MIL-STD-883 class B or Atmel standard screening.

Applicable Documents

MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics.

2. MIL-I-38535: general specifications for microcircuits.

3. DESC 5962-93143.

Requirements

General The microcircuits are in accordance with the applicable document and as specified

herein.

Design and Construction

Terminal Connections See Figure 2 and Figure 3.

Lead Material and Finish Lead material and finish shall be as specified in MIL-STD-883 (see enclosed “MIL-STD-

883 C and Internal Standard” on page 46).

Package The macro circuits are packaged in hermetically sealed ceramic packages which con-

form to case outlines of MIL-STD-1835-or as follow:

• CMGA 10-179-PAK pin grid array, but see “179 pins – PGA” on page 43.

• Similar to CQCC1-F196C-U6 ceramic uniform lead chip carrier package with

ceramic nonconductive tie-bar but use Atmel’s internal drawing, see “196 pins – Tie Bar CQFP Cavity Up (on request)” on page 44.

• Gullwing shape CQFP see “196 pins – Gullwing CQFP cavity up” on page 45.

TS68040

2116A–HIREL–09/02

TS68040

The precise case outlines are described at the end of the specification (See “Package Mechanical Data” on page 43.) and into MIL-STD-1835.

Electrical Characteristics

Absolute Maximum Ratings Stresses above the absolute maximum rating may cause permanent damage to the

device. Extended operation at the maximum levels may degrade performance and affect reliability.

Table 4 . Absolute Maximum Ratings

Symbol Parameter Condition Min Max Unit

Supply Voltage Range -0.3 7.0 V

Input Voltage Range -0.3 7.0 V

Large buffers enabled 7.7 W

stg

lead

Power Dissipation

Small buffers enabled 6.3 W

Operating Temperature -55 T

°C

Storage Temperature Range -65 +150 °C

Junction Temperature

(1)

+125 °C

Lead Temperature Max.10 sec soldering +300 °C

Note: 1. This device is not tested at TC = +125°C. Testing is performed by setting the junction temperature Tj = +125°C and allowing

the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

Table 5 . Recommended Conditions of Use Unless otherwise stated, all voltages are referenced to the reference terminal

Symbol Parameter Min Typ Max Unit

Note: 1. This device is not tested at TC = +125°C. Testing is performed by setting the junction temperature T

the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

Supply Voltage Range +4.75 +5.25 V

Logic Low Level Input Voltage Range GND

-0.3

0.8 V

Logic High Level Input Voltage Range +2.0 VCC+0.3 V

High Level Output Voltage 2.4 V

Low Level Output Voltage 0.5 V

Clock Frequency -25 MHz Version 25 MHz

-33 MHz Version 33 MHz

Case Operating Temperature Range

(1)

-55 T

Jmax

°C

Maximum Operating Junction Temperature +125 °C

=+125°C and allowing

2116A–HIREL–09/02

Thermal Considerations

General Thermal Considerations

Thermal Device Characteristics

Die and Package The TS68040 is being placed in a cavity-down alumina-ceramic 179-pin PGA that has a

This section is only given as user information.

As microprocessors are becoming more complex and requiring more power, the need to efficiently cool the device becomes increasingly more important. In the past, the TS68000 Family, has been able to provide a 0-70°C ambient temperature part for speeds less than 40 MHz. However, the TS68040, which has a 50 MHz arithmetic logic unit (ALU) speed, is specified with a maximum power dissipation for a particular mode, a maximum junction temperature, and a thermal resistance from the die junction to the case. This provides a more accurate method of evaluating the environment, taking into consideration both the air-flow and ambient temperature available. This also allows a user the information to design a cooling method which meets both thermal performance requirements and constraints of the board environment.

This section discusses the device characteristics for thermal management, several methods of thermal management, and an example of one method of cooling the TS68040.

The TS68040 presents some inherent characteristics which should be considered when evaluating a method of cooling the device. The following paragraphs discuss these die/package and power considerations.

specified thermal resistance from junction to case of 1°C/W. This package differs from previous TS68000 Family PGA packages which were cavity up. This cavity-down design allows the die to be attached to the top surface of the package, which increases the ability of the part to dissipate heat through the package surface or an attached heat sink. The maximum perimeter that the TS68040 allows for a heat sink on its surface without interfering with the capacitor pads is 1.48" x 1.48". The specific dimensions and design of the particular heat sink will need to be determined by the system designer considering both thermal performance requirements and size requirements.

Power Considerations The TS68040 has a maximum power rating, which varies depending on the operating

frequency and the output buffer mode combination being used. The large buffer output mode dissipates more power than the small, and the higher frequencies of operation dissipate more power than the lower frequencies. The following paragraphs discuss trade-offs in using the different output buffer modes, calculation of specific maximum power dissipation for different modes, and the relationship of thermal resistances and temperatures.

TS68040

2116A–HIREL–09/02

TS68040

Output Buffer Mode The 68040 is capable of resetting to enable for a combination of either large buffers or

small buffers on the outputs of the miscellaneous control signals, data bus, and address bus/transfer attribute pins. The large buffers offer quicker output times, which allow for an easier logic design. However, they do so by driving about 11 times as much current as the small buffers (refer to TS68040 Electrical specifications for current output). The designer should consider whether the quicker timings present enough advantage to justify the additional consideration to the individual signal terminations, the die power consumption, and the required cooling for the device. Since the TS68040 can be powered-up in one of eight output buffer modes upon reset, the actual maximum power consumption for TS68040 rated at a particular maximum operating frequency is dependent upon the power up mode. Therefore, the TS68040 is rated at a maximum power dissipation for either the large buffers or small buffers at a particular frequency (refer to TS68040 Electrical specifications). This allows the possibility of some of the thermal management to be controlled upon reset. The following equation provides a rough method to calculate the maximum power consumption for a chosen output buffer mode:

D=PDSB

+(P

DLB-PDSB

) · (PINSLB/PINS

)(1)

CLB

where:

= Max. power dissipation for output buffer mode selected

DSB

= Max. power dissipation for small buffer mode (all outputs)

DLB

= Max. power dissipation for large buffer mode (all outputs)

PINS

= Number of pins large buffer mode

= Number of pins capable of the large buffer

CLB

mode

Table 6 shows the simplified relationship on the maximum power dissipation for eight possible configurations of output buffer modes.

Table 6 . Maximum Power Dissipation for Output Buffer Mode Configurations

Output Configuration Maximum Power Dissipation

Address Bus and

Data Bus

Transfer Attrib.

Small Buffer Small Buffer Small Buffer P

Small Buffer Small Buffer Large Buffer P

Small Buffer Large Buffer Small Buffer P

Small Buffer Large Buffer Large Buffer P

Large Buffer Small Buffer Small Buffer P

Large Buffer Small Buffer Large Buffer P

Large Buffer Large Buffer Small Buffer P

Large Buffer Large Buffer Large Buffer P

Misc. Control

Signals PD

+(P

DSB

+(P

DSB

+(P

DSB

+(P

DSB

+(P

DSB

+(P

DSB

+(P

DSB

DLB-PDSB

) · 13%

) · 52%

) · 65%

) · 35%

) · 48%

) · 87%

) · 100%

2116A–HIREL–09/02

To calculate the specific power dissipation of a specific design, the termination method of each signal must be considered. For example, a signal output that is not connected would not dissipate any additional power if it were configured in the large buffer rather than the small buffer mode.

Relationships Between Thermal Resistances and Temperatures

Since the maximum operating junction temperature has been specified to be 125°C. The maximum case temperature, TC, in °C can be obtained from:

C=TJ-PD

· Φ

(2)

where:

= Maximum case temperature

= Maximum junction temperature

= Maximum power dissipation of the device

= Thermal resistance between the junction of the die and the case

In general, the ambient temperature, T

A=TJ-PD

· ΦJC-PD· Φ

Where the thermal resistance from case to ambient, Φ

,in°C is a function of the following formula:

(3)

, is the only user-dependent

parameter once a buffer output configuration has been determined. As seen from equation (3), reducing the case to ambient thermal resistance increases the maximum operating ambient temperature. Therefore, by utilizing such methods as heat sinks and ambient air cooling to minimize the Φ

, a higher ambient operating temperature and/or

a lower junction temperature can be achieved.

However, an easier approach to thermal evaluation uses the following formulas:

A=TJ-PD

· Φ

(4)

or alternatively,

Thermal Management Techniques

J=TA-PD

· Φ

(5)

where:

= thermal resistance from the junction to the ambient (ΦJC+ ΦCA).

This total thermal resistance of a package, Φ

and ΦCA. These components represent the barrier to heat flow from the semicon-

ductor junction to the package (case) surface (Φ ambient (Φ

). Although ΦJCis device related and cannot be influenced by the user, Φ

, is a combination of its two components,

) and from the case to the outside

is user dependent. Thus, good thermal management by the user can significantly reduce Φ

achieving either a lower semiconductor junction temperature or a higher

ambient operating temperature.

To attain a reasonable maximum ambient operating temperature, a user must reduce the barrier to heat flow from the semiconductor junction to the outside ambient (Φ The only way to accomplish this is to significantly reduce Φ

by applying such thermal

management techniques as heat sinks and ambient air cooling.

The following paragraphs discuss some results of a thermal study of the TS68040 device without using any thermal management techniques; using only air-flow cooling, using only a heat sink, and using heat sink combined with air-flow cooling.

TS68040

2116A–HIREL–09/02

TS68040

Thermal Characteristics in Still Air

A sample size of three TS68040 packages was tested in free-air cooling with no heat sink. Measurements showed that the average Φ

was 22.8°C/W with a standard devia-

tion of 0.44°C/W. The test was performed with 3W of power being dissipated from within the package. The test determined that Φ dissipation range possible. Therefore, since the variance in Φ

will decrease slightly for the increasing power

within the possible

power dissipation range is negligible, it can be assumed for calculation purposes that

is valid at all power levels. Using the formulas introduced previously, Table 7 shows

the results of a maximum power dissipation of 3 and 5W with no heat sink or air-flow (refer to Table 6 to calculate other power dissipation values).

Table 7 . Thermal Parameters With No Heat Sink or Air-flow

Defined Parameters Measured Calculated

ΦCA= ΦJA- Φ

TC=TJ-PD* Φ

TA=TJ-PD* Φ

3 Watts 125°C1°C/W 21.8°C/W 20.8°C/W 122°C 59.6°C

5 Watts 125°C1°C/W 21.8°C/W 20.8°C/W 120°C16°C

As seen by looking at the ambient temperature results, most users will want to implement some type of thermal management to obtain a more reasonable maximum ambient temperature.

Thermal Characteristics in Forced Air

A sample size of three TS68040 packages was tested in forced air cooling in a wind tunnel with no heat sink. This test was performed with 3W of power being dissipated from within the package. As previously mentioned, since the variance in ΦJA within the possible power range is negligible, it can be assumed for calculation purposes that Φ constant at all power levels. Using the previous formulas, Table 8 shows the results of the maximum power dissipation at 3 and 5W with air-flow and no heat sink (refer to Table 6 to calculate other power dissipation values).

Table 8 . Thermal Parameters With Forced Air Flow and No Heat Sink

Thermal Mgmt.

Technique Defined Parameters Measured Calculated

Air-flow velocity P

100 LFM 3W 125°C1°C/W 11.7°C/W 10.7°C/W 122°C 89.9°C

250 LFM 3W 125°C1°C/W 10°C/W 9°C/W 122°C95°C

500 LFM 3W 125°C1°C/W 8.9°C/W 7.9°C/W 122°C 98.3°C

750 LFM 3W 125°C1°C/W 8.5°C/W 7.5°C/W 122°C 99.5°C

1000 LFM 3W 125°C1°C/W 8.3°C/W 7.3°C/W 122°C 100.1°C

100 LFM 5W 125°C1°C/W 11.7°C/W 10.7°C/W 120°C 66.5°C

250 LFM 5W 125°C1°C/W 10°C/W 9°C/W, 120°C75°C

500 LFM 5W 125°C1°C/W 8.9°C/W 7.9°C/W 120°C 80.5°C

750 LFM 5W 125°C1°C/W 8.5°C/W 7.5°C/W 120°C 82.5°C

1000 LFM 5W 125°C1°C/W 8.3°C/W 7.3°C/W 120°C 83.5°C

2116A–HIREL–09/02

By reviewing the maximum ambient operating temperatures, it can be seen that by using the all-small-buffer configuration of the TS68040 with a relatively small amount of air flow (100 LFM), a 0-70°C ambient operating temperature can be achieved. However, depending on the output buffer configuration and available forced-air cooling, additional thermal management techniques may be required.

Thermal Characteristics with a Heat Sink

In choosing a heat sink the designer must consider many factors: heat sink size and composition, method of attachment, and choice of a wet or dry connection. The following paragraphs discuss the relationship of these decisions to the thermal performance of the design noticed during experimentation.

The heat sink size is one of the most significant parameters to consider in the selection of a heat sink. Obviously a larger heat sink will provide better cooling. However, it is less obvious that the most benefit of the larger heat sink of the pin fin type used in the experimentation would be at still air conditions. Under forced-air conditions as low as 100 LFM, the difference between the ΦCA becomes very small (0.4°C/W or less). This difference continues to decrease as the forced air flow increases. The particular heat sink used in our testing fit the perimeter package surface area available within the capacitor pads on the TS68040 (1.48" x 1.48") and showed a nice compromise between height and thermal performance needs. The heat sink base perimeter area was 1.24" x 1.30" and its height was 0.49". It was a pin-fin-type (i.e. bed of nails) design composed of Al alloy. The heat sink is shown in Figure 5 can be obtained through Thermalloy Inc. by referencing part number 2338B.

Figure 5. Heat Sink Example

TS68040

2116A–HIREL–09/02

TS68040

All pin fin heat sinks tested were made from extrusion Al products. The planar face of the heat sink mating to the package should have a good degree of planarity; if it has any curvature, the curvature should be convex at the central region of the heat sink surface to provide intimate physical contact to the PGA surface. All heat sinks tested met this criteria. Nonplanar, concave curvature the central regions of the heat sink will result in poor thermal contact to the package. A specification needs to be determined for the planarity of the surface as part of any heat sink design.

Although there are several ways to attach a heat sink to the package, it was easiest to use a demountable heat sink attach called “E-Z attach for PGA packages” developed by Thermalloy (see Figure 6). The heat sink is clamped to the package with the help of a steel spring to a plastic frame (or plastic shoes Besides the height of the heat sink and plastic frame, no additional height added to the package. The interface between the ceramic package and the heat sink was evaluated for both dry and wet (i.e., thermal grease) interfaces in still air. The thermal grease reduced the Φ (about 2.5 °C/W) in still air. Therefore, it was used in all other testing done with the heat sink. According to other testing, attachment with thermal grease provided about the same thermal performance as if a thermal epoxy were used.

Figure 6. Heat Sink with Attachment

quite significantly

2116A–HIREL–09/02

A sample size of one TS68040 package was tested in still air with the heat sink and attachment method previously described. This test was performed with 3W of power being dissipated from within the package. Since the variance in Φ power range is negligible, it can be assumed for calculation purposes that Φ

within the possible

is constant at all power levels. Table 9 shows the result assuming a maximum power dissipation of the part at 3 and 5W (refer to Table 6 to calculate other power dissipation values).

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