Features
• High Performance, Low Power AVR
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)
Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)
Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny25/45/85)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
• Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
4 Single Ended Channels
2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP and 8-pin SOIC
• Operating Voltage
– 1.8 - 5.5V for ATtiny25/45/85V
– 2.7 - 5.5V for ATtiny25/45/85
• Speed Grade
– ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 450µA
– Power-down Mode:
0.1µA at 1.8V
®
8-Bit Microcontroller
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25/V
ATtiny45/V
ATtiny85/V
Preliminary
Summary
2586AS–AVR–02/05
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
1. Pin Configurations
Figure 1-1. Pinout ATtiny25/45/85
PDIP/SOIC
8
VCC
7
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
6
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
5
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
GND
1
2
3
4
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
1.1 Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers
manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2
ATtiny25/45/85
2586AS–AVR–02/05
2. Overview
2.1 Block Diagram
ATtiny25/45/85
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
Figure 2-1. Block Diagram
8-BIT DATABUS
CALIBRATED
INTERNAL
TOR
OSCILLA
VCC
GND
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
DATA REGISTER
PORT B
WATCHDOG
TIMER
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
INTERRUPT
UNIT
DATA
EEPROM
DATA DIR.
REG.PORT B
TIMING AND
CONTROL
OSCILLATORS
ADC /
ANALOG COMPARATOR
2586AS–AVR–02/05
PORT B DRIVERS
RESET
PB0-PB5
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
3
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
2.2 Pin Descriptions
2.2.1 VCC
Supply voltage.
2.2.2 GND
Ground.
2.2.3 Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on
page 60.
On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged
in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15.
2.2.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page
37. Shorter pulses are not guaranteed to generate a reset.
4
ATtiny25/45/85
2586AS–AVR–02/05
ATtiny25/45/85
3. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F SREG I T H S V N Z C page 7
0x3E SPH – – – – – – – SP8 page 10
0x3D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 10
0x3C Reserved –
0x3B GIMSK – INT0 PCIE – – – – – page 49
0x3A GIFR – INTF0 PCIF – – – – – page 50
0x39 TIMSK – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – page 81
0x38 TIFR – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – page 81
0x37 SPMCSR – – – CTPB RFLB PGWRT PGERS SPMEN page 146
0x36 Reserved –
0x35 MCUCR –PUDSESM1SM0 –ISC01ISC00page 32, page 60, page 49
0x34 MCUSR – – – – WDRF BORF EXTRF PORF page 40,
0x33 TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 79
0x32 TCNT0 Timer/Counter0 page 80
0x31 OSCCAL Oscillator Calibration Register page 27
0x30 TCCR1 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 page 88, page 100
0x2F TCNT1 Timer/Counter1 page 90, page 101
0x2E OCR1A Timer/Counter1 Output Compare Register A page 90, page 102
0x2D OCR1C Timer/Counter1 Output Compare Register C page 91, page 102
0x2C GTCCR TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0
0x2B OCR1B Timer/Counter1 Output Compare Register B page 91
0x2A TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – WGM01 WGM00 page 76
0x29 OCR0A Timer/Counter0 – Output Compare Register A page 80
0x28 OCR0B Timer/Counter0 – Output Compare Register B page 80
0x27 PLLCSR SM – – – – PCKE PLLE PLOCK page 93, page 103
0x26 CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 30
0x25 DT1A DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 page 108
0x24 DT1B DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 page 109
0x23 DTPS1 - - - - - - DTPS11 DTPS10 page 108
0x22 DWDR DWDR[7:0] page 143
0x21 WDTCR WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 42
0x20 PRR – PRTIM1 PRTIM0 PRUSI PRADC page 33
0x1F EEARH EEAR8 page 16
0x1E EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 16
0x1D EEDR EEPROM Data Register page 16
0x1C EECR – – EEPM1 EEPM0 EERIE EEMWE EEWE EERE page 17
0x1B Reserved –
0x1A Reserved –
0x19 Reserved –
0x18 PORTB – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 64
0x17 DDRB – – DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 64
0x16 PINB
0x15 PCMSK – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 51
0x14 DIDR0
0x13 GPIOR2 General Purpose I/O Register 2
0x12 GPIOR1 General Purpose I/O Register 1
0x11 GPIOR0 General Purpose I/O Register 0
0x10 USIBR USI Buffer Register page 118
0x0F USIDR USI Data Register page 117
0x0E USISR USICIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 118
0x0D USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 119
0x0C Reserved
0x0B Reserved –
0x0A Reserved
0x09 Reserved
0x08 ACSR ACD ACBG
0x07 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 137
0x06 ADCSRA ADEN ADSC
0x05 ADCH ADC Data Register High Byte page 140
0x04 ADCL ADC Data Register Low Byte page 140
0x03 ADCSRB BIN ACME IPR – – ADTS2 ADTS1 ADTS0 page 122, page 140
0x02 Reserved
0x01 Reserved
0x00 Reserved –
– – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 64
– – ADC0D ADC2D ADC3D ADC1D EIN1D AIN0D page 124, page 141
–
–
–
ACO ACI ACIE – ACIS1 ACIS0 page 122
ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 138
–
–
page 84, page 89, page
2586AS–AVR–02/05
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