ATMEL ATtiny167 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

• Non-volatile Program and Data Memories

– 16K Byte of In-System Programmable (ISP) Program Memory Flash

Endurance: 10,000 Write/Erase Cycles

– 512 Bytes In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles – 512 Bytes Internal SRAM – Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

– Low size LIN/UART Software In-System Programmable

• Peripheral Features

– LIN 2.1 and 1.3 Controller or 8-Bit UART – 8-bit Asynchronous Timer/Counter0:

. 10-bit Clock Prescaler

. 1 Output Compare or 8-bit PWM Channel – 16-bit Synchronous Timer/Counter1:

. 10-bit Clock Prescaler

. External Event Counter

. 2 Output Compares Units or 16-bit PWM Channels on 2x 4 Separated Pins – Master/Slave SPI Serial Interface, – Universal Serial Interface (USI) with Start Condition Detector (Master/Slave SPI,

TWI, AES, ...) – 10-bit ADC:

. 11 Single Ended Channels

. 16 Differential ADC Channel Pairs with Programmable Gain (8x or 20x) – On-chip Analog Comparator with Selectable Voltage Referenc e – 100µA ±6% Current Source (LIN Node Identification) – On-chip Temperature Sensor – Programmable Watchdog Timer with Separate On-chip Oscillator

• Special Microcontroller Features

– Dynamic Clock Switching (External/Internal RC/Watchdog Clock) – DebugWIRE On-chip Debug (OCD) System – Hardware In-System Programmable (ISP) via SPI Port – External and Internal Interrupt Sources – Interrupt and Wa ke -up on Pin Change – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated RC Oscillator 8MHz – 4-16 MHz and 32 KHz Crystal/Ceramic Resonator Oscillators

• I/O and Packages

– 16 Programmable I/O Lines – 20-pin SOIC, 32-pad QFN and 20 -p in TSSOP

• Operating Voltage:

– 2.7 - 5.5V for ATtiny167

• Speed Grade:

– 0 - 8 MHz @ 2.7 - 5.5V (Automotive Temp. Range: -40°C to +125°C) – 0 - 16 MHz @ 4.5 - 5.5V (Automotive Temp. Range: -40°C to +125°C)

8-Bit Microcontroller

8-bit Microcontroller with 16K Bytes In-System Programmable Flash and LIN Controller

ATtiny167 Automotive

Preliminary

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1. Description

1.1 Part Description

The ATtiny167 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny167 achieves throughputs approaching 1 MIPS pe r MHz allow ing the sy stem de signer to op timize po wer con sumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATtiny167 provides the following features: 16K byte of In-System Programmable Flash, 512 bytes EEPROM, 512 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Co unter, Universal Serial Interface, a LIN controller, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, an d Inte rrup t syst em t o co ntinu e fu nctio ning. Th e Pow er-dow n mode saves the register contents, disabling all chip functions until the nex t Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The Boot program can use any interface to download the application program in the Flash memory. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtin y167 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATtiny167 AVR is supported w ith a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

1.2 Automotive Quality Grade

The ATtiny167 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of exten sive characterizatio n (temperature and voltage). The q uality and reliability of the ATtiny167 have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in only one temperature grade as listed in Table 1-1.

Table 1-1. Temperature Grade Identification for Automotive Products

Temperature

-40°C / +125°C Z Automotive Temperature Range

Temperature

Identifier

Comments

ATtiny167

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1.3 Disclaimer

PORT A (8) LIN / UARTPORT B (8)

SPI & USI

Timer/Counter-0

Timer/Counter-1 A/D Conv.

Internal

Voltage

References

Analog Comp.

SRAMFlash

EEPROM

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

Powe r

Supervision

POR / BOD &

RESET

VCC

GND

PROGRAM

LOGIC

debugWIRE

AGND

AVCC

DATA B U S

PA[0..7]PB[0..7]

RESET XTAL[1;2]

CPU

1.4 Block Diagram

ATtiny167

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max values will be available after the device is characterized.

Figure 1-1. Block Dia gram

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1.5 Pin Configuration

PB0 (PCINT8 / OC1AU / DI / SDA) PB1 (PCINT9 / OC1BU / DO) PB2 (PCINT10 / OC1AV / USCK / SCL) PB3 (PCINT11 / OC1BV) GND VCC PB4 (PCINT12 / OC1AW / XTAL1 / CLKI) PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO) PB6 (PCINT14 / ADC9 / OC1AX / INT0) PB7 (PCINT15 / ADC10 / OC1BX / RESET / dW)

(RXLIN / RXD / ADC0 / PCINT0) PA0 (TXLIN / TXD / ADC1 / PCINT1) PA1

(MISO / DO / OC0A / ADC2 / PCINT2) PA2

(INT1 / ISRC / ADC3 / PCINT3) PA3

AVCC

AGND

(MOSI / SDA / DI / ICP1 / ADC4 / PCINT4) PA4

(SCK / SCL / USCK / T1 / ADC5 / PCINT5) PA5

(SS / AIN0 / ADC6 / PCINT6) PA6

(AREF / XREF / AIN1 / ADC7 / PCINT7) PA7

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

20-pin

top

view

(INT0 / OC1AX / ADC9 / PCINT14 ) PB6

PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO)

PB4 (PCINT12 / OC1AW / XTAL1 / CLKI)

VCC

GND

1 2

3 4 5

21 20 19 18

323029

32-lead

top view

PB2 (PCINT10 / OC1AV / USCK / SCL)

PB1 (PCINT9 / OC1BU / DO) (dW / RESET / OC1BX / ADC10 / PCINT15) PB7

(AREF / XREF / AIN1 / ADC7 / PCINT7) PA7

(SS / AIN0 / ADC6 / PCINT6) PA6

(SCK / SCL / USCK / T1 / ADC5 / PCINT5) PA5

AGND

AVCC

(INT1 / ISRC / ADC3 / PCINT3) PA3

PA1 (PCINT1 / ADC1 / TXD / TXLIN)

PA2 (PCINT2 / ADC2 / OC0A / DO / MISO)

nc nc nc

nc nc

PA0 (PCINT0 / ADC0 / RXD / RXLIN)

INDEX CORNER

Bottom pad should be soldered to ground

6 7

141516

PB3 (PCINT11 / OC1BV)

24 23 22

272526

PB0 (PCINT8 / OC1AU / DI / SDA)

(MOSI / SDA / DI / ICP1 / ADC4 / PCINT4) PA4

Figure 1-2. Pinout ATtiny167 - SOIC20 & TSSOP20

Figure 1-3. Pinou t ATt iny 16 7 - QF N3 2

1.6 Pin Description

1.6.1 Vcc

ATtiny167

Supply voltage.

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1.6.2 GND

Ground.

1.6.3 AVcc

Analog supply voltage.

1.6.4 AGND

Analog ground.

1.6.5 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port wit h intern al pull-up r esistors ( selecte d for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port A also serves the functions of various special feat ures of the AT tiny167 as liste d on Section

9.3.3 ”Alternate Functions of Port A” on page 73.

1.6.6 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port wit h intern al pull-up r esistors ( selecte d for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

ATtiny167

Port B also serves the functions of various special feat ures of the AT tiny167 as liste d on Section

9.3.4 ”Alternate Functions of Port B” on page 78.

1.7 Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

1.8 About Code Examples

This documentation contains simple code examples that briefly sh ow how to use vari ous parts of the device. These code examples assume that the part specific header file is included b efore compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Plea se con firm with th e C com piler d ocumentation for more details.

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2. AVR CPU Core

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

EEPROM

Data Bus 8-bit

I/O Lines

Data

SRAM

Direct Addressing

Indirect Addressing

I/O Module 2

Analog

Comparator

I/O Module1

Watchdog

Timer

I/O Module n

Interrupt

Unit

A.D.C.

2.1 Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 2-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipe lining. While one instruc tion is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) opera tion. In a typical ALU operation, two operands are output from the Reg ister File, the opera tion is executed, and the result is stored back in the Register File – in one clock cycle.

ATtiny167

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ATtiny167

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.

2.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU opera tions are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

2.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in man y case s re move th e need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be ha nd le d by software.

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2.3.1 SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

I T H S V N Z C SREG

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

ATtiny167

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2.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 2-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 2-2. AVR CPU General Purpose Working Registers

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

ATtiny167

7 0 Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 2-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

2.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some a dded functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 2-3 on page 10.

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2.5 Stack Pointer

Figure 2-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A) 15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C) 15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed d isplacem ent, automatic increment, and automatic decrement (see the instruction set reference fo r details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memor y locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present

2.5.1 SPH and SPL – Stack Pointer Register

Bit 151413121110 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

ATtiny167

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2.6 Instruction Execution Timing

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 2-4 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 2-4. The Parallel Instruction Fetches and Instruction Executions

ATtiny167

, directly generated from the selected clock source for the

CPU

2.7 Reset and Interrupt Handling

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Figure 2-5 shows the internal timing concept for the Register File. In a single clock cycl e an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

Figure 2-5. Single Cycle ALU Operation

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with th e Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in Section 7. ”Interrupts” on page 57. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0.

2.7.1 Interrupt behavior

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disap pears befo re the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

ATtiny167

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When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

2.7.2 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clo ck cycles. This increase comes in addition to the start-up time from the selected sleep mode.

ATtiny167

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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3. AVR Memories

This section describes the different memories in the ATtiny167. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny167 features an EEPROM Memory for data storage. All three memory spaces are lin ear and regular.

Table 3-1. Memory Mapping.

Memory Mnemonic ATtiny167

Flash

32 Registers

I/O

Registers

Ext I/O

Registers

Internal

SRAM

EEPROM

Size Start Address

End Address

Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address

Flash size 16 K bytes

Flash end

- 32 bytes

- 0x0000

- 0x001F

- 64 bytes

- 0x0020

- 0x005F

- 160 bytes

- 0x0060

- 0x00FF ISRAM size 512 bytes ISRAM start 0x0100 ISRAM end 0x02FF

E2 size 512 bytes

- 0x0000

E2 end 0x01FF

0x3FFF 0x1FFF

(1) (2)

Notes: 1. Byte address.

2. Word (16-bit) address.

3.1 In-System Re-programmable Flash Program Memory

The ATtiny167 contains On-chip In-System Reprogrammable Flash memory for program storage (see “Flash size” in Table 3-1 on page 14). Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16 bits wide. ATtiny167 does not have separate Boot Lo ader and Application Program sections, and the SPM instruction can be executed from the entire Flash. See SELFPRGEN description in Section 20.2.1 ”Store Program Memory Control and Status

The Flash memory has an endurance of at least 10,000 write/erase cycles in automotive range. The ATtiny167 Program Counter (PC) address the program memory locations. Section 21.

”Memory Programming” on page 216 contains a detailed description on Flash data serial down-

loading using the SPI pins. Constant tables can be allocated within the entire Prog ram memory address space (se e the

LPM – Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in Section 2.6 ”Instruction

Execution Timing” on page 11.

ATtiny167

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Figure 3-1. Program Memory Map

0x0000

Flash end

Program Memory

3.2 SRAM Data Memory

Figure 3-2 shows how the ATtiny167 SRAM Memory is organized.

ATtiny167

The ATtiny167 is a complex microcontroller with more peripheral units tha n can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next locations address the internal data SRAM (see “ISRAM size” in Table 3-1 on page 14).

The five different addressing modes for the Data memory cov er: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base addres s given

by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers and the

internal data SRAM in the ATtiny167 are all accessible through all these add ressing mo des. The Register File is described in ”General Purpose Register File” on page 9.

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Figure 3-2. Data Memory Map

32 Registers

64 I/O Registers

Internal SRAM

(ISRAM size)

0x0000 - 0x001F 0x0020 - 0x005F

ISRAM end

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

ISRAM start

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

3.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Figure 3-3. On-chip Data SRAM Access Cycles

cycles as described in Figure 3-3.

CPU

3.3 EEPROM Data Memory

3.3.1 EEPROM Read/Write Access

The ATtiny167 contains EEPROM memory (see “E2 size” in Table 3-1 on page 14). It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control Register.

Section 21. ”Memory Programming” on page 216 contains a detailed description on EEPROM

programming in SPI or Parallel Programming mode.

The EEPROM Access Registers are accessible in the I/O space.

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The write access times for the EEPROM are given in Table 3-2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, Vcc is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specif ied as m inimu m for the clock fre que ncy us ed. See ”Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to ”Atomic Byte Programming” on page 17 and ”Split Byte Programming” on page 17 for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

3.3.2 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEARL Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations.

ATtiny167

3.3.3 Split Byte Programming

It is possible to split the erase and write cycle in two different operation s. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required th at the loca tions to be written have been erased before the write oper ation. But since the e rase and write operatio ns are split, it is possible to do the erase operations whe n the system allows doing time-critical operations (typically after Power-up).

3.3.4 Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b0 1, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations.

3.3.5 Write

To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations.

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in ”OSCCAL – Oscillator Calibration Register” on

page 36.

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The following code examples s how o ne as sembly a nd one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR, r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0<<EEPM0);

/* Set up address and data registers */

EEAR = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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ATtiny167

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

3.3.6 Preventing EEPROM Corruption

During periods of low Vcc, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situ at ion s wh en the vo lt age is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

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EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-ou t Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low Vcc reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

3.4 I/O Memory

The I/O space definition of the ATtiny167 is shown in Section 25. ”Register Summary” on page

257.

All ATtiny167 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructio ns, transferring data be tween the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny167 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instru ct ion s can be us ed .

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

3.4.1 General Purpose I/O Registers

The ATtiny167 contains three General Purpose I/O Registers. These registers can b e used for storing any information, and they are particularly useful for storing global variables and Status Flags.

The General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

3.5 Register Description

3.5.1 EEARH and EEARL – EEPROM Address Register

Bit 76543210

-------EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Bit 76543210 Read/Write RRRRRRRR/W Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value0000000X Initial ValueXXXXXXXX

• Bit 7:1 – Reserved Bits

These bits are reserved for future use and will always read as 0 in ATtiny167.

• Bits 8:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM address in the EEPROM space (see “E2 size” in Table 3-1 on page 14). The EEPROM data bytes are

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addressed linearly between 0 and “E2 size”. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

Note: For information only - ATtiny47: EEAR8 exists as register bit but it is not used for addressing.

3.5.2 EEDR – EEPROM Data Register

Bit 76543210

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

3.5.3 EECR – EEPROM Control Register

Bit 76543210

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

ATtiny167

• Bit 7,6 – Res: Reserved Bits

These bits are reserved for future use and will always read as 0 in ATtiny167. After reading, mask out these bits. For compatibility with future AVR devices, always write these bits to zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in on e atomic operation (e rase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for th e differen t modes are shown in Table 3- 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 3-2. EEPROM Mode Bits

Typical

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

Programming

Time

Operation

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming.

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• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

3.5.4 General Purpose I/O Register 2 – GPIOR2

Bit 76543210

GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000

3.5.5 General Purpose I/O Register 1 – GPIOR1

Bit 76543210

GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000

3.5.6 General Purpose I/O Register 0 – GPIOR0

Bit 76543210

GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000

ATtiny167

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4. System Clock and Clock Options

Modules

clk

I/O

clk

ASY

AVR Clock

Control Unit

clk

CPU

clk

FLASH

Source Clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Prescaler

Multiplexer

Watchdog Clock

Low-frequency

Crystal Oscillator

Crystal

Oscillator

External Clock

clk

ADC

Asynchronous

Timer/Counter0

General I/O ADC CPU Core RAM

Flash and EEPROM

Calibrated RC

Oscillator

PB5 / XTAL2 / CLKOPB4 / XTAL1 / CLKI

CKOUT

Fuse

Clock Switch

The ATtiny167 provides a large number of clock sources. They can be divided into two categories: internal and external. Some external clock sources can be shared with the asynchronous timer. After reset, the clock source is determined by the CKSEL Fuses. Once the device is running, software clock switching is possible to any other clock sources. Hardware controls are provided for clock switching management but some specific pro cedures must be observed. Clock switching should be performed with caution as some settings could result in the device having an incorrect configuration.

4.1 Clock Systems and their Distribution

Figure 4-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

may not need to be active at any given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using diffe rent sleep mo des or by using features of the dynamic clock switch circuit (See ”Power Management and Sleep Modes” on page 41 and

”Dynamic Clock Switch” on page 30). The clock systems are detailed below.

Figure 4-1. Clock Distribution

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4.1.1 CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with the AVR core operation. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

4.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like synchronous Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

4.1.3 Flash Clock – clk

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

4.1.4 Asynchronous Timer Clock – clk

The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an external low frequency crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.

4.1.5 ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

4.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits (default) or by the CLKSELR register (dynamic clock switch circuit) as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

ASY

Table 4-1. Device Clocking Options Select

Device Clocking Option

External Clock 0000 Calibrated Internal RC Oscillator 8.0 MHz 0010 Watchdog Oscillator 128 kHz 001 1 External Low-frequency Oscillator 01xx External Crystal/Ceramic Resonator (0.4 - 0.9 MHz) 10 0x External Crystal/Ceramic Resonator (0.9 - 3.0 MHz) 10 1x External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) 110x External Crystal/Ceramic Resonator (8.0 - 16.0 MHz) 111x

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option are given in the following sections.

ATtiny167

2. Flash Fuse bits.

3. CLKSELR register bits.

(1)

vs. PB4 and PB5 Functionality

CKSEL3..0

CSEL3..0

(2)

(3)

PB4 PB5

CLKI CLKO - I/O

I/O CLKO - I/O

I/O CLKO - I/O XTAL1 XTAL2 XTAL1 XTAL2 XTAL1 XTAL2 XTAL1 XTAL2 XTAL1 XTAL2

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ATtiny167

When the CPU wakes up from Power-down or Power-save, or when a new clock source is enabled by the dynamic clock switch circuit, the selected clock source is used to time the startup, ensuring stable oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up sequence. The number of WDT Oscillator cycles used for each time-out is shown in Table 4-2.

Table 4-2. Number of Watchdog Oscillator Cycles

Typ. Time-out

(Vcc = 5.0V)

4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192)

4.2.1 Default Clock Source

At reset, the CKSEL and SUT fuse settings are copied into the CLKSELR register. The device will then use the clock source and the start-up timings defined by the CLKSELR bits (CSEL3..0 and CSUT1:0).

The device is shipped with CKSEL Fuses = 0010 grammed. The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with the longest start-up time and an initial system clock divided by 8. This default setting ensures that all users can make their desired clock source setting using an In-System or Highvoltage Programmer. This set-up must be taken into account when using ISP tools.

4.2.2 Calibrated Internal RC Oscillator

By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be accurately calibrated by the user. See Table 22-1

on page 235 and Section 24.7 ”Internal Oscillator Speed” on page 254 for more details.

If selected, it can operate without external components. At reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically configuring the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 22-1 on

page 235.

Typ. Time-out

(Vcc = 5.0V)

, SUT Fuses = 10 b, and CKDIV8 Fuse pro-

Number of Cycles

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By adjusting the OSCCAL register in software, see ”OSCCAL – Oscillator Calibration Register”

on page 36, it is possible to get a higher calibration accuracy than by using the factory calibra-

tion. The accuracy of this calibration is shown as User calibration in Table 22-1 on page 235. The Watchdog Oscillator will still be used for the Watchdog Timer and for th e Reset Time-out

even when this Oscillator is used as the device clock. For more information on the pre-programmed calibration value, see the section ”Calibration Byte” on page 218.

Table 4-3. Internal Calibrated RC Oscillator Operating Modes

Frequency Range

7.6 - 8.4 0010

Notes: 1. If 8 MHz frequency exceeds the specification of the device (depends on Vcc), the CKDIV8

fuse can be programmed in order to divide the internal frequency by 8.

2. The frequency ranges are guideline values.

3. The device is shipped with this CKSEL = “0010”.

4. Flash Fuse bits.

(2)

(MHz)

(1)

CKSEL3..0

CSEL3..0

(3)(4) (5)

5. CLKSELR register bits.

When this Oscillator is selected, start-up times are determined by the SUT Fuses or by CSUT field as shown in Table 4-4.

Table 4-4. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1..0

CSUT1..0

Notes: 1. Flash Fuse bits

(1)

(3)

01 6 CK 14CK + 4.1 ms Fast rising power

(4)

11 Reserved

2. CLKSELR register bits

3. This setting is only available if RSTDISBL fuse is not set

4. The device is shipped with this option selected.

4.2.3 128 KHz Internal Oscillator

The 128 KHz internal Oscillator is a low power Oscillator providing a clock of 128 KHz. The frequency is nominal at 3V and 25°C. This clock may be selected as the system clock by programming CKSEL Fuses or CSEL field as shown in Table 4-1 on page 24.

When this clock source is selected, start-up times are determined by the SUT Fuses or by CSUT field as shown in Table 4-5.

(2)

Start-up Time from

Power-down/save

6 CK 14CK BOD enabled

6 CK 14CK + 65 ms Slowly rising power

Additional Delay from

Reset (Vcc = 5.0V)

Recommended Usage

Table 4-5. Start-up Times for the 128 kHz Internal Oscillator

Notes: 1. Flash Fuse bits

4.2.4 Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 4-2. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 4-6. For ceramic resonators, the capacitor values given by the manufacturer should be used.

SUT1..0

CSUT1..0

(1)

(2)

(3)

01 6 CK 14CK + 4.1 ms Fast rising power 10 6 CK 14CK + 65 ms Slowly rising power 11 Reserved

2. CLKSELR register bits

3. This setting is only available if RSTDISBL fuse is not set

Start-up Time from

Power-down/save

6 CK 14CK BOD enabled

Additional Delay

from Reset

(Vcc = 5.0V)

Recommended Usage

ATtiny167

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ATtiny167

XTAL2

XTAL1

GND

Figure 4-2. Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in

Table 4-6.

Table 4-6. Crystal Oscillator Operating Modes

CKSEL3..1

CSEL3..1

100

(1)

(2)

(3)

Frequency Range (MHz)

0.4 - 0.9 –

Recommended Range for Capacitors

C1 and C2 for Use with Crystals (pF)

101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22

111 8.0 - 16.0 12 - 22

Notes: 1. Flash Fuse bits.

2. CLKSELR register bits.

3. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown in Table 4-7.

Table 4-7. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0

CSEL0

(1)

(2)

SUT1..0

CSUT1..0

(1)

Start-up Time from

(2)

Power-down/save

0 00 258 CK

0 01 258 CK

010

(5)

1K (1024) CK

0 11 1K (1024)CK

1 00 1K (1024)CK

(3)

(4)

Additional Delay

from Reset

(Vcc = 5.0V)

14CK + 4.1 ms

14CK + 65 ms

14CK

14CK + 4.1 ms

14CK + 65 ms

Recommended Usage

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

7728A–AUTO–07/08

Table 4-7. Start-up Times for the Crystal Oscillator Clock Selection (Continued)

XTAL2

XTAL1

GND

C1=12-22 pF

32.768 KHz

12-22 pF capacitors may be necessary if parasitic

impedance (pads, wires & PCB) is very low.

C2=12-22 pF

(1)

CKSEL0

Notes: 1. Flash Fuse bits.

(2)

CSEL0

101

1 10 16K (16384) CK 14CK + 4.1 ms

1 11 16K (16384) CK 14CK + 65 ms

2. CLKSELR register bits.

3. These options should only be used when not operating close to the maximum frequency of the

4. These options are intended for use with ceramic resonators and will ensure frequency stability

5. This setting is only available if RSTDISBL fuse is not set.

SUT1..0

CSUT1..0

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

4.2.5 Low-frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses or CSEL field as shown in Table 4-1 on page

24. The crystal should be connected as shown in Figure 4-3. Refer to the 32.768 kHz Crystal

Oscillator Application Note for details on oscillator operation and how to choose appropriate values for C1 and C2.

(1)

Start-up Time from

(2)

Power-down/save

(5)

16K (16384) CK 14CK

Additional Delay

from Reset

(Vcc = 5.0V)

Recommended Usage

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

The 32.768 kHz watch crystal oscillator can be used by the asynchronous timer if the (high-frequency) Crystal Oscillator is not running or if the External Clock is not enabed (See

”Enable/Disable Clock Source” on page 31.). The asynchronous timer is then able to start itself

this low-frequency crystal oscillator.

Figure 4-3. Low-frequency Crystal Oscillator Connections

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4.2.6 External Clock

(XTAL2)

(CLKO)

CLKI

(XTAL1)

GND

External

Clock

Signal

ATtiny167

When this oscillator is selected, start-up times are determined by the SUT fuses or by CSUT field as shown in Table 4-8.

Table 4-8. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

SUT1..0

CSUT1..0

Notes: 1. Flash Fuse bits.

To drive the device from this external clock so ur ce, CL KI sho uld be d riven as shown in Figure 4-

4. To run the device on an external clock, the CKSEL Fuses or CSEL field must be programmed

as shown in Table 4-1 on page 24.

(1)

Start-up Time from

(2)

Power-down/save

00 1K (1024) CK 01 1K (1024) CK 10 32K (32768) CK 65 ms Stable frequency at start-up 11 Reserved

2. CLKSELR register bits.

3. These options should only be used if frequency stability at start-up is not important for the application.

(3)

Additional Delay from

Reset (Vcc = 5.0V)

4.1 ms Fast rising power or BOD enabled 65 ms Slowly rising power

Recommended usage

Figure 4-4. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in Table 4-9.

This external clock can be used by the asynchronous timer if the high or low frequency Crystal Oscillator is not running (See ”Enable/Disable Clock Source” on page 31.). The asynchronous timer is then able to enable this input.

Table 4-9. Start-up Times for the External Clock Selection

SUT1..0

CSUT1..0

(1)

00 6 CK 14CK (+ 4.1 ms 01 6 CK 14CK + 4.1 ms Fast rising power 10 6 CK 14CK + 65 ms Slowly rising power

Start-up Time from

(2)

Power-down/save

Additional Delay from Reset

(Vcc = 5.0V)

(3)

) BOD enabled

Recommended Usage

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11 Reserved

Notes: 1. Flash Fuse bits.

2. CLKSELR register bits.

3. Additional delay (+ 4ms) available if RSTDISBL fuse is set.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page

36 for details.

4.2.7 Clock Output Buffer

If not using a crystal oscillator, the device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse or COUT bit of CLKSELR register has to be programmed. This option is useful when the device clock is nee ded to d rive ot her circ uits on th e sys tem. N ote that the clock will not be output during reset and the normal operation of I/O pin will be overridden when the fuses are programmed. If the System Clock Prescaler is used, it is the divided system clock that is output.

4.3 Dynamic Clock Switch

4.3.1 Features

The ATtiny167 provides a powerful dynamic clock switch circuit that allows users to turn on and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or disabled asynchronously. This enables efficient power management schemes to be implemented easily and quickly. In a safety application, the dynamic clock switch circuit allows continuous monitoring of the external clock permitting a fallback scheme in case of clock failure.

The control of the dynamic clock switch circuit must be supervised by software. This operation is facilitated by the following features:

• Safe commands, to avoid unintentional commands, a special write procedure must be

• Exclusive action, the actions are controlled by a decoding table (commands) written to the

• Command status return. The ‘Request Clock Availability ’ command returns status via the

4.3.2 CLKSELR Register

4.3.2.1 Fuses Substitution

At reset, bits of the Low Fuse Byte are copied into the CL KSELR register. The content of this register can subsequently be user modified to overwrite the default values from the Low Fuse Byte. CKSEL3..0, SUT1..0 and CKOUT fuses correspond respectively to CSEL3..0, CSUT1:0 and ~(COUT) bits of the CLKSELR register as shown in Figure 4-5 on page 31.

followed to change the CLKCSR register bits (See Section “4.5.3” on page 38.):

CLKCSR register. This ensures that only one command operation can be launched at any time. The main actions of the decoding table are:

–‘Disable Clock Source’, –‘Enable Clock Source’, –‘Request Clock Availability’, –‘Clock Source Switching’, –‘Recover System Clock Source’, –‘Enable Watchdog in Automatic Reload Mode’.

CLKRDY bit in the CLKCSR register. The ‘Recover System Clock Source ’ command returns a code of the current clock source in the CLKSELR register. This information is used in the supervisory software routines as shown in Section 4.3.7 on page 32.

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