ATMEL ATtiny13A User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 120 Powe rful Instructions – Most Single Clock Cy cle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Througput at 20 MHz

• High Endurance Non-volatile Memory segments

– 1K Bytes of In-System Self-programmable Flash program memory – 64 Bytes EEPROM – 64 Bytes Internal SRAM – Write/Erase cyles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (see page 6) – Programming Lock for Self-Programming Flash & EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels – 4-channel, 10-bit ADC with Internal Voltage Reference – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator

• Special Microcontroller Features

– debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit with Software Disable Function – Internal Calibrated Oscillator

• I/O and Pac kages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines – 20-pad MLF: Six Programmable I/O Lines

• Operating Voltage:

– 1.8 - 5.5V

• Speed Grade:

– 0 - 4 MHz @ 1.8 - 5.5V – 0 - 10 MHz @ 2.7 - 5.5V – 0 - 20 MHz @ 4.5 - 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode:

• 190 µA at 1.8 V and 1 MHz

–Idle Mode:

• 24 µA at 1.8 V and 1 MHz

8-Bit Microcontroller

8-bit

Microcontroller with 1K Bytes In-System Programmable Flash

ATtiny13A

Rev. 8126A–AVR–05/08

ATtiny13A

1. Pin Configurations

Figure 1-1. Pinout ATtiny13A

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

8-PDIP/SOIC

1 2 3

GND

20-QFN/MLF

DNC

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

DNC

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC DNC

(PCINT4/ADC2) PB4

NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

(PCINT4/ADC2) PB4

GND

2019181716

1 2 3 4 5

DNC

GND

10-QFN/MLF

1 2 3 4 5

DNC

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

DNC

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect

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1.1 Pin Descriptions

1.1.1 VCC

Digital supply voltage.

1.1.2 GND

Ground.

1.1.3 Port B (PB5:PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny13A as listed on page

55.

1.1.4 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 18-4 on page

120. Shorter pulses are not guaranteed to gener at e a re se t.

ATtiny13A

The reset pin can also be used as a (weak) I/O pin.

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ATtiny13A

2. Overview

2.1 Block Diagram

The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS pe r MHz allow ing the sy stem de signer to optimize power c onsumption versus processing speed.

Figure 2-1. Block Diagram

8-BIT DATABUS

VCC

GND

INSTRUCTION

DECODER

CONTROL

LINES

STACK

POINTER

SRAM

PROGRAM

COUNTER

PROGRAM

FLASH

GENERAL

PURPOSE

REGISTERS

X Y Z

ALU

STATU S

WATCHDOG

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

MCU STATUS

TIMER/

COUNTER0

INTERRUPT

UNIT

PROGRAMMING

LOGIC

DATA

EEPROM

CALIBRATED

INTERNAL

TOR

OSCILLA

TIMING AND

CONTROL

ADC / ANALOG COMPARATOR

DATA REGISTER

PORT B

PORT B DRIVERS

PB0-PB5

DATA DIR.

REG.PORT B

RESET

CLKI

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ATtiny13A

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATtiny13A provides the following feat ures: 1K byte of In -System Programm able Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core.

The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.

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ATtiny13A

3. About

3.1 Resources

A comprehensive set of drivers, application notes, data sheet s and descr iption s on development tools are available for download at http://www.atmel.com/avr.

3.2 Code Examples

This documentation contains simple code examples t hat brief ly show h ow to us e various parts of the device. These code examples assume that the part specific header file is included b efore compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume ntation for more details.

3.3 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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4. CPU Core

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

4.1 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

ATtiny13A

Data Bus 8-bit

Flash

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Indirect Addressing

Status

and Control

32 x 8

General

Purpose

Registrers

ALU

Data

SRAM

Interrupt

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

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EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memo ry. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

ATtiny13A

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointe rs can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the AL U. After an arith metic operation, the Status Register is updated to reflect informat ion about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Prog ram Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.

4.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are execut ed . The ALU ope ra tio ns are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

4.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Refe rence. This wil l in many cases remove the n eed for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be hand le d by so ftware.

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4.3.1 SREG – Status Register

Bit 76543210

Read/Write R/W R/W R/WR/WR/WR/WR/WR/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

ATtiny13A

I T H S V N Z C SREG

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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ATtiny13A

4.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order t o achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10

Registers R17 0x11

7 0 Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2 on page 10, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3 on page 11.

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ATtiny13A

Figure 4-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7070

R31 (0x1F) R30 (0x1E)

In the different addressing modes these addr ess regist er s have fun cti ons a s fi xed d isp lacement , automatic increment, and automatic decrement (see the instruction set reference for details).

4.5 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is imp lemented as growing f rom higher memor y locations to lower memory locations. This implies that a Stack PUSH co mmand decr eases th e Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM is automaticall defined to the last address in SRAM during power on reset. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

4.5.1 SPL - Stack Pointer Low.

Bit 151413121110 9 8

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value10011111

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

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ATtiny13A

4.6 Instruction Execution Timing

T1 T2 T3 T4

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled

by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MH z with the correspo nding unique results for function s per cost, functions per clocks, and functions per power-unit.

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

clk

CPU

, directly generated from the selected clock source for the

CPU

Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock

cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 4-5. Single Cycle ALU Operation

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

4.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one toge ther with the Glo bal Interru pt Enable bit in the Status Register in order to enable the int errupt.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45. The list also determines the priority levels of the different interrupts. The lower the address the higher is the

clk

CPU

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ATtiny13A

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Int errupt Flags. If the interrup t condition disappears before t he interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt rou tine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

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Note: See “Code Examples” on page 6.

ATtiny13A

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Note: See “Code Examples” on page 6.

4.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the a ctual interru pt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in ad dition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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5. Memories

This section describes the different memories in the ATtiny13A. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny13A features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

5.1 In-System Reprogrammable Flash Program Memory

The ATtiny13A contains 1K byt e On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x

16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13A Pro-

gram Counter (PC) is nine bits wide, thus addressing the 512 Program m emory locations.

“Memory Programming” on page 103 contains a detailed description on Flash data serial down-

loading using the SPI pins. Constant tables can be allocated within the entire Prog ram memory address space (se e the

LPM – Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

ATtiny13A

Figure 5-1. Program Memory Map

5.2 SRAM Data Memory

Figure 5-2 on page 16 shows how the ATtiny13A SRAM Memory is organized.

The lower 160 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 64 locations addr ess the internal data SRAM.

The five different addressing modes for the Data memory cover: Dire ct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

Program Memory

0x0000

0x01FF

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The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations f rom the base address given

by the Y- or Z-register.

ATtiny13A

When using register indirect addressing modes with automatic pre-decrement and post-incre-

T1 T2 T3

Read

Write

ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data

SRAM in the ATtiny13A are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10.

Figure 5-2. Data Memory Map

Data Memory

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Figure 5-3. On-chip Data SRAM Access Cycles

clk

CPU

ddress

Data

32 Registers

64 I/O Registers

Internal SRAM

(64 x 8)

Compute Address

0x0000 - 0x001F 0x0020 - 0x005F 0x0060

0x009F

cycles as described in Figure 5-3.

CPU

Address valid

5.3 EEPROM Data Memory

The ATtiny13A contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see page 106.

Memory Access Instruction

Next Instruction

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5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEARL Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 5-1 on page 21. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations.

ATtiny13A

is likely to rise or fall slowly on Power-up/down. This causes the

5.3.3 Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations whe n the system allows doing time-critical operations (typically after Power-up).

5.3.4 Erase

To erase a byte, the address must be written to EEARL. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 5-1 on page 21). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations.

5.3.5 Write

To write a location, the user must write the address into EEARL and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 5-1 on page 21). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations.

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ATtiny13A

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on

page 27.

The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r17) in address register

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0>>EEPM0)

/* Set up address and data registers */

EEARL = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

Note: See “Code Examples” on page 6.

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ATtiny13A

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r17) in address register

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEARL = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

Note: See “Code Examples” on page 6.

5.3.6 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

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, the EEPROM data can be corrupted because the supply voltage is

reset protection circuit can

ATtiny13A

5.4 I/O Memory

The I/O space definition of the ATtiny13A is shown in “Register Summary” on page 157. All ATtiny13A I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instr uctions, transferring data be tween the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In th ese re gisters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresse s.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

5.5 Register Description

5.5.1 EEARL – EEPROM Address Register

Bit 76543210

– – EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X X X X X

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 5:0 – EEAR[5:0]: EEPROM Address

The EEPROM Address Register – EEARL – specifies the EEPROM address in the 64 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. The initial value of EEARL is undefined. A proper value must be written before the EEPROM may be accessed.

5.5.2 EEDR – EEPROM Data Register

Bit 76543210

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEARL.

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5.5.3 EECR – EEPROM Control Register

Bit 76543210

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny13A. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny13A and will always read as zero.

• Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in on e atomic operation (e rase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1 on page 21. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

ATtiny13A

Table 5-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

Time Operation

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the

selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

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ATtiny13A

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEARL Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEARL Register.

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6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consump tion, th e cloc ks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 30. The clock systems are detailed below.

Figure 6-1. Clock Distribution

ATtiny13A

ADC

clk

ADC

General I/O

Modules

clk

I/O

External Clock

AVR Clock

Control Unit

Source clock

Clock

Multiplexer

CPU Core RAM

clk

CPU

clk

FLASH

Reset Logic

Flash and EEPROM

Watchdog Timer

Watchdog clock

Watchdog

Oscillator

Calibrated RC

Oscillator

6.1.1 CPU Clock – clk

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority o f the I/O modules, like T imer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

6.1.3 Flash Clock – clk

The Flash clock controls operation of the Flash inte rface. The Fla sh clock is usually active simultaneously with the CPU clock.

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CPU

FLASH

ATtiny13A

6.1.4 ADC Clock – clk

6.2 Clock Sources

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion results.

The device has the following clock source options, selectable by Flash fuse bits as shown below. The clock from the selected so ur ce is i npu t to th e AVR clo c k gene ra to r, and r ou te d to t he appropriate modules.

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL1:0

External Clock (see page 24)00 Calibrated Internal 4.8/9.6 MHz Oscillator (see page 25)01, 10 Internal 128 kHz Oscillator (see page 26)11

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-

(1)

6.2.1 External Clock

Table 6-2. Number of Watchdog Oscillator Cycles

Typ Time-out Number of Cycles

4 ms 512

64 ms 8K (8,192)

To drive the device from an extern al cloc k source, CLKI should be driven as shown in Figure 6-

2. To run the device on an external clock, the CKSEL fuses must be programmed to “00”.

Figure 6-2. External Clock Drive Configuration

EXTERNAL

CLOCK

CLKI

SIGNAL

GND

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ATtiny13A

When this clock source is selected, start-up times ar e dete rmin ed by the SUT fuses as shown in

Table 6-3.

Table 6-3. Start-up Times for the External Clock Selection

Start-up Time from

SUT1..0

00 6 CK 14CK BOD enabled 01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 Reserved

Power-down and Power-save

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-ti me changes of the int ernal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

26 for details.

6.2.2 Calibrated Internal 4.8/9.6 MHz Oscillator

The calibrated internal oscillator provides a 4.8 or 9.6 MHz clock source. The frequency is nominal at 3V and 25°C. If the frequency exceeds the specification of the device (depends on V the CKDIV8 fuse must be programmed so that the internal clock is divided by 8 during start-up.

See “System Clock Prescaler” on page 26. for more details.

Additional Delay

from Reset

Recommended

Usage

The internal oscillator is selected as the system clock by programming the CKSEL fuses as shown in Table 6-4. If selected, it will operate with no external components.

Table 6-4. Internal Calibrated RC Oscillator Operating Modes

CKSEL1..0 Nominal Frequency

(1)

01 4.8 MHz

Note: 1. The device is shipped with this option selected.

9.6 MHz

During reset, hardware loads the calibration data into the OSCCAL register and thereby automatically calibrates the oscillator. There are separate calibration bytes for 4.8 and 9.6 MHz operation but only one is automatically loaded during reset (see section “Calibration Bytes” on

page 105). This is because the only difference between 4.8 MHz and 9.6 MHz mode is an inter-

nal clock divider. By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 27, it is possible to get a higher calibration accuracy than by using the factory calibration.

See “Calibrated Internal RC Oscillator Accuracy” on page 119. When this oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Bytes” on page 105.

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ATtiny13A

When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 6-5.

Table 6-5. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1..0

00 6 CK 14CK BOD enabled 01 6 CK 14CK + 4 ms Fast rising power

(1)

11 Reserved

Note: 1. The device is shipped with this option selected.

6.2.3 Internal 128 kHz Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the system clock by programming the CKSEL fuses to “11”.

When this clock source is selected, start-up times ar e dete rmin ed by the SUT fuses as shown in

Table 6-6.

Table 6-6. Start-up Times for the 128 kHz Internal Oscillator

SUT1:0

00 6 CK 14CK BOD enabled

Start-up Time

from Power-down

6 CK 14CK + 64 ms Slowly rising power

Start-up Time from

Power-down and Power-save

Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

Additional Delay

from Reset

Recommended

Usage

01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 Reserved

6.2.4 Default Clock Source

The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 9.6 MHz with longest startup time and an initial system clock prescaling of 8. Th is defau lt se tting ensure s th at all us ers can make their desired clock source setting using an In-System or High-voltage Programmer.

6.3 System Clock Prescaler

The ATtiny13A system clock can be divided by setting the “CLKPR – Clock Prescale Register”

on page 28. This feature can be used to decrease power consumption when the requiremen t for

processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk are divided by a factor as shown in Table 6-8 on page 28.

6.3.1 Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

I/O

, clk

ADC

, clk

CPU

, and clk

FLASH

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The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

6.4 Register Description

6.4.1 OSCCAL – Oscillator Calibration Register

Bit 76543210

– CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 Device Specific Calibration Value

• Bit 7 – Res: Reserved Bit

This bit is reserved bit in ATtiny13A and it will always read zero.

ATtiny13A

• Bits 6:0 – CAL[6:0]: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writ ing non-zero value s to this register will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives the highest available frequency.

The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 9.6 MHz or

4.8 MHz. Tuning to other values is not guaranteed, as indica ted in Table 6-7 below. To ensure stable operation of the MCU t he calibration value shou ld be ch anged in small steps. A

variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency

Table 6-7. Internal RC Oscillator Frequency Range

Typical Lowest Frequency

OSCCAL Value

0x00 50% 100% 0x3F 75% 150% 0x7F 100% 200%

with Respect to Nominal Frequency

Typical Highest Frequency

with Respect to Nominal Frequency

8126A–AVR–05/08

ATtiny13A

6.4.2 CLKPR – Clock Prescale Register

Bit 7 6 5 4 3 2 1 0

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R /W R/W R/W Initial Value 0 0 0 0 See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Selec t Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to t he MCU, the speed o f all synchronous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-8 on page 28.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure t he write procedur e is not interrupted.hee setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 fuse programmed.

Table 6-8. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128

1000 256

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ATtiny13A

Table 6-8. Clock Prescaler Select (Continued)

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved

8126A–AVR–05/08

ATtiny13A

7. Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

7.1 Sleep Modes

Figure 6-1 on page 23 presents the different clock systems in the ATtiny13A, and their distribu-

tion. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up sources.

Table 7-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock Domains Oscillators Wake-up Sources

Sleep Mode

Idle X X X X X X X X ADC Noise

Reduction Power-down X

Note: 1. For INT0, only level interrupt.

CPU

clk

FLASH

clk

ADC

clk

XXX

Main Clock

Source Enabled

INT0 and

Pin Change

(1)

SPM/

EEPROM

Ready

ADC

Other I/O

Watchdog

XX X

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction. See Table 7-2 on page 34 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from slee p. I f a r eset occurs d uri ng sle ep mode, the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 46 for details.

Interrupt

7.1.1 Idle Mode

When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

CPU

and clk

FLASH

, while

allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well a s internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

8126A–AVR–05/08

Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

7.1.2 ADC Noise Reduction Mode

When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU ent er ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clk while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is e ntered. Apart fo rm the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

7.1.3 Power-down Mode

When the SM[1:0] bits are written to 10, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchd og Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only.

ATtiny13A

I/O

, clk

, and clk

CPU

FLASH

7.2 Software BOD Disable

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 17-3 on page

104), the BOD is actively monitoring the supply voltage during a sleep period. It is possible to

save power by disabling the BOD by software in Power-Down sleep mode. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.

If BOD is disabled by software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the V

When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60µs to ensure that the BOD is working correctly before the MCU continues executing code.

BOD disable is controlled by the BODS (BOD Sleep) bit of BOD Control Register, see “BODCR

– Brown-Out Detector Control Register” on page 33. Writing this bit to one turns off BOD in

Power-Down and Stand-By, while writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see “BODCR –

Brown-Out Detector Control Register” on page 33.

7.3 Po wer Reduction Register

The Power Reduction Register (see “PRR – Power Reduction Register” on page 34) provides a method to reduce power consumption by stopping the clock to individual peripherals. The current state of the peripheral is frozen and the I/O registers can not be read or written. When stopping the clock resources used by the peripheral will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module (by clearing the bit in PRR) puts the module in the same state as before shutdown.

level has dropped during the sleep period.

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ATtiny13A

Modules can be shut down in Idle and Active modes, significantly helping to reduce the overall power consumption. In all other sleep modes, the clock is already stopped. See “Supply Current

of I/O Modules” on page 125 for examples.

7.4 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

7.4.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 82 for details on ADC operation.

7.4.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Ana log Compar ator” on page 79 for de tails o n how to co nfigure the Analog Comparator.

7.4.3 Brown-out Detector

If the Brown-out Detector is not needed in the ap plication, this module should be turne d off. If the Brown-out Detector is enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumpt ion. See “Brown-out Detection” on page 37 and “Software BOD Dis-

able” on page 31 for details on how to configure the Brown-out Detector.

7.4.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 38 for details on the start-up time.

7.4.5 Watchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Interrupts” on page 45 for details on how to configure the Watchdog Timer.

8126A–AVR–05/08

7.4.6 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk

) and the ADC clock (clk

I/O

will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 53 for details on which pins are enabled. If the input buffer is enab led and the in put sig nal is le ft fl oati ng or ha s an analog signal level close to V

/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V

/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to

“DIDR0 – Digital Input Disable Register 0” on page 81 for details.

7.5 Register Description

7.5.1 BODCR – Brown-Out Detector Cont rol Register

The BOD Control Register contains control bits for disabling the BOD by software.

Bit 76543210

— — — — — — BODS BODSE MCUCR Read/WriteRRRRRRR/WR/W Initial Value 0 0 0 0 0 0 0 0

ATtiny13A

) are stopped, the input buffers of the device

ADC

• Bit 1 – BODS: BOD Sleep

In order to disable BOD during sleep the BODS bit must be writte n to logic one. This is contr olled by a timed sequence and the enable bit, BODSE. First, both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.

• Bit 0 – BODSE: BOD Sleep Enable

The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by a timed sequence.

7.5.2 MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management .

Bit 76543210

Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when th e SLEEP instruction is executed. To avoid the MCU enteri ng th e sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) b it to one just befor e the exe cution of the SLEEP instruction and to clear it immediately after waking up.

— PUD SE SM1 SM0 — ISC01 ISC00 MCUCR

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ATtiny13A

• Bits 4:3 – SM[1:0]: Sleep Mode Select Bit s 1:0

These bits select between the three available sleep modes as shown in Table 7-2 on page 34.

Table 7-2. Sleep Mode Select

SM1 SM0 Sleep Mode

00Idle 0 1 ADC Noise Reduction 1 0 Powe r-down 11Reserved

• Bit 2 – Res: Reserved Bit

This bit is reserved in ATtiny13A and will always read as zero.

7.5.3 PRR – Power Reduction Register

The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock signals to be disabled.

Bit 76543 210

————— —PRTIM0PRADC PRR

Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 7:2

— Res: Reserved Bits

These bits are reserved and will always read as zero.

•Bit 1

— PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

•Bit 0

— PRADC: Power Reduction ADC

Writing a logic one to this bit shuts do wn the ADC. The ADC mu st be disabled b efore shut down. The analog comparator cannot be used when the ADC is shut down.

8126A–AVR–05/08

8. System Control and Reset

]

8.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 on page 35 shows the reset logic. “System and

Reset Characteristics” on page 120 defines the electrical parameters of the reset circuitry.

Figure 8-1. Reset Logic

Power-on Reset

Circuit

DATA BU S

MCU Status

BORF

PORF

WDRF

EXTRF

ATtiny13A

BODLEVEL [1..0]

Pull-up Resistor

SPIKE

FILTER

Brown-out

Reset Circuit

Watchdog

Oscillator

Clock

Generator

CKSEL[1:0]

SUT[1:0

Delay Counters

TIMEOUT

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL fuses. The different selections for the delay period are presented in “Clock Sources” on page 24.

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ATtiny13A

8.2 Reset Sources

RESET

8.2.1 Power-on Reset

The ATtiny13A has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V

• External Reset. The MCU is reset when a low level is present on the RESET

POT

pin for longer

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V Reset threshold (V

) and the Brown-out Detector is enabled.

BOT

is below the Brown-out

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 120. The POR is activated whenever V

is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as

well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reac hing the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V

decreases below the detection level.

rise. The RESET signal is activated again, without any delay,

TOUT

Tied to V

Figure 8-2. MCU Start-up, RESET

RESET

IME-OUT

NTERNAL

POT

RST

Figure 8-3. MCU Start-up, RESET Extended Externally

RESET

IME-OUT

POT

RST

TOUT

NTERNAL

RESET

8126A–AVR–05/08

8.2.2 External Reset

ATtiny13A

An External Reset is generated by a low level on the RESET than the minimum pulse width (See “System and Reset Characteristics” on page 120.) will gen- erate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V edge, the delay counter starts the MCU afte r the Time-out period – t

Figure 8-4. External Reset During Operation

pin if enabled. Reset pulses longer

– on its positive

RST

has expired.

TOUT –

8.2.3 Brown-out Dete ction

ATtiny13A has an On-chip Brown-out Detection (BOD) circuit for mo nitor ing the V operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection le vel should be int erpreted as V and V

When the BOD is enabled, and V

8-5 on page 37), the Brown-out Reset is immediately activated. When V

trigger level (V out period t

The BOD circuit will only detect a drop in V longer than t

Figure 8-5. Brown-out Reset During Operation

BOT-

= V

- V

BOT

BOT+

has expired.

TOUT

given in “System and Reset Characteristics” on page 120.

BOD

RESET

/2.

HYST

decreases to a value below the trigger level (V

in Figure 8-5 on page 37), the delay counter starts the MCU after the Time-

if the voltage stays below the trigger level for

BOT-

BOT+

level during

= V

BOT+

increases above the

BOT

BOT-

+ V

in Figure

HYST

IME-OUT

NTERNAL

RESET

TOUT

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ATtiny13A

8.2.4 Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

“Interrupts” on page 45 for details on operation of the Watchdog Timer.

Figure 8-6. Watchd og R eset Du rin g Op er a tion

TOUT

. Refer to

8.3 Internal Voltage Reference

ATtiny13A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.3.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. T he start-up time is given in “System and Reset Characteristics” on page 120. To save power, the reference is not always turned on. The reference is on during the following situations:

• When the BOD is enabled (by programming the BODLEVEL [1..0] fuse).

• When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

• When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

8.4 Watchdog Timer

ATtiny13A has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out

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ATtiny13A

value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.

Figure 8-7. Watchdog Timer

128kHz

OSCILLATOR

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

WATCHDOG RESET

OSC/512K

OSC/128K

OSC/256K

OSC/1024K

WDP0 WDP1 WDP2 WDP3

WDE

WDTIF

WDTIE

MCU RESET

INTERRUPT

In Interrupt mode, the WDT gives an interrupt when the time r expires. This int errupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, th e WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDTIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)

and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next f our clock cycles , write the WDE and W atchdog pr escaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

8126A–AVR–05/08

ATtiny13A

The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.

Assembly Code Example

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in r16, MCUSR

andi r16, (0xff - (1<<WDRF))

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

in r16, WDTCR

ori r16, (1<<WDCE) | (1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

; Turn on global interrupt

sei

ret

C Code Example

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

__enable_interrupt();

}

Note: See “Code Examples” on page 6.

If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-ou t resets. To avo id this situ a-

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ATtiny13A

tion, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.

Assembly Code Example

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in r16, WDTCR

ori r16, (1<<WDCE) | (1<<WDE)

out WDTCR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

out WDTCR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed sequence */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

Note: See “Code Examples” on page 6.

The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period.

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ATtiny13A

8.5 Register Description

8.5.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit 76543210

Read/WriteRRRRR/WR/WR/WR/W Initial Value0000 See Bit Description

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

––––WDRFBORFEXTRFPORFMCUSR

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a r eset condition, t he user should r ead and t hen reset

the MCUSR as early as possible in the prog ram. If the register is cle ared before anot her reset occurs, the source of the reset can be found by examining the Reset Flags.

8.5.2 WDTCR – Watchdog Timer Control Register

Bit 76543210

WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0

• Bit 7 - WDTIF: Watchdog Timer Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDTIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDTIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDTIE: Watchdog Timer Interrupt Enable

When this bit is written to one and the I-bit in the Status Re gister is set, the Wa tchdog Interr upt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDTIF. Executing the corresponding interrupt vector will clear WDTIE and WDTIF automatically by hardware (the Watchdog goes to System Reset Mode).

8126A–AVR–05/08

ATtiny13A

This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Inte rrupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not be done within the interrupt service r outine itsel f, as this might compr omise the safety-funct ion of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.

Table 8-1. Watchdog Timer Configuration

WDTON

(1)

1 0 0 Stopped None 1 0 1 Interrupt Mode Interrupt 1 1 0 System Reset Mode Reset

WDE WDTIE Mode Action on Time-out

111

0 x x System Reset Mode Reset

Note: 1. WDTON fuse set to “0“ means programmed and “1“ means unprogrammed.

Interrupt and System Reset Mode

Interrupt, then go to System Reset Mode

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensur es multiple reset s during co nditions causing failure, and a safe start-up after the failure.

• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in

Table 8-2 on page 43..

Table 8-2. Watchdog Timer Prescale Select

8126A–AVR–05/08

Number of WDT Oscillator

WDP3 WDP2 WDP1 WDP0

0000 2K (2048) cycles 16 ms 0001 4K (4096) cycles 32 ms 0010 8K (8192) cycles 64 ms 0011 16K (16384) cycles 0.125 s 0100 32K (32768) cycles 0.25 s 0101 64K (65536) cycles 0.5 s 0110 128K (131072) cycles 1.0 s 0111 256K (262144) cycles 2.0 s 1000 512K (524288) cycles 4.0 s 10011024K (1048576) cycles 8.0 s

Cycles

Typical Time-out at

VCC = 5.0V

ATtiny13A

Table 8-2. Watchdog Timer Prescale Select (Continued)

WDP3 WDP2 WDP1 WDP0

1010 1011 1100 1101 1110 1111

Number of WDT Oscillator

Cycles

Reserved

Typical Time-out at

VCC = 5.0V

8126A–AVR–05/08

9. Interrupts

This section describes the specifics of the interrupt handling as performed in ATtiny13A. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on

page 12.

9.1 Interrupt Vectors

The interrupt vectors of ATtiny13A are described in Table 9-1 below.

Table 9-1. Reset and Interrupt Vectors

Vector No. Program Address Source Interrupt Definition

ATtiny13A

1 0x0000 RESET

2 0x0001 INT0 External Interrupt Request 0 3 0x0002 PCINT0 Pin Change Interrupt Request 0 4 0x0003 TIM0_OVF Timer/Counter Overflow 5 0x0004 EE_RDY EEPROM Ready 6 0x0005 ANA_COMP Analog Comparator 7 0x0006 TIM0_COMPA Timer/Counter Compare Match A 8 0x0007 TIM0_COMPB Timer/Counter Compare Match B 9 0x0008 WDT Watchdog Time-out

10 0x0009 ADC ADC Conversion Complete

External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset

If the program never enables an interr upt sou rce, the I nter rupt Vect ors ar e n ot used , and regu lar program code can be placed at these locations.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny13A is:

Address Labels Code Comments

0x0000 rjmp RESET ; Reset Handler

0x0001 rjmp EXT_INT0 ; IRQ0 Handler

0x0002 rjmp PCINT0 ; PCINT0 Handler

0x0003 rjmp TIM0_OVF ; Timer0 Overflow Handler

0x0004 rjmp EE_RDY ; EEPROM Ready Handler

0x0005 rjmp ANA_COMP ; Analog Comparator Handler

0x0006 rjmp TIM0_COMPA ; Timer0 CompareA Handler

0x0007 rjmp TIM0_COMPB ; Timer0 CompareB Handler

0x0008 rjmp WATCHDOG ; Watchdog Interrupt Handler

0x0009 rjmp ADC ; ADC Conversion Handler

;

0x000A RESET: ldi r16, low(RAMEND); Main program start

0x000B out SPL,r16 ; Set Stack Pointer to top of RAM

0x000C sei ; Enable interrupts

0x000D <instr> xxx

... ... ... ...

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ATtiny13A

9.2 External Interrupts

The External Interrupts are triggered by the INT0 pin or any of the PCINT5 ..0 pins. Obser ve that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT5..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 23.

9.2.1 Low Level Interrupt

A low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power -down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as described in

“System Clock and Clock Options” on page 23.

If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command.

9.2.2 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 9-1 below.

Figure 9-1. Timing of pin change interrupts

PCINT(0)

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

cint_setflag

pin_lat

D Q

clk

pin_sync

PCINT(0) in PCMSK(x)

pcint_in_(0)

0 x

clk

pcint_syn

pcint_setflag

PCIF

8126A–AVR–05/08

9.3 Register Description

9.3.1 MCUCR – MCU Control Register

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 76543210

Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value00000000

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2 on page 47. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

Table 9-2. Interrupt 0 Sense Control

ISC01 ISC00 Description

ATtiny13A

– PUD SE SM1 SM0 – ISC01 ISC00 MCUCR

0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.

9.3.2 GIMSK – General Interrupt Mask Register

Bit 76543210

–INT0PCIE–––––GIMSK Read/WriteRR/WR/WRRRRR Initial Value00000000

• Bits 7, 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The I nterrupt Sen se Control0 bits 1/ 0 (ISC0 1 and ISC0 0) in the MCU Control Register (MCUCR) define whether the exter nal inter rupt is activate d on r ising and/ or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.

8126A–AVR–05/08

• Bit 5 – PCIE: Pin Change Interrupt Enable

When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one) , pin change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK Register.

ATtiny13A

9.3.3 GIFR – General Interrupt Flag Register

Bit 76543210

–INTF0PCIF–––––GIFR Read/WriteRR/WR/WRRRRR Initial Value00000000

• Bits 7, 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrup t requ est, INTF0 be comes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT5:0 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

9.3.4 PCMSK – Pin Change Mask Register

Bit 76543210

– – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 5:0 – PCINT5:0: Pin Change Enable Mask 5:0

Each PCINT5:0 bit selects whether pin change interrupt is enabled on the correspond ing I/O pin. If PCINT5:0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT5:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

8126A–AVR–05/08

10. I/O Ports

10.1 Overview

ATtiny13A

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/ disabling of p ull-up resist ors (if con figured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

acteristics” on page 117 for a complete list of parameters.

Figure 10-1. I/O Pin Equivalent Schematic

and Ground as indicated in Figure 10-1. Refer to “Electrical Char-

Pxn

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” rep resents the bit number. However, when using the register or bit defines in a program , the precise form must be used. For examp le, PORTB3 for bit no. 3 in Port B, here documented ge ner ally as PO RTxn . The physical I /O Registers and bit locations are listed in “Register Description” on page 57.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

50. Most port pins are multiplexed with alternate func tions for the peripheral featur es on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 54. Refer to the individual module sections for a full description of the alter-

nate functions.

See Figure

"General Digital I/O" for

Logic

Details

8126A–AVR–05/08

ATtiny13A

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 on page 50 shows a functional description of one I/O-port pin, here generically called Pxn.

Figure 10-2. General Digital I/O

Pxn

SLEEP

(1)

SYNCHRONIZER

DLQ

PUD

DDxn

CLR

RESET

WDx

RDx

PORTxn

CLR

DATA BU S

RESET

WRx

RRx

RPx

PINxn

WPx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

10.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description” on page 57, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL

: I/O CLOCK

clk

I/O

SLEEP, and PUD are common to all ports.

clk

I/O

WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER

8126A–AVR–05/08

I/O

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin h as to be configured as an output pin. The port pi ns are tri-stated when re set condition b ecomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

10.2.2 Toggli ng the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

10.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.

ATtiny13A

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-sta te ({DDxn, PORTxn} = 0b00) o r the o utput high state ({DDxn, PORTxn} = 0b10) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

Table 10-1. Port Pin Configurations

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-stat e (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source)

10.2.4 Reading the Pin Value

Independent of the setting of Data Direction b it DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2 on page 50, the PINxn Register bit a nd th e pr eceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 on

page 52 shows a timing diagram of the synchronization when reading an externally applied pin

value. The maximum and minimum propaga tion delays are denoted t respectively.

PUD

(in MCUCR) I/O Pull-up Comment

pd,max

and t

pd,min

8126A–AVR–05/08

ATtiny13A

Figure 10-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

XXX in r17, PINx

XXX

SYNC LATCH

PINxn

r17

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4 on page 52. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period.

0x00 0xFF

pd, max

pd, min

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16

INSTRUCTIONS

out PORTx, r16 nop in r17, PINx

0xFF

SYNC LATCH

PINxn

r17

0x00 0xFF

8126A–AVR–05/08

ATtiny13A

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. T he resulting pin values are read back again, but as previously discussed, a nop i nstruction is in cluded to be able t o read back the value recently assigned to some of the pins.

Assembly Code Example

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB4)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

(1)

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Note: See “Code Examples” on page 6.

10.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 10-2 on page 50, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analo g signa l level close to V

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 54.

8126A–AVR–05/08

/2.

ATtiny13A

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the extern al interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

10.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure t hat these pins have a defi ned level. Even though most of the digital inputs are disabled in th e deep sleep modes as de scribed above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5 shows how port pin control signals from th e sim plified Figu re 10 -2 on page 50 can be overridden by alternate functions.

or GND is not recommended, since this may caus e excessiv e currents if t he pin is

Figure 10-5. Alternate Port Functions

Pxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

PUOExn

PUOVxn

DDOExn

DDOVxn

PVOExn

PVOVxn

DIEOExn

DIEOVxn

SLEEP

PUD

DDxn

CLR

RESET

PORTxn

CLR

RESET

SYNCHRONIZER

SET

DLQ

PINxn

CLR

PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx

: I/O CLOCK

clk

I/O

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

WDx

RDx

RRx

RPx

clk

DIxn

AIOxn

PTOExn

WRx

I/O

WPx

DATA BU S

Note: WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

and PUD are common to all ports. All other signals are unique for each pin.

8126A–AVR–05/08

, SLEEP,

I/O

ATtiny13A

The overriding signals may not be present in all port pins, but Figure 10-5 serves as a generic description applicable to all port pins in the AVR microcontroller family.

Table 10-2 on page 55 summarizes the functio n of the overriding signals. The pin and port

indexes from Figure 10-5 on page 54 are not shown in the succ eeding tables. The overriding signals are generated internally in the modules having the alternate function.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

Pull-up Override Enable

Pull-up Override Value

Data Direction Override Enable

Data Direction Override Value

Port Value Override Enable

Port Value Override Value

Port Toggle Override Enable

Digital Input Enable Override Enable

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

DIEOV

DI Digital Input

AIO Analog Input/Output

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

10.3.1 Alternate Functions of Port B

The Port B pins with alternate function are shown in Table 10-3 on page 56.

8126A–AVR–05/08

Digital Input Enable Override Value

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer . Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/Output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally.

ATtiny13A

Table 10-3. Port B Pins Alternate Functions

Port Pin Alternate Function

RESET

: Reset Pin

PB5

PB4

PB3

PB2

PB1

PB0

dW: debugWIRE I/O ADC0: ADC Input Channel 0 PCINT5:Pin Change Interrupt, Source 5

ADC2: ADC Input Channel 2 PCINT4:Pin Change Interrupt 0, Source 4

CLKI: External Clock Input ADC3: ADC Input Channel 3 PCINT3:Pin Change Interrupt 0, Source 3

SCK: Serial Clock Input ADC1: ADC Input Channel 1 T0: Timer/Counter0 Clock Source. PCINT2:Pin Change Interrupt 0, Source 2

MISO: SPI Master Data Input / Slave Data Output AIN1: Analog Comparator, Negative Input OC0B: Timer/Counter0 Compare Match B Output INT0: External Interrupt 0 Input PCINT1:Pin Change Interrupt 0, Source 1

MOSI:: SPI Master Data Output / Slave Data Input AIN0: Analog Comparator, Positive Input OC0A: Timer/Counter0 Compare Match A output PCINT0:Pin Change Interrupt 0, Source 0

Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 54.

Table 10-4. Overriding Signals for Alternate Functions in PB5:PB3

Signal PB5/RESET/ADC0/PCINT5 PB4/ADC2/PCINT4 PB3/ADC3/CLKI/PCINT3

(1)

PUOE RSTDISBL

• DWEN PUOV100 DDOE RSTDISBL

(1)

• DWEN DDOV debugWire T ransmit 0 0 PVOE000 PVOV000 PTOE000

(1)

DIEOE

RSTDISBL PCIE + ADC0D)

+ (PCINT5 •

DIEOV ADC0D ADC2D ADC3D DI PCINT5 Input PCINT4 Input PCINT3 Input AIO RESET Input, ADC0 Input ADC2 Input ADC3 Input

Note: 1. 1 when the fuse is “0” (Programmed).

(1)

PCINT4 • PCIE + ADC2D PCINT3 • PCIE + ADC3D

8126A–AVR–05/08

Table 10-5. Overriding Signals for Alternate Functions in PB2:PB0

ATtiny13A

Signal Name

PUOE000 PUOV000 DDOE 0 0 0 DDOV 0 0 0 PVOE 0 OC0B Enable OC0A Enable PVOV 0 OC0B OC0A PTOE000 DIEOE PCINT2 • PCIE + ADC1D PCINT1 • PCIE + AIN1D PCINT0 • PCIE + AIN0D DIEOV ADC1D AIN1D AIN0D

AIO ADC1 Input

10.4 Register Description

PB2/SCK/ADC1/ T0/PCINT2

T0/INT0/ PCINT2 Input

PB1/MISO/AIN1/ OC0B/INT0/PCINT1

PB0/MOSI/AIN0/ AREF/OC0A/PCINT0

PCINT1 Input PCINT0 Input

Analog Comparator Negative Input

Analog Comparator Positive Input

10.4.1 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0

–PUD Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 7, 2– Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 6 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 50 for more details about this feature.

10.4.2 PORTB – Port B Data Register

Bit 76543210

– – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

10.4.3 DDRB – Port B Data Direction Register

Bit 76543210

––

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

SE SM1 SM0 – ISC01 ISC00 MCUCR

DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

8126A–AVR–05/08

ATtiny13A

10.4.4 PINB – Port B Input Pins Address

Bit 76543210

––

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 N/A N/A N/ A N/A N/A N/A

PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

8126A–AVR–05/08

11. 8-bit Timer/Counter0 with PWM

11.1 Features

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

11.2 Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate progr am execution timing (event management) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 11-1 on page 59. For the actual placement of I/O pins, refer to “Pinout ATtiny13A” on page 2 . CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 70.

ATtiny13A

Figure 11-1. 8-bit Timer/Counter Block Diagram

Count

Clear

Direction

Timer/Counter

TCNTn

Control Logic

TOP BOTTO M

OCRnA

Fixed

TOP

Val ue

DATA B U S

OCRnB

clk

= 0

TOVn

(Int.Req.)

Clock Select

Edge

Detector

( From Prescaler )

OCnA

(Int.Req.)

Wavefo rm

Generation

OCnB

(Int.Req.)

Wavefo rm

Generation

OCnA

OCnB

8126A–AVR–05/08

TCCRnA TCCRnB

ATtiny13A

11.2.1 Registers

11.2.2 Definitions

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A an d OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interr upts are individ ually masked with the Timer Inte rrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via th e prescaler, or b y an external clo ck source on the T0 pin. The Clock Select logic block controls which clock source a nd edge the Tim er/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk

The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 61. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compa re interrupt request.

Many register and bit references in this section are written in genera l form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in Table 11-1 on page 60 are also used extensively throughout the document. Table 11-1. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest valu e in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation.

11.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B) . For details o n clock sources and p rescaler, see “Timer/Counter Prescaler” on page 77.

11.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

11-2 shows a block diagram of the counter and its surroundings.

8126A–AVR–05/08

Figure 11-2. Counter Unit Block Diagram

DATA BUS

count

TCNTn Control Logic

clear

direction

TOVn

(Int.Req.)

clk

ATtiny13A

Clock Select

Edge

Detector

( From Prescaler )

bottom

top

Signal description (internal signals):

count Incr em e nt or de cre m en t TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk

Timer/Counter clock, referred to as clkT0 in the following.

top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk

). clkT0 can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk

is present or not. A CPU write overrides (has priority over) all counter clear or

count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see “Modes of Opera-

tion” on page 64.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

11.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is aut om atica lly cleare d wh en the int errup t is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compa re Outpu t mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 64.).

Figure 11-3 on page 62 shows a block diagram of the Output Compare unit.

8126A–AVR–05/08

ATtiny13A

Figure 11-3. Output Compare Unit, Block Diagram

DATA BUS

WGMn1:0

COMnX1:0

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

The OCR0x Registers are double buffered when using any o f the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Comp are (CTC) mode s of oper ation, the do uble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the doub le buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.

Waveform Generator

OCnx

11.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled).

11.5.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an inte rrupt when the Timer/Counte r clock is enabled.

11.5.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the va lue written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform

8126A–AVR–05/08

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their valu es even when changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately.

11.6 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two funct ions. The Wavefor m Generato r uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 11-4 on page 6 3 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.

ATtiny13A

Figure 11-4. Compare Match Output Unit, Schematic

COMnx1

COMnx0 FOCn

Waveform

Generator

OCnx

PORT

DATA BU

DDR

clk

I/O

OCn

8126A–AVR–05/08

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independen t of the Waveform Generation mode.

ATtiny13A

The design of the Output Compare pin logic allows initialization of the OC0x state befor e the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 70.

11.6.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits diff erently in Nor mal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 11- 2 on page 70. For fast PWM mode, r efer to Table 11-3 on

page 71, and for phase correct PWM refer to Table 11-4 on page 71.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.

11.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Gen eration mode (WGM02:0) and Comp are Output mode (COM0x1:0) bits. The Compare Output mode bits do no t affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1: 0 bits control wheth er the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See “Compare Match Output Unit” on page 63.).

For detailed timing information refer to Figure 11-8 on page 69, Figure 11-9 on page 69, Figure

11-10 on page 69 and Figure 11-11 on page 70 in “Timer/Counter Timing Diagrams” on page

68.

11.7.1 Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to ge nerate int errupts at some given time . Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

11.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero wh en the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting exte rn al ev en ts.

8126A–AVR–05/08

ATtiny13A

O (

---

The timing diagram for the CTC mode is shown in Figure 11-5 on page 65. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0 A, and then counter (TCNT0) is cleared.

Figure 11-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

CNTn

Toggle)

eriod

1 4

2 3

(COMnx1:0 = 1)

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Co mpare Match can occur.

For generating a waveform output in CT C mod e, the O C0A outp ut can be set to t oggle it s logica l level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f f

/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

clk_I/O

OC0

equation:

OCnx

-----------------------------------------------

2 N 1 OCRnx+()⋅⋅

clk_I/O

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same tim er clock cycle tha t the

counter counts from MAX to 0x00.

11.7.3 Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non inverting Compare Output mode, the Out put Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mo de can be twice as high as the phase co rrect PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

8126A–AVR–05/08

ATtiny13A

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-6 on page 66. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slop es represent Compare Matches between OCR0x and TCNT0.

Figure 11-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Se

OCRnx Update and TOVn Interrupt Flag Set

CNTn

eriod

2 3

4 5 6 7

(COMnx1:0 = 2)

(COMnx1:0 = 3)

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the AC0A pin to toggle on Compare Matches if the WGM02 bit is set . T his opt ion is not ava ilable for the OC0B pin (See Table 11-3 on page 71). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output . Th e PWM wa vef orm is g ene rate d by setting (or clearing) the OC0x Register a t the Comp are Ma tch between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

clk_I/O

OCnxPWM

------------------=

N 256⋅

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Regis ter represe nts specia l cases when generat ing a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

8126A–AVR–05/08

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each C ompare Match (COM 0x1:0 = 1). The wavefo rm generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

11.7.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non inverting Compare Output mode, the Out put Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while downcounting. In inverting Output Compar e mod e, the operat ion is in verted . The dual-s lope o peration has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

OC0

= f

ATtiny13A

/2 when OCR0A is set to zero. This

clk_I/O

In phase correct PWM mode the counter is increme nted until the counter valu e matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 11-7 on page 67. The TCNT0 value is in the timing diagram show n as a h i st og ra m fo r illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.

Figure 11-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

8126A–AVR–05/08

OCn

Period

(COMnx1:0 = 2)

(COMnx1:0 = 3)

1 2 3

ATtiny13A

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTT OM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inve rted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Tab le 11-4 on page 71). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is se t as o ut put. Th e PWM wa vef orm is generated by clearing (or setting) the OC0x Register at the Compare Mat ch between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements. Th e PWM frequency for the output when using phase correct PWM can be calculated by the following equation:

OCnxPCPWM

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If th e OCR0A is set equal to BOTTOM , the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

clk_I/O

------------------=

N510⋅

At the very start of period 2 in Figure 11-7 on page 67 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value fr om MAX, like in Figu re 11-7 on page 67. When the OCR0A v alue is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Matc h.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that wou ld have happened on the way up.

11.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. Th e figures include information on whe n Interrupt Flags are set. Figure 11-8 on page 69 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

8126A–AVR–05/08

ATtiny13A

Figure 11-8. Timer/Counter Timing Diagram, no Prescaling

clk

I/O

clk

(clk

/1)

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

Figure 11-9 shows the same timing data, but with the prescaler enabled.

Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f

clk

I/O

clk

(clk

/8)

I/O

TCNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk_I/O

/8)

TOVn

Figure 11-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

Figure 11-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f

clk

I/O

clk

(clk

/8)

I/O

TCNTn

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk_I/O

/8)

8126A–AVR–05/08

OCRnx

OCRnx Value

OCFnx

Figure 11-11 on page 70 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode

and fast PWM mode where OCR0A is TOP.

ATtiny13A

Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

clk

I/O

clk

(clk

/8)

I/O

TCNTn

(CTC)

caler (f

/8)

clk_I/O

TOP - 1 TOP BOTTOM BOTTOM + 1

OCRnx

OCFnx

11.9 Register Description

11.9.1 TCCR0A – Timer/Counter Control Register A

Bit 7 6 5 4 3 210

COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A

Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 7:6 – COM01A:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal por t function ality of th e I/O pin it is conne cted to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting.

Table 11-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or

CTC mode (non-PWM).

TOP

Table 11-2. Compare Output Mode, non-PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on Compare Match 1 0 Clear OC0A on Compa r e Match 1 1 Set OC0A on Compa r e Match

Table 11-3 on page 71 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to

fast PWM mode.

8126A–AVR–05/08

ATtiny13A

Table 11-3. Compare Output Mode, Fast PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0A disconnected.

1 0 Clear OC0A on Compare Match, set OC0A at TOP 1 1 Set OC0A on Compare Match, clear OC0A at TOP

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 65 for more details.

WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match.

(1)

Table 11-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 11-4. Compare Output Mode, Phase Correct PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match.

Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting.

Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting.

(1)

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 67 for more details.

• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal por t function ality of th e I/O pin it is conne cted to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting.

Table 11-5 on page 72 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to

a normal or CTC mode (non-PWM).

8126A–AVR–05/08

ATtiny13A

Table 11-5. Compare Output Mode, non-PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0B disconnected. 0 1 Toggle OC0B on Compare Match 1 0 Clear OC0B on Compa r e Match 1 1 Set OC0B on Compa r e Match

Table 11-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Table 11-6. Compare Output Mode, Fast PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0B disconnected. 01Reserved 1 0 Clear OC0B on Compare Match, set OC0B at TOP 1 1 Set OC0B on Compare Match, clear OC0B at TOP

Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 65 for more details.

(1)

Table 11-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 11-7. Compare Output Mode, Phase Correct PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0B disconnected. 01Reserved

Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting.

(1)

Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 67 for more details.

Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

8126A–AVR–05/08

ATtiny13A

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 11-8 on page 73. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation ” on page 64).

Table 11-8. Waveform Generation Mode Bit Des crip tio n

Timer/Counter Mode of

Mode WGM2 WGM1 WGM0

0 0 0 0 Normal 0xFF Immediate MAX

1001

2010CTC OCRAImmediateMAX 3 0 1 1 Fast PWM 0xFF TOP MAX 4100Reserved – – –

5101

Operation TOP

PWM (Phase Correct)

0xFF TOP BOTTOM

OCRA TOP BOTTOM

Update of

OCRx at

TOV Flag

Set on

(1)(2)

6110Reserved – – – 7 1 1 1 Fa st PWM OCRA TOP TOP

Notes: 1. MAX = 0xFF

2. BOTTOM = 0x00

11.9.2 TCCR0B – Timer/Counter Control Register B

Bit 7 6 5 4 3 210

FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B

Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.

8126A–AVR–05/08

The FOC0A bit is always read as zero.

ATtiny13A

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “TCCR0A – Timer/Counter Control Register A” on page 70.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 11-9. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped) 001clk 010clk 011clk 100clk 101clk 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.

11.9.3 TCNT0 – Timer/Counter Register

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

/(No prescaling)

I/O

/8 (From prescaler)

I/O

/64 (From prescaler)

I/O

/256 (From prescaler)

I/O

/1024 (From prescaler)

I/O

TCNT0[7:0] TCNT0

8126A–AVR–05/08

11.9.4 OCR0A – Output Compare Register A

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to ge nerate an Output Compare interru pt, or to generate a waveform output on the OC0A pin.

11.9.5 OCR0B – Output Compare Register B

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to ge nerate an Output Compare interru pt, or to generate a waveform output on the OC0B pin.

11.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register

Bit 76543210

– – – – OCIE0B OCIE0A TOIE0 – TIMSK0 Read/Write R R R R R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0

ATtiny13A

OCR0A[7:0] OCR0A

OCR0B[7:0] OCR0B

• Bits 7:4, 0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The correspondin g interrupt is ex ecuted if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.

• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Ma tch A interrupt is enabled. The co rr esponding interrupt is execute d if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer /Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TO V0 bit is set in the Timer/Cou nter 0 Interrupt Flag Register – TIFR0.

8126A–AVR–05/08

ATtiny13A

11.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register

Bit 76543210

––––OCF0BOCF0A Read/Write R R R R R/W R/W R/W R Initial Value00000000

• Bits 7:4, 0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs betwee n the Timer/Count er and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hard ware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 2 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is clear ed by hardware when e xecuting the co rresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

TOV0 –TIFR0

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

The setting of this flag is dependent of the WGM 02:0 b it settin g. Re fer to Table 11 -8, “Waveform

Generation Mode Bit Description” on page 73.

8126A–AVR–05/08

12. Timer/Counter Prescaler

12.1 Overview

The Timer/Counter can be clocked directly by the syst em clo ck (by se tting t he CSn2:0= 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f clock source. The prescaled clock has a frequency of either f f

/1024.

CLK_I/O

12.2 Prescaler Reset

The prescaler is free running, i.e., operates independently of t he Clock Select logic of the Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enable d and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clo ck cycles from when t he timer is ena bled to the f irst count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution.

ATtiny13A

). Alternatively, one of four taps from the prescaler can be used as a

CLK_I/O

/8, f

CLK_I/O

/64, f

CLK_I/O

/256, or

12.3 External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Cou nter clo ck (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detecto r. Figure 12-1 on page 7 7 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock ( parent in the high period of the internal system clock.

The edge detector generates one clk = 6) edge it detects.

Figure 12-1. T0 Pin Sampling

clk

I/O

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated.

clk

). The latch is trans-

I/O

pulse for each positive (CSn2:0 = 7) or negat ive (CSn2 :0

DQDQ

Edge DetectorSynchronization

Tn_sync

(To Clock Select Logic)

8126A–AVR–05/08

Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Count er clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f

ExtClk

< f

/2) given a 50/50% duty cycle. Since the edge detec tor uses

clk_I/O

ATtiny13A

sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f

clk_I/O

/2.5.

An external clock source can not be prescaled.

Figure 12-2. Prescaler for Timer/Counter0

clk

I/O

PSR10

Synchronization

Clear

Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 12-1 on page 77.

12.4 Register Description.

12.4.1 GTCCR – General Timer/Counter Control Register

Bit 7 6 5 4 3 2 1 0

TSM Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mo de. In th is m o de , th e value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting.

• Bit 0 – PSR10: Prescaler Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.

– – – – – – PSR10 GTCCR

clk

8126A–AVR–05/08

13. Analog Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and nega tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator . The user can select Inter rupt trig gering on compar ator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 13-1 on page 79.

Figure 13-1. Analog Comparator Block Diagram

BANDGAP

REFERENCE

ATtiny13A

ACBG

ACME ADEN

ADC MULTIPLEXER

OUTPUT

(1)

See Figure 1-1 on page 2, Table 10-5 o n p age 57 , and ator pin placement.

13.1 Analog Comparator Multiplexed Input

It is possible to select any of the ADC3..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1:0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table

13-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator.

Table 13-1. Analog Comparator Multiplexed Input

ACME ADEN MUX1..0 Analog Comparator Negative Input

0x xxAIN1 11 xxAIN1 1 0 00 ADC0 1 0 01 ADC1

Table 13-2 on page 81 for Analog Compar-

8126A–AVR–05/08

1 0 10 ADC2 1 0 11 ADC3

ATtiny13A

13.2 Register Description

13.2.1 ADCSRB – ADC Control and Status Register

Bit 76543210

– ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R R/W R R R R/W R/W R/W Initial Value00000000

• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 79.

13.2.2 ACSR– Analog Comparator Control and Status Register

Bit 76543210

ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 ACSR Read/Write R/W R/W R R/W R/W R R/W R/W Initial Value00N/A00000

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switche d off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is ap plied to the positive input of the Analog Comparator. When the bandgap reference is used as input to the Analog Comparator, it will take certain time for the voltage to stabilize. If not stabilized, the first value may give a wrong value.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bi t in the Status Re gister is set, the Analo g Comparator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny13A and will always read as zero.

8126A–AVR–05/08

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that t rigger the Analog Comparator inte rrupt. The different settings are shown in Table 13-2 on page 81.

Table 13-2. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle. 01Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Outp ut Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Regist er. Othe rwise an interru pt can occur whe n the bits are changed.

13.2.3 DIDR0 – Digital Input Disable Register 0

Bit 76543210

– – ADC3D ADC2D ADC1D ADC0D AIN1D AIN0D DIDR0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value00000000

ATtiny13A

• Bits 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital inp ut buff er on the AIN1 /0 pin is disa bled. The corr esponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.

8126A–AVR–05/08

ATtiny13A

14. Analog to Digital Converter

14.1 Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

• ± 2 LSB Absolute Accuracy

• 13 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• Four Multiplexed Single Ended Input Channels

• Optional Left Adjustment for ADC Result Readout

• 0 - V

• Selectable 1.1V ADC Reference Voltage

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

14.2 Overview

The ATtiny13A features a 10-bit successive approximation ADC. A block diagram of the ADC is shown in Figure 14-1.

Figure 14-1. Analog to Digital Converter Block Schematic

ADC Input Voltage Range

ADC CONVERSION

COMPLETE IRQ

ADC3

ADC2

ADC1

ADC0

8-BIT DATA BUS

INTERNAL 1.1V

REFERENCE

INPUT

MUX

REFS1

ADC MULTIPLEXER

SELECT (ADMUX)

MUX1

ADLAR

MUX DECODER

CHANNEL SELECTION

MUX0

ADIF

ADC CTRL. & STATUS

ADEN

ADSC

ADIF

ADATE

10-BIT DAC

ADTS[2:0]

ADIE

ADPS0

ADPS1

ADPS2

PRESCALER

CONVERSION LOGIC

INTERRUPT

FLAGS

15 0

ADC DATA REGISTER

(ADCH/ADCL)

TRIGGER

SELECT

START

SAMPLE & HOLD COMPARATOR

ADC MULTIPLEXER OUTPUT

ADC[9:0]

8126A–AVR–05/08

14.3 Operation

ATtiny13A

The ADC is connected to a 4-channel Analog Multiplexer which allows four single-end ed voltage inputs constructed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. Internal reference voltages of nominally 1.1V or V are provided On-chip.

The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on V

or an internal 1.1V reference voltage.

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, can be selected as single ended inputs to the ADC.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage referen ce and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before enterin g power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more tha n 8-bit precision is required , it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conve rsion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.

14.4 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a differe nt da ta channe l is se lected wh ile a conver sion is in progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (se e descri ption of t he ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrup t Enable b it in SREG is cleared. A conve rsion can thus be triggered without causing an interrupt. Howeve r, the Inter rupt Flag must be cleared in order to trigger a new conversion at the next interrupt event.

8126A–AVR–05/08

ATtiny13A

Figure 14-2. ADC Auto Trigger Logic

ADC CLOCK SOURCE

A S

ADIF SOURCE 1

. . . .

SOURCE n

DSC

ADTS[2:0]

START

ADATE

EDGE

DETECTOR

PRESCALER

CLK

CONVERSION

LOGIC

ADC

Using the ADC Interrupt Flag as a trigger source makes the ADC star t a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The firs t conversion must be star ted by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progre ss. The ADSC bit will be read as one during a conversion, independently of how the conversion was started.

14.5 Prescaling and Conversion Timing

By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

Figure 14-3. ADC Prescaler

DEN TART

ADPS0 ADPS1 ADPS2

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

Reset

7-BIT ADC PRESCALER

CK/2

CK/4

CK/8

CK/16

CK/32

CK/64

CK/128

8126A–AVR–05/08

ATtiny13A

Update

Complete

One Conversion Next Conversion

Update

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry, as shown in Figure 14-4 below.

Figure 14-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

ycle Number

DC Clock

DEN

DSC

DIF

DCH

DCL

1 2121314 15

MUX and REFS

First Conversion

16 17

Sample & Hold

18 19 20 21 22 23

Conversion

24 25

Conversion

1 2

Sign and MSB of Result

LSB of Result

MUX and REF

When the bandgap reference voltage is used as input to the ADC, it will take a certain time for the voltage to stabilize. If not stabilized, the first value read after the first conversion may be wrong.

The actual sample-and-hold takes place 1.5 ADC clock cycles aft er t he sta rt of a no rma l con version and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

Figure 14-5. ADC Timing Diagram, Single Conversion

2 3 4 5 6 7 8

ycle Number

DC Clock

DSC

DIF

DCH

8126A–AVR–05/08

DCL

Sample & Hold

MUX and REFS

9 10 11 12 13

Conversion

Complete

Sign and MSB of Result

LSB of Result

MUX and REF Update

ATtiny13A

When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in

A T

One Conversion Next Conversion

Update

Figure 14-6 below. This assures a fixed delay from the trigger event to th e start of conversion. In

this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchro nization logic.

Figure 14-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion Next Conversio

ycle Number

DC Clock

rigger

ource

DATE

DIF

DCH

DCL

Prescaler Reset

1 2 3 4 5 6 7 8

Sample &

MUX and REFS Update

Hold

10 11 12 13

Conversion

Complete

Sign and MSB of Resul

LSB of Result

Prescaler Reset

In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high.

Figure 14-7. ADC Timing Diagram, Free Running Conversion

ycle Number

11 12 13

DC Clock

DSC

DIF

DCH

DCL

Conversion

Complete

Sign and MSB of Result

LSB of Result

Sample & Ho

MUX and REFS

8126A–AVR–05/08

For a summary of conversion times, see Table 14-1.

Table 14-1. ADC Conversion Time

Condition

First conversion 13.5 25 Normal conversions 1.5 13 Auto Triggered conversions 2 13.5

14.6 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is sta rted. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling t ime for th e ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on th e following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or refere nce select ion values to ADMUX until one ADC clock cycle after ADSC is written.

ATtiny13A

Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles)

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways:

• When ADATE or ADEN is cleared.

• During conversion, minimum one ADC clock cycle after the trigger event.

• After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.

14.6.1 ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion t o complete bef ore changin g the ch annel selectio n.

In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection.

8126A–AVR–05/08

ATtiny13A

14.6.2 ADC Voltage Reference

The reference voltage for the ADC (V ended channels that exceed V either V voltage source may be inaccurate, and the user is advised to discard this result.

14.7 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. Th e noise canceler can be use d with ADC Noise Reduction and Idle mode. To mak e us e of this feat ure, the fo llowing pr oced ure sh ould be used:

• Make sure tha t the ADC is enabled and is no t busy con verting. Single Conv ersion mode must be selected and the ADC conversion complete interrupt must be enabled.

• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.

• If no other interrupts occur before the ADC conv ersion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If an othe r int errupt wakes up the CPU before the ADC con version is complete, the interrupt will be ex ecuted, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.

) indicates the conversion range for the ADC. Single

REF

will result in codes close to 0x3FF. V

REF

, or internal 1.1V reference. The first ADC conversion result after switching reference

can be selected as

REF

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption.

14.8 Analog Input Circuitry

The analog input circuitry for single ended channels is shown in Figure 14-8 An analog source applied to ADCn is subjected to pin capacitance and input leakage of that pin, regardless if the channel is chosen as input for the ADC, or not. When the channel is selected, the source drives the S/H capacitor through the series resistance (combined resistance in input path).

Figure 14-8. Analog Input Circuitry

1..100 kohm

= 14 pF

S/H

Note: The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and

any stray or parasitic capacitance inside the device. The value given is worst case.

8126A–AVR–05/08

ATtiny13A

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible. If a sour ce with hig her impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.

Signal components higher than the Nyquist frequenc y (f distortion from unpredictable signal convolution. The user is advised to remove high frequ ency components with a low-pass filter before applying the signals as inputs to the ADC.

14.9 Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. When conversion accuracy is critical, the noise level can be reduced by applying the following techniques:

• Keep analog signal paths as short as possible.

• Make sure analog tracks run ov er the analog ground plane.

• Keep analog tracks well away from high-speed switching digital tracks.

• If any port pin is used as a digital output, it mustn’t switch while a conver sion is in progress.

• Place bypass capacitors as close to V

Where high ADC accuracy is required it is recommended to u se ADC Noise Redu ction Mo de, as described in Section 14.7 on page 88. This is especially the case when system clock frequency is above 1 MHz. A good system design with properly placed, external bypass capacitors does reduce the need for using ADC Noise Reduction Mode

14.10 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the highest code is read as 2

/2) should not be present to avoid

ADC

and GND pins as possible.

-1.

in 2n steps

REF

8126A–AVR–05/08

Several parameters describe the deviation from the ideal behavior:

ATtiny13A

• Offset: The deviation of the first transition (0x000 to 0x001 ) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB.

Figure 14-9. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

Input Voltage

REF

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB

Figure 14-10. Gain Error

Output Code

Gain

Error

REF

Ideal ADC

Actual ADC

Input Voltage

8126A–AVR–05/08

ATtiny13A

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.

Figure 14-11. Integral Non-linearity (INL)

Output Code

INL

Ideal ADC

Actual ADC

• Diffe rential Non-linearity (DNL): The maxim um de viation of t he actual code width (the int erval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 14-12. Differential Non-linearity (DNL)

REF

Input Voltage

Output Code

0x3FF

1 LSB

DNL

0x000

8126A–AVR–05/08

REF

Input Voltage

ATtiny13A

• Quantization Error: Due to the quantization of the input v oltage int o a finite n umbe r of codes , a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.

• Absolute Accuracy: The maxim um de viation of an actu al (unadjusted ) tra nsition compared to an ideal transition for any code. This is the compound effect of offset, gain error, dif ferential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.

14.11 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH).

For single ended conversion, the result is

ADC

1024⋅

--------------------------=

REF

where V

is the voltage on the selected input pin and V

Table 14-2 on page 92 and Table 14-3 on page 93). 0x000 represents analog ground, and

0x3FF represents the selected reference voltage minus one LSB.

14.12 Register Description

14.12.1 ADMUX – ADC Multiplexer Selection Register

Bit 76543210

– REFS0 ADLAR – – – MUX1 MUX0 ADMUX Read/Write R R/W R/W R R R R/W R/W Initial Value00000000

• Bit 7 – Res: Reserved Bit

This bit is reserved bit in the ATtiny13A and will always read as zero.

• Bit 6 – REFS0: Reference Selection Bit

This bit selects the voltage reference for the ADC, as shown in Table 14-2. If this bit is changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).

Table 14-2. Voltage Reference Selections for ADC

REFS0 Voltage Reference Selection

the selected voltage reference (see

REF

0V 1 Internal Voltage Reference.

•

Bit 5 – ADLAR: ADC Left Adjust Result

used as analog reference.

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Other wise, the r esult is righ t adju sted. Chan ging the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on

page 94.

8126A–AVR–05/08

• Bits 4:2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 1:0 – MUX1:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 14-3 on page 93 for details. will not go in effect until this conversion is complete (ADIF in ADCSRA is set).

Table 14-3. Input Channel Selections

MUX1..0 Single Ended Input

00 ADC0 (PB5) 01 ADC1 (PB2) 10 ADC2 (PB4) 11 ADC3 (PB3)

14.12.2 ADCSRA – ADC Control and Status Register A

Bit 76543210

ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

ATtiny13A

If these bits are changed during a conversion, t he change

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start ea ch conversion. In Free Ru nning mode, write this bit to one to start the first conver sion. The f irst con version aft er ADSC has bee n written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit ha s no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion comple tes and t he data reg iste rs ar e upd at ed. Th e ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

8126A–AVR–05/08

ATtiny13A

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and t he I- bit in SREG is set, the ADC Conversion Complete Interrupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and th e inpu t clock to the ADC.

Table 14-4. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor

000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128

14.12.3 ADCL and ADCH – The ADC Data Register

14.12.3.1 ADLAR = 0

14.12.3.2 ADLAR = 1

Bit 151413121110 9 8

––––––ADC9 ADC8 ADCH

ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 151413121110 9 8

ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH

ADC1 ADC0 ––––––ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.

8126A–AVR–05/08

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the resu lt is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 92.

14.12.4 ADCSRB – ADC Control and Status Register B

Bit 76543210

– Read/Write R R/W R R R R/W R/W R/W Initial Value00000000

ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB

• Bits 7, 5:3 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set

ATtiny13A

Table 14-5. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 T rigger Source

0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer/Counter Compare Match A 1 0 0 Timer/Counter Overflow 1 0 1 Timer/Counter Compare Match B 1 1 0 Pin Change Interrupt Request

14.12.5 DIDR0 – Digital Input Disable Register 0

Bit 76543210

– – ADC3D ADC2D ADC1D ADC0D AIN1D AIN0D DIDR0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 5:2 – ADC3D:ADC0D: ADC3:0 Digital Input Disable

When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.

8126A–AVR–05/08

ATtiny13A

15. debugWIRE On-chip Debug System

15.1 Features

• Complete Program Flow Control

• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin

• Real-time Operation

• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

• Unlimited Number of Program Break Points (Using Software Break Points)

• Non-intrusive Operation

• Electrical Characteristics Identical to Real Device

• Automatic Configuration System

• High-Speed Operation

• Programming of Non-volatile Memories

15.2 Overview

The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different non-volatile memories.

15.3 Physical Interface

When the debugWIRE Enable (DWEN) fuse is programmed and lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator.

Figure 15-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator

connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL fuses.

Figure 15-1. The debugWIRE Setup

1.8 - 5.5

VCC

dW(RESET)

GND

8126A–AVR–05/08

When designing a system where debugWIRE will be used, the following must be observed:

• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional.

• Connecting the RESET pin directly to V

• Capacitors inserted on the RESET pin must be disconnected when using debugWire.

• All external reset sources must be disconnected.

15.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio tion replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the program.

The Flash must be re-programmed each time a Break Point is changed. This is automatically handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore reduce the Flash Data retention. Devices used for debu gging pur poses should not be shipp ed to end customers.

ATtiny13A

will not work.

will insert a BREAK instruction in the Program memory. The instruc-

15.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is enabled.

The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O Registers via the debugger (AVR Studio). See the debugWIRE documentation for detailed description of the limitations.

The debugWIRE interface is asynchronous, which means that the debugger needs to synchronize to the system clock. If the system clock is changed by software (e.g. by writing CLKPS bits) communication via debugWIRE may fail. Also, clock frequencies below 100 kHz may cause communication problems.

A programmed DWEN fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN fuse should be disabled when debugWire is not used.

15.6 Register Description

The following section describes the registers used with th e de bu g Wire .

15.6.1 DWDR –debugWire Data Register

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

DWDR[7:0] DWDR

8126A–AVR–05/08

The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations.

ATtiny13A

16. Self-Programming the Flash

The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”).

The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, th e rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re -written. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write fe at ure which allo ws t he user sof t ware to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the P age Er ase and Page Write operation is addressing the same page.

16.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.

Note: The CPU is halted during the Page Erase operation.

16.2 Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buff er.

8126A–AVR–05/08

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.

16.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.

Note: The CPU is halted during the Page Write operation.

16.4 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Bit 151413121110 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7Z6Z5Z4Z3Z2Z1Z0

76543210

Since the Flash is organized in pages (see Table 17-5 on page 105), the Program Counter can be treated as having two different sections. One section , consisting of the least signifi cant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 16-1. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation.

ATtiny13A

Figure 16-1. Addressing the Flash During SPM

BIT

Z - REGISTER

PROGRAM MEMORY

PROGRAM COUNTER

PAGE ADDRESS WITHIN THE FLASH

PAG E

ZPCMSB

PCMSB

ZPAGEMSB

PAGEMSB

PCWORDPCPAGE

(1)

0115

WORD ADDRESS WITHIN A PAGE

INSTRUCTION WORD

PAG E

PCWORD[PAGEMSB:0]:

PAGEEND

8126A–AVR–05/08

Note: 1. The variables used in Figure 16-1 are listed in Table 17-5 on page 105.

ATtiny13A

The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z- po in te r is used .

16.5 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the fuses and lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register.

16.6 Reading Fuse and Lock Bits from Firmware

It is possible to read fuse and lock bits from software.

16.6.1 Reading Lock Bits from Firmware

Issuing an LPM instruction within three CPU cycles after RFLB and SELFPRGEN bits have been set in SPMCSR will return lock bit values in the destination register. The RFLB and SELFPRGEN bits automatically clear upon completion of read ing the lock bit s, or if no L PM instruction is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles. When RFLB and SELFPRGEN are cleared, LPM functions normally.

To read the lock bits, follow the below procedure.

1. Load the Z-pointer with 0x0001.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issuing an LPM instruction within three clock cycles will return lock bits in the destina-

tion register .

If successful, the contents of the destination register are as follows.

Bit 76543210 Rd ––––––LB2LB1

See section “Program And Data Memory Lock Bits” on page 103 for more information on lock bits.

16.6.2 Reading Fuse Bits from Firmware

The algorithm for reading fuse bytes is similar to the one described above for reading lock bits, only the addresses are different.

To read the Fuse Low Byte (FLB), follow the below procedure:

1. Load the Z-pointer with 0x0000.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issuing an LPM instruction within three clock cycles will FLB in the destination register.

If successful, the contents of the destination register are as follows.

Bit 76543210 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

100

8126A–AVR–05/08

ATMEL ATtiny13A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

1.1 Pin Descriptions

1.1.1 VCC

1.1.2 GND

1.1.3 Port B (PB5:PB0)

1.1.4 RESET

2. Overview

2.1 Block Diagram

3. About

3.1 Resources

3.2 Code Examples

3.3 Data Retention

4. CPU Core

4.1 Architectural Overview

4.3 Status Register

4.4 General Purpose Register File

4.4.1 The X-register, Y-register, and Z-register

4.5 Stack Pointer

4.5.1 SPL - Stack Pointer Low.

4.6 Instruction Execution Timing

4.7 Reset and Interrupt Handling

4.7.1 Interrupt Response Time

5. Memories

5.1 In-System Reprogrammable Flash Program Memory

5.2 SRAM Data Memory

5.2.1 Data Memory Access Times

5.3 EEPROM Data Memory

5.3.1 EEPROM Read/Write Access

5.3.2 Atomic Byte Programming

5.3.3 Split Byte Programming

5.3.4 Erase

5.3.5 Write

5.3.6 Preventing EEPROM Corruption

5.4 I/O Memory

5.5 Register Description

6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

6.2 Clock Sources

6.2.1 External Clock

6.2.2 Calibrated Internal 4.8/9.6 MHz Oscillator

6.2.3 Internal 128 kHz Oscillator

6.2.4 Default Clock Source

6.3 System Clock Prescaler

6.3.1 Switching Time

6.4 Register Description

7. Power Management and Sleep Modes

7.1 Sleep Modes

7.1.1 Idle Mode

7.1.2 ADC Noise Reduction Mode

7.1.3 Power-down Mode

7.2 Software BOD Disable

7.3 Po wer Reduction Register

7.4 Minimizing Power Consumption

7.4.1 Analog to Digital Converter

7.4.2 Analog Comparator

7.4.3 Brown-out Detector

7.4.4 Internal Voltage Reference

7.4.5 Watchdog Timer

7.4.6 Port Pins

7.5 Register Description

8. System Control and Reset

8.1 Resetting the AVR

8.2 Reset Sources

8.2.1 Power-on Reset

8.2.2 External Reset

8.2.3 Brown-out Dete ction

8.2.4 Watchdog Reset

8.3 Internal Voltage Reference

8.3.1 Voltage Reference Enable Signals and Start-up Time

8.4 Watchdog Timer

8.5 Register Description

9. Interrupts

9.1 Interrupt Vectors

9.2 External Interrupts

9.2.1 Low Level Interrupt