ATMEL ATtiny13A User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 120 Powe rful Instructions – Most Single Clock Cy cle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Througput at 20 MHz

• High Endurance Non-volatile Memory segments

– 1K Bytes of In-System Self-programmable Flash program memory – 64 Bytes EEPROM – 64 Bytes Internal SRAM – Write/Erase cyles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (see page 6) – Programming Lock for Self-Programming Flash & EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels – 4-channel, 10-bit ADC with Internal Voltage Reference – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator

• Special Microcontroller Features

– debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit with Software Disable Function – Internal Calibrated Oscillator

• I/O and Pac kages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines – 20-pad MLF: Six Programmable I/O Lines

• Operating Voltage:

– 1.8 - 5.5V

• Speed Grade:

– 0 - 4 MHz @ 1.8 - 5.5V – 0 - 10 MHz @ 2.7 - 5.5V – 0 - 20 MHz @ 4.5 - 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode:

• 190 µA at 1.8 V and 1 MHz

–Idle Mode:

• 24 µA at 1.8 V and 1 MHz

8-Bit Microcontroller

8-bit

Microcontroller with 1K Bytes In-System Programmable Flash

ATtiny13A

Rev. 8126A–AVR–05/08

ATtiny13A

1. Pin Configurations

Figure 1-1. Pinout ATtiny13A

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

8-PDIP/SOIC

1 2 3

GND

20-QFN/MLF

DNC

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

DNC

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC DNC

(PCINT4/ADC2) PB4

NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

(PCINT4/ADC2) PB4

GND

2019181716

1 2 3 4 5

DNC

GND

10-QFN/MLF

1 2 3 4 5

DNC

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

DNC

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect

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1.1 Pin Descriptions

1.1.1 VCC

Digital supply voltage.

1.1.2 GND

Ground.

1.1.3 Port B (PB5:PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny13A as listed on page

55.

1.1.4 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 18-4 on page

120. Shorter pulses are not guaranteed to gener at e a re se t.

ATtiny13A

The reset pin can also be used as a (weak) I/O pin.

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ATtiny13A

2. Overview

2.1 Block Diagram

The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS pe r MHz allow ing the sy stem de signer to optimize power c onsumption versus processing speed.

Figure 2-1. Block Diagram

8-BIT DATABUS

VCC

GND

INSTRUCTION

DECODER

CONTROL

LINES

STACK

POINTER

SRAM

PROGRAM

COUNTER

PROGRAM

FLASH

GENERAL

PURPOSE

REGISTERS

X Y Z

ALU

STATU S

WATCHDOG

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

MCU STATUS

TIMER/

COUNTER0

INTERRUPT

UNIT

PROGRAMMING

LOGIC

DATA

EEPROM

CALIBRATED

INTERNAL

TOR

OSCILLA

TIMING AND

CONTROL

ADC / ANALOG COMPARATOR

DATA REGISTER

PORT B

PORT B DRIVERS

PB0-PB5

DATA DIR.

REG.PORT B

RESET

CLKI

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ATtiny13A

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATtiny13A provides the following feat ures: 1K byte of In -System Programm able Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core.

The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.

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ATtiny13A

3. About

3.1 Resources

A comprehensive set of drivers, application notes, data sheet s and descr iption s on development tools are available for download at http://www.atmel.com/avr.

3.2 Code Examples

This documentation contains simple code examples t hat brief ly show h ow to us e various parts of the device. These code examples assume that the part specific header file is included b efore compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume ntation for more details.

3.3 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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4. CPU Core

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

4.1 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

ATtiny13A

Data Bus 8-bit

Flash

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Indirect Addressing

Status

and Control

32 x 8

General

Purpose

Registrers

ALU

Data

SRAM

Interrupt

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

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EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memo ry. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

ATtiny13A

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointe rs can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the AL U. After an arith metic operation, the Status Register is updated to reflect informat ion about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Prog ram Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.

4.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are execut ed . The ALU ope ra tio ns are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

4.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Refe rence. This wil l in many cases remove the n eed for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be hand le d by so ftware.

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4.3.1 SREG – Status Register

Bit 76543210

Read/Write R/W R/W R/WR/WR/WR/WR/WR/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

ATtiny13A

I T H S V N Z C SREG

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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ATtiny13A

4.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order t o achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10

Registers R17 0x11

7 0 Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2 on page 10, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3 on page 11.

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ATtiny13A

Figure 4-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7070

R31 (0x1F) R30 (0x1E)

In the different addressing modes these addr ess regist er s have fun cti ons a s fi xed d isp lacement , automatic increment, and automatic decrement (see the instruction set reference for details).

4.5 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is imp lemented as growing f rom higher memor y locations to lower memory locations. This implies that a Stack PUSH co mmand decr eases th e Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM is automaticall defined to the last address in SRAM during power on reset. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

4.5.1 SPL - Stack Pointer Low.

Bit 151413121110 9 8

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value10011111

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

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ATtiny13A

4.6 Instruction Execution Timing

T1 T2 T3 T4

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled

by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MH z with the correspo nding unique results for function s per cost, functions per clocks, and functions per power-unit.

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

clk

CPU

, directly generated from the selected clock source for the

CPU

Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock

cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 4-5. Single Cycle ALU Operation

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

4.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one toge ther with the Glo bal Interru pt Enable bit in the Status Register in order to enable the int errupt.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45. The list also determines the priority levels of the different interrupts. The lower the address the higher is the

clk

CPU

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ATtiny13A

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Int errupt Flags. If the interrup t condition disappears before t he interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt rou tine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

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Note: See “Code Examples” on page 6.

ATtiny13A

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Note: See “Code Examples” on page 6.

4.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the a ctual interru pt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in ad dition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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5. Memories

This section describes the different memories in the ATtiny13A. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny13A features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

5.1 In-System Reprogrammable Flash Program Memory

The ATtiny13A contains 1K byt e On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x

16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13A Pro-

gram Counter (PC) is nine bits wide, thus addressing the 512 Program m emory locations.

“Memory Programming” on page 103 contains a detailed description on Flash data serial down-

loading using the SPI pins. Constant tables can be allocated within the entire Prog ram memory address space (se e the

LPM – Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

ATtiny13A

Figure 5-1. Program Memory Map

5.2 SRAM Data Memory

Figure 5-2 on page 16 shows how the ATtiny13A SRAM Memory is organized.

The lower 160 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 64 locations addr ess the internal data SRAM.

The five different addressing modes for the Data memory cover: Dire ct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

Program Memory

0x0000

0x01FF

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The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations f rom the base address given

by the Y- or Z-register.

ATtiny13A

When using register indirect addressing modes with automatic pre-decrement and post-incre-

T1 T2 T3

Read

Write

ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data

SRAM in the ATtiny13A are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10.

Figure 5-2. Data Memory Map

Data Memory

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Figure 5-3. On-chip Data SRAM Access Cycles

clk

CPU

ddress

Data

32 Registers

64 I/O Registers

Internal SRAM

(64 x 8)

Compute Address

0x0000 - 0x001F 0x0020 - 0x005F 0x0060

0x009F

cycles as described in Figure 5-3.

CPU

Address valid

5.3 EEPROM Data Memory

The ATtiny13A contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see page 106.

Memory Access Instruction

Next Instruction

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5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEARL Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 5-1 on page 21. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations.

ATtiny13A

is likely to rise or fall slowly on Power-up/down. This causes the

5.3.3 Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations whe n the system allows doing time-critical operations (typically after Power-up).

5.3.4 Erase

To erase a byte, the address must be written to EEARL. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 5-1 on page 21). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations.

5.3.5 Write

To write a location, the user must write the address into EEARL and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 5-1 on page 21). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations.

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ATtiny13A

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on

page 27.

The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r17) in address register

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0>>EEPM0)

/* Set up address and data registers */

EEARL = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

Note: See “Code Examples” on page 6.

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ATtiny13A

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r17) in address register

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEARL = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

Note: See “Code Examples” on page 6.

5.3.6 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

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, the EEPROM data can be corrupted because the supply voltage is

reset protection circuit can

ATtiny13A

5.4 I/O Memory

The I/O space definition of the ATtiny13A is shown in “Register Summary” on page 157. All ATtiny13A I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instr uctions, transferring data be tween the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In th ese re gisters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresse s.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

5.5 Register Description

5.5.1 EEARL – EEPROM Address Register

Bit 76543210

– – EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X X X X X

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 5:0 – EEAR[5:0]: EEPROM Address

The EEPROM Address Register – EEARL – specifies the EEPROM address in the 64 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. The initial value of EEARL is undefined. A proper value must be written before the EEPROM may be accessed.

5.5.2 EEDR – EEPROM Data Register

Bit 76543210

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEARL.

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5.5.3 EECR – EEPROM Control Register

Bit 76543210

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny13A. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny13A and will always read as zero.

• Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in on e atomic operation (e rase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1 on page 21. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

ATtiny13A

Table 5-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

Time Operation

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the

selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

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ATtiny13A

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEARL Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEARL Register.

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6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consump tion, th e cloc ks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 30. The clock systems are detailed below.

Figure 6-1. Clock Distribution

ATtiny13A

ADC

clk

ADC

General I/O

Modules

clk

I/O

External Clock

AVR Clock

Control Unit

Source clock

Clock

Multiplexer

CPU Core RAM

clk

CPU

clk

FLASH

Reset Logic

Flash and EEPROM

Watchdog Timer

Watchdog clock

Watchdog

Oscillator

Calibrated RC

Oscillator

6.1.1 CPU Clock – clk

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority o f the I/O modules, like T imer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

6.1.3 Flash Clock – clk

The Flash clock controls operation of the Flash inte rface. The Fla sh clock is usually active simultaneously with the CPU clock.

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CPU

FLASH

ATtiny13A

6.1.4 ADC Clock – clk

6.2 Clock Sources

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion results.

The device has the following clock source options, selectable by Flash fuse bits as shown below. The clock from the selected so ur ce is i npu t to th e AVR clo c k gene ra to r, and r ou te d to t he appropriate modules.

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL1:0

External Clock (see page 24)00 Calibrated Internal 4.8/9.6 MHz Oscillator (see page 25)01, 10 Internal 128 kHz Oscillator (see page 26)11

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-

(1)

6.2.1 External Clock

Table 6-2. Number of Watchdog Oscillator Cycles

Typ Time-out Number of Cycles

4 ms 512

64 ms 8K (8,192)

To drive the device from an extern al cloc k source, CLKI should be driven as shown in Figure 6-

2. To run the device on an external clock, the CKSEL fuses must be programmed to “00”.

Figure 6-2. External Clock Drive Configuration

EXTERNAL

CLOCK

CLKI

SIGNAL

GND

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ATtiny13A

When this clock source is selected, start-up times ar e dete rmin ed by the SUT fuses as shown in

Table 6-3.

Table 6-3. Start-up Times for the External Clock Selection

Start-up Time from

SUT1..0

00 6 CK 14CK BOD enabled 01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 Reserved

Power-down and Power-save

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-ti me changes of the int ernal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

26 for details.

6.2.2 Calibrated Internal 4.8/9.6 MHz Oscillator

The calibrated internal oscillator provides a 4.8 or 9.6 MHz clock source. The frequency is nominal at 3V and 25°C. If the frequency exceeds the specification of the device (depends on V the CKDIV8 fuse must be programmed so that the internal clock is divided by 8 during start-up.

See “System Clock Prescaler” on page 26. for more details.

Additional Delay

from Reset

Recommended

Usage

The internal oscillator is selected as the system clock by programming the CKSEL fuses as shown in Table 6-4. If selected, it will operate with no external components.

Table 6-4. Internal Calibrated RC Oscillator Operating Modes

CKSEL1..0 Nominal Frequency

(1)

01 4.8 MHz

Note: 1. The device is shipped with this option selected.

9.6 MHz

During reset, hardware loads the calibration data into the OSCCAL register and thereby automatically calibrates the oscillator. There are separate calibration bytes for 4.8 and 9.6 MHz operation but only one is automatically loaded during reset (see section “Calibration Bytes” on

page 105). This is because the only difference between 4.8 MHz and 9.6 MHz mode is an inter-

nal clock divider. By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 27, it is possible to get a higher calibration accuracy than by using the factory calibration.

See “Calibrated Internal RC Oscillator Accuracy” on page 119. When this oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Bytes” on page 105.

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ATtiny13A

When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 6-5.

Table 6-5. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1..0

00 6 CK 14CK BOD enabled 01 6 CK 14CK + 4 ms Fast rising power

(1)

11 Reserved

Note: 1. The device is shipped with this option selected.

6.2.3 Internal 128 kHz Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the system clock by programming the CKSEL fuses to “11”.

When this clock source is selected, start-up times ar e dete rmin ed by the SUT fuses as shown in

Table 6-6.

Table 6-6. Start-up Times for the 128 kHz Internal Oscillator

SUT1:0

00 6 CK 14CK BOD enabled

Start-up Time

from Power-down

6 CK 14CK + 64 ms Slowly rising power

Start-up Time from

Power-down and Power-save

Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

Additional Delay

from Reset

Recommended

Usage

01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 Reserved

6.2.4 Default Clock Source

The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 9.6 MHz with longest startup time and an initial system clock prescaling of 8. Th is defau lt se tting ensure s th at all us ers can make their desired clock source setting using an In-System or High-voltage Programmer.

6.3 System Clock Prescaler

The ATtiny13A system clock can be divided by setting the “CLKPR – Clock Prescale Register”

on page 28. This feature can be used to decrease power consumption when the requiremen t for

processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk are divided by a factor as shown in Table 6-8 on page 28.

6.3.1 Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

I/O

, clk

ADC

, clk

CPU

, and clk

FLASH

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The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

6.4 Register Description

6.4.1 OSCCAL – Oscillator Calibration Register

Bit 76543210

– CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 Device Specific Calibration Value

• Bit 7 – Res: Reserved Bit

This bit is reserved bit in ATtiny13A and it will always read zero.

ATtiny13A

• Bits 6:0 – CAL[6:0]: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writ ing non-zero value s to this register will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives the highest available frequency.

The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 9.6 MHz or

4.8 MHz. Tuning to other values is not guaranteed, as indica ted in Table 6-7 below. To ensure stable operation of the MCU t he calibration value shou ld be ch anged in small steps. A

variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency

Table 6-7. Internal RC Oscillator Frequency Range

Typical Lowest Frequency

OSCCAL Value

0x00 50% 100% 0x3F 75% 150% 0x7F 100% 200%

with Respect to Nominal Frequency

Typical Highest Frequency

with Respect to Nominal Frequency

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ATtiny13A

6.4.2 CLKPR – Clock Prescale Register

Bit 7 6 5 4 3 2 1 0

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R /W R/W R/W Initial Value 0 0 0 0 See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Selec t Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to t he MCU, the speed o f all synchronous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-8 on page 28.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure t he write procedur e is not interrupted.hee setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 fuse programmed.

Table 6-8. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128

1000 256

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ATtiny13A

Table 6-8. Clock Prescaler Select (Continued)

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved

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ATtiny13A

7. Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

7.1 Sleep Modes

Figure 6-1 on page 23 presents the different clock systems in the ATtiny13A, and their distribu-

tion. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up sources.

Table 7-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock Domains Oscillators Wake-up Sources

Sleep Mode

Idle X X X X X X X X ADC Noise

Reduction Power-down X

Note: 1. For INT0, only level interrupt.

CPU

clk

FLASH

clk

ADC

clk

XXX

Main Clock

Source Enabled

INT0 and

Pin Change

(1)

SPM/

EEPROM

Ready

ADC

Other I/O

Watchdog

XX X

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction. See Table 7-2 on page 34 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from slee p. I f a r eset occurs d uri ng sle ep mode, the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 46 for details.

Interrupt

7.1.1 Idle Mode

When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

CPU

and clk

FLASH

, while

allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well a s internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

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