Asus z61ae Schematics
5
D D
4
3
2
1
Z61Ae SCHEMATIC V2.0
PAGE
SYSTEM PAGE REF.
4
DOTHAN CPU-1
5
DOTHAN CPU-2
6
CPU CAP & THERMAL SENSOR
7
ALVISO: CPU
8
ALVISO: DDR2 & DMI & PEG
ALVISO: DDR2
9
ALVISO: POWER & Caps
10
ALVISO: GND & NCTF & Straps
11
DDR2 SO-DIMM_0
12
DDR2 SO-DIMM_1
13
DDR2 ADDRESS TERMINATION
C C
B B
14
LVDS & INVERTER CONNECTOR
15
CRT
16
17
ICH6M--SATA/LPC/IDE/PM (1)
18
ICH6M--PCI/DMIUSB/PCIE (2)
19
ICH6M--PWR/GND(3)
20
ICH6M--PULL UP/STRAP (4)
21
CLOCK ICS954206
22
HDD & SWAP BAY CONN
23
USB PORTS
24
SUPER I/O LPC47N217
25
SCREW HOLE
PORT BAR 3
26
KBC 38857
27
SM BUS & POWER PORT
28
LAN-RTL8101L
29
RJ45 / RJ11
30
31
MINIPCI
PCI CARDBUS R5C841
32
33
PCI PCMCIA SOCKET A
PCI IEEE1394A & 3 IN1 CON
34
FAN CONTROL
35
FWH BIOS/Bluetooth Conn.
36
AUDIO CODEC ALC880
37
AUDIO_AMP_MB (TPA0212)
38
MIC AMP & MDC Conn.
39
40
LED BOARD
TP CONN
41
DISCHARGE MOS/EMI
42
Content
PAGE
POWER PAGE REF.
POWER-ON SEQUENCE
43
VCORE ADP3205
44
SYSTEM
45
2.5V & 1.5V & 1.8V & 1.05V
46
1.5VA & DDR2
47
PIC16C54/PWROK
48
49
BATCONN
50
CHARGER
BATLOW/SD#
51
52
LOAD SWITCH
53
+5VLCM
Content
Notice
The Z61Ae project code is ?
01
CON17/CON19 are SMT Level(SMT Request);DC Jack J6 is DIP Level.
02
CN1/J1/U23 are changed to DIP Level(They will drop in SMT reflow ).
03
J4 is changed to DIP.Due to it will broken in reflow.
Need to add ME and Power 59 level BOM in EE 60 BOM
04
Check FWH IC 05-001017122 in BOM.
05
Alviso U49 need to be changed to C1 version 02-010002640 (INTEL
06
ALVISO-GM SL8G2),second source is 02-010002610(C0 version)
AMI BIOS LABEL P/N:15-135001010.
07
It need to add in P/R 59-MID BOM by ME.
08
J2 need to be unmounted at PR stage for ATS power test
R501(255 ohm) 10G213255013010 need to add second source 10-003412515.
09
Add ACCL PCB Vendor 08-26ZA0020W???-->Need to create in SMT level.
10
Need add other PCB vendors by document manager.
All 0.01uF/25V/X7R (P/N:11-034110320) need to add 11-034110323
11
into second source.
MINIPCI Connector (P/N:12-023511240) need to add 12-023521243
12
into second source.
All CHIP RES. ARRAY 10 OHM(0402) 8R16P (P/N:10-124901000) need
13
to add 10-12490100A into second source.(ECR is NA12958)
If delete debug card function,R876 and R628 mount 0 ohm.
14
If use another power
15
switch method.D30 unmount.
If use another power
16
switch method.C616
mount 0.1uF/0402
A A
Title :
Z61AE PAGE REF.
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
157Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
Z61Ae: DOTHAN/ALVISO-GM BLOCK DIAGRAM
Main Battery is Li-ION 8 cells(4*2),16.8V(4.2V*4),4400mAH(2200mAH*2),65W(3.7V*4cell*4.4A) battery pack.
Second battery is Li-ION 6 cells(3*2),12.6V(4.2*3),3600mAH(1800mAH*2),40W(3.7V*3 cells*3.6A)battery pack.
BATTERY
D D
CLOCK
GEN.
ICS954206
PAGE 21
2 TYPE
3 X 2 &
4 X 2
PAGE 49
SWITCH BOARD CON
FUNCTION KEY
PAGE 40
LED
TOUCHPAD CONN
PAGE 41
Dothan
478 uFCPGA
LVDS &
INV.
PAGE 15
CRT
CONN
PAGE 16
TO PORT BAR3
CONN.
C C
B B
(FOR CRT)
PAGE 26
TO PORT BAR3
CONN.
(FROM USB
PORT2)
PAGE 26
TO BLUETOOTH
(FROM USB
PORT5)
R1.1-S01
PAGE 31
VCORE
SYSTEM
1.5V,1.8V,
1.05V,2.5V
CHARGE
PIC16C54
BATCON
PAGE 44
PAGE 45
PAGE 46
PAGE 50
PAGE 48,49
PAGE 22
SWITCH
PAGE 16
HDD
Master
PAGE 26
USB X4
PAGE 23
SATA TO PATA
SII3811CNU
PAGE 22
SUPER I/O
LPC47N217
PAGE 24
TO PORT BAR3
CONN.
(FOR LPT)
USB2.0
LPC, 33MHz
KEYBOARD
CONTROLLER
M3885XHP
PAGE 27
INTERNAL
KEYBOARD
PAGE 27
SWAP BAY
(HOT
PAGE 22
PLUG)
PAGE 4,5
PAGE 7,8,9,10,11
SATA BUS
PATA BUS
HOST BUS
AGTL
1.468V,133MHZ
ALVISO
Intel 915GM C1 version
1257 uFCBGA
DMI x4
ICH6-M
Intel ICH6 B2 version
609 BGA
PAGE 17,18,19,20
AMI 4MB FLASH
FWH
PAGE 36
MIC AMP
NJM2100
PAGE 39
....
DDR2 SDRAM 400/533MHz
AC LINK / ACZ
Azalia
ALC880-H
PAGE 37
AUDIO AMP
TPA0212
MDC CONN.
PAGE 38
SPDIF
PAGE 38
MIC IN
PAGE 38
CPU
CAP
PAGE 6
PCI_BUS
PAGE 39
3 IN 1 CARD
READER
(MMC/SD/
MS-PRO)
PAGE 34
1394
SLOT
PAGE 34
DDR2 400/533
SODIMM X2
+1.8V
+0.9VS
PAGE 12,13
BATLOW/SD#
LOAD Switch
PAGE 51,53
A A
+0.9VS
DC IN (19V
DC,3.42A,65W)
PAGE 52
PAGE 47
PAGE 53
CN2
CRT
5
4
CON5
USB
CON2
PORT BAR 3
TOP VIEW
CON4
USB
PIN1
PIN2
3
CON1
PIN1
PIN2
CON3
RJ45
POWER
SEQENCE
PAGE 43
....
RESET
PAGE 43
DDR
CAP/RES
PAGE 13,14
SM_BUS
PAGE 28
PAGE 35
PAGE 35
3.3V, 33MHz
CARDBUS
RICOH
R5C841
PAGE 32,33
CARDBUS
1 SLOT
VCCA, VCCB
VPPA, VPPB
PAGE 33
LAN 10/100M
LAN-RTL8101L
PAGE 29
LAN IO
PAGE 30
SWITCH
PAGE 26
TO PORT BAR3
CONN.
(FOR LAN)
PAGE 26
PORT BAR III part number is 90-N6W1P1010
CN3
LPT
J1
DCIN
2
FAN
CON.
H/W MONITOR
THERMAL
(ADT7463)
SCREW
HOLE
PAGE 25
RTC
PAGE 17
MINI PCI
TYPE III
PAGE 31
RJ11 JACK
RJ45
CONN
PAGE 30
ASUSTECH CO.,LTD.
Size Project Name
C
Date: Sheet
DISCHARGE
CIRCUIT
PAGE 42
Z61Ae
Title :
Engineer:
1
BLOCK DIAGRAM
Sam Wang
of
257Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
***********GPIO setting is not final in this page.*********
***********Please reference Z61Ae GPIO setting document.*********
D D
PCI Device
Chipset (Host to PCI)
Mini_PCI
LAN-RTL8101L
CardBus
1394
ICH6M_GPIO Use As Signal Name Power
GPI 00 GPI
GPI 01 GPI
GPI 02 GPI
GPI 03 GPI
GPI 04 GPI
GPI 05 GPI
C C
B B
GPI 07 GPI
GPI 08 GPI EXT_SMI#_3A
GPI 09 GPI
GPI 10 GPI
GPI 12 GPI
GPI 13 GPI
GPI 14 GPI
GPI 15 GPI
GPO 16 GPO
GPO 17 GPO
GPO 19 BLINK
GPO 23 GPO
GPIO24 GPO
GPIO25 GPO
GPI 26 GPI
GPIO27 GPI
GPIO28 GPI
GPI 29 GPI
GPI 30 GPI
GPI 31 GPI
GPIO33 GPO
GPIO34 GPO
GPI 40 GPI
GPI 41 GPI
GPO 48 GPO
GPO 49 GPO N/A (CPUPWRGD)
IDSEL#
(AD30 internal)
AD18
AD16
AD17
AD17
KBDDT0
KBDDT1
N/A (PIRQE#)
N/A (PIRQF#)
N/A (PIRQG#)
N/A (PIRQH#)
BMBUSY#GPI 06 GPI
N/A (USB_OC#4)
N/A (USB_OC#5)
LID_ICH_3AGPI 11 GPI
KBDSCI_3
BAT1_LLOW#_ICH6
BAT2_LLOW#_ICH6
BACK_OFF#GPO 21 GPO
FWH_WP#
CB_SD#
IHZ_ICH6
PCB_VID0
PCB_VID1
PCB_VID2
ACIN_OC_3
OP_SD#
PCB_VID3
BATSEL_2P
REQ/GNT#
n/a
3
0C
1
1
13 IN 1 C
Interrupts
B,D
B
A
PC/PCI
USE_ASM38857_GPIO SIGNAL_NAME
P23
P22
P20
P42
P43
P45
P50
P51
P52
P53 GPO BT_ON
P54
P55
P56
P57
P67
P66
P65
P64
P63
P62
P61 GPI
P60
P77
GPO
GPO
GPOP21
GPO
GPI
GPOP44
GPO
GPO
GPI
GPI
GPO
GPO
GPI
GPI
GPI
GPI
GPI
GPI
GPIOP76
GPIO
BAT_LEARN
BAT_SEL
KBCRSMGPO
WATCHDOG
CHG_FULL_OC
KBDCPURST_3Q
KBC_GA20GPO
KBSCI_3QGPOP46
PM_CLKRUN#P47 GPI
BAT_LOW#_KBCGPO
XIDE_EN#_3
BAYDOCK_IN#
BAY_RST
BAT1_IN#_OC
ADJ_BL
BAT2_IN#_OC
DISTP#
MARATHON_#
ACIN_OCGPI
LID_ICH#_3
802_ON
INTERNET#
EMAIL#
SMD_BAT
SMC_BAT
SMBUS ADDRESS :
Azalia : PCI_INTB#
USB 0,1 : PCI_INTA#
USB 2,3 : PCI_INTD#
USB 4,5 : PCI_INTC#
DDR_SODIMM0 = 1010010x ( A4 )
DDR_SODIMM1 = 1010000x ( A0 )
CLK = 1101001x ( D2 )
P27
P26
P25
P24
P41
P40 KBC_EXTSMIGPO
R5C593_GPIO
IRQ4
IRQ5
IRQ7
GPI23
GPI40
GPI41
GPI42
GPI43
GPI44
GPI45
GPI46
GPI47
GPO
GPO
GPO
GPO
GPO
USE_AS
GPOIRQ3
GPO
GPO
GPO
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPO
GPO
SIGNAL_NAMEUSE_ASM38857_GPIO
SCROLLOCK#
NUM_LED#
CAP_LED#
SET_PCIRSTNS#
EMAIL_LED#
SIGNAL_NAME
SIGNAL_NAMEUSE_AS47N217_GPIO
PID_0
PID_1
BAY_IN0
BAY_IN1
A A
Schematic information
Title :
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
357Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
CPU Socket P/N : 12-046004791
C169
H_D#[63:0] <7>
H_DINV#2 <7>
H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#3 <7>
H_DSTBN#3 <7>
H_DSTBP#3 <7>
12
12
C260
C263
10UF/10V
/*
R146
0Ohm
0.01UF
+3VS
12
12
C172
12
C171
0.1UF
0.01UF
CPU_F_SEL
R838
1 2
0Ohm
/*
ASUSTECH CO.,LTD.
Size Project Name
C
Date: Sheet
For FSB(400/533)
U20
1
SHDN#
2
GND
IN3OUT
G913C
Vset=1.25
Vout=1.25*(1+A/B)
1 2
3
1
G
2
Title :
Engineer:
Z61Ae
1
SET
VCCA_FB
R137
80.6KOhm
D
S
Q17
2N7002
/*
VCCA_FB
5
+1.8VS_PROC
4
A
R136
20KOhm
1 2
B
R138
100KOhm
1 2
DOTHAN CPU (1)
Sam Wang
457Thursday, June 09, 2005
C166
12
2200P
Rev
2.0
of
D D
C C
B B
VCCA layout: T / S :
100 mil / 25 mil
H_A#[16:3]<7>
H_ADSTB#0<7>
H_REQ#[4:0]<7>
H_A#[31:17]<7>
H_ADSTB#1<7>
DPWR#<7>
CLK_CPU_BCLK<21>
CLK_CPU_BCLK#<21>
H_A20M#<17>
H_FERR#<17>
H_IGNNE#<17>
H_DPSLP#<17>
H_CPUSLP#<7,17>
H_INTR<17>
H_NMI<17>
H_SMI#<17>
H_STPCLK#<17>
H_PWRGD<17>
VR_VID[5:0]<44>
1.05V OUTPUT
120mA
H_THERMDA<35>
H_THERMDC<35>
H_THRMTRIP_S#<6>
PM_PSI#<44>
CPU_BSEL0<21>
CPU_BSEL1<21>
FSB BSEL1 BSEL0 BSEL0
400 0 N/A 1
533 0 N/A 0
A A
5
A-STEP B-STEP
H_A#16
H_A#15
H_A#14
H_A#13
H_A#12
H_A#11
H_A#10
H_A#9
H_A#8
H_A#7
H_A#6
H_A#5
H_A#4
H_A#3
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_A#31
H_A#30
H_A#29
H_A#28
H_A#27
H_A#26
H_A#25
H_A#24
H_A#23
H_A#22
H_A#21
H_A#20
H_A#19
H_A#18
H_A#17
T68
1
R455 49.9Ohm 1%
12
R456 49.9Ohm 1%
12
VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0
+1.8VS_VCCA
+1.8VS_PROC
H_PROCHOT_S#
T264
T87
T263
Reserve for ITP
H_BPM#5
H_PROCHOT_S#
H_PWRGD
U48B
AA2
Y3
AA3
U1
Y1
Y4
W2
T4
W1
V2
R3
V3
U4
P4
U3
T1
P1
T2
P3
R2
AF1
AE1
AF3
AD6
AE2
AD5
AC6
AB4
AD2
AE4
AD3
AC3
AC7
AC4
AF4
AE5
C19
SOCKET479P
P/N = 12-046004791
T73
1
B15
B14
A16
A15
C2
OD
D3
A3
B7
A6
D1
D4
B4
C6
OD
E4
H4
G4
G3
F3
F2
E2
AC26
N1
B1
F26
B18
A18
C17
B17
E1
C16
C3
1
C14
AF7
1
B2
1
R464
56Ohm
/*
1 2
1 2
OD
A[16]#
A[15]#
A[14]#
A[13]#
A[12]#
A[11]#
A[10]#
A[9]#
A[8]#
A[7]#
A[6]#
A[5]#
A[4]#
A[3]#
ADSTB[0]#
REQ[4]#
REQ[3]#
REQ[2]#
REQ[1]#
REQ[0]#
A[31]#
A[30]#
A[29]#
A[28]#
A[27]#
A[26]#
A[25]#
A[24]#
A[23]#
A[22]#
A[21]#
A[20]#
A[19]#
A[18]#
A[17]#
ADSTB[1]#
DPWR#
U48C
BCLK[0]
BCLK[1]
ITP_CLK[0]
ITP_CLK[1]
A20M#
FERR#
IGNNE#
DPSLP#
SLP#
LINT0
LINT1
SMI#
STPCLK#
PWRGOOD
VID[5]
VID[4]
VID[3]
VID[2]
VID[1]
VID[0]
VCCA[3]
VCCA[2]
VCCA[1]
VCCA[0]
THERMDA
THERMDC
THERMTRIP#
PROCHOT#
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
SOCKET479P
+VCCP+VCCP+VCCP
R453
56Ohm
ADS#
PRDY#
PREQ#
BNR#
BPRI#
DBR#
ADDRESS GROUP 0ADDRESS GROUP 1
DEFER#
DRDY#
DBSY#
BR0#
CONTROL
IERR#
INIT#
LOCK#
RESET#
RS[2]#
RS[1]#
RS[0]#
TRDY#
HIT#
HITM#
COMP[3]
COMP[2]
HOSTCLKLEGACY CPU
COMP[1]
COMP[0]
BPM[3]#
BPM[2]#
BPM[1]#
BPM[0]#
GTLREF[3]
GTLREF[2]
GTLREF[1]
GTLREF[0]
TEST1
TEST2
MISC
TRST#
VCCSENSE
VSSSENSE
R234
200Ohm
1 2
1KOhm /*
Reserve for ITP
4
R235
N2
A10
B10
L1
J3
A7
L4
H2
M2
N4
A4
B5
J2
B11
L2
K1
H1
M3
K3
K4
AB1
AB2
P26
P25
C9
A9
B8
C8
AC1
G1
E26
AD26
C5
F23
A13
TCK
C12
TDI
A12
TDO
C11
TMS
B13
AE7
AF6
12
H_IERR#
OD
H_RS#2
H_RS#1
H_RS#0
1
T100
1
T238
R466 1KOhm /*
1 2
R147 1KOhm /*
R461 150Ohm
R459 680Ohm
VCCSENSE
VSSSENSE
R468 56Ohm
H_COMP3
H_COMP2
H_COMP1
H_COMP0
H_BPM#0 <6>
H_BPM#1 <6>
H_BPM#2 <6>
H_BPM#3 <6>
Z0=55 ohm < 0.5''
12
12
12
R184 54.9Ohm
R201 54.9Ohm
H_PWRGD_ITP <6>
H_ADS# <7>
H_BPM#4 <6>
H_BPM#5 <6>
H_BNR# <7>
H_BPRI# <7>
H_DBRESET# <6,17>
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
H_BR0# <7>
+VCCP
12
H_INIT# <17>
+VCCP
H_LOCK# <7>
H_RS#[2:0] <7>
H_TRDY# <7>
H_HIT# <7>
H_HITM# <7>
H_DPRSTP# <17>
GTLREF0
TDI <6>
TCK <6>
+VCCP
TDO <6>
TMS <6>
TRST# <6>
12
/*1%
12
/*1%
R228
54.9Ohm
/*1%
1 2
H_CPURST# <7>
Reserve for ITP
Place resistance close ITP
+VCCP
R144
1KOhm
1 2
R145
2KOhm
1%
1 2
R1.1-S29
+5V
H_COMP3
H_COMP2
H_COMP1
H_COMP0
R148
10KOhm
/*
R2.0-S11
3
H_D#15
H_D#14 H_D#46
H_D#13
H_D#12
H_D#11
H_D#10
H_D#9
H_D#8
H_D#7
H_D#6
H_D#5
H_D#4
H_D#3
H_D#2
H_D#1
H_DINV#0<7>
H_DSTBN#0<7>
H_DSTBP#0<7>
H_DINV#1<7>
H_DSTBN#1<7>
H_DSTBP#1<7>
H_D#0
H_D#31
H_D#30
H_D#29
H_D#28
H_D#27
H_D#26
H_D#25
H_D#24
H_D#23
H_D#22
H_D#21
H_D#20
H_D#19
H_D#18
H_D#17
H_D#16
R1.1-S30
+1.8VS_PROC
12
C167
10UF/10V
A-2 STEPPING 1.8V/1.5V
B STEPPING 1.5V only
12
R232 54.9Ohm 1%
12
R233 27.4Ohm 1%
12
R143 54.9Ohm 1%
1 2
R142 27.4Ohm 1%
S
D
+1.8VS_PROC+1.8VS_VCCA
3
2
G
1
Q16 SI2302DS
/*
12
3
D
Q18
1
VCCA_1.8_EN# <21>
G
S
2
2N7002
/*
Switch default is PIN3 and PIN4 ON.
For FSB 400 CPU.
SW2 switch TO PIN1 "pin1 & 4 OPEN"==>133MHz/1.5V"VCCA0
SW2 switch TO PIN4 "pin1 & 4 SHORT"==>100MHz/1.8V"VCCA0
SW2 switch TO PIN2 "pin2 & 3 OPEN"==>DOTHAN 533
SW2 switch TO PIN3 "pin2 & 3 SHORT"=>CELERON/BANIAS/DOTHAN400
+3VS
100
133
U48A
C25
D[15]#
E23
D[14]#
B23
D[13]#
C26
D[12]#
E24
D[11]#
D24
D[10]#
B24
D[9]#
C20
D[8]#
B20
D[7]#
A21
D[6]#
B26
D[5]#
A24
DATA GROUP 0DATA GROUP 1
D[4]#
B21
D[3]#
A22
D[2]#
A25
D[1]#
A19
D[0]#
D25
DINV[0]#
C23
DSTBN[0]#
C22
DSTBP[0]#
K25
D[31]#
N25
D[30]#
H26
D[29]#
M25
D[28]#
N24
D[27]#
L26
D[26]#
J25
D[25]#
M23
D[24]#
J23
D[23]#
G24
D[22]#
F25
D[21]#
H24
D[20]#
M26
D[19]#
L23
D[18]#
G25
D[17]#
H23
D[16]#
J26
DINV[1]#
K24
DSTBN[1]#
L24
DSTBP[1]#
SOCKET479P
12
12
C170
C264
10UF/10V
0.01UF
/*
D[47]#
D[46]#
D[45]#
D[44]#
D[43]#
D[42]#
D[41]#
D[40]#
D[39]#
D[38]#
D[37]#
D[36]#
DATA GROUP 2DATA GROUP 3
D[35]#
D[34]#
D[33]#
D[32]#
DINV[2]#
DSTBN[2]#
DSTBP[2]#
D[63]#
D[62]#
D[61]#
D[60]#
D[59]#
D[58]#
D[57]#
D[56]#
D[55]#
D[54]#
D[53]#
D[52]#
D[51]#
D[50]#
D[49]#
D[48]#
DINV[3]#
DSTBN[3]#
DSTBP[3]#
+1.8VS_VCCA
12
C262
0.01UF
Y25
AA26
Y23
V26
U25
V24
U26
AA23
R23
R26
R24
V23
U23
T25
AA24
Y26
T24
W25
W24
AF26
AF22
AF25
AD21
AE21
AF20
AD24
AF23
AE22
AD23
AC25
AC22
AC20
AB24
AC23
AB25
AD20
AE24
AE25
12
/*
Place near CPU pin
Layout note:
COMP0 and COMP2 need to be Zo=27.4ohm traces.
Best estimate is 18mil wide trace for outer
layers and
14mil if on internal layer. See RDDP of
Banias.
Traces should be shorter than 0.5". Refer to
latest CS layout
COMP1, COMP3 should be routed as Zo=55ohm
traces shorter than 0.5"
PM_SUSB#<17,21,29,32,37,40,43,48,52>
If CPU_F_SEL=LOW
-->+1.8VS_PROC=1.81V
CPU_F_SEL=OPEN
-->+1.8VS_PROC=1.5V
1 2
4
1
R139
100KOhm
/*
CPU_F_SEL
2 3
+1.8VS_VCCA
OTHER
SW2
SWITCH_4P
DOTHAN
+1.8VS_PROC
2
H_D#47
H_D#45
H_D#44
H_D#43
H_D#42
H_D#41
H_D#40
H_D#39
H_D#38
H_D#37
H_D#36
H_D#35
H_D#34
H_D#33
H_D#32
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_D#53
H_D#52
H_D#51
H_D#50
H_D#49
H_D#48
C168
10UF/10V
12
0.01UF
VCCA_1.8_EN<21>
5
D D
U48D
W4
VCCQ[1]
P23
VCCQ[0]
D10
VCCP1
D12
VCCP2
D14
VCCP3
D16
VCCP4
E11
VCCP5
E13
VCCP6
E15
VCCP7
F10
VCCP8
F12
VCCP9
F14
VCCP10
F16
VCCP11
K6
VCCP12
L5
VCCP13
L21
VCCP14
M6
VCCP15
M22
VCCP16
N5
VCCP17
N21
VCCP18
P6
VCCP19
P22
VCCP20
R5
VCCP21
R21
C C
B B
VCCP22
T6
VCCP23
T22
VCCP24
U21
VCCP25
VCC
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
AF8
AF10
AF12
AF14
AF16
AF18
AE13
AE15
AE17
AE19
VCC63
VCC62
AE11
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
SOCKET479P
AE9
D6
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
F18
F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
V6
V22
W5
W21
Y6
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
4
+VCORE+VCCP
AF24
AF21
AF19
AF17
AF15
AF13
AF11
AF9
AF5
AF2
AE26
AE23
AE20
VSS187
VSS70
VSS186
VSS185
VSS71J1VSS72J4VSS73J6VSS74
AE18
VSS184
VSS183
VSS182
VSS181
VSS180
VSS75
VSS76K2VSS77
K5
J22
J24
K21
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
SOCKET479P
U48E
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS192
VSS191
VSS190
VSS189
VSS188
VSS65
VSS66
VSS67H3VSS68H5VSS69
H21
H25
G23
G26
AE16
AE14
AE12
AE10
VSS179
VSS178
VSS177
VSS176
GND
VSS79
VSS78
K26
K23
3
AE8
AE6
AE3
AD25
AD22
AD19
AD17
AD15
AD13
AD11
AD9
AD7
AD4
AD1
AC24
VSS160
AC21
VSS159
AC18
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS88
VSS87M5VSS86M4VSS85M1VSS84
VSS83
VSS82L6VSS81L3VSS80
L25
L22
M24
M21
VSS158
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
AC16
VSS157
AC14
VSS156
AC12
VSS155
AC10
VSS154
AC8
VSS153
AC5
VSS152
AC2
VSS151
AB26
VSS150
AB23
VSS149
AB21
VSS148
AB19
VSS147
AB17
VSS146
AB15
VSS145
AB13
VSS144
AB11
VSS143
AB9
VSS142
AB7
VSS141
AB5
VSS140
AB3
VSS139
AA25
VSS138
AA22
VSS137
AA20
VSS136
AA18
VSS135
AA16
VSS134
AA14
VSS133
AA12
VSS132
AA10
VSS131
AA8
VSS130
AA6
VSS129
AA4
VSS128
AA1
VSS127
Y24
VSS126
Y21
VSS125
Y5
VSS124
Y2
VSS123
W26
VSS122
W23
VSS121
W22
VSS120
W6
VSS119
W3
VSS118
V25
VSS117
V21
VSS116
V5
VSS115
V4
VSS114
V1
VSS113
U24
VSS112
U22
VSS111
U6
VSS110
U2
VSS109
T26
VSS108
T23
VSS107
T21
VSS106
T5
VSS105
T3
VSS104
R25
VSS103
R22
VSS102
R6
VSS101
R4
VSS100
R1
VSS99
P24
VSS98
P21
VSS97
VSS95P2VSS94
VSS93
VSS92
VSS91N6VSS90N3VSS89
VSS96
P5
N26
N23
N22
2
MOBILE DOTHAN VID TABLE
0 0 0 0 0 0 1.708V
0 0 0 0 0 1 1.692V
0 0 0 0 1 0 1.676V
0 0 0 0 1 1 1.660V
0 0 0 1 0 0 1.644V
0 0 0 1 0 1 1.628V
0 0 0 1 1 0 1.612V
0 0 0 1 1 1 1.596V
0 0 1 0 0 0 1.580V
0 0 1 0 0 1 1.564V
0 0 1 0 1 0 1.548V
0 0 1 0 1 1 1.532V
0 0 1 1 0 0 1.516V
0 0 1 1 0 1 1.500V
0 0 1 1 1 0 1.484V
0 0 1 1 1 1 1.468V
0 1 0 0 0 0 1.452V
0 1 0 0 0 1 1.436V
0 1 0 0 1 0 1.420V
0 1 0 0 1 1 1.404V
0 1 0 1 0 0 1.388V
0 1 0 1 0 1 1.372V
0 1 0 1 1 0 1.356V
0 1 0 1 1 1 1.340V
0 1 1 0 0 0 1.324V
0 1 1 0 0 1 1.308V
0 1 1 0 1 0 1.292V
0 1 1 0 1 1 1.276V
0 1 1 1 0 0 1.260V
0 1 1 1 0 1 1.244V
0 1 1 1 1 0 1.228V
0 1 1 1 1 1 1.212V
VID[5..0]VID[5..0]
1 0 0 0 0 0 1.196V
1 0 0 0 0 1 1.180V
1 0 0 0 1 0 1.164V
1 0 0 0 1 1 1.148V
1 0 0 1 0 0 1.132V
1 0 0 1 0 1 1.116V
1 0 0 1 1 0 1.100V
1 0 0 1 1 1 1.084V
1 0 1 0 0 0 1.068V
1 0 1 0 0 1 1.052V
1 0 1 0 1 0 1.036V
1 0 1 0 1 1 1.020V
1 0 1 1 0 0 1.004V
1 0 1 1 0 1 0.988V
1 0 1 1 1 0 0.972V
1 0 1 1 1 1 0.956V
1 1 0 0 0 0 0.940V
1 1 0 0 0 1 0.924V
1 1 0 0 1 0 0.908V
1 1 0 0 1 1 0.892V
1 1 0 1 0 0 0.876V
1 1 0 1 0 1 0.860V
1 1 0 1 1 0 0.844V
1 1 0 1 1 1 0.828V
1 1 1 0 0 0 0.812V
1 1 1 0 0 1 0.796V
1 1 1 0 1 0 0.780V
1 1 1 0 1 1 0.764V
1 1 1 1 0 0 0.748V
1 1 1 1 0 1 0.732V
1 1 1 1 1 0 0.716V
1 1 1 1 1 1 0.700V
VoltageVoltage
1
A A
Title :
DOTHAN CPU (2)
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
557Thursday, June 09, 2005
Rev
2.0
5
VCORE 10uF/10V * 35
220uF/2V * 4
VCCP 0.1uF * 10 for CPU
D D
+VCORE 10uF is
/6.3V/0805/X5R as
M7V R2.0
+VCORE
R1.1-S32
27A for 1.8G
12
C202
10UF
12
C228
10UF
12
C198
10UF
12
C196
10UF
150uF * 1 for CPU
0.1uF * 10 for Alviso
150uF * 2 for Alviso
4.7uF * 1 for Alviso
2.2uF * 1 for Alviso
0.47uF * 2 for Alviso on A6 B2 G1 V1
0.22uF * 2 for Alviso on A6 B2 G1 V1
Decoupling guide from INTEL
12
12
12
12
C229
10UF
C195
10UF
C214
10UF
12
12
C197
10UF
C215
10UF
C462
10UF
4
12
12
C216
C184
10UF
10UF
12
12
C231
C466
10UF
10UF
12
12
C181
10UF
12
C482
10UF
12
C180
C199
10UF
10UF
12
12
C192
C232
10UF
10UF
3
2
+VCCP
12
12
R462
R460
R465
39.2Ohm
54.9Ohm
1KOhm
1%
1
T270
1
T269
1
T111
1
T74
1
T251
1
T248
1
T253
1
T254
1 2
/*1%
/*
CLK_ITP_BCLK <21>
CLK_ITP_BCLK# <21>
H_CPURST#_ITP <7>
H_DBRESET# <4,17>
TDO <4>
TRST# <4>
TDI <4>
TMS <4>
1
12
12
C211
10UF
C C
R1.1-S32
B B
12
+VCCP
C230
10UF
12
150U/4.0V
2.5A for 1.8G
+
CE19
C212
10UF
12
12
C227
C220
10UF
10UF
12
+
CE9
220UF/2V
12
12
0.1UF
0.1UF
C469
C464
12
C465
0.1UF
12
C480
0.1UF
12
12
12
+
C218
10UF
CE11
220UF/2V
12
0.1UF
12
0.1UF
C479
C481
C219
10UF
12
C472
0.1UF
DOTHAN VID TABLE
C3/C4
CPU
FREQ.
1.8G
1.7G
HFM
VOLTAGE
1.6G 1.2G
1.308V
LFM
1G1.4G
0.6G
0.844V
0.748V
1.196V1.228V1.260V1.292V
12
12
C190
10UF
12
+
CE20
220UF/2V
/*
12
C463
0.1UF
C191
10UF
NEAR CPU
PIN W4
12
12
C188
C478
10UF
10UF
H_PWRGD_ITP<4>
CTL_CLK<8>
CTL_DATA<8>
+2.5VS
NEAR CPU
PIN P23
12
0.1UF
C474
12
C471
0.1UF
+VCCP
R127
75Ohm
1 2
R452 0Ohm
H_THRMTRIP_S#<4>
GMCH_THRMTRIP#<8>
BUF_PLT_RST#<8,17,18,22,24,27,36>
12
R457 0Ohm
12
/*
R498
2.2KOhm
/*
1 2
+VCCP
Q90
E12
PMBS3904
1 2
B
R445
330Ohm
C
1 2
3
R497
2.2KOhm
/*
1 2
C457
0.1UF
H_BPM#5<4>
H_BPM#4<4>
H_BPM#3<4>
H_BPM#2<4>
H_BPM#1<4>
H_BPM#0<4>
TCK<4>
R458
27.4Ohm
1%
S
2
G
1
T257
1
T256
1
T83
1
T82
1
T258
1
T79
1
T124
1
T277
1
T273
1
D
Q84
3
2N7002
T245
H_THRMTRIP# <17>
OTP_RESET# <43,48>
12
1
A A
CPU CAP/THERMAL
Title :
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
657Thursday, June 09, 2005
Rev
2.0
5
D D
R478
24.9Ohm
1%
1 2
+VCCP
R479
54.9Ohm
1%
1 2
+VCCP
R474
221Ohm
1%
+VCCP
+VCCP
1 2
1 2
1 2
1 2
1 2
R473
100Ohm
1%
1 2
R472
24.9Ohm
1%
R476
54.9Ohm
1%
R470
221Ohm
1%
R471
100Ohm
1%
/*
12
/*
H_YSWING
12
H_XSWING
C491
10UF/10V
C490
10UF/10V
C C
B B
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
4
U49 Original P/N is 02-010002600(ALVISO-PM)
Z61AE R1.0 use C0 version part number is 02-010002610 (ALVISO GM)
U49 need to change to new C1 version 02-010002640 (INTEL ALVISO-GM SL8G2)
R1.1 has changed it in symbol.
H_D#[0..63]<4>
12
C494
0.1UF
12
C489
0.1UF
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
3
U49D
E4
HD0#
E1
HD1#
F4
HD2#
H7
HD3#
E2
HD4#
F1
HD5#
E3
HD6#
D3
HD7#
K7
HD8#
F2
HD9#
J7
HD10#
J8
HD11#
H6
HD12#
F3
HD13#
K8
HD14#
H5
HD15#
H1
HD16#
H2
HD17#
K5
HD18#
K6
HD19#
J4
HD20#
G3
HD21#
H3
HD22#
J1
HD23#
L5
HD24#
K4
HD25#
J5
HD26#
P7
HD27#
L7
HD28#
J3
HD29#
P5
HD30#
L3
HD31#
U7
HD32#
V6
HD33#
R6
HD34#
R5
HD35#
P3
HD36#
T8
HD37#
R7
HD38#
R8
HD39#
U8
HD40#
R4
HD41#
T4
HD42#
T5
HD43#
R1
HD44#
T3
HD45#
V8
HD46#
U6
HD47#
W6
HD48#
U3
HD49#
V5
HD50#
W8
HD51#
W7
HD52#
U2
HD53#
U1
HD54#
Y5
HD55#
Y2
HD56#
V4
HD57#
Y7
HD58#
W1
HD59#
W3
HD60#
Y3
HD61#
Y6
HD62#
W2
HD63#
C1
HXRCOMP
C2
HXSCOMP
D1
HXSWING
T1
HYRCOMP
L1
HYSCOMP
P1
HYSWING
ALVISO_BGA1257
02-010002640
HADSTB0#
HADSTB1#
HBREQ0#
HCPURST#
HCLKINN
HCLKINP
HOST
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDPWR#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHITM#
HLOCK#
HPCREQ#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HCPUSLP#
HTRDY#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HVREF
HBNR#
HBPR#
HHIT#
HRS0#
HRS1#
HRS2#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
R225 22.6Ohm
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_CPURST#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
12
/*1%
2
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_CPURST# <4>
H_CPURST#_ITP <6>
CLK_MCH_BCLK# <21>
CLK_MCH_BCLK <21>
H_DBSY# <4>
H_DRDY# <4>
H_DSTBN#0 <4>
H_DSTBN#1 <4>
H_DSTBN#2 <4>
H_DSTBN#3 <4>
H_DSTBP#0 <4>
H_DSTBP#1 <4>
H_DSTBP#2 <4>
H_DSTBP#3 <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>
H_A#[3..31] <4>
H_DEFER# <4>
H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>
DPWR# <4>
T121
1
T274
1
H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>
H_CPUSLP# <4,17>
H_TRDY# <4>
+VCCP
1 2
1 2
R216
100Ohm
1%
R217
200Ohm
1%
1
12
C257
0.1UF
A A
Title :
Alviso--CPU (1)
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
757Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
SDVO SMbus have
D D
DMI_TXN[0..3]<18>
DMI_TXP[0..3]<18>
DMI_RXN[0..3]<18>
DMI_RXP[0..3]<18>
T63
TP_SMCK2
1
T70
TP_SMCK5
1
T69
TP_SMCK#2
1
T72
C C
Layout Note:
Route as short
as possible.
R677
R678
40.2Ohm
40.2Ohm
1%
1%
1 2
B B
TP_SMCK#5
1
1 2
+1.8V
R150
1 2
80.6Ohm
1%
DCLK0<13>
DCLK1<13>
DCLK3<12>
DCLK4<12>
DCLK0#<13>
DCLK1#<13>
DCLK3#<12>
DCLK4#<12>
SCKE0<13,14>
SCKE1<13,14>
SCKE2<12,14>
SCKE3<12,14>
SCS0#<13,14>
SCS1#<13,14>
SCS2#<12,14>
SCS3#<12,14>
M_OCDCOMP0
M_OCDCOMP1
ODT0<13,14>
ODT1<13,14>
ODT2<12,14>
ODT3<12,14>
M_RCOMPN
M_RCOMPP
R158
80.6Ohm
1%
1 2
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
VTT_REF
SMXSLEW
SMYSLEW
Zo=55 ohm
Zo=55 ohm
AA31
AB35
AC31
AD35
AA35
AB31
AC35
AA33
AB37
AC33
AD37
AA37
AB33
AC37
AM33
AE11
AJ34
AC10
AN33
AE10
AJ33
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AE27
AE28
AF10
Y31
Y33
AL1
AF6
AK1
AF5
AD1
AF9
U49A
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
ALVISO_BGA1257
02-010002640
G16
CFG0
H13
CFG1
G14
CFG2
F16
CFG3
F15
CFG4
G15
CFG5
E16
CFG6
D17
CFG7
J16
CFG8
D15
CFG9
E15
CFG10
D14
CFG11
E14
CFG12
H12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
PM
THRMTRIP#
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
CLK
DREF_SSCLKP
NC
NC10
NC11
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
C37
D37
AP37
NC1
AN37
NC2
AP36
NC3
AP2
NC4
AP1
NC5
AN1
NC6
B1
NC7
A2
NC8
B37
NC9
A36
A37
DMIDDR MUXING
R229 1KOhm
CFG3
1
CFG4
1
CFG5
CFG6
CFG7
CFG8
1
CFG9
CFG10
1
CFG11
1
CFG12
1
CFG13
1
CFG14
1
CFG15
1
CFG16
CFG17
1
CFG18
TPC28t
CFG19
CFG20
1
1
1
1
1
1
1
1
PM_EXTTS#0
PM_EXTTS#1
MCH_PWROK
12
R173 100Ohm
1%
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
12
T122
1
1
1
1
1
1
1
1
1
1
1
internal pull down
+2.5VS
MCH_SEL1 <21>
MCH_SEL0 <21>
T116
T120
CFG5 <11>
CFG6 <11>
CFG7 <11>
T123
CFG9 <11>
T137
T135
T125
T115
T140
T138
CFG16 <11>
CFG18 <11>
CFG19 <11>
T132
T126
T109
T131
T142
T146
T133
T136
LCD_BACKEN_GM<15>
PM_BMBUSY# <17>
GMCH_THRMTRIP# <6>
BUF_PLT_RST# <6,17,18,22,24,27,36>
T47
T49
T48
T51
T54
T53
T268
T275
T267
T272
T271
LCD_VDD_EN_GM<15>
DREFCLK# <21>
DREFCLK <21>
DREFSSCLK# <21>
DREFSSCLK <21>
SDVOCRTL_DATA Int PD
0 : No SDVO device
1 : SDVO device present
T106
T103
CLK_MCH_3GPLL#<21>
CLK_MCH_3GPLL<21>
DDC2BC_GM<16>
DDC2BD_GM<16>
DAC_B_GM<16>
DAC_G_GM<16>
DAC_R_GM<16>
ADJ_BL_GM<15>
CTL_CLK<6>
CTL_DATA<6>
DDCCLK_GM<15>
DDCDATA_GM<15>
LVDS_CLKAM_GM<15>
LVDS_CLKAP_GM<15>
LVDS_CLKBM_GM<15>
LVDS_CLKBP_GM<15>
LVDS_YA0M_GM<15>
LVDS_YA1M_GM<15>
LVDS_YA2M_GM<15>
LVDS_YA0P_GM<15>
LVDS_YA1P_GM<15>
LVDS_YA2P_GM<15>
LVDS_YB0M_GM<15>
LVDS_YB1M_GM<15>
LVDS_YB2M_GM<15>
LVDS_YB0P_GM<15>
LVDS_YB1P_GM<15>
LVDS_YB2P_GM<15>
SDVO_SMDATA
1
SDVO_SMCLK
1
TVDAC_A_GM
TVDAC_B_GM
TVDAC_C_GM
TV_REFSET_GM
TVDAC_A_GM#
TVDAC_B_GM#
TVDAC_C_GM#
DAC_B_GM
DAC_B_GM#
DAC_G_GM
DAC_G_GM#
DAC_R_GM
DAC_R_GM#
VSYNC_GM
HSYNC_GM
REFSET_GM
T143
1
T141
1
T150
1
T145
1
DDCCLK_GM
DDCDATA_GM
L_IBG
L_LVBG
L_LVREFH
L_LVREFL
Disable TV_OUT :
TVDAC A/B/C and TVIRTN A/B/C and TV_REFSET
and VCCA_TVDAC A/B/C ... ( ALL TV POWER )
connect to GND
U49F
H24
AB29
AC29
H25
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
ALVISO_BGA1257
02-010002640
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
MISCTVVGALVDS
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
PCI-EXPRESS GRAPHICS
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
PCI-E signals can be left NC, If unused.
+1.8V
R725
10KOhm
1 2
12
C725
R726
0.01UF
10KOhm
1 2
A A
+5V
12
C724
0.1UF
VTT_REF
52
U65
V+
1
+
4
3
V-
LMV321
5
T340
1
12
C726
1UF/10V
MCH_PWROK
DAC_B_GM
DAC_G_GM
DAC_R_GM
REFSET_GM
255 ohm main source is 10G213255013010.
Second source is 10-003412515.
DAC_VSYNC_GM<16>
DAC_HSYNC_GM<16>
4
1 2
R202 0Ohm /*
1 2
R203 0Ohm
R246 150Ohm
1 2
R252 150Ohm
1 2
R253 150Ohm
1 2
R501 255Ohm
1 2
10G213255013010
R222
1 2
R227
39Ohm
1 2
39Ohm
VCC_MCH_VRPWRGD <44,48>
ICH6_PWROK <17,43>
DAC_B_GM#
DAC_G_GM#
DAC_R_GM#
VSYNC_GM
HSYNC_GM
+2.5VS
PM_EXTTS#0
RN50A
1 2
10KOhm
3 4
10KOhm
5 6
10KOhm
7 8
10KOhm
R499
1 2
1.5KOhm 1%
3
RN50B
RN50C
RN50D
L_IBG
PM_EXTTS#1
DDCDATA_GM
DDCCLK_GM
Title :
Z61Ae
ASUSTECH CO.,LTD.
Size Project Name
C
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
857Thursday, June 09, 2005
Rev
2.0
5
D D
4
3
2
1
M_A_DQ[0..63]<13> M_B_DQ[0..63]<12>
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AP11
AP10
AM9
AL9
AL6
AP7
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U49B
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
ALVISO_BGA1257
02-010002640
AK15
SA_BS0#
AK16
SA_BS1#
AL21
SA_BS2#
AJ37
SA_DM0
AP35
SA_DM1
AL29
SA_DM2
AP24
SA_DM3
AP9
SA_DM4
AP4
SA_DM5
AJ2
SA_DM6
AD3
SA_DM7
AK36
SA_DQS0
AP33
SA_DQS1
AN29
SA_DQS2
AP23
SA_DQS3
AM8
SA_DQS4
AM4
SA_DQS5
AJ1
SA_DQS6
AE5
SA_DQS7
AK35
SA_DQS0#
AP34
SA_DQS1#
AN30
SA_DQS2#
AN23
SA_DQS3#
AN8
SA_DQS4#
AM5
SA_DQS5#
AH1
SA_DQS6#
AE4
SA_DQS7#
AL17
SA_MA0
AP17
SA_MA1
AP18
SA_MA2
AM17
SA_MA3
AN18
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_WE#
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
DDR SYSTEM MEMORY A
SA_RCVENOUT#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
M_A_BS#0 <13,14>
M_A_BS#1 <13,14>
M_A_BS#2 <13,14>
M_A_DM[0..7] <13>
M_A_DQS[0..7] <13>
M_A_DQS#[0..7] <13>
M_A_A[0..13] <13,14>
T57 TPC28t
1
T65 TPC28t
1
M_A_CAS# <13,14>
M_A_RAS# <13,14>
M_A_WE# <13,14>
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AH11
AH10
AG9
AG8
AH8
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
U49C
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
ALVISO_BGA1257
02-010002640
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
DDR SYSTEM MEMORY B
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
M_B_DM0
AF32
M_B_DM1
AK34
M_B_DM2
AK27
M_B_DM3
AK24
M_B_DM4
AJ10
M_B_DM5
AK5
M_B_DM6
AE7
M_B_DM7
AB7
M_B_DQS0
AF34
M_B_DQS1
AK32
M_B_DQS2
AJ28
M_B_DQS3
AK23
M_B_DQS4
AM10
M_B_DQS5
AH6
M_B_DQS6
AF8
M_B_DQS7
AB4
M_B_DQS#0
AF35
M_B_DQS#1
AK33
M_B_DQS#2
AK28
M_B_DQS#3
AJ23
M_B_DQS#4
AL10
M_B_DQS#5
AH7
M_B_DQS#6
AF7
M_B_DQS#7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
TP_MB_RCVENIN#
AF15
TP_MB_RCVENOUT#
AF14
AH16
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_BS#0 <12,14>
M_B_BS#1 <12,14>
M_B_BS#2 <12,14>
T60 TPC28t
1
T62 TPC28t
1
M_B_DM[0..7] <12>
M_B_DQS[0..7] <12>
M_B_DQS#[0..7] <12>
M_B_A[0..13] <12,14>
M_B_CAS# <12,14>
M_B_RAS# <12,14>
M_B_WE# <12,14>
A A
Title :
Alviso--DDR2 (3)
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
957Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
3
246
135
1
D67
BAT54C
/*
8
7
+2.5VS +3VS
+VCC_GMCH_CORE +1.5VS
1
2
3
246
135
D38
BAT54C
8
7
RN49
10Ohm
RN52A
22Ohm
2
1
D41
BAT54C
3
RN52D
22Ohm
3 4
7 8
5 6
1 2
RN52B
RN52C
22Ohm
22Ohm
R1.1-S18
12
C760
0.1UF
+2.5VS
R10
P10
N10
M10
K10
J10
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
AB9
AP8
AE1
AM1
AB11
AB10
AC11
Note: All VCCSM pins
shorted internally.
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
12
C503
10UF/10V
0.1UF
+1.5VS
12
C237
0.1UF
Place near pin
A25, B25, B26
VCC_SYNC
12
+
CE17
150U/4.0V
R784 0Ohm
R785 0Ohm
W10
V10
U10
T10
VTT14
VTT15
VTT16
VTT17
VCCSM55
VCCSM56
VCCSM57
VCCSM58
AF12
AE12
AD11
AG12
12
C207
0.1UF
12
+1.5VS_MPLL
1 2
1 2
L11
K11
VTT11
VTT12
VTT13
VCCSM52
VCCSM53
VCCSM54
AJ12
AH12
C224
10UF/10V
+1.5VS
+1.5VS_HPLL
12
+
AE17
12
AA2
VCCSM33
AE18
+
AA1
VCCA_HPLL
VCCA_MPLL
VCCSM31
VCCSM32
AE19
12
CE28
150U/4.0V
C35
AE20
C461
0.1UF
12
VCCA_DPLLB
VCCSM30
B23
VCCA_DPLLA
VCCSM29
AE21
C501
0.01UF
AC1
AE22
AC2
VCCH_MPLL0
VCCSM28
AE23
CE12
150U/4.0V
12
+
VCCH_MPLL1
VCCSM26
VCCSM27
AE24
12
CE14
150U/4.0V
K18
K17
VCC47
VCC48
VCCSM24
VCCSM25
AF25
AE25
C459
0.1UF
L76
21
120Ohm/100Mhz
12
C476
0.1UF
VCCA_CRTDAC
VCC_SYNC
/*
H20
K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
AL12
AF13
AE13
AP12
AK12
AN12
AG13
AM12
12
12
C458
C449
0.1UF
0.1UF
C186
10UF/10V
G19
F19
E19
VTT0
VTT1
VTT2
VTT3
VCC_SYNC
VSSA_CRTDAC
VCCA_CRTDAC0
VCCA_CRTDAC1
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
AJ13
AL13
AE16
AE15
AE14
AP13
AK13
AN13
AH13
AM13
Note: All VCCSM pins
shorted internally.
12
C454
0.1UF
+1.8V
12
12
C453
0.1UF
+2.5VS
12
C500
0.1UF
12
C223
0.1UF
+1.5VS_DPLLB
12
U19
K19
W18
V18
T18
VCC43
VCC44
VCC45
VCC46
POWER
VCCSM20
VCCSM21
VCCSM22
VCCSM23
AJ25
AL25
AK25
AH25
AG25
L38
120Ohm/100Mhz
120Ohm/100Mhz
C271
0.1UF
T20
K20
V19
VCC39
VCC40
VCC41
VCC42
VCCSM16
VCCSM17
VCCSM18
VCCSM19
AP25
AN25
AM25
V1.8_DDR_CAP5
V1.8_DDR_CAP2
V1.8_DDR_CAP1
+2.5VS
21
L43
W20
U20
VCC37
VCC38
VCCSM14
VCCSM15
AF26
AE26
C509
10UF/10V
+1.5VS_DPLLA
12
+
CE15
150U/4.0V
21
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
B22
B21
AJ26
AL26
AP26
AK26
AN26
AH26
AG26
AM26
12
12
C502
0.1UF
A21
AP29
AH37
AD28
AD27
AC27
AM37
+1.5VS
12
12
V27
C498
0.1UF
VCC18
C272
0.1UF
G28
A35
VCC17
VCCA_LVDS
12
H28
J28
VCC16
A25
12
C250
10UF/10V
L28
K28
VCC14
VCC15
VCCD_LVDS1
VCCD_LVDS2
B26
B25
C497
0.01UF
L42
120Ohm/100Mhz
12
C244
10UF/10V
R28
P28
N28
M28
VCC10
VCC11
VCC12
VCC13
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
D19
H17
VCCDQ_TVDAC
VCCD_TVDAC
21
U28
T28
VCC7
VCC8
VCC9
VCCA_TVBG
VSSA_TVBG
H18
G18
VCCA_TVBG
12
C247
10UF/10V
K29
J29
V28
VCC4
VCC5
VCC6
VCCA_TVDACC0
VCCA_TVDACC1
F18
E18
VCCA_TVDACC
12
C236
0.1UF
T29
R29
N29
M29
U49G
ALVISO_BGA1257
VCC0
VCC1
VCC2
VCC3
02-010002640
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
F17
E17
D18
C18
Disable TV_OUT
VCCA_TVDACA
==> All TV POWER short to GND
VCCA_TVDACB
Place near pin A35
R857
1 2
4.3Ohm
C762
2.2UF/16V
R1.1-S32
+2.5VS_CRTDAC
R783
0Ohm
/*
1 2
12
12
C496
0.1UF
12
C495
0.1UF
+1.5VS
+1.5VS
120Ohm/100Mhz
+VCCP
VCCP_GMCH_CAP1
VCCP_GMCH_CAP2
VCCP_GMCH_CAP3
12
C492
0.1UF
12
C475
0.1UF
L37
21
120Ohm/100Mhz
L78
21
C759
1UF
1.05V
CE13
150U/4.0V
/*
CAP4
G1
1 2
+2.5VS
+1.5VS_3GPLL
12
+1.5VS
12
C265
0.1UF
12
C233
0.1UF
+
CE18
150U/4.0V
/*
12
12
+
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
F37
Y27
G37
12
+1.5VS_PCIE
12
L36
120Ohm/100Mhz
C267
0.01UF
VCCA_3GPLL1
Y29
Y28
C239
10UF/10V
C248
0.1UF
21
VCCA_3GPLL0
12
12
C243
0.1UF
A6
VTT38
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
J37
L37
U37
R37
N37
12
C241
10UF/10V
+1.5VS_DDRDLL
12
C261
0.1UF
VCC3G1
W37
C205
0.1UF
12
AE37
C240
10UF/10V
R1.1-S18
VCCA_SM3
VCC3G0
AF19
AF18
12
+
150U/4.0V
VCCA_SM2
CE10
VCCA_SM1
AP19
+2.5VS
AF20
VCCA_SM0
+2.5VS_CRTDAC
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
B28
A28
A27
12
C499
R1.1-S18
Int VGA
+2.5VS
12
C761
0.1UF
D D
C C
B B
+VCC_GMCH_CORE
2
R1.1-S18
RN60
10Ohm
/*
+2.5VS_CRTDAC
+VCC_GMCH_CORE
1.05V
12
12
C246
C255
0.1UF
0.1UF
1.8V: 1A for DDR2 400 1 channel
2A for DDR2 400 2 channel
1.3A for DDR2 533 1 channel
2.7A for DDR2 533 2 channel
1.05VS:850mA for CPU
3100mA for external gfx
1.5VS: 1264mA
2.5VS: 293mA
3VS: 120mA
A A
Title :
Alviso--POWER (4)
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
10 57Thursday, June 09, 2005
Rev
2.0
5
D D
AL24
AN24
A26
E26
G26
J26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
4
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS75
3
AL31
A32
C32
Y32
AA32
AB32
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
2
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
AG37
U49H
ALVISO_BGA1257
VSS1
VSS0
02-010002640
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS9
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
1
VSS
VSSALVDS
VSS271Y1VSS270D2VSS269G2VSS268J2VSS260L2VSS259P2VSS258T2VSS257V2VSS256
B36
VSS255
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
VSS248
VSS247
VSS246
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
VSS238
VSS237E5VSS236W5VSS235
VSS234
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS163
J12
AJ3
AL2
AE2
AA3
AD2
AB3
AH2
AN2
AC3
AL5
AF4
AP5
AN4
AJ6
AA6
AE6
AA7
AC6
AG7
AL8
AK7
AN7
L10
F11
Y10
Y11
D10
AA9
AE9
AC9
H11
AH9
AN9
AJ11
AL11
AF11
AA10
AA11
AG11
J14
F14
B12
A14
B14
K14
K15
A16
D12
AN11
AJ14
AG14
K16
C15
D16
H16
C17
G17
AL14
AN14
AJ17
AL16
AF17
J19
T19
A18
B18
C19
H19
U18
AL18
AN17
F20
A20
E20
V20
D20
G20
W19
AG19
AK20
AN19
J22
F21
A22
E22
C21
D22
AL22
AF21
AN21
AH22
VSS130
J24
F24
B24
H23
D24
AJ24
AF23
AG24
+1.8V
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
C C
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
+VCC_GMCH_CORE
AD21
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
L12
P12
N12
M12
VCCSM_NCTF0
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
L13
T12
R12
U12
T13
V12
P13
V13
N13
R13
U13
M13
W12
W13
L14
Y12
Y13
M14
AA12
AA13
NCTF
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
L15
T14
P14
V14
Y14
N14
R14
U14
P15
N15
R15
M15
W14
AA14
AB14
L16
T15
V15
Y15
U15
W15
T16
P16
V16
Y16
N16
R16
M16
AA15
AB15
Y17
U16
R17
W16
AA16
AB16
VCC_NCTF19
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
AA17
R21
AB17
AA18
AB18
AA19
AB19
AA20
AB20
V25
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
VCC_NCTF10
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
Y21
Y22
Y23
AA21
AB21
AA22
AB22
AA23
+VCC_GMCH_CORE
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26
U49E
ALVISO_BGA1257
02-010002640
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
Y24
Y25
Y26
AB23
AA24
AB24
AA25
AB25
AA26
AB26
NCTF pin can share the via each other or even leave NC
CFG5 : LOW = DMI X 2
V
B B
CFG5<8>
HIGH = DMI X 4 (Default)
R245
2.2KOhm
/*
1 2
CFG7 : CPU STRAP
CFG7<8>
LOW = Mobile Prescott
V
HIGH = Dothan CPU (Default)
R251
2.2KOhm
/*
1 2
CFG9 : PCIE GRAPHIC LANE
CFG9<8>
R249
2.2KOhm
/*
1 2
CFG18 : GMCH CORE SELECT
+2.5VS
V
R238
1KOhm
/*
1 2
CFG18<8>
LOW = REVERSE LANE
V
HIGH = NORMAL OPERATION (Default)
LOW = 1.05V (Default)
HIGH = 1.5V
CFG16 : FSB DYNAMIC ODT
CFG16<8>
CFG [ 2 : 0 ]
533 0 0 1
400 1 0 1
SDVOCRTL_DATA :
LOW = No SDVO device present (Default)
CFG[17..3] have internal pullup resistors.
CFG[19..18] have internal pulldown resistors.
SDVOCRTL_DATA has internal pulldown resistors.
LOW = Dynamic ODT Disabled
V
HIGH = Dynamic ODT Enabled (Default)
R223
2.2KOhm
/*
1 2
CFG [13:12]
1 1 : Normal operation
1 0 : Z MODE
0 1 : Xor MODE
CFG19 : CPU VTT SELECT
+2.5VS
R239
1KOhm
/*
1 2
CFG19<8>
CFG6 : LOW = DDR2 SDRAM
HIGH = DDR SDRAM (Default)
CFG6<8>
R250
2.2KOhm
1 2
V
LOW = 1.05V (Default)
HIGH = 1.2V
V
A A
Title :
Alviso-GND/NCTF/Strap(5)
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
11 57Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
M_B_DQ[0..63] <9>
B102
B101
B100
B105
B116
B107
B106
B110
B115
B164
B166
B113
B108
B109
B198
B200
B197
B195
B114
B119
B130
B147
B170
B185
B131
B148
B169
B188
B129
B146
B167
B186
B111
B117
B103
B133
B183
B121
B193
B199
B99
B98
B97
B94
B92
B93
B91
B90
B89
B86
B84
B85
B30
B32
B79
B80
B10
B26
B52
B67
B13
B31
B51
B70
B11
B29
B49
B68
B95
B81
B87
B47
B77
B71
B41
B53
B59
B65
B1
R1.1-S20
CON21B
B:A0
B:A1
B:A2
B:A3
B:A4
B:A5
B:A6
B:A7
B:A8
B:A9
B:A10/AP
B:A11
B:A12
B:A13
B:A14
B:A15
B:A16_BA2
B:BA0
B:BA1
B:S0#
B:S1#
B:CK0
B:CK0#
B:CK1
B:CK1#
B:CKE0
B:CKE1
B:CBS#
B:RAS#
B:WE#
B:SA0
B:SA1
B:SCL
B:SDA
B:ODT0
B:ODT1
B:DM0
B:DM1
B:DM2
B:DM3
B:DM4
B:DM5
B:DM6
B:DM7
B:DQS0
B:DQS1
B:DQS2
B:DQS3
B:DQS4
B:DQS5
B:DQS6
B:DQS7
B:DQS0#
B:DQS1#
B:DQS2#
B:DQS3#
B:DQS4#
B:DQS5#
B:DQS6#
B:DQS7#
B:VDD2
B:VDD3
B:VDD5
B:VDD7
B:VDD9
B:VDD10
B:VSS1
B:VSS2
B:VSS3
B:VSS4
B:VSS9
B:VSS11
B:VSS14
B:VSS18
B:VSS19
B:VSS22
B:VSS23
B:VDDSPD
B:VREF
DDR_DIMM_331P
B:DQ0
B:DQ1
B:DQ2
B:DQ3
B:DQ4
B:DQ5
B:DQ6
B:DQ7
B:DQ8
B:DQ9
B:DQ10
B:DQ11
B:DQ12
B:DQ13
B:DQ14
B:DQ15
B:DQ16
B:DQ17
B:DQ18
B:DQ19
B:DQ20
B:DQ21
B:DQ22
B:DQ23
B:DQ24
B:DQ25
B:DQ26
B:DQ27
B:DQ28
B:DQ29
B:DQ30
B:DQ31
B:DQ32
B:DQ33
B:DQ34
B:DQ35
B:DQ36
B:DQ37
B:DQ38
B:DQ39
B:DQ40
B:DQ41
B:DQ42
B:DQ43
B:DQ44
B:DQ45
B:DQ46
B:DQ47
B:DQ48
B:DQ49
B:DQ50
B:DQ51
B:DQ52
B:DQ53
B:DQ54
B:DQ55
B:DQ56
B:DQ57
B:DQ58
B:DQ59
B:DQ60
B:DQ61
B:DQ62
B:DQ63
B:VSS26
B:VSS27
B:VSS29
B:VSS30
B:VSS31
B:VSS33
B:VSS34
B:VSS37
B:VSS38
B:VSS39
B:VSS40
B:VSS47
B:VSS48
B:VSS49
B:VSS50
B:VSS51
B:VSS52
B:NC1
B:NC2
B:NC3
B:NC4
B:NCTEST
B5
B7
B17
B19
B4
B6
B14
B16
B23
B25
B35
B37
B20
B22
B36
B38
B43
B45
B55
B57
B44
B46
B56
B58
B61
B63
B73
B75
B62
B64
B74
B76
B123
B125
B135
B137
B124
B126
B134
B136
B141
B143
B151
B153
B140
B142
B152
B154
B157
B159
B173
B175
B158
B160
B174
B176
B179
B181
B189
B191
B180
B182
B192
B194
B127
B139
B145
B165
B171
B177
B187
B9
B21
B33
B155
B3
B15
B27
B39
B149
B161
B83
B120
B50
B69
B163
M_B_DQ0
M_B_DQ6
M_B_DQ2
M_B_DQ3
M_B_DQ7
M_B_DQ1
M_B_DQ5
M_B_DQ4
M_B_DQ8
M_B_DQ9
M_B_DQ15
M_B_DQ14
M_B_DQ12
M_B_DQ13
M_B_DQ11
M_B_DQ10
M_B_DQ20
M_B_DQ16
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ29
M_B_DQ28
M_B_DQ26
M_B_DQ27
M_B_DQ24
M_B_DQ25
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ36
M_B_DQ34
M_B_DQ38
M_B_DQ33
M_B_DQ37
M_B_DQ39
M_B_DQ35M_B_DM1
M_B_DQ45
M_B_DQ44
M_B_DQ42
M_B_DQ47
M_B_DQ40
M_B_DQ41
M_B_DQ43
M_B_DQ46
M_B_DQ53
M_B_DQ48
M_B_DQ54
M_B_DQ50
M_B_DQ52
M_B_DQ49
M_B_DQ55
M_B_DQ51
M_B_DQ61
M_B_DQ56
M_B_DQ60
M_B_DQ58
M_B_DQ59
M_B_DQ57
M_B_DQ62
M_B_DQ63
GND
DDR2 DIMM SOCKET and
SCHEMATC is the same as A6V.
M_B_A[0..13]<9,14>
M_B_A0
M_B_A1
M_B_A2
M_B_A3
R2.0-S03
C734
0.1UF
c0402
M_B_DM0
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
GND
12
GND
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
C743
0.1UF
c0402
D D
C C
DCLK3
C722
PLACE NEAR SO-DIMM_0
10PF
c0402
1 2
DCLK3#
DCLK4
C723
PLACE NEAR SO-DIMM_0
10PF
c0402
1 2
DCLK4#
GND
+3VS
R724
10KOhm
1 2
r0402
M_B_BS#2<9,14>
M_B_BS#0<9,14>
M_B_BS#1<9,14>
SCS2#<8,14>
SCS3#<8,14>
DCLK3<8>
DCLK3#<8>
DCLK4<8>
DCLK4#<8>
SCKE2<8,14>
SCKE3<8,14>
M_B_CAS#<9,14>
M_B_RAS#<9,14>
M_B_WE#<9,14>
SCL_3S<13,21,28,35>
SDA_3S<13,21,28,35>
ODT2<8,14>
ODT3<8,14>
M_B_DM[0..7]<9>
M_B_DQS[0..7]<9>
M_B_DQS#[0..7]<9>
Layout Note: Place these High-Freq decoupling Caps near the GMCH
B B
+1.8V
GND
12
C727
0.1UF
c0402
12
12
C729
C728
0.1UF
0.1UF
c0402
c0402
GND
GND GND
12
C730
0.1UF
c0402
Layout Note: Place these resistors near the GMCH
+1.8V
A A
12
12
C737
2.2uF/6.3V
C738
2.2uF/6.3V
GNDGND GND
12
GND GND
C739
2.2uF/6.3V
12
C740
2.2uF/6.3V
12
C741
2.2uF/6.3V
Layout Note: Place these Caps near SO DIMM 0
+1.8V
12
C731
0.1UF
c0402
GND GND
+3VS
GND
VREF -> 10/10
mils
VTT_REF
Layout Note: Place these Caps near SO DIMM 0
GND
12
12
C735
0.1UF
c0402
C732
0.1UF
c0402
GND
GND
12
12
C736
0.1UF
c0402
C733
0.1UF
c0402
12
GND
12
C742
2.2uF/6.3V
Title :
DDR2 SO-DIMM_0
ASUSTECH CO.,LTD.
Size Project Name
Custom
5
4
3
2
Date: Sheet
Z61Ae
Engineer:
Sam Wang
Rev
2.0
of
1
12 57Thursday, June 09, 2005
5
4
3
2
1
M_A_A[0..13]<9,14>
M_A_A0
A102
M_A_A1
A101
M_A_A2 M_A_DQ2
A100
M_A_A3
M_A_A4
M_A_A5
M_A_A6
D D
DCLK0
C744
PLACE NEAR SO-DIMM_1
10PF
c0402
1 2
DCLK0#
DCLK1
C745
PLACE NEAR SO-DIMM_1
10PF
c0402
1 2
DCLK1#
R2.0-S03
C C
GND
GND
M_A_BS#2<9,14>
M_A_BS#0<9,14>
M_A_BS#1<9,14>
SCS0#<8,14>
SCS1#<8,14>
DCLK0<8>
DCLK0#<8>
DCLK1<8>
DCLK1#<8>
SCKE0<8,14>
SCKE1<8,14>
M_A_CAS#<9,14>
M_A_RAS#<9,14>
M_A_WE#<9,14>
SCL_3S<12,21,28,35>
SDA_3S<12,21,28,35>
ODT0<8,14>
ODT1<8,14>
M_A_DM[0..7]<9>
M_A_DQS[0..7]<9>
M_A_DQS#[0..7]<9>
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6 M_A_DQ55
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
A99
A98
A97
A94
A92
A93
A91
A105
A90
A89
A116
A86
A84
A85
A107
A106
A110
A115
A30
A32
A164
A166
A79
A80
A113
A108
A109
A198
A200
A197
A195
A114
A119
A10
A26
A52
A67
A130
A147
A170
A185
A13
A31
A51
A70
A131
A148
A169
A188
A11
A29
A49
A68
A129
A146
A167
A186
CON21A
A:A0
A:A1
A:A2
A:A3
A:A4
A:A5
A:A6
A:A7
A:A8
A:A9
A:A10/AP
A:A11
A:A12
A:A13
A:A14
A:A15
A:A16_BA2
A:BA0
A:BA1
A:S0#
A:S1#
A:CK0
A:CK0#
A:CK1
A:CK1#
A:CKE0
A:CKE1
A:CAS#
A:RAS#
A:WE#
A:SA0
A:SA1
A:SCL
A:SDA
A:ODT0
A:ODT1
A:DM0
A:DM1
A:DM2
A:DM3
A:DM4
A:DM5
A:DM6
A:DM7
A:DQS0
A:DQS1
A:DQS2
A:DQS3
A:DQS4
A:DQS5
A:DQS6
A:DQS7
A:DQS0#
A:DQS1#
A:DQS2#
A:DQS3#
A:DQS4#
A:DQS5#
A:DQS6#
A:DQS7#
R1.1-S20
A:DQ0
A:DQ1
A:DQ2
A:DQ3
A:DQ4
A:DQ5
A:DQ6
A:DQ7
A:DQ8
A:DQ9
A:DQ10
A:DQ11
A:DQ12
A:DQ13
A:DQ14
A:DQ15
A:DQ16
A:DQ17
A:DQ18
A:DQ19
A:DQ20
A:DQ21
A:DQ22
A:DQ23
A:DQ24
A:DQ25
A:DQ26
A:DQ27
A:DQ28
A:DQ29
A:DQ30
A:DQ31
A:DQ32
A:DQ33
A:DQ34
A:DQ35
A:DQ36
A:DQ37
A:DQ38
A:DQ39
A:DQ40
A:DQ41
A:DQ42
A:DQ43
A:DQ44
A:DQ45
A:DQ46
A:DQ47
A:DQ48
A:DQ49
A:DQ50
A:DQ51
A:DQ52
A:DQ53
A:DQ54
A:DQ55
A:DQ56
A:DQ57
A:DQ58
A:DQ59
A:DQ60
A:DQ61
A:DQ62
A:DQ63
A5
A7
A17
A19
A4
A6
A14
A16
A23
A25
A35
A37
A20
A22
A36
A38
A43
A45
A55
A57
A44
A46
A56
A58
A61
A63
A73
A75
A62
A64
A74
A76
A123
A125
A135
A137
A124
A126
A134
A136
A141
A143
A151
A153
A140
A142
A152
A154
A157
A159
A173
A175
A158
A160
A174
A176
A179
A181
A189
A191
A180
A182
A192
A194
M_A_DQ5
M_A_DQ4
M_A_DQ7
M_A_DQ0
M_A_DQ1
M_A_DQ6
M_A_DQ3
M_A_DQ9
M_A_DQ12
M_A_DQ14
M_A_DQ15
M_A_DQ8
M_A_DQ13
M_A_DQ10
M_A_DQ11
M_A_DQ21
M_A_DQ23
M_A_DQ19
M_A_DQ22
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ20
M_A_DQ28
M_A_DQ29
M_A_DQ26
M_A_DQ27
M_A_DQ24
M_A_DQ25
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ35
M_A_DQ34
M_A_DQ37
M_A_DQ36
M_A_DQ38
M_A_DQ39
M_A_DQ45
M_A_DQ40
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ44
M_A_DQ47
M_A_DQ46
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ48
M_A_DQ49
M_A_DQ54
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQ57
M_A_DQ56
M_A_DQ58
M_A_DQ59
M_A_DQ[0..63] <9>
Layout Note: Place these Caps near SO DIMM 1
B B
Layout Note: Place these Caps near SO DIMM 1
+1.8V
12
C750
2.2uF/6.3V
12
C751
2.2uF/6.3V
GNDGND GNDGND
12
C752
2.2uF/6.3V
GND
12
C753
2.2uF/6.3V
12
C754
2.2uF/6.3V
SO-DIMM 1 is placed father from
the GMCH than SO-DIMM 0
A A
+1.8V
GND
12
C746
0.1UF
c0402
12
C747
0.1UF
c0402
GND GND
+3VS
VTT_REF
VREF -> 10/10
mils
12
GND
C748
0.1UF
c0402
12
C755
0.1UF
c0402
GND
12
C749
0.1UF
c0402
GND
12
C756
0.1UF
c0402
GND
12
GND
C757
2.2uF/6.3V
GND
12
C758
0.1UF
c0402
A112
A:VDD1
A96
A:VDD4
A118
A:VDD6
A82
A:VDD8
A88
A:VDD11
A104
A:VDD12
A12
A:VSS5
A48
A:VSS6
A184
A:VSS7
A78
A:VSS8
A72
A:VSS10
A122
A:VSS12
A196
A:VSS13
A8
A:VSS15
A18
A:VSS16
A24
A:VSS17
A42
A:VSS20
A199
A:VDDSPD
A1
A:VREF
DDR_DIMM_331P
NP_NC1
201
202
NP_NC2
NP_NC3
203
204
NP_NC4
205
GND1
206
GND2
208
GND3
207
GND4
A:VSS21
A:VSS24
A:VSS25
A:VSS28
A:VSS32
A:VSS35
A:VSS36
A:VSS41
A:VSS42
A:VSS43
A:VSS44
A:VSS45
A:VSS46
A:VSS53
A:VSS54
A:VSS55
A:VSS56
A:VSS57
A:NC1
A:NC2
A:NC3
A:NC4
A:NCTEST
A54
A60
A66
A128
A172
A178
A190
A34
A132
A144
A156
A168
A2
A28
A40
A138
A150
A162
A83
A120
A50
A69
A163
GND
DDR2 DIMM SOCKET and SCHEMATC
is the same as A6V.
Title :
DDR2 SO-DIMM_1
ASUSTECH CO.,LTD.
Size Project Name
Custom
5
4
3
2
Date: Sheet
Z61Ae
Engineer:
Sam Wang
Rev
2.0
of
1
13 57Thursday, June 09, 2005
5
D D
R1.1-S28
C C
+0.9VS
12
C692
0.1UF
12
12
C693
0.1UF
C694
0.1UF
12
Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
+0.9VS
12
12
12
C706
B B
C705
0.1UF
0.1UF
C707
0.1UF
12
C695
0.1UF
C708
0.1UF
4
M_A_A[0..13] <9,13>
M_A_BS#[0..2] <9,13>
M_B_A[0..13] <9,12>
M_B_BS#[0..2] <9,12>
SCKE[0:3] <8,12,13>
ODT[0:3] <8,12,13>
12
C696
0.1UF
12
C709
0.1UF
12
12
C697
0.1UF
12
C710
0.1UF
12
C698
0.1UF
12
C711
0.1UF
12
C699
C700
0.1UF
0.1UF
12
12
C713
C712
0.1UF
0.1UF
12
12
C701
0.1UF
12
C714
0.1UF
12
C702
0.1UF
12
12
C715
0.1UF
C703
0.1UF
C716
0.1UF
3
+0.9VS
R685 56Ohm
1 2
R686 56Ohm
1 2
R687 56Ohm
1 2
R688 56Ohm
1 2
R689 56Ohm
1 2
R690 56Ohm
1 2
R691 56Ohm
1 2
R692 56Ohm
1 2
R693 56Ohm
1 2
R694 56Ohm
1 2
R696 56Ohm
1 2
R697 56Ohm
1 2
R699 56Ohm
1 2
R700 56Ohm
1 2
R701 56Ohm
1 2
R702 56Ohm
1 2
R703 56Ohm
1 2
R704 56Ohm
1 2
R705 56Ohm
1 2
R706 56Ohm
1 2
R707 56Ohm
1 2
R708 56Ohm
12
C704
0.1UF
12
C717
0.1UF
1 2
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
RN56A
RN56B
RN56C
RN56D
RN56E
RN56F
RN56G
RN56H
RN57A
RN57B
RN57C
RN57D
RN57E
RN57F
RN57G
RN57H
RN58A
RN58B
RN58C
RN58D
RN58E
RN58F
RN58G
RN58H
RN59A
RN59B
RN59C
RN59D
RN59E
RN59F
RN59G
RN59H
2
SCKE0
SCKE1
SCKE2
SCKE3
ODT0
ODT1
ODT2
ODT3
M_A_A13
M_A_BS#1
M_B_A12
M_A_RAS#
M_B_BS#2
M_B_A10
M_B_A3
M_B_CAS#
M_B_A5
M_B_WE#
SCS0#
SCS1#
SCS2#
SCS3#
M_A_CAS#
M_A_BS#0
M_A_WE#
M_B_BS#0
M_A_A10
M_A_A1
M_B_A13
M_B_RAS#
M_B_BS#1
M_B_A0
M_B_A2
M_B_A6
M_A_A8
M_B_A11
M_A_A0
M_A_A2
M_A_A4
M_A_A6
M_A_A7
M_A_A11
M_B_A4
M_B_A7
M_B_A1
M_A_A5
M_A_A3
M_A_A9
M_B_A8
M_B_A9
M_A_A12
M_A_BS#2
M_A_RAS# <9,13>
M_B_CAS# <9,12>
M_B_WE# <9,12>
SCS0# <8,13>
SCS1# <8,13>
SCS2# <8,12>
SCS3# <8,12>
M_A_CAS# <9,13>
M_A_WE# <9,13>
M_B_RAS# <9,12>
1
A A
DDR2 TERMINATION
Title :
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
14 57Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
TO SUPPORT SPWG PANEL(EDID)
+2.5VS
Q146
2N7002
/*
3
D
Q147
1
2N7002
G
S
/*
2
3
D
D D
DDCDATA_GM<8>
DDCCLK_GM<8>
C C
1
G
S
2
PID_0
PID_1
L21
1KOhm/100MHz
PID_0<24>
PID_1<24>
R25
10KOhm
+3VS
2 1
2 1
L23
1KOhm/100MHz
R37
10KOhm
1 2
1 2
12
C271000PF
12
C251000PF
A theoretical maximum limit is calculated at 1.923 Gbit/s
C800
1 2
0.1UF
L22
+LCD_VCC
LVDS_CLKBM_GM<8>
LVDS_CLKBP_GM<8>
LVDS_YB1M_GM<8>
LVDS_YB1P_GM<8>
LVDS_YB2P_GM<8>
LVDS_YB2M_GM<8>
LVDS_YB0P_GM<8>
LVDS_YB0M_GM<8>
LVDS_CLKAM_GM<8>
LVDS_CLKAP_GM<8>
LVDS_YA2P_GM<8>
LVDS_YA2M_GM<8>
LVDS_YA1P_GM<8>
LVDS_YA1M_GM<8>
LVDS_YA0M_GM<8>
LVDS_YA0P_GM<8>
LVDS_CLKBM_GM
LVDS_CLKBP_GM
LVDS_YB1M_GM
LVDS_YB1P_GM
LVDS_YB2P_GM
LVDS_YB2M_GM
LVDS_YB0P_GM
LVDS_YB0M_GM
LVDS_CLKAM_GM
LVDS_CLKAP_GM
LVDS_YA2P_GM
LVDS_YA2M_GM
LVDS_YA1P_GM
LVDS_YA1M_GM
LVDS_YA0M_GM
LVDS_YA0P_GM
21
120Ohm/100Mhz
LVDS
+3VS
CON2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
hold_gnd2
hold_gnd1
CON Part Number Modify as M3N
35
31
32
33
34
LVDS default Cable is 08-20C28012N.(None EDID function)
It default PID setting is PID_0 = 1 and PID_1 = 0 on cable.
36
To support EDID function that need new cable.
Panel ID is LCD vendor apply to system
WtoB_2P
Panel Size Resolution Pixels Aspect Ratio
14.1” XGA 1024 x 768 4:3
14.1” SXGA+ 1400 x 10504:3
14.1” UXGA 1600 x 12004:3
CNT
S
D
Q4
3
2
G
2N7002
1
+3VSUS +12VS
B B
LCD_VDD_EN_GM<8>
R46
10KOhm
A A
5
R24
10KOhm
1 2
D5
1 2
RB751V_40
R47
12
470KOhm
3
D
Q3
1
2N7002
G
S
2
1 2
R41
1MOhm
1 2
R858
LCDVCC_ON
0Ohm
1 2
3
D
Q6
1
2N7002
G
S
2
12
C64
0.01UF
12
4
C51
0.01UF
G
D
S
564
80Ohm/100Mhz
12
123
C31
0.1UF
Q2
SI3456DV
L24
21
1 2
100Ohm
3 4
100Ohm
+3VS
+LCD_VCC
12
C30
0.1UF
RN2A
RN2B
12
C42
1UF/10V
12
ADJ_BL_GM<8>
To support PWM inverter.
ADJ_BL<27>
LID_SW#<40,43>
12
R340
1KOhm
C41
10UF/10V
3
3
+LCD_VCC
VCC
GND
R21 100KOhm
+3V
147
U42A
1
2
LV08A
1 2
1
2
R342
10KOhm
12
D3
RB717F
3
L91
1KOhm/100MHz
2 1
/*
L17
2 1
1KOhm/100MHz
L14
2 1
1KOhm/100MHz
AC_BAT_SYS
2 1
80Ohm/100Mhz
12
12
C15
0.1UF
BACK_OFF# <17,20>
LCD_BACKEN_GM <8>
L8
C20
0.1UF
2
+VCC_INVERTOR
1A
12
C11
0.1UF/25V
INVERTOR
CNT
Date: Sheet
CON Part Number Modify as M3N
CON1
1
VCC1
2
VCC2
3
GND1
4
GND2
5
VREF
6
BKEN
7
PWM
WTOB_CON_7P
ASUSTECH CO.,LTD.
Size Project Name
C
Z61Ae
8
9
8
9
1
Title :
Engineer:
LVDS & INVERTER CONN.
Sam Wang
of
15 57Thursday, June 09, 2005
Rev
2.0
5
4
3
2
1
CON Part Number Modify as M3N
1
2
3
13
14
12
15
7846S_15G2T
CON10
RED
GREEN
BLUE
HSYNC
VSYNC
DATA
DCLK
VCC
NC1
NC2
15
PIN
CRT
1
SIDE_G16
SIDE_G17
GND2
GND3
GND4
GND510GND1
6
7
8
5
9
4
11
16
17
D D
+12VS
12
+3VS
R318
RN27D
2.2KOhm
DAC_R
DAC_G
DAC_B
0Ohm
Q53A UM6K1N
2
5
Q53BUM6K1N
3
1
G
2
61
34
D
Q55
S
2N7002
R317 39Ohm
R325 0Ohm
+5VS_CRT
RN27A
2.2KOhm
1 2
3
D
1
G
S
2
1 2
RN27B
2.2KOhm
3 4
Q54
2N7002
12
DDC2BD_5
DDC2BC_5
U40
B
1
5
VCC
A
DAC_VSYNC_GM<8>
DAC_HSYNC_GM<8>
C C
+2.5VS
B B
DDC2BD_GM<8>
DDC2BC_GM<8>
2
3 4
GND
Y
VCC
Y
5 6
5
DAC_IO_P
RN27C
2.2KOhm
+3VS
7 8
U39
74LVC1G32GV
B
1
A
2
3 4
GND
74LVC1G32GV
DAC_R_GM<8>
DAC_G_GM<8>
DAC_B_GM<8>
Zo= 50 ohm
VSYNC_CRT
HSYNC_Q
DAC_R_CRT
DAC_G_CRT
DAC_B_CRT
DAC_IO_P
DAC_R_CRT
DAC_B_CRT
DAC_G_CRT
R319
1%
150Ohm
1 2
12
C6
47pF/50V
12
RED
GREEN
BLUE
DDC2BD
HSYNC
VSYNC
DDC2BC
C8
47pF/50V
12
C2
47pF/50V
21
L1 0.068UH
21
L2 0.068UH
21
DDC2BD_5
HSYNC_CRT
VSYNC_CRT
C350
8.2PF/50V
/*
+12VS
+5VS
12
C351
8.2PF/50V
/*
1 2
PR_IN#
DAC_R_PB
DAC_R_CRT
DAC_R
DAC_G_PB
DAC_G_CRT
DAC_G
DAC_R_PB<26>
DAC_G_PB<26>
DAC_B_PB<26>
DDC2BD_5<26>
DDC2BC_5<26>
HSYNC_PB<26>
VSYNC_PB<26>
DDC2BC_5
R326
10KOhm
1.2PF/50V
U10
1
2
3
4
5
6
7
8
12
C346
/*
Intel Recommend
C = 10pF / 22pF / 10pF
Bead = 47 ohm /100Mhz
1
Q59 2N7002
G
3
2
D
S
16
IN
VCC
15
S1A
EN#
14
S2A
S1D
13
DA
S2D
12
S1B
DD
11
S2B
S1C
10
DB
S2C
9
GND
DC
PI5V330W16
IN : 0 = S1
: 1 = S2
DAC_R_PB
DAC_G_PB
DAC_B_PB
DDC2BD_5
DDC2BC_5
HSYNC_PB
VSYNC_CRT
R321
12
C349
1%
150Ohm
1 2
8.2PF/50V
/*
R320
1%
150Ohm
1 2
D25
1
3
2
BAV99
D26
1
3
2
BAV99
D27
1
3
2
BAV99
12
PR_IN#<26>
L3 0.068UH
L6 120Ohm/100Mhz
L7 120Ohm/100Mhz
L4 120Ohm/100Mhz
L5 120Ohm/100Mhz
12
C348
1.2PF/50V
/*
12
C347
1.2PF/50V
/*
+5VS_CRT
+5V
HSYNC_PBS
HSYNC_CRTS
HSYNC_Q
DAC_B_PB
DAC_B_CRT
DAC_B
R343 39Ohm
1 2
21
21
21
21
12
C3
8.2PF/50V
1 2
R38 39Ohm
HSYNC_PBS
12
C4
8.2PF/50V
HSYNC_CRT
12
C7
8.2PF/50V
12
C5
47pF/50V
RED
GREEN
BLUE
HSYNC
VSYNC
DDC2BD
DDC2BC
To PortBar III
A A
Title :
CRT
ASUSTECH CO.,LTD.
Size Project Name
C
5
4
3
2
Date: Sheet
Engineer:
Z61Ae
1
Sam Wang
of
16 57Thursday, June 09, 2005
Rev
2.0
5
U15 Original P/N is 02-010002500(ICH6-M-None MP Version)
U15 (SB) need to change to 02-010004402(ICH6-M-MP B2 Version)
R1.1 has changed it in symbol.
R1.1-S22
SATA_ICH_TXN0
AD13
AG15
AE15
AC13
AB13
AB12
AF13
AE13
AB11
AD11
AC11
AE14
AD12
AF14
AF15
AD14
AB15
AB14
AE16
AC14
AF16
AC16
AB17
AC17
AD16
AE17
AB16
SATA_ICH_TXP0
U15C
DD_15
DD_14
DD_13
DD_12
DD_11
DD_10
DD_9
DD_8
DD_7
DD_6
DD_5
DD_4
DD_3
DD_2
DD_1
DD_0
DDACK#
DDREQ
DIOR#
DIOW#
IORDY
DA0
DA1
DA2
DCS1#
DCS3#
IDEIRQ
ICH6_M
02-010004402
D D
IDE_PDD[0..15]<22>
C C
B B
R86
10MOhm
1 2
IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDDACK#<22>
IDE_PDDREQ<22>
IDE_PDIOR#<22>
IDE_PDIOW#<22>
IDE_PIORDY<22>
IDE_PDA0<22>
IDE_PDA1<22>
IDE_PDA2<22>
IDE_PDCS1#<22>
IDE_PDCS3#<22>
INT_IRQ14<20,22>
RTC_X2RTC_X1
SATA_0RXN
SATA_0RXP
SATA_0TXN
SATA_0TXP
SATA_1RXN
SATA_1RXP
SATA_1TXN
SATA_1TXP
SATA_2RXN
SATA_2RXP
SATA_2TXN
SATA_2TXP
SATA_3RXN
SATA_3RXP
SATA_3TXN
SATA_3TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
SMBCLK
SMBDATA
LINKALERT#
SMLINK_0
SMLINK_1
SATALED#
SATA_0GP/GPI26
SATA_1GP/GPI29
SATA_2GP/GPI30
SATA_3GP/GPI31
INTRUDER#
RSMRST#
RTCX1
RTCX2
RTCRST#
INTVRMEN
SPKR
4
12
C763 3900PF/50V
12
C764 3900PF/50V
PLACE CLOSELY TOGETHER
SATA_ICH_RXN0
AE3
SATA_ICH_RXP0
AD3
SATA_ICH_TXN0
AG2
SATA_ICH_TXP0
AF2
AC5
AD5
AF4
AG4
AD7
AC7
AF6
AG6
AC9
AD9
AF8
AG8
AC2
AC1
AG11
AF11
R1.1-S35
1 2
1 2
0Ohm
3 4
0Ohm
5 6
0Ohm
7 8
0Ohm
CLK_PCIE_SATA# <21>
CLK_PCIE_SATA <21>
R122
24.9Ohm
1%
R1.1-S22
Y4
W5
Y5
W4
U6
AC19
AF17
AE18
AF18
AG18
AA3
Y3
Y1
Y2
AA2
AA5
F8
SCL_3A <20,28>
SDA_3A <20,28>
SATA[x]GP pins if unused require
8.2-k to 10-k pull-up to Vcc3_3.
LINKALERT# <20>
SM_LINK0 <20,28>
SM_LINK1 <20,28>
R1.1-S22
1 2
1 2
8.2KOhm
RTC_X1
RTC_X2
RTC_RST#
1 2
R391 10KOhm
1 2
ICH_SPKR <20,37>
SATALED# <22>
PCB_VID2 <20>
12
R1.1 _ NO17
+3VSUS
/*
R123 8.2KOhm
R124
R111 1MOhm
R390 0Ohm
R1.1-S34
RTC CMOS CLEAR
(RTC_CLR)
Azalia_BCLK_R
Azalia_SYNC
Azalia_RST#
Azalia_SDOUT
SATA_BRIDGE_RXN0 <22>
SATA_BRIDGE_RXP0 <22>
SATA_ICH_RXN0 <22>
SATA_ICH_RXP0 <22>
RN61A
RN61B
RN61C
RN61D
+3VS
+VCCP
+3VS
H_FERR#<4>
ACIN_OC_3 <27>
+VCC_RTC
PM_RSMRST# <43>
+VCC_RTC
1
JRST1
1
SGL_JUMP
2
/*
2
3
1 2
RA8 39Ohm
1 2
RA3 39Ohm
1 2
RA6 39Ohm
1 2
RA2 39Ohm
1 2
RA7 39Ohm
1 2
RA4 39Ohm
1 2
RA5 39Ohm
1 2
RA1 39Ohm
Unused SATA pin
- Connect RX, RBIAS, CLK to GND
- Leave TX, LED# as NC
BATSEL_2P<20>
LPC_AD0<24,27,33,36>
LPC_AD1<24,27,33,36>
LPC_AD2<24,27,33,36>
LPC_AD3<24,27,33,36>
LPC_DRQ#0<20,24>
LPC_FRAME#<24,27,33,36>
Azalia_BCLK_R
Azalia_RST#
Azalia_SDIN0<37>
Azalia_SDIN1<39>
Azalia_SDOUT<20>
Azalia_SYNC<20>
CLK_ICH14<21>
EEP_DOUT<20>
EE_DOUT: Internal weak pull up
EE_CS: Internal weak pull down
56Ohm
R423
1 2
12
R106
20KOhm
12
C141
1UF/10V
X7R
R32 0Ohm
R31 0Ohm
R29 0Ohm
R30 0Ohm
H_CPUSLP# R94 : B STEP NO STUFF
H_DPRSTP# R95 : A STEP NO STUFF
HA20GATE<27>
H_A20M#<4>
H_CPUSLP#<4,7>
PM_DPRSLPVR<44>
H_DPRSTP#<4>
H_DPSLP#<4>
H_IGNNE#<4>
FWH_INIT#<36>
H_INIT#<4>
H_INTR<4>
H_NMI<4>
KBDCPURST<27>
INT_SERIRQ<20,24,27,32>
H_SMI#<4>
H_STPCLK#<4>
H_THRMTRIP#<6>
Azalia_BCLK_AUD <37>
Azalia_SYNC_AUD <37>
Azalia_RST#_AUD <37,38>
Azalia_SDOUT_AUD <37>
Azalia_BCLK_MDC <39>
Azalia_SYNC_MDC <39>
Azalia_RST#_MDC <39>
Azalia_SDOUT_MDC <39>
R72 0Ohm
1 2
R68 0Ohm
1 2
R63 0Ohm
1 2
R64 0Ohm
1 2
R74 0Ohm
1 2
C22 10PF /*
1 2
1 2
1 2
1 2
R197 0Ohm/*
1 2
R420 0Ohm/*
1 2
R422 56Ohm
1 2
BATSEL_2P
12
T219
R126
56Ohm
2
R421
12
U15D
P4
LDRQ_1#/GPIO41
P2
LAD_0/FWH0
N3
LAD_1/FWH1
N5
LAD_2/FWH2
N4
LAD_3/FWH3
N6
LDRQ_0#
P3
LFRAME#/FWH4
C10
ACZ_BIT_CLK
A10
ACZ_RST#
F11
ACZ_SDIN_0
F10
ACZ_SDIN_1
B10
ACZ_SDIN_2
C9
ACZ_SDOUT
B9
ACZ_SYNC
E10
CLK14
D12
1
12
AF22
AF23
AE27
AE20
AE24
AD27
AG26
AE22
AF27
AG24
AF24
AF25
AD23
AB20
AG27
AE26
AE23
F13
D11
B12
F12
B11
E12
E11
C13
C12
C11
E13
EE_CS
EE_DIN
EE_DOUT
EE_SHCLK
LAN_CLK
LAN_RSTSYNC
LAN_RXD_0
LAN_RXD_1
LAN_RXD_2
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
A20GATE
A20M#
CPUSLP#
DPRSLPVR/TP_1
DPRSLP#/TP_2
DPSTP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THRMTRIP#
ICH6_M
02-010004402
BMBUSY#/GPI6
SMBALERT#/GPIO11
STP_PCI#/GPO18
STP_CPU#/GPO20
CLKRUN#/GPIO32
CPUPWRGD/GPIO49
SUS_STAT#/LPCPD#
GPI7
GPI8
GPI12
GPI13
GPIO19
GPIO21
GPIO23
GPIO24
GPIO25
GPIO27
GPIO28
GPIO33
GPIO34
MCH_SYNC#
PWRBTN#
SLP_S3#
SLP_S4#
SLP_S5#
SUSCLK
SYS_RESET#
LAN_RST#
BATLOW#
TP_3
VRMPWRGD
THRM#
WAKE#
PWROK
RI#
AD19
AE19
R1
W6
M2
R6
AC21
AB21
AD22
AD20
AD21
V3
P5
R3
T3
AF19
AF20
AC18
AG25
AG21
U1
T2
T4
T5
T6
W3
V6
U2
V5
V2
U3
AF21
AC20
U5
AA1
SUSCLK
LAN_RST#
BAT1_LLOW#_ICH6
SB_GPIO19
XIDE_EN#_3
1
T229
ICH6_PWROK
1KOhm
ICH6_PWROK
8.2KOhm
MCH_SYNC# <20>
PM_PWRBTN# <43>
PM_RI# <20>
PM_SUSB# <4,21,29,32,37,40,43,48,52>
PM_SUSC# <43,52>
PM_SUS_STAT# <20,24>
T230
1
1 2
/*
1 2
1 2
R87 0Ohm
R84 0Ohm/*
R85 10KOhm
1 2
PM_THRM# <20,35>
R75
12
ICH6_PWROK <8,43>
+3VS
PM_BMBUSY# <8>
GPI7 <20>
EXTSMI#_3A <27>
LID_ICH#_3A <20,43>
KBDSCI_3 <27>
BAT1_LLOW#_ICH6 <20>
STP_PCI# <21>
STP_CPU# <21,44>
BACK_OFF# <15,20>
FWH_WP# <20,36>
CB_SD# <20,32>
ICH6_1HZ <40>
PCB_VID0 <20>
PCB_VID1 <20>
PM_CLKRUN# <20,24,27,31,32>
OP_SD# <20,38>
H_PWRGD <4>
AUXPWROK <43>
+3VSUS
R7810KOhm
H_DBRESET# <4,6>
R810Ohm
BUF_PLT_RST# <6,8,18,22,24,27,36>
PM_BATLOW# <20>
TP3 <20>
12
BAT_LLOW#_OC <51>
+3VSUS
1
+3VS
12
R786
8.2KOhm
/*
1
R2.0-S09
R2.0-S07
T350
CHECK_MODE <40>
XIDE_EN#_3 <22>
R1.1-S22
2
Y1
12
C131
15P
A A
R2.0-S03
112
SIDE
32.768KHZ CITIZEN 12.5PF/20PPM
3
07-010303271
GND
5
12
C130
15P
BAT1_LLOW#<48,51>
NC1
SPKL-
SPKL+
NC2
WtoB_2P
U36
3
1
2
4
D7
RB751V_40
BAT1_LLOW#_ICH6
12
C340
12
0.1UF
/*
RTC_BAT
T35
1
R130
1KOhm
+VCC_RTC+3VALWAYS
D10
2
12
3
1
RB715F
12
C147
1UF/10V
BATSEL_2P#<49,50>
CON Part Number Modify as ME
RTC BAT
4
3
2
BATSEL_2P
3
D
Q9
1
2N7002
G
S
/*
2
ASUSTECH CO.,LTD.
Size Project Name
C
Date: Sheet
Engineer:
Z61Ae
1
Title :
ICH6M--SATA/LPC/IDE/PM (1)
Sam Wang
of
17 57Thursday, June 09, 2005
Rev
2.0
5
D D
PCI_PAR<29,31,32>
PCI_DEVSEL#<20,29,31,32>
CLK_ICHPCI<21>
PCI_IRDY#<20,29,31,32>
PME_SB#<20,29>
PCI_SERR#<20,29,31,32>
PCI_STOP#<20,29,31,32>
PCI_LOCK#<20>
PCI_TRDY#<20,29,31,32>
PCI_PERR#<20,29,31,32>
PCI_FRAME#<20,29,31,32>
PCI_GNT#0<29>
PCI_GNT#1<32>
PCI_GNT#3<31>
GPIO17<20>
GPIO16<20>
PCI_REQ#0<20,29>
PCI_REQ#1<20,32>
PCI_REQ#2<20>
C C
PCI_REQ#3<20,31>
PCB_VID3<20>
KBDDT1<20,27>
KBDDT0<20,27>
PCI_INTA#<20,32>
PCI_INTB#<20,31,32>
PCI_INTC#<20,29,32>
PCI_INTD#<20,31>
PCI_INTE#<20>
PCI_INTF#<20>
PCI_INTG#<20>
PCI_INTH#<20>
T222
T221
PCI_RST#_ICH
PLT_RST#_SB
PCI_GNT#2
1
1
4
E1
C3
G6
R2
R5
A3
P6
G5
J1
C5
J2
E3
J3
C1
B6
F1
C8
E7
F6
D8
L5
B5
M5
B8
F7
E8
B7
N2
L2
M1
L3
D9
C7
C6
M3
U15A
PAR
DEVSEL#
PCICLK
PCIRST#
PLTRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#
GNT_0#
GNT_1#
GNT_2#
GNT_3#
GNT_4#/GPIO48
GNT_5#/GPIO17
GNT_6#/GPIO16
REQ_0#
REQ_1#
REQ_2#
REQ_3#
REQ_4#/GPIO40
REQ_5#/GPIO1
REQ_6#/GPIO0
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
AD_0
AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
AD_8
AD_9
AD_10
AD_11
AD_12
AD_13
AD_14
AD_15
AD_16
AD_17
AD_18
AD_19
AD_20
AD_21
AD_22
AD_23
AD_24
AD_25
AD_26
AD_27
AD_28
AD_29
AD_30
AD_31
C_BE_3#
C_BE_2#
C_BE_1#
C_BE_0#
3
PCI_AD0
E2
PCI_AD1
E5
PCI_AD2
C2
PCI_AD3
F5
PCI_AD4
F3
PCI_AD5
E9
PCI_AD6
F2
PCI_AD7
D6
PCI_AD8
E6
PCI_AD9
D3
PCI_AD10
A2
PCI_AD11
D2
PCI_AD12
D5
PCI_AD13
H3
PCI_AD14
B4
PCI_AD15
J5
PCI_AD16
K2
PCI_AD17
K5
PCI_AD18
D4
PCI_AD19
L6
PCI_AD20
G3
PCI_AD21
H4
PCI_AD22
H2
PCI_AD23
H5
PCI_AD24
B3
PCI_AD25
M6
PCI_AD26
B2
PCI_AD27
K6
PCI_AD28
K3
PCI_AD29
A5
PCI_AD30
L1
PCI_AD31
K4
G2
G4
H6
J6
PCI_C/BE#3 <29,31,32>
PCI_C/BE#2 <29,31,32>
PCI_C/BE#1 <29,31,32>
PCI_C/BE#0 <29,31,32>
PCI_AD[0..31] <29,31,32>
DMI_RXN0<8>
DMI_RXP0<8>
DMI_RXN1<8>
DMI_RXP1<8>
DMI_RXN2<8>
DMI_RXP2<8>
DMI_RXN3<8>
DMI_RXP3<8>
+1.5VS
DMI_TXN0<8>
DMI_TXP0<8>
DMI_TXN1<8>
DMI_TXP1<8>
DMI_TXN2<8>
DMI_TXP2<8>
DMI_TXN3<8>
DMI_TXP3<8>
T23
T21
T24
T225
T227
T226
T32
T29
R360
1 2
24.9Ohm
1
1
1
1
1
1
1
1
AB24
AB23
AA27
AA26
T25
T24
R27
R26
V25
V24
U27
U26
Y25
Y24
W27
W26
H25
H24
G27
G26
K25
K24
J27
J26
M25
M24
L27
L26
P24
P23
N27
N26
F24
F23
U15B
DMI_0RXN
DMI_0RXP
DMI_0TXN
DMI_0TXP
DMI_1RXN
DMI_1RXP
DMI_1TXN
DMI_1TXP
DMI_2RXN
DMI_2RXP
DMI_2TXN
DMI_2TXP
DMI_3RXN
DMI_3RXP
DMI_3TXN
DMI_3TXP
HSIN_0
HSIP_0
HSON_0
HSOP_0
HSIN_1
HSIP_1
HSON_1
HSOP_1
HSIN_2
HSIP_2
HSON_2
HSOP_2
HSIN_3
HSIP_3
HSON_3
HSOP_3
DMI_ZCOMP
DMI_IRCOMP
2
USBP_0N
USBP_0P
USBP_1N
USBP_1P
USBP_2N
USBP_2P
USBP_3N
USBP_3P
USBP_4N
USBP_4P
USBP_5N
USBP_5P
USBP_6N
USBP_6P
USBP_7N
USBP_7P
OC_0#
OC_1#
OC_2#
OC_3#
OC_4#/GPIO9
OC_5#/GPIO10
OC_6#/GPIO14
OC_7#/GPIO15
USBRBIAS
USBRBIAS#
CLK48
C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14
C27
B27
B26
C26
C23
D23
C25
C24
B22
A22
A27
BAT2_LLOW#_ICH6
USBRBIAS
PLACE within
500 mils of
ICH.
R26
1 2
22.6Ohm
1%
CLK_USB48 <21>
USB_PN0 <23>
USB_PP0 <23>
USB_PN1 <23>
USB_PP1 <23>
USB_PN2 <26>
USB_PP2 <26>
USB_PN3 <23>
USB_PP3 <23>
USB_PN4 <23>
USB_PP4 <23>
USB_PN5 <31>
USB_PP5 <31>
USB_OC#01 <23>
USB_OC#23 <23>
USB_OC#4 <20>
USB_OC#5 <20>
BAT2_LLOW#_ICH6 <20>
GPIO15 <20>
1
PLACE within 500 mils of ICH.
+3V
U42B
147
VCC
D32
RB751V_40
GND
PCI_RST#
12
C445
0.01UF
BAT2_LLOW#_ICH6
12
4
5
LV08A
12
U45
B
1
VCC
A
2
3 4
GND
74LVC1G32GV
0.1UF
Y
ICH6_M
02-010004402
+3V
C443
5
4
PCI_RST#<22,29,31,32>
BUF_PLT_RST#<6,8,17,22,24,27,36>
PCI_RSTNS# <27>
6
B B
SET_PCIRSTNS#<27>
A A
BAT2_LLOW#<48,51>
5
1 2
R435 10KOhm
12
R434
47KOhm
C375
1 2
0.1UF
U42C
147
VCC
8
GND
LV08A
+3V
U42D
147
VCC
11
12
13
GND
LV08A
C376
0.01UF
/*
PCI_RST#_ICH
9
10
PLT_RST#_SB
12
3
CLK_PCIE_ICH#<21>
CLK_PCIE_ICH<21>
+3V
AD25
DMI_CLKN
AC25
DMI_CLKP
ICH6_M
02-010004402
Can be issue SCI or SMI List: GPIO0~GPIO15
Resume Power Well GPIO List: GPIO8,11,13,14,15,24,25,27,28
Only GPI Pin: GPI0~8,11~15,26,29,30,31,40(5V),41
Only GPO Pin: GPIO16~17,19,21,23,48
Can be GPIO: GPIO24,25,27,28,33,34
Resume Power Input Pin List:
BATLOW#,AC_SDIN[0:1],LAN_RST#,
OC[7:0]#,PME#,PWRBTN#,RI#,SMBALERT#,SYS_RESET#,USBRBIAS#
ASUSTECH CO.,LTD.
Size Project Name
C
2
Date: Sheet
Z61Ae
Title :
Engineer:
1
ICH6M--PCI/DMIUSB/PCIE (2)
Sam Wang
of
18 57Thursday, June 09, 2005
Rev
2.0
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