Asus ME370T Schematic

ME370T (Nakasi)

1.0

2012/02/08

HEADSET

HEADSET JACK

Speaker

DMIC KNOWLES SPM0423HD4H-WB

Touch screen

ELAN

LCD Panel

EXT MIC

Internal D MIC

Battery Gauge

Charger

SMB347

Micro HDMI

LVDS

LVDSLVDS

GEN1_SMB_3V3

GEN1_SMB_3V3GEN1_SMB_3V3

GEN2_I2C_3V3

GEN2_I2C_3V3GEN2_I2C_3V3

I/O Board & TP

EXTERNAL SD SCOKET

USB Conn.

Docking USB Port

USB*3 , Line out , Mic In , DC Jack

Docking

Transmitter

TI SN75LVDS83B

Audio DSP

FM34

I2S CODEC

ALC5642

PWR_I2C_1V8

PWR_I2C_1V8PWR_I2C_1V8

HDMI

HDMIHDMI

DDC_I2C 5V0

DDC_I2C 5V0DDC_I2C 5V0

LCD_RGB_1V8

LCD_RGB_1V8 LCD_RGB_1V8

Gen1_I2C_1V8

Gen1_I2C_1V8Gen1_I2C_1V8

I2S_1V8

I2S_1V8I2S_1V8

PWR_I2C_1V8

PWR_I2C_1V8PWR_I2C_1V8

USB_1_3V3

USB_1_3V3USB_1_3V3

USB_3_3V3

USB_3_3V3USB_3_3V3

Gen1_I2C_1V8

Gen1_I2C_1V8Gen1_I2C_1V8

MIPI_CSIB_1V2

MIPI_CSIB_1V2MIPI_CSIB_1V2

Tegra

T30L

Kai

Front Camera module

Aptina 1040

PWR_I2C_1V8

PWR_I2C_1V8PWR_I2C_1V8

DDR3L x 32_1V35

DDR3L x 32_1V35DDR3L x 32_1V35

HSMMC x8_1V8

HSMMC x8_1V8HSMMC x8_1V8

JTAG_1V8

JTAG_1V8JTAG_1V8

UART_4_1V8

UART_4_1V8UART_4_1V8

GEN2_I2C_1V8

GEN2_I2C_1V8GEN2_I2C_1V8

SDIO_1_1V8

SDIO_1_1V8SDIO_1_1V8 UART_3_1V8

UART_3_1V8

UART_3_1V8UART_3_1V8

32.768KHz

32.768KHz32.768KHz

32.768KHz

32.768KHz32.768KHz

UART_2_1V8

UART_2_1V8UART_2_1V8

MIPI_CSIA_1V2

MIPI_CSIA_1V2MIPI_CSIA_1V2

CAM_I2C_1V8

CAM_I2C_1V8CAM_I2C_1V8

CAM_I2C_1V8

CAM_I2C_1V8CAM_I2C_1V8

CAM_I2C_1V8

CAM_I2C_1V8CAM_I2C_1V8

CAM_I2C_1V8

CAM_I2C_1V8CAM_I2C_1V8

Controls

ControlsControls

32.768KHz

32.768KHz32.768KHz

XTAL 12MHZ

Rear Camera module

OV5650

Light sensor

LSC3010

E-COMPASS

AICHI AMI304

Gyro sensor

Invensense MPU-6050

PMIC

MAXIM MAX77663

Thermal Sensor

OnSemi NCT72

DDR3L 256M x8 x4pcs 1333(667MHz)

eMMC 8GB

Debug Port

EC

NUVOTON NPCE795LA0DX

WIFI + BT

Azurewave AW/NH-665

XTAL 37.4MHz

TCXO 26MHz

GPS

Broadcom BCM4751

Antenna

NFC NXP PN65

XTAL 27.12MHz

XTAL

32.768KHz

Button FPC

Power Button Volume Up & Down Reset Button

Antenna

5

ME370T (Nakasi)

Power Tree

D D

Power Source

USB Conn.

Dock Conn.

C C

VDD_AC_BAT

(VPH_PWR_CHGR)

B B

A A

VDD_USB1_VBUS

DOCK_5V

page 49

Charger

SMB347

page 48

Buck-Boost

TPS63020

page 48

Boost

RT9276GQW

page 50~52

PMIC

MAX77663

MBATT, MON,

Internal Usage

GPIO_INA & AVSD

SD0

SD1

SD2

SD3

IN_LDO4/6

U27

page 31

LDO S-1132

2.8V. 300mA

CAM1_LDO_EN(T30 KB_ROW6)

U28

page 31

LDO S-1132

2.8V. 300mA

CAM2_LDO_EN(T30 KB_ROW8)

5

VBATT

EN_3V3_SYS(PMU GPIO3)

VDD_5V0_SYS

5V. 1A

EN_5V0_SBY(T30 GMI_AD11)

VDD_1V0_GEN

VDD_1V2_SOC

LDO4

LDO6

VDD_PMU_LDO4_1V2

1.2V. 150mA, PMIC

VDD_PMU_LDO6_3V_1V8 T30

3/1.8V. 150mA, PMIC

page 27

page 44

AVDD_CAM1 Camera AVDD

AVDD_VCM CAMERA AF VCM

VDD_SPK Codec Speaker Amp.

NFC_VBAT NFC VBAT

Battery

page 21

+3VSUS

3.3V. 2A

page 29

LDO S-1167

3.3V. 150mA

VDD_5V0_SYS enable

VCC_LED

T30 CPU

1.05V, 6.1A, Terga (Tj=90, 1.3GHz)1.05V. 6A, PMIC

T30 CORE

U30

for Touch Sensor

VDD_CPU

VDD_CORE

1.2V, 2.5A, Terga1.2V. 3A, PMIC

T30

VDD_RTC

VDDIO_SDMMC1

4

TP_3V3

page 29

4

+1.35V

1.35V. 1.5A, PMIC

page 52

PMIC

MAX77663

IN_LDO2

IN_LDO3/5

page 52

PMIC

MAX77663

IN_LDO0/1

IN_LDO7/8

DRAM Chip 256Mb x8bits x4pcs

page 19

170mA x4, each DRAM chip

3

LDO2

LDO3

LDO5

+3VSUS_CPU

VDD_PNL

page 22

page 25

page 26

page 41

LDO0

LDO1

LDO7

LDO8

3

VDD_PMU_LDO2_2V8 T30

2.8V. 150mA, PMIC

VDD_PMU_LDO3_2V8

2.8V. 300mA, PMIC

VDD_PMU_LDO5

2.8V. 300mA, PMIC

page 5

Power SW NCT352

page 14

Power SW NCT352

page 21

Power SW NCT352

VDD_LVDS_30

VDD_ALS

VDD_GYRO

AVDD_ECOM

WiFi_BT_VCC_3V3

GPS_VDD_BAT_3V3

VDD_PMU_LDO0_1V0 T30

1.0V. 150mA, PMIC

VDD_PMU_LDO1

VDD_PMU_LDO7_1V2

1.2V. 450mA, PMIC

VDD_PMU_LDO8_1V2

1.2V. 300mA, PMIC

VDD_DDR_RX

page 20

VCORE_EMMC_S

page 31

U1

T30

EN_VDD_FUSE (T30 LCD_PWR1)

T30

U14

T30

EN_AVDD_USB (MAX77663 GPIO2)

page 26

for eMMC VCC200mA

VDDIO_CAM

Camera VDDIO

VDD_FUSE

VDD_3V3_GMI

AVDD_USB

VCORE_TEMP

for Thermal Sensor

T30

VDDIO_PEX_CTL

TBD (no use)

U8

VCC_LCD3V3

for LCD Panel

EN_VDD_PNL (T30 LCD_M1)

for LVDS Transmitter

VCC

VDD_LVDS_30

LVDSVCC

VDD_LVDS_F_30

PLLVCC

VDD_LVDS_PLL_30

for Hall Sensor, ALS

for Gyro VDD

for E-compass AVDD

for Wifi/BT Module

for GPS

VDD_DDR_HS

No usage150mA, PMIC

T30

AVDD_DSI_CSI

T30

AVDD_PLLA_P_C

AVDD_PLLM

AVDD_PLLU_D

AVDD_PLLX

T30

VDDIO_DDR

Max. 710mA

VDD_DDR3L for DDR3L VDD

VDDQ_DDR3L for DDR3L VDDQ

2

VDD_1V8_GEN

1.8V. 2.0A, PMIC

2

page 20

page 22

page 26

page 27

VDD_1V8_GEN_CPU

Q2

page 14

Load SW PMOS

CORE_PWR_REQ

VDD_1V8_CDC

page 27

page 41

page 43

page 44

page 50

PMIC

MAX77663

Internal Usage

GPIO_INB

1

T30

AVDD_OSC

T30

VDDIO_SYS

T30

VDDIO_CAM

T30

VDDIO_LCD

T30

VDDIO_BB

T30

VDDIO_UART

T30

VDD_IO_AUDIO

T30

VDDIO_SDMMC4

T30

VDDIO_SDMMC3

T30

AVDD_USB_PLL

for eMMC VCCQ

VDDIO_HSMMC

for LVDS Transmitter

IOVCC

IOVCC_30

VDDIO_GYRO for Gyro VLOGIC

DVDD_ECOM for E-compass DVDD

for Audio Codec

DBVDD

VDB_CDC

CPVDD

VCP_CDC

AVDD

AVDD_CDC_F

DCVDD

DACREF_CDC

VDD_1V8_DMIC

for DMIC VDD

WiFi_BT_VDDIO_1V8

for Wifi/BT Module

GPS_VDD_IO_1V8 for GPS

NFC_PVDD for NFC

Title :

02.POWER TREE

Engineer:

Richard Lin

Engineer:

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

Custom

Date: Sheet of

ME370T

1

Richard Lin

Rev

2.0

2 60Thursday, March 01, 2012

TF300T_T3 Power On/Off

5

4

3

2

1

D D

AC_BAT_SYS

AC_OK

+3VA_PAL(PU8805)

3.3V

PWR_SW#

3.3V

+3VA_EC (PU8806)

AC_BAT_SYS

P_+5VSO_EN_10 (Q7900)EC to PU8100

5V

+5VSUS (PU8100)

1.8V

VDD_1V8_PMU_VRTC(PMU VRTC)

A/D_IN

C C

PMU_ONKEY#SW# to PMU

EN_5V0_SBY(PMU GPIO0)

VDD_5V0_SBY(PQ9106, 2A)

VDD_RTC(PMU LDO4)

PMU to T3 VDD_1V8_GEN(PMU SWIO)

VDD_CORE(PMU SW1)PMU to T3

PMU to T3

VDD_PMU_LDO7(T3 AVDD_PLLx)

3.3V

1.8V

5V

1.8V

1.2V

1.1V

CLK_32K_IN(PMU)PMU to T3

T3 XTAL

B B

System Clock(T3 26MHz)

EN_VDD_1V35(EN_DDR, PMU GPIO7)

+1.8V

5.0V

1.8V

1.35V

+1.2V(for DDR3L 1.35V)

5.0V

PMU to PU8100

T3 to Q1603

EN_3V3_SYS(PMU GPIO6)

EN_3V3_EMMC(T3)

1.8V

2.85V

VCORE_eMMC_S(Q1603)

PMU to T3

A A

T3 to PMU

PMU to T3

VDD_DDR_HS(PMU LDO8)

1.0V

VDD_SATA(PMU LDO2)

VDD_PEX(PMU LDO1) (EEPROM OFF)

SYS_RESET#(PMU)

CPU_PWR_REQ(TERGA)

VDD_CPU(PMU SW)

1.05V

1.8V

1.0V

+1.05VS/+1.2VS/+1.5VS

OTHERS

5

(PMU LDOs, Switched Rails)

4

Title :

Timing

Engineer:

Richard Lin

Engineer:

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Pr oject Name

Custom

Date: Sheet of

3

2

Date: Sheet of

ME370T

1

Richard Lin

3 60Thursday, March 01, 2012

Rev

2.0

5

4

3

2

1

TF300T T3 power on/off map

1201

D D

C C

B B

A A

Adapter

A/D IN

Buck Boost

AC_BAT_SYS

Charger BQ24740

BAT

EN_VDD_BL

<7>VDD_1V8_GEN

Sequence: <1>--><2>--><2A>--><2B>--><2C>--><2D>--> <3>--><4>--><5>--><6>--><6A>--><7>--><8>--> <9>--><10>--><10A>--><10B>--><11>--><12>--><13>

Button

BAT

Battery Pack

<1>PWR_SW#

LDO <2B>+3VA_EC

LDO +3V_PAL

<10A> EN_3V3_SYS

P-MOS SI2305DS

EN

P-MOS SI2305DS

EN<OFF>EN_1V8_CAM

Power Latch

<2A>P_+3VA_EN

TI TPS51125ARGER

EN1 EN2

<2C> P_+5VSO_EN_10

VCC_LED

VDDIO_CAM

<2A>P_+3VA_EN

SW1 <10B>+3VSUS(+3VSO1)

<3>+5VSUS(+5VSO1)

SW2

LDO <4>+3VA

LCD panel backlight

<6>EN_VDD_SOC

<10>+3VSUS(+3VSO1)

<OFF>VDD_5V0_SYS

<7>VDD_1V8_GEN

VDD_CELL_LCL

<5>VDD_1V8_PMU_VRTC

AP_OVERHEAT#

HOT_RST

<2D>PMU_ONKEY#

<10B>+3VSUS

EN_VDD_FUSE

<10B>VDD_PNL(+3VSUS)

EN_VDD_PNL

<10B>+3VSUS

EN_3V3_COM

<5>EN_5V0_SBY

<OFF>EN_5V0_SYS

<OFF>DOCK_IN

<10B>+3VSUS

<5A>VDD_5V0_SBY

***

@

P-MOS SI2305DS

EN

P-MOS SI2305DS

EN

P-MOS SI2305DS

EN

N-MOS IRFHS8342TRPBF

EN

N-MOS IRFHS8342TRPBF

EN

P-MOS SI2305DS

EN

P-MOS SI2305DS

EN

P-MOS SI2305DS

EN

V5IN

VCC1

VCC2

VCCIO

VCC7

VCC6

VCC5

VCC4

VCC3

VDDIO

VBACKUP

GPIO4 GPIO5 PWRDN(power down) HOT_RST PWRON

time slot duration: 2ms

VDD_FUSE

VCC_LCD3V3

WiFi_BT_VCC_3V3

<5A>VDD_5V0_SBY

VDD_5V0_SYS

HDMI_VBUS_EN_AIO

<OFF>+5VSUS_DOCK

<11>VCC_TCH

<6A>VDD_1V2_SOC T30

EN2 EN1

SLEEP

NRESPWRON

PWR_INT#

CLK32KOUT

SW

SW1

SW2

SWIO

VRTC

LDO1 LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

GPIO0 GPIO2 GPIO6 GPIO7

EEPROM

T30

<10B>+3VSUS

CAM1_LDO_EN EN

LCD panel

WIFI+BT

<10B>+3VSUS

CAM2_LDO_EN EN

**

***

P-MOS SI2305DS

EN

<13>CPU_PWR_REQ

CORE_PWR_REQ

<12>SYS_RESET#

PWR_INT#

<9>CLK_32K_IN

<0FF>VDD_CPU

<0FF>VDD_1V2_GEN

<9>+1.2V

<7>VDD_1V8_GEN

<5>VDD_1V8_PMU_VRTC

<11>VCORE_eMMC_S(core power)

<OFF>VDD_SD_S

<OFF> VDDIO_SDMMC1

<4>VDD_RTC

<OFF>VDD_PMU_LDO5

<OFF>VDD_PMU_LDO6

<9>VDD_PMU_LDO7(T3 AVDD_PLLx)

<11>VDD_DDR_HS

<5>EN_5V0_SBY <6>EN_VDD_SOC <10>EN_3V3_SYS <9>EN_DDR

<10B>+3VSUS

<9>+1.2V

HVDD_PEX VDD_FUSE

LDO 2.85V RT9193-2HGU5

VDDIO_HDMI_CONN_AIO

CPU_PWR_REQ CORE_PWR_REQ SYS_RESET_N PWR_INT_N CLK_32K_IN

VDD_CPU

VDD_CORE

VDD_1V8_GEN

@

VDD_SATA

VDD_RTC

VDDIO_SDMMC1(3.3V)

AVDD_DSI_CSI(1.2V)

AVDD_PLLx

VDD_DDR_HS

AVDD_USB VDD_DDR_RX AVDD_HDMI VDDIO_GMI VDD_PEX_CTL VDDIO_LCD

VDDIO_DDR HVDD_PEX(3.3V) VPP_FUSE(3.3V)

AVDD_CAM1

AVDD_VCM

* ***

5

4

3

2

5

VDD_PMU_LDO4_1V2

1.2V

0.9~1.0V

D D

VDD_1V0_GEN

1.0~1.2V

0622

+3VSUS_CPU VDD_FUSE

12

C C

C24

0.1U6.3VX5RC1K

N/A

EN_VDD_FUSE10

VDD_FUSE_DISABLE

VDD_1V2_SOC

0720

MAX77663 LDO4

MAX77663 SD0(6A)

MAX77663 SD1(3A)

Unmount

R1

R1 0R2J /@

0R2J /@

1 2

U1

OUT

IN

GND

NCT3521U N/A

R2

R2 300R1F N/A

300R1F N/A

1 2

12

R3

100KR1J

/@

12

R4

R4 100KR1J

100KR1J

N/A

EN3DIS

Unmount

1 2

5

4

VDDIO_UART

VDD_RTC

VDD_CPU

VDD_CORE

0720 default di sable FUSE fun ction

B B

A A

5

4

BOM

需需需需需需需需需需需需需需需需

02004-00120000 C.S T30-R-A3 FCBGA-728

0620

U2A

1/22 CORE POWER

A2

GND_001

A29

GND_002

AC11

GND_003

AC14

GND_004

AC17

GND_005

AC2

GND_006

AC20

GND_007

AC23

GND_008

AC26

GND_009

AC29

GND_010

AC5

GND_011

AC8

GND_012

AF11

GND_013

AF14

GND_014

AF17

GND_015

AF2

GND_016

AF20

GND_017

AF23

GND_018

AF26

GND_019

AF29

GND_020

AF5

GND_021

AF8

GND_022

AJ1

GND_023

AJ11

GND_024

AJ14

GND_025

AJ17

GND_026

AJ2

GND_027

AJ20

GND_028

AJ23

GND_029

AJ26

GND_030

AJ29

GND_031

AJ30

GND_032

AJ5

GND_033

AJ8

GND_034

AK2

GND_035

AK29

GND_036

B1

GND_037

B11

GND_038

B14

GND_039

B17

GND_040

B2

GND_041

B20

GND_042

B23

GND_043

B26

GND_044

B29

GND_045

B30

GND_046

B5

GND_047

B8

GND_048

E11

GND_049

E14

GND_050

E17

GND_051

E2

GND_052

E20

GND_053

E23

GND_054

E26

GND_055

E29

GND_056

E5

GND_057

E8

GND_058

H11

GND_059

H14

GND_060

H17

GND_061

H2

GND_062

H20

GND_063

H23

GND_064

H26

GND_065

H29

GND_066

H5

GND_067

H8

GND_068

L2

GND_069

L23

GND_070

L26

GND_071

L29

GND_072

L5

GND_073

L8

GND_074

M12

GND_075

M14

GND_076

M16

GND_077

M18

GND_078

N13

GND_079

N15

GND_080

N17

GND_081

N19

GND_082

P12

GND_083

P18

GND_084

P2

GND_085

P23

GND_086

P26

GND_087

P29

GND_088

P5

GND_089

P8

GND_090

R13

GND_091

R15

GND_092

R16

GND_093

R19

GND_094

T12

GND_095

T15

GND_096

T16

GND_097

T18

GND_098

U13

GND_099

U19

GND_100

U2

GND_101

U23

GND_102

U26

GND_103

U29

GND_104

U5

GND_105

U8

GND_106

V12

GND_107

V14

GND_108

V16

GND_109

V18

GND_110

W12

GND_111

W13

GND_112

W15

GND_113

W17

GND_114

W19

GND_115

Y2

GND_116

Y23

GND_117

Y26

GND_118

Y29

GND_119

Y5

GND_120

Y8

GND_121

T30L-R-P-A3

T30

4

(1.0 ~ 1.2V)

VDD_RTC_0001 VDD_RTC_0002

0.9~1.0V

(0.9 ~ 1.0V)

1.0~1.2V

(1.0 ~ 1.2V)

VDD_CPU_SENSE

GND_CPU_SENSE

VVDD_CPU_SENSE

VGND_CORE_SENSE

VDD_CORE_SENSE

GND_CORE_SENSE

(3.3V)

VDD_CPU_01 VDD_CPU_02 VDD_CPU_03 VDD_CPU_04 VDD_CPU_05 VDD_CPU_06 VDD_CPU_07 VDD_CPU_08 VDD_CPU_09 VDD_CPU_10 VDD_CPU_11 VDD_CPU_12 VDD_CPU_13 VDD_CPU_14 VDD_CPU_15 VDD_CPU_16 VDD_CPU_17 VDD_CPU_18 VDD_CPU_19 VDD_CPU_20 VDD_CPU_21 VDD_CPU_22

VDD_CORE_01 VDD_CORE_02 VDD_CORE_03 VDD_CORE_04 VDD_CORE_05 VDD_CORE_06 VDD_CORE_07 VDD_CORE_08 VDD_CORE_09 VDD_CORE_10 VDD_CORE_11 VDD_CORE_12 VDD_CORE_13 VDD_CORE_14 VDD_CORE_15 VDD_CORE_16 VDD_CORE_17 VDD_CORE_18 VDD_CORE_19 VDD_CORE_20 VDD_CORE_21 VDD_CORE_22 VDD_CORE_23 VDD_CORE_24 VDD_CORE_25 VDD_CORE_26 VDD_CORE_27 VDD_CORE_28

VPP_KFUSE

1.2V

VPP_FUSE

V22 V23

H10 J10 J8 K8 K9 M7 M8 M9 N8 N9 P14 P15 P16 P17 R14 R17 T14 T17 U14 U15 U16 U17

M13 M15 M17 M19 N12 N14 N16 N18 N7 P13 P19 R12 R18 R7 R8 R9 T13 T19 T8 T9 U18 V13 V15 V17 V19 W14 W16 W18

AB12

AB15

AB16

AA23

W23

W22

AB8

AA4

3

VDD_CPU_SENSE_T30

GND_CPU_SENSE_T30

VDD_CORE_SENSE_T30

GND_CORE_SENSE_T30

VPP_KFUSE

R5

10KR1J

N/A

VDD_RTC

VDD_CPU

VDD_CORE

12

VDD_CORE

12

1220 add

R6

R6 1KR1J

1KR1J

/@

Unmount

1 2

2

C1

1 2

0.1U6.3VX5RC1K

C2

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C4

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C6

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C8

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C7

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C3

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C10

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C13

4.7U6.3VX5RC2M

C15

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C12

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C20

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C22

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C18

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C26

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C27

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C28

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C25 33P25VNPOC1J

33P25VNPOC1J

C14

N/AC14

N/A

22U6.3VX5RC5M

C17

N/AC17

N/A

22U6.3VX5RC5M

VDD_RTC

VDD_CPU

VDD_CORE VDD_CORE

0614 remove VDD_CPU_SENSE

Note: Place the 0402 shunts close to Tegra side

VDD_CPU_SENSE_T30 VDD_CPU_SENSE

GND_CPU_SENSE_T30

Short Copper

GND_CORE_SENSE_T30

VDD_FUSE

12

C30

0.1U6.3VX5RC1K

N/A

2

1

N/AC1

N/A

N/AC2

N/A

VDD_CPU

N/AC4

N/A

N/AC6

N/A

N/AC8

N/A

N/AC7

N/A

N/AC3

N/A

N/AC10

N/A

N/AC13

N/A

0906 NV add

1 2

C5

N/AC5

N/A

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C29

/@C29

/@

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C9

N/AC9

N/A

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C11 8P25VNPOC1J

8P25VNPOC1J

0906 NV add

N/AC15

N/A

N/AC12

N/A

N/AC20

N/A

N/AC22

N/A

N/AC18

N/A

N/AC26

N/A

N/AC27

N/A

N/AC28

N/A

N/AC25

N/A

PJP1

PJP1 SHORT_PIN

SHORT_PIN

/@

12

P05

P05 P05

P05

PJP2

PJP2 SHORT_PIN

SHORT_PIN

PJP3

PJP3 SHORT_PIN

SHORT_PIN

P05

P05 P05

P05

PJP4

PJP4 SHORT_PIN

SHORT_PIN

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

/@

12

/@

12

/@

12

GND_CPU_SENSE

VDD_CORE_SENSEVDD_CORE_SENSE_T30

GND_CORE_SENSE

ME370T

C16

1 2

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C19

1 2

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C21

1 2

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C23

1 2

0.1U6.3VX5RC1K

MAX77663 SD0 sense

VDD_CORE_SENSE 51

MAX77663 SD1 sense

GND_CORE_SENSE 51

Title :

T30 Core & Fuse

Engineer:

1

N/AC11

N/A

N/AC16

N/A

N/AC19

N/A

/@C21

/@

/@C23

/@

VDD_CPU_SENSE 51

GND_CPU_SENSE 51

Richard Lin

5 60Saturday, March 24, 2012

Rev

2.0

5

1.2V

VDD_PMU_LDO8_1V2

MAX77663 LDO8

VDD_PMU_LDO8_1V2_CPU

1.2V

R8

N/A

1.8V

D D

PMU

R1.0 R1.2

12

C31

4.7U6.3VX5RC2M

N/A

12

C37

0.1U6.3VX5RC1K

N/A

DOWN

AVDD_PLLA_P_C

POR Deep Sleep

PUPD

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

50K

AVDD_OSC

AVDD_PLLU_D VDDIO_SYS

C C

VDDIO_SYS

COL0

COL1

COL2

COL3

COL4

COL5

COL6

B B

COL7

ROW0

ROW1

ROW2

ROW3

ROW4

ROW5

ROW6

ROW7

ROW8

ROW9

ROW10

ROW11

ROW12

ROW13

ROW14

ROW15

A A

1 2

0R3J

MAX77663 SD2 (2A)

VDD_1V8_PMU_DCDC2

VDD_PMU_LDO7

1.1V

1.2V

12

C34

0.1U6.3VX5RC1K

N/A

12

C38

0.1U6.3VX5RC1K

N/A

PinState

PU

PD

Config. Reset

VDD_1V8_GEN_CPUVDD_1V8_GEN

Remove C35, C36 for AVDD_PLLX & AVDD_PLLM

PUPD After Wake

PJ1

/@PJ1

/@

12

SHORT_PIN

Short Copper

1.8V

VDD_1V8_GEN_CPU

AVDD_PLLA_P_C

AVDD_PLLU_D

4

VDD_PMU_LDO8_1V2_CPU

Remove AVDD_PLLX

Remove AVDD_PLLM

AVDD_OSC

AVDD_PLLE_no_use

VDDIO_SYS

L7

21

30Ohm/100Mhz

0906 NV change

U2B

2/22 OSC, PLL & SYS

1.8V

(1.8V)

F30

AVDD_OSC

(1.1V)

H13

AVDD_PLLA_P_C

(1.1V)

J12

AVDD_PLLX

(1.1V)

J13

AVDD_PLLM

(1.1V)

AA8

AVDD_PLLU_D

(1.1V)

AD7

AVDD_PLLU_D2

(1.05V)

AA22

AVDD_PLLE

(1.8/3.3V)

K29

VDDIO_SYS_1

K30

VDDIO_SYS_2

<Value>

T30L-R-P-A3

N/A

1.2V

1.05V

1.8V

AVDD_PLLA_P_C

AVDD_PLLU_D

VDDIO_SYSVDD_1V8_GEN_CPU

AVDD_OSC

AUDIO&PERIPHERAL

CPU

DRAM

USB&DSI

PCIE&SATA

XTAL_IN

XTAL_OUT

NC37

PWR_I2C_SCL PWR_I2C_SDA

SYS_RESET_N

PWR_INT_N

CORE_PWR_REQ

CPU_PWR_REQ

SYS_CLK_REQ

CLK_32K_IN

CLK_32K_OUT

KB_COL00 KB_COL01 KB_COL02 KB_COL03 KB_COL04 KB_COL05 KB_COL06 KB_COL07

KB_ROW00 KB_ROW01 KB_ROW02 KB_ROW03 KB_ROW04 KB_ROW05 KB_ROW06 KB_ROW07 KB_ROW08 KB_ROW09 KB_ROW10 KB_ROW11 KB_ROW12 KB_ROW13 KB_ROW14 KB_ROW15

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

JTAG_RTCK

THERM_DN THERM_DP

OWR

HDMI_CEC

TEST_MODE_EN

3

XTAL_IN

T30

XTAL_OUT

T29

XTAL_OUT_R

H12

remove PLL_S_PLL_LF

M24 N27

N28

M22

N25 R24

T23

R22 U27

J30 N26 V25 R26 W26 R30 P27 N29

T26 M23 V27 M28 N24 N30 T24 T25 R27 M26 R25 M27 N23 V28 M25 V26

T27 R29 T28 R23 T22 V24

M30 M29

N22

AC18

R28

0721

NC

12P50VNPOC2J

N/A

Change

PWR_I2C_SCL PWR_I2C_SDA

SYS_RESET#

PWR_INT#

CORE_PWR_REQ CPU_PWR_REQ

CLK_32K_IN CLK_32K_OUT

PCB_ID2 PCB_ID5

PCB_ID3

PCB_ID4

PCB_ID0 PCB_ID1 CAM1_LDO_EN

CAM2_LDO_EN

LL_BAT_T30

1V8_O_LID#

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRT_N JTAG_RTCK

THERMD_N THERMD_P

TEST_MODE_EN

C32

12

R10

R10 0R1J

0R1J

N/A

12

Unmount

1 2

0R1J /@

R26 0R1J

0R1J

1 2

R9

N/AR9

N/A

2MR2J

1 2

Change

X1

N/AX1

N/A

12MHz

1 3

2

4

TXC/7V12000011

VDDIO_SYS VDDIO_SYS

12

R11

R12

1KR1J

N/A

R16

1 2

1KR1J N/A

KB_COL0 KB_COL1 KB_COL2 KB_COL3 SNN_KB_COL4 SNN_KB_COL5

0802 ID5

SNN_KB_COL6 SNN_KB_COL7

KB_ROW0 KB_ROW1 KB_ROW2 SNN_KB_ROW3 SNN_CAM_I2C_SEL0 SNN_CAM_I2C_SEL1 CAM1_LDO_EN CAM2_LDO_EN CAM3_LDO_EN SNN_CAM1_AF_PWDN* SNN_CAM2_AF_PWDN* CAM3_AF_PWDN* SNN_KB_ROW12 SNN_KB_ROW13 SNN_KB_ROW14 SNN_KB_ROW15

R21

Unmount

N/AR26

N/A

Power from MAX77663

MAX77663 LDO8 1.2V to T30 AVDD_PLLx

MAX77663 SD2 1.8V (VDD_1V8_PMU_DCDC2) to VDD_1V8_GEN

Signal to & from MAX77663

SYS_RESET# from MAX77663 nRSTIO, check reset circuit(p.32) and PMU side

PWR_INT# from MAX77663 nIRQ, check PU resister in PMU side(100k PU to VDD_1V8_GEN)

CORE_PWR_REQ to MAX77663 EN1, check PU resister in PMU side(100k PU to VDD_1V8_GEN)

CPU_PWR_REQ to MAX77663 EN2, check PD resister in PMU side(100k PD)

CLK_32K_IN from MAX77663 GPIO4, check PU resister in PMU side(100k PU to VDD_1V8_GEN)

X1 change to 12MHz XTAL

Change

12

C33

C33 12P50VNPOC2J

12P50VNPOC2J

N/A

C32 & C33 change to 12pF

12

1227 R0732 100K -> 10K

PWR_I2C_SCL 26,27,49,50 PWR_I2C_SDA 26,27,49,50

SYS_RESET# 20,32,50

JTAG_TRST#

PWR_INT# 50

CLK_32K_IN 50

CLK_32K_OUT 40,41,43

PWR_SW#_BUTTON_R 33

VOL_UP_BUTTON 32 VOL_DWN_BUTTON 32

KB_ROW0 32,33

NFC_GPIO4_R 44

CAM1_LDO_EN 31

CAM2_LDO_EN 31

SMB347_USB51HC 33 SMB347_SUSP 33

LL_BAT_T30 33

1V8_O_LID# 25

NFC_VEN 44

JTAG_TCK 24

JTAG_TDO 24

JTAG_RTCK 24

THERMD_N 26

THERMD_P 26

ROW10, 11 for charger control

TEMP_ALERT#_KAI form Thermal Sensor

JTAG_TDI 24

JTAG_TMS 24 JTAG_TRST# 24

2

VDDIO_SYS

12

0229 NV change 10k -> 100k

TEMP_ALERT#_KAI 26

R14

R14 100KR1J

100KR1J

N/A

12

R15

100KR1J

N/A

CPU_PWR_REQ PD 100k in KAI design

JTAG_TRT_N

12

R24

100KR1J

N/A

CORE_PWR_REQ 14,50 CPU_PWR_REQ 50

Pin to Pin

Unmount

1

PCBID ID5 ID4 ID3 0 0 0 for ME370 T SR3

PCBID ID2 = 0 for BCM47511 ID2 = 1 for BCM4751

PCBID ID1 ID0 0 0 AW-NH660 BCM4330

1 0 AW-NH665 BCM4330

PCB_ID0

PCB_ID1

PCB_ID2

PCB_ID3

PCB_ID4

PCB_ID5

1 2 1 2

Unmount

1 2 1 2

Unmount

1 2 1 2

R18100KR1J /@ /PCBID/WIFIR18100KR1J /@/PCBID/WIFI R17100KR1J /PC BID/WIFIR17100KR1J /PC BID/WIFI

R19100KR1J /PC BID/WIFIR19100KR1J /PC BID/WIFI R20100KR1J /@ /PCBID/WIFIR20100KR1J /@/PCBID/WIFI

R22100KR1J /PC BID/GPSR22100KR1J /PC BID/GPS R27100KR1J /@ /PCBID/GPSR27100KR1J /@/PCBID/GPS

R23100KR1J /@ /PCBID/PROJECTR23100KR1J /@ /PCBID/PROJECT R25100KR1J /PC BID/PROJECTR25100KR1J /PCBID/ PROJECT

R31100KR1J /@ /PCBID/PROJECTR31100KR1J /@ /PCBID/PROJECT R28100KR1J /PC BID/PROJECTR28100KR1J /PCBID/ PROJECT

R30100KR1J /@ /PCBID/PROJECTR30100KR1J /@ /PCBID/PROJECT R29100KR1J /PC BID/PROJECTR29100KR1J /PCBID/ PROJECT

VDD_1V8_GEN_CPU

Title :

01.Block Diagram

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

6 60Thursday, March 22, 2012

Rev

2.0

3.3V

5

R35

1 2

0R3J

TPS63020 buck-boost

4

N/A

+3VSUS_CPU+3VSUS

3.3V

VDD_3V3_GMI+3VSUS_CPU

3

2

1

D D

C C

B B

VDDIO_GMI

AD00

AD01

AD02

AD03

AD04

AD05

AD06

AD07

AD08

AD09

AD10

AD11

AD12

AD13

AD14

AD15

A16

A17

A18

A19

CS0

CS1

CS2

CS3

CS4

CS6

CS7

ADV_N

CLK

RST_N

WAIT

WP_N

IORDY

OE_N

WR_N

DQS

VDD_3V3_GMI

PUPD1PinState

None

NoneZZ

None

NoneZZ

None

NoneZZ

None

NoneZZ

DOWN

100K

DOWN

100K

None Z

None

None Z

None

None Z

None

NoneZZ

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

None

None10

UP

100K

UP

100K

UP PU100K

None 1

None Z

POR

1 2

Z

PD

Z

PU

1

PU

0

PU

10U6.3VX5RC3M

0.1U6.3VX5RC1K

C39

N/AC39

N/A

C40

N/AC40

N/A

Deep Sleep

PUPD After Wake

Disable Reset

Config. Hold

Config.

Config. Hold

Config.

Disable Reset

Config.

Disable Reset

Config.

Disable Reset

Hold

Reset

ResetConfig.

VDD_3V3_GMI

C1 C2 D1

U2D

T30L-R-P-A3

N/A

4/22 GMI

(1.8/3.3V)

VDDIO_GMI_1 VDDIO_GMI_2 VDDIO_GMI_3

3.3V

GMI_AD00 GMI_AD01 GMI_AD02 GMI_AD03 GMI_AD04 GMI_AD05 GMI_AD06 GMI_AD07 GMI_AD08 GMI_AD09 GMI_AD10 GMI_AD11 GMI_AD12 GMI_AD13 GMI_AD14 GMI_AD15

GMI_A16 GMI_A17 GMI_A18 GMI_A19

GMI_CS0_N GMI_CS1_N GMI_CS2_N GMI_CS3_N GMI_CS4_N GMI_CS6_N GMI_CS7_N

GMI_ADV_N

GMI_CLK

GMI_RST_N

GMI_WAIT

GMI_WP_N

GMI_IORDY

GMI_OE_N

GMI_WR_N

GMI_DQS

GEN2_I2C_SCL GEN2_I2C_SDA

NAND_D0

F8

NAND_D1

G6

NAND_D2

D3

NAND_D3

E4

NAND_D4

G2

NAND_D5

D2

NAND_D6

B3

NAND_D7

G1

LCD_BL_PWM

H6

NC

F4 E7

TS_WAKEUP#

F3

TS_IRQ#

F5 F7

TS_RESET#_3V3

J2 F1

NC

H4

NC

J6

NC

C4

NC

J3

NC

J4

NC

K7

NC

F6

NC

A3 D6 J5

FTM_MODE#

J7

NAND_ALE

E6

NAND_CLE

A4

D4 B4 D5

C3

NAND_RE#

F2

NAND_WE#

G4

G3

GEN2_I2C_SCL

G5

GEN2_I2C_SDA

G7

LCD1_BL_PWM PWM_3D LCD1_BL_EN EN_VDD_BL1 TS_IRQ*

TS_RESET* CARD_PEX_RST#

SPI4_SCK SPI4_DOUT SPI4_DIN SPI4_CS1

PCB_ID6 PCB_ID7 PCB_ID8

LCD_LANDSCAPE SNN_TP_IRQ# SNN_GMI_CS6 WW_WAKE*

SNN_GMI_RST* RECOVERY_MODE* MFG_MODE_R

SNN_GMI_DQS

R44, R45 (GEN2_I2C PU) placed on P.29

R44, R45 (GEN2_I2C PU) placed on P.29R44, R45 (GEN2_I2C PU) placed on P.29

NAND_D0 18 NAND_D1 18 NAND_D2 18 NAND_D3 18 NAND_D4 18 NAND_D5 18 NAND_D6 18 NAND_D7 18

LCD_BL_PWM 23

TS_WAKEUP# 29,48

TS_IRQ# 29

TS_RESET#_3V3 29

TS_WAKEUP# for TS 5V enable (PD 1M on page.48)

TS_WAKEUP# for TS 5V enable (PD 1M on page.48)TS_WAKEUP# for TS 5V enable (PD 1M on page.48)

SNN_GMI_CS0 CHARGER_STAT

SNN_GMI_CS2

NAND_ALE 18

NAND_CLE 18,26

NAND_CLE for AP thermal shut down in KAI

NAND_CLE for AP thermal shut down in KAINAND_CLE for AP thermal shut down in KAI

NAND_RE# 18 NAND_WE# 18

VDD_3V3_GMI VDD_3V3_GMI

Boot Straps

GEN2_I2C_SCL 29 GEN2_I2C_SDA 29

TS I2C

LCD_BL_PWM

FTM_MODE#

PCBID ID7 ID6 0 0 ALC5631Q 0 1 WM8903 1 0 ALC5642 1 1 Reserved

PCBID ID8 Reserved

PCB_ID6

1 2 1 2

Unmount

PCB_ID7

1 2 1 2

Unmount

PCB_ID8

1 2 1 2

R43

N/AR43

N/A

330KR1J

1 2

VDD_3V3_GMI

12

R316

R316 1MR1J

1MR1J

N/A

R37100KR1J /@/PCBI D/CODECR37100KR1J /@/PCBI D/CODEC R36100KR1J /PCBID/ CODECR36100KR1J /PCBID/CODEC

R38100KR1J /PCBID/ CODECR38100KR1J /PCBID/CODEC R39100KR1J /@/PCBI D/CODECR39100KR1J /@/PCBI D/CODEC

R40100KR1J /@/PCBI DR40100KR1J /@/PCBI D R41100KR1J /PCBIDR41100KR1J /PCBID

T51

/@T51

/@

1

tpc40t_np_68

VDD_3V3_GMI

A A

Title :

T30 GMI IF

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

7 60Wednesday, March 21, 2012

Rev

2.0

5

from PMIC

D D

2.8V

+1.35V

VDD_PMU_LDO2_2V8

MAX77663 SD3(2A)

MAX77663 LDO2

VDDIO_DDR

VDD_DDR_RX

from PMIC

1.0V

VDD_PMU_LDO0_1V0

MAX77663 LDO0

VDD_DDR_HS

from PMIC

C41

N/AC41

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C43

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C44

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C42

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C45

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C46 10U6.3VX5RC3M

10U6.3VX5RC3M C47 10U6.3VX5RC3M

10U6.3VX5RC3M C48 10U6.3VX5RC3M

10U6.3VX5RC3M

C60

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C61

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C64

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C67

4.7U6.3VX5RC2M

C49

4.7U6.3VX5RC2M

C50

4.7U6.3VX5RC2M

N/A

N/AC43

N/A

N/AC44

N/A

N/AC42

N/A

N/AC45

N/A

N/AC46

N/A

N/AC47

N/A

N/AC48

N/A

N/AC60

N/A

N/AC61

N/A

N/AC64

N/A

N/AC67

N/A

N/AC49

N/A

N/AC50

N/A

VDDIO_DDR

C C

VDDIO_DDR

VDD_DDR_HS

VDD_DDR_RX

B B

1 2

4

U2C

3/22 DDR3/LPDDR2

(1.2/1.25/1.35/1.5)

VDDIO_DDR

0620

1.35V

VDD_DDR_RX

G16 G19 H15 H16 H18 H19 H21 H22 J15 J16 J18 J19 J21 J23 K22 K23

A27

VDDIO_DDR_01 VDDIO_DDR_02 VDDIO_DDR_03 VDDIO_DDR_04 VDDIO_DDR_05 VDDIO_DDR_06 VDDIO_DDR_07 VDDIO_DDR_08 VDDIO_DDR_09 VDDIO_DDR_10 VDDIO_DDR_11 VDDIO_DDR_12 VDDIO_DDR_13 VDDIO_DDR_14 VDDIO_DDR_15 VDDIO_DDR_16

(2.8/3.3V)

VDD_DDR_RX

3.3V

(1.00V)

VDD_DDR_HS

E10

H9

VDD_DDR_HS_1 VDD_DDR_HS_2

1.0V

0503

T30L-R-P-A3

N/A

3

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31

DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3

DDR_DQS0N DDR_DQS0P

DDR_DQS1N DDR_DQS1P

DDR_DQS2N DDR_DQS2P

DDR_DQS3N DDR_DQS3P

DDR_A00 DDR_A01 DDR_A02 DDR_A03 DDR_A04 DDR_A05 DDR_A06 DDR_A07 DDR_A08 DDR_A09 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14

DDR_RAS_N DDR_CAS_N

DDR_WE_N

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CS0_N DDR_CS1_N

DDR_ODT0 DDR_ODT1

DDR_CKE0 DDR_CKE1

DDR_CLK_N

DDR_CLK

DDR_RESET

DDR_QUSE0 DDR_QUSE1 DDR_QUSE2 DDR_QUSE3

DDR_COMP_PU

DDR_COMP_PD

2

R49

R49 0R1J

0R1J

1 2

0R1J

1 2

R52

Unmount

N/A

DDR_DQ[31..0] 19

DDR_DM[3..0] 19

DDR_DQS0N 19 DDR_DQS0P 19

DDR_DQS1N 19 DDR_DQS1P 19

DDR_DQS2N 19 DDR_DQS2P 19

DDR_DQS3N 19 DDR_DQS3P 19

DDR_A[14..0] 19

/@

/@R52

/@

VDDIO_DDR

DDR_RESET_N

Unmount

R4810KR1J /@R4810KR1J /@

1 2

0906 NV change to UM

R50

45.3R2F

N/A

12

DDR_DQ0

D24

DDR_DQ1

B25

DDR_DQ2

A25

DDR_DQ3

D21

DDR_DQ4

A24

DDR_DQ5

A21

DDR_DQ6

A22

DDR_DQ7

B22

DDR_DQ8

C15

DDR_DQ9

A13

DDR_DQ10

C12

DDR_DQ11

B13

DDR_DQ12

C13

DDR_DQ13

A10

DDR_DQ14

B10

DDR_DQ15

C10

DDR_DQ16

G22

DDR_DQ17

D22

DDR_DQ18

D25

DDR_DQ19

F23

DDR_DQ20

G21

DDR_DQ21

E25

DDR_DQ22

F24

DDR_DQ23

F22

DDR_DQ24

F13

DDR_DQ25

G13

DDR_DQ26

G10

DDR_DQ27

D13

DDR_DQ28

G9

DDR_DQ29

F10

DDR_DQ30

D10

DDR_DQ31

F12

DDR_DM0

C22

DDR_DM1

D12

DDR_DM2

E22

DDR_DM3

G12

DDR_DQS0N

B24

DDR_DQS0P

C24

DDR_DQS1N

B12

DDR_DQS1P

A12

DDR_DQS2N

E24

DDR_DQS2P

D23

DDR_DQS3N

E12

DDR_DQS3P

D11

DDR_A0

D20

DDR_A1

G15

DDR_A2

A18

DDR_A3

D14

DDR_A4

B19

DDR_A5

A16

DDR_A6

C21

DDR_A7

A15

DDR_A8

D15

DDR_A9

C16

DDR_A10

E16

DDR_A11

D18

DDR_A12

E15

DDR_A13

A19

DDR_A14

B16

DDR_RAS_N

G18

DDR_CAS_N

D17

DDR_WE_N

D19

DDR_BA0_N

F15

DDR_BA1_N

E21

DDR_BA2_N

F21

DDR_CS0_N

F16

DDR_CS1_N

E19

DDR_ODT0_N

D16 F18

DDR_CKE0

F19 E18

DDR_CLKN

B18

DDR_CLKP

C18

DDR_RESET_N

C19

DDR_QUSE0

D27

DDR_QUSE1

D26

DDR_QUSE2

E9

DDR_QUSE3

F9

DDR_COMP_PU

B21

DDR_COMP_PD

B15

DDR_RAS_N 19

DDR_CAS_N 19

DDR_WE_N 19

DDR_BA0_N 19

DDR_BA1_N 19

DDR_BA2_N 19

DDR_CS0_N 19

DDR_CS1_N 19

DDR_ODT0_N 19

DDR_CKE0 19

DDR_RESET_N 19

No Use

R53

40.2R2F N /A

1 2

40.2R2F

40.2R2F R54

R54

VDDIO_DDR

DDR_CLK_R_C

C51

0.01U10VX7RC1K

N/A

12

1

R51

45.3R2F

N/A

DDR_CLKN 19 DDR_CLKP 19

A A

Title :

T30 DDR

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

8 60Wednesday, March 21, 2012

Rev

2.0

5

4

3

2

1

0502

CSI_CLKAN CSI_CLKAP

CSI_D1AN CSI_D1AP

CSI_D2AN CSI_D2AP

CSI_CLKBN CSI_CLKBP

CSI_D1BN CSI_D1BP

DSI_CSI_RUP

DSI_CSI_RDN

DSI_CSI_TEST_OUT

T30 VI

VI_MCLK

VI_PCLK

VI_HSYNC VI_VSYNC

VI_DO0 VI_DO1 VI_DO2 VI_DO3 VI_DO4 VI_DO5 VI_DO6 VI_DO7 VI_DO8 VI_DO9 VI_DO10 VI_DO11

1.2V

D D

0.1U6.3VX5RC1K

MAX77663 LDO7

AVDD_DSI_CSI

12

C52

N/A

AVDD_DSI_CSIVDD_PMU_LDO7_1V2

12

C53

4.7U6.3VX5RC2M

N/A

0620

U2H

7/22 DSI & CSI

(1.2V)

AVDD_DSI_CSI

AB6

AVDD_DSI_CSI

1.2V

C C

B B

T30L-R-P-A3

N/A

1.8V

DSI_CSI_TEST_OUT

0626

VDDIO_CAM_T30SVDD_1V8_GEN_CPU

CSI_CLKAN CSI_CLKAP

CSI_D1AN CSI_D1AP

CSI_D2AN CSI_D2AP

CSI_CLKBN CSI_CLKBP

CSI_D1BN CSI_D1BP

CSI_D2BN CSI_D2BP

DSI_CLKAN DSI_CLKAP

DSI_D1AN DSI_D1AP

DSI_D2AN DSI_D2AP

DSI_CSI_RUP

DSI_CSI_RDN

AC4 AD4

AD3 AD2

AE2 AE3

AG3 AG2

AD1 AE1

AH2 AH1

AA1 AB1

AB2 AB3

AA2 AA3

AG4

AJ3

AB4

T30 GPIO

PRO_RST#

HDMI_VBUS_EN_OC#

EN_VDDIO_SD EN_VDD_MC

BAT_IN_CPU# COMPASS_DRDY ALS_INT#_MB GS_INT LVDS_SHTDN# CAM_RST_2M EN_VDD_PNL DSP_RST# EN_VDD_FUSE EN_HVDD_PEX DSP_PWDN# SDMMC1_WP

1 2

0626

VDDIO_CAM_T30S

12

C54

0.1U6.3VX5RC1K

N/A

VDDIO_CAM_T30S

A A

5

12

C55

4.7U6.3VX5RC2MN/A

AD9

U2G

18/22 CAM

(1.8/2.8 ~ 3.3V)

VDDIO_CAM

T30L-R-P-A3

N/A

0626

1.8V

CAM_I2C_SCL

CAM_I2C_SDA

CAM_MCLK

GPIO_PBB0 GPIO_PBB3 GPIO_PBB4 GPIO_PBB5 GPIO_PBB6 GPIO_PBB7

GPIO_PCC1 GPIO_PCC2

4

CAM_I2C_SDA

AH7

VI_MCLK

AD5

CAM_RST_5M

AF6 AD6 AG7

PWDN_5M

AE5 AE6

PWDN_2M

AE7

NC

AC6

TEMP_ALERT#

AG6

CAM_I2C_SCL

AG5

T30S pin

AA1

BB

W5

BB

W5

BB

AA3

BB

V4

BB

AC11

BB

AF6

BB

AA9

BB

AP18

LCD

AM14

CAM

AG33

UART

V8

BB

AM36

UART

X

XX

AM16

CAM

D36

AUDIO

CSI_CLKAN 31 CSI_CLKAP 31

CSI_D1AN 31 CSI_D1AP 31

CSI_D2AN 31 CSI_D2AP 31

CSI_CLKBN 31 CSI_CLKBP 31

CSI_D1BN 31 CSI_D1BP 31

R58

49.9R2F

N/A

0626 0626

VDD_1V8_GEN VDD_1V8_GEN

12

2.2KR1J

R59

N/A

12

CAM2_PWDN

FRONT_SEL

R60

2.2KR1J

N/A

3

GPIO

Camera 1 (Rear)

Camera 2 (Front)

AVDD_DSI_CSI

R56

R56 453R2F

453R2F

N/A

1 2

R57

49.9R2F

N/A

1 2

CAM_I2C_SCL 25,26,31,44

CAM_I2C_SDA 25,26,31,44

CAM_RST_5M 31

PWDN_5M 31

PWDN_2M 31

TEMP_ALERT# 26

R61 33R2J

33R2J

1 2

12

C56

/@C56

/@

33P25VNPOC1J

Unmount

12/23 RF add 33P

VDDIO_VI

D00

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

MCLK

PCLK

HSYNC

VSYNC

VDDIO_CAM

PBB0

PBB3

PBB4

PBB5

PBB6

PBB7

PCC1

PCC2

N/AR61

N/A

CAM_MCLK 31

CW/0228 Check SI

POR

PUPD PinState

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

DOWN

15K

POR

PUPD PinState

None

UP

50K

UP

50K

2

PD

PD15K

PD

PD15K

PD

PD15K

PD

PD15K

PD

Deep Sleep

PUPD After Wake

Disable Hold

Config. Hold

Disable Hold

Disable

Disable Hold

Deep Sleep

PUPD After Wake

Config.

Z

Config.

Z

Config.

Z

Config.

Z

Config.

Z

Config.

PU

Config.

PU

Config. Reset

Hold

Title :

T30 DSI/CSI,CAM

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

9 60Tuesday, March 20, 2012

Rev

2.0

5

1.8V

D D

C C

VDD_1V8_GEN_CPU VDDIO_LCD

C57

N/AC57

VDDIO_LCD

1 2

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C58

0.1U6.3VX5RC1K

0.1U6.3VX5RC1K C59

0.1U6.3VX5RC1K

N/A

N/AC58

N/A

N/AC59

N/A

VDDIO_LCD

4

U2I

8/22 LCD

1.8V

AB13 AC13

VDDIO_LCD_1 VDDIO_LCD_2

(1.8 ~ 3.3V)

LCD_PCLK

LCD_WR_N

LCD_DE

LCD_HSYNC

LCD_VSYNC

LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23

LCD_M1

LCD_PWR0 LCD_PWR1 LCD_PWR2

LCD_SCK LCD_CS0_N LCD_CS1_N

LCD_SDOUT

LCD_SDIN

LCD_DC0

LCD_DC1

CRT_HSYNC CRT_VSYNC

DDC_SCL DDC_SDA

HDMI_INT

AG11

AH16 AG9 AF16 AF10

AE8 AF12 AD10 AK15 AK16 AK10 AK12 AG16 AG8 AD15 AK9 AJ12 AF9 AC12 AD12 AE18 AF13 AH15 AE9 AE10 AH13 AH9 AE13 AK13

AG12

AJ9 AG10 AH12

AG15 AJ15 AC10 AJ13 AH10

AE15 AE12

AD13 AJ16

AG14 AJ10

AG13

NC NC NC NC NC NC

EN_VDD_PNL

NC

EN_VDD_FUSE

NC

COMPASS_DRDY

ALS_INT#_MB

LVDS_SHTDN#

0721

3

LCD_PCLK

SNN_LCD_ER#

LCD_DE LCD_HSYNC LCD_VSYNC

LCD_D0 LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D5 LCD_D6 LCD_D7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17

EN_VDD_PNL1

SNN_LCD_PWR0 EN_3V3_FUSE SNN_LCD_PWR2

SDMMC_WP* BAT_DET* COMPASS_DRDY SNN_LCD_SDOUT ALS_IRQ*

LVDS1_SHTDN* SNN_LCD_DC1

SNN_CRT_HSYNC SNN_CRT_VSYNC

EN_VDD_PNL 21,48

EN_VDD_FUSE 5

0621

COMPASS_DRDY 26

ALS_INT#_MB 25

LVDS_SHTDN# 22

LCD_PCLK 22

LCD_DE 22 LCD_HSYNC 22 LCD_VSYNC 22

LCD_D[17..0] 22

2

VDDIO_LCD

LCD_M1

LCD_PWR0

LCD_PWR1

LCD_PWR2

LCD_SCK

LCD_CS0_N

LCD_CS1_N

LCD_SDOUT

LCD_SDIN

LCD_DC0

LCD_DC1

0502

POR

PUPD PinState

DOWN PD100K

UP 100K PU

DOWN 100K

PD

1

Deep Sleep

PUPD After Wake

Disable

Disable Hold

Hold

T30L-R-P-A3

N/A

B B

A A

Title :

T30 LCD

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

10 60Tuesday, March 20, 2012

Rev

2.0

5

4

3

2

1

3.3V

D D

1.8V

AE4 AF4

AF7

U2K

T30L-R-P-A3

10/22 HDMI

3.3V

AVDD_HDMI_1 AVDD_HDMI_2

(3.3V)

1.8V

AVDD_HDMI_PLL

(1.8V)

HDMI_TXCN HDMI_TXCP

HDMI_TXD0N

HDMI_TXD0P

HDMI_TXD1N

HDMI_TXD1P

HDMI_TXD2N

HDMI_TXD2P

HDMI_PROBE

HDMI_RSET

AK3 AK4

AJ4 AH4

AH6 AJ6

AK7 AJ7

AG1

AH3

HDMI Conn.

All HDMI pins & powers leave NC when HDMI is not be used.

U2J

9/22 VDAC

AK6

AVDD_VDAC

(2.8V)

C C

T30L-R-P-A3

VDAC_R VDAC_G VDAC_B

VDAC_VREF

VDAC_RSET

AB7 AA9 AA7

AA5

AA6

All VDAC pins & powers leave NC

CEC

B B

0818 NC son't support CEC

A A

Title :

T30 HDMI,VGA

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

11 60Saturday, March 03, 2012

Rev

2.0

5

VDDIO_BB

1.8V

D D

C69

VDDIO_BB

C C

1 2

1U6.3VX5RC2K

1U6.3VX5RC2K C70

0.1U6.3VX5RC1K

1.8V

VDDIO_UART

12

C71

0.1U6.3VX5RC1K

N/A

B B

N/A

VDDIO_BBVDD_1V8_GEN_CPU

N/AC69

N/A

N/AC70

N/A

VDDIO_UARTVDD_1V8_GEN_CPU

VDDIO_UART

AA30

4

U2S

W1

T30L-R-P-A3

N/A

U2R

14/22 UART

(1.8/3.3V)

VDDIO_UART

T30L-R-P-A3

N/A

12/22 BB

1.8V

VDDIO_BB

(1.8/3.3V)

1.8V

ULPI_DATA0 ULPI_DATA1 ULPI_DATA2 ULPI_DATA3 ULPI_DATA4 ULPI_DATA5 ULPI_DATA6 ULPI_DATA7

ULPI_CLK

ULPI_DIR ULPI_NXT ULPI_STP

DAP3_DIN

DAP3_DOUT

DAP3_FS

DAP3_SCLK

GPIO_PV0 GPIO_PV1

GEN1_I2C_SCL GEN1_I2C_SDA

UART2_TXD

UART2_RXD UART2_RTS_N UART2_CTS_N

UART3_TXD

UART3_RXD UART3_RTS_N UART3_CTS_N

Z

GPIO_PU0

Z

GPIO_PU1

Z

GPIO_PU2

Z

GPIO_PU3

Z

GPIO_PU4

Z

GPIO_PU5

Z

GPIO_PU6

DAP4_DIN

DAP4_DOUT

DAP4_FS

DAP4_SCLK

CLK3_OUT CLK3_REQ

3

Note: 'EN_VDD_SDMMC1' reserved for power gating

UART1_TXD

R3

UART1_RXD

V1 N1

WLAN_MAC_WAKEN

T3 P4

NC

T4

NC

T1

CAM_RST_2M

T2

UART4_TXD

M2

UART4_RXD

M4 N2 N4

NC

CDC_LDO1_EN

N3 M3 R4 R6

AP_ONKEY#

R1

AP_ACOK#

R2

DEBUG_GPIO0 DEBUG_GPIO1 DBG_IRQ# WF_WAKEUP ACC_IRQ* SNN_ULPI_DATA5 SNN_ULPI_DATA6 SNN_ULPI_DATA7

EN_VDD_SDMMC1 EN_VDDIO_VID_OC* EN_3V3_MODEN SNN_DAP3_SCLK

SNN_D_AP_ONKEY# SNN_D_AP_ACOK#

GPI : Disable SD card write protection

JTAG

不不不不不不不不不不不不不不不不不不不不, 需需需需需需需需

+3VSUS_CPU +3VSUS_CPU

12

R75

4.7KR1J

N/A

BT_EN BT_WAKEUP GPS_PWRON GPS_RST* MB_DET_DOCK* GPS_IRQ# BT_IRQ*

12

R76

4.7KR1J

N/A

AB25 V29

W25 AB28 AB26 AA25

AC27 W27 AB29 W29

AA28 V30 AB30 AB27 AC25 W30 AA27

AA29 W28 AA24 AA26

Y27 W24

0906 NV change

2.2K -> 4.7K

GEN1_I2C_SCL GEN1_I2C_SDA

GPS_UART2_TXD GPS_UART2_RXD GPS_UART2_RTS# GPS_UART2_CTS#

BT_UART3_TXD BT_UART3_RXD BT_UART3_RTS# BT_UART3_CTS#

BT_EN BT_WAKEUP GPS_PWRON

DOCK_IN# AP_CHARGING#

BT_IRQ#

DAP4_DIN DAP4_DOUT DAP4_FS DAP4_SCLK

CLK3_OUT CLK3_REQ

WLAN_MAC_WAKEN 41

CAM_RST_2M 31

CDC_LDO1_EN 27

AP_ONKEY# 33 AP_ACOK# 33

No Use

DSP_1V8_EN -> CODEC_1V8_EN

TX/RX GND

Cardhu use 4.7K

GEN1_I2C_SCL GEN1_I2C_SDA

GPS_UART2_TXD 43

GPS_UART2_RXD 43

GPS_UART2_RTS# 43

GPS_UART2_CTS# 43

BT_UART3_TXD 41

BT_UART3_RXD 41

BT_UART3_RTS# 41

BT_UART3_CTS# 41

BT_EN 40,41 BT_WAKEUP 40,41 GPS_PWRON 40,43

DOCK_IN# 28 AP_CHARGING# 33

BT_IRQ# 41

DAP4_DIN 41 DAP4_DOUT 41 DAP4_FS 41 DAP4_SCLK 41

GEN1_I2C no use KAI -- ALS, Compass, G yro, NFC I2C connect to GEN1 I2C Current connect to CAM_I2C

DOCK_IN# -> MAX8903B_CHG#_1V8

williams 0602

2

Debug??

GPIO

Debug??

UART4_TXD

UART4_RXD

UART1_TXD

UART1_RXD

GPS UART

BT UART

GPIO

BT PCM

VDDIO_BB

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

PV0

PV1

VDDIO_BB

DAP3_DIN

DAP3_DOUT

DAP3_FS

DAP3_SCLK 100K

Unmount

1 2

R690R1J /@R690R1J /@

R700R1J /@R700R1J /@

R720R1J N/AR720R1J N/A

R730R1J N/AR730R1J N/A

VDDIO_UART

PU0

PU1

PU2

PU3

PU4

PU5

PU6 None Z

POR

PUPD PinState

UP 100K

UP PU

100K

UP 100K

None Z

POR

PUPD PinState

DOWN 100K

100K

DOWN

100K

DOWN

VDD_1V8_GEN_CPU

12

R71

R71 1MR1J

1MR1J

/@

12

R74

R74 1MR1J

1MR1J

N/A

POR

PUPD PinState

None Z

None

Deep Sleep

PUPD After Wake

PU

Disable

PU Disable

PU

Disable

PU

Config.

PU

Config. Hold

PU

Disable

Disable Hold

PU

Config. Hold

Deep Sleep

PUPD After Wake

PD

Disable

PD Disable

PD

Disable

PD

Disable

Unmount

UART_DEBUG_TXD 24,28

UART_DEBUG_RXD 24,28

0902

PUPD After Wake

Disable Hold

Z

Disable

Z

Disable

Z

Disable

Z

Disable

Z

Config.

1

Hold

Deep Sleep

Hold

A A

Title :

T30 BB,UART

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

12 60Tuesday, March 20, 2012

Rev

2.0

5

4

3

2

1

D D

1.8V

VDD_IO_AUDIO DAP_MCLK1 27

C C

B B

VDD_IO_AUDIOVDD_1V8_GEN_CPU

C30

U2Q

13/22 AUDIO

1.8V

VDDIO_AUDIO

(1.8/3.3V)

T30L-R-P-A3

N/A

VDD_IO_AUDIO

12

C72

0.1U6.3VX5RC1K

N/A

CLK1_OUT CLK1_REQ

DAP1_SCLK

DAP1_FS

DAP1_DOUT

DAP1_DIN

DAP2_SCLK

DAP2_FS

DAP2_DOUT

DAP2_DIN

SPDIF_IN

SPDIF_OUT

SPI1_SCK

SPI1_CS0_N

SPI1_MOSI SPI1_MISO

SPI2_SCK SPI2_CS0_N SPI2_CS1_N SPI2_CS2_N

SPI2_MOSI SPI2_MISO

Change

09002-00050000 N/A

DAP_MCLK1_H

C27

NC

F26

G29 D28 G26 G25

DAP2_SCLK_H

C28

DAP2_FS_H

C29

DAP2_DOUT

G27

DAP2_DIN

F27

NC NC

NC

SNN_SPDIF_IN SNN_SPDIF_OUT

HOOK_DET#_CPU CDC_IRQ# HEAD_DET#

LINOUT_DET

GYRO_INT

H27 A28

B28 J24 F29 F28

D29 G28 F25 E27 B27 D30

SNN_MODEM_AUDIO_CLK SNN_MODEM_AUDIO_CS SNN_MODEM_AUDIO_DI SNN_MODEM_AUDIO_DOUT

SNN_DIS_5V_SWITCH SNN_SATA_DET* HP_DET* CDC_IRQ* NFC_IRQ*NC GYRO_IRQ*

DAP2_DOUT 27

DAP2_DIN 27

HOOK_DET#_CPU

CDC_IRQ# 27 HEAD_DET# 28

LINOUT_DET 28 NFC_IRQ_R 44

GYRO_INT 26

27P25VNPOC1J

C75

/@

27P25VNPOC1J

GPIO

12

C73

C73 33P25VNPOC1J

33P25VNPOC1J

N/A

12

C89

/@

09002-00050000 N/A

R77 0R1J

1 2

R78 33R1J N/AR78 33R1J N/A

1 2

R79 33R1J N/AR79 33R1J N/A

1 2

12

C76

C76 27P25VNPOC1J

27P25VNPOC1J

/@

Unmount

1 2

12

Unmount

R2340R1JN/A R2340R1JN/A

12

C74

C74 33P25VNPOC1J

33P25VNPOC1J

/@

Unmount

HOOK_DET# 28

DAP2_SCLK 27 DAP2_FS 27

REMOVE FM I2S 0609

CODEC

0229 EMI add

VDD_IO_AUDIO

SPI2_SCK

SPI2_CS0_N

SPI2_CS1_N

SPI2_CS2_N

SPI2_MOSI

SPI2_MISO

POR

PUPD PinState

UP 100K

DOWN 100K

PU

PDPDDisable

Deep Sleep

PUPD After Wake

Disable

Disable Reset

Config.

Disable

Reset

Hold

A A

Title :

T30 AUDIO

Richard Lin

Engineer:

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

ME370T

1

Richard Lin

13 60Tuesday, March 20, 2012

Rev

2.0

5

3.3V

D D

TPS63020 buck-boost

+3VSUS AVDD_USB

12

0720

C62

0.1U6.3VX5RC1K

N/A

AVDD_USB_DISCHARGE

EN_AVDD_USB50

1 2

5

IN

4

DIS

1 2

R68

R68 0R2J /@

0R2J /@

U14

OUT GND

EN

NCT3521U

330R1J

330R1J R66

1 2 3

N/A

N/AR66

N/A

MAX77663 GPIO2

Signal from MAX77663

EN_AVDD_USB from MAX77663 GPIO2, check PU resister in PMU side(100k PU to VPH_PWR_CHGR)

C77

N/AC77

AVDD_USB

C C

1 2

1.8V

T30 AVDD_USB_PL L 1.8V

VDD_1V8_GEN AVDD_USB_PLL

B B

1 2

CORE_PWR_REQ6,50

Q2

Q2 SI2305DS

SI2305DS

N/A

R63

N/AR63

N/A

EN_AVDD_USB_PLL__SWITCH_1

100KR1J

From T30

N/A

4.7U6.3VX5RC2M

4.7U6.3VX5RC2M C78

N/AC78

N/A

0.1U6.3VX5RC1K

SI2305DS 2nd Source 07G005C69010 P-MOSFET EMF44P02J SOT-23 07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2 07G005051310 P-MOSFET NTR2101PT1G SOT-23 07G00538101L P-MOSFET AP2305GN SOT-23

AVDD_USB_PLL_1

Unmount

D

S

D

S

2 3

2

3

G

12

1

12

R64

R64 10KR1J

10KR1J

N/A

EN_AVDD_USB_PLL_SWITCH_3

61

Q3A

Q3A UM6K1N

UM6K1N

2

N/A

C63

C63 100P25VNPOC1J

100P25VNPOC1J

/@

5

12

R62

R62 330R1J

330R1J

N/A

34

Q3B

Q3B UM6K1N

UM6K1N

N/A

Vth=1.5V

EN_AVDD_USB_PLL__SWITCH_2

R80

30Ohm/100Mhz

21

4

N/AR80

N/A

AVDD_USB_PLL

12

C79

0.1U6.3VX5RC1K

N/A

3

AVDD_USB

AVDD_USB_PLL

0229 EMI add Close to CPU

0.1U6.3VX5RC1K

Unmount

0620

U2L

11/22 USB

(3.3V)

3.3V

U12

AVDD_USB

(1.8V)

1.8V

U4

AVDD_USB_PLL

T30L-R-P-A3

N/A

U2N

16/22 IC_USB

V9

AVDD_IC_USB

(1.8V)

USB1_VBUS

C90

/@

2

USB1_VBUS

12

C80

0.1U6.3VX5RC1K

12

USB1_DN USB1_DP

0.1U6.3VX5RC1K

Unmount

C81

4.7U6.3VX5RC2M

N/A

1014 TF201 add

W5

W3 W2

T7

/@

USB1_VBUS

USB1_DN USB1_DP

USB1_ID

AVDD_USB

USB1_VBUS

12

USB1_VBUS

ACC1_DETECT

Q6

SI2305DS

D

3

G

1

ACOK_DOCKOK_3

12

R82

R82 100KR1J

100KR1J

N/A

ACOK_DOCKOK_2

61

Q5A

Q5A UM6K1N

UM6K1N

2

N/A

USB1_VBUS

USB1_DN 28,49 USB1_DP 28,49

0229 EMI add

Close to CPU

0.1U6.3VX5RC1K

Unmount

SNN_USB2_VUS

V5

USB2_VBUS

T6

USB2_DN

T5

USB2_DP

ACC2_DETECT

USB3_VBUS

USB3_DN USB3_DP

ACC3_DETECT

USB_REXT

IC_USB_DN IC_USB_DP

W4

R5

V3 V2

V4

Y4

W8 W9

SNN_USB2_ID

SNN_USB3_VUS

SNN_USB3_ID

USB_RSET

SNN_IC_USB_DNSNN_AVDD_IC_USB SNN_IC_USB_DP

12

R84

R84 1KR1F

1KR1F

N/A

VDD_USB1_VBUS

S

N/A

23

2

R81

R81 1MR1J N/A

1MR1J N/A

1 2

SI2305DS 2nd Source 07G005C69010 P-MOSFET EMF44P02J SOT-23 07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2 07G005051310 P-MOSFET NTR2101PT1G SOT-23 07G00538101L P-MOSFET AP2305GN SOT-23

AVDD_USB

12

100KR1J

12

C156

/@

3G Module

Dock USB HUB

1

USB VBUS

R83

/@

Unmount

USB Conn.(OTG)

USB1_ID 28

T30L-R-P-A3

N/A

A A

Note:

1. once USB1 is connected and USB1_VBUS is a wake source, our EMC, CPU would run at max frequency and voltage.

2. USB1_VBUS must be powered w hen force recovery mode.

3. USB1_VBUS is powered with U SB_DP/N data transition, SW wil l recognize that a HOST PC is plugged in.

5

4

3

W7

U2M

15/22 HSIC

(1.2V)

VDDIO_HSIC

T30L-R-P-A3

N/A

IC_USB_REXT

HSIC_DATA

HSIC_STROBE

HSIC_REXT

HSIC_DATA

V6

HSIC_STROBE

V7

W6

ASUSTeK COMPUTER INC. EPAD

Size Project Name

C

Date: Sheet of

2

Date: Sheet of

Title :

Engineer:

ME370T

1

T30 USB,HSIC,ICUSB

Richard Lin

14 60Wednesday, March 21, 2012

Rev

2.0

SNN_IC_USB_REXT

V8