Apple Macbook Air A2337 Schematic

X1757/MLB

LAST_MODIFICATION=Tue May 5 21:26:43 2020LAST_MODIFICATION=Tue May 5 21:26:43 2020

DATESYNCCSAPAGEDATESYNCCONTENTSCSAPAGE

1
2
3
4
5
6

8
9
10
11
12
13
14

1
2
3
4
5
6
7

9
10
11
12
13
14

Table of Contents
BOM Configuration
BOM Configuration
PD Parts
SOC: Support

SOC: AP I/Os
SOC: LPDP & MIPI
SOC: PCIE
SOC: AOP
SOC: POWER (DDR,SRAM)
SOC: POWER (IO)
SOC: POWER (SOC, CPU, GPU)
SOC: POWER (SRAM)

eli 08/27/2019

06/06/2019
06/06/2019
06/06/2019

ref_soc_h13g

ref_soc_h13g
ref_soc_h13g
ref_soc_h13g 54
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g

05/04/2020
05/04/2020
05/04/20207
05/04/20208
05/04/2020
05/04/2020
05/04/2020
05/04/2020
05/04/2020
05/04/2020

46
47
48
49

52
53

55
56
57
58
59

138
140
141
144

SENSORS: POWER LOW SIDE (1/2) t668
SENSORS: POWER SUPPORT
Sensors: Thermal

SENSORS: MOTION
14950 RIO Connector
150
151
152
153
154
155
156
157
159

USB-C: High Speed ATC051ref_soc_h13gSOC: CIO, USB, RESETS, CLOCKS, SWD

USB-C: High Speed ATC1

USB-C: Support 1 ATC01

USB-C: Support 2 ATC01

USB-C: Port Controller ATC0

USB-C: Port Controller ATC1 ref_usbc_ace2

USB-C: Connector(s)

USB-C: HS Level Shifters

USB-C: Project Specific

08/27/2019

t668

t668 09/27/2019
tga_140
ref_usbc_ace2
ref_usbc_ace2
ref_usbc_ace2
ref_usbc_ace2
ref_usbc_ace2

ref_usbc_ace2
ref_usbc_ace2 04/24/2020

08/27/2019

05/31/2019
04/24/2020
04/24/2020
04/24/2020
04/24/2020
04/24/2020
04/24/2020
09/26/2019

15

15

1616
17
18

17

18
19 19
20

21
21 ref_se_ceres50
22
23
24
25
26
27
28

51

52

53

57

58 ref_vr_iceman

59

77

SOC: POWER (Fixed, PLL's, Filtered)
SOC: GND
SOC: GND-2
SOC: DESENSE CAPS
SPI NOR
SOC: Project Support
Secure Element
BMU Connector, Btn Logic
PBUS SUPPLY & BATTERY CHARGER
BATTERY CHARGER SUPPORT
POWER: 3V8 AON (1/2)
POWER: 3V8 AON (2/2)
POWER: 3V8 AON SUPPORT
PMU: SLAVE INPUT PWR & BUCKS

ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g

tga_140
ref_charger_suona
ref_charger_suona
ref_vr_iceman

T585_REF_VR_ICEMAN_0.36.0
ref_pmu_sera_simetra

05/04/2020
05/04/2020 ref_wireless_rasputin
05/04/2020
10/08/2019
05/04/2020

03/29/2020
05/31/2019
05/02/2020
05/02/2020
04/20/2020
04/20/2020
10/11/2019
04/28/2020

60
61

201

WIFI/BT: MODULE

WIFI/BT: ANTENNA and GND 04/28/2020
62 220 STORAGE: SSD0 S5E <0>
63 STORAGE: SSD0 S5E <1>
64
65

221
224
230

STORAGE: NON OCARINA SUPPORT

STORAGE: SSD Support

23166 SECDIS: MIPI MUX ref_secdis_mipimux 10/07/2019
67
68

236

237

23869
70 239
71
72
73

242

243

244

eDP Display Connector
DISPLAY POWER SEQUENCER ref_panelpwr_bnj
BEN: CONTROLLER
BEN: KEYBOARD
SECDIS: AMR
SECDIS: FPGA
Audio Level Shifters

ref_wireless_rasputin200

ref_storage_s5e
ref_storage_non_ocarina_support
T668

tga_140

ref_blc_ben
ref_blc_ben
ref_secdis_amr
ref_secdis_sak
ref_spkramp_tas5770

04/28/2020

05/02/2020ref_storage_s5e
05/02/2020
02/17/2020
08/01/2019

05/31/2019
05/02/2020
11/20/2019
11/20/2019
10/21/2019
04/28/2020
11/18/2019

29
30

78

79
31 80
32
33
34
35
36
37
38
39
40
41
42

81

82

83

84

121

122

123

127

128

130

131

PMU: SLAVE LDO
PMU: SLAVE GPIO & GND
PMU: Slave extra
PMU: MASTER INPUT PWR & BUCKS
PMU: MASTER BUCKS & GND
PMU: MASTER LDO & GPIO
PMU: Master extra
Power: LDOs
POWER: 5V, 3V3 Support
POWER: 5V S2
POWER: 3V3 S2
Power: Load Switches
I2C: SIO, DISP
I2C: ISP, AOP

ref_pmu_sera_simetra
ref_pmu_sera_simetra

ref_pmu_sera_simetra

ref_pmu_sera_simetra

tga_140

ref_vr_5v_lt8642s
ref_vr_3v3_tps62135
tga_140
eli
T668

04/28/2020
04/28/2020

04/28/2020
04/28/2020ref_pmu_sera_simetra
04/28/2020

05/31/2019

04/20/2020
01/02/2020
05/31/2019
10/15/2019
08/01/2019

74
75

246
248

AUDIO AMPLIFIERS (1/2)

Audio Connectors
76 253 Trackpad Support
77 254
78
79
80
81

260 Power Aliases - 1 tga_140 05/31/2019
261
263

264 Signal Aliases 2
82 270
83
84
85

281

500

501
86 502
87

503

IPD Combined Connector

Power Aliases - 2
Signal Aliases 1

DEBUG
Desense

17.2 RULES

17.2 PHYSICAL CSETS

17.2 SPACING CSETS, ISO

ref_spkramp_tas5770
tga_140
ref_ipd_oregano 08/01/2019
card_ipd_oregano 08/01/2019

tga_140

tga_140

eli
eli
eli 10/15/2019
eli17.2 SPACING CSETS, CLASS-CLASS

04/20/2020
05/31/2019

05/31/2019

05/31/2019

10/15/2019
10/15/2019

10/15/2019

43
44
45

132
135
136

I2C: SMC
SENSORS: POWER HIGH SIDE (1/2) 11/01/2019t668
SENSORS: POWER HIGH SIDE (2/2)

T668
t668
t668

08/01/2019
08/27/2019
08/27/2019

88
89
90

601

602

610 BOM Alternates

BOM OPTION TABLES
BOM GROUPS

t668

11/01/2019

Programmable PartsBModule PartsA

TBT Burnside Bridge

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

338S00561 CRITICAL TBT_BB:PRQA12 UF000,UF100

IC,TBT,BBR,SLMN7,PRQ,A1,BGA105

Ace2

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123353S02158 UF400,UF500 ACE2:B2_BGA2 CRITICAL

eUSB Level Shifter

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

2 CRITICAL EUSB_LS:B0_OTP6998-20641 UF700,UF750IC,PARROT,CD2E224,B0,OTP-6,CSP25

Secure Element

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

338S00630

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_I TEM

CRITICAL2 EUSB_LS:B0_LSB1_OTP6338S00628 UF700,UF750IC,PARROT,CD2E226B,B0 LSB1,OTP-6,CSP25

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TBT ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART# BOM OPTIONCRITICAL

335S00133

IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8 CRITICAL TBT_ROM:BLANK1 UF260

PART NUMBER

ROM,TBT/ACE (V31.5) PROTO-1,X1757

ROM,TBT/ACE (V2.45.0.7) PROTO-1,X1757

UF260 CRITICAL1 TBT_ROM:PP1341S01676

SOC ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART# BOM OPTIONCRITICAL

998-20613 1 CRITICAL SOC_ROM:BLANK_ORIGU1970

335S00500 rdar://problem/59964804U1970335S00494

IC,SPI SERIAL FLASH,64MBIT,1.8V,XSON8

IC,SPI SERIAL FLASH,64MBIT,1.8V,4X3,SON8 SOC_ROM:BLANKU1970 CRITICAL1335S00494

PART NUMBER

SOC_ROM:BLANK

TABLE_ALT _HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT _ITEM

rdar://problem/50598337TBT_ROM:BLANK335S00232 UF260335S00133

CRITICAL1341S01617 TBT_ROM:PP0UF260

TABLE_ALT _HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT _ITEM

CRITICALU5000 SE:DEV_SW_V71998-19915 IC,SN210V,B1,CERES,DEV KY,SW=V7,WLCSP81

TABLE_5_I TEM

CRITICALU5000 SE:DEV_SW_H31998-21255 IC,SN210V,B1,CERES,DEV,SW=H3,WLCSP81

TABLE_5_I TEM

SE:PROD_SW_MUCRITICALU50001 IC,SN210V,B1,CERES,PROD,VER=MU,WLCSP81

BOM Configuration

A

BOM Groups

BOM GROUP BOM OPTIONS

MLB_COMMON

MLB_USBC

MLB_PROGPARTS

MLB_POWER

MLB_WIRELESS

MLB_MECH
MLB_MISC

MLB_DEV
MLB_BLC

SCHEM,PCBF,ALTERNATE,COMMON,CMN_IC,MLB_PROGPARTS,MLB_USBC,MLB_POWER,MLB_WIRELESS,MLB_MECH,MLB_MISC,MLB_BLC,EVT,SECDIS_EXT_CLK,DMIC_CLK_10OHM

TBT_BB:PRQA1,ACE2:B2_BGA,UPC_ATCRTMR_INT,UPC_EUSBLS_INT,EUSB_LS:B0_LSB1_OTP6

WFBT_ROM:BLANK,SOC_ROM:BLANK,TBT_ROM:PP1,SE:PROD_SW_MU

PBUS_3S,MPMU_IC:B0,SPMU_IC:A1,P3V8AON_IC:A1_R0B0

WLBT:ES6_3_M

SHLD_CAN_BSB:EVT,SHLD_CAN_ICE:EVT

BOARD_ID,SYSDET:FET,BOOT_CONFIG2,LOADISNS

DEVELOPMENT,WLBT_DBG,USBC_DBG

BLC_BEN_IC:V7,BLC_LEDS_PER_STRING:16,BLC_5V_CAP:4P7_UF,BLC_5V_SERIES:10_OHM,BLC_KBD_BOOST_USED:YES

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 CRITICALCBOMCOMMON PARTS,MLB,X1757 CMN_PARTS_BOM685-00339

CRITICAL1 PARTS_SSDNAND1PARTS,SSDNAND1,MLB,X1757685-00377 P1BOM

CRITICAL1 DEV1985-01176 DEV PARTS,MLB,X1757 DEV_PARTS_BOM

051-05392 SCHEMSCHEMSCHEM,MLB,X17571 CRITICAL

CRITICAL820-02016 PCBF PCBF1 PCBF,MLB,X1757

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

B

Build Specific Groups

BOM GROUP BOM OPTIONS

BOARDID1,BOARDID2BOARD_ID
PROTO0
PROTO1 BOARD_REV3,BOARD_REV2,BOARD_REV1

BOARD_REV3,BOARD_REV2,BOARD_REV1,BOARD_REV0

BOARD_REV3,BOARD_REV2,BOARD_REV0EVT

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

Pull-ups: 0x0000110

TABLE_BOM GROUP_ITEM

Pull-downs: 0x0000

TABLE_BOM GROUP_ITEM

Pull-downs: 0x0001

TABLE_BOM GROUP_ITEM

Pull-downs: 0x0002

C

DC/DC BOM Groups

BOM GROUP BOM OPTIONS

DCDC_COMMON

DCDC_USBC UPC_ATCRTMR_INT,UPC_EUSBLS_INT

D

Reference Design Pack Options

PACK_OPTIONS TO INCLUDE IN NETLIST

USBC_SPI_UPC0

USBC_DEBUG_UPC0

USBC01_VR5V_LOCAL_NO

USBC_LAPTOP

NO_DFR

FTCAM

HAS_LID

5V_S2_PBUS-D12
3V3_S2_PBUS-D2

3V8_AON_PBUS-B12

3V8_AON_I2C-DEV

NO_AMR_INTERPOSER_LEFT

NO_AMR_INTERPOSER_RIGHT

PKGS:SMALL_PITCH

ACE2_SS_CAP

SCHEM,PCBF,COMMON,DCDC_USBC,MLB_POWER,MLB_MECH,MLB_MISC,MLB_BLC,EVT

PACK_OPTIONS TO INCLUDE IN NETLISTPACK_OPTIONS TO INCLUDE IN NETLIST

PROD_SECDIS

JTAG_SECDIS:NO

PROTO_PULLDOWN_SECDIS

80UM_STEN

INTERNAL_DISPLAY

CHGR_40W

PACK_OPTIONS TO INCLUDE IN NETLIST

SUNWAY

WLBT_DBG_CONN

SPKRAMP_A

PORTABLE

SMALL_NOR

SPKRAMP_LVL_SON

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

PACK_OPTIONS TO INCLUDE IN NETLIST

CHGR_TP

CHGR_TP_BOT

3V8_EXT_DIODE

BOM Configuration

Mounting HolesA

Burnside Bridge Shield CanD

SH0400

TH-NSP TH-NSP

1

SL-3.41X2.0-5.91X4.5

998-11113

SH0402

4.6R1.7-NSP

1

998-19374998-19374

SH0401

1

SL-3.41X2.0-5.91X4.5

998-11114

SH0403

4.6X5.2R1.7X2.3-NSP

1

E

Plated slots for shield can

SH0430

TH-NSP

1

SL-0.5X1.28-1.25X2.03

Sled, Thermal Module

SHLD1SHIELD CAN,BURNSIDE BRIDGE,X1419806-19070 CRITICAL SHLD_CAN_BSB1

SH0431

TH-NSP

1

SL-0.5X1.28-1.25X2.03

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SHLD_CAN_BSB:EVTSHIELD CAN,BURNSIDE BRIDGE,X1739806-26240 1 CRITICALSHLD1

Heatsink Mounting HolesB

998-6473

SH0410

4P0R3P15-NSP

1

998-21888

SH0412

4.45R3.6-NSP

1

998-22161

SH0411

TH-NSP

1

SL-3.65X3.15-4.45X4.0

998-21888

SH0413

4.45R3.6-NSP

1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SLD1,SLD22 CRITICAL806-25230 SLED,SOLDER,X1757

C

Antenna Cowling Bosses

860-01273

SH0420

5.25X2.8R-1.4ID-1.81H-SM

1

F

Inductor Shield Fence

SHIELD FENCE,ICEMAN,INDUCTORS,X1739806-27192 SHLD2 SHLD_CAN_ICE1 CRITICAL

Plated slots for shield can

998-1681

SH0440

TH

1

SL-0.4X1.20

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

998-1681

SH0441

TH

1

SL-0.4X1.20

SHLD_CAN_ICE:EVTSHIELD,FENCE,INDUCTORS,X1739806-27475 CRITICAL1 SHLD2

PD Parts

**OK2INTEGRATE**

BOOT CONFIG ID

720

720

720

BOOT_CONFIG2

OUT

BOOT_CONFIG1

OUT

BOOT_CONFIG0

OUT

BOOT_CFG[2:0]

000
001
010
011

POR ---> 100

101
110
111

78 12 9 7 6 5

PP1V25_AWAKE_IO

MODE
SPI1 NOR (12 MHZ)
SPI1 NOR (12 MHZ) TESTMODE
SPI0 NAND
SPI0 NAND TESTMODE
SPI1 NOR (40 MHZ)
SPI1 NOR (40 MHZ) TESTMODE
SPI1 NOR (6 MHZ)
SPI1 NOR (6MHZ) TESTMODE

1

R0502

4.7K

5%
1/20W
MF
201

2

1

R0501

4.7K

5%
1/20W
MF
201

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

BOOT_CONFIG0BOOT_CONFIG1BOOT_CONFIG2

1

R0500

4.7K

5%
1/20W
MF
201

2

R0533

10K

5%

1/20W

MF

201

R0534

10K

5%

1/20W

MF

201

21

SOC_JTAG_SEL

21

SOC_TESTMODE

OUT

OUT

10

6

BOARD ID

78 12 9 7 6 5

7

7

7

7

7

BOARD_ID4

OUT

BOARD_ID3

OUT

BOARD_ID2

OUT

BOARD_ID1

OUT

BOARD_ID0

OUT

PP1V25_AWAKE_IO

BOARDID4

1

R0514

1K

5%
1/20W
MF
201

2

1

R0513

1K

5%
1/20W
MF
201

2

1

R0512

1K

5%
1/20W
MF
201

2

BOARDID0BOARDID1BOARDID2BOARDID3

1

R0511

1K

5%
1/20W
MF
201

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

1

R0510

1K

2

5%
1/20W
MF
201

PP1V25_AWAKE_IO

78

SEP EEPROM (128-Kbit)

PP1V8_AWAKE

1

R0540

2.2K

5%
1/20W
MF
201

2

R0535

10K

5%

1/20W

MF

201

SOC_HOLD_RESET

21

R0536

10K

1/20W

(Write: 0xA2, Read 0xA3)

21

SOC_KIS_DFU_SELECT

5%
MF

201

APN:335S00455

1

R0541

2.2K

5%
1/20W
MF
201

2

VCC

U0500

STOCT

DFN

OUT

OUT

6

6

1

C0500

1.0UF

20%
4V

2

X6S
0201

REFERENCE DESIGN ATOR

U0600

PIN DELAY MAPPING FILE

PIN DELAY CSV FI LE NAME

TGA_PINDELAY_2020_03_26.csv

BOARD REVISION

7

OUT

7

OUT

7

OUT

7

OUT

BOARD_REV0
BOARD_REV1
BOARD_REV2
BOARD_REV3

BOARD_REV3

1

R0523

1K

5%
1/20W
MF
201

2

NOTE: STUFFING RESISTOR MEANS 0

BOARD_REV0BOARD_REV1BOARD_REV2

1

R0522

1K

5%
1/20W
MF
201

2

1

R0521

1K

5%
1/20W
MF
201

2

R0520

1K

5%
1/20W
MF
201

2

I2C_SEEPROM_SCL

7

I2C_SEEPROM_SDA

7

OCELOT I2C pulls

7

SCL

6

SDA

VSS EPAD

VIO

NC

5

2

NC

3

NC

4

NC

board rev should start at 0b0000 and increment each rev.

S/W READ FLOW

1. SET GPIO AS INPUT

2. ENABLE PU AND DISABLE PD

3. READ

PAGE TITLE

SOC: Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

5 OF 801

SHEET

5 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

D

2

1

8

**OK2INTEGRATE**

SOC: CIO, USB, DRAM, RESETS, CLOCKS, SWD, FPWM

OMIT_TABLE

U0600

TMLR68A0-B09

BGA

SYM 1 OF 23

10347282

IN

6345482

5

IN

345382

IN

5

IN

PMU_RESET_L

SOC_FORCE_DFU
SOC_REQUEST_DFU1

6

SOC_REQUEST_DFU2

6

SOC_TESTMODE

PMU_ACTIVE_READY

SOC_HOLD_RESET

R2

AA49
AK55
AJ54

AD2

AL54

AC1

LP4_IN_RESET_N

FORCE_DFU
REQUEST_DFU1
REQUEST_DFU2

TESTMODE

CFSB

HOLD_RESET

IPD

IPD

RESET

DFU_STATUS

V51

SOC_DFU_STATUS

OUTIN

20 54 82

AMUX_OUT can go to TP or to AMUX_IN on PMU

SOC_KIS_DFU_SELECT

5

20

BI

20

BI

58

IN

58

OUT

EUSB_ATC0_P
EUSB_ATC0_N

CIO_ATC0_LSRX_1V2
CIO_ATC0_LSTX_1V2

SOC_ATC0_USB_RESREF

6

AB49

BB54
BB55

BE18
BE13

BB53

KIS_DFU_SELECT

ATC0_USB_EDP
ATC0_USB_EDM

USB_C0_LSRX
USB_C0_LSTX

ATC0_USB_RESREF

CLOCKS

XI0
XO0

TST_CLKOUT

BE36
BF36

P54

SOC_XTAL24M_IN
SOC_XTAL24M_OUT

TPT_TST_CLKOUT

20

SOC_ATCPHY0_RCAL_POS

6

SOC_ATCPHY0_RCAL_NEG

6

SOC_ATCPHY1_RCAL_POS

6

SOC_ATCPHY1_RCAL_NEG

6

1

R0600

200

1%
1/20W
MF
201

2

1

C0600

10PF

5%
25V

2

C0G
0201

1

R0601

200

1%
1/20W
MF
201

2

1

C0601

10PF

5%
25V

2

C0G
0201

TPT_TMU_CLK_OUT0

20

20

BI

20

BI

58

IN

58

OUT

51

BI

51

BI

51

OUT

51

OUT

51

BI

51

BI

51

OUT

51

OUT

51

BI

51

BI

52

BI

52

BI

52

OUT

52

OUT

52

BI

52

BI

52

OUT

52

OUT

EUSB_ATC1_P
EUSB_ATC1_N

CIO_ATC1_LSRX_1V2
CIO_ATC1_LSTX_1V2

SOC_ATC1_USB_RESREF

6

TPT_TMU_CLK_OUT1

20

USB_VBUS_DETECT

6

USBC_ATC0_D2R_P<1>
USBC_ATC0_D2R_N<1>
USBC_ATC0_R2D_C_P<1>
USBC_ATC0_R2D_C_N<1>

USBC_ATC0_D2R_P<2>
USBC_ATC0_D2R_N<2>
USBC_ATC0_R2D_C_P<2>
USBC_ATC0_R2D_C_N<2>

USBC_ATC0_AUX_P
USBC_ATC0_AUX_N

SOC_ATCPHY0_RCAL_POS

6

SOC_ATCPHY0_RCAL_NEG

6

USBC_ATC1_D2R_P<1>
USBC_ATC1_D2R_N<1>
USBC_ATC1_R2D_C_P<1>
USBC_ATC1_R2D_C_N<1>

USBC_ATC1_D2R_P<2>
USBC_ATC1_D2R_N<2>
USBC_ATC1_R2D_C_P<2>
USBC_ATC1_R2D_C_N<2>

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

V48

BC54
BC55

BD3

BE10

BC53

R48

AG1

BE50
BF50
BC49
BD49

BE48
BF48
BC47
BD47

AY51
AY52

BE52
BF52

BF44
BE44

BF46
BE46
BD45
BC45

USB_C0_HPD/TMU_CLK_OUT0

ATC1_USB_EDP
ATC1_USB_EDM

USB_C1_LSRX
USB_C1_LSTX

ATC1_USB_RESREF

USB_C1_HPD/TMU_CLK_OUT1

EUSB_VBUS_DETECT

ATCPHY0_RX0_P
ATCPHY0_RX0_N
ATCPHY0_TX0_P
ATCPHY0_TX0_N

ATCPHY0_RX1_P
ATCPHY0_RX1_N
ATCPHY0_TX1_P
ATCPHY0_TX1_N

ATCPHY0_AUX_P
ATCPHY0_AUX_N

ATCPHY0_RCAL_P
ATCPHY0_RCAL_N

ATCPHY1_RX0_P
ATCPHY1_RX0_N
ATCPHY1_TX0_P
ATCPHY1_TX0_N

ATCPHY1_RX1_P
ATCPHY1_RX1_N
ATCPHY1_TX1_P
ATCPHY1_TX1_N

ATC

SWD

FPW

ANALOGMUX_OUT

SWD_TCK_OUT1

SWD_TMS2
SWD_TMS3
SWD_TMS4

FPWM0/MASTER_SYNC_GEN_0

FPWM1
FPWM2

AL48

AJ1
U54
V54
AH3

V50
Y49

SOC_AMUX_OUT

SWD_NAND0_SWCLK
SWD_NAND0_SWDIO
NC_SWD_TMS3
NC_SWD_TMS4

IPD

WLAN_TIME_SYNC
KBD_BKLT_PWM
NC_FPWM2

78 12 9 7 6 5

6

PP1V25_AWAKE_IO

SOC_REQUEST_DFU1

OUT

OUT

BI

81

81

IN

OUT

81

1

2

20

20

20

60

70

78 12 9 7 6 5

R0630

10K

5%
1/20W
MF
201

499

1%

1/20W

MF

201

1

2

R0651

SOC_24M_O_R

CRITICAL

1

C0650

15PF

5%
50V

2

C0G
0201

PP1V25_AWAKE_IO

SOC_REQUEST_DFU2

6

CRITICAL

Y0600

1.60X1.20MM

24.000MHZ-20PPM-9.5PF-60OHM

31

42

SOC_FORCE_DFU

6345482

1

R0631

10K

5%
1/20W
MF
201

2

CRITICAL

1

C0651

15PF

5%
50V

2

C0G
0201

1

R0632

47K

5%
1/20W
MF
201

2

78 12 9 7 6 5

PP1V25_AWAKE_IO

USB_VBUS_DETECT

6

1

R0639

0

5%
1/20W
MF
0201

2

52

BI

52

BI

USBC_ATC1_AUX_P
USBC_ATC1_AUX_N

SOC_ATCPHY1_RCAL_POS

6

SOC_ATCPHY1_RCAL_NEG

6

BA52
BA51

BF42
BE42

ATCPHY1_AUX_P
ATCPHY1_AUX_N

ATCPHY1_RCAL_P
ATCPHY1_RCAL_N

SOC_ATC0_USB_RESREF

6

1

R0641

200

1%
1/20W
MF
201

2

SOC_ATC1_USB_RESREF

6

1

R0640

200

1%
1/20W
MF
201

2

PAGE TITLE

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SOC: CIO, USB, RESETS, CLOCKS, SWD

SIZE

D

PART NUMBER

197S0591 EPSON,24MHZ.XTAL197S0590 Y0600
197S0591 TXC,24MHZ,XTAL197S0588 Y0600

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

BOM_COST_GROUP=SOC

TABLE_ALT _HEAD

TABLE_ALT _ITEM

TABLE_ALT _ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

6 OF 801

SHEET

6 OF 92

2

13

6

**OK2INTEGRATE**

all signals are 1.2 unless otherwise specified.
all signals on this page reference PP1V2_AWAKE_GRP if they are 1.2V
if they are 1.8V they reference PP1V8_AWAKE_GRP

SOC: I/Os

U0600

TMLR68A0-B09

BGA

SYM 3 OF 23

20

OUT

80

IN

20

OUT

20

OUT

TDM_SPKRAMP_L_BCLK_R
TDM_SPKRAMP_L_D2R
TDM_SPKRAMP_L_R2D_R
TDM_SPKRAMP_L_FSYNC_R
NC_SOC_I2S0_MCK

81

AK4
AJ3
AJ5
AJ4
AK3

I2S0_BCLK
I2S0_DIN
I2S0_DOUT
I2S0_LRCK
I2S0_MCK

IPD

IPD

IPD

SPI0_MISO
SPI0_MOSI
SPI0_SCLK

SPI1_MISO
SPI1_MOSI

20

OUT

80

IN

20

OUT

20

OUT

TDM_SPKRAMP_R_BCLK_R
TDM_SPKRAMP_R_D2R
TDM_SPKRAMP_R_R2D_R
TDM_SPKRAMP_R_FSYNC_R
NC_SOC_I2S1_MCK

81

AG3
AF3
AG4
AF2
AG2

I2S1_BCLK
I2S1_DIN
I2S1_DOUT
I2S1_LRCK
I2S1_MCK

IPD

I2S

SPI

IPD

SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK

50

OUT

50

IN

50

OUT

50

OUT

TDM_CODEC_BCLK_R
TDM_CODEC_D2R
TDM_CODEC_R2D_R
TDM_CODEC_FSYNC_R
NC_SOC_I2S2_MCK

81

AK5
AL6
AJ7
AM4
AK6

I2S2_BCLK
I2S2_DIN
I2S2_DOUT
I2S2_LRCK
I2S2_MCK

SPI2_SSIN

IPD

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

NC_I2S3_BCLK

81

NC_I2S3_D2R

81

NC_I2S3_R2D

81

NC_I2S3_LRCLK

81

NC_I2S3_MCLK

81

AH6
AH4
AG5
AJ6
AF5

I2S3_BCLK
I2S3_DIN
I2S3_DOUT
I2S3_LRCK
I2S3_MCK

IPD

SPI4_MISO
SPI4_MOSI
SPI4_SCLK
SPI4_SSIN

AL4
AK2
AK1

AD4
AE4
AF4
AE3

AF53
AF54
AF55
AF52

Y1
W1
AB1
AA1

AC4
AB4
AA4
AB3

BOOT_CONFIG2
BOOT_CONFIG1
BOOT_CONFIG0

SPI_SOCROM_MISO
SPI_SOCROM_MOSI_R
SPI_SOCROM_CLK_R
SPI_SOCROM_CS_L

SPI_1V8_TOUCHID_MISO
SPI_1V8_TOUCHID_MOSI_R
SPI_1V8_TOUCHID_CLK_R
NC_SOC_SPI2_SSIN

SPI_IPD_MISO
SPI_IPD_MOSI_R
SPI_IPD_CLK_R
SPI_IPD_CS_L

SPI_TCON_MISO
SPI_TCON_MOSI_R
SPI_TCON_CLK_R
SPI_TCON_CS_L

5 20

IN

5 20

OUT

5 20

OUT

19

IN

19

OUT

19

OUT

19

OUT

50

IN

50

OUT

50

OUT

81

76

IN

20

OUT

20

OUT

76

OUT

67

IN

20

OUT

20

OUT

67

OUT

1.8V IO

1.8V IO

41

OUT

41

BI

41

OUT

41

BI

41

OUT

41

BI

I2C_UPC_SCL
I2C_UPC_SDA

I2C_SPKRAMP_L_SCL
I2C_SPKRAMP_L_SDA

NC_I2C_CODEC_SCL
NC_I2C_CODEC_SDA

W52
V52

AA48

Y48

AB50

Y50

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

I2C2_SCL
I2C2_SDA

I2C

SEP

SGPIO0
SGPIO1

SI2C0_SCL
SI2C0_SDA

SSPI0_MISO
SSPI0_MOSI
SSPI0_SCLK

41

OUT

41

BI

41

OUT

41

BI

I2C_SPKRAMP_R_CODEC_SCL
I2C_SPKRAMP_R_CODEC_SDA

NC_I2C_DFR_SCL
NC_I2C_DFR_SDA

AF6
AE6

AF50
AG49

I2C3_SCL
I2C3_SDA

I2C4_SCL
I2C4_SDA

THROTTLE

IPU FOR ALL

THROTTLE_TRIGGER

THROTTLE_TRIGGER0/MTR_ADC_DOUT

SOCHOT1

THROTTLE_TRIGGER1/MTR_ADC_CLKOUT

THROTTLE_TRIGGER2/PLL_DIGOBS_0
THROTTLE_TRIGGER3/PLL_DIGOBS_1

THROTTLE_TRIGGER4

NC_SPMI2_CLK

81

NC_SPMI2_DATA

81

AK7

AP_SPMI2_SCLK

AL7

AP_SPMI2_SDATA

SPMI

AC3
AC2

Y5
Y4

AC5
AD5
AD6

AK52

AK53
AL53
AJ55
AJ53
AJ49

DBL_CLICK_DET
DISABLE_STROBE

I2C_SEEPROM_SCL
I2C_SEEPROM_SDA

FTCAM_DISABLE_L
NC_SSPI0_MOSI
DMIC_DISABLE_L

SOC_SOCHOT_L

BUCK1_THERMAL_THROTTLE_L
BUCK0_THERMAL_THROTTLE_L
NC_SOC_TRIGGER2
PMU_VDDHI_UVWARN_L
PMU_VDDMAIN_UVWARN_L

PORTABLES SHOULD NC TRIGGER2

81

OUT

OUT

OUT

OUT

OUT

IN
IN
IN
IN
IN

IN

BI

34

72

5

5

72

72

7 34

34 35

34 35

80

35

34 35

78 12 9 6 5

PP1V25_AWAKE_IO

SOC_SOCHOT_L

734

1

R0790

47K

5%
1/20W
MF
201

2

UPC_FORCE_PWR will likely be

removed in the future

TOUCHID_PWR_EN gets
pulled up to S2 on
TOUCHID page
This is OK because
the GPIO is failsafe

PD needed on DFR PAGE

U0600

TMLR68A0-B09

BGA

SYM 2 OF 23

41

IN

75

IN

75

IN

80

OUT

5074

IN

5075

IN

53

OUT

20

IN

81

IN

5

IN

5

IN

5

IN

5

IN

81

IN

53

BI

80

BI

80

IN

81

OUT

50

IN

80

OUT

2059

OUT

80

OUT

80

OUT

80

IN

UPC_I2C_INT_L
NC_SOC_GPIO01

81

SPKR_ID0
SPKR_ID1
SPKRAMP_RESET_L
SPKRAMP_INT_L
CODEC_INT_L
SWD_UPC_SWCLK
GPU_CFG_L
NC_SOC_GPIO09

81

NC_SOC_GPIO10
BOARD_REV0
BOARD_REV1
BOARD_REV2
BOARD_REV3
NC_SOC_GPIO15 NC_UART3_D2R
NC_SOC_GPIO16

81

SWD_UPC_SWDIO0
NC_SWD_UPC_SWDIO1
NC_DFR_TOUCH_INT_L
IPD_SPI_EN
TOUCHID_INT
TOUCHID_PWR_EN
UPC_FORCE_PWR
NC_DFR_PWR_EN
NC_SPI_DFR_CS_L
NC_ENET_SYNC_1588

AJ51
AA50

V53
U53
T53
W53
W50
U52

AC48

R53
R52
N55

AH54

Y52

AA51

R54

AC50

U51

AK50

T52

V49
AJ52
AJ50
AC49

R51
AL49
AF49

GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]

IPU
IPU

IPU
IPU

IPU

GPIO

UART

IPD
IPDIPU

IPU
IPU

UART0_RXD
UART0_TXD

UART1_CTSN
UART1_RTSN

UART1_RXD
UART1_TXD

UART2_CTSN
UART2_RTSN

UART2_RXD
UART2_TXD

UART3_CTSN
UART3_RTSN

UART3_RXD
UART3_TXD

UART4_CTSN
UART4_RTSN

UART4_RXD
UART4_TXD

UART6_RXD
UART6_TXD

UART7_RXD
UART7_TXD

5

IN

5

IN

5

IN

5

IN

5

IN

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4

W49

BOARD_ID0/SOC_DEBUG1

R55

BOARD_ID1/SOC_DEBUG2

T55

BOARD_ID2/SOC_DEBUG3

V55

BOARD_ID3/SPI0_SSIN

U55

BOARD_ID4

BOARD ID

NAND

NAND_SYS_CLK0
NAND_SYS_CLK1

SSD_BFH

SSD_RESETN

AB53
AC53

AC54
AA53
AA54
AC55

W55
Y54
Y53
Y55

AC51
AC52
AF48
AB52

AJ48
AK48
AL52
AL50

AF51
AG50

AM2
AJ2

AG52
AH53

AH51
AG53

UART_DEBUGPRT_D2R
UART_DEBUGPRT_R2D

NC_DFR_1V8_TOUCH_RESET_L
NC_DFR_1V8_DISP_RESET_L
NC_DFR_1V8_DISP_INT
BT_TIME_SYNC_1V8

UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L
UART_WLAN_D2R
UART_WLAN_R2D

NC_UART3_D2R_CTS_L
NC_UART3_R2D_RTS_L

NC_UART3_R2D

NC_UART4_D2R_CTS_L
NC_UART4_R2D_RTS_L
NC_UART4_D2R
NC_UART4_R2D

UART_TCON_D2R
NC_UART_TCON_R2D

NC_UART7_RXD
NC_UART7_TXD

NAND0_CLK24M_0_R
NAND0_CLK24M_1_R

NAND_BFH
NAND0_RESET_L

81

81

81

81

81

81

81

81

81

81

IN

OUT

OUT
OUT

IN
IN

IN

OUT

IN

OUT

IN

OUT

OUT
OUT

OUT
OUT

54

54

80

80

80

60 61

60

60

60

60

80

80

65

65

62 63

7 62 63

1.8V IO

1.8V IO

Use UART2 if your wireless module is 1.2V IO

R2D is for desktop only

NAND0_RESET_L

6263

NOSTUFF

1

R0791

47K

5%
1/20W
MF
201

2

BOM_COST_GROUP=SOC

PAGE TITLE

SOC: AP I/Os

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

7 OF 801

SHEET

7 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

A

D

**OK2INTEGRATE**

SOC: LPDP & MIPI

NC_LPDPRX_AUX0

81

NC_LPDPRX_AUX1

81

NC_LPDPRX_AUX2

81

NC_LPDPRX_AUX3

81

NC_LPDPRX_AUX4

81

NC_LPDPRX_AUX5

81

NC_LPDPRX_AUX6

81

NC_LPDPRX_AUX7

81

NC_LPDPRX_AUX8

81

NC_LPDPRX_AUX9

81

NC_LPDPRX_AUX10

81

NC_LPDPRX_AUX11

81

NC_LPDPRX_RXP0

81

NC_LPDPRX_RXN0

81

NC_LPDPRX_RXP1

81

NC_LPDPRX_RXN1

81

NC_LPDPRX_RXP2

81

NC_LPDPRX_RXN2

81

NC_LPDPRX_RXP3

81

NC_LPDPRX_RXN3

81

NC_LPDPRX_RXP4

81

NC_LPDPRX_RXN4

81

NC_LPDPRX_RXP5

81

NC_LPDPRX_RXN5

81

NC_LPDPRX_RXP6

81

NC_LPDPRX_RXN6

81

NC_LPDPRX_RXP7

81

NC_LPDPRX_RXN7

81

NC_LPDPRX_RXP8

81

NC_LPDPRX_RXN8

81

AP7

LPDPRX_AUX_D0_P

AR7

LPDPRX_AUX_D1_P

AT7

LPDPRX_AUX_D2_P

AV7

LPDPRX_AUX_D3_P

AW7

LPDPRX_AUX_D4_P

AY7

LPDPRX_AUX_D5_P

AP8

LPDPRX_AUX_D6_P

AR8

LPDPRX_AUX_D7_P

AT8

LPDPRX_AUX_D8_P

AV8

LPDPRX_AUX_D9_P

AW8

LPDPRX_AUX_D10_P

AY8

LPDPRX_AUX_D11_P

AP1

LPDPRX_RX_D0_P

AP2

LPDPRX_RX_D0_N

AR1

LPDPRX_RX_D1_P

AR2

LPDPRX_RX_D1_N

AT1

LPDPRX_RX_D2_P

AT2

LPDPRX_RX_D2_N

AV1

LPDPRX_RX_D3_P

AV2

LPDPRX_RX_D3_N

AW1

LPDPRX_RX_D4_P

AW2

LPDPRX_RX_D4_N

AY1

LPDPRX_RX_D5_P

AY2

LPDPRX_RX_D5_N

AP4

LPDPRX_RX_D6_P

AP5

LPDPRX_RX_D6_N

AR4

LPDPRX_RX_D7_P

AR5

LPDPRX_RX_D7_N

AT4

LPDPRX_RX_D8_P

AT5

LPDPRX_RX_D8_N

U0600

TMLR68A0-B09

BGA

SYM 4 OF 23

IPD

LPDP_TX0P
LPDP_TX0N

LPDP_TX1P
LPDP_TX1N

LPDP_TX2P
LPDP_TX2N

LPDP_TX3P
LPDP_TX3N

LPDP_TX4P
LPDP_TX4N

LPDP_TX5P
LPDP_TX5N

LPDP_AUX_P
LPDP_AUX_N

LPDP_RCAL_P
LPDP_RCAL_N

DISP_HPD

DISP_POL

DISP_SPI_MISO/DWI_CLK

DISP_SPI_MOSI/DWI_DO
DISP_SPI_SCLK/DISP_I2C_SCL
DISP_SPI_SSIN/DISP_I2C_SDA

DISP_SPMI_SCLK

DISP_SPMI_SDATA

DISP_FSYNC

DISP_LSYNC

GND_VOID=TRUE

AR55
AR54

AT55
AT54

AU54
AU55

AV55
AV54

AW55
AW54

AY55
AY54

AU52
AU51

AV52
AV51

AG55

AH55

AC6
AC7
AD7
AB6

W4
W3

T49

R50

LPDP_INT_DATA_C_P<0>
LPDP_INT_DATA_C_N<0>

GND_VOID=TRUE
GND_VOID=TRUE

LPDP_INT_DATA_C_P<1>
LPDP_INT_DATA_C_N<1>

GND_VOID=TRUE
GND_VOID=TRUE

LPDP_INT_DATA_C_P<2>
LPDP_INT_DATA_C_N<2>

GND_VOID=TRUE
GND_VOID=TRUE

LPDP_INT_DATA_C_P<3>
LPDP_INT_DATA_C_N<3>

GND_VOID=TRUE

NC_LPDP_TX4P
NC_LPDP_TX4N

NC_LPDP_TX5P
NC_LPDP_TX5N

LPDP_INT_AUX_C_P
LPDP_INT_AUX_C_N

SOC_LPDP_INT_RCAL_POS
SOC_LPDP_INT_RCAL_NEG

LPDP_INT_HPD

NC_DISPLAY_POL

NC_SPI_DISP_BKLT_MISO
NC_SPI_DISP_BKLT_MOSI
I2C_DISP_BKLT_SCL
I2C_DISP_BKLT_SDA

NC_DISP_SPMI_CLK
NC_DISP_SPMI_DATA

NC_DISP_FSYNC

NC_DISP_BKLT_LSYNC

81

81

81

81

8

8

81

81

81

81

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

OUT

BI
BI

U0600

TMLR68A0-B09

BGA

SYM 5 OF 23

NC_ISP_I2C0_SCL

42

BI

81

NC_ISP_I2C0_SDA

81

NC_ISP_I2C1_SCL

81

NC_ISP_I2C1_SDA

81

I2C_CAM_SCL

OUT

I2C_CAM_SDA

BI

NC_ISP_I2C3_SCL

81

NC_ISP_I2C3_SDA

81

FTCAM_RESET_L

OUT

NC_ISP_GPIO1

81

NC_ISP_GPIO2

81

NC_ISP_GPIO3

81

NC_ISP_SPMI0_CLK81
NC_ISP_SPMI0_DATA

81

NC_ISP_SPMI1_CLK

81

NC_ISP_SPMI1_DATA

81

NC_SENSOR0_CLK

81

NC_SENSOR1_CLK

81

NC_SENSOR2_CLK

81

NC_SENSOR3_CLK

81

80

80

41

41

67

67

67

67

67

67

67

67

67

67

67

80

42

7280

IN
OUT
OUT

Y2

ISP_I2C0_SCL/ISP_GPIO_8

Y3

ISP_I2C0_SDA/ISP_GPIO_9

AA5

ISP_I2C1_SCL/ISP_GPIO_10

AA6

ISP_I2C1_SDA/ISP_GPIO_11

AA3

ISP_I2C2_SCL

AA2

ISP_I2C2_SDA

AA7

ISP_I2C3_SCL

AB7

ISP_I2C3_SDA

Y6

ISP_GPIO_0

W6

ISP_GPIO_1

Y7

ISP_GPIO_2

W7

ISP_GPIO_3

AG7

ISP_SPMI0_SCLK/ISP_GPIO_5

AF7

ISP_SPMI0_SDATA/ISP_GPIO_4

AG6

ISP_SPMI1_SCLK/ISP_GPIO_7

AH7

ISP_SPMI1_SDATA/ISP_GPIO_6

AD1

SENSOR0_CLK

AE1

SENSOR1_CLK

AD3

SENSOR2_CLK

AF1

SENSOR3_CLK

ISP SPMI

MIPI0C_DPCLK
MIPI0C_DNCLK

MIPI0C_DPDATA0
MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPID_DPCLK
MIPID_DNCLK

MIPID_DPDATA0
MIPID_DNDATA0

MIPI_D

MIPI0C_REXT
MIPI1C_REXT

MIPID_REXT

L15

NC_MIPI0C_CLKP

L14

NC_MIPI0C_CLKN

K15

NC_MIPI0C_DATAP0

K14

NC_MIPI0C_DATAN0

M14

NC_MIPI0C_DATAP1

M15

NC_MIPI0C_DATAN1

GND_VOID=TRUE

L11

MIPI_FTCAM_CLK_P

L12

MIPI_FTCAM_CLK_N

GND_VOID=TRUE

M12

MIPI_FTCAM_DATA_P<0>

M11

MIPI_FTCAM_DATA_N<0>

GND_VOID=TRUE

K11

NC_MIPI_FTCAM_DATA1P

K12

NC_MIPI_FTCAM_DATA1N

GND_VOID=TRUE

GND_VOID=TRUE

K9

NC_MIPI_DFR_CLKP

K8

NC_MIPI_DFR_CLKN

GND_VOID=TRUE
GND_VOID=TRUE

L9

NC_MIPI_DFR_DATAP

L8

NC_MIPI_DFR_DATAN

GND_VOID=TRUE

K17
L17

SOC_MIPI1C_REXT

M9

GND

GND_VOID=TRUE

GND_VOID=TRUE

81

81

81

81

81

81

66

IN

66

IN

66

IN

66

IN

80

IN

80

IN

80

OUT

80

OUT

80

OUT

80

OUT

8

8

NC_LPDPRX_RXP9

81

NC_LPDPRX_RXN9

81

NC_LPDPRX_RXP10

81

NC_LPDPRX_RXN10

81

NC_LPDPRX_RXP11

81

NC_LPDPRX_RXN11

81

NO_TEST=1

NC_LPDPRX0_RCAL_POS
NC_LPDPRX0_RCAL_NEG

NO_TEST=1
NO_TEST=1

NC_LPDPRX1_RCAL_POS
NC_LPDPRX1_RCAL_NEG

NO_TEST=1

AV4

LPDPRX_RX_D9_P

AV5

LPDPRX_RX_D9_N

AW4

LPDPRX_RX_D10_P

AW5

LPDPRX_RX_D10_N

AY4

LPDPRX_RX_D11_P

AY5

LPDPRX_RX_D11_N

AU1

LPDPRX0_RCAL_P

AU2

LPDPRX0_RCAL_N

AU4

LPDPRX1_RCAL_P

AU5

LPDPRX1_RCAL_N

DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1

DISP_TOUCH_EB

DFR_BSYNC/DISP_INT

DFR_DISP_TE

T50
R49
U49

AM5

AL51

NC_DISP_TOUCH_BSYNC0
NC_DISP_TOUCH_BSYNC1
NC_DISP_TOUCH_EB

NC_BKLT_FAULT_INT_L

NC_DFR_DISP_TE

81

81

81

80

IN

80

IN

SOC_MIPI1C_REXT

8

GND

8

PLACE_NEAR=U0600.K17:6MM
PACK_IGNORE=TRUE
PACK_OPTION=DFR

1

R0800

200

1%

2

1/20W
MF
201

MAKE_BASE=TRUE MAKE_BASE=TRUE

PACK_OPTION=NO_FTCAMPACK_OPTION=NO_DFR

PLACE_NEAR=U0600.L17:6MM
PACK_OPTION=FTCAM

1

R0820

200

1%
1/20W
MF
201

2

SOC_LPDP_INT_RCAL_POS

8

SOC_LPDP_INT_RCAL_NEG

8

1

R0895

200

1%
1/20W
MF
201

2

1

C0895

10PF

5%
25V

2

C0G
0201

BOM_COST_GROUP=SOC

SYNC_MASTER=ref_soc_h13g SYNC_DATE=05/04/2020

PAGE TITLE

SOC: LPDP & MIPI

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

8 OF 801

SHEET

8 OF 92

1

A

**OK2INTEGRATE**

SOC: PCIE

78 12 7 6 5

80 9

PP1V25_AWAKE_IO

NAND0_CLKREQ1_L

965

WLBT_CLKREQ_L

96061

NAND0_CLKREQ0_L

965

NC_ENET_CLKREQ_L
USBHC_CLKREQ_L

9

PER PCISIG SPEC, AC COUPLING CAPS SHOULD BE BETWEEN
75 NF AND 265 NF FOR GEN1/2 AND BETWEEN

176 NF AND 265 NF FOR GEN 3/4

R0970 IS NEEDED DUE TO RDAR://53793006

1

R0930

47K

5% 5%
1/20W
MF

2

1

R0940

47K

1/20W
MF
201

2

1

R0950

47K

5%
1/20W
MF
201201

2

1

R0960

47K

5%
1/20W
MF
201

2

PACK_IGNORE=TRUE
PACK_OPTION=ENET

1

R0970

47K

5%
1/20W
MF
201

2

U0600

TMLR68A0-B09

BGA

SYM 6 OF 23

GND_VOID=TRUE

62

IN

62

IN

62

OUT

62

OUT

62

OUT

62

OUT

965

BI

962

OUT

63

63

IN

63

IN

63

OUT

63

OUT

63

OUT

63

OUT

PCIE_NAND0_D2R_P<0>
PCIE_NAND0_D2R_N<0>

PCIE_NAND0_R2D_C_P<0>
PCIE_NAND0_R2D_C_N<0>

PCIE_CLK100M_NAND0_0_P
PCIE_CLK100M_NAND0_0_N

NAND0_CLKREQ0_L

NAND0_PCIE_RESET_L

PCIE_NAND0_D2R_P<1>
PCIE_NAND0_D2R_N<1>

PCIE_NAND0_R2D_C_P<1>
PCIE_NAND0_R2D_C_N<1>

PCIE_CLK100M_NAND0_1_P
PCIE_CLK100M_NAND0_1_N

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

BE26
BF26

BC27
BD27

BB37
BC37

AH50

AH52

BE28
BF28

BC29
BD29

BB38
BC38

ST_PCIE_RX0_P
ST_PCIE_RX0_N

ST_PCIE_TX0_P
ST_PCIE_TX0_N

ST_PCIE_REF_CLK0_P
ST_PCIE_REF_CLK0_N

ST_PCIE_CLKREQ0_N

ST_PCIE_PERST0_N

ST_PCIE_RX1_P
ST_PCIE_RX1_N

ST_PCIE_TX1_P
ST_PCIE_TX1_N

ST_PCIE_REF_CLK1_P
ST_PCIE_REF_CLK1_N

GP_PCIE_RX0_P
GP_PCIE_RX0_N

GP_PCIE_TX0_P
GP_PCIE_TX0_N

GP_PCIE_REF_CLK0_P
GP_PCIE_REF_CLK0_N

GP_PCIE_CLKREQ0_N

GP_PCIE_PERST0_N

GP_PCIE_RX1_P
GP_PCIE_RX1_N

GP_PCIE_TX1_P
GP_PCIE_TX1_N

GP_PCIE_REF_CLK1_P
GP_PCIE_REF_CLK1_N

GND_VOID=TRUE

BE30
BF30

BC31
BD31

BE40
BF40

AB55

AA52

BE32
BF32

BC33
BD33

BE38
BF38

PCIE_WLBT_D2R_P
PCIE_WLBT_D2R_N

GND_VOID=TRUE
GND_VOID=TRUE

PCIE_WLBT_R2D_C_P
PCIE_WLBT_R2D_C_N

GND_VOID=TRUE

PCIE_CLK100M_WLBT_P
PCIE_CLK100M_WLBT_N

WLBT_CLKREQ_L

WLBT_RESET_L

GND_VOID=TRUE

NC_PCIE_USBHC_D2RP
NC_PCIE_USBHC_D2RN

GND_VOID=TRUE
GND_VOID=TRUE

NC_PCIE_USBHC_R2DCP
NC_PCIE_USBHC_R2DCN

GND_VOID=TRUE

NC_PCIE_CLK100M_USBHCP
NC_PCIE_CLK100M_USBHCN

IN
IN

OUT
OUT

OUT
OUT

BI

OUT

IN
IN

OUT
OUT

OUT
OUT

60

60

60

60

60

60

9 60 61

9 60 61

80

80

80

80

80

80

TO BE CHECKED WITH SEG- DO NOT MATCH WITH SILVAL

IS THE PULL-UP VOLTAGE CORRECT?

965

BI

NAND0_CLKREQ1_L

NC_NAND0_PCIE_RESET1_L

81

AH49

AH48

ST_PCIE_CLKREQ1_N

ST_PCIE_PERST1_N

GP_PCIE_CLKREQ1_N

GP_PCIE_PERST1_N

GP_PCIE_RX2_P
GP_PCIE_RX2_N

GP_PCIE_TX2_P
GP_PCIE_TX2_N

GP_PCIE_REF_CLK2_P
GP_PCIE_REF_CLK2_N

GP_PCIE_CLKREQ2_N

GP_PCIE_PERST2_N

AA55

P55

BE34
BF34

BC35
BD35

BE39
BF39

AH1

AE7

USBHC_CLKREQ_L

NC_USBHC_RESET_L

GND_VOID=TRUE

NC_PCIE_ENET_D2RP
NC_PCIE_ENET_D2RN

GND_VOID=TRUE
GND_VOID=TRUE

NC_PCIE_ENET_R2DCP
NC_PCIE_ENET_R2DCN

GND_VOID=TRUE

NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_ENETN

NC_ENET_CLKREQ_L

NC_ENET_RESET_L

BI

OUT

IN
IN

OUT
OUT

OUT
OUT

BI

OUT

9

9 80

80

80

80

80

80

80

9 80

9 80

SOC_ST_PCIE_RCAL_POS

9

SOC_ST_PCIE_RCAL_NEG

9

SOC_GP_PCIE_RCAL_POS

9

SOC_GP_PCIE_RCAL_NEG

9

1

R0990

200

1%
1/20W
MF
201

2

1

C0990

10PF

5%
25V

2

C0G
0201

1

R0991

200

1%
1/20W
MF
201

2

1

C0991

10PF

5%
25V

2

C0G
0201

NC_USBHC_RESET_L

80 9

NC_ENET_RESET_L

80 9

NAND0_PCIE_RESET_L

96263

WLBT_RESET_L

96061

SOC_ST_PCIE_RCAL_POS

9 9

SOC_ST_PCIE_RCAL_NEG

9

NC_PAD_MTR_ANALOG_TEST_POS

81

NC_PAD_MTR_ANALOG_TEST_NEG

81

NC_PAD_MTR_VREF_POS

81

NC_PAD_MTR_VREF_NEG

81

1

R0941

47K

5%
1/20W
MF
201

2

1

R0951

47K

5%
1/20W
MF
201

2

1

R0961

47K

5%
1/20W
MF
201

2

PACK_IGNORE=TRUE
PACK_OPTION=ENET

BC24
BB24

AM3
AL3

AL1
AM1

ST_PCIE_RCAL_P
ST_PCIE_RCAL_N

PAD_MTR_ANALOG_TEST_P
PAD_MTR_ANALOG_TEST_N

PAD_MTR_VREF_P
PAD_MTR_VREF_N

1

R0971

47K

5%
1/20W
MF
201

2

PACK_IGNORE=TRUE
PACK_OPTION=USBHC

GP_PCIE_RCAL_P
GP_PCIE_RCAL_N

BC25
BB25

SOC_GP_PCIE_RCAL_POS
SOC_GP_PCIE_RCAL_NEG

9

SYNC_MASTER=ref_soc_h13g SYNC_DATE=05/04/2020

PAGE TITLE

SOC: PCIE

SIZE

D

BOM_COST_GROUP=SOC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

9 OF 801

SHEET

9 OF 92

2

1

568

**OK2INTEGRATE**

72

IN

output if gyro, input for radar

LID_OPEN

MAKE_BASE=TRUE

I2C0 is ALS for portables

PACK_OPTION=HAS_LID

AOP, NUB, and SMC GPIO's are referenced to PP1V25_S2_AOP

NC_AOP_FUNC0

80

NC_AOP_FUNC1

81

NC_AOP_FUNC2

80

NC_AOP_FUNC3

80

NC_SPI_R1_CS_L

80

NC_AOP_FUNC5

81

49

OUT

49

IN

49

IN

SPI_GYRO_CS_L
GYRO_INT
GYRO_MOTION_INT
LID_OPEN
NC_AOP_FUNC10

81

6061

OUT

6061

OUT

80

IN

42

OUT

42

BI

42

OUT

42

BI

72

72

WLAN_CONTEXT_A
WLAN_CONTEXT_B
NC_ALS_INT_L
NC_AOP_FUNC14

81

I2C_AOP_ALS_SCL
I2C_AOP_ALS_SDA

NC_I2C_AOP_ENET_SCL
NC_I2C_AOP_ENET_SDA

NC_PDM_CLK1

81

NC_PDM_CLK2

81

PDM_DMIC_CLK3

OUT

PDM_DMIC_CLK4

OUT

NC_PDM_CLK5

81

NC_PDM_CLK6

81

BB18
BC16
BC12
BC13
BA16
BA13
BA15
BD13
BD16
BA14
BB12
BD20
BA11
BD18
BA10

BC20
BB19

BB16
BE15

BB9
BC9
BC6
BD9
BC8
BD8

AOP_FUNC[0]
AOP_FUNC[1]
AOP_FUNC[2]
AOP_FUNC[3]
AOP_FUNC[4]
AOP_FUNC[5]
AOP_FUNC[6]
AOP_FUNC[7]
AOP_FUNC[8]
AOP_FUNC[9]

IPD

AOP_FUNC[10]
AOP_FUNC[11]
AOP_FUNC[12]
AOP_FUNC[13]
AOP_FUNC[14]

AOP_I2CM0_SCL
AOP_I2CM0_SDA

AOP_I2CM1_SCL
AOP_I2CM1_SDA

AOP_PDM_IN_CLK1/AOP_I2S1_BCLK
AOP_PDM_IN_CLK2/AOP_I2S0_MCK
AOP_PDM_IN_CLK3/AOP_I2S0_LRCK
AOP_PDM_IN_CLK4/AOP_I2S0_DOUT
AOP_PDM_IN_CLK5/AOP_I2S0_DIN
AOP_PDM_IN_CLK6/AOP_I2S0_BCLK

SOC: AOP

U0600

TMLR68A0-B09

BGA

SYM 7 OF 23

AOP GPIO

NUB GPIO

AOP I2C

NUB SPMI

NUB SWD

AOP PDM

NUB_CLK_OUT0

NUB_DOCK_ATTENTION/CTM_TRIGGER

NUB_DOCK_CONNECT

NUB_GPIO_0/AOP_FUNC15/NUB_CLK_OUT1

NUB_GPIO_1/AOP_PDM_IN_CLK0
NUB_GPIO_2/AOP_PDM_IN_DATA0
NUB_GPIO_3/AOP_LEAP_MADI_IN

IPU

NUB_GPIO_4/AOP_LEAP_MADI_OUT

NUB_GPIO_5/AOP_PDM_OUT_CLK0

NUB_GPIO_6/AOP_PDM_OUT_DATA0/AOP_FUNC16

NUB_GPIO_7/AOP_FUNC17
NUB_GPIO_8/AOP_FUNC18
NUB_GPIO_9/AOP_FUNC19

NUB_GPIO_10/AOP_FUNC20
NUB_GPIO_11/KIS_GPIO0/AOP_FUNC21
NUB_GPIO_12/KIS_GPIO1/AOP_FUNC22

NUB_SPMI0_SCLK

NUB_SPMI0_SDATA

NUB_SPMI1_SCLK

NUB_SPMI1_SDATA

NUB_SWD_TCK_OUT0

NUB_SWD_TMS0
NUB_SWD_TMS1

BA17
BC15
BC17

BD14
BD15
BD21
BD17
BB13
BD19
BD22
BB10
BD12
BD11
BC10
BB7
BD10

BB15
BC14

BA12
BC11

BC18
BC19
BC21

NC_DFR_TOUCH_CLK32K_RESET_L
TPT_SOC_DOCK_ATTENTION
SOC_DOCK_CONNECT

NC_BKLT_PWR_ON
CODEC_RESET_L
SOC_SW_DBG
IPD_SPI_INT_L
SMC_FIXTURE_MODE_L
CHGR_INT_L
NC_CCG_SMC_I2C_INT_L
NC_ACDC_ID
NC_ACDC_BURST_EN_L
NC_SPI_DP2HDMI_HOLD_L
NC_HDMI_CEC_AOP_TX
NC_HDMI_CEC_AOP_RX
NC_HDMI_HPD_AOP

SPMI_NUB_MPMU_CLK_R
SPMI_NUB_MPMU_DATA_R

SPMI_NUB_SPMU_CLK_R
SPMI_NUB_SPMU_DATA_R

SWD_NUB_SWCLK
SWD_NUB_PMU_SWDIO
NC_NUB_SWD_TMS1

80

OUT

20

10 80

IN

80

OUT

50

OUT

82

OUT

80

IN

20

IN

80

IN

80

IN

80

IN

80

OUT

80

OUT

80

OUT

80

IN

80

IN

20

OUT

20

BI

20

OUT

20

BI

30 34

OUT

30 34

BI

80

DOC_ATTENTION should be a TP
for non dev programs,

SOC_SW_DBG SHOULD GO TO
A LED IF POSSIBLE.
NEEDS A TEST POINT AT MINIMUM

FIXTURE_MODE_L should be aliased to a TP
for non dev programs,
The TP is required

1080

SOC_DOCK_CONNECT

R1066

47K

5%

1/20W

MF

201

1

2

78 12 10

6347282

IN

PP1V25_S2

PMU_RESET_L

R1083

10K

5%

1/20W

MF

201

NC_PDM_DATA1

81

NC_PDM_DATA2

81

IPD

72

IPD

72

20

IN

20

OUT

20

OUT

PDM_DMIC_DATA3

IN

PDM_DMIC_DATA4

IN

SPI_AOP_GYRO_MISO
SPI_AOP_GYRO_MOSI_R
SPI_AOP_GYRO_CLK_R

CKPLUS_WAIVE=CLK_DATA_CON
CKPLUS_WAIVE=CLK_DATA_CON

BE21
BE16
BE19

BD5

BF15
BF14
BF17

AOP_PDM_IN_DATA1/AOP_I2S1_MCK
AOP_PDM_IN_DATA2/AOP_I2S1_LRCK
AOP_PDM_IN_DATA3/AOP_I2S1_DOUT/AOP_PDM_IN_CLK7
AOP_PDM_IN_DATA4/AOP_I2S1_DIN/AOP_PDM_IN_CLK8

AOP_SPI0_MISO
AOP_SPI0_MOSI
AOP_SPI0_SCLK

AOP SPI

JTAG

IPU
IPU

IPU
IPD

JTAG_SEL
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRSTN

SMC_I2CM0_SCL

NC_AOP_SPMI0_SCLK

81

NC_AOP_SPMI0_SDATA

81

20

OUT

20

BI

SPMI_SE_CLK_R
SPMI_SE_DATA_R

BF18
BF19

BF20
BF21

AOP_SPMI0_SCLK/AOP_UART0_TXD
AOP_SPMI0_SDATA/AOP_UART0_RXD

AOP_SPMI1_SCLK/AOP_UART1_TXD
AOP_SPMI1_SDATA/AOP_UART1_RXD

AOP SPMI

SMC_I2CM0_SDA

SMC_I2CM1_SCL/SMC_UART1_TXD
SMC_I2CM1_SDA/SMC_UART1_RXD

SMC_I2CM2_SCL

NC_AOP_UART2_D2R

81

NC_AOP_UART2_R2D

81

BB3

AOP_UART2_RXD

BB4

AOP_UART2_TXD

AOP UART

SMC I2C

SMC_I2CM2_SDA

SMC_I2CM3_SCL
SMC_I2CM3_SDA

1

2

34

PMU_CLK32K_SOC

IN

BE6

BF10

BB5

RT_CLK32768

CFSB_AON

COLD_RESETN

AOP RESET

SMC UART

IPU

SMC_I2CM4_SCL
SMC_I2CM4_SDA

SMC_UART0_RXD
SMC_UART0_TXD

BE4
BF5
BF16
BC1
BB1
BF7

BC3
BC2

BD4
BB2

BD6
BC5

BC7
BD7

BE7
BF9

BF4
BF8

SOC_JTAG_SEL
SWD_SOC_SWCLK
TPT_JTAG_SOC_TDI
TPT_JTAG_SOC_TDO
SWD_SOC_SWDIO
TPT_JTAG_SOC_TRST_L

I2C_SMC_PWR_SCL
I2C_SMC_PWR_SDA

I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA

NC_I2C_SMC_SNS1_SCL
NC_I2C_SMC_SNS1_SDA

I2C_SMC_IPD_SCL
I2C_SMC_IPD_SDA

NC_I2C_SMC_SNS0_SCL
NC_I2C_SMC_SNS0_SDA

UART_SMC_DEBUGPRT_D2R
UART_SMC_DEBUGPRT_R2D

5

IN

54

IN

20

20

54

BI

20

43

OUT

43

BI

43

OUT

43

BI

43

OUT

43

BI

43

OUT

43

BI

43

OUT

43

BI

54

IN

54

OUT

78 12 10

PP1V25_S2

81

34

OUT

XW1022

SHORT-14L-0.1MM-SM

21

58

BI

58

BI

NC_AON_SLEEP1_RESET_L

SOC_WDOG

SOC_DBG_PROBE_VALID

EUSB_DBG_P
EUSB_DBG_N

SOC_USBDBG_RESREF

1

R1042

200

1%
1/20W
MF
201

2

BB21

BF12

BF6

BF24
BE24

BE23

AON_SLEEP1_RESETN

WDOG

DBG_PROBE_VALID

DBG_USB_EDP
DBG_USB_EDM

DBG_USB_RESREF

AOP DEBUG

SMC GPIO

IPU

SMC_GPIO0
SMC_GPIO1

SMC_FPWM0
SMC_FPWM1

BF11
BF13

BE12
BE9

UPC_SMC_I2C_INT_L
NC_SMC_GPIO1

NC_SMC_FAN_PWM_SMC_SIL_LED_PWM
NC_SMC_FAN_TACH

43

IN

81

80

OUT

80

IN

BOM_COST_GROUP=SOC

SYNC_MASTER=ref_soc_h13g SYNC_DATE=05/04/2020

PAGE TITLE

SOC: AOP

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

10 OF 801

SHEET

10 OF 92

1

2

1

**OK2INTEGRATE**

78 18 11

PP1V8_S2SW_VDD1

18

PP1V2_AWAKE_PLL

78

78 18 11

PP0V6_S1_VDDQL

DDR0_ZQ

11

DDR1_ZQ

11

DDR4_ZQ

11

DDR5_ZQ

11

CRITICAL

1

C1100

1.0UF

20%
4V

2

X6S
0201 0201 0201

1

2

1

C1113

0.22UF

20%

6.3V

2

X6S-CERM

PP1V06_S2SW_DRAM

1

R1161

240

1%
1/20W
MF
201

2

PLACE_NEAR=U0600.A5:5MM
PLACE_NEAR=U0600.A7:5MM
PLACE_NEAR=U0600.A33:5MM
PLACE_NEAR=U0600.A35:5MM

CRITICAL

C1101

1.0UF

20%
4V
X6S

1

2

1

C1112

0.1UF

10%

6.3V

2

X6S
0201

1

C1111

2.2UF

20%
4V

2

X6S-CERM
0201

1

R1162

240

1%
1/20W
MF
201

2

CRITICAL

C1102

1.0UF

20%
4V
X6S

C1105

11UF

1

1

R1163

240

1%
1/20W
MF
201

2

1

C1103

12PF

5%
25V

2

NP0-C0G

C1106

20%

2.5V
X6T

0402 0402

3

4

2

1

C1110

0.1UF

10%

6.3V

2

X6S
02010201

1

C1115

1.0UF

20%
4V

2

X6S
0201

DDR0_RREF

11

DDR1_RREF

11

DDR2_RREF

11

DDR3_RREF

11

DDR4_RREF

11

DDR5_RREF

11

DDR6_RREF

11

DDR7_RREF

11

DDR0_ZQ

11

DDR1_ZQ

11

DDR4_ZQ

11

DDR5_ZQ

11

DDR0_ZQ1

11

DDR1_ZQ1

11

DDR4_ZQ1

11

DDR5_ZQ1

11

11UF

20%

2.5V
X6T

1

2

1

R1164

240

1%
1/20W
MF
201

2

3

4

1

2

C1107

1

1

C1114

0.01UF

10%
25V

2

X7R
0201

C1104

3PF

+/-0.1PF
25V
C0G
0201

11UF

20%

2.5V
X6T

0402

3

4

2

1

R1165

240

1%
1/20W
MF
201

2

D21
D22
D48
D49

D7

D8
E21
E35
E48

E8
D34
D35

AJ19
AG19
AE13

T25

AA29

Y31
T33

AC43

AJ14
AH14
AC14

R25
T29
T30
T36

AA42

J1

H1

G1
A26
A31
A32
G55
H55

A5

A7
A33
A35

A6

A8
A34
A36

1

R1166

240

1%
1/20W
MF
201

2

SOC: POWER (DDR,SRAM)

U0600

TMLR68A0-B09

BGA

SYM 9 OF 23

VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2

VDDIO12_PLL_DDR0
VDDIO12_PLL_DDR1
VDDIO12_PLL_DDR2
VDDIO12_PLL_DDR3
VDDIO12_PLL_DDR4
VDDIO12_PLL_DDR5
VDDIO12_PLL_DDR6
VDDIO12_PLL_DDR7

VDDIO11_RET_DDR0_S2
VDDIO11_RET_DDR1_S2
VDDIO11_RET_DDR2_S2
VDDIO11_RET_DDR3_S2
VDDIO11_RET_DDR4_S2
VDDIO11_RET_DDR5_S2
VDDIO11_RET_DDR6_S2
VDDIO11_RET_DDR7_S2

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF
DDR4_RREF
DDR5_RREF
DDR6_RREF
DDR7_RREF

DDR0_ZQ[0]
DDR1_ZQ[0]
DDR4_ZQ[0]
DDR5_ZQ[0]

DDR0_ZQ[1]
DDR1_ZQ[1]
DDR4_ZQ[1]
DDR5_ZQ[1] VDD2_S2

1

R1167

240

1%
1/20W
MF
201

2

1

R1168

240

1%
1/20W
MF
201

2

VDD2_S2
VDD2_S2

VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2

B30
B31

B52
F23
F25
F50
F52
G24
G26
G51
G53
H23
H25
H50
H52
J24
J26
J51
J53
P5
P24
P32
P51
B4
B3
B25
B26
B53
F4
F6
F31
F33
G3
G5
G30
G32
H4
H6
H31
H33
J3
J5
J30
J32
P6
P23
P33
P50

PP1V06_S2SW_DRAM

3

3

C1121

4.3UF

20%

2.5V
X6T

0402

1

2

C1126

4.3UF

20%

2.5V
X6T

0402

1

2

C1120

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1125

4.3UF

20%

2.5V
X6T

0402

1

4

2

TABLE_ALT _HEAD

PART NUMBER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT _ITEM

138S00138 ALL 4.7UF 20% 4V 0201138S00139

TABLE_ALT _ITEM

138S00138138S00164 ALL 4.7UF 20% 4V 0201

PP0V6_S1_VDDQL78 18 11

1

U0600

TMLR68A0-B09

781811

AA14
AA16
AA40
AB15
AB41
AC16
AC40
AD15
AE16
AF15
AG14
AH15
AK15
AL14
AL16
AM15
AM17

3

3

C1123

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1128

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1122

4.3UF

20%

2.5V
X6T

0402

3

4

4

2

C1127

4.3UF

20%

2.5V
X6T

0402

1

3

4

4

2

3

3

C1124

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1129

4.3UF

20%

2.5V
X6T

0402

1

4

2

3

3

B21
B23
B33
B35
B50

B6

B8
C22
C24

C3
C32
C34
C49

C5
C51
C53

C7
D23
D25
D31
D33

D4
D50
D52

D6
E24
E26

E3
E30
E32
E51
E53
K24
K26

K3
K30
K32

K5
K51

VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1

BGA

SYM 8 OF 23

VDDQL S1

VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1

K53
L23
L25
L31
L33
L4
L50
L52
L6
M24
M26
M3
M30
M32
M5
M51
M53
N25
N31
N4
N52
T16
T18
T20
T22
T26
T28
T32
T38
T40
U14
U15
U17
U19
U21
U23
U25
U27
U29
U31
U33
U35
U37
U39
V16
V22
V24
V26
V32
V34
V40
W14
W40
Y15

C1150

12PF

25V

2

NP0-C0G
0201

C1133

4.3UF

20%

2.5V
X6T

0402

1

2

C1140

4.3UF

20%

2.5V
X6T

0402

1

2

3

4

3

4

1

2

C1134

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1141

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1151

3PF

+/-0.1PF
25V0201
C0G
0201

C1131

4.3UF

2.5V
0402

1

2

C1135

4.3UF

2.5V
0402

1

3

2

C1142

4.3UF

2.5V
0402

1

3

2

20%
X6T

20%
X6T

20%
X6T

C1132

4.3UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

C1136

4.3UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

B

3

4

78 18 11

DDR0_ZQ1

11

DDR1_ZQ1

11

DDR4_ZQ1

11

DDR5_ZQ1

11

PP0V6_S1_VDDQL

DDR0_RREF

11

DDR1_RREF

11

DDR2_RREF

11

DDR3_RREF

11

DDR4_RREF

11

DDR5_RREF

11

DDR6_RREF

11

DDR7_RREF

11

PLACE_NEAR=U0600.A6:5MM
PLACE_NEAR=U0600.A8:5MM
PLACE_NEAR=U0600.A34:5MM
PLACE_NEAR=U0600.A36:5MM

1

R1169

240

1%
1/20W
MF
201

2

PLACE_NEAR=U0600.J1:5MM
PLACE_NEAR=U0600.H1:5MM
PLACE_NEAR=U0600.G1:5MM
PLACE_NEAR=U0600.A26:5MM
PLACE_NEAR=U0600.A31:5MM
PLACE_NEAR=U0600.A32:5MM
PLACE_NEAR=U0600.G55:5MM
PLACE_NEAR=U0600.H55:5MM

1

R1170

240

1%
1/20W
MF
201

2

1

R1171

240

1%
1/20W
MF
201

2

1

R1172

240

1%
1/20W
MF
201

2

1

R1173

240

1%
1/20W
MF
201

2

1

R1174

240

1%
1/20W
MF
201

2

1

R1175

240

1%
1/20W
MF
201

2

1

R1176

240

1%
1/20W
MF
201

2

BOM_COST_GROUP=SOC

PAGE TITLE

SOC: POWER (DDR,SRAM)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

11 OF 801

SHEET

11 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

D

2

1

8

**OK2INTEGRATE**

Internally generated rail

PP0V6_S2_GRP1

4UF

20%

2.5V
X6S

0201

1

2

C1200

VOLTAGE=0.6V

PP0V6_S2_GRP2

C1201

4UF

20%

2.5V
X6S

0201

SOC: POWER (IO)

VOLTAGE=0.6V

1

2

78 10

PP1V25_S2

PP1V25_S2

78

desense recomends an additional 3 pF cap on PP1v25_awake_grp3
J313 can't fit it so it should go on a project specific page

78 9 7 6 5

PP1V25_AWAKE_IO

20%

6.3V
0402

1

2

C1233

10UF

CER-X6S

XW1232

SM

21

C1232

2.2UF

20%

4V

X6S-CERM

0201

1

C1213

2.2UF

20%
4V

2

X6S-CERM
0201 0201

XW1231

SM

C1231

2.2UF

20%

4V

X6S-CERM

0201

21

1

2

VOLTAGE=1.25V

PP1V25_AWAKE_GRP4

C1236

NP0-C0G

PP1V25_AWAKE_GRP5

1

2

1

C1210

2.2UF

20%
4V

2

X6S-CERM

12PF

5%

25V

0201

1

2

1

C1211

0.1UF

10%

6.3V

2

X6S
0201

C1234

2.2UF

X6S-CERM

0201

XW1230

SM

C1237

3PF

+/-0.1PF

25V
C0G

0201

VOLTAGE=1.25V

20%

4V

1

C1241

12PF

2

VOLTAGE=1.25V

21

PP1V25_AWAKE_GRP3

C1230

2.2UF

1

2

X6S-CERM

NP0-C0G

20%

4V

0201

25V

0201

1

2

C1238

12PF

25V

NP0-C0G

0201

5%

1

C1242

2

C1235

NP0-C0G

1

2

3PF

+/-0.1PF

25V
C0G

0201

12PF

5%

25V

0201

C1239

3PF

+/-0.1PF

0201

1

2

25V
C0G

U0600

TMLR68A0-B09

BGA

SYM 14 OF 23

AR40
AP40

BB22

AY23

1

2

1

2

AY25
AY27
BA24
BA26

AP39

AF41
AG42
AH40
AL40
AN40

AT40
AV40

AP16
AR17
AT16
AU17
AV16
AW17

VDD06_GRP1_S2
VDD06_GRP2_S2 VDD2_S2_SENSE2

VDDDIO_HIB_S4

VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_S2

VDDIO12_GRP1_S2

VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3

VDDIO12_GRP4
VDDIO12_GRP4

VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5

VDD2_S2_SENSE1

VDD_PCPU_SENSE
VDD_ECPU_SENSE

VDD_GPU_SENSE

VDD_SOC_S1_SENSE

VDD_DISP_S1_SENSE

VDD_DCS_SENSE

VDDQL_SENSE

VSS_PCPU_SENSE

VSS_DDR_SENSE

VSS_SENSE1

VSS_SENSE2

B10
B37

AD36
AN23
AC23
AH22
Y17
AN17
AN15

AD37
AN16
B9
B36

VSNS_VDD2_1
VSNS_VDD2_2

VSNS_VDD_PCPU
VSNS_VDD_ECPU
VSNS_VDD_GPU
VSNS_VDD_SOC
VSNS_VDD_DISP
VSNS_VDD_DCS
VSNS_VDDQL

VSNS_VSS_PCPU
VSNS_VSS_DDR
VSNS_VSS_1
VSNS_VSS_2

47

47

47

47

47

47

47

47

47

47

47

47

47

PP1V8_AWAKE

78

C1243

12PF

5%

25V

NP0-C0G

0201

1

2

C1244

3PF

+/-0.1PF

25V
C0G

0201

AP41
AR41

1

C1240

2.2UF

2

X6S-CERM

20%

4V

0201

1

2

VDDIO18_GRP1
VDDIO18_GRP1

BOM_COST_GROUP=SOC

PAGE TITLE

SOC: POWER (IO)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

12 OF 801

SHEET

12 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

D

**OK2INTEGRATE**

3458

SOC: POWER (CPU, GPU)

78 18 13

C1310

11UF

20%

2.5V
X6T

0402

1

4

2

C1318

11UF

20%

2.5V
X6T

0402

1

3

3

C1311

11UF

20%

2.5V
X6T

0402

1

4

2

C1312

11UF

1

3

2

C1319

11UF

20%

2.5V
X6T

0402

1

PPVDD_PCPU_AWAKE

C1300

+/-0.1PF

C1313

11UF

20%

2.5V
X6T

0402

3

3

4

20%

2.5V
X6T

0402

1

4

2

3PF

25V
C0G

0201

3

1

2

C1301

C1314

11UF

20%

2.5V
X6T

0402

1

4

2

12PF

NP0-C0G

3

1

5%

25V

2

0201

C1315

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1316

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1317

11UF

20%

2.5V
X6T

0402

1

4

2

0.575V @ 4400MA

U0600

TMLR68A0-B09

BGA

SYM 11 OF 23

AE33
AE35
AE36
AE37
AF33
AF36
AF39
AG34
AG38
AH34
AH39
AJ33
AJ34
AK29
AK33
AK35
AK36
AK38
AK40
AK41
AK42
AK43
AK44
AK45
AK46
AL30
AL32
AL37
AL41
AL42
AL43
AL44
AL45
AL46
AM29
AM34
AM38
AM41
AM42
AM43
AM44
AM45
AM46
AM47
AM48
AM49
AM50
AM51
AM52
AM53
AM54
AM55
AN33
AN34
AN38
AN42
AN43
AN44
AN45
AN46
AN47
AN48
AN49
AN50
AN51

3

AN52
AN53
AN54
AN55
AP29
AP33
AP38
AP43
AP44

VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU

VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU

VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU

VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1

AP45
AP46
AP47
AP48
AP49
AP50
AP51
AP52
AR30
AR32
AR33
AR35
AR36
AR37
AR39

AK25
AL26
AL28
AL29
AN24
AN29
AP25
AR26
AR28

AB23
AC33
AC38
AE23
AE32
AE38
AF28
AG23
AG39
AJ20
AJ22
AJ24
AJ26
AJ28
AJ30
AJ32
AL20
AL22
AL24
AM39
AN18
AN20
AN22
AR18
AR22
AR24
AT33
AT35
AT37
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU38
Y21
Y26
Y36

PPVDD_PCPU_AWAKE

PPVDD_ECPU_AWAKE

C1320

11UF

20%

2.5V
X6T

0402

1

4

2

PPVDD_SOC_S1

C1330

11UF

20%

2.5V
X6T

0402

1

2

C1334

11UF

20%

2.5V
X6T

0402

1

4

2

4

3

C1331

1

3

C1335

11UF

20%

2.5V
X6T

0402

1

2

3

11UF

20%

2.5V
X6T

0402

2

3

4

C1321

11UF

20%

2.5V
X6T

0402

1

2

3

4

C1336

11UF

20%

2.5V
X6T

0402

1

2

C1322

1

3

4

C1332

11UF

20%

2.5V
X6T

0402

1

4

2

3

4

11UF

2

3

C1337

1

781813

20%

2.5V
X6T

0402

4

C1333

11UF

1

11UF

20%

2.5V
X6T

0402

4

2

78 18 13

3

20%

2.5V
X6T

0402

2

3

PPVDD_GPU_AWAKE

C1323

11UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

78

1

2

C1324

11UF

20%

2.5V
X6T

0402

1

4

2

C1340

12PF

5%
25V
NP0-C0G
0201

3

C1350

11UF

20%

2.5V
X6T

0402

1

4

2

1

C1341

3PF

+/-0.1PF
25V

2

C0G
0201

C1325

11UF

20%

2.5V
X6T

0402

1

4

2

C1351

11UF

1

3

2

3

20%

2.5V
X6T

0402

AA24
AA26
AA28
AA31
AA33
AA35
AA37
AB25
AB27
AB28
AB30
AB32
AB34
AB36
AC24

7818

AC26
AC31
AC35
AC37
AD25
AD27
AD32
AD34
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD50
AD51
AD52
AD53
AD54
AD55
AE24

VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU

C1352

11UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

U0600

TMLR68A0-B09

BGA

SYM 12 OF 23

VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU

VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1

AE26
AE27
AE29
AE30
AE31
AE42
AE43
AE44
AE45
AE46
AE47
AE48
AE49
AE50
AE51
AE52
AE53
AE54
AE55
AF24
AF32
AG25
AG27
AG31
AG33

AA19
AA21
AA23
AB22
AC19
AD22
AE19
AE21
AG21

PPVDD_GPU_AWAKE

C1353

11UF

20%

2.5V
X6T

0402

1

4

2

1

C1370

12PF

5%
25V

2

NP0-C0G
0201

C1354

11UF

20%

2.5V
X6T

0402

1

3

3

4

2

PPVDD_DISP_S1

C1361

11UF

20%

2.5V
X6T

0402

1

3

4

2

C1365

11UF

20%

2.5V
X6T

0402

1

4

2

C1355

11UF

20%

2.5V
X6T

0402

1

4

2

C1362

11UF

20%

2.5V
X6T

0402

1

4

2

3

1

3

1

3

C1366

1

C1356

11UF

20%

2.5V
X6T

0402

4

2

C1363

11UF

20%

2.5V
X6T

0402

4

2

11UF

20%

2.5V
X6T

0402

3

4

2

3

3

C1357

11UF

20%

2.5V
X6T

0402

1

4

2

C1364

11UF

20%

2.5V
X6T

0402

1

4

2

781813

3

7818

3

4

4

2

2

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

PAGE TITLE

SOC: POWER (SOC, CPU, GPU)

SIZE

D

BOM_COST_GROUP=SOC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

13 OF 801

SHEET

13 OF 92

1

**OK2INTEGRATE**

78 18

PPVDD_CPU_SRAM_AWAKE

C1400

11UF

20%

2.5V
X6T

0402

1

4

2

SOC: POWER (SRAM, SOC)

U0600

TMLR68A0-B09

BGA

SYM 10 OF 23

AE34

1

C1406

12PF

5%
25V

2

NP0-C0G
0201

3

C1402

11UF

20%

2.5V
X6T

0402

1

4

2

C1401

11UF

20%

2.5V
X6T

0402

3

1

4

2

PPVDD_DCS_S1

78 18

C1410

11UF

20%

2.5V
X6T

0402

1

3

4

2

3

C1411

1

C1403

11UF

20%

2.5V
X6T

0402

1

4

2

11UF

20%

2.5V
X6T

0402

3

4

2

3

C1404

11UF

20%

2.5V
X6T

0402

1

4

2

C1412

11UF

20%

2.5V
X6T

0402

1

4

2

3

3

C1405

11UF

20%

2.5V
X6T

0402

1

4

2

C1413

11UF

20%

2.5V
X6T

0402

1

4

2

3

3

1

C1407

3PF

+/-0.1PF
25V

2

C0G
0201

AE39
AG36
AH35
AH37
AJ36
AJ38
AK27
AK31
AK37
AL33
AL35
AL38
AM25
AM26
AM31
AM36
AN26
AN27
AN30
AN32
AN35
AN37
AP27
AP36
AR31
AR34
AR38

AA39
AB17
AB38
AC18
AC39
AD17
AE18
AF17
AG18
AJ18
AK17
AL18

VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM

VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1

W17

VDD_DCS_S1

W22

VDD_DCS_S1

W24

VDD_DCS_S1

W26

VDD_DCS_S1

W31

VDD_DCS_S1

W33

VDD_DCS_S1

W35

VDD_DCS_S1

W39

VDD_DCS_S1

Y18

VDD_DCS_S1

Y20

VDD_DCS_S1

Y23

VDD_DCS_S1

Y25

VDD_DCS_S1

Y27

VDD_DCS_S1

Y29

VDD_DCS_S1

Y32

VDD_DCS_S1

Y34

VDD_DCS_S1

Y38

VDD_DCS_S1

VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1

AA18
AA32
AB20
AB24
AB31
AB35
AC21
AC28
AC30
AD20
AD21
AD24
AD28
AD30
AD35
AF20
AF22
AF26
AF30
AG28
AH19
AH21
AH23
AH25
AH27
AH29
AH31
AK19
AK21
AK23
AM19
AM21
AM23
AP21
AP23
AT19
AT21
AT23
AT25
AT27
AT29
AT31
AT39
AU36
AV37

PP0V764_S1_SRAM

C1420

11UF

20%

2.5V
X6T

0402

1

4

2

7818

C1423

11UF

20%

2.5V
X6T

0402

1

4

2

3

3

C1422

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1421

11UF

20%

2.5V
X6T

0402

3

1

4

2

C1424

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1425

11UF

20%

2.5V
X6T

0402

1

4

2

3

PAGE TITLE

SOC: POWER (SRAM)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

**OK2INTEGRATE**

PP0V805_S1_VDD_FIXED

78

LPDP_RX Power may be grounded,
Wait until Dev Bringup is complete before grounding it.

Until then connect it to PP1V2_AWAKE

PP0V805_S1_VDD_FIXED

78

20%

4V

0201

1

2

C1508

78 15

78 15

C1507

2.2UF

X6S-CERM

PP0V805_S1_VDD_FIXED

PP0V805_S1_VDD_FIXED

C1513

4.3UF

20%

2.5V
X6T

0402

1

3

4

2

120OHM-25%-0.25A-0.5OHM

78 15

78 18

78 18

PP0V805_S1_VDD_FIXED

PP0V805_S1_VDD_FIXED

78

PP0V805_S1_VDD_FIXED

PP0V72_S2_VDD_LOW

C1520

3PF

+/-0.1PF

25V
C0G

0201

1

2

1

C1510

2.2UF

20%
4V

2

X6S-CERM
0201

C1521

2.2UF

20%

X6S-CERM

0201

C1530

4.3UF

20%

2.5V
X6T

0402

3

4

2

PP0V72_S2_VDD_LOW

78

PP0V72_S2_VDD_LOW

78

1

78 18

0.1UF

6.3V
0201

1

4V

2

PP0V805_S1_VDD_FIXED

C1505

0.1UF

10%

6.3V 4V
X6S

0201 0201

10%
X6S

1

2

R1500

C1514

78 15

FL1510

21

PP0V805_S1_SOC_VDDFIXEDPLL_F

0201

20%

4V

0201

1

2

C1511

2.2UF

X6S-CERM

C1531

4.3UF

20%

2.5V
X6T

0402

1

3

4

2

PP0V805_S1_VDD_FIXED

78

1

2

0

5%

1/20W

MF

0201

0.1UF

C1506

2.2UF

X6S-CERM

78

VOLTAGE=0.805V

21

PP0V805_S1_SOC_VDDFIXEDPCIE_R

1

10%

6.3V
2

X6S

1

20%

2

PP0V805_S1_VDD_FIXED

C1515

0.1UF

6.3V
02010201

PP0V805_S1_VDD_FIXED

C1502

0.1UF

VOLTAGE=0.805V

C1512

0.1UF

R1590

10

5%

1/20W

MF

201

21

1

10%

6.3V
2

X6S

0201

VOLTAGE=0.805V

PP0V805_S1_SOC_VDDFIXEDXTAL_R

1

2

R1535

10

2 1

5%

1/20W

MF

201

R1536

49.9

1/20W

78

21
1%
MF

201

PP0V72_S2_VDD_LOW

5%

25V

0201

C1500

0.1UF

6.3V

1

2

2.2UF

X6S-CERM

10%
X6S

C1519

20%

4V

0201

1

2

C1517

0.22UF

20%

6.3V

X6S-CERM

02010201

3PF

+/-0.1PF

25V
C0G

0201

1

2

C1504

2.2UF

X6S-CERM

1

2

C1501

1

10%

2

X6S

1

10%

6.3V
2

X6S

C1516

0.1UF

6.3V

C1518

12PF

NP0-C0G

C1503

1

10%

2

X6S

C1590

4UF

20%

2.5V
X6S
0201

VOLTAGE=0.72V

PP0V72_S2_VDD_LOWFLPLL_R

C1535

0.22UF

X6S-CERM

VOLTAGE=0.72V

PP0V72_S2_VDD_LOWULPPLL_R

1

20%

6.3V
2

0201

1

C1536

4UF

20%

2.5V

2

X6S
0201

1

2

0.1UF

6.3V
0201

20%

4V

020102010201

10%
X6S

1

2

5

U0600

PP0V855_S2SW_CIO

TMLR68A0-B09

BGA

SYM 13 OF 23

C1540

0.1UF

AM28

AW19
AW20
AW21

BA37
BA38
BA39

1

2

AY18

AV33

AV29
AV30
AV31
AV32

AL34

AT32

AF29

AR20

AH13
AG13
AC13

AC42

BA32

AD40
AG40
AJ39
AP17
AU32
AV39
AY16

AV23
AV25
AV27
AW26
AY26
BA23

AW24

AW22

AW28

BA22

VDD_FIXED_ECPU_S1

VDD_FIXED_LPDP_RX_S1
VDD_FIXED_LPDP_RX_S1
VDD_FIXED_LPDP_RX_S1

VDD_FIXED_LPDP_TX_S1
VDD_FIXED_LPDP_TX_S1
VDD_FIXED_LPDP_TX_S1

R11

VDD_FIXED_MIPIC_S1

R12

VDD_FIXED_MIPIC_S1

R13

VDD_FIXED_MIPIC_S1

R10

VDD_FIXED_MIPID_PLL_S1

P9

VDD_FIXED_MIPID_S1

R9

VDD_FIXED_MIPID_S1

VDD_FIXED_MTR_S1

VDD_FIXED_PCIE_REFBUF_S1

VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1

VDD_FIXED_PCPU_S1

VDD_FIXED_PLL_ANE_S1

VDD_FIXED_PLL_GPU_S1

VDD_FIXED_PLL_SOC_S1

VDD_FIXED_PLL_DDR0_S1
VDD_FIXED_PLL_DDR1_S1
VDD_FIXED_PLL_DDR2_S1

T24

VDD_FIXED_PLL_DDR3_S1

R28

VDD_FIXED_PLL_DDR4_S1

R29

VDD_FIXED_PLL_DDR5_S1

T34

VDD_FIXED_PLL_DDR6_S1
VDD_FIXED_PLL_DDR7_S1

VDD_FIXED_XTAL_S1

VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1

V17

VDD_FIXED_S1

VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2

VDD_LOW_FLPPLL_S2

VDD_LOW_ULPPLL_S2

VDD_LOW_USB_DEBUG_S2

VDD_HIB_S4

VDD_CIO
VDD_CIO
VDD_CIO

VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2

VDD_CIO_USB

VDD12_CIO_USB_S2

VDD12_AMUX_S2

VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX

VDD12_LPDP_TX
VDD12_LPDP_TX
VDD12_LPDP_TX

VDD12_MIPIC
VDD12_MIPIC
VDD12_MIPIC

VDD12_MIPID
VDD12_MIPID

VDD12_MTR

VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE

VDD12_PCIE_REFBUF

VDD12_PLL_ANE

VDD12_PLL_CPU

VDD12_PLL_GPU

VDD12_PLL_SOC

VDD12_TSADC_CPU

VDD12_TSADC_SOC0
VDD12_TSADC_SOC1
VDD12_TSADC_SOC2
VDD12_TSADC_SOC3
VDD12_TSADC_SOC4

VDD12_ULPPLL_S2

VDD12_USB_DEBUG_S2

VDD12_XTAL

AV34
AV36
AW35

AU42
AU43
AV42
AV43
AY34
AY36
BA35

AU34

AU35

AT42

AV11
AV20
AW11
AW13
AY13
AY19
AY20
AY21

AW37
AW38
AW39

P11
P12
P13

P8
R8

AW18

AY29
AY30
AY31
AY32
AY43
BA42
BA43

AW33

AP31

AK34

AG29

AP19

AK32

U20
Y33
AH32
AY15
AE40

AW23

AY28

BA33

PP1V2_S2_CIO

C1544

PP0V855_S2SW_CIO
PP1V2_S2_CIO
PP1V25_S2
PP1V25_AWAKE_IO

PP1V2_AWAKE_PLL

C1563

+/-0.1PF

PP1V25_AWAKE_IO

10%

6.3V
X6S

C1554

1

2

0.1UF

C1560

2.2UF

X6S-CERM

1

20%

4V

0201 0201

C1561

0.1UF

PP1V25_AWAKE_IO

PP1V2_AWAKE_PLL

C1553

0.1UF

VOLTAGE=1.2V

1

10%

6.3V
2

X6S

0201 0201

PP1V2_AWAKE_PLL_PCIE_R

PP1V2_AWAKE_PLL

PP1V25_AWAKE_IO

VOLTAGE=1.25V

PP1V25_S2_ULPPLL_R

PP1V25_S2

1

C1582

0.1UF

10%

6.3V

2

X6S
0201

0.1UF

6.3V

C1573

1

10%

6.3V
2

X6S

1

10%

6.3V
2

X6S

0201 0201

1

3PF

25V

2

C0G

0201

C15622

10%

2

X6S

1

0.1UF

10%

6.3V 4V
X6S

0201 0201

C1541

C1545

C1564

NP0-C0G

2.2UF

20%

4V

X6S-CERM

0201

C1574

X6S-CERM

0.1UF

0.1UF

12PF

5%

25V

0201

1

2

2.2UF

C1570

78

78

1

10%

6.3V
2

X6S

02010201

1

10%

6.3V
2

X6S

1

C1550

2.2UF

2

X6S-CERM

20%

4V

0201

1

C1551

0.1UF

2

R1574

0

21

5%

1

20%

2

0.1UF

10%

6.3V 4V
X6S

0201 02010201

1/20W

MF

0201

1

C1571

0.1UF

2

10%

6.3V
X6S

1

2

R1584

1

C1584

4.7UF

20%

6.3V

2

CER
0402

49.9

1/20W

1%
MF

201

21

PP1V25_S2

1

10%

6.3V
2

X6S

0201

C1572

2.2UF

20%

X6S-CERM

Wait until Dev Bringup is complete before grounding it.

C1555

4.3UF

20%

2.5V
X6T

0402

1

1

2

3

4

2

C1542

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1546

4.3UF

20%

2.5V
X6T

0402

1

4

2

3

3

78

78

78

78

78

LPDP_RX Power may be grounded,

Until then connect it to PP1V2_AWAKE

78

78

C1556

4.3UF

1

2

78

78

20%

2.5V
X6T

0402

4

C1543

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1547

4.3UF

20%

2.5V
X6T

0402

1

4

2

3

3

3

FL1580

VDD12_EFUSE1
VDD12_EFUSE2
VDD12_EFUSE3

VDD12_FMON

AU40
AT20
AB43

AU19

VOLTAGE=1.25V

PP1V25_AWAKE_XTAL_F

VOLTAGE=1.25V

PP1V25_AWAKE_FMON_R

1

C1583

2.2UF

20%
4V

2

X6S-CERM
0201

240-OHM-0.2A-0.9-OHM

2 1

0201

1

C1580

0.1UF

10%

6.3V

2

X6S
0201

R1583

49.9

1/20W

1%
MF

201

2

1

C1581

2.2UF

20%
4V

2

X6S-CERM
0201

PP1V25_AWAKE_IO

PP1V25_AWAKE_IO

78

78

PAGE TITLE

SOC: POWER (Fixed, PLL's, Filtered)

78

78

78

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

A

PP0V72_S2_VDD_LOW

78

C1537

0.1UF

10%

6.3V
X6S

0201

1

2

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

**OK2INTEGRATE**

SOC: GND (1)

A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

A2
A20
A21
A22
A23
A24
A25
A27
A28
A29

A3
A30
A37
A38
A39

A4
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54

A9

AA10
AA11
AA12
AA13
AA15
AA17
AA20
AA22
AA25
AA27
AA30
AA34
AA36
AA38
AA41
AA43
AA44
AA45
AA46
AA47

AA8
AA9

AB10
AB11
AB12
AB13
AB14
AB16
AB18
AB19

AB2

AB21
AB26
AB29
AB33
AB37
AB39
AB40

U0600

TMLR68A0-B09

SYM 15 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB42
AB44
AB45
AB46
AB47
AB48
AB5
AB51
AB54
AB8
AB9
AC10
AC11
AC12
AC15
AC17
AC20
AC22
AC25
AC27
AC29
AC32
AC34
AC36
AC41
AC44
AC45
AC46
AC47
AC8
AC9
AD10
AD11
AD12
AD13
AD14
AD16
AD18
AD19
AD23
AD26
AD29
AD31
AD33
AD38
AD39
AD8
AD9
AE10
AE11
AE12
AE14
AE15
AE17
AE2
AE20
AE22
AE25
AE28
AE41
AE5
AE8
AE9
AF10
AF11
AF12
AF13
AF14
AF16
AF18
AF19
AF21
AF23
AF25
AF27
AF31
AF34
AF35
AF37
AF38

AF40
AF42
AF43
AF44
AF45
AF46
AF47

AF8

AF9
AG10
AG11
AG12
AG15
AG20
AG22
AG24
AG26
AG30
AG32
AG35
AG37
AG41
AG43
AG44
AG45
AG46
AG47
AG48
AG51
AG54

AG8

AG9
AH10
AH11
AH12
AH18

AH2
AH20
AH24
AH26
AH28
AH30
AH33
AH36
AH38
AH41
AH42
AH43
AH44
AH45
AH46
AH47

AH5

AH8

AH9
AJ10
AJ11
AJ12
AJ13
AJ15
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ35
AJ37
AJ40
AJ41
AJ42
AJ43
AJ44
AJ45
AJ46
AJ47

AJ8

AJ9
AK10
AK11

U0600

TMLR68A0-B09

SYM 16 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK12
AK13
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AK39
AK47
AK49
AK51
AK54
AK8
AK9
AL10
AL11
AL12
AL13
AL15
AL17
AL19
AL2
AL21
AL23
AL25
AL27
AL31
AL36
AL39
AL47
AL5
AL55
AL8
AL9
AM10
AM11
AM12
AM13
AM14
AM16
AM18
AM20
AM22
AM24
AM27
AM30
AM32
AM33
AM35
AM37
AM40
AM6
AM7
AM8
AM9
AN1
AN10
AN11
AN12
AN13
AN14
AN19
AN2
AN21
AN25
AN28
AN3
AN31
AN36
AN39
AN4
AN41
AN5
AN6
AN7
AN8

AN9
AP10
AP11
AP12
AP13
AP14
AP15
AP18
AP20
AP22
AP24
AP26
AP28

AP3
AP30
AP32
AP34
AP35
AP37
AP42
AP53
AP54
AP55

AP6

AP9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR19
AR21
AR23
AR25
AR27
AR29

AR3
AR42
AR43
AR44
AR45
AR46
AR47
AR48
AR49
AR50
AR51
AR52
AR53

AR6

AR9
AT10
AT11
AT12
AT13
AT14
AT15
AT17
AT18
AT22
AT24
AT26
AT28

AT3
AT30
AT34
AT36
AT38
AT41
AT43
AT44
AT45
AT46
AT47
AT48
AT49
AT50
AT51

U0600

TMLR68A0-B09

SYM 17 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AT52
AT53
AT6
AT9
AU10
AU11
AU12
AU13
AU14
AU15
AU16
AU21
AU23
AU25
AU27
AU29
AU3
AU31
AU33
AU37
AU39
AU41
AU44
AU45
AU46
AU47
AU48
AU49
AU50
AU53
AU6
AU7
AU8
AU9
AV10
AV12
AV13
AV14
AV15
AV17
AV18
AV19
AV21
AV22
AV24
AV26
AV28
AV3
AV35
AV38
AV41
AV44
AV45
AV46
AV47
AV48
AV49
AV50
AV53
AV6
AV9
AW10
AW12
AW14
AW15
AW16
AW25
AW27
AW29
AW3
AW30
AW31
AW32
AW34
AW36
AW40
AW41
AW42
AW43
AW44

AW45
AW46
AW47
AW48
AW49
AW50
AW51
AW52
AW53

AW6

AW9
AY10
AY11
AY12
AY14
AY17
AY22
AY24

AY3
AY33
AY35
AY37
AY38
AY39
AY40
AY41
AY42
AY44
AY45
AY46
AY47
AY48
AY49
AY50
AY53

AY6

AY9

B1
B11
B12
B13
B14
B15
B16
B17
B18
B19

B2
B20
B22
B24
B27
B28
B29
B32
B34
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B49

B5
B51
B54
B55

B7
BA1

BA18
BA19

BA2

BA20
BA21
BA25
BA27

U0600

U0600

TMLR68A0-B09 TMLR68A0-B09

BGA

SYM 19 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SYM 18 OF 23

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA28
BA29
BA3
BA30
BA31
BA34
BA36
BA4
BA40
BA41
BA44
BA45
BA46
BA47
BA48
BA49
BA5
BA50
BA53
BA54
BA55
BA6
BA7
BA8
BA9
BB11
BB14
BB17
BB20
BB23
BB26
BB27
BB28
BB29
BB30
BB31
BB32
BB33
BB34
BB35
BB36
BB39
BB40
BB41
BB42
BB43
BB44
BB45
BB46
BB47
BB48
BB49
BB50
BB51
BB52
BB6
BB8
BC22
BC23
BC26
BC28
BC30
BC32
BC34
BC36
BC39
BC4
BC40
BC41
BC42
BC44
BC46
BC48
BC50
BC51
BC52
BD1
BD2
BD23
BD24

BD25
BD26
BD28
BD30
BD32
BD34
BD36
BD37
BD38
BD39
BD40
BD41
BD42
BD44
BD46
BD48
BD50
BD51
BD52
BD53
BD54
BD55

BE1
BE11
BE14
BE17

BE2
BE20
BE22
BE25
BE27
BE29

BE3
BE31
BE33
BE35
BE37
BE41
BE43
BE45
BE47
BE49

BE5
BE51
BE53
BE54
BE55

BE8

BF2
BF22
BF23
BF25
BF27
BF29

BF3
BF31
BF33
BF35
BF37
BF41
BF43
BF45
BF47
BF49
BF51
BF53
BF54

C1
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19

C2
C20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C21
C23
C25
C26
C27
C28
C29
C30
C31
C33
C35
C36
C37
C38
C39
C4
C40
C41
C42
C43
C44
C45
C46
C47
C48
C50
C52
C54
C55
C6
C8
C9
D1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D2
D20
D24
D26
D27
D28
D29
D3
D30
D32
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D5
D51
D53
D54
D55
D9
E1
E10
E11
E12
E13
E14
E15
E16
E17

PAGE TITLE

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

A

BOM_COST_GROUP=SOC

2

SOC: GND

1

8

**OK2INTEGRATE**

SOC: GND (2)

E18
E19

E2
E20
E22
E23
E25
E27
E28
E29
E31
E33
E34
E36
E37
E38
E39

E4
E40
E41
E42
E43
E44
E45
E46
E47
E49

E5
E50
E52
E54
E55

E6

E7

E9

F1
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19

F2
F20
F21
F22
F24
F26
F27
F28
F29

F3
F30
F32
F34
F35
F36
F37
F38
F39
F40
F41
F42
F43
F44
F45
F46
F47
F48
F49

F5
F51
F53
F54
F55

F7

U0600

TMLR68A0-B09

SYM 20 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F8
F9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G2
G20
G21
G22
G23
G25
G27
G28
G29
G31
G33
G34
G35
G36
G37
G38
G39
G4
G40
G41
G42
G43
G44
G45
G46
G47
G48
G49
G50
G52
G54
G6
G7
G8
G9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H2
H20
H21
H22
H24
H26
H27
H28
H29
H3
H30
H32
H34
H35
H36
H37
H38
H39
H40
H41
H42
H43
H44

H45
H46
H47
H48
H49

H5
H51
H53
H54

H7

H8

H9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19

J2
J20
J21
J22
J23
J25
J27
J28
J29
J31
J33
J34
J35
J36
J37
J38
J39

J4
J40
J41
J42
J43
J44
J45
J46
J47
J48
J49
J50
J52
J54
J55

J6

J7

J8

J9

K1
K10
K13
K16
K18
K19

K2
K20
K21
K22
K23
K25
K27
K28
K29
K31
K33
K34
K35
K36
K37
K38

U0600

TMLR68A0-B09

SYM 21 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K39
K4
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K50
K52
K54
K55
K6
K7
L1
L10
L13
L16
L18
L19
L2
L20
L21
L22
L24
L26
L27
L28
L29
L3
L30
L32
L34
L35
L36
L37
L38
L39
L40
L41
L42
L43
L44
L45
L46
L47
L48
L49
L5
L51
L53
L54
L55
L7
M1
M10
M13
M16
M17
M18
M19
M2
M20
M21
M22
M23
M25
M27
M28
M29
M31
M33
M34
M35
M36
M37

M38
M39

M4
M40
M41
M42
M43
M44
M45
M46
M47
M48
M49
M50
M52
M54
M55

M6

M7

M8

N1
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19

N2
N20
N21
N22
N23
N24
N26
N27
N28
N29

N3
N30
N32
N33
N34
N35
N36
N37
N38
N39
N40
N41
N42
N43
N44
N45
N46
N47
N48
N49

N5
N50
N51
N53
N54

N6

N7

N8

N9

P1
P10
P14
P15
P16
P17
P18
P19

P2
P20

U0600

TMLR68A0-B09

SYM 22 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P21
P22
P25
P26
P27
P28
P29
P3
P30
P31
P34
P35
P36
P37
P38
P39
P4
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P52
P53
P7
R1
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R26
R27
R3
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R4
R40
R41
R42
R43
R44
R45
R46
R47
R5
R6
R7
T1
T10
T11
T12
T13
T14
T15
T17
T19
T2
T21
T23
T27

T3
T31
T35
T37
T39

T4
T41
T42
T43
T44
T45
T46
T47
T48

T5
T51
T54

T6

T7

T8

T9

U1
U10
U11
U12
U13
U16
U18

U2
U22
U24
U26
U28

U3
U30
U32
U34
U36
U38

U4
U40
U41
U42
U43
U44
U45
U46
U47
U48

U5

U6

U7

U8

U9

V1
V10
V11
V12
V13
V14
V15

V2
V21
V23
V25
V27

V3
V31
V33
V35
V39

V4
V41
V42
V43
V44
V45
V46
V47

V5

U0600

TMLR68A0-B09

SYM 23 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

V6
V7
V8
V9
W10
W11
W12
W13
W15
W16
W2
W21
W23
W25
W27
W32
W34
W41
W42
W43
W44
W45
W46
W47
W48
W5
W51
W54
W8
W9
Y10
Y11
Y12
Y13
Y14
Y16
Y19
Y22
Y24
Y28
Y30
Y35
Y37
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y51
Y8
Y9
B48

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

PAGE TITLE

SOC: GND-2

79 11

PP1V8_S2SW_VDD1

78 15

PP0V72_S2_VDD_LOW

78 11

78 11

5%

25V

0201

1

2

C1801

3.0PF

+/-0.1PF

NP0-C0G

C1800

12PF

NP0-C0G

PP1V06_S2SW_DRAM

5%

25V

0201

1

2

C1811

3.0PF

+/-0.1PF

NP0-C0G

C1810

12PF

NP0-C0G

PP0V6_S1_VDDQL

5%

25V

0201

1

2

C1821

3.0PF

+/-0.1PF

NP0-C0G

C1820

12PF

NP0-C0G

25V

0201

25V

0201

25V

0201

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

C1805

3.0PF

+/-0.1PF

NP0-C0G

C1815

3.0PF

+/-0.1PF

NP0-C0G

C1825

3.0PF

+/-0.1PF

NP0-C0G

1

C1802

12PF

2

1

NP0-C0G

C1812

12PF

2

1

NP0-C0G

C1822

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

C1803

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1813

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1823

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

C1804

12PF

2

1

NP0-C0G

C1814

12PF

2

1

NP0-C0G

C1824

12PF

2

NP0-C0G

25V

0201

25V

0201

25V

0201

1

C1870

12PF

2

78 13

1

PPVDD_ECPU_AWAKE

NP0-C0G

C1872

12PF

2

78 13

1

2

PPVDD_DISP_S1

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

C1871

3.0PF

+/-0.1PF

NP0-C0G

C1873

3.0PF

+/-0.1PF

NP0-C0G

C1874

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

25V

0201

1

2

1

2

1

2

78 13

78 13

78 14

PPVDD_PCPU_AWAKE

5%

25V

0201

1

2

C1831

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1830

12PF

NP0-C0G

PPVDD_GPU_AWAKE

5%

25V

0201

1

2

C1841

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1840

12PF

NP0-C0G

PPVDD_CPU_SRAM_AWAKE

1

C1832

12PF

2

1

NP0-C0G

C1842

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

C1833

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1843

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

C1834

12PF

2

1

NP0-C0G

C1844

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

C1835

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1845

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

2

1

2

78 14

78 14

1

2

C1851

3.0PF

+/-0.1PF

NP0-C0G

C1850

12PF

5%

25V

NP0-C0G

0201

PPVDD_DCS_S1

5%

25V

0201

1

2

C1855

3.0PF

+/-0.1PF

NP0-C0G

C1854

12PF

NP0-C0G

PP0V764_S1_SRAM

1

2

C1861

3.0PF

+/-0.1PF

NP0-C0G

C1860

12PF

5%

25V

NP0-C0G

0201

25V

0201

25V

0201

25V

0201

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

C1853

3.0PF

+/-0.1PF

NP0-C0G

C1857

3.0PF

+/-0.1PF

NP0-C0G

C1863

3.0PF

+/-0.1PF

NP0-C0G

1

C1852

12PF

2

1

NP0-C0G

C1856

12PF

2

1

NP0-C0G

C1862

12PF

2

NP0-C0G

25V

0201

25V

0201

25V

0201

1

2

1

2

1

2

78 15

78 15

PP0V805_S1_VDD_FIXED

PP0V805_S1_VDD_FIXED

C1864

12PF

5%

25V

NP0-C0G

0201

C1866

12PF

5%

25V

NP0-C0G

0201

2

1

2

C1865

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1867

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

2

1

SYNC_DATE=10/08/2019SYNC_MASTER=ref_soc_h13g

PAGE TITLE

2

SOC: DESENSE CAPS

DRAWING NUMBER

051-05392

Apple Inc.

REVISION

SIZE

D

4.0.0

BRANCH

evt-1

PAGE

18 OF 801

SHEET

18 OF 92

BOM_COST_GROUP=DESENSE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

1

8

**OK2INTEGRATE**

SPI NOR (1.8V 64 M-BIT)

PP1V8_AWAKE

78

78 19

R1974

7

SPI_SOCROM_MOSI_R

IN

R1975

7

SPI_SOCROM_CLK_R

IN

1

R1972

47K

5%
1/20W

201

2

1

R1973

47K

5%
1/20W
MFMF
201

2

78 19

PP1V25_AWAKE_IO

33

21

5%

1/20W

MF

201

33

5%

1/20W

MF

201

21

SPI_SOCROM_MOSI
SPI_SOCROM_CLK

PP1V8_AWAKE

1

C1974

0.1UF

10%

6.3V

2

X6S

U1974

74AVC2T45

1A
2A

5

DIR

VSSOP

GND

PP1V8_AWAKE

VCCBVCCA

72

1B
2B

SPI_SOCROM_1V8_MOSI_R

63

SPI_SOCROM_1V8_CLK_R

PP1V25_AWAKE_IO

7819

1

C1975 2

0.1UF

10%

6.3V

2

X6S
02010201

7819

R1976

33

5%

1/20W

MF

201

R1977

33

5%

1/20W

MF

201

21

SPI_SOCROM_1V8_MOSI

21

SPI_SOCROM_1V8_CLK

19

19

19

19

1

C1970

0.1UF

10%

6.3V
X6S
0201

R1971

SPI_SOCROM_1V8_CLK

SPI_SOCROM_1V8_CS_L

10K

5%

1/20W

MF

201

1

2

R1970

100K

5%

1/20W

MF

201

SPI_SOCROM_WP_L

1

VCC

2

U1970

W25Q64JWUUIQ

64MB-1.8V

6

CLK

1

CS*

3

WP*/IO2

7

HOLD*/RESET*/(IO3)

USON

DI(IO0)

DO(IO1)

EPADGND

5

SPI_SOCROM_1V8_MOSI

2

SPI_SOCROM_1V8_MISO_R

19

19

SPI_SOCROM_1V8_MISO_R

19

1

R1980

100K

5%
1/20W
MF
201

2

R1983

33

5%

1/20W

MF

201

78 19

1

C1983

0.1UF

10%

6.3V

2

X6S
0201

21

SPI_SOCROM_1V8_MISO

PP1V25_AWAKE_IO

1

C1992

0.1UF

10%

6.3V

2

X6S
0201

1

R1992

47K

5%
1/20W
MF
201

2

VCCA VCCB

5

DIR

A

VCCA VCCB

5

DIR

GND

U1983

SN74AXC1T45

SOT-5X3

43

B

PP1V8_AWAKE

U1992

SN74AXC1T45

SOT-5X3

1

C1984

0.1UF

10%

6.3V

2

X6S
0201

1

C1993

0.1UF

10%

6.3V

2

X6S
0201

R1984

33

21

SPI_SOCROM_MISOSPI_SOCROM_MISO_R

5%

1/20W

MF

201

7819

OUT

7

43

7

IN

A

GND

B

SPI_SOCROM_1V8_CS_LSPI_SOCROM_CS_L

19

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

PAGE TITLE

SPI NOR

SIZE

D

BOM_COST_GROUP=SOC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

19 OF 801

SHEET

19 OF 92

2

1

A Series Terminations D Test Points

TCON SPI Interface

7 67

IN

IN OUT

SPI_TCON_CLK_R SPI_TCON_CLK

SPI_TCON_MOSI_R

R2101

R2102

2 1

2 1

MF 5%

20

5%MF

1/20W201

20

1/20W201

SPI_TCON_MOSI

Speaker Amp TDM Interface

7

IN OUT

7

IN OUT

7

IN OUT

TDM_SPKRAMP_L_BCLK_R

TDM_SPKRAMP_L_R2D_R

TDM_SPKRAMP_L_FSYNC_R

R2110

201 1/20W

R2111

201 1/20W

R2112

201 1/20W

2 1

MF 5%

2 1

MF 5%

2 1

MF 5%

20

20

20

TDM_SPKRAMP_L_BCLK

TDM_SPKRAMP_L_R2D

TDM_SPKRAMP_L_FSYNC

OUT

10

OUT

6

IN

10

IN

677

6

IN

80

80

80

6

IN

6

IN

SMC_FIXTURE_MODE_L
SOC_AMUX_OUT
TPT_SOC_DOCK_ATTENTION

TPT_SOC_DOCK_ATTENTION

MAKE_BASE=TRUE

TPT_TST_CLKOUT

TPT_TST_CLKOUT

MAKE_BASE=TRUE

TPT_TMU_CLK_OUT0

TPT_TMU_CLK_OUT0

MAKE_BASE=TRUE

TPT_TMU_CLK_OUT1

TPT_TMU_CLK_OUT1

MAKE_BASE=TRUE

1

TP
TP
TP

TP

TP

TP

TP-P4
TP-P4
TP-P4

TP-P4

TP-P4

TP-P4

1
1

1

1

1

TP2101
TP2102
TP2103

TP2104

TP2105

TP2106

7

IN

7

7

IN

TDM_SPKRAMP_R_BCLK_R

TDM_SPKRAMP_R_R2D_R

TDM_SPKRAMP_R_FSYNC_R

R2162

R2163

201 5%MF

R2164

20

21

1/20WMF201 5%

20

21

1/20W

20

21

1/20W201 MF 5%

TDM_SPKRAMP_R_BCLK

TDM_SPKRAMP_R_R2D

TDM_SPKRAMP_R_FSYNC

Trackpad SPI Interface

7 76

IN

7

IN

SPI_IPD_MOSI_R SPI_IPD_MOSI

SPI_IPD_CLK_R

R2113

201 1/20W

R2114

201

2 1

MF 5%

2 1

20

20

5%MF

1/20W

SPI_IPD_CLK

Master PMU SPI Interface

10 34

IN OUT

10 34

BI BI

SPMI_NUB_MPMU_CLK_R SPMI_NUB_MPMU_CLK

SPMI_NUB_MPMU_DATA_R SPMI_NUB_MPMU_DATA

R2115

R2116

201 1/20W

2 1

2 1

MF 5%

20

5%MF

1/20W201

20

OUT

OUTIN

OUT

OUT

OUT

10

80

80

80

IN

10

IN

10

IN

TPT_JTAG_SOC_TDI

TPT_JTAG_SOC_TDI

MAKE_BASE=TRUE

TPT_JTAG_SOC_TDO

TPT_JTAG_SOC_TDO

MAKE_BASE=TRUE

TPT_JTAG_SOC_TRST_L

TPT_JTAG_SOC_TRST_L

MAKE_BASE=TRUE

1

TP

TP-P4

1

TP

TP-P4

1

TP

TP-P4

TP2107

TP2108

TP2109

Place near level shifterPlace near SOC

76

6

6

6

EUSB_ATC0_P

BI

BI

BI

EUSB_ATC0_N

EUSB_ATC1_P

PP2190

PP2191

PP2192

PP

PP

PP

1

P4MM

P4MM

1

P4MM

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

EUSB_ATC0_P
EUSB_ATC0_P

EUSB_ATC0_N

EUSB_ATC0_N

EUSB_ATC1_P

EUSB_ATC1_P

TP-P4

TP-P4

TP-P4

58

BI

1

TP

1

TP

1

TP

TP2194

TP2195

TP2196

BI

BI

58

58

Slave PMU SPI Interface

10 30

IN OUT

10

BI

SPMI_NUB_SPMU_CLK_R SPMI_NUB_SPMU_CLK

SPMI_NUB_SPMU_DATA_R

R2117

R2118

201 1/20W

2 1

MF 5%

2 1

20

1/20W201

20

5%MF

SPMI_NUB_SPMU_DATA

SPMI Interface

10

IN

10 21

BI

SPMI_SE_CLK_R

SPMI_SE_DATA_R SPMI_SE_DATA

R2119

201 1/20W

R2120

2 1

2 1

MF 5%

20

5%MF

SPMI_SE_CLK

20

1/20W201

AOP Gyro SPI Interface

IN

SPI_AOP_GYRO_MOSI_R

SPI_AOP_GYRO_MOSI_R

MAKE_BASE=TRUE

IN OUT

SPI_AOP_GYRO_CLK_R

SPI_AOP_GYRO_CLK_R

MAKE_BASE=TRUE

49

OUT

SPI_AOP_GYRO_MISO

R2121

201 1/20W

10

R2122

201 1/20W

10

2 1

2 1

20

5%MF

20

5%MF

SPI_AOP_GYRO_MOSI

SPI_AOP_GYRO_CLK

SPI_AOP_GYRO_MISO

MAKE_BASE=TRUE

10

BI

OUT

BI

OUT

6

BI

30

21

EUSB_ATC1_N

PP2193

PP

1

P4MM

MAKE_BASE=TRUE

EUSB_ATC1_N

EUSB_ATC1_N

TP-P4

58

BI

1

TP

TP2197

E Pull Down Resistors

UPC_FORCE_PWR

759

49

49

SOC_DFU_STATUS

65482

1

R2170

47K

5%
1/20W
MF
201

2

1

R2175

47K

5%
1/20W
MF
201

2

GPU_CFG_L

7

SOC_SEL:GOOD

1

R2176

1K

5%
1/20W
MF
201

2

B BOOT Config Aliases

57

OUT

57

OUT

57

OUT

BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2

SSD S5E Data/Clock AliasesC

SWD_NAND0_SWCLK

6

MAKE_BASE=TRUE

SWD_NAND0_SWDIO

6

MAKE_BASE=TRUE

BOOT_CONFIG0

MAKE_BASE=TRUE

BOOT_CONFIG1

MAKE_BASE=TRUE

BOOT_CONFIG2

MAKE_BASE=TRUE

SWD_NAND0_SWCLK
SWD_NAND0_SWCLK

SWD_NAND0_SWDIO
SWD_NAND0_SWDIO

62

63

62

63

SOC: Project Support

Apple Inc.

Timing Requirements:

- VBAT supply ramp time: 20ms

Ceres - Secure Element

*** OK2INTEGRATE ***

Per TGA Power Block Diagram v0.3

U5000.B5:3mm

C5008

0.22UF

6.3V
0201

X5R

PP1V8_S2

78

IccMax SE only: 125mA IccMax SE only: 10mA

U5000.F9:3mm

C5014

1.0UF

6.3V

0201-1

20%
X5R

U5000.F8:3mm

20%

6.3V
X5R

0201

0

1

2

21

VUP_SEVDDBOOST_SE

5%0201

1

C5002

0.22UF

2

R5030

MF1/20W

U5000.E7:3mm

C5003

0.22UF

6.3V
0201

20%
X5R

1

2

PP1V25_S2

VDDPLL_SE
VDDNV_SE
VDDC_SE

20%
10V
X5R

0201

1

2

C5051

U5000.E8:3mm

1

2

C5009

0.22UF

20%20%
X5R

0201

1

2

U5000.E9:3mm

C5010

0.22UF

6.3V6.3V
0201

20%
X5R

2

2.2UF

PP3V8_AON_VDDMAIN 7921

IccMax: 100mA

78

Based on SPMI only use case

As per NXP preliminary estimate, final pending

NC

D4

NFC_CLK_32K

H6

NC

SE_CTLR_FW_DWLD

21

NC_SE_GPIO0

81

NC
NC
NC

R5042

MF1/20W 201

R5041

1/20W MF 201

20

20

BI

SPMI_SE_CLK

IN

SPMI_SE_DATA

1

R5050

1M

5% 5%
1/20W
MF
201

2

5%

5%

47K

47K

1

R5051

1M

1/20W
MF
201

2

21

UART_SE_R2D_RTS_L
NC_UART_SE_D2R_CTS_L

NO_TEST

21

UART_SE_R2D
NC_UART_SE_D2R

21

SE_DEV_WAKE

NO_TEST

NC
NC

NC

NC
NC

NC

NFC_CLK_REQ

A6

NFC_CLK_XTAL1

G4

NFC_DWL_REQ

F6

NFC_GPIO0

J7

NFC_GPIO1

J5

NFC_GPIO2_AO

H4

NFC_GPIO3_AO

E6

NFC_HSU_CTS

F5

NFC_HSU_RTS

G5

NFC_HSU_RX

E5

NFC_HSU_TX

E4

NFC_I2C_SCL

F4

NFC_I2C_SDA

J6

NFC_IRQ

G9

NFC_SIM_SWIO1

J8

NFC_SIM_SWIO2

H7

NFC_SPMI_SCLK

G7

NFC_SPMI_SDATA

H5

NFC_WKUP_REQ

B6

NFC_XTAL2

G6

TM

A3

RXP

A4

RXN

50K internal pull-down

U5000

SN210VUK/B101V7

WLCSP

OMIT_TABLE

NC

NCNCNC

TX1
TX2

VHV

VEN

H3

NC

F3

NC

G1
H1

F2

NC

F1

NC

G3

NC

G2

NC

J2

NC

H2

NC

E2

NC

D2

NC

D1

NC

B3

NC

C2

NC

A1

NC

C1

NC

D7

NC

C7

NC

B8
B9

B7

VHV_SE

D3

NC

D5

SE_PWR_EN

C5

VREF_SE

Pulls to be added in system, can be NC'd if unused

NC_I2C_SE_SCL
NC_I2C_SE_SDA

IN
BI

80

80

PP3V8_AON_VDDMAIN

34

IN

7921

SE_GPIO0
SE_GPIO1

SE_I2C_SCL
SE_I2C_SDA

SE_ISO_CLK

SE_ISO_IO

SE_ISO_RST

SE_SPI_CLK

SE_SPI_CS
SE_SPI_MISO
SE_SPI_MOSI

TXVCASCP
TXVCASCN

RXVCM
TXVCM

VCASCHI
VCASCLO

BOOST_LX
BOOST_LX

VTUNE

VREF

R5000
R5006

47K
47K

21

5% MF

21

2011/20W

MF1/20W5% 201

SE_CTLR_FW_DWLD
SE_DEV_WAKE

1

C5004

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C5017

0.22UF

20%

6.3V

2

X5R
0201

SYNC_DATE=03/29/2020SYNC_MASTER=ref_se_ceres

Secure Element

DRAWING NUMBER

051-05392

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

21

21

<rdar://problem/52067756> [SN200V] Wired Mode SE Only Reference Design Material
<rdar://problem/45108950> Mac - Venus Reference guide and De-coupling requirements

BOM_COST_GROUP=SECURE ELEMENT

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

evt-1

PAGE

50 OF 801

SHEET

21 OF 92

SIZE

D

8

CRITICAL

J5150

RCPT-BMU-ANGLED-X1764

STRUCTURE ONLY
STRUCTURE ONLY

Mates with x

F-RT-TH

PWR

PWR
SIGNAL
SIGNAL
SIGNAL

PWR

PWR

1
2
3
4
5
6
7
8
9

518-00040

1

C5150

0.1UF

10%
25V

2

X7R-CERM-1
0402

OMIT_TABLE

1

C5151

1UF

10%
16V
CER-X6S
0402

D51502

SC-75

RCLAMP2402B

PPVBAT_AON_CONN
I2C_SMC_PWR_3V3_SCL
I2C_SMC_PWR_3V3_SDA
SYS_DETECT_L

SYSDET:AON

1

R5150

10K

5%
1/20W
MF
201

2

23

43 82

IN

43 82

BI

3

SYSDET:FET

D

Q5155

NTNS4CS69N

XDFN

SYM_VER_2

376S00282

1

2

GS

PP3V8_AON_VDDMAIN

SYSDET:FET

1

R5155

10K

5%
1/20W
MF
201

2

79

SYS_DETECT

BMU output is enabled after power is
supplied by other means, such as USBC connector.
MLB is thus unpowered during system assembly.

BMU Connector, Btn Logic

8

*** OK2INTEGRATE ***

PPDCIN_AON_CHGR_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1800

VOLTAGE=20V

FROM USB-C SOURCE

79 23

PACK_OPTION=CHGR_TP_TOP

PPDCIN_AONSW

PP5201

P2MM

SM

1

23

PP

PLACE_SIDE=TOP

PACK_IGNORE=TRUE

CHGR_GATE_Q1

CRITICAL

1

C5201

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

CRITICAL

1

C5204

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PP5211

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

CRITICAL

1

C5202

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

CRITICAL

1

C5205

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

CRITICAL

1

C5203

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

CRITICAL

1

C5206

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

CRITICAL

1

C520A

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

1

C5205

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

R5220

0.01

0.5%

0.5W
MF

0306

NO_XNET_CONNECTION=1

(AMON)
2-CELL: 0.02 OHM
3-CELL: 0.01 OHM

107S00053

21
43

CRITICAL

1

C520B

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

1

C5206

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

1

C520C

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

1

C5207

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

1

C520D

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

L5230

2.7UH-20%-12.5A-0.0196OHM

CHGR_PHASE1

23 23

DIDT=TRUE
SWITCH_NODE=TRUE SWITCH_NODE=TRUE

CRITICAL

ALLOW_APPLE_PREFIX=Q

IHLP4040BD-PIMA102D-COMBO

152S00198

21

CRITICAL

ALLOW_APPLE_PREFIX=Q

CHGR_PHASE2

23

PPVBAT_AON_CHGR_REG

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=13.05V

CKPLUS_WAIVE=CAPDERATE

CKPLUS_WAIVE=CAPDERATE

CRITICAL

1

C5250

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

1

2

CRITICAL

1

C5254

33UF

20%
16V

2

TANT
CASED12-SM

CAPMAT=POLY-TANT

PACK_OPTION=CHGR_40W

1

2

CKPLUS_WAIVE=CAPDERATE

CRITICAL

C5251

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

1

2

CRITICAL

C5255

33UF

20%
16V
TANT
CASED12-SM

CAPMAT=POLY-TANT

PACK_OPTION=CHGR_40W

1

2

CRITICAL

F5200

12A-32V-0.0045OHM

CKPLUS_WAIVE=CAPDERATE

CRITICAL

C5252

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

1

2

CRITICAL

C5256

2.2UF

20%
25V
X5R
0402-1

1206

21

1

2

CRITICAL

C5253

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

C5257

2.2UF

20%
25V
X5R
0402-1

TO SYSTEM

PPBUS_AON

1

2

C5258

1000PF

10%
25V
X7R
0201

79

PP5202

P2MM

SM

1

23

PP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PACK_OPTION=CHGR_TP

PACK_OPTION=CHGR_TP

79 23

PACK_IGNORE=TRUE

PP5203

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5204

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5205

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5206

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5207

P2MM

SM

PP

PP5208

P2MM

SM

PP

PPDCIN_AONSW

CHGR_GATE_Q2

1

23

CHGR_GATE_Q3

1

23

CHGR_GATE_Q4

1

23

CHGR_PHASE1

1

23

CHGR_PHASE2

1

CHGR_EN_MVR

1

CHGR_INT_1V8_L

78 24

PP1V8_S2

PP5212

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5213

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5214

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5215

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5216

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

23 24

23 24

1

R5215

750K

1%
1/20W
MF
201

2

NOSTUFF

C5216

0.01UF

X5R-CERM

1

10%
25V

2

0201

C5280

1.0UF

20%

6.3V
X5R

0201-1

1

2

PPVBAT_AON_CHGR_REG

23

C5278

2.2UF

X5R-CERM

CHGR_AUX_DET

1

R5216

255K

1%
1/20W
MF
201

2

CHGR_CSI_P CHGR_CSI_N

PLACE_NEAR=U5200.D5:2MM

R5221

1.00

1/20W
MF-LF

0201

CHGR_CSI_FILT_P

CRITICAL

1

10%
50V

2

0402

NO_XNET_CONNECTION=1

20%
35V

0402

C5221

0.047UF

CER-X7R

1

2

1%

2

CRITICAL

C5220

0.47UF

20%

4V

CERM-X5R-1

201

CRITICAL

C5270

0.12UF

10%
10V
X5R

0402

PLACE_NEAR=U5200.C5:2MM

1

R5222

1.00

1%
1/20W
MF-LF
0201

2

CHGR_CSI_FILT_N

CRITICAL

1

C5222

0.047UF

10%
50V

2

CER-X7R
0402

21

43

43

35

I2C_SMC_PWR_1V8_SDA

BI

I2C_SMC_PWR_1V8_SCL

IN

CHGR_RST_IN

IN

CHGR_COMP

NOSTUFF

CRITICAL

1

2

C5271

0.12UF

10%
10V
X5R

0402

PPVBAT_AON_CHGR_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

CHGR_GATE_Q1

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

CRITICAL

1

C5230

0.1UF

2

CHGR_GATE_Q2

2323 23

DIDT=TRUE
GATE_NODE=TRUE

2

XW5240

SMSM

1

10%
25V
X7R-CERM-1
0402

2

XW5230

1

CHGR_GATE_Q3

DIDT=TRUE

GATE_NODE=TRUE

CHGR_LX2

SWITCH_NODE=TRUE

CRITICAL

X7R-CERM-1

DIDT=TRUE

C5240

0.1UF

10%
25V

0402

1

2

CHGR_BOOT1_RC CHGR_BOOT2_RC

DIDT=TRUE
SWITCH_NODE=TRUE

1

R5230

0

5%
1/16W
MF-LF
402

2

CHGR_BOOT1

DIDT=TRUE
SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

R5240

0

5%
1/16W
MF-LF

402

CHGR_BOOT2

DIDT=TRUE

1

2

R5275

VOLTAGE=5V

24

PPCHGR_VDDA

CRITICAL

1

C5275

2.2UF

20%
25V

2

X5R-CERM
0402-1

4.7

5%

1/20W

MF

201

21

VOLTAGE=5V

PPCHGR_VDDP

CRITICAL

C5277

10UF

20%
10V
X5R

0603-1

1

2

XW5260

SM

21

PLACE_NEAR=Q5240.3:2MM

PLACE_NEAR=U5200.A4:2MM

CHGR_CSO_FILT_P

U5200

B5

P_IN

C5

CSIN

D5

CSIP

A5

PBUS_PWR

D3

AUX_DET

F5

VDDIO1P8

G5

SDA

H5

SCL

G2

SMC_RST_IN

G3

HPWR_EN*

E5

COMP

G4

B2
C2
E4

CELL

NC0
NC1

H:3-CELL

L:2-CELL

1

ISL9240HI

WCSP

CRITICAL

SCH SYMBOL

353S01525

(5V)

(OD)

GATE_Q1

BOOT1

LX1
GATE_Q2
GATE_Q3

LX2

BOOT2

GATE_Q4

PBUS
CSOP
CSON

BGATE

VBAT

EN_VR1

SMC_RST*

IRQ*
CBC_ON
EN_MVR
AUX_OK

AMON

BMONNC2

H1
F1
G1
E1
D1
B1
C1
A1
A3
A4
B4
B3
C3
F2
H4
H3
H2
F4
F3
D4
C4

CHGR_PBUS_SNS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CHGR_BGATE
CHGR_VBAT

NC_CHGR_EN_VR1

NC_CHGR_SMC_RST_L

CHGR_INT_1V8_L

NC_CHGR_CBC_ON
CHGR_EN_MVR
CHGR_AUX_OK
CHGR_AMON
CHGR_BMON

CHGR_GATE_Q4

DIDT=TRUE
SWITCH_NODE=TRUE

NO_XNET_CONNECTION=1

23

CRITICAL

R5260

0.005

0612-8

1 2
3 4

(BMON)
2-CELL: 0.010 OHM

1%

3-CELL: 0.005 OHM

1W
MF

107S00087

CHGR_CSO_P CHGR_CSO_N

1

PLACE_NEAR=U5200.B4:2MM

1

R5261

1.00 1.00

1%

2

1/20W
MF-LF

0201

R5262

1%
1/20W
MF-LF
0201

2

CHGR_CSO_FILT_N

CRITICAL

C5261

0.047UF

10%
50V

CER-X7R

0402

1

2

CRITICAL

1

C5262

0.047UF

10%
50V

2

CER-X7R
0402

CRITICAL

C5260

0.47UF

21

20% 4V

CERM-X5R-1

201

NO_XNET_CONNECTION=1

81

81

23 24

OUT

81

23 24

OUT

24

OUT

44

OUT

44

OUT

CRITICAL

Q5265

SI7655DN-COMBO

PWRPK-1212-8

SYM-VER-2

S

3
2
1

G

4

C5264

1000PF

21

10%
25V
X7R

0201

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

NTNS4CS69N

1

R5263

1K

5%
1/20W
MF
201

2

D

1

C5263

4700PF

10%
25V

2

CER-X5R
0201

CRITICAL

Q5270

SYM_VER_1

SAVE_BAT_S SAVE_BAT_G

CRITICAL

1

C5265

2.2UF

20%
25V

2

X5R
0402-1

5

XDFN

R5270

24K

1/20W

5%
MF

201

3

D

G

S

2

1

2

CRITICAL

1

C5266

2.2UF

20%
25V

2

X5R
0402-1

1

C5269

0.1UF

10%
25V

2

X5R
0201

<rdar://37259372&39763505>

1

CRITICAL

D5270

DFN0201

ALLOW_APPLE_PREFIX=D

GDZ5V6LP3-55

SYNC_MASTER=ref_charger_suona SYNC_DATE=05/02/2020

PAGE TITLE

PBUS SUPPLY & BATTERY CHARGER

CRITICAL

1

C5267

0.1UF

10%
25V

2

X5R
0201

CRITICAL

1

C5268

0.01UF

10%
25V

2

X5R-CERM
0201

PPDCIN_AONSW

1

R5271

200K

1%
1/20W
MF
201

2

TO/FROM BATTERY

PPVBAT_AON_CONN

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

7923

22

Apple Inc.

2

*** OK2INTEGRATE ***

CHGR I2C Level Translation

SMBUS_CHGR_1V8_[SCL/SDA]: Level translation circuit to be placed in project specific I2C page.

CHGR_INT_L Level Translation

Stuff R5320 in case, glitch during power sequencing is a concern.

78 23

PP1V8_S2

NOSTUFF

1

R5320

47K

5%
1/20W
MF
201

2

PP1V25_S2

78

PLACE_NEAR=U5320.6:5MM

1

C5320

0.1UF

10%

6.3V

2

CERM-X5R
0201

U5320

SN74AUP1G17

GND

SON

Y

4

CHGR_INT_L

VCC

23 80

CHGR_INT_1V8_L

2

A

NC

NC

CHGR_AUX_OK Pull Up

Pull up to MPMU LDO9, or rely on MPMU internal pull up.
OK, to completely remove pull up , but consult PMU architecture and check OTP before that.

PP1V8_AON_MPMU

78

NOSTUFF

1

R5330

47K

5%
1/20W
MF
201

2

>> SOC NUB_GPIO_5

OUTIN

23

IN

CHGR_AUX_OK

Delay for 3.8V VR Enable

RDAR://59315467
R5340 and C5340 might need tweaking afer charz.

R5342

2.2K

1/20W

R5340

23

IN

CHGR_EN_MVR

200K

1/20W

5%
MF

201

1%
MF

201

21

CHGR_EN_MVR_A

21

CHGR_EN_MVR_DLY

1

C5340

1UF

20%
10V

2

X5R
0201

CHGR_AUX_OK

MAKE_BASE=TRUE

D5340

X3DFN2

KA

NSR01L30MXT5G-COMBO

PPCHGR_VDDA

23

PLACE_NEAR=U5340.5:2MM

1

C5341

0.1UF

10%

6.3V

2

CERM-X5R
0201

>> MPMU GPIO2

34

OUT

NOSTUFF

R5341

0

5%

1/20W

MF

0201

2

NC

21

5

1 3

U5340

74LVC1G17

X2SON5

4

PLACE_NEAR=U5200:5MM

P3V8AON_PWR_EN

OUT

25

BOM_COST_GROUP=BATTERY

PAGE TITLE

BATTERY CHARGER SUPPORT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

53 OF 801

SHEET

24 OF 92

1

SYNC_DATE=05/02/2020SYNC_MASTER=ref_charger_suona

SIZE

D

*** OK2RELEASE ***

3V8 AON CONTROLLER

79 26

5.5 < VIN < 13.5 V

27

4.75 < VDRV < 5.5 V
VDRV IS EXTERNAL OPTION TO
POWER IC INSTEAD OF VIN
TO SAVE POWER

79

4.75 < LDO5 < 5.25 V
MAX I_OUT TYP 160 MA
LDO5 NOT TO BE USED BY
SYSTEM IN 30A DESIGNS

26

PPBUS_AON

1

C5704

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

BYPASS=U5700.8::15MM

PP5V_S2_P3V8AON_VDRV

1

C5700

10UF

20%
16V

2

X6S
0603-1

138S00248

BYPASS=U5700.6::15MM

0603 SIZE REQUESTED BY DCDC

PP5V_AON_P3V8VRLDO

1

C5702

10UF

20%
16V

2

X6S
0603-1

138S00248

BYPASS=U5700.7::15MM

0603 SIZE REQUESTED BY DCDC

P3V8AON_PVCC

8

6

7

5

VIN

VDRV

LDO5

PVCC

U5700

RAA225501A-BOM1

OMIT_TABLE

"BOM1" SCH SYMBOL

FOR 30A OTP

APN OF SYMBOL

353S02326

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

BOOT3

UGATE3

PHASE3

LGATE3

4

3

2

1

29

30

31

32

28

27

26

25

F_SW IS REGISTER CONTROLLED
ICCMAX 30A DESIGN: 1 MHZ

P3V8AON_BST1
P3V8AON_DRVH1
P3V8AON_SW1
P3V8AON_DRVL1

P3V8AON_BST2
P3V8AON_DRVH2
P3V8AON_SW2
P3V8AON_DRVL2

P3V8AON_BST3
P3V8AON_DRVH3
P3V8AON_SW3
P3V8AON_DRVL3

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

26

26

26 27

26

26

26

26 83

26

26

26

26 83

26

1

ONLY FOR USE BY GATE
DRIVE CIRCUITRY

R5710

0

5%
MF

0201

21

24

IN

P3V8AON_PWR_EN

1/20W

C5701

10UF

20%
16V

2

X6S
0603-1

138S00248

BYPASS=U5700.5::15MM

0603 SIZE REQUESTED BY DCDC

27

P3V8AON_PWR_EN_R

VIH_MAX 1.07 V
VIL_MIN 0.63 V

ENABLE

(9M PD)

VSEN

VRTN

15

16

P3V8AON_VSENSE

P3V8AON_VRTN

IN

IN

26 27

26

R5711

0

5%
MF

0201

21

35

IN

P3V8AON_LPM

1/20W

27

P3V8AON_LPM_R

VIH_MAX 1.1 V
VIL_MIN 0.5 V

P3V8AON_LPM

79

27

PP5V_AON_P3V8VRLDO

PU TO INT LDO5 OR OTHER RAIL

P3V8AON_FAULT_L

1

R5712

47K

5%
1/20W
MF
201

2

25

25

I2C_P3V8AON_SCL
I2C_P3V8AON_SDA

VIH_MAX 1.1 V
VIL_MIN 0.5 V
GND'ED FOR POR (DATASHEET TABLE 1.5)

FAULT PULL DOWN CURRENT 1-2 MA TYPICAL

13

10

9

14

LPM

SCL

SDA

FAULT*

(9M PD)

(OD)

CSP1

CSN1

CSP2

CSN2

19

20

21

22

P3V8AON_ISEN1_P
P3V8AON_ISEN1_N

P3V8AON_ISEN2_P
P3V8AON_ISEN2_N

IN

IN

IN

IN

26

26

26

26

P3V8AON_IMON

IMON NOT TO BE USED SYSTEM SIDE
<RDAR://58648650>
IMON IS 2.52 V @ 30 A
VENDOR REQUIRES R > 1M, C < 50 PF

1

C5751

10PF

5%
25V

2

C0G
0201

131S00003

NOSTUFF

1

R5751

2.21K

1%
1/20W
MF
201

2

118S0199

R5750

1M

5%

1/20W

MF

201

117S0009

21

P3V8AON_IMON_P3V8AON

P3V8AON_GPIO

OPEN FOR PRODUCTION APPLICATION
PER DATASHEET REV 1.0

P3V8AON_SS

LONG STARTUP TIME SO INRUSH

NOSTUFF

1

R5700

100K

5%
1/20W
MF
201

2

BELOW 0.5A USB LIMIT

1

C5703

0.22UF

10%
25V

2

X5R
0201-1

18

IMON

11

GPIO

17

SOFTSTART

(0-4.5V)

CSP3

CSN3

EPAD

23

24

P3V8AON_ISEN3_P

P3V8AON_ISEN3_N

IN

IN

26

26

132S00202

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 U5700 CRITICAL353S02472 IC,RAA225501B,ICE,BOM1,A1,OTP-R0B0,QFN32 P3V8AON_IC:A1_R0B0

BOM OPTIONCRITICAL

P3V8AON_IC:A0CRITICALU57001353S02326 IC,RAA225501,3-PH VOLT REG,TQFN32

TABLE_5_H EAD

TABLE_5_I TEM

TABLE_5_I TEM

3V8_AON_I2C-DEV

NOSTUFF

1

R5760

1K

5%
1/20W
MF
201

2

3V8_AON_I2C-DEV

1

R5762

0

5%
1/20W
MF
0201

2

80

TPT_P3V8AON_PU_RAIL

3V8_AON_I2C-DEV

NOSTUFF

1

R5761

1K

5%
1/20W
MF
201

2

3V8_AON_I2C-DEV

1

R5763

0

5%
1/20W
MF
0201

2

TP5700

1

TP

TP-P5

3V8_AON_I2C-DEV

GND

MAKE_BASE=TRUE

CKPLUS_WAIVE=I2C_PULLUP

I2C_P3V8AON_SCL

CKPLUS_WAIVE=I2C_PULLUP

I2C_P3V8AON_SDA

3V8_AON_I2C-POR3V8_AON_I2C-POR

GND

MAKE_BASE=TRUE

SYNC_MASTER=ref_vr_iceman SYNC_DATE=04/20/2020

PAGE TITLE

25

25

051-05392

SIZEDRAWING NUMBER

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

BOM_COST_GROUP=PLATFORM POWER

5 478

8

*** OK2RELEASE ***

79 26 25

PPBUS_AON

CRITICAL

R5804

2.2

5%
MF

201

21

C5811

0.1UF

21

10%
25V

X7R-CERM-1

0402

132S0438

P3V8AON_DRVH1_R

27

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_SW1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

25 27

OUT

CRITICAL

Q5800

CSD58889Q3D

376S00012

3

TG

4

TGR

Q3D

VIN

VSW

1

6
7
8

83 83

25

IN

P3V8AON_DRVH1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

1/20W

117S0056

<RDAR://59524111>

R5803

0

5%
MF

0201

21

25

OUT

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

1/20W

117S0201

NOSTUFF

P3V8AON_BST1_RCP3V8AON_BST1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

D5800

SOD523

KA

5

BG

R5805

1

5%
1/16W
MF-LF

402

116S0006

21

P3V8AON_DRVL1_R

27

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

2526

25

IN

P3V8AON_PVCC

P3V8AON_DRVL1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

SBR1A30T5

371S00245

3V8_EXT_DIODE

1

C5800

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

P3V8AON_VSW1 PP3V8AON_PH1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

116S0007

1

R5809

1.5

5%
1/16W
MF-LF
402

2

P3V8AON_SNUB1

SWITCH_NODE=TRUE
DIDT=TRUE

CRITICAL

C5801

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

CRITICAL

1

C5800

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D12

1

2

NOSTUFF

C5814

220PF

5%
50V
C0G
0201-1

CRITICAL

1

C5801

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D12

1UH-20%-11A-0.0127OHM

NO_XNET_CONNECTION=1

1

C5810

5600PF

10%
10V

2

CERM-X7R
0201

132S0370

CRITICAL

1

C5800

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

CRITICAL

L5800

PIHA052D-SM

152S00265

R5801

2 1

118S0744

R5802

131S0514

1

C5809

150PF

5%
50V

2

C0G-CERM
0402

<RDAR://59524111>

25

OUT

P3V8AON_ISEN1_P

NOSTUFF

1

C5815

220PF

5%
50V

2

C0G
0201-1

118S0744

CRITICAL

1

C5801

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

21

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=5V

1.00

1%
1/20W
MF-LF

0201

1.00

1%
1/20W
MF-LF

0201

P3V8AON_ISNS1_P

21

P3V8AON_ISNS1_N

1

C5804

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

MIRROR_WITH=C5804

1

C5805

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

107S00373

R5800

0.004

1%

1/3W

LF

0306

NO_XNET_CONNECTION=1

21
43

27

ICCMAX = 30 A

PP3V8_AON_VDDMAIN

CRITICAL

1

C5890

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

MIRROR_WITH=C5887

1

C5886

2.2UF

20%
25V

2

27

X6S-CERM
0402

CRITICAL

1

C5891

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

1

C5887

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042138S00042

CRITICAL

1

C5892

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

MIRROR_WITH=C5889

1

C5888

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

1

C5893

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

1

C5889

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

1

C5894

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

CRITICAL

1

C5895

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

79

79 26 25

25

OUT

P3V8AON_ISEN1_N

PPBUS_AON

CRITICAL

1

C5820

ALLOW_APPLE_PREFIX=Q

R5824

1.5

5%

1/8W

TK

0402

21

25

IN

P3V8AON_DRVH2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_DRVH2_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

Q5820

AONE36196

DFN

376S00281

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

CRITICAL

1

C5821

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

CRITICAL

1

C5820

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D12

107S00371

8

D1

R5823

0

25

OUT

P3V8AON_BST2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

1/16W

MTL-FILM

21

0%

0402

116S00006

P3V8AON_BST2_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

C5831

0.22UF

21

10%
25V
X7R

0402

132S0401

P3V8AON_SW2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

25 26 83

OUT

1

G1

2
3

D2/S1

4

NOSTUFF

D5820

SOD523

0.100

1%

1/4W

MF

0402

KA

R5826

21

P3V8AON_DRVL2_R

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

0.100

1%

1/4W

MF

0402

104S0050

21

P3V8AON_DRVL2_RR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

VER-1

2526

P3V8AON_PVCC

SBR1A30T5

371S00245

3V8_EXT_DIODE

R5825

25

IN

25

OUT

25

OUT

P3V8AON_DRVL2

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_ISEN2_P
P3V8AON_ISEN2_N

104S0050

D1

G2

9

SAME SW NET
ON BOTH SIDES

252683

IN

7

P3V8AON_SW2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

1

R5829

2.2

5%
1/16W
MF-LF
402

2

NOSTUFF

DIDT=TRUE
SWITCH_NODE=TRUE

P3V8AON_SNUB2

1

C5829

100PF

5%
50V

2

C0G
0402

NOSTUFF

CRITICAL

1

C5820

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

NOSTUFF

1

C5834

220PF

5%
50V

2

C0G
0201-1

NOSTUFF

1

C5835

220PF

5%
50V

2

C0G
0201-1

MIRROR_WITH=C5824

1

C5824

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

1

C5825

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

L5820

0.56UH-20%-22.0A-0.0067OHM

21

PP3V8AON_PH2

83

PILA062D-SM-COMBO

152S01248

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=5V

R5821

2 1

NO_XNET_CONNECTION=1

1

C5830

5600PF

10%
10V

2

CERM-X7R
0201

132S0370

118S0744

R5822

118S0744

1.00

1%
1/20W
MF-LF

0201

1.00

1%
1/20W
MF-LF

0201

P3V8AON_ISNS2_P

21

P3V8AON_ISNS2_N

107S00090

R5820

0.001

1%

1/3W

MF

0306

NO_XNET_CONNECTION=1

21
43

27

27

79 26 25

PPBUS_AON

CRITICAL

ALLOW_APPLE_PREFIX=Q

R5844

1.5

5%

1/8W

TK

0402

21

25

IN

P3V8AON_DRVH3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_DRVH3_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

Q5840 2

AONE36196

DFN

376S00281

107S00371

8

D1

9

R5843

0

25

OUT

P3V8AON_BST3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

1

0%

1/16W

MTL-FILM

0402

116S00006

P3V8AON_BST3_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

C5851

0.22UF

21

10%
25V
X7R

0402

132S0401

P3V8AON_SW3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

25 26 83

OUT

1

G1

2
3

D2/S1

4

D1

NOSTUFF

D5840

SOD523

0.100

1%

1/4W

MF

0402

KA

G2

7

R5846

21

P3V8AON_DRVL3_R

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

0.100

1%

1/4W

MF

0402

104S0050

21

P3V8AON_DRVL3_RR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

VER-1

2526

P3V8AON_PVCC

SBR1A30T5

371S00245

3V8_EXT_DIODE

R5845

25

IN

25

OUT

25

OUT

P3V8AON_DRVL3

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_ISEN3_P
P3V8AON_ISEN3_N

104S0050

1

C5840

33UF

20%
16V
TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

252683

IN

SAME SW NET
ON BOTH SIDES

P3V8AON_SW3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

1

R5849

2.2

5%
1/16W
MF-LF
402

2

P3V8AON_SNUB3

1

C5849

100PF

5%
50V

2

C0G
0402

CRITICAL

1

C5841

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12 3V8_AON_PBUS-D12

NOSTUFF

DIDT=TRUE
SWITCH_NODE=TRUE

NOSTUFF

CRITICAL

1

C5840

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE

CRITICAL

1

C5840

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

NOSTUFF

1

C5854

220PF

5%
50V

2

C0G
0201-1

NOSTUFF

1

C5855

220PF

5%
50V

2

C0G
0201-1

MIRROR_WITH=C5844

1

C5844

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

1

C5845

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

L5840

0.56UH-20%-22.0A-0.0067OHM

21

PP3V8AON_PH3

83

PILA062D-SM-COMBO

152S01248

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=5V

R5841

2 1

NO_XNET_CONNECTION=1

1

C5850

5600PF

10%
10V

2

CERM-X7R
0201

132S0370

118S0744

R5842

118S0744

1.00

1%
1/20W
MF-LF

0201

1.00

1%
1/20W
MF-LF

0201

P3V8AON_ISNS3_P

21

P3V8AON_ISNS3_N

107S00090

R5840

0.001

1%

1/3W

MF

0306

NO_XNET_CONNECTION=1

21
43

27

NO_XNET_CONNECTION=1

XW5870

2 1

SM

NO_XNET_CONNECTION=1

P3V8AON_VSNS_XW_P

27

XW5871

2 1

SM

27

P3V8AON_VSNS_XW_N

BOM_COST_GROUP=PLATFORM POWER

NO_XNET_CONNECTION=1

R5870

0

21

5%

1/20W

MF

0201

117S0201

NO_XNET_CONNECTION=1

R5871

0

21

5%

1/20W

MF

0201

NOSTUFF

1

C5870

1UF

20%
10V

2

X6S-CERM
0201

138S00044

NO_XNET_CONNECTION=1

P3V8AON_VSENSE

P3V8AON_VRTN

OUT

OUT

25 27

25

117S0201

SYNC_MASTER=ref_vr_iceman SYNC_DATE=04/20/2020

PAGE TITLE

POWER: 3V8 AON (2/2)

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

58 OF 801

SHEET

26 OF 92

PP5V_S2 to PP3V8_AON VDRV Connection

R5900

0

79

PP5V_S2

5%
1/16W
MF-LF

402

21

PP5V_S2_P3V8AON_VDRV

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

PP5V_S2_P3V8AON_VDRV

CBA PPBUS_AON Bulk CapacitancePP3V8_AON Probe Points

PPBUS_AON

998-0955

25

PP5900

SM

PP

1

P4MM

P3V8AON_DRVH1_R

26

PP5901

P4MM

SM

PP

1

P3V8AON_SW1

25 26

PP5902

P4MM

SM

PP

1

GND

PP5903

SM

PP

1

P4MM

PP5904

SM

PP

1

P4MM

PP5905

SM

PP

1

P4MM

P3V8AON_DRVL1_R

P3V8AON_PWR_EN_R

P3V8AON_FAULT_L

26

25

25

PP5906

SM

PP

1

P4MM

PP5907

SM

PP

1

P4MM

PP5908

SM

PP

1

P4MM

P3V8AON_LPM_R

P3V8AON_VSNS_XW_P

P3V8AON_VSENSE

25

26

25 26

79

NOSTUFFNOSTUFFNOSTUFFNOSTUFFNOSTUFF

1

C5960

68UF 68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C5961

2

20%
16V
POLY-TANT
CASE-D2E-SM

1

C5962

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C5963

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C5964

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

D

PP3V8_AON Current Sense

NO_XNET_CONNECTION=1

26

IN

26

IN

26

IN

26

IN

26

IN

26

IN

P3V8AON_ISNS3_P

P3V8AON_ISNS2_P

P3V8AON_ISNS1_P

P3V8AON_ISNS1_N

P3V8AON_ISNS2_N

P3V8AON_ISNS3_N

R5924

NO_XNET_CONNECTION=1

R5922

NO_XNET_CONNECTION=1

R5920

NO_XNET_CONNECTION=1

R5921

NO_XNET_CONNECTION=1

R5923

NO_XNET_CONNECTION=1

R5925

1/20W 0.1%

0.1% MF-LF1/20W 0201

118S0714

0.1%1/20W 0201

118S0714

0.1% 0201MF 103S03171/20W

0.1%

103S0317

0.1%1/20W

118S0714

118S0714

21

5K

21

5K

MF-LF

21

20K

21

20K

MF1/20W

21

5K

21

5K

MF-LF 0201

P3V8AON_ISNSP

0201

0201MF-LF

117S0201

R5912

R5913

5%1/20W MF 0201

117S0201

P3V8AON_ISNS_SH

79 27

21

0

MF1/20W 5%

21

0

27

P3V8AON_ISNS_RP

0201

P3V8AON_ISNS_RNP3V8AON_ISNSN

1

R5914

324K

0.1%
1/20W
MF
0201

2

103S00053

1

R5916

0

5%
1/20W
MF
0201

2

117S0201

PP3V8_AON_VDDMAIN

1

+

3

-

R5911

0.1%

1/20W

103S00053

NO_XNET_CONNECTION=1

21

324K

353S1429

U5910

OPA333DCKG4

5

SC70-5-COMBO

V+

V-

2

P3V8AON_ISNS_FB

MF

0201

1

2

P3V8AON_ISUM_IOUT

R5917

5%

1/20W 0201

0

117S0201

BYPASS=U5910.5::5MM

C5910

1UF

20%
10V
X6S-CERM
0201

138S00044

21

MF

PLACE_NEAR=U8100.E14:5MM

118S0385

R5915

1

R5910

100K

5%
1/20W
MF
201

2

117S0008

1% MF1/20W

21

45.3K

201

NOSTUFF

1

R5918

3.32M

1%
1/20W
MF-LF
0201

2

118S0759

P3V8AON_IMEAS

1

C5915

2.2UF

20%
10V

2

X5R
0201

138S00136

VSS_SENSOR_MPMU

47

OUT

4744

E

LTSpice:

344044

PP3V8_AON Current Sense Cal Control Circuit

PP3V8_AON_VDDMAIN

79 27

IN

SENSOR_PWR_EN

1/20W MF5%

R5930

0

21

SENSOR_PWR_EN_R

0201

376S0855

DMN5L06VK-7

Q5930

SOT563

VER-3

2

SENSOR_PWR_EN_CAL

6

D

SG

1

117S0008

R5931

100K

5%

1/20W

MF

201

1

2

DMN5L06VK-7

NOSTUFF

1

C5930

47PF

5%
25V

2

C0G
0201

131S0806

P3V8AON_ISNS_RP

27

376S0855

Q5930

SOT563

VER-3

5

PLACE_NEAR=R5912.2:5MM

NOSTUFF

118S0176

R5932

P3V8AON_ISNS_CAL

3

D

SG

4

200K

1%

1/20W

MF

201

1

2

$X1757GHUB/mlb/sim/ltspice/pp3v8_aon_vddmain/pp3v8_aon_vddmain_current_sense.asc

BOM_COST_GROUP=PLATFORM POWER

PAGE TITLE

POWER: 3V8 AON SUPPORT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/11/2019SYNC_MASTER=T585_REF_VR_ICEMAN_0.36.0

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

59 OF 801

SHEET

27 OF 92

SIZE

D

2

1

SLAVE PMU BUCKS

PP3V8_AON_VDDMAIN

29 28

79

1

C7700

10UF

20%

6.3V

2

0402 0402 0402 0402

1

C770A

1UF

10V

2

X6S-CERM

1

C7701

10UF

20%

6.3V

2

1

C770B

1UF

10V

2

X6S-CERM

1

C7702

10UF

20%

6.3V

2

CER-X6S
0402

1

C770C

1UF

10V

2

X6S-CERM

1

C770K

1UF

20%
10V

2

X6S-CERM

1

C7703

10UF

20%

6.3V

2

1

C770D

1UF

20%
10V

2

X6S-CERM

PLACE_NEAR=U7700.L1:5MM

1

C770L

10V 25V

2

X6S-CERM
02010201

1

C7704

10UF

20%

6.3V

2

0402

1

C770E

1UF

20% 20%20%20%20%20%20%20%20%
10V

2

X6S-CERM
0201 020102010201020102010201020102010201

PLACE_NEAR=U7700.L1:5MM

1

C770M

12PF

5%20%
25V

2

NP0-C0G
0201

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C7705

10UF

20%

6.3V

2

CER-X6SCER-X6SCER-X6SCER-X6SCER-X6S

1

C770F

1UF

10V

2

X6S-CERM

PLACE_NEAR=U7700.C13:5MM

1

C770N

3PF

+/-0.1PF 5%
25V

2

C0G
0201

1

C7706

1UF

10V

2

X6S-CERM
0201

1

C770G

1UF

10V

2

X6S-CERM

PLACE_NEAR=U7700.C13:5MM

1

C771M

12PF

25V

2

NP0-C0G
0201

1

C7707

1UF

10V

2

X6S-CERM
0201 0201

1

C770H

1UF

10V

2

X6S-CERM

1

C771N

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7708

1UF

20%20%20%

2

X6S-CERM

1

C770I

1

2

1

1UF

10V

2

X6S-CERM

PLACE_NEAR=U7700.G13:5MM

PLACE_NEAR=U7700.G13:5MM

1

C772M

12PF1UF

5%

2

NP0-C0G
0201

2

1

2

C7709

1UF

20%
10V10V
X6S-CERM
0201

C770J

1UF

10V
X6S-CERM

C772N

3PF

+/-0.1PF
25V
C0G
0201

C13

VDD_BUCK5_4_10

C14

VDD_BUCK5_4_10

G13

VDD_BUCK5_4_10

G14

VDD_BUCK5_4_10

M2

VDD_BUCK6

N2

VDD_BUCK6

P2

VDD_BUCK6

N6

VDD_BUCK12

P6

VDD_BUCK12

L13

VDD_BUCK13

L14

VDD_BUCK13

L1

VDD_MAIN_BUCK6

U7700

SIM

BGA

SYM 1 OF 4

OMIT_TABLE

BUCK4_LX0

BUCK4_LX1
BUCK4_LX1

BUCK4_FB

BUCK4_VSS_FB

BUCK5_LX_0
BUCK5_LX_1

BUCK5_FB

BUCK5_VSS_FB

F14

D13
D14

F11

PLACE_NEAR=U7700.F11:5MM

F12

H13
H14

H11

H12

31

SWITCH_NODE=TRUE

31

SWITCH_NODE=TRUE

BUCK4_FB

31

BUCK5_FB

PLACE_NEAR=U7700.H12:5MM

BUCK4_LX0

DIDT=TRUE

BUCK4_LX1

DIDT=TRUE

R770A

5%

VSS_ANA_SPMU

BUCK5_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

R770B

1/20W MF

5%

0

MF1/20W

0

CRITICAL

L7740

1.0UH-20%-4A-0.038OHM

PIKA20161B-COMBO

CRITICAL

L7741

0.22UH-20%-6.7A-0.023OHM

PINA20121T-SM

21

BUCK4_FB_R

0201

313028

CRITICAL

L7750

NO_XNET_CONNECTION=1

0.47UH-20%-4A-0.027OHM

2012

XW7701

SHORT-14L-0.1MM-SM

21

BUCK5_FB_R

0201

NO_XNET_CONNECTION=1

21

21

XW7700

SHORT-14L-0.1MM-SM

21

21

21

CRITICAL

CRITICAL

1

C7750

15UF

20%
2V

2

X6S
0402

CRITICAL

1

C7740

15UF

20%
2V

2

X6S
0402

1

C7713

15UF

20%
2V

2

X6S
0402

1

C7751

15UF

20%
2V

2

X6S
0402 0402

1

C7741

15UF

20%

2

X6S
0402

1

C7712

15UF

20%
2V

2

X6S
0402

1

C7752

15UF

20%
2V

2

CRITICAL CRITICAL

1

C7742

15UF

20%
2V

2

X6S
0402

1

2

CRITICALCRITICALCRITICALCRITICAL

1

C7711

15UF

20%
2V

2

X6S
0402

1

C7753

15UF

20%
2V

2

X6S
0402

1

2

1

C7754

15UF

20%
2V

2

0402

C7743

15UF 15UF

20%
2V
X6S
0402

C7710

15UF

20%
2V
X6S
0402

1

C7744

20%
2V

2

X6S
0402

PLACE_NEAR=L7740.2:5MM

1

C777M

12PF

5%
25V

2

NP0-C0G
0201

1

C7755

15UF

20%
2V

2

X6SX6SX6S
0402

1

C7745

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L7741.2:5MM

1

C777N

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7756

15UF

20%
2V

2

X6S
0402

PP1V06_S2SW_DRAM

CRITICAL

1

C7746

15UF

20%
2V2V

2

X6S
0402

PP0V764_S1_SRAM

PLACE_NEAR=L7750.2:5MM

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C7757

15UF

20%
2V

2

X6S
0402

1

C778M

12PF

5%
25V

2

NP0-C0G
0201

CRITICALCRITICALCRITICALCRITICAL

1

C7747

15UF

20%
2V

2

X6S
0402

1

C778N

3PF

+/-0.1PF
25V

2

C0G
0201

78

78

PLACE_NEAR=U7700.M2:5MM

PLACE_NEAR=U7700.M2:5MM

1

C773M

12PF

5%
25V 25V25V

2

NP0-C0G
0201

FED BY SPMU BUCK13 (1.2V)POWER ALIAS=>

FED BY MPMU BUCK3 (1.8V)POWER ALIAS=>

1

C773N

3PF

+/-0.1PF
25V

2

C0G
0201

PLACE_NEAR=U7700.N6:5MM

PLACE_NEAR=U7700.N6:5MM

1

C774M

1

12PF

2

NP0-C0G

PLACE_NEAR=U7700.D4:5MM

2

29

PLACE_NEAR=U7700.G10:5MM

PLACE_NEAR=U7700.L13:5MM

PLACE_NEAR=U7700.L13:5MM

1

C774N

3PF

+/-0.1PF
25V
C0G
0201

C775M

12PF

5%5%

2

NP0-C0G
02010201

PP1V5_VLDOINT_SPMU

29

79 29 28

PP5V_BSTLQ_SPMU

VOLTAGE=5V

PP1V25_S2

78

PP1V8_S2

78

PLACE_NEAR=U7700.D9:5MM

1

C775N

3PF

+/-0.1PF
25V

2

C0G
0201

1

2

PP3V8_AON_VDDMAIN

CRITICALCRITICAL CRITICAL

1

C7717

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U7700.L7:5MM

1

2

CRITICAL

1

C7716

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U7700.D9:5MM

31 30 28

1

C776N

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7715

0.1UF

10%
10V

2

X6S-CERM
0201

VSS_ANA_SPMU

C776M

12PF

5%
25V
NP0-C0G
0201

PLACE_NEAR=U7700.C9:5MM

C7714

0.1UF

10%
10V
X6S-CERM
0201

CRITICAL

1

C771A

0.1UF

10%
10V

2

X6S-CERM
0201

L9

E8

D2
E2

D8

E10

C12

D3
E7

G12

K3
L8

L12

M6

D5

D10

J3

J10

D9

B2
C2

E9

D4
L4

L7
M10
J11
A11

C9

G10

H10

K6

PLACE_NEAR=U7700.H10:5MM

VDD_MAIN_SOUTH

VDD_MAIN

VDD_MAIN_LDO
VDD_MAIN_LDO

VDD_MAIN_SNS

VDD_SNS_SPARE

VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA

VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG

VDD_BOOST

VDD_BOOST_LDO
VDD_BOOST_LDO

VDD_BOOST_SNS

VDD_HI_INT1
VDD_HI_INT2
VDD_HI_INT3
VDD_HI_INT4
VDD_HI_INT5
VDD_HI_INT6
VDD_HI_INT7

VDDIO_1V2

VDDIO_BUCK3

VPP

BUCK6_LX_0
BUCK6_LX_1
BUCK6_LX_2

BUCK6_FB

BUCK6_VSS_FB

BUCK6_VOUT_0
BUCK6_VOUT_1
BUCK6_VOUT_2

BUCK10_LX_0
BUCK10_LX_1

BUCK10_FB

BUCK10_VSS_FB

BUCK12_LX_0
BUCK12_LX_1

BUCK12_FB

BUCK12_VSS_FB

BUCK13_LX_0
BUCK13_LX_1

BUCK13_FB

BUCK13_VSS_FB

M3
N3

P3

L3

K2

M1
N1
P1

B13
B14

B11

B12

N5
P5

L5

M5

K13
K14

K11

K12

31

BUCK6_FB

31

BUCK10_FB

PLACE_NEAR=U7700.B11:5MM

31

BUCK12_FB

PLACE_NEAR=U7700.L5:5MM

31

BUCK13_FB

PLACE_NEAR=U7700.K11:5MM

VSS_ANA_SPMU

BUCK6_LX0

R770C

1/20W

PLACE_NEAR=U7700.L3:5MM

5%

VSS_ANA_SPMU

PP2V5_AWAKE_NAND

BUCK10_LX0

DIDT=TRUE

SWITCH_NODE=TRUE

R770D

5%

VSS_ANA_SPMU

BUCK12_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

R770E

1/20W0MF

5%

VSS_ANA_SPMU

0.47UH-20%-4A-0.027OHM

BUCK13_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

R770F

1/20W

VSS_ANA_SPMU

313028

DIDT=TRUE

SWITCH_NODE=TRUE

0

21

BUCK6_FB_R

MF

0201

313028

0.47UH-20%-4A-0.027OHM

0

21

BUCK10_FB_R

MF1/20W

0201

313028

21

BUCK12_FB_R

0201

313028

L77D0

2012

0

21

BUCK13_FB_R

MF5% 0201

313028

CRITICAL

L7760

0.47UH-20%-6.9A-0.022OHM

21

PIUA25201B-SM

XW7760

SHORT-14L-0.1MM-SM

21

NO_XNET_CONNECTION=1

7828

CRITICAL

L77A0

21

2012

XW77A0

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

L77C0

0.47UH-20%-4A-0.027OHM

CRITICAL

XW77C0

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

CRITICAL

21

XW77D0

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

2012

21

PLACE_NEAR=L7750.2:5MM

PP2V5_AWAKE_NAND 7828

CRITICALCRITICAL

1

C7760

10UF

20%

6.3V

2

CER-X6S
0402

1

C7761

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1

C7766

10UF 10UF

20%

6.3V

2

CER-X6S
0402

1

C7767

20%

6.3V

2

CER-X6S
0402

1

C7768

20%

6.3V

2

CER-X6S
0402

CRITICAL CRITICAL CRITICAL

1

C7762

10UF

20%

6.3V

2

CER-X6S
0402

1

C7769

20%

6.3V

2

CER-X6S
0402

1

C7763

10UF

20%

6.3V

2

CER-X6S
0402

1

C776A

20%

6.3V

2

CER-X6S
0402

1

C7764

10UF

20%

6.3V

2

CER-X6S
0402

1

C776B

10UF10UF 10UF 10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL CRITICAL

1

C7765

10UF

20%

6.3V

2

CER-X6S
0402

1

C776E

10UF

20%

6.3V

2

CER-X6S
0402

1

C776C

10UF

20%

6.3V

2

0402

PLACE_NEAR=L7760.2:5MM

1

C776F

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C776D

10UF

20%

6.3V

2

CER-X6SCER-X6S
0402

PLACE_NEAR=L7760.2:5MM

1

C779M

12PF

5%
25V

2

NP0-C0G
0201

1

C779N

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICAL CRITICAL

PP0V6_S1_VDDQL

PLACE_NEAR=L77A0.2:5MM

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C77A0

15UF

20%
2V

2

21

21

21

X6S
0402

CRITICAL CRITICAL

1

C77C0

15UF

20%
2V

2

X6S X6SX6S X6SX6S
0402

PLACE_NEAR=L77C0.2:5MM

1

C77A1

20%
2V

2

X6S
0402

CRITICAL

NOSTUFF

1

C77C1

15UF

20%
2V

2

0402

PLACE_NEAR=L77C0.2:5MM

1

C7792

12PF

5%
25V

2

NP0-C0G
0201

1

C77A2

15UF15UF

20%
2V

2

X6S
0402

CRITICAL

1

C77C2

15UF

20%
2V

2

0402

1

C7793

3PF

+/-0.1PF
25V

2

C0G
0201

1

C77A3

15UF

20%
2V

2

X6S
0402

CRITICAL

NOSTUFF

1

C77C3

15UF

20%
2V

2

1

C7723

15UF

20%
2V

2

X6S
0402

1

C7719

15UF

20%
2V

2

04020402

1

C7722

15UF

20%
2V

2

X6S
0402

CRITICAL

1

C7718

15UF

20%
2V

2

X6S X6S X6S

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C77D6

15UF

20%
2V

2

X6S
0402

1

C77D3

15UF

20%
2V

2

X6S
0402

1

C77D4

15UF

20%

2

X6S
0402

1

C77D5

15UF

20%
2V2V

2

X6S
0402

1

C77D7

15UF

20%
2V

2

X6S
0402

1

C77D8

15UF

20%
2V

2

X6S
0402

1

C7794

12PF

5%
25V

2

NP0-C0G
0201 0201

PLACE_NEAR=L77D0.2:5MM

PLACE_NEAR=L77A0.2:5MM

1

C7790

12PF

5%
25V

2

NP0-C0G
0201

PP0V88_S1

1

C7721

15UF

20%
2V

2

CRITICAL

PP1V25_S2

1

C7791

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7720

15UF

20%

CRITICAL

2V

2

040204020402

1

C7795

3PF

+/-0.1PF
25V

2

C0G

PLACE_NEAR=L77D0.2:5MM

78

78

B

78

BOM_COST_GROUP=PLATFORM POWER

SYNC_DATE=04/28/2020SYNC_MASTER=ref_pmu_sera_simetra

PAGE TITLE

PMU: SLAVE INPUT PWR & BUCKS

SIZEDRAWING NUMBER

SLAVE PMU LDO

LDO INPUTS

FROM BUCK13 POWER ALIAS =>
OR OPTION BUCK14

FROM BUCK13 POWER ALIAS =>
OR OPTION BUCK14

FROM BUCK4 POWER ALIAS =>

PP1V25_S2

78

PPVDD_PMU_LDO_PREREG

35 29

PP1V06_S2SW_DRAM

78

M7

C4

N7

VDD_LDO4

VDD_LDO8

VDD_LDO11

U7700

SIM

BGA

SYM 2 OF 4

OMIT_TABLE

VLDO11

VLDO4

VLDO6

VLDO8

VLDO9

M8

D1

C3

E3

N8

PP0V72_S2_VDD_LOW

NC_SPMU_VLDO6
PP1V2_AWAKE_PLL

CAP_PPSPMU_VLDO9

PP0V855_S2SW_CIO

LDO OUTPUTS

7829

31

7829

3129

7829

PLACE_NEAR=U7700.B3:5MM

FROM BUCK3 POWER ALIAS =>
FROM BUCK13 POWER ALIAS =>

FROM BUCK12 POWER ALIAS =>

DECOUPLING : VDD_LDO8

PPVDD_PMU_LDO_PREREG

PLACE_NEAR=U7700.C4:5MM

CRITICAL

1

C7813

10UF

20%

6.3V
CER-X6S
0402

DECOUPLING : LDO20

PP1V2_S2_CIO

NOSTUFF
CRITICAL

1

C7804

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C780A

10UF

20%

6.3V

2

CER-X6S
0402

PP1V8_S2

78

PP1V25_S2

78 30

PP0V88_S1

78 29

3529

7829

PLACE_NEAR=U7700.B3:5MM

PLACE_NEAR=U7700.C3:5MM PLACE_NEAR=U7700.C3:5MM

FROM BUCK12 POWER ALIAS =>

CRITICAL

1

C7810

10UF

20%

6.3V

2

CER-X6S
0402

DECOUPLING : VDD_LDO20

PPVDD_PMU_LDO_PREREG

PLACE_NEAR=U7700.B4:5MM

CRITICAL

1

C78142

10UF

20%

6.3V

2

CER-X6S
0402

DECOUPLING : LDO8

PP1V2_AWAKE_PLL

CRITICAL

1

C7805

10UF

20%

6.3V

2

CER-X6S
0402

FROM BUCK13 POWER ALIAS =>
OR OPTION BUCK14

CRITICAL

1

C7811

10UF

20%

6.3V

2

CER-X6S
0402

3529

CRITICAL

1

C7806

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7812

10UF

20%

6.3V

2

CER-X6S

0402

PP1V5_VLDOINT_SPMU

28

78 29

79 29 28

35 29

79 29 28

THIS IS AN OUTPUT(1.5V) =>

VOLTAGE=1.5V

7829

PP0V88_S1

PP3V8_AON_VDDMAIN

PPVDD_PMU_LDO_PREREG

PP3V8_AON_VDDMAIN

1

C7807

220PF

10%
16V

2

CER-X7R
0201

1

C7808

220PF

10%
16V

2

CER-X7R
0201

M11
M13
N13
P13
N11
P11

CRITICAL

1

C7823

10UF

20%

6.3V

2

CER-X6S
0402

P7

VDD_LDO12

A1

VDD_LDO15

A2

VDD_LDO15

B4

VDD_LDO20

VDD_SW4
VDD_SW5
VDD_SW5
VDD_SW5
VDD_SW6
VDD_SW6

N9

VDD_SW7

P9

VDD_SW7

J2

VDD_MAIN_BSTLQ

E1

VLDOINT

CRITICAL

1

C7834

10UF

20%

6.3V

2

CER-X6S
0402

SWITCHED RAILS

VLDO12

VLDO15

VLDO17

VLDO18

VLDO20

BUCK_SW4
BUCK_SW5
BUCK_SW5
BUCK_SW5
BUCK_SW6
BUCK_SW6
BUCK_SW7
BUCK_SW7

BSTLQ_LX
BSTLQ_FB

BSTLQ_VOUT

VCP_OUT_SPARE

VMBX_SPARE

P8

A3

B1

C1

B3

M12
M14
N14
P14
N12
P12
N10
P10

G1
J1
H1

M9

F10

PP0V805_S1_VDD_FIXED

NC_SPMU_VLDO15

NC_SPMU_VLDO17

NC_SPMU_VLDO18

PP1V2_S2_CIO

PP1V8_AWAKE_SPMU_GPIO

PP1V25_AWAKE_NAND

PP0V88_AWAKE_NAND

SPMU_BSTLQ_LX

28

PP5V_BSTLQ_SPMU

VOLTAGE=5V

NO_TEST=1

NC_SPMU_VCP_OUT_SPARE
NC_SPMU_VMBX_SPARE

NO_TEST=1

PLACE_NEAR=U7700.J1:5MM

7829

31

31

31

7829

7829

7829

SWITCH_NODE=TRUE

DIDT=TRUE

PLACE_NEAR=U7700.H1:5MM

1

C7892

12PF

5%
25V

2

NP0-C0G
0201

CRITICAL

1

C7825

0.1UF

10%
10V

2

X6S-CERM
0201

VOLTAGE=1.8V

0.47UH-20%-1.7A-0.175OHM

XW78D0

SM

21

PLACE_NEAR=U7700.H1:5MM

1

C7893

3PF

+/-0.1PF
25V

2

C0G
0201

PLACE_NEAR=U7700.M12:5MM

1

C7822

1UF

20%

6.3V

2

X6S-CERM
0201

L7800

PIJT1005FE-SM-COMBO

CRITICAL

1

C7800

20UF

20%
10V

2

X5R
0402

DECOUPLING : BSTLQ

PLACE_NEAR=L7800.2:5MM

PLACE_NEAR=L7800.2:5MM

1

C7890

12PF

5%
25V

2

NP0-C0G
0201

1

2

21

CRITICAL

1

C7801

20%
10V

2

X5R
0402

1

2

<==BUCK4_SW USED FOR SPMU GPIO, INTERNALLY CONNECTED

PLACE_NEAR=U7700.M12:5MM

C7898

12PF

5%
25V
NP0-C0G
0201

1

C7899

3PF

+/-0.1PF
25V

2

C0G
0201

PP3V8_AON_VDDMAIN

PP5V_BSTLQ_VOUT_SPMU

CRITICAL

1

C7831

0.1UF20UF

10%
10V

2

X6S-CERM
0201

GND

PP3V8_AON_VDDMAIN

CRITICAL

C7891

3PF

+/-0.1PF
25V
C0G
0201

1

C7815

1UF

20%
10V

2

X6S-CERM

PLACE_NEAR=U7700.J2:5MM

VOLTAGE=5V

PLACE_NEAR=U7700.H1:5MM

CRITICAL

1

C7816

1UF

20%
10V

2

X6S-CERM
02010201

792928

3130

792928

PLACE_NEAR=U7700.J2:5MM

PLACE_NEAR=U7700.P8:5MM

PLACE_NEAR=U7700.E3:5MM

DECOUPLING : LDO12

PP0V805_S1_VDD_FIXED 7829

CRITICAL

1

C7821

10UF

20%

6.3V

2

CER-X6S
0402

DECOUPLING : LDO9

CRITICAL

1

C780B

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U7700.P8:5MM

CAP_PPSPMU_VLDO9

CRITICAL

1

C7824

1UF

20%
10V 10V

2

X6S-CERM
0201

CRITICAL

1

C7835

1UF

20%

2

X6S-CERM
0201

PLACE_NEAR=U7700.E3:5MM

PLACE_NEAR=U7700.N8:5MM

3129

PLACE_NEAR=U7700.M8:5MM

DECOUPLING : LDO11

PP0V855_S2SW_CIO

CRITICAL

1

C7809

10UF

20%

6.3V

2

CER-X6S
0402

DECOUPLING : LDO4

CRITICAL

1

2

PP0V72_S2_VDD_LOW

CRITICAL

1

C7820

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

2

7829

NOSTUFF

C780C

10UF

20%

6.3V
CER-X6S
0402

PLACE_NEAR=U7700.M8:5MM

PLACE_NEAR=U7700.N8:5MM

C780D

10UF

20%

6.3V
CER-X6S
0402

DECOUPLING : SW6/7

CRITICAL

1

C7830

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U7700.N12:5MM

1

2

CRITICAL CRITICAL

C7829

10UF

20%

6.3V
CER-X6S
0402

PLACE_NEAR=U7700.N12:5MMPLACE_NEAR=U7700.N12:5MM

1

C7828

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U7700.N12:5MM

PP0V88_AWAKE_NAND

PLACE_NEAR=U7700.N12:5MM

1

C7894

12PF

5%
25V

2

NP0-C0G
0201

1

C7895

3PF

+/-0.1PF
25V

2

C0G
0201

7829

SYNC_DATE=04/28/2020SYNC_MASTER=ref_pmu_sera_simetra

PAGE TITLE

PMU: SLAVE LDO

7829

PLACE_NEAR=U7700.M14:5MM

DECOUPLING : SW5

CRITICAL

1

C7802

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U7700.M14:5MM

PLACE_NEAR=U7700.M14:5MM

CRITICAL

1

C7803

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U7700.M14:5MM

1

C7896

12PF

5%
25V

2

NP0-C0G
0201

1

C7897

3PF

+/-0.1PF
25V

2

C0G
0201

PP1V25_AWAKE_NAND

7829

BOM_COST_GROUP=PLATFORM POWER

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

SLAVE PMU GND,ADC,& GPIO

48 31 30

VSS_ANA_SPMU

1

R7903

200K

0.1%

XW79D0

SHORT-14L-0.1MM-SM

2 1

PLACEMENT NOTE:

CONNECT VSS_REF THROUGH ALL GND PLANES PLACE XW AT VSS_REF PIN, ROUTE VSS_RTN
BACK FROM THE VREF / IREF PASSIVES

SPMU_VREF_IREF_RTN

1/20W

TF

0201

2

CRITICAL

R7940

3.92K

0.1%

0201-2

1/20W

VSS_ANA_SPMU

31

SPMU_IREF
SPMU_VREF

1

C7905

1.5UF

6.3V

2

CER-X5R
0201

2

MF

1

1

C7940

100PF

5%
25V

2

C0G
0201

30

30

NOSTUFF

1

C7906

0.1UF20%

10%

6.3V

2

CERM-X5R
0201

48 31 30

48

IN

48

IN

48

IN

48

IN

48

IN

31

IN

47

IN

47

IN

47

IN

47

IN

31

OUT

47

IN

47

IN

47

IN

47

IN

31

OUT

SPMU_VREF_ADC

C7985

0.1UF

10%

6.3V
CERM-X5R
0201

30

SPMU_IREF

30

SPMU_VREF

30

SPMU_VREF_ADC

1

2

VSS_ANA_SPMU

VSS_ANA_SPMU

SPMU_TCAL

NC_SPMU_TDEV1
SPMU_TDEV2
NC_SPMU_TDEV3
SPMU_TDEV4
SPMU_TDEV5

SPMU_ADC_IN

LCDBKLT_HS_ISENSE
KBDBKLT_5V_ISENSE
NC_SPMU_AMUX_A2
NC_SPMU_AMUX_A3

SPMU_AMUX_AY
NC_SPMU_AMUX_B0

NC_SPMU_AMUX_B1
WLANBT_3V3_ISENSE
NC_SPMU_AMUX_B3

SPMU_AMUX_BY

30

3130

OMIT_TABLE

D7

IREF

D6

VREF

C7

VREF_ADC

C6

VSS_REF

A7

TCAL

A6

TDEV1

A5

TDEV2

B8

TDEV3

B7

TDEV4

B6

TDEV5

E6

ADC_IN

B10

AMUX_A<0>

A10

AMUX_A<1>

A9

AMUX_A<2>

A8

AMUX_A<3>

C8

AMUX_AY

D11

AMUX_B<0>

E11

AMUX_B<1>

B9

AMUX_B<2>

C10

AMUX_B<3>

B5

AMUX_BY

TDEV

AMUX

U7700

SIM

BGA

SYM 3 OF 4

GPIO

SPMI

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

SPMI_SCLK

SPMI_SDATA

SGPIO_SCLK

SGPIO_SDATA

H7

NC_SPMU_GPIO1

K8

NC_SPMU_GPIO2

K7

SWD_NUB_PMU_SWDIO

J7

NC_SPMU_GPIO4

G7

NC_SPMU_GPIO5

F7

NC_SPMU_GPIO6

F6

NC_SPMU_GPIO7

H6

NC_SPMU_GPIO8

G6

NC_SPMU_GPIO9

J6

NC_SPMU_GPIO10

F5

NC_SPMU_GPIO11

H5

NC_SPMU_GPIO12

J5

NC_SPMU_GPIO13

G5

NC_SPMU_GPIO14

F4

NC_SPMU_GPIO15

F3

NC_SPMU_GPIO16

J9

SPMI_NUB_SPMU_CLK

H9

SPMI_NUB_SPMU_DATA

H3

SGPIO_SCLK

G3

SGPIO_SDATA

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN

IN

BI

BI

BI

31

31

10 34

31

31

31

31

31

31

31

31

31

31

31

31

31

20

20

34

34

RECOMMENDED TO HAVE PD ON UNUSED RESET_IN PIN

DFT_CTRL0=0 ==> DFT_CTRL1=SWDCLK

CAN DIRECTLY SHORT TO GND BUT PD HELPS
IF NEED TO OVERRIDE BY NOSTUFFING IT ==>

CAN LEAVE IT FLOATING AS OTP DISABLES IT AND
HAS IPD. PAD KEEPS PD ON DEV TO BE ABLE TO
OVERRIDE IT

31

31 30 28

1034

==>

R7902

10K

1/20W

U7700

SIM

SYM 4 OF 4

GND31 29

GND31

GND31

GND31

GND31

VSS_ANA_SPMU31

F1

VSS_BSTLQ

E13

VSS_BUCK4

E14

VSS_BUCK4

A13

VSS_BUCK10

A14

VSS_BUCK10

N4

VSS_BUCK12_6

P4

VSS_BUCK12_6

J13

VSS_BUCK13_5

J14

VSS_BUCK13_5

F8

VSS_DFT_2

OMIT_TABLE

BGA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A4
A12
C5
C11
D12
E4
E5
E12
F2
F13
G2
G11
H2
J12
K1
K4
K5
K10
L2
L6
L10
L11
M4

VSS_ANA_SPMU 3130
VSS_ANA_SPMU 313028
VSS_ANA_SPMU 3130
VSS_ANA_SPMU 313028

VSS_ANA_SPMU

VSS_ANA_SPMU 3130
VSS_ANA_SPMU

VSS_ANA_SPMU 3130
VSS_ANA_SPMU 313028
VSS_ANA_SPMU 3130
VSS_ANA_SPMU 313028
VSS_ANA_SPMU 3130
VSS_ANA_SPMU 313028

VSS_ANA_SPMU 313028
VSS_ANA_SPMU 313028

VSS_ANA_SPMU 313028

VSS_ANA_SPMU 313028
VSS_ANA_SPMU 313028

313028

313028

201

SPMU_RESET_IN

IN

VSS_ANA_SPMU

SWD_NUB_SWCLK

IN

SPMU_EXT32K_EN
NC_SPMU_EXT32K_IN

IN

FORCE_SYNC

1

1%
MF

2

R7920

10K

1/20W

201

PP1V25_S2
PP1V8_AON_MPMU

1

1%
MF

2

R7900

R7901

1/20W5% 201

1/20W MF5% 201

J4

H8
J8

F9

K9

G9

NOSTUFF

10K

10K

DFT_CTRL_0
DFT_CTRL_1

EXT32K_EN

EXT32K_IN

FORCE_SYNC

29

<== FROM BUCK13 POWER ALIAS

78
34

78

<== FROM LDO9 POWER ALIAS

21

PMU_SCRASH_L

MF

21

VDD_MAIN_PRE_UVLO_L

UVWARN*RESET_IN

SCRASH*

SGPIO_READY_REQ

G8

VDD_MAIN_PRE_UVLO_L

G4

PMU_SCRASH_L

H4

PMU_SGPIO_READY_REQ

<== SERA HAS IPU WHILE SIMETRA DOESN'T, WHICH IS GOOD!

30 34

30

30

30 34

BI

34

IN

BOM_COST_GROUP=PLATFORM POWER

PMU: SLAVE GPIO & GND

30 29

30 28

30 28

30 28

48 30

GND
GND

30

GND

30

GND

30

GND

30

VSS_ANA_SPMU

30

VSS_ANA_SPMU

30

VSS_ANA_SPMU
VSS_ANA_SPMU
VSS_ANA_SPMU
VSS_ANA_SPMU

30

VSS_ANA_SPMU
VSS_ANA_SPMU

30

VSS_ANA_SPMU

MAKE_BASE=TRUE

XW8000

SHORT-14L-0.1MM-SM

21

XW8001

SHORT-14L-0.1MM-SM

21

XW8002

SHORT-14L-0.1MM-SM

21

30

IN

30

IN

NC_SPMU_VLDO6

29

CAP_PPSPMU_VLDO9

29

NC_SPMU_VLDO15

29

NC_SPMU_VLDO17

29

NC_SPMU_VLDO18

29

NC_SPMU_EXT32K_IN

30

NC_SPMU_GPIO1

30

NC_SPMU_GPIO2

30

NC_SPMU_GPIO4

30

NC_SPMU_GPIO5

30

NC_SPMU_GPIO6

30

NC_SPMU_GPIO7

30

NC_SPMU_GPIO8

30

NC_SPMU_GPIO9

30

NC_SPMU_GPIO10

30

NC_SPMU_GPIO11

30

NC_SPMU_GPIO12

30

NC_SPMU_GPIO13

30

NC_SPMU_GPIO14

30

47

NC_SPMU_GPIO15

30

NC_SPMU_GPIO16

30

NC_SPMU_VLDO6

MAKE_BASE=TRUE

CAP_PPSPMU_VLDO9

MAKE_BASE=TRUE

NC_SPMU_VLDO15

MAKE_BASE=TRUE

NC_SPMU_VLDO17

MAKE_BASE=TRUE

NC_SPMU_VLDO18

MAKE_BASE=TRUE

NC_SPMU_EXT32K_IN

MAKE_BASE=TRUE

NC_SPMU_GPIO1

MAKE_BASE=TRUE

NC_SPMU_GPIO2

MAKE_BASE=TRUE

NC_SPMU_GPIO4

MAKE_BASE=TRUE

NC_SPMU_GPIO5

MAKE_BASE=TRUE

NC_SPMU_GPIO6

MAKE_BASE=TRUE

NC_SPMU_GPIO7

MAKE_BASE=TRUE

NC_SPMU_GPIO8

MAKE_BASE=TRUE

NC_SPMU_GPIO9

MAKE_BASE=TRUE

NC_SPMU_GPIO10

MAKE_BASE=TRUE

NC_SPMU_GPIO11

MAKE_BASE=TRUE

NC_SPMU_GPIO12

MAKE_BASE=TRUE

NC_SPMU_GPIO13

MAKE_BASE=TRUE

NC_SPMU_GPIO14

MAKE_BASE=TRUE

NC_SPMU_GPIO15

MAKE_BASE=TRUE

NC_SPMU_GPIO16

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

28

IN PP

28

IN PP

28

IN PP

28

IN PP

28

IN PP

28

IN PP

28

IN PP

29

IN PP

SPMU_AMUX_AY
SPMU_AMUX_BY

BUCK4_LX0
BUCK4_LX1
BUCK5_LX0
BUCK6_LX0
BUCK10_LX0
BUCK12_LX0
BUCK13_LX0
SPMU_BSTLQ_LX

1

TP
TP

TP-P4
TP-P4

P4MMSM
P4MMSM
P4MMSM
P4MMSM
P4MMSM
P4MMSM
P4MMSM
P4MMSM

1

1

1

1

1

1

1

1

1

TP8000
TP8001

PP8000
PP8001
PP8002
PP8003
PP8004
PP8005
PP8006
PP8007

XW8003

SHORT-14L-0.1MM-SM

21

XW8004

SHORT-14L-0.1MM-SM

21

XW8005

SHORT-14L-0.1MM-SM

21

XW8006

SHORT-14L-0.1MM-SM

21

XW8007

SHORT-14L-0.1MM-SM

21

PP2V5_AWAKE_NAND

7883

OMIT_TABLE OMIT_TABLE

1

C8022

1UF

10%
16V

2

CER-X6S
0402

1

C8025

1UF

10%
16V

2

CER-X6S
0402

NOSTUFF

1

C8020

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C8021

10UF

20%

6.3V

2

CER-X6S
0402

1

C8023

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFFNOSTUFF

1

C8024

10UF

20%

6.3V

2

CER-X6S
0402

1

R8000

100K

5%
1/20W
MF
201

2

1

R8001

1M

5%
1/20W
MF
201

2

SPMU_RESET_IN

SPMU_ADC_IN

OUT

OUT

NOSTUFF

1

C8027

10UF

20%

6.3V

2

CER-X6S
0402

PAGE TITLE

1

C8029

10UF

20%

6.3V

2

CER-X6S
0402

BOM OPTIONCRITICAL

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NOSTUFF

1

C8026

10UF

20%

6.3V

2

CER-X6S
0402

OMIT_TABLEOMIT_TABLE

1

C8028

1UF

10%
16V

2

CER-X6S
0402

138s00336 5 CAP,CER,1UF,10%,16V,X6S,MUR,0402 C5151,C8022,C8025,C8028,C8031

30

1

C8031

1UF

10%
16V

2

CER-X6S
0402

NOSTUFFNOSTUFF

1

C8030

10UF

20%

6.3V

2

CER-X6S
0402

TABLE_5_H EAD

TABLE_5_I TEM

PMU: Slave extra

DRAWING NUMBER

051-05392

Apple Inc.

REVISION

4.0.0

BOM_COST_GROUP=PLATFORM POWER

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

80 OF 801

MASTER PMU BUCKS

34 32
79 35

PP3V8_AON_VDDMAIN

1

C81F8

1

1UF

2

1

2

1

C81F6

1UF

20% 20%
10V

2

X6S-CERM
0201 0201

2

X6S-CERM X6S-CERM

1

C81F7

1UF

10V

2

X6S-CERM

CRITICAL

1

C81D0

10UF 10UF

20% 15UF

6.3V

2

CER-X6S
0402

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1

C81D9

1

2

CRITICAL

1

10UF

6.3V

2

CER-X6S
0402

PLACE_NEAR=U8100.B1:5MM

FROM BUCK13 POWER ALIAS =>
OPTION BUCK14

FED BY SPMU BUCK13 (1.2V)POWER ALIAS=>
FED BY MPMU BUCK3 (1.8V)POWER ALIAS=>

PLACE_NEAR=U8100.R16:5MM

2

PLACE_NEAR=U8100.L1:5MM

1

2

PLACE_NEAR=U8100.B1:5MM

1

C81FA

12PF

5% 5%
25V 25V25V

2

NP0-C0G NP0-C0GNP0-C0G
0201 020102010201

OMIT_TABLE

PPBUS_AON

79

103S00385

103S00480

103S00481

103S00385

1

RES,TK,887KOHM,0.1%,1/20W,0201

1

RES,MF,453KOHM,0.1,1/20W,0201

RES,MF,910KOHM,0.1,1/20W,0201

RES,MF,280KOHM,0.1,1/20W,0201103S00043

RES,TK,887KOHM,0.1%,1/20W,0201

1 CRITICAL

RES,MF,205KOHM,0.1%,1/20W,0201103S00086

C81F9

1UF

20%20%
10V

C81C6

1UF 1UF

20% 20% 20% 20% 20% 20%20%
10V 10V 10V 10V 10V10V
X6S-CERM
0201 0201 0201 0201 0201 02010201

1

C81E0

1UF

20%
10V10V

2

X6S-CERM
020102010201

1

C81C7

1UF

2

X6S-CERM

CRITICAL

1

C81D1

20% 20%

6.3V
CER-X6S
0402

C81D2

10UF

6.3V

2

CER-X6S
0402

CRITICAL

1

C81DA

10UF

20%

6.3V
CER-X6S
0402

PLACE_NEAR=U8100.L1:5MM

C81FJ

12PF

5%
25V
NP0-C0G
0201

C81DB

10UF

20%

6.3V

2

CER-X6S
0402

1

C81FK

3PF

+/-0.1PF
25V

2

C0G
0201

1

C81FB

3PF

+/-0.1PF
25V

2

C0G
0201

PLACE_NEAR=U8100.F1:5MM

1

C81E1

1UF

20%
10V

2

X6S-CERM
0201

1

C81C8

20%
10V

2

X6S-CERM
0201

1

C81D3

10UF

20%

6.3V

2

CER-X6S
0402

1

2

1

2

1

2

CRITICAL

1

C81DC

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U8100.R1:5MM

PLACE_NEAR=U8100.R1:5MM

1

C81FL

12PF

5%
25V

2

NP0-C0G
0201

PLACE_NEAR=U8100.F1:5MM

1

C81FC

1

2

1

2

1

12PF

2

25V
NP0-C0G

2

C81C0

1UF

20%
10V
X6S-CERM
0201

C81C9

1UF 1UF 1UF

X6S-CERM

CRITICALCRITICALCRITICAL

C81D4

10UF

20%

6.3V
CER-X6S
0402

1

C81C1

1UF 1UF

20%
10V

2

X6S-CERM
0201

1

C81CA

1UF

10V

2

X6S-CERM

CRITICAL

1

C81D5

10UF 20%

20%

6.3V

2

CER-X6S
0402

1

C81C2

20%
10V

2

X6S-CERM
0201

1

C81CB

1UF

2

X6S-CERM

CRITICAL

1

C81D6

10UF

6.3V

2

CER-X6S
0402

CRITICAL

1

C81DD

10UF

20%

6.3V
CER-X6S
0402

C81FM

3PF

+/-0.1PF
25V
C0G
0201

PLACE_NEAR=U8100.K1:5MM

C81FD

+/-0.1PF
25V
C0G
0201

PPVDD_PMU_LDO_PREREG

35

PP1V5_VLDOINT_MPMU

3334

C81F2

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U8100.W1:5MM

PLACE_NEAR=U8100.W1:5MM

1

C81FN

12PF

5%

2

NP0-C0G

1

C81FE

12PF

5%5%

2

1

C81F3

10UF

6.3V

2

CER-X6S
0402

1

C81FP

+/-0.1PF
25V

2

C0G
0201

1

C81FF

3PF3PF

+/-0.1PF
25V

2

C0G
0201

PMU_VDD_HI

32

PP1V25_S2
PP1V8_S2

CRITICAL

1

C8132

0.1UF

10%
10V

2

X6S-CERMX6S-CERM
0201

COINCELL BATTERY =>

PP3V8_AON_VDDMAIN

U8110

OPA333DCKG4

1

+

3

-

5

SC70-5-COMBO

V+

V-

2

PP3V8_AON_VDDMAIN

4

R8100

887K

0.1%

1/20W

TK

0201

1

2

21

MPMU_SNS_DIV

CRITICAL

C8131

0.1UF

10%
10V

0201

PLACE_NEAR=U8100.N16:5MM

79 35 34 32

1

R8101

453K

1%
1/20W
MF
201

2

OMIT_TABLE

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

R8100

R81001 PBUS_12VDCIN

R81011 CRITICAL

R8100 CRITICAL1

R8101

CRITICAL PBUS_3S

CRITICALR8101 PBUS_3S

CRITICAL

BOM OPTIONCRITICAL

PBUS_12VDCIN

PBUS_15P8VDCIN

PBUS_15P8VDCIN

1

C81C3

1UF

2

X6S-CERM

1

C81CC

2

X6S-CERM

CRITICAL

1

C81D7

10UF

20%

6.3V

2

CER-X6S
0402

1

C81F4

10UF

6.3V

2

CER-X6S
0402

PLACE_NEAR=U8100.Y7:5MM

PLACE_NEAR=U8100.Y7:5MM

1

C81FQ

12PF

5%
25V25V

2

NP0-C0G
02010201

PLACE_NEAR=U8100.A15:5MM

PLACE_NEAR=U8100.A15:5MMPLACE_NEAR=U8100.K1:5MM

1

C81FG

12PF

2

PLACE_NEAR=U8100.B15:5MM

PLACE_NEAR=U8100.B15:5MM

1

C81F0

12PF

5%
25V

2

NP0-C0G
0201

1

C8130

10UF

20%

6.3V

2

CER-X6S
0402

35 33 32

PLACE_NEAR=U8110.5:5MM

1

C8128

0.1UF

10%

6.3V

2

CERM-X5R
0201

VSS_ANA_MPMU

PMU_VDD_HI

TABLE_5_H EAD

TABLE_5_I TEM

<== FOR 3S BATTERY

TABLE_5_I TEM

TABLE_5_I TEM

<== FOR 12V DCIN

TABLE_5_I TEM

TABLE_5_I TEM

<== FOR 15.8V DCIN

TABLE_5_I TEM

1

C81C4

1UF

20%20%
10V10V

2

X6S-CERM
02010201

1

C81CD

2

X6S-CERM

CRITICAL

1

C81D8

10UF

20%

6.3V

2

CER-X6S
0402

1

C81F5

10UF

20%20%20%20%

6.3V

2

CER-X6S
0402

1

C81FR

3PF3PF

+/-0.1PF
25V

2

C0G
0201

1

C81FH

3PF

+/-0.1PF
25V

2

C0G
0201

1

C81F1

3PF

+/-0.1PF
25V

2

C0G
0201

32

OMIT_TABLE

L1

VDD_BUCK0_2_7_11

L2

VDD_BUCK0_2_7_11

L3

VDD_BUCK0_2_7_11

L4

VDD_BUCK0_2_7_11

R1

VDD_BUCK0_2_7_11

R2

VDD_BUCK0_2_7_11

R3

VDD_BUCK0_2_7_11

R4

VDD_BUCK0_2_7_11

W1

VDD_BUCK0_2_7_11

W2

VDD_BUCK0_2_7_11

W3

VDD_BUCK0_2_7_11

W4

VDD_BUCK0_2_7_11

W7

VDD_BUCK0_2_7_11

W11

VDD_BUCK0_2_7_11

W15

VDD_BUCK0_2_7_11

W19

VDD_BUCK0_2_7_11

Y7

VDD_BUCK0_2_7_11

Y11

VDD_BUCK0_2_7_11

Y15

VDD_BUCK0_2_7_11

Y19

VDD_BUCK0_2_7_11

A7

VDD_BUCK1_8_9

A11

VDD_BUCK1_8_9

B1

VDD_BUCK1_8_9

B2

VDD_BUCK1_8_9

B3

VDD_BUCK1_8_9

B4

VDD_BUCK1_8_9

B7

VDD_BUCK1_8_9

B11

VDD_BUCK1_8_9

F1

VDD_BUCK1_8_9

F2

VDD_BUCK1_8_9

F3

VDD_BUCK1_8_9

F4

VDD_BUCK1_8_9

K1

VDD_BUCK1_8_9

K2

VDD_BUCK1_8_9

K3

VDD_BUCK1_8_9

K4

VDD_BUCK1_8_9

A15

VDD_BUCK3_14

B15

VDD_BUCK3_14

K19

VDD_LDO2

L20

VDD_LDO3_14

K21

VDD_LDO5

J19

VDD_LDO19

C18

VDD_MAIN_WBOOST

F20

VDD_MAIN_WBOOST

F15

VDD_MAIN_WIDAC

K11

VDD_MAIN

V17

VDD_MAIN1

E19

VDD_MAIN_DRV

K10

VDD_MAIN_SNS

F19

VDD_MAIN_SNS_WLED

H8

VDD_BOOST_SNS

R16

VDDIO_1V2

N16

VDDIO_BUCK3

N20

VDD_RTC_ALT

K6

VPP

U8100

SER

BGA

SYM 1 OF 6

BUCK0_LX0
BUCK0_LX0

BUCK0_LX1
BUCK0_LX1
BUCK0_LX1
BUCK0_LX1

BUCK0_LX2
BUCK0_LX2
BUCK0_LX2
BUCK0_LX2

BUCK0_LX3
BUCK0_LX3
BUCK0_LX3
BUCK0_LX3

BUCK0_LX4
BUCK0_LX4
BUCK0_LX4
BUCK0_LX4

BUCK0_FB

BUCK0_VSS_FB

BUCK1_LX0
BUCK1_LX0

BUCK1_LX1
BUCK1_LX1
BUCK1_LX1
BUCK1_LX1

BUCK1_LX2
BUCK1_LX2
BUCK1_LX2
BUCK1_LX2

BUCK1_LX3
BUCK1_LX3
BUCK1_LX3
BUCK1_LX3

BUCK1_LX4
BUCK1_LX4
BUCK1_LX4
BUCK1_LX4

BUCK1_FB

BUCK1_VSS_FB

BUCK2_LX0

BUCK2_LX1
BUCK2_LX1

BUCK2_LX2
BUCK2_LX2

BUCK2_FB

BUCK2_VSS_FB

35

BUCK0_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

W6
Y6

V1
V2
V3
V4

P1
P2
P3
P4

T1
T2
T3
T4

M1
M2
M3
M4

U6

PLACE_NEAR=U8100.U6:5MM

T6

35

BUCK0_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK0_LX2

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK0_LX3

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK0_LX4

DIDT=TRUE
SWITCH_NODE=TRUE

BUCK0_FB BUCK0_FB_R

VSS_ANA_MPMU

A6
B6

C1
C2
C3
C4

G1
G2
G3
G4

E1
E2
E3
E4

J1
J2
J3
J4

D6

E6

35

BUCK1_LX0

DIDT=TRUE

SWITCH_NODE=TRUE

35

BUCK1_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK1_LX2

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK1_LX3

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK1_LX4

DIDT=TRUE
SWITCH_NODE=TRUE

BUCK1_FB

PLACE_NEAR=U8100.D6:5MM

VSS_ANA_MPMU

Y20

W18
Y18

W16
Y16

V20

U20

35

BUCK2_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK2_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK2_LX2

DIDT=TRUE
SWITCH_NODE=TRUE

BUCK2_FB

PLACE_NEAR=U8100.V20:5MM

VSS_ANA_MPMU

CRITICAL

1.0UH-20%-4A-0.038OHM

PIKA20161B-COMBO

CRITICAL

0.1UH-20%-10.3A-0.01OHM

1

2

152S01268

CRITICAL

0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM

1

2

152S01268

R810A

0

21

MF

5%

1/20W

0201

353332

L8110

1.0UH-20%-4A-0.038OHM

PIKA20161B-COMBO

L8111

0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM

1

2

152S01268

CRITICAL

L8112

0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM

1

2

152S01268

R810B

0

21

BUCK1_FB_R

5%

1/20W

MF

0201

3533

1.0UH-20%-4A-0.038OHM

CRITICAL

R810C

0

1/20W

21

MF

BUCK2_FB_R

0201

353433

L8100

L8101

PCCE20161B-SM

L8102

CRITICAL

21

CRITICAL

SHORT-14L-0.1MM-SM

CRITICAL

L8120

PIKA20161B-COMBO

0.1UH-20%-10.3A-0.01OHM

1

2

152S01268

21

3

4

3

4

XW8100

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

3

4

3

4

XW8110

21

21

L8121

PCCE20161B-SM

XW8120

SHORT-14L-0.1MM-SM

2 1

NO_XNET_CONNECTION=1

CRITICAL

1

C8100

15UF

20%
2V

2

X6S
0402

1

C8109

15UF

20%
2V

2

X6S
0402

21

1

C8110

15UF

20%
2V

2

X6S
0402

1

C8119

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8110.2:5MM

PLACE_NEAR=L8110.2:5MM

1

C81H4

12PF

5%
25V

2

NP0-C0G
0201

1

2

1

2

1

C81H5

3PF

+/-0.1PF
25V

2

0201 0201

NO_XNET_CONNECTION=1

CRITICAL
NOSTUFF

1

C8120

15UF

20%
2V

2

X6S
0402

3

4

BOM_COST_GROUP=PLATFORM POWER

1

C8101

15UF

20%
2V

2

X6S
0402

1

C810A

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8100.2:5MM

C8111

15UF

20%
2V
X6S
0402

C811A

15UF

20%
2V
X6S
0402

1

C8121

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8120.2:5MM

PLACE_NEAR=L8120.2:5MM

1

C81H8

12PF

5%
25V

2

NP0-C0G
0201

1

C8112

15UF

20%
2V

2

X6S
0402

1

C811B

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8111.3:5MM

1

C81H6

12PF

5%
25V

2

NP0-C0GC0G
0201

1

C8102

15UF

20%
2V

2

X6S
0402

1

C810B

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8100.2:5MM

1

C81H0

12PF

5%

2

NP0-C0G

1

2

1

2

1

2

C8113

15UF

20%
2V
X6S
0402

CRITICAL

1

C811C

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8111.4:5MM

1

C81H7

3PF

+/-0.1PF
25V

2

C0G

1

C8122

15UF

20%
2V

2

X6S
0402

1

C81H9

3PF

+/-0.1PF
25V

2

C0G
0201

1

2

1

C8103

15UF

20%
2V

2

X6S
0402

C810C

15UF

20%
2V
X6S
0402

C81H1

3PF

+/-0.1PF
25V
C0G
0201

1

2

1

2

CRITICAL

C8123

15UF

20%
2V
X6S
0402

1

C8104

15UF

20%
2V

2

X6S
0402

1

C810D

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8101.3:5MM

PLACE_NEAR=L8101.4:5MM

1

C81H2

12PF

5%
25V25V

2

NP0-C0G
02010201

C8114

15UF

20%
2V
X6S
0402

C8116

15UF

20%
2V
X6S
0402

PAGE TITLE

1

2

1

C8124

15UF

20%
2V

2

X6S
0402

C8115

15UF

20%
2V
X6S
0402

1

2

CRITICALCRITICALCRITICALCRITICALCRITICAL

1

C8105

15UF

20%
2V

2

X6S
0402

PPVDD_PCPU_AWAKE

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C810E

20%
2V

2

X6S
0402

1

C81H3

3PF

+/-0.1PF
25V

2

C0G
0201

PPVDD_GPU_AWAKE

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C811D

15UF

20%
2V

2

X6S
0402

1

C811E

15UF

20%
2V

2

X6S
0402

CRITICALCRITICALCRITICALCRITICALCRITICAL

C8117

15UF

20%
2V
X6S
0402

PPVDD_SOC_S1

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C8125

15UF

20%
2V

2

X6S
0402

1

C8126

15UF

20%
2V

2

X6S
0402

1

C8127

15UF

20%
2V

2

X6S
0402

PMU: MASTER INPUT PWR & BUCKS

Apple Inc.

78

78

7835

SYNC_DATE=04/28/2020SYNC_MASTER=ref_pmu_sera_simetra

MASTER PMU BUCKS & GND

GND

35

GND

35

GND

35

GND

35

GND

35

GND

35

GND

35

GND

35

GND

34
35

35

VSS_ANA_MPMU

33
34
48

VSS_ANA_MPMU

35

48 35 34 33

U8100

SER

BGA

SYM 6 OF 6

N1

VSS_BUCK0

N2

VSS_BUCK0

N3

VSS_BUCK0

N4

VSS_BUCK0

U1

VSS_BUCK0

U2

VSS_BUCK0

U3

VSS_BUCK0

U4

VSS_BUCK0

W5

VSS_BUCK0

Y1

VSS_BUCK0

Y2

VSS_BUCK0

Y3

VSS_BUCK0

Y4

VSS_BUCK0

Y5

VSS_BUCK0

A1

VSS_BUCK1

A2

VSS_BUCK1

A3

VSS_BUCK1

A4

VSS_BUCK1

A5

VSS_BUCK1

B5

VSS_BUCK1

D1

VSS_BUCK1

D2

VSS_BUCK1

D3

VSS_BUCK1

D4

VSS_BUCK1

H1

VSS_BUCK1

H2

VSS_BUCK1

H3

VSS_BUCK1

H4

VSS_BUCK1

W17

VSS_BUCK2

W21

VSS_BUCK2

W22

VSS_BUCK2

Y17

VSS_BUCK2

Y21

VSS_BUCK2

Y22

VSS_BUCK2

A17

VSS_BUCK3

B17

VSS_BUCK3

W13

VSS_BUCK7

Y13

VSS_BUCK7

A9

VSS_BUCK8

B9

VSS_BUCK8

A13

VSS_BUCK9_14

B13

VSS_BUCK9_14

W9

VSS_BUCK11

Y9

VSS_BUCK11

V22

VSS_BSTLQ

A21

VSS_WLED_LP

A22

VSS_WLED_LP

B21

VSS_WLED_LP

B22

VSS_WLED_LP

A20

VSS_WLED_HP1

B20

VSS_WLED_HP1

C20

VSS_WLED_HP1

D21

VSS_WLED_HP2

D22

VSS_WLED_HP2

J11

VSS_REF

K7

VSS_DFT_2

OMIT_TABLE

XW82B2

SHORT-14L-0.1MM-SM

VSS_ANA_MPMU

PLACEMENT NOTE:

CONNECT VSS_REF THROUGH ALL GND PLANES PLACE XW AT VSS_REF PIN, ROUTE VSS_RTN
BACK FROM THE VREF / IREF PASSIVES

2 1

MPMU_VREF_IREF_RTN

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A18
B8
B18
C5
C6
C9
C10
C13
C17
D5
D7
D10
D11
D15
D18
D19
D20
E5
E7
E15
E17
E20
F6
F16
F17
F21
F22
G5
G6
G15
G18
H5
H6
H15
H18
J5
J6
J13
J17
J18
K15
K18
L6
L7
L8
L9
L10
L11
L12
L15
M5
N5
N18
N22
P5
P7
R18
T5
T18
U5
U19
V5
V6
V9
V10
V13
V14
V16
V18
V21
W8
W12
W20

1

C8204

1.5UF

20%

6.3V

2

CER-X5R
0201

VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU

VSS_ANA_MPMU
VSS_ANA_MPMU

1

R8201

200K

0.1%
1/20W
TF
0201

2

UNUSED ADC_IN PIN NEED 1M PD

35

3234

3533

353433

3533

353332

353433

3533

353332

353433

3533

353332

353433

3533

353332

3533

353332

353433

353332

353433

353332

3533

353433

353332

3533

353433

353332

35343332

3534

353332

35343332

353332

35343332

353332

35343332

353332

3533

MPMU_ADC_IN
PP1V5_VLDOINT_MPMU

PLACE_NEAR=U8100.C15:5MM

UNUSED VBAT/IBAT PINS NEED
1M PD

PP1V8_S2

78

FROM BUCVK3 POWER ALIAS =>

PP1V25_S278 33

FROM BUCK13 POWER ALIAS =>

35343332

3533

3533

3533

MPMU_VREF
MPMU_IREF

33

33

NOSTUFF

1

C8205

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C8206

0.1UF

10%
10V

2

X6S-CERM
0201

33

35

35

33

DECOUPLING : VDD_SW3

MPMU_VREF
MPMU_VBAT
MPMU_IBAT
MPMU_IREF

PP1V25_S2

PLACE_NEAR=U8100.R19:5MM

CRITICAL

1

C8201

10UF

20%

6.3V

2

CER-X6S
0402

K9

ADC_IN

C7

VDD_ANA

C11

VDD_ANA

C15

VDD_ANA

F5

VDD_ANA

F18

VDD_ANA

J15

VDD_ANA

K5

VDD_ANA

K8

VDD_ANA

L5

VDD_ANA

P18

VDD_ANA

R5

VDD_ANA

V7

VDD_ANA

V11

VDD_ANA

V15

VDD_ANA

V19

VDD_ANA

D9

VDD_DIG

E16

VDD_DIG

J7

VDD_DIG

M18

VDD_DIG

P9

VDD_DIG

R17

VDD_DIG

K12

VREF

J10

VBAT

J9

IBAT

J8

IREF

R21

VDD_SW1

R22

VDD_SW1

T20

VDD_SW2

R19

VDD_SW3

R20

VDD_SW3

7833

CRITICAL CRITICAL

1

C8240

15UF

20%
2V

2

X6S
0402

1

C8241

15UF

20%
2V

2

X6S
0402

U8100

SER

BGA

SYM 2 OF 6

SWITCHED RAILS

PP1V25_AWAKE_IO

OMIT_TABLE

BUCK3_LX
BUCK3_LX

BUCK3_FB

BUCK3_VSS_FB

BUCK7_LX0

BUCK7_LX1
BUCK7_LX1

BUCK7_FB

BUCK7_VSS_FB

BUCK8_LX0

BUCK8_LX1
BUCK8_LX1

BUCK8_FB

BUCK8_VSS_FB

BUCK9_LX
BUCK9_LX

BUCK9_FB

BUCK9_VSS_FB

BUCK11_LX0

BUCK11_LX1
BUCK11_LX1

BUCK11_FB

BUCK11_VSS_FB

BUCK14_LX
BUCK14_LX

BUCK14_FB

BUCK14_VSS_FB

BUCK_SW1
BUCK_SW1
BUCK_SW2
BUCK_SW3
BUCK_SW3

1

C8230

10UF

20% 20% 20% 20% 20%

6.3V

2

CER-X6S
0402

CRITICAL

A16
B16

D16

C16

35

BUCK3_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

BUCK3_FB

PLACE_NEAR=U8100.D16:5MM

VSS_ANA_MPMU

L8230

0.47UH-20%-4A-0.027OHM

2 1

2012

R820A

0

21

BUCK3_FB_R

5%

1/20W

0201

MF

3533

L8270

XW8230

SHORT-14L-0.1MM-SM

2 1

NO_XNET_CONNECTION=1

CRITICAL CRITICAL CRITICAL

1

C8236

10UF

20%

6.3V

2

CER-X6S
0402

1.0UH-20%-4A-0.038OHM

CRITICAL

1

C8271

15UF

20%
2V

2

X6S
0402

Y12

W14
Y14

U12

PLACE_NEAR=U8100.U12:5MM

V12

35

BUCK7_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

35

BUCK7_LX1

DIDT=TRUE

SWITCH_NODE=TRUE

BUCK7_FB

VSS_ANA_MPMU

R820B

5%

CRITICAL

2 1

PIKA20161B-COMBO

L8271

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

CRITICAL

0

21

BUCK7_FB_R

0201

MF1/20W

3533

CRITICAL
NOSTUFF NOSTUFF

1

C8270

15UF

20%
2V

2

X6S
0402

XW8270

SHORT-14L-0.1MM-SM

2 1

NO_XNET_CONNECTION=1

CRITICAL

A8

A10
B10

D8

C8

A12
B12

D12

C12

Y8

W10
Y10

U8

V8

A14
B14

D14

C14

P21
P22
T19
P19
P20

35

BUCK8_LX0

DIDT=TRUE

SWITCH_NODE=TRUE

35

BUCK8_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

1.0UH-20%-4A-0.038OHM

0.22UH-20%-6.7A-0.023OHM

BUCK8_FB

VSS_ANA_MPMU

PLACE_NEAR=U8100.D8:5MM

35

BUCK9_LX0

DIDT=TRUE

SWITCH_NODE=TRUE

35
33
34

0.47UH-20%-4A-0.027OHM

BUCK9_FB

VSS_ANA_MPMU

PLACE_NEAR=U8100.D12:5MM

35

BUCK11_LX0

DIDT=TRUE

SWITCH_NODE=TRUE

35

BUCK11_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

35
33
34

5%

BUCK11_FB
VSS_ANA_MPMU

PLACE_NEAR=U8100.U8:5MM

33
35

5%

R820E

1/20W0MF

BUCK14_LX0

VIN FROM BUCK13 IS POR FOR LDO4,20,8. IF PDN (VMIN VIOLATION, WHEN LDO8 IN DROPOUT MODE)
IS AN ISSUE THEN BUCK14 WILL BE THE BACKUP OPTION. THIS WOULD THEN REQUIRE ADDING BEAD AND CAPS

BUCK14_FB
VSS_ANA_MPMU

PP1V8_AWAKE

NC_MPMU_BUCK_SW2

PP1V25_AWAKE_IO

CRITICAL

7833

1

C8202

10UF

20%

6.3V

2

CER-X6S

1

2

L8280

2 1

PIKA20161B-COMBO

L8281

2 1

PINA20121T-SM

CRITICAL

R820C

0

21

BUCK8_FB_R

0201

5%

2 1

MF1/20W

L8290

2012

CRITICAL

R820D

0

21

BUCK9_FB_R

1/20W MF

0201

L82B0

CRITICAL

NO_XNET_CONNECTION=1

1.0UH-20%-4A-0.038OHM

2 1

PIKA20161B-COMBO

L82B1

CRITICAL

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

XW82B0

SHORT-14L-0.1MM-SM

21

BUCK11_FB_R

0201

35

35

7833

NO_TEST=1

7833

CRITICAL

NO_XNET_CONNECTION=1

353433

PP1V8_AWAKE

2 1

C8203

10UF

20%

6.3V
CER-X6S
04020402

XW8280

SHORT-14L-0.1MM-SM

2 1

NO_XNET_CONNECTION=1

XW8290

SHORT-14L-0.1MM-SM

2 1

1

2

C82B6

15UF

20%
2V
X6S
0402

CRITICAL

1

C8231

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C8237

10UF

20%

6.3V

2

CER-X6S
0402

1

C8272

15UF

20%
2V

2

X6S
0402

1

C8280

15UF

20%
2V

2

X6S
0402

1

C8295

15UF

20%
2V

2

X6S
0402

1

C82B7

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L82B0.1:5MM

1

C82D8

12PF

5%
25V

2

NP0-C0G
0201

7833

PLACE_NEAR=L82B1.1:5MM

1

C8232

10UF

6.3V

2

CER-X6S
0402 0402

CRITICAL

1

C8238

10UF

20%

6.3V

2

CER-X6S
0402

1

C8273

2

1

C8281

15UF

20%
2V

2

X6S
0402

1

2

1

C82B8

2

1

2

15UF

20%
2V
X6S
0402

C8290

15UF

20%
2V
X6S
0402

15UF

20%
2V
X6S
0402

C82D9

3PF

+/-0.1PF
25V
C0G
0201

1

2

BOM_COST_GROUP=PLATFORM POWER

CRITICAL

1

C8233

10UF

6.3V

2

CER-X6S

1

C8239

10UF

20%

6.3V

2

CER-X6S
0402 0402

1

C8274

15UF

20%
2V

2

X6S
0402

C8282

15UF

20%
2V
X6S
0402

1

C8291

15UF

20%
2V

2

X6S
0402

1

C8283

15UF

2

CRITICALCRITICALCRITICALCRITICAL

1

C82B9

15UF

20%
2V

2

X6S
0402

CRITICALCRITICALCRITICAL

1

C8234

10UF

6.3V

2

CER-X6S
0402 0201

CRITICAL

PLACE_NEAR=L8230.1:5MM

1

C8235

10UF

6.3V

2

CER-X6S
0402

CRITICAL

1

C823A

10UF

20%

6.3V

2

CER-X6S

CRITICAL

1

C8275

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8270.1:5MM

1

C823B

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C8276

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8271.1:5MM

1

C82D2

12PF

5%
25V

2

NP0-C0G
0201

CRITICALCRITICALCRITICALCRITICAL

1

C8277

15UF

20%
2V

2

X6S
0402

1

C82D3

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

20%
2V
X6S
0402

1

C8284

15UF

20%
2V

2

X6S
0402

1

C8285

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L8280.1:5MM

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C8292

15UF

20%
2V

2

X6S
0402

1

C8293

15UF

20%
2V

2

X6S
0402

1

C8294

15UF

20%
2V

2

X6S
0402

CRITICALCRITICAL

NOSTUFF NOSTUFF

1

C82B1

15UF

20%
2V

2

X6S
0402

PAGE TITLE

1

C82B2

15UF

20%
2V

2

X6S
0402

PMU: MASTER BUCKS & GND

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

C82D0

12PF

5%
25V

2

NP0-C0G
0201

1

2

PLACE_NEAR=L8230.1:5MM

PPVDD_CPU_SRAM_AWAKE

1

C82D4

12PF

5%
25V

2

NP0-C0G
0201

PLACE_NEAR=L8290.1:5MM

1

C82D6

12PF

5%
25V

2

NP0-C0G
0201

PPVDD_ECPU_AWAKE

1

C82B3

15UF

20%
2V

2

X6S

PP1V8_S2

C82D1

3PF

+/-0.1PF
25V
C0G

PPVDD_DISP_S1

1

C82D5

3PF

+/-0.1PF
25V

2

C0G
0201

PLACE_NEAR=L8281.1:5MM

PPVDD_DCS_S1

PLACE_NEAR=L8290.1:5MM

1

C82D7

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICALCRITICAL

1

C82B4

15UF

20%
2V

2

X6S
0402

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

82 OF 801

SHEET

33 OF 92

78

78

78

78

SYNC_DATE=04/28/2020SYNC_MASTER=ref_pmu_sera_simetra

SIZE

D

2

1

MASTER PMU LDO,ADC, & GPIO

35

PP3V8_AON_VDDMAIN

32
34
79

PLACE_NEAR=L8300.1:5MM

1

2

CRITICAL

1

C8300

20UF

20%
10V

2

X5R
0402

1

C83A2

12PF

5%
25V

2

NP0-C0G
0201

79 35 34 32

LDO1 NOT USED ==> INT PD ENABLED

THIS IS AN OUTPUT ==>

THIS IS AN OUTPUT ==>

1

C8326

1.0UF

20%

6.3V

2

X5R
0201-1

PACK_IGNORE=TRUE
PACK_OPTION=DESKTOP

1

2

PP3V8_AON_VDDMAIN

CRITICAL

PACK_IGNORE=TRUE
PACK_OPTION=DESKTOP

CRITICAL

C8307

10UF

20%

6.3V
CER-X6S
0402

CRITICAL

1

C8327

1.0UF

20%

6.3V

2

X5R
0201-1

CRITICAL

1

2

PP1V5_VLDOINT_MPMU

CRITICAL

1

C8322

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U8100.M21:5MM

CRITICAL

1

2

PLACE_NEAR=U8100.M21:5MM

PLACE_NEAR=L8300.1:5MM

C83A0

12PF

5%
25V
NP0-C0G
0201

1

C83A1

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICAL

1

C8301

20UF

20%
10V

2

X5R
0402

1

C83A3

3PF

+/-0.1PF
25V

2

C0G
0201

NC_MPMU_LDO1_EN

35

PP1V5_VLDOINT_MPMU

3233
34

PP1V5_VLDOINT_MPMU

CRITICAL

1

C8328

1.0UF

20%

6.3V

2

X5R
0201-1

PACK_IGNORE=TRUE
PACK_OPTION=DESKTOP

PORTABLE= NO CAPS NEEDED
DESKTOP =4X1UF

PP1V2_S2

CRITICAL

1

C830A

10UF

20%

6.3V
CER-X6S
0402

C830D

10UF

20%

6.3V
CER-X6S
0402

C8309

10UF

20%

6.3V

2

CER-X6S
0402

PLACE_NEAR=U8100.M21:5MM

PLACE_NEAR=U8100.M21:5MM

1

C830G

220PF

2

CRITICAL

0.47UH-20%-1.7A-0.175OHM

PIJT1005FE-SM-COMBO

CRITICAL

1

C8302

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U8100.T22:5MM

GND

1

C8314

10UF

20%

6.3V

2

CER-X6S
0402

VOLTAGE=1.5V

PACK_OPTION=PORTABLE

CRITICALCRITICAL

1

2

CRITICAL

1

C8329

1.0UF

20%

6.3V

2

X5R
0201-1

PACK_IGNORE=TRUE
PACK_OPTION=DESKTOP

1

C830H

220PF

2

10%
16V
CER-X7R
0201

10%
16V
CER-X7R
0201

L8300

VOLTAGE=5V

35 34 32

79

C8315

10UF

20%

6.3V
CER-X6S
0402

7834

32 33 34

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

21

PP3V8_AON_VDDMAIN

XW83D0

SM

21

VOLTAGE=5V

PLACE_NEAR=U8100.T21:5MM

3533

MAKE_BASE=TRUE

1

2

NC_MPMU_IDAC_OUT<0>
NC_MPMU_IDAC_OUT<1>
NC_MPMU_IDAC_OUT<2>
NC_MPMU_IDAC_OUT<3>
NC_MPMU_IDAC_OUT<4>
NC_MPMU_IDAC_OUT<5>
NC_MPMU_IDAC_OUT<6>
NC_MPMU_IDAC_OUT<7>
NC_MPMU_IDAC_OUT<8>
NC_MPMU_IDAC_OUT<9>
NC_MPMU_IDAC_OUT<10>
NC_MPMU_IDAC_OUT<11>
NC_MPMU_IDAC_OUT<12>
NC_MPMU_IDAC_OUT<13>
NC_MPMU_IDAC_OUT<14>
NC_MPMU_IDAC_OUT<15>
NC_MPMU_IDAC_OUT<16>
NC_MPMU_IDAC_OUT<17>

35

MPMU_BSTLQ_LX

SWITCH_NODE=TRUE

DIDT=TRUE

PP5V_BSTLQ_VOUT_MPMU

PP5V_BSTLQ_MPMU

CRITICAL

1

C8310

0.1UF

10%
10V

2

X6S-CERM
0201

1

C8316

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U8100.D17:5MM

G19

VDD_BOOST_LDO

G21

VDD_BOOST_LDO

H19

VDD_BOOST_LDO

H21

VDD_BOOST_LDO

J21

VDD_BOOST_LDO

M20

VDD_MAIN_LDO

N17

LDO1_EN

M21

VLDOINT

N21

VLDORTC

PP1V8_AON_MPMU

CRITICAL

C8304

1UF

20%
10V
X6S-CERM
0201

1

2

PP3V3_S2_UPC

NOSTUFF
CRITICAL

1

C8303

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C8311

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U8100.L18:5MM

CRITICALCRITICAL

1

C8317

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U8100.H12:5MM

U8100

SER

BGA

SYM 3 OF 6

CRITICAL

C830C

1UF

20%
10V
X6S-CERM
0201

CRITICAL

1

C830E

10UF

20%

6.3V

2

CER-X6S
0402

G17

IDAC_OUT<0>

G16

IDAC_OUT<1>

G14

IDAC_OUT<2>

G13

IDAC_OUT<3>

H17

IDAC_OUT<4>

H16

IDAC_OUT<5>

H14

IDAC_OUT<6>

H13

IDAC_OUT<7>

J16

IDAC_OUT<8>

J14

IDAC_OUT<9>

K17

IDAC_OUT<10>

K16

IDAC_OUT<11>

K14

IDAC_OUT<12>

K13

IDAC_OUT<13>

L17

IDAC_OUT<14>

L16

IDAC_OUT<15>

L14

IDAC_OUT<16>

L13

IDAC_OUT<17>

U22

BSTLQ_LX

T22

BSTLQ_VOUT

H9

VDD_BOOST

H10

VDD_SNS_SPARE

T21

VDD_HI_INT1

H11

VDD_HI_INT2

D13

VDD_HI_INT3

D17

VDD_HI_INT4

H12

VDD_HI_INT5

L18

VDD_HI_INT6

OMIT_TABLE

VLDO1

VLDO2

VLDO3

VLDO5

VLDO7

VLDO9

VLDO10

VLDO13

VLDO14

VLDO16

VLDO19

VREF_ADC

INTEGRATOR ALIAS TO:
1V8 OCARINA=Y
1V2 OCARINA=N

J22

K20

L21

K22

H22

M19

G20

H20

L19

G22

J20

H7

7834

7834

U8100

SER

SYM 5 OF 6

OMIT_TABLE

BGA

VCP_OUT_SPARE

NC_MPMU_VLDO1

NC_MPMU_VLDO2

PP1V2_S2

NC_MPMU_VLDO5

PP3V3_S2_UPC

PP1V8_AON_MPMU

NC_MPMU_VLDO10

NC_MPMU_VLDO13

NC_MPMU_VLDO14

NC_MPMU_VLDO16

NC_MPMU_VLDO19

MPMU_VREF_ADC

48 35 33

VSS_ANA_MPMU

PP1V25_S2

WLED_LP_LX
WLED_LP_LX

WLED_HP1_LX
WLED_HP1_LX
WLED_HP1_LX

WLED_HP2_LX
WLED_HP2_LX

WLED_VOUT_FB

VMBX_SPARE

C21
C22

A19
B19
C19

E21
E22

E18

U21

J12

NO_TEST=1

NO_TEST=1

1

2

R8343

10K

1/20W 201MF5%

NOSTUFF

PP1V8_AON_MPMU

R8324

R8325

R8338

R8339

5% 1/20W MF 201

10K

1/20W5% 201MF

100K

1/20W5%

100K

10K

NC_MPMU_WLED_LP_LX_0
NC_MPMU_WLED_LP_LX_1

NC_MPMU_WLED_HP1_LX_0
NC_MPMU_WLED_HP1_LX_1
NC_MPMU_WLED_HP1_LX_2

NC_MPMU_WLED_HP2_LX_0
NC_MPMU_WLED_HP2_LX_1

NC_MPMU_WLED_VOUT_FB

NC_MPMU_VCP_OUT_SPARE
NC_MPMU_VMBX_SPARE

FEED BY PP1V8_AON (LDO9)POWER ALIAS ==>

78

7834

35

7834

7834

35

35

35

35

C8321

0.1UF

10%

6.3V
CERM-X5R
0201

78

21

PMU_SYS_ALIVE

<== LDO9 POWER ALIAS

30

7834

21

PMU_ONOFF_L

21

PMU_RSLOC_RST_L

MF 201

NOSTUFF

21

MPMU_FAULT_OUT_L

MF

2011/20W5%

NOSTUFF

21

PMU_CRASH_L

OTP HAS IPU

78 34 30

34 35 65 82

34 35 50 82

34 35 77 82

34

34

NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1

NO_TEST=1

NO_TEST=1
NO_TEST=1

PP1V8_AON_MPMU

NXTAL_MEMS=0 ==> XTAL

VSS_ANA_MPMU

35

NOSTUFF

R8326

5%

R8327

R8328

R8329

R8335

R8336

100K

100K

1/20W

100K

1/20W MF5% 201

100K

1/20W

100K

100K

117S0008

R8334

1/20W5% 201MF

R8337

1/20W5% MF

R8344

5% 1/20W MF 201

10K

100K

100K

CRITICAL

R8320

3.92K

0.1%

0201-2

1/20W

MF

XW83D1

SHORT-14L-0.1MM-SM

21

21

WLBT_PWR_EN

201MF1/20W

NOSTUFF

21

SE_PWR_EN

201MF5%

NOSTUFF

21

LCD_PWR_EN

21

P3V3S2_PWR_EN_MPMU

201MF5%

21

SENSOR_PWR_EN

MF1/20W5% 201

NOSTUFF

21

IPD_WAKE_L

201MF1/20W5%

21

MPMU_REQUEST_DFU

21

P3V8AON_LPM

201

NOSTUFF

21

PVDD1_PWR_EN

U8100

OMIT_TABLESER

BGA

SYM 4 OF 6

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

NC_MPMU_TDEV1
NC_MPMU_TDEV2
MPMU_TDEV3
MPMU_TDEV4
MPMU_TDEV5
NC_MPMU_TDEV6
MPMU_TDEV7
MPMU_TDEV8

MPMU_TCAL

2

1

34355082

34357782

35 35

35

35

7

IN
IN
IN
IN

IN
IN
IN

1

C8320

100PF

5%
25V

2

C0G
0201

PMU_ONOFF_L
PMU_RSLOC_RST_L
NC_MPMU_BUTTON3 NC_MPMU_BUTTONO3
NC_MPMU_BUTTON4

PMU_RESET_1V8
SOC_SOCHOT_L

MPMU_VBUS_DET

VSS_ANA_MPMU

35 33

PMU_SHDN

E8

TDEV1

F9

TDEV2

F8

TDEV3

F7

TDEV4

G9

TDEV5

G10

TDEV6

G8

TDEV7

G7

TDEV8

F10

TCAL

TDEV GPIO

P10

BUTTON1

M6

BUTTON2

N8

BUTTON3

P11

BUTTON4

N11 N13

RESET_IN1

M10

RESET_IN2

M9

RESET_IN3

R7

VBUS_DET

E9

BRICK_ID1

E10

BRICK_ID2

M8

SHDN

IPD

BUTTONS

DBLCLICK_DET

RESET

SGPIO_READY_REQ

GPIO1
GPIO2
GPIO3
GPIO4

IPU

GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27

BUTTONO1
BUTTONO2
BUTTONO3

RESET*

FORCE_DFU

FAULT_OUT*

SCRASH*

R8322

10K

21

1%

NOSTUFF

1/20W

MF

201

35 33 32

MPMU_XIN

34

MPMU_XOUT

34

47

IN

47

IN

47

IN

47

IN

35

IN

47

IN

47

IN

47

IN

47

IN

35

IN

DCIN_VSENSE
DCIN_ISENSE
PBUS_VSENSE
BMON_ISENSE
MPMU_AMUX_AY

P3V8AON_IMEAS
P3V3S2_HS_ISENSE
P5VS2_HS_ISENSE
NC_MPMU_AMUX_B3
MPMU_AMUX_BY

34 60 61

21 34

VSS_ANA_MPMU

3534

N19

L22
M22

E13
F11
E12
E11
G12

E14
F14
F12
F13
G11

NXTAL_MEMS

XIN
XOUT

AMUX_A<0>
AMUX_A<1>
AMUX_A<2>
AMUX_A<3>
AMUX_AY

AMUX_B<0>
AMUX_B<1>
AMUX_B<2>
AMUX_B<3>
AMUX_BY

AMUX

SPMI

CLOCKS

MPMU_XTAL1_R

CRITICAL

3534

Y8301

32.768KHZ-20PPM-12.5PF

27 34 40 44

3534

CRITICAL

1

C8312

18PF

5%
25V

2

C0G-CERM
0201

1.60X1.00-SM

SGPIO_SCLK

SGPIO_SDATA

SPMI_SCLK

SPMI_SDATA

SLEEP_32K

OUT_32K

CRASH*

DFT_CTRL0
DFT_CTRL1

SYS_ALIVE

ACTIVE_READY

REQUEST_DFU

CPU_TRIGGER0*
CPU_TRIGGER1*
GPU_TRIGGER0*
GPU_TRIGGER1*

UVWARN*

VDD_BOOST_UVLO*

21

P16
T9
T7
R11
T8
U7
T11
U10
R12
U9
T12
U11
T13
U13
M13
M14
N14
R13
U14
U15
T14
U16
U17
R14
N10
P8
P17

N7
N9
M7

N6

IPD_LID_OPEN_1V8
CHGR_AUX_OK
SWD_NUB_PMU_SWDIO
CODEC_WAKE_L
WLBT_WAKE
IPD_PWR_EN
NC_HDMI_CEC_IRQ
NC_USB3_WAKE
NC_HDMI_RESET_L
LCD_PWR_EN
P3V3S2_PWR_EN_MPMU
PVDD1_PWR_EN
WLBT_PWR_EN
IPD_WAKE_L
SE_PWR_EN
SENSOR_PWR_EN

NAND0_LPB_L

BL_PWR_EN
P3V8AON_LPM
P5VS2_PWR_EN
NC_MPMU_NAND0_RESET_L
IPD_OCP_FLT
NC_USB3_PWR_EN
NC_MPMU_GPIO24

P2V5_NAND0_DISCHARGE_EN

NC_FAN_PWR_EN
NC_MPMU_GPIO27

NC_MPMU_BUTTONO1
NC_MPMU_BUTTONO2

DBL_CLICK_DET

PMU_RESET_LSOC_WDOG

1V2 OUTPUT

T10

M12

N12

M15

N15
P15

R15
T15

U18

T16

PMU_CLK32K_SOC_R

SOC_FORCE_DFU
MPMU_FAULT_OUT_L
PMU_SCRASH_L
PMU_SGPIO_READY_REQ

SGPIO_SCLK_R
SGPIO_SDATA_R

SPMI_NUB_MPMU_CLK
SPMI_NUB_MPMU_DATA

R8331

PLACE_NEAR=U8100.U18:5MM

R8330

PMU_CLK32K_WLBT_R

P12
M16
M17

M11

P13

R6

P6
R9
R8
R10
P14
T17

PLACE_NEAR=U8100.T16:5MM

PMU_CRASH_L

VSS_ANA_MPMU

SWD_NUB_SWCLK
PMU_SYS_ALIVE
PMU_ACTIVE_READY
MPMU_REQUEST_DFU
BUCK0_THERMAL_THROTTLE_L

PMU_VDDHI_UVWARN_L

BUCK1_THERMAL_THROTTLE_L

NC_GPU_TRIGGER1_L
PMU_VDDMAIN_UVWARN_L
TPT_MPMU_BOOST_UVLO_L

MPMU_BOOST_UVLO IS OD. IF NEED TO PROBE OR USE IT , ADD A PU
INTERNAL PULL CAN BE ENABLED AS WELL!

R8313

0

21

0201MF5%1/20W

1

NOSTUFF

CRITICAL

1

C8313

18PF

5%
25V

2

C0G-CERM
0201

VSS_ANA_MPMU

INTERNAL XTAL DRIVER CIRCUIT IS CONNECTED TO CLOSEST VSS PIN N22

R8318

1M

5%
1/20W
MF
201

2

3533

MPMU_XOUT
MPMU_XIN

IN
IN

BI
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN

OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT

OUT

OUT

OUT

34

OUT

34

34

33

21

21

PMU_CLK32K_SOC

201MF1/20W5%

33

PMU_CLK32K_WLBT

201MF1/20W5%

OD
OD
OD
OD

34

34

OD
OD

34

OUT

OUT

34

OUT
OUT
OUT
OUT
OUT

35

71 77

24

10 30

50 75

60 61

GPIO6=ENET_WAKE_L ==> DESKTOP
GPIO6=IPD_PWR_EN ==> PORTABLE

35

GPIO6 NEED PD ON PORTABLES

35

35

35

34
35

34 35

34 40

34 60 61

34
35

21 34

27 34 40 44

62 63

69

34 35

35

65

35

35

35

64

35

35

BI

IN

BI

3533

IN

<= FOR J274 ONLY
<= FOR DESKTOPS ONLY
<= FOR J274 ONLY

GPIO10=P5VS2_PWR_EN ==> DESKTOP
GPIO10=LCD_PWR_EN ==> PORTABLE

GPIO14=ENET_PWR_EN ==> DESKTOP
GPIO14=TPAD_KBD_WAKE_L ==>

HDMI_CECFET_EN==> FOR J274 ONLY

FOR PORTABLES

GPIO20=LCD_PWR_EN ==>J456/J457
GPIO20=HDMI_PWR_EN ==>J274
GPIO20=P5VS2_PWR_EN ==>PORTABLE

<= FOR DESKTOP ONLY

FOR J456 ONLY (ENABLE UWB LDO)

<= NOT USED
<= NOT USED
<= NOT USED

7

6 10 72 8210

PMOS OD

30

30

20

20

10 30

34 35 65 82

6 53 82

7 35

<= TO SOC ON PORTABLES ONLY

7 35

35

7 35

6 54 82

R8341

34

34 40

20

5%
MF

201

2

SGPIO_SCLK

OUT

30

SGPIO_SCLK_R

34

PLACE_NEAR=U8100.N15:5MM

1/20W

R8342

20

21

SGPIO_SDATA_R

34

3534

PLACE_NEAR=U8100.P15:5MM

5%

1/20W

MF

BOM_COST_GROUP=PLATFORM POWER

SGPIO_SDATA

OUT

30

SYNC_MASTER=ref_pmu_sera_simetra SYNC_DATE=04/28/2020

PAGE TITLE

PMU: MASTER LDO & GPIO

DRAWING NUMBER

051-05392

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

4.0.0

BRANCH

evt-1

PAGE

83 OF 801

SHEET

34 OF 92

PORTABLE

35

35

10

OUT

60 61

OUT

SIZE

D

35 468

A BUCK 14 Filter

B PMU Main BUCK Decoupling

79 35 34 32

PP3V8_AON_VDDMAIN

L84E0

0.47UH-20%-4A-0.027OHM

35 33

BUCK14_LX0

BUCK14_FB

33

BUCK14_LX0

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PLACE_NEAR=U8100.D14:5MM

5% 1/20W 0201

2012

R84E0

0

MF

21

21

BUCK14_FB_RBUCK14_FB

NO_XNET_CONNECTION=1

XW84E0

SHORT-14L-0.1MM-SM

2 1

CRITICAL

1

C84E0

15UF

20%
2V

2

X6S
0402

CRITICAL

1

C84E1

15UF

20%
2V

2

X6S
0402

C D

NOSTUFF

R8411

0

5%
MF

0402

0

5%
MF

0402

21

2

PPVDD_PMU_LDO_PREREG

MAKE_BASE=TRUE

VOLTAGE=1.4V

PPVDD_PMU_LDO_PREREG
PPVDD_PMU_LDO_PREREG

PPVDD_PMU_LDO_PREREG

78 32

29

32

29

PP1V25_S2

78

PP1V4_LDO_PREREG

78

1/16W

R8422

1/16W

CRITICAL

1

C84E2

15UF

20%
2V

2

X6S
0402

PPVDD_SOC_S1 DecouplingPPVDD_PMU_LDO_PREREG Aliases

PPVDD_SOC_S1

CRITICAL

1

C84E3

15UF

20%
2V

2

0402

1

2

1

C8460

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

C84E4

15UF

20%
2V
X6SX6S
0402

CRITICAL

1

C84E5

15UF

20%
2V

2

X6S
0402

1

C8461

2.2UF

20%
4V

2

X6S-CERM
0201

PP1V4_LDO_PREREG

1

C82EA

12PF

5%
25V

2

NP0-C0G
0201

1

C8462

2.2UF

20%
4V

2

X6S-CERM
0201

1

C82EB

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8463

2.2UF

20%
4V

2

X6S-CERM
0201

1

C84C0

1UF

20%

78

79 35 34 32

PP3V8_AON_VDDMAIN

10V

2

X6S-CERM
0201

1

C84C8

1UF

20%
10V

2

X6S-CERM
0201

1

C84C1

1UF

20%
10V

2

X6S-CERM
0201

1

C84C9

1UF

20%
10V

2

X6S-CERM
0201

1

C84C2

1UF

20%
10V

2

X6S-CERM
0201

1

C84CA

1UF

20%
10V

2

X6S-CERM
0201

1

C84C3

1UF

20%
10V

2

X6S-CERM
0201

1

C84CB

1UF

20%
10V

2

X6S-CERM
0201

1

C84C4

1UF

20%
10V

2

X6S-CERM
0201

1

C84CC

1UF

20%
10V

2

X6S-CERM
0201

1

C84C5

1UF

20%
10V

2

X6S-CERM
0201

1

C84CD

1UF

20%
10V

2

X6S-CERM
0201

1

C84C6

1UF

20%
10V

2

X6S-CERM

1

C84CE

1UF

20%
10V

2

X6S-CERM
0201

1

C84C7

1UF

20%
10V

2

X6S-CERM
0201

1

C84CF

1UF

20%
10V

2

X6S-CERM
0201

PP3V8_AON_VDDMAIN

1

C84D7

1UF

20%
10V

2

X6S-CERM
0201

1

C84DF

1UF

20%
10V

2

X6S-CERM
0201

79 35 34 32

PP3V8_AON_VDDMAIN

1

C84D0

1UF

20%
10V

2

X6S-CERM
0201

1

C84D8

1UF

20%
10V

2

X6S-CERM
0201

1

C84D1

1UF

20%
10V

2

X6S-CERM
0201

1

C84D9

1UF

20%
10V

2

X6S-CERM
0201

1

C84D2

1UF

20%
10V

2

X6S-CERM
0201

1

C84DA

1UF

20%
10V

2

X6S-CERM
0201

1

C84D3

1UF

20%
10V

2

X6S-CERM
0201

1

C84DB

1UF

20%
10V

2

X6S-CERM
0201

1

C84D4

1UF

20%
10V

2

X6S-CERM
0201

1

C84DC

1UF

20%
10V

2

X6S-CERM
0201

1

C84D5

1UF

20%
10V

2

X6S-CERM
0201

1

C84DD

1UF

20%
10V

2

X6S-CERM
0201

1

C84D6

1UF

20%
10V

2

X6S-CERM
0201

1

C84DE

1UF

20%
10V

2

X6S-CERM
0201

I

78 75

PMU Control Flag Pull-Ups

PP1V25_AWAKE_IO

10K

10K

10K

10K

21

21

21

21

R8450

1/20W

5% MF 201

R8451
R8452

5% 1/20W MF 201

R8454

NC_GPU_TRIGGER1_L

NO_TEST=1

MAKE_BASE=TRUE

BUCK0_THERMAL_THROTTLE_L

PMU_VDDHI_UVWARN_L

201MF5% 1/20W

BUCK1_THERMAL_THROTTLE_L

PMU_VDDMAIN_UVWARN_L

201MF1/20W5%

NC_GPU_TRIGGER1_L

PMU_RESET_1V8 Generation

PP3V3_AON

79

BYPASS=U8440::3MM

10%
25V
X5R

0201

1

VDD

2

U8440

SLG4AP43601

STQFN

NC

10

2
5
6
8
9
11
12

CHGR_RST_IN_R

NC
NC
NC
NC
NC
NC
NC

3

BTN1

4

BTN2

RESET

CRITICAL

343S00387

GND

C8440

0.1UF

345082

IN

347782

IN

PMU_ONOFF_L
PMU_RSLOC_RST_L

PMU GND Aliases

VSS_ANA_MPMU

47

MAKE_BASE=TRUE

33 32

33 32

34 33

34 33

34 33 32

34 33

48 34 33

VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU

33

VSS_ANA_MPMU

33

VSS_ANA_MPMU
VSS_ANA_MPMU

33

VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU

33

VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU

33

VSS_ANA_MPMU

34

GND

33

GND

33

GND

33

GND

33

GND

33

XW8400

SHORT-14L-0.1MM-SM

21

XW8401

SHORT-14L-0.1MM-SM

21

XW8402

SHORT-14L-0.1MM-SM

21

XW8403

SHORT-14L-0.1MM-SM

21

XW8404

SHORT-14L-0.1MM-SM

21

XW8405

SHORT-14L-0.1MM-SM

21

XW8406

SHORT-14L-0.1MM-SM

21

XW8407

SHORT-14L-0.1MM-SM

21

XW8408

SHORT-14L-0.1MM-SM

21

XW8409

SHORT-14L-0.1MM-SM

21

OUT

OUT

OUT

OUT

OUT

FE

7 34

34 35

7 34

7 34

34

PMU Input Protection PMU Test Points

1

R8400

1M

5%
1/20W
MF
201

2

1

R8401

1M

5%
1/20W
MF
201

2

1

R8402

1M

5%
1/20W
MF
201

2

MPMU_ADC_IN
MPMU_VBAT
MPMU_IBAT

OUT
OUT
OUT

33

33

33

R8440

3.3K

1/20W

R8441

3.3K

1/20W

5556

UPC_PMU_RESET_3V3

IN

5%
MF

201

5%
MF

201

21

CHGR_RST_IN

Normally acts
as pull-down.

21

C8445

0.1UF

10%

6.3V

CERM-X5R

0201

23

OUT

PP1V8_AON

79

U8445

VCC

2

1

2

GND

SN74AUP1G17

SON

4

NC

NC

NC

NC

PMU_RESET_1V8

OUT

34

G H

34

IN

TPT_MPMU_BOOST_UVLO_L

TPT_MPMU_BOOST_UVLO_L

MAKE_BASE=TRUE

34

IN

34

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN

32

IN PP

32

IN PP

32

IN PP

32

IN PP

32

IN PP

33

IN PP

33

IN PP

33

IN PP

33

IN PP

33

IN PP

33

IN PP

33

IN PP

33

IN PP

3335

IN PP

34

IN PP

MPMU_AMUX_AY
MPMU_AMUX_BY

BUCK0_LX0
BUCK0_LX1
BUCK0_LX2
BUCK0_LX3
BUCK0_LX4
BUCK1_LX0
BUCK1_LX1
BUCK1_LX2
BUCK1_LX3
BUCK1_LX4
BUCK2_LX0
BUCK2_LX1
BUCK2_LX2
BUCK3_LX0
BUCK7_LX0
BUCK7_LX1
BUCK8_LX0
BUCK8_LX1
BUCK9_LX0
BUCK11_LX0
BUCK11_LX1
BUCK14_LX0
MPMU_BSTLQ_LX

1

TP

1

TP

1

TP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

TP-P4

TP-P4
TP-P4

SM P4MM

SM

P4MM

SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM
SM P4MM

TP8410

TP8400
TP8401

PP8400
PP8401
PP8402
PP8403
PP8404
PP8405
PP8406
PP8407
PP8408
PP8409
PP8410
PP8411
PP8412
PP8413
PP8414
PP8415
PP8416
PP8417
PP8418
PP8419
PP8420
PP8421
PP8422

J K

PMU NC Aliases

NC_HDMI_CEC_IRQ

34

NC_USB3_WAKE

34

NC_HDMI_RESET_L

34

NC_USB3_PWR_EN

34

NC_MPMU_GPIO24

34

NC_MPMU_LDO1_EN

34

NC_FAN_PWR_EN

34

NC_MPMU_GPIO27

34

NC_HDMI_CEC_IRQ

MAKE_BASE=TRUE

NC_USB3_WAKE

MAKE_BASE=TRUE

NC_HDMI_RESET_L

MAKE_BASE=TRUE

NC_USB3_PWR_EN

MAKE_BASE=TRUE

NC_MPMU_GPIO24

MAKE_BASE=TRUE

NC_MPMU_LDO1_EN

MAKE_BASE=TRUE

NC_FAN_PWR_EN

MAKE_BASE=TRUE

NC_MPMU_GPIO27

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NC_MPMU_VLDO5

34

NC_MPMU_VLDO10

34

NC_MPMU_VLDO13

34

NC_MPMU_VLDO14

34

NC_MPMU_VLDO16

34

NC_MPMU_BUTTON3

34

NC_MPMU_BUTTON4

34

NC_MPMU_BUTTONO1

34

NC_MPMU_BUTTONO2

34

NC_MPMU_BUTTONO3

34

NC_MPMU_VLDO5

MAKE_BASE=TRUE

NC_MPMU_VLDO10

MAKE_BASE=TRUE

NC_MPMU_VLDO13

MAKE_BASE=TRUE

NC_MPMU_VLDO14

MAKE_BASE=TRUE

NC_MPMU_VLDO16

NC_MPMU_BUTTON3

MAKE_BASE=TRUE

NC_MPMU_BUTTON4

MAKE_BASE=TRUE

NC_MPMU_BUTTONO1

MAKE_BASE=TRUE

NC_MPMU_BUTTONO2

MAKE_BASE=TRUE

NC_MPMU_BUTTONO3

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

7

OUT

PMU Signal Aliases

R8480

5% MF1/20W

100K

117S0008

21

IPD_OCP_FLT

34

LCD_PWR_EN

34

P3V8AON_LPM

34

P5VS2_PWR_EN

34

P3V3S2_PWR_EN_MPMU

34

IPD_PWR_EN34

201

IPD_WAKE_L

34

PMU_SYS_ALIVE

68

PMU_VDDHI_UVWARN_L

IPD_OCP_FLT

MAKE_BASE=TRUE

LCD_PWR_EN

MAKE_BASE=TRUE

P3V8AON_LPM

MAKE_BASE=TRUE

P5VS2_PWR_EN

MAKE_BASE=TRUE

P3V3S2_PWR_EN_MPMU

MAKE_BASE=TRUEMAKE_BASE=TRUE

IPD_PWR_EN

MAKE_BASE=TRUE

IPD_WAKE_L

MAKE_BASE=TRUE

PMU_SYS_ALIVE

MAKE_BASE=TRUE

PMU_VDDHI_UVWARN_L

MAKE_BASE=TRUE

40

68

25

37 38 40

37

40

76

34 65 82

34 35

BOM_COST_GROUP=PLATFORM POWER

GND

33

GND

33

GND

33

34 33

PAGE TITLE

GND

PMU: Master extra

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

84 OF 801

SHEET

35 OF 92

SIZE

D

1

3.3V AON LDO

PP3V8_AON_VDDMAIN

79

353S3698

UC100

LP5907UVX-3.3V

VIN

USMD

VOUT

250mA max
+/-2% DC max error

A2A1

PP3V3_AON

79

RC100

0

21

78

IN

PP1V8_AON_MPMU

5%

1/20W

MF

0201

P3V3_AON_EN

CC100

1.0UF

20%

6.3V
X5R

0201-1

B1

VEN

GND

1

2

1

CC101

1.0UF

20%

6.3V

2

X5R
0201-1

1.8V AON LDO

353S4262

PP3V8_AON_VDDMAIN

79

RC120

0

21

P1V8_AON_EN

5%

1/20W

MF

0201

CC120

1.0UF

20%

6.3V
X5R

0201-1

UC120

LP5907UVX-1.8

VIN

B1

VEN

1

2

DSBGA

GND

VOUT

250mA max
+/-2% DC max error

A2A1

1

CC121

1.0UF

20%

6.3V

2

X5R
0201-1

PP1V8_AON

79

BOM_COST_GROUP=PLATFORM POWER

SYNC_MASTER=tga_140 SYNC_DATE=05/31/2019

PAGE TITLE

Power: LDOs

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

121 OF 801

SHEET

36 OF 92

A

PP3V3_S2 Discharge Circuit

PP3V3_S2

79

D

PP3V3_S2 Probe Points

LTSpice:

79 37

376S0855

DMN5L06VK-7

RC210

3739

IN

P3V3S2_PWR_EN

1/20W MF5% 0201

21

0

P3V3_S2_PWR_EN_R

QC210

SOT563

VER-3

2

D

SG

PP3V8_AON_VDDMAIN

P3V3S2_DSCHG_EN_RC

6

1

$X1757GHUB/mlb/sim/ltspice/pp3v3_s2_discharge/pp3v3_s2_discharge_diodes_inc.asc

117S0008

RC211

100K

5%

1/20W

MF

201

NOSTUFF

114S0217

RC213

976

1%
1/16W
MF-LF

402

376S0855

1

2

DMN5L06VK-7

QC210

SOT563

VER-3

5

P3V3S2_DSCHG

3

D

SG

4

1

2

NOSTUFF

114S0217

RC212

1/16W
MF-LF

976

1%

402

PPC200

1

P4MM

SM

PP

1

P3V3S2_EN

39

PPC201

P4MM

2

SM

1

PP PP

P3V3S2_PGOOD

39

PPC203

PP

1

P4MM

SM

PPC204

P4MM

SM

1

P3V3S2_VOS

P3V3S2_SW

39

39

PPC202

P4MM

SM

E

1

PP

PP5V_S2 Probe Points

P3V3S2_FB_LPF

39

NOSTUFF

1

CC210

47PF

5%
25V

2

C0G
0201

131S0806

PPC210

P4MM

SM

1

PP PP

P5VS2_EN

38

PPC211

P4MM

SM

PP

1

P5VS2_PGOOD

38

PPC212

P4MM

SM

PP

1

P5VS2_FB_XW

38

PPC213

P4MM

SM

1

PPC214

PP

1

P4MM

SM

PPC215

PP

1

P4MM

SM

P5VS2_FB_RC

P5VS2_SW

GND

38

38 83

B

LTSpice:

353840

IN

PP5V_S2 Discharge Circuit

376S0855

QC220

DMN5L06VK-7

SOT563

VER-3

2

P5VS2_PWR_EN

RC220

1/20W MF5% 0201

21

0

P5V_S2_PWR_EN_R

79 37

PP3V8_AON_VDDMAIN

P5VS2_DSCHG_EN_RC

6

D

SG

1

117S0008

RC221

100K

5%

1/20W

MF

201

PP5V_S2

79

1

2

NOSTUFF

114S0212

RC222

1/16W
MF-LF

866

1%

402

1

2

376S0855

P5VS2_DSCHG

NOSTUFF

114S0212

RC223

1/16W
MF-LF

866

1%

402

QC220

3

1

2

DMN5L06VK-7

SOT563

VER-3

5

D

SG

4

NOSTUFF

1

CC220

47PF

5%
25V

2

C0G
0201

131S0806

$X1757GHUB/mlb/sim/ltspice/pp5v_s2_discharge/pp5v_s2_discharge_diodes_inc.asc

C

P3V3S2_PWR_EN Gating Logic

78 76 40

40

35

PP1V8_AON_MPMU

IN

IN

IPD_PWR_EN_GATE

P3V3S2_PWR_EN_MPMU

BYPASS=UC240::5MM

1

CC240

0.1UF

10%

6.3V

2

CERM-X5R
0201

2

1

UC240

NC

5 3

311S00060

6

74LVC1G32FW5

X1-DFN1010

4

P3V3S2_PWR_EN

OUT

Radar:

37 39

1/20W MF5%

NOTE:

Per Sera PMU OTP, GPIO11 is OFF when the System is OFF.
A side-effect is that during the SIP_SMC->AWAKE transition the rail
goes from ON->OFF->ON, which means we lose trackpad power during
the OFF transition.

IPD_PWR_EN and PP5V_S2_EN were moved to GPIOs that Sera PMU can "hold" off.

RC240

21

0

NOSTUFF

0201

PAGE TITLE

POWER: 5V, 3V3 Support

051-05392

Apple Inc.

122 OF 801

37 OF 92

SIZE

D

* OK2INTEGRATE *

PPBUS_5VS2_VIN

79

5V_S2 Voltage Regulator

SET ONE OPTION FOR PBUS CAPS

PACK_OPTION=5V_S2_PBUS-B12
PACK_OPTION=5V_S2_PBUS-D2
PACK_OPTION=5V_S2_PBUS-D12

CAPDERATE
POLY-TANT

CRITICAL

1

CC320

33UF

20%
16V

2

TANT
CASE-T

128S00009

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_OPTION=5V_S2_PBUS-B12

PACK_OPTION=5V_S2_PBUS-B12

PACK_OPTION=5V_S2_PBUS-B12

CAPDERATE
POLY-TANT

CRITICAL

1

CC340

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE
PACK_OPTION=5V_S2_PBUS-D2

PACK_OPTION=5V_S2_PBUS-D2

CAPDERATE
POLY-TANT

CRITICAL

1

CC350

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CAPDERATE CAPDERATE
POLY-TANT

CRITICAL

1

CC321

33UF

20%
16V

2

TANT
CASE-T

128S00009

CAPDERATE
POLY-TANT

CRITICAL

1

CC341

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CAPDERATE
POLY-TANT

CRITICAL

1

CC351

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

POLY-TANT

CRITICAL

1

CC322

33UF

20%
16V

2

TANT
CASE-T

128S00009

P5VS2_PGOOD

3738

RC328

100K

5%

1/20W

MF

201

117S0008

21

PP5V_S2

START UP TIME < 15 MS

79

P5VS2_VC_R

PACK_OPTION=5V_S2_PBUS-D12

PACK_OPTION=5V_S2_PBUS-D12

1

CC323

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

353740

IN

1

2

1

2

P5VS2_PWR_EN

RC321

20.5K

1%
1/20W
MF
201

118S0180

CC328

1000PF

10%
16V
X7R-1
0201

132S0651

1

CC324

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

1

CC329

100PF

5%
25V

2

C0G
0201

131S0805

1

CC325

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

117S0201

1

CC327

0.01UF

10%
16V

2

X7R-CERM
0402

132S0374

RC333

0

5%

1/20W

MF

0201

3738

38

1

CC326

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

21

37

OUT

P5VS2_EN
P5VS2_VC
P5VS2_PGOOD
P5VS2_FB
P5VS2_SS
P5VS2_RT

1

RC320

25.5K

1%
1/20W
MF
201

2

118S0235

XWC320

SM

21

4

VIN

5

VIN

6

VIN

13

VIN

14

VIN

15

VIN

17

EN/UV

22

VC

23

PG

24

FB

21

SS

18

RT

20

SYNC/MODE

UC300

LT8642EV-2#PBF

LQFN

353S02219

CRITICAL

GND

NC

BIAS

INTVCC

BST

SW
SW
SW
SW
SW

CLKOUT

1

2

7

8
9
10
11
12

19

1

CC330

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

P5VS2_BIAS
P5VS2_INTVCC
P5VS2_BST P5VS2_BST_R

SWITCH_NODE=TRUE
DIDT=TRUE

P5VS2_SW

3783

SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

NC

RC332

1.5

5%

1/20W

MF

201

117S0029

21

SWITCH_NODE=TRUE
DIDT=TRUE

P5VS2_FB_RC

37

1

CC331

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

RC326

1/20W

118S0395

47K

1%
MF

201

CC332

47NF

10%
10V

X6S-CERM

0201

132S00028

1

2

1

RC327

0

5%
1/20W
MF
0201

2

117S0201

Vout=5.15V

21

CRITICAL

LC320

1UH-20%-11A-0.0127OHM

21

P5VS2_FB_XW

37

PIHA052D-SM

152S00265

XWC321

2

SM

1

1

RC322

10

5%
1/20W
MF
201

2

117S0004

1

RC323

9.31K

1%
1/20W
MF
201

2

118S0569

CAPDERATE
POLY-TANT

CRITICAL

1

CC334

150UF

20%

6.3V

2

TANT
CASE-B-SM

128S00038

CAPDERATE
POLY-TANT

CRITICAL

1

CC335

150UF

20%

6.3V

2

TANT
CASE-B-SM

128S00038

CRITICAL

1

CC337

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

EDC=6.6A
F=1.5MHz

PP5V_S2 79

CRITICAL

1

CC338

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

P5VS2_AGND

P5VS2_FB

38

P5VS2_FB_C P5VS2_FB_RC2

10%
16V

0201

1

2

CC333

470PF

X5R-X7R-CERM

132S0361

CRITICAL

1

RC324

200K

0.1%
1/20W
TF
0201

2

118S0738

CRITICAL

1

RC325

27.4K

0.1%
1/20W
MF
0201

2

103S00009

SYNC_MASTER=ref_vr_5v_lt8642s

PAGE TITLE

POWER: 5V S2

Apple Inc.

BOM_COST_GROUP=PLATFORM POWER

* OK2INTEGRATE *

PPBUS_3V3S2_VIN

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_OPTION=3V3_S2_PBUS-B12

PACK_OPTION=3V3_S2_PBUS-B12

CAPDERATE
POLY-TANT

CRITICAL

1

CC710

33UF

20%
16V

2

TANT
CASE-T

128S00009

CAPDERATE
POLY-TANT

CRITICAL

1

CC711

33UF

20%
16V

2

TANT
CASE-T

128S00009

3V3_S2 VR

SET ONE OPTION FOR PBUS CAPS

PACK_OPTION=3V3_S2_PBUS-B12
PACK_OPTION=3V3_S2_PBUS-D2
PACK_OPTION=3V3_S2_PBUS-D12
PACK_OPTION=3V3_S2_PBUS-25V_D2

START UP TIME <5 MS

CAPDERATE
POLY-TANT

CRITICAL

1

CC721

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

PACK_OPTION=3V3_S2_PBUS-D2

CAPDERATE
POLY-TANT

CRITICAL

1

CC722

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

PACK_IGNORE=TRUE

PACK_OPTION=3V3_S2_PBUS-D12

CRITICAL

1

CC723

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

128S0217

PACK_IGNORE=TRUE

PACK_OPTION=3V3_S2_PBUS-25V_D2

P3V3S2_PGOOD

3739

RC715

100K

5%

1/20W

MF

201

117S0008

21

PP3V3_S2

79

CRITICAL

1

CC712

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

1

CC713

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

VOUT=3.3V
EDC=2.5A

CRITICAL

UC710

SN621371

1 2

RC714

0

5%
MF

0201

21

37

P3V3S2_SS

1

CC714

0.01UF

10%
10V

2

X7R-CERM
0201

132S0411

37

IN

P3V3S2_PWR_EN P3V3S2_EN

1/20W

117S0201

VIN

8

EN

9

SS/TR

11

VSEL

10

MODE

XWC710

SM

VQFN

353S02228

CRITICAL

GND

21

SW

VOS

FB

PG

FB2

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

P3V3S2_SW

37

6

P3V3S2_VOS

37

5

P3V3S2_FB

7

P3V3S2_PGOOD

4

OUT

37 39

LC710

1.5UH-20%-3.9A-0.048OHM

1210

152S00476

21

P3V3S2_FB_XW

2

XWC711

SM

1

1

RC709

15

5%
1/20W
MF
201

2

117S0030

P3V3S2_FB_LPF

37

CC719

0.1UF

21

POLY-TANT

CRITICAL

1

CC715

150UF

20%

6.3V

2

TANT
CASE-B-SM

128S00038

CRITICAL

1

CC717

10UF

20%

6.3V

2

CER-X6S
0402

138S00073

TDC=2.0A
F=1.5MHz

PP3V3_S2

CRITICAL

1

CC718

10UF

20%

6.3V

2

CER-X6S
0402

138S00073

79

1

CC720

150PF

5%
50V

2

CER-C0G
0201

131S00142

P3V3S2_FB_R

1

RC710

0

5%
1/20W
MF
0201

2

117S0201

1

RC711

2.26K

1%
1/20W
MF
201

2

118S0204

CRITICAL

1

RC712

127K

0.1%
1/20W
MF
0201

2

103S0442

CRITICAL

1

RC713

34.8K

0.1%
1/20W
MF
0201-1

2

103S00058

10%
16V
CER

0201

132S00048

SYNC_MASTER=ref_vr_3v3_tps62135

POWER: 3V3 S2

P3V3S2_AGND

PP3V3_S2SW_IPD Load Switch & e-Fuse

D

IPD OCP FaultA

LTSpice

3740

IPD_PWR_EN_GATE

IN

RC833

117S0006

21

MF1/20W5%

P3V3_S2SW_IPD_EN_D

1K

201

RC Delay: 25.5 ms
Current Limit: 490mA
RLIM = 2000 / (490mA - 0.04) = 4.44k (4.42k)

PP3V3_S2

79

CC830

0.1UF

X5R-CERM

RC832

1/20W1% MF

118S0236

DC831

K A

NSR01L30MXT5G-COMBO

371S00062

21

X3DFN2

CC832

0.1UF

X5R-CERM

132S0288

10%
10V

0201

255K

201

10%
16V

0201

1

2

1

2

/FLT Open Drain
Host-Controlled (EN = MPMU GPIO6, 1.8V LVCMOS (PP1V8_AON))
$X1757GHUB/mlb/sim/ltspice/ocp_rc_filters/ocp_filters.asc

B

PP5V_S2SW_IPD Load Switch & e-Fuse

NOSTUFF

CC831

3300PF

10%
10V

X7R-CERM

0201

P3V3_S2SW_IPD_EN

1

2

3
4

2

1

IN
IN

EN/UVLO

DVDT

79 40

PP1V8_AON

UC830

TPS259570

DFN

353S02482

OUT

FLT*

ILM

PP1V8_AON

79 40

10%
25V
X5R

0201

1

2

1

CC861

0.1UF

2

311S0226

74LVC1G08

5

3

SOT553

4

P3V3_AND_P5V_IPD_FLT_L

40

PBUS_AONSW_IPD_FLT_L

IN

1

UC860

2

08

10%
25V
X5R

0201

1

2

311S00290

5

1

A

UC861

2

B

SN74LVC1G00DRL

SOT-5X3

4

Y

3

IPD_OCP_FLT

OUT

35

UC810

CC860

1

RC831

100K

1%
1/20W
MF
201

2

118S0014

5

6

7

P3V3_S2SW_IPD_ILMP3V3_S2SW_IPD_DVDT

1

RC830

4.42K

1%
1/20W
MF
201

2

118S0379

PP3V3_S2SW_IPD

P3V3_S2SW_IPD_FLT_L

79

OUT

40

E

40

IN

40

IN

PP3V3_S2SW_SNS Load Switch

79

P3V3_S2SW_IPD_FLT_L

P5V_S2SW_IPD_FLT_L

PP3V3_S2

0.1UF

CC810

0.1UF

10%

6.3V

CERM-X5R

0201

SLG5AP1569V

2

VIN

2734

SENSOR_PWR_EN

IN

1

ON

STDFN

353S00763

GND

VOUT

3

PP3V3_S2SW_SNS

79

LTSpice

3740

IPD_PWR_EN_GATE

IN

DC841

X3DFN2

KA

P5V_S2SW_IPD_EN_D

NSR01L30MXT5G-COMBO

371S00062

RC843

117S0106

21

470K

MF1/20W5% 201

PP5V_S2

79

RC842

117S0006

RC Delay: 4.7 ms
Current Limit: 1.35A = 1.25A (KBDBKLT) + 100mA (IPD)
RLIM = 2000 / (1.35A - 0.04) = 1.5267k (1.5k)

CC840

0.1UF

X5R-CERM

21

MF1/20W5%

CC842

0.01UF

X5R-CERM

132S0391

10%
10V

0201

1K

201

10%
25V

0201

79 40

1

UC840

2

3

IN

4

IN

P5V_S2SW_IPD_EN

NOSTUFF

P5V_S2SW_IPD_DVDT

10%
10V

0201

1

2

CC841

3300PF

X7R-CERM

1

2

2

1

EN/UVLO

DVDT

353S02482

PP1V8_AON

DFN

OUT

FLT*

ILM

1

RC841

100K

1%
1/20W
MF

201TPS259570

2

118S0014

5

6

7

P5V_S2SW_IPD_ILM

1

RC840

1.5K

1%
1/20W
MF
201

2

118S0104

PP5V_S2SW_IPD

P5V_S2SW_IPD_FLT_L

79

OUT

F

40

PP1V8_S2SW_VDD1 Load Switch

PP3V8_AON_VDDMAIN

79

10%

6.3V
0201

1

2

VDD

UC820

CC820

0.1UF

CERM-X5R

SLG5AP1445V

P1V8_S2_SW_CAP

34

PVDD1_PWR_EN

IN

1

CC821

4700PF

10%
10V

2

X7R
201

CAP

ON S

TDFN8

353S00764

GND

37

D

PP1V8_S2

52

PP1V8_S2SW_VDD1

78

79

/FLT Open Drain
Host-Controlled (EN = MPMU GPIO6, 1.8V LVCMOS (PP1V8_AON))
$X1757GHUB/mlb/sim/ltspice/ocp_rc_filters/ocp_filters.asc

C

3540

PPBUS_AONSW_IPD Load Switch & e-Fuse

PPBUS_AON

79

10%
25V
X5R

0201

0201

10%
10V

0201

1

2

1

2

IPD_PWR_EN

IN

RC852

NOSTUFF

CC850

0.1UF

21

0

MF1/20W5%

CC852

0.1UF

X5R-CERM

PBUS_AONSW_IPD_EN

PBUS_AONSW_IPD_DVDT PBUS_AONSW_IPD_ILM

NOSTUFF

1

2

CC851

3300PF

10%
10V

X7R-CERM

0201

3
4

2

1

IN
IN

EN/UVLO

DVDT

79 40

PP1V8_AON

UC850

TPS259570

DFN

353S02482

OUT

FLT*

ILM

G

1

RC851

100K

1%
1/20W
MF
201

2

118S0014

5

6

7

1

RC850

665

1%
1/20W
MF
201

2

118S0483

PPBUS_AONSW_IPD

PBUS_AONSW_IPD_FLT_L

79

OUT

40

Radar:

IPD_PWR_EN Gating Logic

78 76 37

353738

IN

3540

IN

P5VS2_PWR_EN

IPD_PWR_EN

PP1V8_AON_MPMU

2

B

UC870

1

A

NC

5

RC870

5%

0

311S00008

6

74LVC1G08FW5

DFN1010

Y

3

21

NOSTUFF

4

0201MF1/20W

Power: Load Switches

NOSTUFF

BYPASS=UC870::5MM

1

CC870

0.1UF

10%

6.3V

2

CERM-X5R
0201

IPD_PWR_EN_GATE

OUT

37 40

Current Limit: 3A
RLIM = 2000 / (3A - 0.04) = 676 (665)
/FLT Open Drain
Self-Controlled (EN = 3.13V to 5.93V)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

78

PP1V25_S2

SIO I2C0

SIO I2C1

DEVICE DEV WR RD

------ ---- ---- ---­ACE 0 0x38 0x70 0x71

ACE 1 0x3F 0x7E 0x7F

DEVICE DEV WR RD

------ ---- ---- ---­SPKR AMP L 0x31 0x62 0x63

1

RD000

1.5K

5%
1/20W
MF
201

2

MAKE_BASE=TRUE

7

7

BI

7

78

I2C_UPC_SCL

IN

I2C_UPC_SDA

MAKE_BASE=TRUE

UPC_I2C_INT_L

OUT

MAKE_BASE=TRUE

PP1V25_AWAKE_IO

1

CD010

0.1UF

20%
16V

2

X6S
0201

SOC has internal pull-up.

1

RD001

1.5K

5%
1/20W
MF
201

2

1

RD010

1.5K

5%
1/20W
MF
201

2

1

RD011

1.5K

5%
1/20W
MF
201

2

I2C_UPC_SCL
I2C_UPC_SCL

I2C_UPC_SDA
I2C_UPC_SDA

UPC_I2C_INT_L
UPC_I2C_INT_L

UD010

LSF0101DRY

SON

6

EN

VER-2

1

RD012

2.2K

5%
1/20W
MF
201

2

BI
BI

OUT
OUT

IN
IN

1

RD013

2.2K

5%
1/20W
MF
201

2

53 55

56

53 55

56

53 55

56

PP1V8_AWAKE

78

SIO I2C2

DEVICE DEV WR RD

------ ---- ---- ----

7

7

BI

7

7

BI

I2C_SPKRAMP_L_SCL

IN

I2C_SPKRAMP_L_SDA

NC_I2C_CODEC_SCL

IN

NC_I2C_CODEC_SDA

5 2

VREF_B

4 3

INB

VREF_A

GND

NC_I2C_CODEC_SCL

MAKE_BASE=TRUE

NC_I2C_CODEC_SDA

MAKE_BASE=TRUE

INA

I2C_1V8_SPKRAMP_L_SCL

MAKE_BASE=TRUE

I2C_1V8_SPKRAMP_L_SDA

MAKE_BASE=TRUE

I2C_1V8_SPKRAMP_L_SCL
I2C_1V8_SPKRAMP_L_SDA

OUT

BI

74

74

UNUSED

SIO I2C3

SIO I2C4

DEVICE DEV WR RD

------ ---- ---- ---­SPKR AMP R 0x34 0x68 0x69
CODEC 0x48 0x90 0x91

DEVICE DEV WR RD

------ ---- ---- ----

78

PP1V25_AWAKE_IO

1

RD030

1.5K

5%
1/20W
MF
201

2

1

RD031

1.5K

5%
1/20W
MF
201

2

I2C_SPKRAMP_R_CODEC_SCL

MAKE_BASE=TRUE

IN

7

BI

I2C_SPKRAMP_R_CODEC_SDA

I2C_SPKRAMP_R_CODEC_SCLI2C_SPKRAMP_R_CODEC_SCL
I2C_SPKRAMP_R_CODEC_SDA

OUT

BI

507

50

I2C_SPKRAMP_R_CODEC_SDA

MAKE_BASE=TRUE

Both CODEC and Right-side Speaker Amp

DISP I2C

DEVICE DEV WR RD

------ ---- ---- ---­LP8549 0x2C 0x58 0x59

7

7

BI

NC_I2C_DFR_SCL

IN

NC_I2C_DFR_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_I2C_DFR_SCL
NC_I2C_DFR_SDA

UNUSED

78

8

8

BI

PP1V25_AWAKE_IO

I2C_DISP_BKLT_SCL

IN

I2C_DISP_BKLT_SDA

1

CD050

0.1UF

20%
16V

2

X6S
0201

1

RD050

1.5K

5% 5%
1/20W
MF
201

2

1

RD051

1.5K

1/20W
MF
201

2

VREF_A VREF_B

CMN_IC

3

A1

4

A2 B2

I2C_DISP_BKLT_SCL
I2C_DISP_BKLT_SDA

MAKE_BASE=TRUE
MAKE_BASE=TRUE

VBIAS_I2CBKLT

UD050

LSF0102

X2SON

GND

EN

B1

1

RD054

200K

5%
1/20W
MF
201

8

6

5

2

1

CD051

0.1UF

20%
16V

2

X6S
0201

1

RD052

1.8K

5%
1/20W
MF
201

2

PP3V3_SW_LCD

1

RD053

1.8K

5%
1/20W
MF
201

2

I2C_MLB2JERRY_3V3_SCL
I2C_MLB2JERRY_3V3_SDA

79

SYNC_MASTER=T668 SYNC_DATE=08/01/2019

PAGE TITLE

67

OUT

BI

67

I2C: SIO, DISP

Apple Inc.

DRAWING NUMBER

051-05392

REVISION

SIZE

D

BOM_COST_GROUP=SMC

ISP I2C0

ISP I2C1

DEVICE DEV WR RD

------ ---- ---- ----

DEVICE DEV WR RD

------ ---- ---- ----

UNUSED

ISP I2C2

DEVICE DEV WR RD

------ ---- ---- ---­CAMERA 0x10 0x20 0x21
IMAGE SENSOR 0x36 0x6C 0x6D

UNUSED

78

8

IN

8

BI

PP1V25_S2

I2C_CAM_SDA

1

CD120

0.1UF

20%
16V

2

X6S
0201

1

RD120

1.5K

5%
MF

201

2

1

RD121

1.5K

5%
1/20W1/20W
MF
201

2

UD120

LSF0101DRY

SON

6

EN

5 2

VREF_B

4 3

INB

VER-2

VREF_A

INA

GND

1

RD122

2.2K

5%
1/20W
MF
201

2

1

RD123

2.2K

5%
1/20W
MF
201

2

PP1V8_S2

MAKE_BASE=TRUE

I2C_CAM_1V8_SCLI2C_CAM_SCL
I2C_CAM_1V8_SDA

MAKE_BASE=TRUE

78

I2C_CAM_1V8_SCL
I2C_CAM_1V8_SDA

OUT

BI

66

66

ISP I2C3

DEVICE DEV WR RD

------ ---- ---- ----

AOP I2C0

DEVICE DEV WR RD

------ ---- ---- ---­ALS 0x29 0x52 0x53

UNUSED

78

10

IN

10

BI

PP1V25_S2

I2C_AOP_ALS_SCL
I2C_AOP_ALS_SDA

I2C_AOP_ALS_SCL
I2C_AOP_ALS_SDA

MAKE_BASE=TRUE
MAKE_BASE=TRUE

1

CD140

0.1UF

20%
16V

2

X6S
0201

1

RD140

1.5K

5%
MF

201

2

1

RD141

1.5K

5%
1/20W1/20W
MF
201

2

UD140

LSF0101DRY

SON

6

EN

5 2

VREF_B

4 3

INB

VER-2

VREF_A

INA

GND

1

RD142

2.2K

5%
1/20W
MF
201

2

1

RD143

2.2K

5%
1/20W
MF
201

2

PP1V8_S2

MAKE_BASE=TRUE

I2C_ALS_1V8_SCL
I2C_ALS_1V8_SDA

MAKE_BASE=TRUE

78

I2C_ALS_1V8_SCL
I2C_ALS_1V8_SDA

OUT

BI

67

67

AOP I2C1

DEVICE DEV WR RD

------ ---- ---- ----

SYNC_MASTER=T668

PAGE TITLE

10

10

BI

NC_I2C_AOP_ENET_SCL

IN

NC_I2C_AOP_ENET_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_I2C_AOP_ENET_SCL

NO_TEST=1

NC_I2C_AOP_ENET_SDA

NO_TEST=1

UNUSED

I2C: ISP, AOP

Apple Inc.

45

SMC I2C0

DEVICE DEV WR RD

------ ---- ---- ---­CHARGER 0x09 0x12 0x13

BMU 0x0B 0x16 0x17

78 43

10 23

IN

10

I2C_SMC_PWR_SCL
I2C_SMC_PWR_SDA

PP1V25_S2

1

CD200

0.1UF

20%
16V

2

X6S
0201

1

RD200

10K 10K

5%
1/20W
MF
201 201

2

I2C_SMC_PWR_SCL I2C_SMC_PWR_1V8_SCL
I2C_SMC_PWR_SDA

MAKE_BASE=TRUE

1

RD201

5%
1/20W
MF

2

UD200

LSF0101DRY

SON

6

EN

5 2

VREF_B

4 3

INB

VER-2

VREF_A

INA

GND

1

RD202

2.2K

5%
1/20W
MF
201

2

1

RD203

2.2K

5%
1/20W
MF
201

2

RD206

MAKE_BASE=TRUE

78 43

PP1V25_S2

VREF_A VREF_B

UD201

LSF0102

3

A1

4

A2 B2

X2SON

GND

VBIAS_I2CPWR

8

EN

6

B1

5

1

CD201

0.1UF

20%
16V

2

X6S
0201

200K

MF 201

5%

21

PP1V8_S2

MAKE_BASE=TRUE

I2C_SMC_PWR_1V8_SCL
I2C_SMC_PWR_1V8_SDA

MAKE_BASE=TRUE

PP3V3_S2

1/20W

PP3V3_AON

2

RD207

4.7K 4.7K

5%
1/20W

MF
201 201

1

2

RD208

5%
1/20W

MF

1

I2C_SMC_PWR_3V3_SCL

MAKE_BASE=TRUE

I2C_SMC_PWR_3V3_SDA

MAKE_BASE=TRUE

78

I2C_SMC_PWR_1V8_SDA

79

79

I2C_SMC_PWR_3V3_SCL
I2C_SMC_PWR_3V3_SDA

BI

BI

OUTBI

22 82

22 82

BI

23

SMC I2C1

DEVICE DEV WR RD

------ ---- ---- ---­ACE 0 0x38 0x70 0x71

ACE 1 0x3F 0x7E 0x7F

SMC I2C2

78

IN

10

BI

10

OUT

PP1V25_S2

MAKE_BASE=TRUE

I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA

MAKE_BASE=TRUE

UPC_SMC_I2C_INT_L

MAKE_BASE=TRUE

1

RD210

1.5K

5%
1/20W
MF
201

2

1

RD211

1.5K

5%
1/20W
MF
201

2

I2C_SMC_UPC_SCL
I2C_SMC_UPC_SCL

I2C_SMC_UPC_SDA
I2C_SMC_UPC_SDA

UPC_SMC_I2C_INT_L
UPC_SMC_I2C_INT_L

OUT
OUT

IN
IN

BI
BI

53 55

5610

53 55

56

53 55

56

DEVICE DEV WR RD

------ ---- ---- ---­TBD 0x-- 0x-- 0x--

SMC I2C3

DEVICE DEV WR RD

------ ---- ---- ---­PALM TEMP 0x4C 0x98 0x99

10

10

BI

78

NC_I2C_SMC_SNS1_SCL

IN

NC_I2C_SMC_SNS1_SDA

PP1V25_S2

1

RD230

1.5K

5%
1/20W
MF
201

2

1

RD231

1.5K

5%
1/20W
MF
201

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_I2C_SMC_SNS1_SCL
NC_I2C_SMC_SNS1_SDA

UNUSED

SMC I2C4

DEVICE DEV WR RD

------ ---- ---- ---­TBD 0x-- 0x-- 0x--

10 76

10

BI

I2C_SMC_IPD_SCL I2C_SMC_IPD_SCL

IN

I2C_SMC_IPD_SDA

I2C_SMC_IPD_SDA

OUT

BI

76

I2C_SMC_IPD_SCL
I2C_SMC_IPD_SDA

MAKE_BASE=TRUE
MAKE_BASE=TRUE

10

10

BI

NC_I2C_SMC_SNS0_SCL

IN

NC_I2C_SMC_SNS0_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_I2C_SMC_SNS0_SCL
NC_I2C_SMC_SNS0_SDA

I2C: SMC

UNUSED

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

BOM_COST_GROUP=SMC

A

79

79

5V S2 VR High Side Current Sensor (IO5R)

GAIN: 100X, EDP: 2.4 A
RSENSE: 0.01 (RD550) OR SHORT
VSENSE: 24 MV, RANGE: 5.0 A
MPMU, AMUX_B<2>

PPBUS_AON

NO_XNET_CONNECTION=1

PPBUS_5VS2_VIN

RD550

0.01

107S00020

1

1%

1/3W

MF

0306

79 46 45 44

79 46 45 44

PLACE_NEAR=UD550.3:5MM

PP3V3_S2SW_SNS

ISNS_5VS2HS_P

ISNS_5VS2HS_N

432

PLACE_NEAR=UD550.4:5MM

PP3V3_S2SW_SNS

3

4

7

UD550

INA190A3RSW

UQFN

IN+

CRITICAL

IN-

LOADISNS

100X

ENABLE

VS

GND

OUT

REF

NC
NC
NC

10

INA_5VS2HS_IOUT

8

1

NC

2

NC

5

NC

BYPASS=UD550.6::5MM

LOADISNS

1

CD550

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=U8100.F12:5MM

RD558

45.3K

1/20W

1%
MF

201

21

NOSTUFF

RD559

100K

1%

1/20W

MF

201

1

2

P5VS2_HS_ISENSE

1

CD559

2.2UF

20%

6.3V

2

X5R-CERM
0201

VSS_SENSOR_MPMU

D

79

47 47

OUT

GAIN: 0.2067X

DCIN Voltage Sensor (VD0R)

PPDCIN_AONSW

1

RD501

78.7K

1%
1/20W
MF
201

RD502

20.5K

1%

1/20W

MF

201

2

1

2

1

CD501

0.022UF

10%

6.3V

2

X5R-CERM
0201

DCIN_VSENSE

VSS_SENSOR_MPMU

Vnominal: 16.5V, Range: 22.29V
MPMU, AMUX_A<0>

474427

OUT

474427

B

79

79

3V3 S2 VR High Side Current Sensor (IO3R)

GAIN: 100X, EDP: 1 A
RSENSE: 0.05 (RD560) OR SHORT
VSENSE: 50 MV, RANGE: 1.0 A
MPMU, AMUX_B<1>

PPBUS_AON

NO_XNET_CONNECTION=1

PPBUS_3V3S2_VIN

RD560

0.05

107S00017

1

1%

1/3W

MF

0306

79 46 45 44

79 46 45 44

PLACE_NEAR=UD560.3:5MM

PP3V3_S2SW_SNS

ISNS_3V3S2HS_P

ISNS_3V3S2HS_N

432

PLACE_NEAR=UD560.4:5MM

PP3V3_S2SW_SNS

3

4

7

UD560

INA190A3RSW

UQFN

IN+

CRITICAL

IN-

LOADISNS

100X

ENABLE

VS

GND

OUT

REF

NC
NC
NC

10

INA_3V3S2HS_IOUT

8

1

NC

2

NC

5

NC

BYPASS=UD560.6::5MM

LOADISNS

1

CD560

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=U8100.F14:5MM

RD568

45.3K

1/20W

1%
MF

201

21

NOSTUFF

RD569

100K

1/20W

201

P3V3S2_HS_ISENSE

1

1%
MF

2

1

CD569

2.2UF

20%

6.3V

2

X5R-CERM
0201

VSS_SENSOR_MPMU

OUT

E

DCIN Current Sensor (ID0R)

RD518

23

47

Charger Gain: 20x, EDP: 4.2A

CHGR_AMON

IN OUT

4.87K

1/20W

RSENSE: 0.010 (R5220)
MPMU, AMUX_A<1>

F

474427

BMON Current Sensor (IPBR)

1%
MF

201

21

NOSTUFF

RD519

4.87K

1%

1/20W

MF

201

DCIN_ISENSE

1

2

1

CD519

0.022UF

10%

6.3V

2

X5R-CERM
0201

VSS_SENSOR_MPMU

47

474427

C

PPBUS Voltage Sensor (VP0R)

GAIN: 0.2865X
Vnominal: 13.05V, Range: 14.05V
MPMU, AMUX_A<2>

273440

IN

PPBUS_AON

79

SENSOR_PWR_EN

PBUS_VSNS_IN

1%
MF

201

1

2

RD531

100K

1/20W

PBUS_VSNS_EN_L_DIV

1%
MF

201

1

2

RD532

100K

1/20W

PBUS_VSNS_EN_L

XWD530

SM

21

2

1

5

4

QD530

NTUD3169CZ

SOT-963

N-CHANNEL

D

G

S

D

G

S

P-CHANNEL

NOSTUFF

RD530

0

5%

1/20W

MF

0201

21

RD528

4.87K

IN OUT

1/20W

LTSpice:

Charger Gain: 7.9x, EDP: 8.48A
RSENSE: 0.005 (R5260)

6

3

PBUS_VSNS_OUT

RD538

78.7K

1/20W

RD539

31.6K

1/20W

1%
MF

201

1%
MF

201

1

2

PBUS_VSENSE

1

1

CD539

0.022UF

10%

6.3V

2

2

X5R-CERM
0201

VSS_SENSOR_MPMU

OUT

47

474427

MPMU, AMUX_A<3>

1%
MF

201

21

NOSTUFF

RD529

4.87K

1%

1/20W

MF

201

BMON_ISENSECHGR_BMON

1

2

1

CD529

0.022UF

10%

6.3V

2

X5R-CERM
0201

VSS_SENSOR_MPMU

4723

474427

$X1757GHUB/mlb/sim/ltspice/vp0r_sense/vp0r_pbus_vsense_pulse_diodesinc.asc
$X1757GHUB/mlb/sim/ltspice/vp0r_sense/vp0r_pbus_vsense_pulse_onsemi.asc

SENSORS: POWER HIGH SIDE (1/2)

Apple Inc.

A

LCD Backlight High Side Current Sensor (IBLR)

GAIN: 100X, EDP: 0.6 A
RSENSE: 0.025 (RP800) OR SHORT
VSENSE: 15 mV, RANGE: 0.6 A
SPMU AMUX_A<0>

69

IN

69

IN

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

79 46 45 44

PP3V3_S2SW_SNS

PP3V3_S2SW_SNS

3

IN+

4

IN-

7

ENABLE

VS

UD6C0

INA190A3RSW

UQFN

CRITICAL
LOADISNS

100X

GND

OUT

REF

NC
NC
NC

10

INA_LCDBKLT_IOUT

8

1

NC

2

NC

5

NC

BYPASS=UD6C0.6::5MM

LOADISNS

1

CD6C0

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=U7700.B10:5MM

RD6C8

45.3K

1/20W

1%
MF

201

21

NOSTUFF

RD6C9

100K

1%

1/20W

MF

201

1

2

LCDBKLT_HS_ISENSE

LOADISNS

1

CD6C9

2.2UF

20%

6.3V

2

X5R-CERM
0201

VSS_SENSOR_SPMU

OUT

47

47

SENSORS: POWER HIGH SIDE (2/2)

4

A

WLAN BT 3V3 S2 Current Sensor (IW3C)

GAIN: 100X, EDP: 1.5 A
RSENSE: 0.01 (RD810) OR SHORT
VSENSE: 15 mV, RANGE: 1.5 A
SPMU AMUX_B<2>

79

79

PP3V3_S2

PP3V3_S2_WLBT

NO_XNET_CONNECTION=1

RD810

0.01

1%

1/3W

MF

107S00020

0306

79 46 45 44

79 46 45 44

PLACE_NEAR=UD810.3:5MM

1

ISNS_WLBT3V3_P

ISNS_WLBT3V3_N

432

PLACE_NEAR=UD810.4:5MM

PP3V3_S2SW_SNS

PP3V3_S2SW_SNS

3

4

7

UD810

INA190A3RSW

UQFN

IN+

CRITICAL

IN-

LOADISNS

100X

ENABLE

VS

GND

OUT

REF

NC
NC
NC

10

8

1
2
5

NC
NC
NC

BYPASS=UD810.6::5MM

LOADISNS

1

CD810

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=U7700.B9:5MM

RD818

45.3K

1/20W

1%
MF

201

21

RD819

100K

1%

1/20W

MF

201

WLANBT_3V3_ISENSEINA_WLBT3V3_IOUT

OUT

47

LOADISNSNOSTUFF

1

2

1

CD819

2.2UF

20%

6.3V

2

X5R-CERM
0201

VSS_SENSOR_SPMU

47

B

Left Speaker Amplifier Current Sensor (Ixxx)

GAIN: 100X, EDP: 2.6 A
RSENSE: 0.005 (RD820) OR SHORT
VSENSE: 13 mV, RANGE: 3.3 A

79

79

PPBUS_AON

NO_XNET_CONNECTION=1

PPBUS_AON_L_SPKRAMP

RD820

0.005

107S00005

1%

1/3W

MF

0306

1

ISNS_SPKRAMPL_P

ISNS_SPKRAMPL_N

432

1

TP

TP-P4

1

TP

TP-P4

TPD820

TPD821

79

79

C

Keyboard LED 5V Current Sensor (IKBC)

GAIN: 100X, EDP: 0.24 A
RSENSE: 0.05 (RD880) OR SHORT
VSENSE: 12 mV, RANGE: 0.33 A
SPMU AMUX_A<1>

PP5V_S2

PP5V_S2SW_IPD

PP5V_S2SW_KBDLED_ISNS_RIN

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V

79

1/16W

PP5V_S2_KBDLED

NOSTUFF

RD881

0

5% MF 0402

21

RD882

0

21

MF1/16W 04025%

NO_XNET_CONNECTION=1

RD880

0.05

1%

1/3W

MF

107S00017

0306

79 46 45 44

79 46 45 44

PLACE_NEAR=UD880.2:5MM

1

ISNS_KBDLED_P

ISNS_KBDLED_N

432

PLACE_NEAR=UD880.4:5MM

PP3V3_S2SW_SNS

PP3V3_S2SW_SNS

3

IN+

4

IN-

7

ENABLE

VS

UD880

INA190A3RSW

UQFN

CRITICAL
LOADISNS

100X

GND

OUT

REF

NC
NC
NC

10

8

1
2
5

NC
NC
NC

BYPASS=UD880.6::5MM

LOADISNS

1

CD880

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=U7700.A10:5MM

LOADISNS

RD888

45.3K

1/20W

1%
MF

201

21

NOSTUFF

RD889

100K

1%

1/20W

MF

201

1

2

KBDBKLT_5V_ISENSEINA_KBDLED_IOUT

OUT

47

LOADISNS

1

CD889

2.2UF

20%

6.3V

2

X5R-CERM
0201

VSS_SENSOR_SPMU

47

SENSORS: POWER LOW SIDE (1/2)

Apple Inc.

A ADC Input Aliases

SLAVE PMU AMUX ALIASMASTER PMU AMUX ALIAS

44

IN

44

IN

44

IN

44

IN

27

IN

44

IN

44

IN

DCIN_VSENSE

MAKE_BASE=TRUE

DCIN_ISENSE

MAKE_BASE=TRUE

PBUS_VSENSE

MAKE_BASE=TRUE

BMON_ISENSE

MAKE_BASE=TRUE

P3V8AON_IMEAS

MAKE_BASE=TRUE

P3V3S2_HS_ISENSE

MAKE_BASE=TRUE

P5VS2_HS_ISENSE

MAKE_BASE=TRUE

NO_TEST=1

NC_MPMU_AMUX_B3

MAKE_BASE=TRUE

NO_TEST=1

DCIN_VSENSE

DCIN_ISENSE

PBUS_VSENSE

BMON_ISENSE

P3V8AON_IMEAS

P3V3S2_HS_ISENSE

P5VS2_HS_ISENSE

NC_MPMU_AMUX_B3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

34

34

34

34

34

34

34

34

45

IN

46

IN

46

IN

LCDBKLT_HS_ISENSE

MAKE_BASE=TRUE

KBDBKLT_5V_ISENSE

MAKE_BASE=TRUE

NC_SPMU_AMUX_A2

MAKE_BASE=TRUE

NO_TEST=1

NC_SPMU_AMUX_A3

MAKE_BASE=TRUE

NO_TEST=1

NC_SPMU_AMUX_B0

MAKE_BASE=TRUE

NO_TEST=1

NC_SPMU_AMUX_B1

MAKE_BASE=TRUE

NO_TEST=1

WLANBT_3V3_ISENSE

MAKE_BASE=TRUE

NC_SPMU_AMUX_B3

MAKE_BASE=TRUE

NO_TEST=1

LCDBKLT_HS_ISENSE

KBDBKLT_5V_ISENSE

NC_SPMU_AMUX_A2

NC_SPMU_AMUX_A3

NC_SPMU_AMUX_B0

NC_SPMU_AMUX_B1

WLANBT_3V3_ISENSE

NC_SPMU_AMUX_B3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

30

30

30

30

30

30

30

30

B

SOC Sense Lines

12

IN

12

IN

12

IN

12

IN

12

IN

12

IN

VSNS_VDD_PCPU

VSNS_VSS_PCPU

VSNS_VDD_GPU

VSNS_VDD_SOC

VSNS_VDD_ECPU

VSNS_VDD_DISP

PPE0A1

P4MM

SM

1

PP

PPE0A2

P4MM

SM

1

PP

PPE0A3

P4MM

SM

1

PP

PPE0A4

P4MM

SM

1

PP

PPE0A5

P4MM

SM

1

PP

PPE0A6

P4MM

SM

1

PP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PPE0A7

P4MM

SM

12

IN

12

IN

12

IN

12

IN

12

IN

12

IN

VSNS_VDD2_1

VSNS_VSS_1

VSNS_VDD2_2

VSNS_VSS_2

VSNS_VDD_DCS

VSNS_VSS_DDR

1

PP

PPE0A8

P4MM

SM

1

PP

PPE0A9

P4MM

SM

1

PP

PPE0AA

P4MM

SM

1

PP

PPE0AB

P4MM

SM

1

PP

PPE0AC

P4MM

SM

1

PP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PLACE_SIDE=TOP

PPE0AE

P4MM

SM

1

PLACE_NEAR=PPE0A3:2MM

PLACE_SIDE=TOP

PP PP

PPE0AF

P4MM

SM

1

PLACE_SIDE=TOP

12

IN

C I/V Sensor Ground Reference Aliases

Master PMU ADC Ground Alias

XWE010

SM

44 27

VSS_SENSOR_MPMU

VSS_SENSOR_MPMU

MAKE_BASE=TRUE

21

VSS_ANA_MPMU

35

VSNS_VDDQL

PPE0AD

P4MM

SM

1

PP

PLACE_SIDE=TOP

Slave PMU ADC Ground Alias

VSS_SENSOR_SPMU

46

VSS_SENSOR_SPMU

45

VSS_SENSOR_SPMU

46

VSS_SENSOR_SPMU

MAKE_BASE=TRUE

XWE020

SM

21

VSS_ANA_SPMU

31

SENSORS: POWER SUPPORT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

Master PMU TDEV1 (Txxx)A

Master PMU TDEV5 (TPMP)F

J

Slave PMU TDEV1 (Txxx)

Location: 3.8V AON VR

NC_MPMU_TDEV1

MAKE_BASE=TRUE

NC_MPMU_TDEV1

OUT

34

B Master PMU TDEV2 (Txxx)

Location: SoC back side ?

NC_MPMU_TDEV2

MAKE_BASE=TRUE

NC_MPMU_TDEV2

OUT

34

G

Location: Master PMU Proximity

1

RE151

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

MPMU_TDEV5

PLACE_NEAR=U8100.G9:5MM

1

CE151

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

VSS_ANA_MPMU

OUT

Master PMU TDEV6 (Txxx)

Location: NAND, TBD

NC_MPMU_TDEV6

MAKE_BASE=TRUE

NC_MPMU_TDEV6

OUT

34

Location: TBD

34

NC_SPMU_TDEV1

MAKE_BASE=TRUE

NC_SPMU_TDEV1

OUT

30

Slave PMU TDEV2 (TH0T)K

48353433

Location: NAND Proximity

THMSNS_SPMU2_P

1

RE1C1

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

THMSNS_SPMU2_N

PLACE_NEAR=XWE1C1.1:2MM

1

CE1C1

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

XWE1C1

SM

21

NO_XNET_CONNECTION=1

PLACE_NEAR=U7700.A5:5MM

XWE1C2

SM

21

NO_XNET_CONNECTION=1

SPMU_TDEV2

THMSNS_SPMU_VSS

48

OUT

30

E

Master PMU TDEV3 (TIOP)C

Location: Thunderbolt Proximity

XWE131

SM

SM

21

21

MPMU_TDEV3

THMSNS_MPMU_VSS

THMSNS_MPMU3_P

1

RE131

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

THMSNS_MPMU3_N

PLACE_NEAR=XWE131.1:2MM

1

CE131

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

PLACE_NEAR=U8100.F8:5MM

XWE132

NO_XNET_CONNECTION=1

Master PMU TDEV4 (TWOP)D

Location: Wireless Proximity

XWE141

SM

SM

21

21

MPMU_TDEV4

THMSNS_MPMU_VSS

THMSNS_MPMU4_P

1

RE141

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

THMSNS_MPMU4_N

PLACE_NEAR=XWE141.1:2MM

1

CE141

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

PLACE_NEAR=U8100.F7:5MM

XWE142

NO_XNET_CONNECTION=1

Master/Slave PMU VSS Connection

PLACE_NEAR=U8100.J11:5MM

XWE100

SM

21

48

THMSNS_MPMU_VSS

PLACE_NEAR=U7700.C6:5MM

VSS_ANA_MPMU

48353433

48

48

OUT

OUT

L

Master PMU TDEV7 (TCHP)H

Slave PMU TDEV3 (Txxx)

Location: TBD

Location: Charger Proximity

34

THMSNS_MPMU7_P MPMU_TDEV7

1

RE171

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

PLACE_NEAR=XWE171.1:2MM

1

CE171

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

PLACE_NEAR=U8100.G8:5MM

THMSNS_MPMU7_N

XWE171

SM

21

NO_XNET_CONNECTION=1

XWE172

SM

21

NO_XNET_CONNECTION=1

THMSNS_MPMU_VSS

48

OUT

34

NC_SPMU_TDEV3

MAKE_BASE=TRUE

Slave PMU TDEV4 (TSCD)M

Location: SOC Proximity

THMSNS_SPMU4_P

1

RE1E1

I Master PMU TDEV8 (TMVR)

Location: Main VR (PP3V8_AON_VDDMAIN)

34

THMSNS_MPMU8_P

1

RE181

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

PLACE_NEAR=XWE181.1:2MM

1

CE181

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

PLACE_NEAR=U8100.G7:5MM

THMSNS_MPMU8_N THMSNS_MPMU_VSS

XWE181

SM

21

NO_XNET_CONNECTION=1

XWE182

SM

21

NO_XNET_CONNECTION=1

MPMU_TDEV8

48

OUT

34

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

THMSNS_SPMU4_N

Slave PMU TDEV5 (TPSP)N

Location: Slave PMU Proximity

THMSNS_SPMU5_P

1

RE1F1

10KOHM-1%-0.31MA

0201

NO_XNET_CONNECTION=1

2

THMSNS_SPMU5_N

NC_SPMU_TDEV3

PLACE_NEAR=XWE1E1.1:2MM

1

CE1E1

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

PLACE_NEAR=XWE1F1.1:2MM

1

CE1F1

100PF

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

30

OUT

XWE1E1

SM

21

NO_XNET_CONNECTION=1

PLACE_NEAR=U7700.B7:5MM

XWE1E2

SM

21

NO_XNET_CONNECTION=1

XWE1F1

SM

21

NO_XNET_CONNECTION=1

PLACE_NEAR=U7700.B6:5MM

XWE1F2

SM

21

NO_XNET_CONNECTION=1

SPMU_TDEV4

THMSNS_SPMU_VSS

SPMU_TDEV5

THMSNS_SPMU_VSS

48

48

OUT

OUT

30

30

XWE1A0

SM

48

THMSNS_SPMU_VSS

21

VSS_ANA_SPMU

3130

PAGE TITLE

Sensors: Thermal

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

OPEN ITEMS:

FERRITE IS PLACEHOLDER ONLY
J417 USES 1555S0686 (01005)
MUST FIND PROPER PART, IF ONE IS NEEDED AT ALL

WHAT DOES SM SCAN MODE PIN DO AND WHY IS IT GROUNDED ON J417?

78 49

PP1V8_S2

RE403

SPI_GYRO_CS_1V8_L

49

GYRO_INT_1V8

49

GYRO_MOTION_INT_1V8

49

100K

5%

1/20W

MF

201

KOBOL: ACCEL & GYRO

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

120OHM-25%-0.25A-0.5OHM

PP1V8_S2_IMU_FILT

1

CE400

0.1UF

10%
10V

2

X5R-CERM
0201

5%

1/20W

MF

201

1

2

1

RE400

100K

5%
1/20W
MF
201

2

VDD

VDDIO

1

RE404

100K

2

1

CE401

0.1UF

10%
10V

2

X5R-CERM
0201

1

CE402

2.2UF

20%
10V

2

X5R
0201

UE400

BMI282AA

LGA

5

CS*

15

SM

INT

7

MOTION_INT

CMN_IC

GND

SCLK

MOSI
MISO

2

SPI_AOP_SENSOR_CLK_1V8

3

SPI_AOP_SENSOR_MOSI_1V8

46

SPI_AOP_SENSOR_MISO_1V8_R

FLE400

0201

49

49

21

PP1V8_S2

7849

RE401

20

5%

1/20W

MF

201

21

SPI_AOP_SENSOR_MISO_1V8

RE405

47K

5%

1/20W

MF

201

49

1

2

78 49

49

78 49

PP1V25_S2

1

CE411

0.1UF

10%
10V

2

X5R-CERM
0201

SPI_AOP_SENSOR_MISO_1V8

PP1V25_S2

SPI LEVEL TRANSLATION

PP1V25_S2

78 49

1

UE411

VCC

2

GND

SN74AUP1G17

SON

4

NC

NC

SPI_AOP_GYRO_MISO

OUT

47K

5%

1/20W

MF

201

1

2

20

RE420

SPI_GYRO_CS_L

10

IN

CE421

0.1UF

10%
10V
X5R-CERM
0201

VCCA VCCB

5

DIR

A

GND

UE4202

SN74AXC1T45

SOT-5X3

43

B

SPI_GYRO_CS_1V8_L

1

2

PP1V8_S2

CE422

0.1UF

10%
10V
X5R-CERM
0201

7849

49

GYRO_INT_1V8

49

78 49

49

PP1V25_S2

1

CE412

0.1UF

10%
10V

2

X5R-CERM
0201

1

CE413

0.1UF

10%
10V

2

X5R-CERM
0201

UE412

VCC

2

GND

SN74AUP1G17

SON

4

NC

NC

GYRO_INT

OUT

10

PLACE_NEAR=UE430:10MM

20

5%

1/20W

MF

201

21

SPI_AOP_SENSOR_CLK_1V8SPI_AOP_SENSOR_CLK_1V8_R

4949

RE436

20

21

RE435

SPI_AOP_SENSOR_MOSI_1V8SPI_AOP_SENSOR_MOSI_1V8_R

5%

1/20W

MF

PLACE_NEAR=UE430:10MM

78 49

UE413

VCC

2

GND

SN74AUP1G17

SON

4

NC

NC

GYRO_MOTION_INTGYRO_MOTION_INT_1V8

OUT

10

20

IN

20

IN

PP1V25_S2

SPI_AOP_GYRO_CLK
SPI_AOP_GYRO_MOSI

RE430

47K

5%

1/20W

MF

201

1

CE431

0.1UF

10%
10V

2

X5R-CERM
0201

5

1

2

RE431

47K

5%

1/20W

MF

201

1

2

201

74AVC2T45

1A
2A

DIR

VCCBVCCA

UE430

VSSOP

GND

1B
2B

PP1V8_S2

1

CE432

0.1UF

10%
10V

2

X5R-CERM
0201

72

SPI_AOP_SENSOR_CLK_1V8_R

63

SPI_AOP_SENSOR_MOSI_1V8_R

4949

7849

49

49

SYNC_MASTER=t668

PAGE TITLE

SENSORS: MOTION

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

RIO Board Connector

502250-8045

F-RT-SM

48
46

1

79 50

507374

IN

75074

OUT

Place at SOC end.

RE954

20

5%
MF

201

21

7

IN

SPI_1V8_TOUCHID_CLK_R

1/20W

41

BI

7380

IN

7380

OUT

75075

OUT

345075

OUT

PP3V8_AON_VDDMAIN

PP1V8_AWAKE

78

SPKRAMP_1V8_RESET_L
SPKRAMP_INT_L
I2C_SPKRAMP_R_CODEC_SCL
TDM_1V8_SPKRAMP_R_FSYNC
TDM_1V8_SPKRAMP_R_D2R

CODEC_INT_L
CODEC_WAKE_L
SPI_1V8_TOUCHID_CLK
SPI_1V8_TOUCHID_MOSI

RE953

20

5%
MF

201

21

7

IN

SPI_1V8_TOUCHID_MOSI_R

1/20W

343582

OUT

750

OUT

7

OUT

79 50

PMU_ONOFF_L
TOUCHID_INT
SPI_1V8_TOUCHID_MISO

PPBUS_AON

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

PP3V8_AON_VDDMAIN

AMR_RIGHT_OR_ND_1V8
TOUCHID_PWR_EN
I2C_SPKRAMP_R_CODEC_SDA
TDM_1V8_SPKRAMP_R_R2D
TDM_1V8_SPKRAMP_R_BCLK
PP1V25_AWAKE_IO

PP1V8_AON
TDM_CODEC_D2R
TDM_CODEC_BCLK
TDM_CODEC_R2D
TDM_CODEC_FSYNC
CODEC_RESET_L

NC_SPKRAMP_ICC
PPBUS_AON

NO_TEST=1

7950

71 72

OUT

50 80

IN

41

BI

73 80

IN

73 80

IN

78

79

7

OUT

10

IN

Place at SOC end.

RE948

20

2 1

5%

1/20W

MF

201

RE945

20

1 2

5%

1/20W

MF

201

TDM_CODEC_BCLK_R

TDM_CODEC_R2D_R

IN

IN

7

7

RE952

20

7950

2 1

5%

1/20W

MF

201

TDM_CODEC_FSYNC_R

IN

7

On RIO Board:

AMR
CODEC
MESA
SPKR AMP

B TOUCHID Power Enable Pull-Up RIO Control CapacitorsC

PP1V25_S2

78 75

1

RE920

47K

5%
1/20W
MF
201

2

TOUCHID_PWR_EN

50 80

1

CE900

100PF

5%
25V

2

C0G
0201

1

CE901

100PF

5%
25V

2

C0G
0201

47
49

518S00155

Mates with 998-11285 or 998-11687
on RIO Flex J0200

TOUCHID_INT
CODEC_INT_L
CODEC_WAKE_L
SPKRAMP_INT_L
SPKRAMP_1V8_RESET_L

1

CE902

100PF

5%
25V

2

C0G
0201

1

CE903

100PF

5%
25V

2

C0G
0201

1

CE904

100PF

5%
25V

2

C0G
0201

7 50

7 50 75

34 50 75

7 50 74

50 73 74

RIO Connector

** OK2INTEGRATE **

6

IN

6

IN

6

IN

6

IN

6

BI

6

BI

6

BI

6

BI

USBC_ATC0_R2D_C_P<1>

USBC_ATC0_R2D_C_N<1>

USBC_ATC0_R2D_C_P<2>

USBC_ATC0_R2D_C_N<2>

USBC_ATC0_D2R_P<1>

USBC_ATC0_D2R_N<1>

USBC_ATC0_D2R_P<2>

USBC_ATC0_D2R_N<2>

USBC HIGH-SPEED AC COUPLING

GND_VOID=TRUE

21

USBC_ATC0_R2D_P<1>

6.3V 0201

20%
X5R

21

USBC_ATC0_R2D_N<1>

20% 6.3V
X5R

21

USBC_ATC0_R2D_P<2>

20%
X5R

21

USBC_ATC0_R2D_N<2>

20%
X5R

21

USBC_ATC0_D2R_C_P<1>

X5R

21

USBC_ATC0_D2R_C_N<1>

20%
X5R

21

USBC_ATC0_D2R_C_P<2>

X5R

21

USBC_ATC0_D2R_C_N<2>

X5R

0201

6.3V

0201

6.3V 0201

0201

6.3V20%

02016.3V

6.3V20%

0201

6.3V

020120%

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CF020

0.22UF

CF021

0.22UF

CF024

0.22UF

CF025

0.22UF

CF022

0.22UF

CF023

0.22UF

CF026

0.22UF

CF027

0.22UF

Caps and connector must be aliased to BBR signals.
Lanes 1 and 2 can be swapped, both pairs, both sides; all or nothing.
Inputs can be polarity inverted independently per pair.
All swaps and inversions must be communicated to TBT Firmware team.

80

80

338S00561

UF000

80

USBC_ATC0_R2D_P<1>

80

80

80

80

80

80

USBC_ATC0_R2D_N<1>

80

USBC_ATC0_R2D_P<2>

80

USBC_ATC0_R2D_N<2>

80

USBC_ATC0_D2R_C_P<1>

80

USBC_ATC0_D2R_C_N<1>

80

USBC_ATC0_D2R_C_P<2>

80

USBC_ATC0_D2R_C_N<2>

80

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

J1
J2

C1
C2

G1
G2

E1
E2

ASSRXP1
ASSRXN1

ASSRXP2
ASSRXN2

ASSTXP1
ASSTXN1

ASSTXP2
ASSTXN2

9999HH

BGA

SYM 1 OF 2

CRITICAL

OMIT_TABLE

BSSRXP1
BSSRXN1

BSSRXP2
BSSRXN2

BSSTXP1
BSSTXN1

BSSTXP2
BSSTXN2

GND_VOID=TRUEGND_VOID=TRUE
GND_VOID=TRUE

J12
J11

GND_VOID=TRUE
GND_VOID=TRUE

C12
C11

GND_VOID=TRUE
GND_VOID=TRUE

G12
G11

GND_VOID=TRUE
GND_VOID=TRUE

E12
E11

USBC0_D2R_P<1>
USBC0_D2R_N<1>

USBC0_D2R_P<2>
USBC0_D2R_N<2>

USBC0_R2D_CR_P<1>
USBC0_R2D_CR_N<1>

USBC0_R2D_CR_P<2>
USBC0_R2D_CR_N<2>

BI
BI

BI
BI

OUT
OUT

OUT
OUT

80

80

80

80

80

80

80

TDI
TMS
TCK
TDO

M10
L10

B8M7
L11

A3
C3
B5
C5

C6
B4
B6
C7

B11
B3

L4
L5

A1
A2

USBC0_AUXLSX_P
USBC0_AUXLSX_N

ATCRTMR01_ACTIVE_READY_3V3
ATCRTMR0_RESET_L

JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR0_TMS
JTAG_ATCRTMR01_TCK
JTAG_ATCRTMR01_TDO

SPI_ATCRTMR0_R_MOSI
SPI_ATCRTMR0_R_MISO
SPI_ATCRTMR0_R_CS_L
SPI_ATCRTMR0_R_CLK

ATCRTMR0_TEST_PWR_GOOD

ATCRTMR0_RBIAS
ATCRTMR0_RSENSE

NC
NC

55

BI

55

BI

51 52 53

IN

53 55 58

IN

53

IN

53

IN

53

IN

53

OUT

53

OUT

53

IN

53

OUT

53

OUT

2 1

4.75K

0.5%
0201

PLACE_NEAR=UF000.L5:2MM
PLACE_NEAR=UF000.L4:2MM

1/20W

RF007

TF

RF006

100

5%

1/20W

MF

201

1

2

6

BI

USBC_ATC0_AUX_P

CF028

0.1UF CERM-X5R

6

BI

USBC_ATC0_AUX_N

CF029

0.1UF

21
10%

21
10%

6.3V 0201

CERM-X5R

02016.3V

58

58

CIO_ATC0_LSTX_3V3

IN

CIO_ATC0_LSRX_3V3

OUT

NOSTUFF

RF028

33K

5%

1/20W

MF

201

1

2

1

RF029

33K

5%
1/20W
MF
201

2

PP3V3_S2SW_USBC0

PP3V3_S2SW_USBC0

100K

5%

1/20W

MF

201

1

2

RF009

RF008

795351

795351

100K

5%

1/20W

MF

201

1

2

USBC_ATC0_AUX_C_P
USBC_ATC0_AUX_C_N

53

535558

535558

53

82

INT_I2C_ATCRTMR0_L

OUT

I2C_UPC0_ATCRTMR0_SCL

BI

I2C_UPC0_ATCRTMR0_SDA

BI

ATCRTMR0_GPIO_5

51

ATCRTMR0_GPIO_6

51

ATCRTMR0_FLASH_SHARE_EN

51

ATCRTMR01_FLASH_MSTR

IN

ATCRTMR0_GPIO_12

51

ATCRTMR0_THERM_DP

OUT

ATCRTMR0_XTAL25M_IN

51

ATCRTMR0_XTAL25M_OUT

51

L8
M8

L7

A10

C9
E7

B9
A8
A4
A5
A6

M11

L9
M9

L12
A11

PA_AUX_P
PA_AUX_N

PA_LSTX_SBU1
PA_LSRX_SBU2

I2C_INT
I2C_SCL
I2C_SDA

POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12

THERMDA

XTAL_25_IN
XTAL_25_OUT

MONDC_SVR
MONDC

INTERNAL CAPS,

PU, PD

IPU ~ 65K

IPU ~ 65K

IPU ~ 65K

To SPI Flash

TEST_PWR_GOOD

BSBU1
BSBU2

PERST*
RESET*

EE_DI

EE_DO
EE_CS*
EE_CLK

TEST_EN

RBIAS
RSENSE

ATEST_P
ATEST_N

100K

NOSTUFF

515253

ATCRTMR01_ACTIVE_READY_3V3

IN

NOSTUFF

NOSTUFF

NOSTUFF

100K

100K

100K

100K

RF050

21

5% MF1/20W 201

RF041

21

5% 1/20W 201

RF051

21

RF043

21

RF045

21

MF

MF5% 1/20W 201

MF 2011/20W5%

MF 2011/20W5%

ATCRTMR0_GPIO_5

ATCRTMR0_GPIO_6

0

21

RF040

1/20W5% MF 0201

ATCRTMR0_FLASH_SHARE_EN

ATCRTMR0_GPIO_12

51

51

51

CF002

CF003

51

ATCRTMR0_XTAL25M_OUT_R

1

20PF

5%

25V

2

C0G

0201
0201

C0G

2

25V

5%

20PF

1

ATCRTMR0_XTAL25M_IN_R

CRITICAL

RF002

0

2 1

0201

5%
1/20WMF

ATCRTMR0_XTAL25M_OUT

YF000

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

RF003

2 1

020105%

1/20WMF

ATCRTMR0_XTAL25M_IN

51

NC
NC
NC
NC

51

M12

A12

J6
L3
J5

TEST_EDM

NC_A12
NC_J6
NC_L3
NC_J5

FORCE_PWR

FLASH_BUSY*

FUSE_VQPS_64

SMBUS_SCL
SMBUS_SDA

338S00561

UF000

PP0V9_ATCRTMR0_SVR

51

3.3V LDO

PP3V8_AON_VDDMAIN

79

59

USBC0_3V3LDO_EN_R

IN

RF012

100K

5%

1/20W

MF

201

1

CF010

1.0UF

2

0201-1

20%

6.3V
X5R

1

2

CRITICAL

1

CF065

20UF

20%

2.5V

2

X6S-CERM
0402

PACK_OPTION=PKGS:SMALL_PITCH

ALLOW_APPLE_PREFIX=U

CRITICAL

1

CF064

20UF

20%

2.5V

2

X6S-CERM
0402

UF015

TLV75533

4

3

X2SON-COMBO

IN

EN

353S02112

GND

OUT

THRM

PAD

CRITICAL

1

CF063

20UF 20UF

20%

2.5V

2

X6S-CERM
0402

1

PP3V3_S2SW_USBC0

1

CF015

1.0UF

20%

6.3V

2

X5R
0201-1

CRITICAL

1

CF062

20%

2.5V

2

X6S-CERM
0402

PACK_IGNORE=TRUE
PACK_OPTION=PKGS:LARGER_PITCH

6

4

1

CF061

4UF 4UF

20%

6.3V

2

CER-X5R
0201

MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750

1

2

UF015

TLV75533

IN OUT

EN

WSON

353S02395

NC

GND EPAD

CF060

20%

6.3V
CER-X5R
0201

CF054

10UF

20%

6.3V
CERM
0402

1

2

1

2

NC

5

NC

20%

6.3V
0201

1

2

1

2

1

2

1

2

CF050

4UF

20%

6.3V
CER-X5R
0201

CF055

2.2UF

X5R-CERM

PP3V3_ATCRTMR0_LC

VOLTAGE=3.3V

CF056

2.2UF

20%

6.3V
X5R-CERM
0201

79

CF051

4UF

20%

6.3V
CER-X5R
0201

VOLTAGE=3.3V

1

CF057

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

CF052

4UF

20%

6.3V

2

CER-X5R
0201

1

CF053

4UF

20%

6.3V

2

CER-X5R
0201

PP0V9_ATCRTMR0_LVR

VOLTAGE=0.9V

PP3V3_ATCRTMR0_ANA
PP0V9_ATCRTMR0_LC

53

VOLTAGE=0.9V

1

CF058

2.2UF

20%

6.3V

2

X5R-CERM
0201

F6
G6
E9
G9

L6
M6

E5
L2
J3

F3
F5
G5

B1

B12

D1
D11
D12

D2

F1
F11
F12

F2

VCC0P9_SVR_ANA

VCC0P9_SVR_PB_ANA

VCC0P9_LVR
VCC0P9_LVR_SENSE

VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC

VSS

VSS_ANA

9999HH

BGA

SYM 2 OF 2

CRITICAL

OMIT_TABLE

VCC3P3_SX

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VSS_ANA

B10

A9
B2

A7
B7

E6

J7

M4
M5

E3
G3

L1
M1

M2
M3

F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2

ATCRTMR0_FORCE_PWR

FLASH_BUSY_USBC01_L

NC_SMBUS_ATCRTMR0_SCL
NC_SMBUS_ATCRTMR0_SDA

VOLTAGE=3.3V

PP3V3_ATCRTMR0_VCCA

1

CF043 2

12PF

5%
25V

2

NP0-C0G
0201

VOLTAGE=3.3V

1

CF032

10UF

20%

6.3V

2

CERM
0402

BYPASS=UF000.M4:M3:3MM

PP0V9_ATCRTMR0_SVR_IND

VOLTAGE=0.9V

_

DIDT=TRUE

XWF030

SM

21

ATCRTMR0_THERM_DN

PLACE_NEAR=UF000.K11:2MM

NO_XNET_CONNECTION=1

CONNECT TO GND PIN
CLOSEST TO THERMDA PIN

53 55

IN

52 53

BI

81

81

1

CF030

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

CF031

10UF

20%

6.3V

2

CERM
0402

PP3V3_ATCRTMR0_SVR

1

CF033

10UF

20%

6.3V

2

CERM
0402

1

CF034

10UF

20%

6.3V

2

CERM
0402

P0V9_ATCRTMR0_SVR_PGND

VOLTAGE=0V

1

CF038

12PF

5%
25V

2

NP0-C0G
0201

1

CF039

4UF

20%

6.3V

2

CER-X5R
0201

CRITICAL

LF000

0.68UH-20%-4.3A-0.043OHM

21

0805

82

OUT

1

CF035

10UF

20%

6.3V

2

CERM
0402

1

CF041

4UF

20%

6.3V

2

CER-X5R
0201

PAGE TITLE

RF000

0

21

402

5%

1/16W

MF-LF

RF001

0

21

5%

1/16W

402

MF-LF

XWF001

NO_XNET_CONNECTION=1

XWF000

PLACE_NEAR=CF032.2:2MM
NO_XNET_CONNECTION=1

1

CF040

47UF

20%

6.3V

2

CER-X5R
0603

USB-C: High Speed ATC0

SM

SM

1

CF036

2.2UF

20%

6.3V

2

X5R-CERM
0201

21

21

FROM USB-C PORT
CONTROLLER (UPC)

PP3V3_S2SW_USBC0

NOSTUFF

1

CF037

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

CF042

47UF

20%

6.3V
CER-X5R
0603

PP3V3_S2SW_USBC0

PP0V9_ATCRTMR0_SVR

VOLTAGE=0.9V

795351

795351

51

SYNC_DATE=04/24/2020SYNC_MASTER=ref_usbc_ace2

BOM_COST_GROUP=TBT

** OK2INTEGRATE **

6

IN

6

IN

6

IN

6

IN

6

BI

6

BI

6

BI

6

BI

USBC_ATC1_R2D_C_P<1>

USBC_ATC1_R2D_C_N<1>

USBC_ATC1_R2D_C_P<2>

USBC_ATC1_R2D_C_N<2>

USBC_ATC1_D2R_N<1>

USBC_ATC1_D2R_P<2>

USBC_ATC1_D2R_N<2>

USBC HIGH-SPEED AC COUPLING

GND_VOID=TRUE

21

USBC_ATC1_R2D_P<1>

20%
X5R

21

USBC_ATC1_R2D_N<1>

X5R

21

USBC_ATC1_R2D_P<2>

20%
X5R

21

USBC_ATC1_R2D_N<2>

20%
X5R

21

USBC_ATC1_D2R_C_P<1>USBC_ATC1_D2R_P<1>

20% 6.3V
X5R

21

USBC_ATC1_D2R_C_N<1>

20%
X5R

21

USBC_ATC1_D2R_C_P<2>

20% 6.3V
X5R

21

USBC_ATC1_D2R_C_N<2>

20% 0201
X5R

02016.3V

6.3V20%

0201

0201

6.3V

02016.3V

0201

6.3V 0201

0201

6.3V

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CF120

0.22UF

CF121

0.22UF

CF124

0.22UF

CF125

0.22UF

CF122

0.22UF

CF123

0.22UF

CF126

0.22UF

CF127

0.22UF

Caps and connector must be aliased to BBR signals.
Lanes 1 and 2 can be swapped, both pairs, both sides; all or nothing.
Inputs can be polarity inverted independently per pair.
All swaps and inversions must be communicated to TBT Firmware team.

80

80

338S00561

UF100

80

USBC_ATC1_R2D_P<1>

80

80

80

80

80

80

USBC_ATC1_R2D_N<1>

80

USBC_ATC1_R2D_P<2>

80

USBC_ATC1_R2D_N<2>

80

USBC_ATC1_D2R_C_P<1>

80

USBC_ATC1_D2R_C_N<1>

80

USBC_ATC1_D2R_C_P<2>

80

USBC_ATC1_D2R_C_N<2>

80

GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

J1
J2

C1
C2

G1
G2

E1
E2

ASSRXP1
ASSRXN1

ASSRXP2
ASSRXN2

ASSTXP1
ASSTXN1

ASSTXP2
ASSTXN2

9999HH

BGA

SYM 1 OF 2

CRITICAL

OMIT_TABLE

BSSRXP1
BSSRXN1

BSSRXP2
BSSRXN2

BSSTXP1
BSSTXN1

BSSTXP2
BSSTXN2

GND_VOID=TRUE

J12
J11

GND_VOID=TRUE
GND_VOID=TRUE

C12
C11

GND_VOID=TRUE
GND_VOID=TRUE

G12
G11

GND_VOID=TRUE
GND_VOID=TRUE

E12
E11

USBC1_D2R_P<1>
USBC1_D2R_N<1>

USBC1_D2R_P<2>
USBC1_D2R_N<2>

USBC1_R2D_CR_P<1>
USBC1_R2D_CR_N<1>

USBC1_R2D_CR_P<2>
USBC1_R2D_CR_N<2>

BI
BI

BI
BI

OUT
OUT

OUT
OUT

80

80

80

80

80

80

80

80

6

BI

6

BI IN

USBC_ATC1_AUX_P

USBC_ATC1_AUX_N

CF128

CF129

0.1UF

RF128

33K

5%

1/20W

MF

201

1

2

1

RF129

33K

5%
1/20W
MF
201

2

PP3V3_S2SW_USBC1

PP3V3_S2SW_USBC1

21
10%

CERM-X5R0.1UF

21
10%

CERM-X5R

795352

795352

6.3V 0201

02016.3V

USBC_ATC1_AUX_C_P
USBC_ATC1_AUX_C_N

58

58

CIO_ATC1_LSTX_3V3
CIO_ATC1_LSRX_3V3

OUT

NOSTUFF

RF108

100K

5%

1/20W

MF

201

1

2

RF109

100K

5%

1/20W

MF

201

1

2

53

535658

535658

53

82

INT_I2C_ATCRTMR1_L

OUT

I2C_UPC1_ATCRTMR1_SCL

BI

I2C_UPC1_ATCRTMR1_SDA

BI

ATCRTMR1_GPIO_5

52

ATCRTMR1_GPIO_6

52

ATCRTMR1_FLASH_SHARE_EN

52

ATCRTMR01_FLASH_SLV_L

IN

ATCRTMR1_GPIO_12

52

ATCRTMR1_THERM_DP

OUT

ATCRTMR1_XTAL25M_IN

52

ATCRTMR1_XTAL25M_OUT

52

L8
M8

L7

A10

C9
E7

B9
A8
A4
A5
A6

M11

L9
M9

L12
A11

PA_AUX_P
PA_AUX_N

PA_LSTX_SBU1
PA_LSRX_SBU2

I2C_INT
I2C_SCL
I2C_SDA

POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12

THERMDA

XTAL_25_IN
XTAL_25_OUT

MONDC_SVR
MONDC

INTERNAL CAPS,

PU, PD

IPU ~ 65K

IPU ~ 65K

IPU ~ 65K

To SPI Flash

TEST_PWR_GOOD

BSBU1
BSBU2

PERST*
RESET*

EE_DI

EE_DO
EE_CS*
EE_CLK

TEST_EN

RBIAS
RSENSE

ATEST_P
ATEST_N

TDI
TMS
TCK
TDO

M10
L10

B8M7
L11

A3
C3
B5
C5

C6
B4
B6
C7

B11
B3

L4
L5

A1
A2

USBC1_AUXLSX_P
USBC1_AUXLSX_N

ATCRTMR01_ACTIVE_READY_3V3
ATCRTMR1_RESET_L

JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR1_TMS
JTAG_ATCRTMR01_TCK
JTAG_ATCRTMR01_TDO

SPI_ATCRTMR1_R_MOSI
SPI_ATCRTMR1_R_MISO
SPI_ATCRTMR1_R_CS_L
SPI_ATCRTMR1_R_CLK

ATCRTMR1_TEST_PWR_GOOD

ATCRTMR1_RBIAS
ATCRTMR1_RSENSE

NC
NC

56

BI

56

BI

51 52 53

IN

56 58

IN

53

IN

53

IN

53

IN

53

OUT

53

OUT

53

IN

53

OUT

53

OUT

2 1

4.75K

0.5%
0201

PLACE_NEAR=UF100.L5:2MM
PLACE_NEAR=UF100.L4:2MM

1/20W

RF107

TF

RF106

100

5%

1/20W

MF

201

1

2

100K

NOSTUFF

515253

ATCRTMR01_ACTIVE_READY_3V3

IN

NOSTUFF

NOSTUFF

NOSTUFF

100K

100K

100K

100K

RF150

21

RF141

21

RF151

21

RF143

21

5% 1/20W 201MF

RF145

21

5% 1/20W 201MF

2015% 1/20W MF

2011/20W5%

MF

0

1

2011/20W5% MF

RF140

ATCRTMR1_GPIO_5

ATCRTMR1_GPIO_6

0201MF5% 1/20W

ATCRTMR1_FLASH_SHARE_EN

ATCRTMR1_GPIO_12

52

52

52

CF102

CF103

52

ATCRTMR1_XTAL25M_OUT_R

1

20PF

5%

25V

2

C0G

0201
0201

C0G

2

25V

5%

20PF

1

ATCRTMR1_XTAL25M_IN_R

CRITICAL

RF102

0

2 1

0201

MF 1/20W

5%

ATCRTMR1_XTAL25M_OUT

YF100

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

RF103

0

2 1

0201

MF 1/20W

5%

ATCRTMR1_XTAL25M_IN

52

NC
NC
NC
NC

52

M12

A12

J6
L3
J5

TEST_EDM

NC_A12
NC_J6
NC_L3
NC_J5

FORCE_PWR

FLASH_BUSY*

FUSE_VQPS_64

SMBUS_SCL
SMBUS_SDA

338S00561

UF100

PP0V9_ATCRTMR1_SVR

52

3.3V LDO VOLTAGE=0.9V

PP3V8_AON_VDDMAIN

79

59

USBC1_3V3LDO_EN_R

IN

RF112

100K

5%

1/20W

MF

201

1

CF110

1.0UF

2

0201-1

20%

6.3V
X5R

1

2

CRITICAL

1

CF165

20UF

20%

2.5V

2

X6S-CERM
0402

PACK_OPTION=PKGS:SMALL_PITCH

ALLOW_APPLE_PREFIX=U

CRITICAL

1

CF164

20UF

20%

2.5V

2

X6S-CERM
0402

UF115

TLV75533

4

3

X2SON-COMBO

IN

353S02112 PACK_IGNORE=TRUE

EN

GND

THRM

PAD

OUT

CRITICAL

1

CF163

20UF

20%

2.5V

2

X6S-CERM
0402

1

PP3V3_S2SW_USBC1

1

CF115

1.0UF

20%

6.3V

2

X5R
0201-1

CRITICAL

1

CF162

20UF 4UF

20%

2.5V

2

X6S-CERM
0402

MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750

PACK_OPTION=PKGS:LARGER_PITCH

6

IN OUT

4

EN

1

2

TLV75533

GND EPAD

CF161

20%

6.3V
CER-X5R
0201

UF115

WSON

1

CF160

2

NC

4UF

20%

6.3V
CER-X5R
0201

CF154

10UF

20%

6.3V
CERM
0402

1

2

NC

5

NC

1

2

1

2

CF150

4UF

20%

6.3V
CER-X5R
0201

CF155

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

2

PP3V3_ATCRTMR1_LC

VOLTAGE=3.3V

1

CF156

2.2UF

20%

6.3V

2

X5R-CERM
0201

79

CF151

4UF

20%

6.3V
CER-X5R
0201

VOLTAGE=3.3V

1

CF157

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

CF152

4UF

20%

6.3V

2

CER-X5R
0201

1

CF153

4UF

20%

6.3V

2

CER-X5R
0201

PP0V9_ATCRTMR1_LVR

VOLTAGE=0.9V

PP3V3_ATCRTMR1_ANA
PP0V9_ATCRTMR1_LC

VOLTAGE=0.9V

1

CF158

2.2UF

20%

6.3V

2

X5R-CERM
0201

F6
G6
E9
G9

L6
M6

E5
L2
J3

F3
F5
G5

B1

B12

D1
D11
D12

D2

F1
F11
F12

F2

VCC0P9_SVR_ANA

VCC0P9_SVR_PB_ANA

VCC0P9_LVR
VCC0P9_LVR_SENSE

VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC

VSS

VSS_ANA

9999HH

BGA

SYM 2 OF 2

CRITICAL

OMIT_TABLE

VCC3P3_SX

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VSS_ANA

B10

A9
B2

A7
B7

E6

J7

M4
M5

E3
G3

L1
M1

M2
M3

F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2

ATCRTMR1_FORCE_PWR

FLASH_BUSY_USBC01_L

NC_SMBUS_ATCRTMR1_SCL
NC_SMBUS_ATCRTMR1_SDA

VOLTAGE=3.3V

PP3V3_ATCRTMR1_VCCA

1

CF143

12PF

5%
25V

2

NP0-C0G
0201

VOLTAGE=3.3V

1

CF132

10UF

20%

6.3V

2

CERM
0402

BYPASS=UF100.M4:M3:3MM

PP0V9_ATCRTMR1_SVR_IND

_

DIDT=TRUE

XWF130

SM

21

ATCRTMR1_THERM_DN

PLACE_NEAR=UF100.K11:2MM

NO_XNET_CONNECTION=1

CONNECT TO GND PIN
CLOSEST TO THERMDA PIN

53 56

IN

51 53

BI

81

81

1

CF130

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

CF131

10UF

20%

6.3V

2

CERM
0402

PP3V3_ATCRTMR1_SVR

1

CF133

10UF

20%

6.3V

2

CERM
0402

1

CF134

10UF

20%

6.3V

2

CERM
0402

P0V9_ATCRTMR1_SVR_PGND

VOLTAGE=0V

1

CF138

12PF

5%
25V

2

NP0-C0G
0201

1

CF139

4UF

20%

6.3V

2

CER-X5R
0201

CRITICAL

LF100

0.68UH-20%-4.3A-0.043OHM

21

0805

82

OUT

RF100

0

21

1/16W5%MF-LF

402

1

CF136

2.2UF

20%

6.3V

2

X5R-CERM
0201

RF101

0

21

402

1

CF135

10UF

20%

6.3V

2

CERM
0402

1

CF141

4UF

20%

6.3V

2

CER-X5R
0201

PAGE TITLE

5%

1/16W

MF-LF

PLACE_NEAR=CF132.2:2MM
NO_XNET_CONNECTION=1

XWF101

SM

21

NO_XNET_CONNECTION=1

XWF100

SM

21

1

CF140

47UF

20%

6.3V

2

CER-X5R
0603

USB-C: High Speed ATC1

NOTICE OF PROPRIETARY PROPERTY:

FROM USB-C PORT
CONTROLLER (UPC)

PP3V3_S2SW_USBC1

NOSTUFF

1

CF137

2.2UF

20%

6.3V

2

X5R-CERM CER-X5R
0201

1

CF142

47UF

20%

6.3V

2

0603

PP3V3_S2SW_USBC1

PP0V9_ATCRTMR1_SVR

VOLTAGE=0.9V

795352

795352

52

SYNC_DATE=04/24/2020SYNC_MASTER=ref_usbc_ace2

BOM_COST_GROUP=TBT

5678

** OK2INTEGRATE **

1

RF260

3.3K

5%
1/20W
MF
201

2

ROM_UPC01_WP_L

53

ROM_UPC01_HOLD_L

NOSTUFF

RF261

3.3K

1/20W

201

RF264

3.3K

1/20W

5%
MF

201

5%
MF

PP3V3_UPC0_LDO 53

RF294

1

2

1

RF263

3.3K

5%
1/20W
MF
201

2

6

CLK

1

CS*

3

WP*(IO2)

7

HOLD*(IO3)

1

2

VCC

UF260

8MBIT-3.0V

W25Q80DVUXIE

USON

OMIT_TABLE

CRITICAL

GND EPAD

DI(IO0)
DO(IO1)

5
2

1

RF262

3.3K

5%
1/20W
MF
201

2

SPI_UPC01_MOSI

53

SPI_UPC01_MISO

53

SPI_UPC01_CLK

53

SPI_UPC01_CS_L

53

1

2

CF260

1UF

10%

6.3V
CERM
402

RF295
RF296
RF297
RF298
RF290
RF291
RF292
RF293
RF299
RF29A
RF29B
RF29C

NO_XNET_CONNECTION=1

100

15
15
15
15
15
15
15
15
15
15
15
15

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

SPI_UPC01_CLK_DBG
SPI_UPC01_R_CLK
SPI_UPC01_R_CS_L
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO
SPI_ATCRTMR0_R_CLK
SPI_ATCRTMR0_R_CS_L
SPI_ATCRTMR0_R_MOSI
SPI_ATCRTMR0_R_MISO
SPI_ATCRTMR1_R_CLK
SPI_ATCRTMR1_R_CS_L
SPI_ATCRTMR1_R_MOSI
SPI_ATCRTMR1_R_MISO

53

53

53

53

53

IN

IN

IN

OUT

IN

IN

IN

OUT

ATC0: I2C_ADDR=GND, I2CM_*_CNFG=1M\u03a9 3V3_LDO_X pull-ups
ATC1: I2C_ADDR=Float, I2CM_*_CNFG=1M\u03a9 3V3_LDO_X pull-ups
ATC2: I2C_ADDR=GND, I2CM_*_CNFG=1M\u03a9 pull-downs

SPI Ace

51

BB

51

51

51

52

52

BB

52

52

51

58

INT_I2C_ATCRTMR0_L

IN

INT_I2C_EUSBLS0_L

IN

ATC3: I2C_ADDR=Float, I2CM_*_CNFG=1M\u03a9 pull-downs

55

56

55

56

GND

OUT

NC_UPC1_I2C_ADDR

OUT

Configure to enable VDDIO and use it for SWD.

GND

OUT

GND

OUT

PP3V3_UPC0_LDO

10K

RF242

21

5% 1/20W MF 201

UPC_ATCRTMR_INT

RF210

5% 1/20W MF 0201

UPC_EUSBLS_INT

RF211

5% 1/20W MF 0201

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

53

FLASH_BUSY_USBC01_L

MAKE_BASE=TRUE

0

21

0

21

NC_UPC1_I2C_ADDR

NO_TEST=1

INT_I2C_UPC0_ATCRTMR0_L

OUT

OUT

51 52 53

53 55

53

53

53

53

53

753

OUT

753

BI

53

PP3V3_S2SW_USBC0

79 51

515253

BI BI BI

SPI_UPC01_R_CLK
SPI_UPC01_R_CS_L
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO
ROM_UPC01_WP_L

SWD_UPC_SWCLK
SWD_UPC_SWDIO0
PP3V3_UPC0_LDO

NOSTUFF

FLASH_BUSY_USBC01_L

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

Master should be on SPI Ace2.

100K

MAKE_BASE=TRUE

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

PACK_OPTION=USBC_SPI_UPC0

RF244

21

5% 1/20W MF 201

Ace 0 is SPI Ace?

SPI_UPC01_R_CLK
SPI_UPC01_R_CS_L
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO

ROM_UPC01_WP_L

SWD_UPC_SWCLK
SWD_UPC_SWDIO0
PP3V3_UPC0_LDO

MAKE_BASE=TRUE

ATCRTMR01_FLASH_MSTR

FLASH_BUSY_USBC01_L

Ace 1 is UART Ace?

PACK_IGNORE=TRUE
PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1

PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1

PACK_OPTION=USBC_SPI_UPC1

53 55

IN

53 55

IN

53 55

IN

53 55

OUT

53 55

IN IN

53 55

IN

53 55

BI

54 55

OUT OUT

Master should be on SPI Ace2.

OUT

51 53

53 55

PP3V3_S2SW_USBC1

79 52

ATCRTMR01_FLASH_MSTR

(Internal pull-up)(Internal pull-up)

NOSTUFF

100K

1 2

MAKE_BASE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE
PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1

PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1

PACK_OPTION=USBC_SPI_UPC1PACK_OPTION=USBC_SPI_UPC1

PACK_OPTION=USBC_SPI_UPC1

PACK_OPTION=USBC_SPI_UPC1

PACK_OPTION=USBC_SPI_UPC1

RF244

5% 1/20W MF 201

GND
GND
GND
GND

PD_UPC1_HPD

SWD_UPC01_UART_CLK
SWD_UPC01_UART_DATA
PP3V3_UPC1_LDO

MAKE_BASE=TRUE

ATCRTMR01_FLASH_SLV_L

PD_UPC1_GPIO1

Ace 1 is SPI Ace?

IN

IN

IN

OUT

IN

BI

OUT

Ace 0 is UART Ace?

53 56

53 56

53 56

53 56

53 56

53 56

53 56

54 56

52 53

53 56

52

58

PP3V3_S2_UPC

55 53
78 56

INT_I2C_ATCRTMR1_L

IN

INT_I2C_EUSBLS1_L

IN

Is UPCx_5V_EN being used?

55

56

UPC0_5V_EN

UPC1_5V_EN

RF220

5% 1/20W MF 201

RF221

5% 1/20W MF 201

RF222

5% 1/20W MF 201

RF223

5% 1/20W MF 201

RF224

5% 1/20W MF 201

UPC_ATCRTMR_INT

RF215

5% 1/20W MF 0201

UPC_EUSBLS_INT

RF216

5% 1/20W MF 0201

10K

10K

100K

100K

10K

21

JTAG_ATCRTMR01_TCK

21

JTAG_ATCRTMR0_TMS

21

JTAG_ATCRTMR1_TMS

21

JTAG_ATCRTMR01_TDI

21

JTAG_ATCRTMR01_TDO

0

21

0

21

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

INT_I2C_UPC1_ATCRTMR1_L

RF234

5% 1/20W MF 201

RF235

5% 1/20W MF 201

PACK_OPTION=USBC01_VR5V_LOCAL_NO

100K

100K

21

21

53 56

OUT

JTAG_ATCRTMR01_TCK

JTAG_ATCRTMR0_TMS
JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR01_TDO

JTAG_ATCRTMR01_TCK

JTAG_ATCRTMR1_TMS
JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR01_TDO

OUT
OUT
OUT

IN

OUT
OUT
OUT

IN

51

51

51

51

52

52

52

52

55 43

55 43

55 43

53

OUT

53

BI

SWD_UPC01_UART_CLK
SWD_UPC01_UART_DATA

RF247
RF272
RF273

SPI Ace

5355

IN

5355

ATCRTMR0_RESET_L

515558

I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA
UPC_SMC_I2C_INT_L
SPI_UPC01_CLK_DBG

53

UART_UPC01_TX
UART_UPC01_RX

OUT

1/20W

5%1/20W MF 201

5%1/20W MF 201

5% MF 201

21

21

21

53

53

UART_UPC01_TX
UART_UPC01_RX

USBC_DBG 505070-1222

SMC

SPI Ace

GND
GND
GND

MAKE_BASE=TRUE

MAKE_BASE=TRUE

2.2K

ATCRTMR01_FLASH_SLV_L

SWD_UPC01_UART_CLK
SWD_UPC01_UART_DATA

100K

100K

MAKE_BASE=TRUE

MAKE_BASE=TRUE

ACE ARKANOID CONN

JF200

M-ST-SM

1413

15

21
43
65
87
109
1211

16

UPC_I2C_INT_L
I2C_UPC_SDA
I2C_UPC_SCL
UPC0_SER_DBG
UPC1_SER_DBG
UART_UPC01_RXUART_UPC01_TX

SPI Ace

PD_UPC1_GPIO1
PD_UPC1_HPD

UART Ace

UART_UPC01_TX
UART_UPC01_RX

SOC

IN

53 56

IN

53 56

IN

53 56

OUT

53 56

IN

53 56

BI

ATCRTMR01_FLASH_SLV_L

52 53

OUT

53 56

BI

53 56

OUT OUT

OUT

IN

53 56

53 56

5356

IN

5356

OUT

RF247
RF272

1/20W

RF273

1/20W MF 2015%

SPI Ace

UART_UPC01_RX
UART_UPC01_TX

1 2

5%1/20W MF 201

5% MF 201

MAKE_BASE=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE

2.2K

21

100K

21

100K

ATCRTMR01_FLASH_MSTR

SPI_UPC01_R_CLKGND
SPI_UPC01_R_CS_L
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO

SWD_UPC_SWCLK
SWD_UPC_SWDIO0

FLASH_BUSY_USBC01_L
ROM_UPC01_WP_L

UART Ace

UART_UPC01_RX
UART_UPC01_TX

IN

IN

IN

OUT

IN

BI

OUT

BI

USBC_DBG

RF280

VREFB_ARDV01

78 56 55 53

5541

555341

555341

55

56

5353

55 53 41

55 53 41

PP1V25_S2

USBC_DBG

CF281

I2C_UPC_SCL
I2C_UPC_SDA

0.1UF

10%

6.3V

CERM-X5R

0201

USBC_DBG

1

2

PACK_OPTION=PKGS:SMALL_PITCH

VREF_A VREF_B

UF280

LSF0102

3

A1

4

A2 B2

X2SON

311S00234

GND

200K

EN

B1

21

MF

1/20W5%201

USBC_DBG

CF280

0.1UF

21

10%

6.3V

8

6

5

CERM-X5R

0201

I2C_UPC01_3V3_SCL
I2C_UPC01_3V3_SDA

PP3V3_S2_UPC

USBC_DBG

RF282

1

5.1K

1/20W

MF

201

2

USBC_DBG

1

RF283

5.1K

5%5%
1/20W
MF
201

2

53 5553 56

53 55

53 55

53 55

53 55

53 55

51 53

53 55

53 55

78 56 55 53

IN

PP1V25_S2

CF230

0.1UF

10%

6.3V

CERM-X5R

0201

1

311S00243

UF230

SN74AXC1T45

2

VCCA VCCB

5

DIR

A

SOT-5X3

B

GND

PP3V3_S2_UPC

43

ATCRTMR01_ACTIVE_READY_3V3PMU_ACTIVE_READY

1

CF231

0.1UF

10%

6.3V

2

CERM-X5R
0201

78565553

51 52 5363482

OUT

HV POWER ALIASES

Fuses for laptop charging.

53 55

OUT

IN

53 55

PACK_OPTION=USBC_LAPTOP

PACK_OPTION=USBC_LAPTOP

CRITICAL

0603-1

FF200

6A-32V

PPDCIN_AONSW

79

78565553

PLACE_NEAR=UF400:5MM

21

PPHV_INT0_AONSW

MAKE_BASE=TRUE

VOLTAGE=20V

CRITICAL

0603-1

FF201

6A-32V

21

PPHV_INT1_AONSW

MAKE_BASE=TRUE

PLACE_NEAR=UF500:5MM

53

PPVBUS_USBC0

53

55

PPVBUS_USBC1

56

VOLTAGE=20V

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE
PACK_OPTION=USBC_DESKTOP

PACK_OPTION=USBC_DESKTOP

RF200

0

5%

1/20W

MF

0201

RF201

0

5%

1/20W

MF

0201

MAKE_BASE=TRUE

MAKE_BASE=TRUE

21

21

Desktops only need connection

for programming OTP.

PPHV_INT0_AONSW

PPHV_INT0_AONSW

PPHV_INT1_AONSW

PPHV_INT1_AONSW

PPVBUS_USBC0
PPVBUS_USBC1

55 57

56 57

55

55

56

56

79 51

79 52

ATCRTMR0_FORCE_PWR

5155

PP3V3_S2SW_USBC0
PP0V9_ATCRTMR0_LC

51

ATCRTMR01_ACTIVE_READY_3V3

515253

PP3V3_S2SW_USBC1
I2C_UPC1_ATCRTMR1_SDA

525658

BRIDGE ARKANOID CONN

JF201

USBC_DBG 505070-1222

15

M-ST-SM

1413

21
43
65
87
109
1211

16

INT_I2C_UPC0_ATCRTMR0_L
I2C_UPC0_ATCRTMR0_SCL
I2C_UPC0_ATCRTMR0_SDA
ATCRTMR1_FORCE_PWR
INT_I2C_UPC1_ATCRTMR1_L
I2C_UPC1_ATCRTMR1_SCL

53 55

51 55 58

51 55 58

52 56

53 56

52 56 58

PACK_IGNORE=TRUE
PACK_OPTION=PKGS:LARGER_PITCH

VREF_BVREF_A

USBC_DBG

UF280

LSF0102

3

A1

4

A2

VSSOP

311S00257

GND

EN

B1

B2

AARDVARKANOID CONN

JF202

USBC_DBG 505070-1222

SPI ACE

78 56 55 53

8

6

5

PP1V25_S2

SWD_UPC_SWDIO0

753

SWD_UPC_SWCLK

753

SPI_UPC01_MISO SWD_UPC01_UART_CLK

53 53

I2C_UPC01_3V3_SDA SWD_UPC01_UART_DATA

53 53

I2C_UPC01_3V3_SCL

53

15

M-ST-SM

1413

21
43
65
87
109
1211

16

SPI_UPC01_CS_L
SPI_UPC01_CLK
SPI_UPC01_MOSI

PP1V25_S2

UART ACE

PAGE TITLE

USB-C: Support 1 ATC01

53

53

53

78565553

SYNC_DATE=04/24/2020SYNC_MASTER=ref_usbc_ace2

BOM_COST_GROUP=USB-C

** OK2INTEGRATE **

Ace 0 is Debug Port?

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0

7

IN

7

OUT

10

BI

10

BI

10

IN

10

OUT

80

BI

80

BI

UART_DEBUGPRT_R2D

MAKE_BASE=TRUE

UART_DEBUGPRT_D2R

MAKE_BASE=TRUE

SWD_SOC_SWCLK

MAKE_BASE=TRUE

SWD_SOC_SWDIO

MAKE_BASE=TRUE

UART_SMC_DEBUGPRT_R2D

MAKE_BASE=TRUE

UART_SMC_DEBUGPRT_D2R

MAKE_BASE=TRUE

USB_DBG_LS_P

MAKE_BASE=TRUE

USB_DBG_LS_N

MAKE_BASE=TRUE

PP1V8_S2
PP1V8_S2

ATC0 / UPC0 / RTMR0

UART_DEBUGPRT_R2D
UART_DEBUGPRT_D2R
SWD_SOC_SWCLK
SWD_SOC_SWDIO
UART_SMC_DEBUGPRT_R2D
UART_SMC_DEBUGPRT_D2R

USB_DBG_LS_P
USB_DBG_LS_N

PP1V8_S2
PP1V8_S2

54 55

IN

54 55

IN

54 55

OUT

54 55

OUT

54 55

OUT

54 55

IN

54 55

BI

54 55

BI

54 55 58

54 58

BI BI

PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1

Ace 1 is Debug Port?

ATC1 / UPC1 / RTMR1

PD_UPC1_DBG0_R
PD_UPC1_DBG1_R
PD_UPC1_DBG2_R
PD_UPC1_DBG3_R
PD_UPC1_DBG4_R
PD_UPC1_DBG5_R

PD_UPC1_USBP2_RP
PD_UPC1_USBP2_RN

PP1V8_S2
PP1V8_S2

OUT

IN

IN

IN

OUT

IN

BI

BI

BIBI

54 56

54 56

54 56

54 56

54 56

54 56

54 56

54 56

54 56 58

54 58

Main Debug Port

Ace2 GPIOs

80

OUT

62082

IN

63482

OUT

SOC_DOCK_CONNECT
SOC_DFU_STATUS

MAKE_BASE=TRUE

SOC_FORCE_DFU

MAKE_BASE=TRUE

SOC_DOCK_CONNECT
SOC_DFU_STATUS
SOC_FORCE_DFU

IN

OUT

IN

54 55

54 55

54 55

PD_UPC1_GPIO7
PD_UPC1_GPIO9
PD_UPC1_GPIO10

OUT

OUT

OUT

54 56

54 56

54 56

Ace 0 is non-debug Port?Ace 1 is non-debug Port?

ATC0 / UPC0 / RTMR0

PP1V8_S2
PP1V8_S2

UART_DEBUGPRT_R2D
UART_DEBUGPRT_D2R
SWD_SOC_SWCLK
SWD_SOC_SWDIO
UART_SMC_DEBUGPRT_R2D
UART_SMC_DEBUGPRT_D2R

BIBI

BI

BI

BI

BI

54 55 58

54 58

54 55

54 55

54 55

54 55

54 55

54 55

Non-debug Port

PP1V8_S2
PP1V8_S2

RF320
RF321
RF322
RF323
RF324
RF325

ATC1 / UPC1 / RTMR1

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PACK_OPTION=USBC_DEBUG_UPC0

PP1V8_S2
PP1V8_S2

21

100K

201MF5%1/20W

21

5% 201MF1/20W

5% 201MF1/20W

5% 201MF1/20W

100K

21

100K

201MF5%1/20W

21

100K

21

100K

201MF5%1/20W

21

100K

PD_UPC1_DBG0_R

MAKE_BASE=TRUE

PD_UPC1_DBG1_R

MAKE_BASE=TRUE

PD_UPC1_DBG2_R

MAKE_BASE=TRUE

PD_UPC1_DBG3_R

MAKE_BASE=TRUE

PD_UPC1_DBG4_R

MAKE_BASE=TRUE

PD_UPC1_DBG5_R

MAKE_BASE=TRUE

PD_UPC1_DBG0_R
PD_UPC1_DBG1_R
PD_UPC1_DBG2_R
PD_UPC1_DBG3_R
PD_UPC1_DBG4_R
PD_UPC1_DBG5_R

54 56 58

54 58

BI BI

54 56

BI BI

54 56

BI

54 56

BI BI

54 56

BI

54 56

BI

54 56

BI

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE

PACK_IGNORE=TRUE
PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

PACK_OPTION=USBC_DEBUG_UPC1

RF310
RF311

5% 201MF1/20W

RF312
RF313

5% 201MF1/20W

RF314
RF315

5% MF1/20W

21

21

21

21

21

21

100K

201MF5%1/20W

100K
100K

201MF5%1/20W

100K
100K

201MF5%1/20W

100K

201

PD_UPC0_DBG0_R

MAKE_BASE=TRUE

PD_UPC0_DBG1_R

MAKE_BASE=TRUE

PD_UPC0_DBG2_R

MAKE_BASE=TRUE

PD_UPC0_DBG3_R

MAKE_BASE=TRUE

PD_UPC0_DBG4_R

MAKE_BASE=TRUE

PD_UPC0_DBG5_R

MAKE_BASE=TRUE

RF328
RF329

RF373
RF374

1/20W 201MF5%

RF375

RF316
RF317

21

100K

201MF5%1/20W

21

5% 201MF1/20W

100K

PD_UPC1_USBP2_RP

MAKE_BASE=TRUE

PD_UPC1_USBP2_RN

MAKE_BASE=TRUE

PD_UPC1_USBP2_RP
PD_UPC1_USBP2_RN

BI

BI

54 56

54 56

RF318
RF319

5% 201MF1/20W

Ace2 GPIOs

100K

21

21

21

201MF5%1/20W

100K
100K

201MF5%1/20W

PD_UPC1_GPIO7

MAKE_BASE=TRUE

PD_UPC1_GPIO9

MAKE_BASE=TRUE

PD_UPC1_GPIO10

MAKE_BASE=TRUE

CKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENETCKPLUS_WAIVE=SINGLE_NODENET

on all nets above.

PD_UPC1_GPIO7
PD_UPC1_GPIO9
PD_UPC1_GPIO10

OUT

OUT

OUT

54 56

54 56

54 56

RF363
RF364

1/20W 201MF5%

RF365

21

100K

201MF5%1/20W

21

100K

PD_UPC0_USBP2_RP

MAKE_BASE=TRUE

PD_UPC0_USBP2_RN

MAKE_BASE=TRUE

USB_DBG_LS_P
USB_DBG_LS_N

BI

BI

54 55

54 55

Ace2 GPIOs

100K

21

21

21

201MF5%1/20W

100K
100K

201MF5%1/20W

PD_UPC0_GPIO7

MAKE_BASE=TRUE

PD_UPC0_GPIO9

MAKE_BASE=TRUE

PD_UPC0_GPIO10

MAKE_BASE=TRUE

on all nets above.

SOC_DOCK_CONNECT
SOC_DFU_STATUS
SOC_FORCE_DFU

OUT

OUT

OUT

54 55

54 55

54 55

Unused ports

21

21

100K
100K

201MF1/20W 5%

5% MF 2011/20W

PD_UPC0_DBG6_R

MAKE_BASE=TRUE

PD_UPC0_DBG7_R

MAKE_BASE=TRUE

PD_UPC0_DBG6_R
PD_UPC0_DBG7_R

BI

BI

55

55

RF326
RF327

21

21

100K
100K

5%1/20W MF 201

5% 2011/20W MF

PD_UPC1_DBG6_R
PD_UPC1_DBG7_R

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PD_UPC1_DBG6_R
PD_UPC1_DBG7_R

BI

BI

56

56

RF31A
RF31B

21

21

100K

201MF5%1/20W

100K

201MF1/20W 5%

PD_UPC0_USBP3_RP

MAKE_BASE=TRUE

PD_UPC0_USBP3_RN

MAKE_BASE=TRUE

PD_UPC0_USBP3_RP
PD_UPC0_USBP3_RN

BI

BI

55

55

RF32A

5% 201MF1/20W

RF32B

1/20W 5% MF 201

21

21

100K
100K

PD_UPC1_USBP3_RP

MAKE_BASE=TRUE

PD_UPC1_USBP3_RN

MAKE_BASE=TRUE

PD_UPC1_USBP3_RP
PD_UPC1_USBP3_RN

BI

BI

56

56

Connections for Desktops (No USBC power in)Connections for Laptops (USBC power in)

PACK_OPTION=USBC_DESKTOPPACK_OPTION=USBC_DESKTOPPACK_OPTION=USBC_DESKTOPPACK_OPTION=USBC_DESKTOPPACK_OPTION=USBC_DESKTOPPACK_OPTION=USBC_DESKTOPPACK_OPTION=USBC_LAPTOPPACK_OPTION=USBC_LAPTOPPACK_OPTION=USBC_LAPTOPPACK_OPTION=USBC_LAPTOPPACK_OPTION=USBC_LAPTOPPACK_OPTION=USBC_LAPTOP

55

55

55

56

56

PP3V3_UPC0_LDO

OUT

BI

BI

OUT

BI

USBC0_CC1
USBC0_CC2

PP3V3_UPC1_LDO

USBC1_CC1

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP3V3_UPC0_LDO

USBC0_CC1

USBC0_CC2

PP3V3_UPC1_LDO

USBC1_CC1

IN

IN

BI

BI

BI

53 55

55 57

55 57

53 56

56 57

MAKE_BASE=TRUE

SYNC_MASTER=ref_usbc_ace2

PAGE TITLE

USB-C: Support 2 ATC01

56

BI

USBC1_CC2

MAKE_BASE=TRUE

USBC1_CC2

BI

56 57

BOM_COST_GROUP=USB-C

** OK2INTEGRATE **

PP3V3_UPC0_LDO

RF409

21

1

1M

10K

100K

1M

100K

100K

RF408

21

1/20W 201MF

5%

RF407

21

5% 1/20W MF

2

RF404

1/20W5% MF

21

RF405

21

RF406

1/20W MF 2015%

21

RF402

5% MF 2011/20W

53 54 55

I2C_UPC0_ATCRTMR0_SCL

MF 2015%1M1/20W

I2C_UPC0_ATCRTMR0_SDA

INT_I2C_UPC0_ATCRTMR0_L

201

UPC_FORCE_PWR

201

2015% 1/20W MF

PD_UPC0_MRESET

PD_UPC0_GPIO5

Either a Testpoint or Arkanoid connector

(EVEN IN PRODUCTION)

Internal Pull-ups
Enabled after reading straps

CKPLUS_WAIVE=I2C_PULLUP

CKPLUS_WAIVE=I2C_PULLUP

PACK_OPTION=ACE2_GPIO6_PD

PACK_IGNORE=TRUE

UART_UPC01_RX

51 53 55 58

51 53 55 58

53 55

5955

5553

55

55

REAR PORT:
FRONT PORT:

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

1

2

RF403

CONNECT UPC SPI TO ROM
GROUND UPC SPI

GND I2C_ADDR

PRIMARY ONLYmust be present for GPIO0

PPHV_INT0_AONSW

53

MAX 100uF TOTAL ON RAIL

PP5V_S2

79 56

PP5V_S2

79 56

CAP FOR PP_5V0 ON VR PAGE

PD_UPC0_MRESET

55

515358

OUT

53

OUT

53

OUT

5355

IN

53

OUT

5153

OUT

5559

IN

54

OUT

3556

OUT

54

IN

54

OUT

ATCRTMR0_RESET_L
UPC0_SER_DBG

FLASH_BUSY_USBC01_L
INT_I2C_UPC0_ATCRTMR0_L
UPC0_5V_EN
ATCRTMR0_FORCE_PWR
PD_UPC0_GPIO5

55

UPC_FORCE_PWR
SOC_DOCK_CONNECT
UPC_PMU_RESET_3V3
SOC_DFU_STATUS
SOC_FORCE_DFU

PP3V3_UPC0_LDO

54

GND

53

UPC0_R_OSC

51535558

BI

51535558

BI

4153

BI

4153

BI

4153

OUT

4353

BI

4353

BI

4353

OUT

53

OUT

53

OUT

53

IN

53

OUT

I2C_UPC0_ATCRTMR0_SDA
I2C_UPC0_ATCRTMR0_SCL

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

I2C_SMC_UPC_SDA
I2C_SMC_UPC_SCL
UPC_SMC_I2C_INT_L

SPI_UPC01_R_CLK
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO
SPI_UPC01_R_CS_L

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

UF400

CD3217B12BCE

FCBGA

DIGITAL CORE I/O & CONTROL POWER

IPU-BOOT

TYPE-C

353S02158

CRITICAL
OMIT_TABLE

VIN_3V3

VDDIO

VDDIO_CFG

LDO_3V3

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

VBUS_OPT

PP_HV_OPT

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

D5

F5

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

CF401

1UF

10%
35V
X5R

0402

CF400

10UF

20%

6.3V
CERM
0402

CF402

1.0UF

20%

6.3V
X5R

0201-1

GND

UPC0_SS

PP1V5_UPC0_LDO_CORE
PPVBUS_USBC0
PPHV_INT0_AONSW

USBC0_CC1

USBC0_CC2

USBC0_CC1
USBC0_CC2

USBC0_USB_TOP_P
USBC0_USB_TOP_N

USBC0_USB_BOT_P
USBC0_USB_BOT_N

USBC0_SBU1
USBC0_SBU2

PPVBUS_USBC0

53 57

1

2

PP3V3_S2_UPC

785653

1

2

PP1V25_S2

1

2

53

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

PP3V3_UPC0_LDO

1

CF408

10UF

20%

6.3V

2

CERM
0402

(cap needed when used as power source)

785653

53 54 55

1

CF403

0.1UF

10%

6.3V

2

CERM-X5R
0201

PP1V8_S2

USBC0_3V3LDO_EN

5854

59

PACK_OPTION=ACE2_SS_CAP

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

53

53

1

CF405

10UF

20%

6.3V

2

CERM
0402

1

CF409

0.68UF

5%

6.3V

2

X6S
0402

PACK_OPTION=ACE2_SS_GND

GND

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

BI

54 57

MIN_LINE_WIDTH=0.4000

BI
BI

BI
BI

BI
BI

BI
BI

MIN_NECK_WIDTH=0.1500

54

54

57

57

57

57

57

57

1

CF414

220PF

5%
50V

2

C0G
0201-1

1

CF413

220PF

5%
50V

2

C0G
0201-1

BI

54 57

53

BI

53

BI

5355

IN

53

OUT

59

BI

59

BI

54

BI

54

BI

54

BI

54

BI

51

BI

51

BI

53

OUT

54

BI

54

BI

54

OUT

54

BI

54

BI

54

BI

54

IN

54

OUT

SWD_UPC_SWDIO0
SWD_UPC_SWCLK

UART_UPC01_RX
UART_UPC01_TX

USB2_UPC0_P1_P
USB2_UPC0_P1_N
USB_DBG_LS_P
USB_DBG_LS_N
PD_UPC0_USBP3_RP
PD_UPC0_USBP3_RN

USBC0_AUXLSX_P
USBC0_AUXLSX_N

ROM_UPC01_WP_L
UART_DEBUGPRT_R2D

UART_DEBUGPRT_D2R
SWD_SOC_SWCLK
SWD_SOC_SWDIO
UART_SMC_DEBUGPRT_R2D

UART_SMC_DEBUGPRT_D2R
PD_UPC0_DBG6_R
PD_UPC0_DBG7_R

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

IPU
IPU

B

GND_OPT
GND_OPT
GND_OPT

GNDPORT_MUX

GND_OPT

GND

C18
E18
D17
G18

BOM_COST_GROUP=USB-C

SYNC_DATE=04/24/2020SYNC_MASTER=ref_usbc_ace2

PAGE TITLE

USB-C: Port Controller ATC0

** OK2INTEGRATE **

PP3V3_UPC1_LDO

1M

1M

10K

100K

1M

100K

100K

RF509

21

RF508

21

5% MF 2011/20W

RF507

21

21

RF504

1/20W

21

RF505

21

RF506

5% 1/20W MF

21

RF502

5% 201MF

1/20W

MF5% 201

MF 2011/20W5%

53 54 56

I2C_UPC1_ATCRTMR1_SCL

2015% MF1/20W

I2C_UPC1_ATCRTMR1_SDA

INT_I2C_UPC1_ATCRTMR1_L

2015% MF1/20W

UPC_FORCE_PWR

PD_UPC1_MRESET

201

PD_UPC1_GPIO5

Either a Testpoint or Arkanoid connector

must be present for GPIO0

(EVEN IN PRODUCTION)

CKPLUS_WAIVE=I2C_PULLUP

CKPLUS_WAIVE=I2C_PULLUP

PACK_OPTION=ACE2_GPIO6_PD

PACK_IGNORE=TRUE

52 53 56 58

52 53 56 58

53 56

5956

5653

56

56

REAR PORT:
FRONT PORT:

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

1

2

RF503

CONNECT UPC SPI TO ROM
GROUND UPC SPI

PRIMARY ONLY

PPHV_INT1_AONSW

53

MAX 100uF TOTAL ON RAIL

PP5V_S2

79 55

PP5V_S2

79 55

CAP FOR PP_5V0 ON VR PAGE

PD_UPC1_MRESET

56

5258

OUT

53

OUT

53

OUT

5356

IN

53

OUT

5253

OUT

5659

IN

54

OUT

3555

OUT

54

IN

54

OUT

ATCRTMR1_RESET_L
UPC1_SER_DBG

PD_UPC1_GPIO1
INT_I2C_UPC1_ATCRTMR1_L
UPC1_5V_EN
ATCRTMR1_FORCE_PWR
PD_UPC1_GPIO5

56

UPC_FORCE_PWRUART_UPC01_TX
PD_UPC1_GPIO7
UPC_PMU_RESET_3V3
PD_UPC1_GPIO9
PD_UPC1_GPIO10

PP3V3_UPC1_LDO

54

NC_UPC1_I2C_ADDR

53

UPC1_R_OSC

52535658

BI

52535658

BI

41

BI

41

BI

41

OUT

43

BI

43

BI

43

OUT

53

OUT

53

OUT

53

IN

53

OUT

I2C_UPC1_ATCRTMR1_SDA
I2C_UPC1_ATCRTMR1_SCL

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

I2C_SMC_UPC_SDA
I2C_SMC_UPC_SCL
UPC_SMC_I2C_INT_L

GND
GND
GND
GND

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

UF500

CD3217B12BCE

FCBGA

DIGITAL CORE I/O & CONTROL POWER

IPU-BOOTGND I2C_ADDR

TYPE-C

353S02158

CRITICAL
OMIT_TABLE

VIN_3V3

VDDIO

VDDIO_CFG

LDO_3V3

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

VBUS_OPT

PP_HV_OPT

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

D5

F5

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

CF501

1UF

10%
35V
X5R

0402

CF500

10UF

20%

6.3V
CERM
0402

CF502

1.0UF

20%

6.3V
X5R

0201-1

GND

UPC1_SS

PP1V5_UPC1_LDO_CORE
PPVBUS_USBC1
PPHV_INT1_AONSW

USBC1_CC1

USBC1_CC2

USBC1_CC1
USBC1_CC2

USBC1_USB_TOP_P
USBC1_USB_TOP_N

USBC1_USB_BOT_P
USBC1_USB_BOT_N

USBC1_SBU1
USBC1_SBU2

PPVBUS_USBC1

53 57

1

2

PP3V3_S2_UPC

785553

1

2

PP1V25_S2

1

2

53

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

PP3V3_UPC1_LDO

1

CF508

10UF

20%

6.3V

2

CERM
0402

(cap needed when used as power source)

785553

53 54 56

1

CF503

0.1UF

10%

6.3V

2

CERM-X5R
0201

PP1V8_S2

USBC1_3V3LDO_EN

5854

59

PACK_OPTION=ACE2_SS_CAP

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

53

53

1

CF505

10UF

20%

6.3V

2

CERM
0402

1

CF509

0.68UF

5%

6.3V

2

X6S
0402

PACK_OPTION=ACE2_SS_GND

GND

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

BI

54 57

MIN_LINE_WIDTH=0.4000

BI

BI

BI
BI

BI
BI

BI
BI

MIN_NECK_WIDTH=0.1500

54

54

57

57

57

57

57

57

1

CF514

220PF

5%
50V

2

C0G
0201-1

1

CF513

220PF

5%
50V

2

C0G
0201-1

BI

54 57

53

BI

53

BI

5356

IN

53

OUT

59

BI

59

BI

54

BI

54

BI

54

BI

54

BI

52

BI

52

BI

53

OUT

54

BI

54

BI

54

OUT

54

BI

54

BI

54

BI

54

IN

54

OUT

SWD_UPC01_UART_DATA
SWD_UPC01_UART_CLK

UART_UPC01_TX
UART_UPC01_RX

USB2_UPC1_P1_P
USB2_UPC1_P1_N
PD_UPC1_USBP2_RP
PD_UPC1_USBP2_RN
PD_UPC1_USBP3_RP
PD_UPC1_USBP3_RN

USBC1_AUXLSX_P
USBC1_AUXLSX_N

PD_UPC1_HPD
PD_UPC1_DBG0_R

PD_UPC1_DBG1_R
PD_UPC1_DBG2_R
PD_UPC1_DBG3_R
PD_UPC1_DBG4_R

PD_UPC1_DBG5_R
PD_UPC1_DBG6_R
PD_UPC1_DBG7_R

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

IPU
IPU

GND_OPT
GND_OPT
GND_OPT

GNDPORT_MUX

GND_OPT

C18
E18
D17
G18

GND

BOM_COST_GROUP=USB-C

SYNC_MASTER=ref_usbc_ace2

PAGE TITLE

USB-C: Port Controller ATC1

---- Reference only ----

Left Rear Port

USBC0_CC1

5455

80

80

80

80

80

80

80

80

USBC0_R2D_CR_N<1>

IN

USBC0_R2D_CR_P<1>

IN

USBC0_D2R_N<1>

OUT

USBC0_D2R_P<1> USBC0_D2R_R_P<1>

OUT

USBC0_SBU2

55

USBC0_USB_BOT_N

55

USBC0_USB_BOT_P

55

2

1

USBC1_USB_BOT_N

56

USBC1_USB_BOT_P

56

USBC1_SBU1

56

USBC1_R2D_CR_P<2>

IN

USBC1_R2D_CR_N<2>

IN

USBC1_D2R_P<2>

OUT

USBC1_D2R_N<2>

OUT

USBC1_CC2

5456

2

1

2

1

2

1

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

PLACE VBUS CAP NEAR EACH VBUS PIN

516S00457

Mates with:

x on y

BYPASS=JF600.57::10MM

BYPASS=JF600.57::10MM

CRITICAL

1

CF620

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.57::10MM

CRITICAL

1

CF626

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

2

BYPASS=JF600.57::10MM

CRITICAL

1

2

CF621

0.01UF

10%
25V
X5R-CERM
0201

CF627

0.01UF

10%
25V
X5R-CERM
0201

BYPASS=JF600.57::10MM

CRITICAL

1

CF622

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.57::10MM

CRITICAL

1

CF628

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.57::10MM

CRITICAL

1

CF623

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.57::10MM

CRITICAL

1

CF625

0.01UF

10%
25V

2

X5R-CERM
0201

PLACE_NEAR=JF600.58:5MM

TVS2200

4

IN

5

IN

6

IN

ALLOW_APPLE_PREFIX=D

DF622

WSON

CRITICAL

K

DZF620

X3-WLB1608-1

SDM2U40CSP

A

PPVBUS_USBC0

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=20V

53 55

(NO LANE REVERSALS ALLOWED)

TPT_USBC0_PP20V

GND_VOID=TRUE

RF661

5% 1/20W MF 201

RF660

5% 1/20W MF 201

GND_VOID=TRUE
GND_VOID=TRUE

RF663

1/20W

5% MF 201

RF662

1/20W

5% MF 201

2

1

2

GND_VOID=TRUE

1

GND_VOID=TRUE

RF680

5% 1/20W MF 201

RF681

5% 1/20W MF 201

GND_VOID=TRUE
GND_VOID=TRUE

RF682

5% 1/20W MF

RF683

5% 1/20W MF 201

2

1

2

GND_VOID=TRUE

1

21

USBC0_R2D_C_N<1>

2

21

USBC0_R2D_C_P<1>

2

21

USBC0_D2R_R_N<1>

2

21

2

2

1

21

USBC1_R2D_C_P<2>

2

21

USBC1_R2D_C_N<2>

2

21

USBC1_D2R_R_P<2>

2

201

21

USBC1_D2R_R_N<2>

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

GND_VOID=TRUE

0.22UF

21CF661

25V10%X5R 0201

0.22UF

21CF660

25V10%X5R 0201

GND_VOID=TRUE
GND_VOID=TRUE

10% 25VCER-X5R 0201

10% 25VCER-X5R 0201

GND_VOID=TRUE

GND_VOID=TRUE

10% 25VX5R 0201

10% 25VX5R 0201

GND_VOID=TRUE
GND_VOID=TRUE

10% 25VCER-X5R 0201

10% 25VCER-X5R 0201

GND_VOID=TRUE

0.33UF

21CF663

0.33UF

21CF662

0.22UF

21CF680

0.22UF

21CF681

0.33UF

21CF682

0.33UF

21CF683

USBC0_R2D_N<1>

USBC0_R2D_P<1>

JF600

20875-056E-01

F-ST-SM

PWR

5857

USBC0_R2D_N<2>

USBC0_R2D_P<2>

USBC0_D2R_CR_N<1>

USBC0_D2R_CR_P<1>

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

1

2

1

2

1

2

1

2

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

USBC1_R2D_P<2>

SIGNAL

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241
4443
4645
4847
5049
5251
5453
5655

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

USBC0_D2R_CR_N<2>

USBC1_R2D_P<1>

USBC1_R2D_N<2>

PWR

6059

USBC1_D2R_CR_P<1>

USBC1_D2R_CR_P<2>

GND

USBC1_D2R_CR_N<2>

1

2

1

2

1

2

1

2

6261
6463
6665
6867
7069
7271
7473
7675
7877
8079
8281
8483
8685

USBC1_D2R_CR_N<1>

1

TP

TP-P4

TPF600

1

2

1

2

1

2

1

2

USBC0_CC2

0.22UF

10% 25VX5R 0201

0.22UF

10% 25VX5R 0201

GND_VOID=TRUE

21 CF691
21 CF690

GND_VOID=TRUE

USBC0_R2D_C_N<2>

USBC0_R2D_C_P<2>

5% 1/20W MF 201

5% 1/20W MF 201

GND_VOID=TRUE

2

2

GND_VOID=TRUE

RF691

21

RF690

21

USBC0_R2D_CR_N<2>

USBC0_R2D_CR_P<2>

USBC0_USB_TOP_P
USBC0_USB_TOP_N

GND_VOID=TRUE

0.33UF

CER-X5R

10% 25V 0201

0.33UF

10% 25V 0201CER-X5R

1

2

1

2

21 CF693
21 CF692

GND_VOID=TRUE

USBC0_D2R_R_N<2>

USBC0_D2R_R_P<2>USBC0_D2R_CR_P<2>

2

1

2

1

5% 1/20W MF 201

5% 1/20W MF 201

2

1

GND_VOID=TRUE

2

2

GND_VOID=TRUE

2

1

RF693

21

RF692

21

2

1

USBC0_D2R_N<2>

USBC0_D2R_P<2>

USBC0_SBU1

2

1

2

1

2

1

USBC1_SBU2

0.22UF

X5R

0.22UF

GND_VOID=TRUE

21 CF670

10%

10%X5R 0201

GND_VOID=TRUE

25V 0201

21 CF671

25V

USBC1_R2D_C_P<1>

USBC1_R2D_C_N<1>

5% 1/20W MF 201

5% 1/20W MF 201

GND_VOID=TRUE

2

2

GND_VOID=TRUE

RF670

21

RF671

21

USBC1_R2D_CR_P<1>

USBC1_R2D_CR_N<1>USBC1_R2D_N<1>

USBC1_USB_TOP_P
USBC1_USB_TOP_N

GND_VOID=TRUE

0.33UF

10% 25VCER-X5R 0201

0.33UF

10% 25VCER-X5R 0201

1

2

1

2

21 CF672
21 CF673

GND_VOID=TRUE

USBC1_D2R_R_P<1>

USBC1_D2R_R_N<1>

2

1

2

1

5% 1/20W MF 201

5% 1/20W MF 201

2

1

GND_VOID=TRUE

2

2

GND_VOID=TRUE

2

1

RF672

21

RF673

21

2

1

USBC1_D2R_P<1>

USBC1_D2R_N<1>

USBC1_CC1

2

1

2

1

2

1

54 55

IN

IN

55

55

OUT

OUT

55

56

IN

IN

56

56

OUT

OUT

54 56

80

80

80

80

80

80

80

80

PPVBUS_USBC1

5356

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=20V

CRITICAL

DZF600

X3-WLB1608-1

SDM2U40CSP

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

BYPASS=JF600.59::10MM

K

PLACE_NEAR=JF600.59:5MM

DF602

TVS2200

WSON

4

A

IN

5

IN

6

IN

CRITICAL

1

CF600

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.59::10MM

CRITICAL

1

CF606

0.01UF

10%
25V

2

ALLOW_APPLE_PREFIX=D

X5R-CERM
0201

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=JF600.59::10MM

CRITICAL

1

CF601

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.59::10MM

CRITICAL

1

CF607

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.59::10MM

CRITICAL

1

2

BYPASS=JF600.59::10MM

CRITICAL

1

2

CF602

0.01UF

10%
25V
X5R-CERM
0201

CF608

0.01UF

10%
25V
X5R-CERM
0201

BYPASS=JF600.59::10MM

CRITICAL

1

CF603

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=JF600.59::10MM

CRITICAL

1

CF605

0.01UF

10%
25V

2

X5R-CERM
0201

TPT_USBC1_PP20V

Cowling Bosses

SHF600

3.1OD1.65ID-1.12H-SM

1

ALLOW_APPLE_PREFIX=SH

860-01443860-01443

3.1OD1.65ID-1.12H-SM

1

TP

TP-P4

SHF601

1

ALLOW_APPLE_PREFIX=SH

TPF601

SYNC_MASTER=ref_usbc_ace2

PAGE TITLE

USB-C: Connector(s)

Left Front Port

BOM_COST_GROUP=USB-C

** OK2INTEGRATE **

79

PP3V3_S2SW_USBC0

1

CF700

0.1UF

10%
10V 10V

2

X5R-CERM
0201

1

CF701

0.1UF

10%

2

X5R-CERM
0201

1

CF702

0.1UF

10%
10V

2

X5R-CERM
0201

VDD1V8VDD3V3

1

2

PP1V8_S2

CF703

0.1UF

10%
10V
X5R-CERM
0201

5854

79

OMIT_TABLE

INT_I2C_EUSBLS1_1V8_L

INT_I2C_EUSBLS0_1V8_L

58

A4

INT

UF700

58

CD2E22

DSBGA

I2C_UPC1_ATCRTMR1_SCL_1V8

I2C_UPC0_ATCRTMR0_SCL_1V8

58

I2C_UPC0_ATCRTMR0_SDA_1V8

58

20

BI

20

BI

EUSB_ATC0_P
EUSB_ATC0_N

A3

A2

A1
B1

SCL

SDA

EDP0
EDN0

GPIO0

GPIO1

DPA
DNA

E2

E3

A5
B5

NC

NC

USB2_ATC0_LS_P
USB2_ATC0_LS_N

BI
BI

80

80

58

I2C_UPC1_ATCRTMR1_SDA_1V8

58

20

BI

20

BI

EUSB_ATC1_P
EUSB_ATC1_N

PP3V3_S2SW_USBC1

1

CF750

0.1UF

10%
10V

2

X5R-CERM
0201

1

2

CF751

0.1UF

10%
10V 10V
X5R-CERM
0201

VDD1V8VDD3V3

1

CF752

0.1UF

10%

2

X5R-CERM
0201

OMIT_TABLE

A4

INT

UF750

CD2E22

DSBGA

A3

A2

A1
B1

SCL

SDA

EDP0
EDN0

GPIO0

GPIO1

DPA
DNA

E2

E3

A5
B5

NC

NC

PP1V8_S2

1

CF753

0.1UF

10%
10V

2

X5R-CERM
0201

5854

USB2_ATC1_LS_P
USB2_ATC1_LS_N

BI
BI

80

80

DPB
DNB

C2

E5
D5

C4C3

NC_USB_LS1P
NC_USB_LS1N

USB_DBG_LS_P
USB_DBG_LS_N

BI

BI

58 80

58 80

CROSS

PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0PACK_OPTION=USBC_DEBUG_UPC0

1058

BI

1058

BI

EUSB_DBG_P

MAKE_BASE=TRUE

EUSB_DBG_N

MAKE_BASE=TRUE

ATCRTMR0_RESET_1V8_L

59

58 54

High:Select 1,8V I2C, GPIOs.

EUSB_DBG_P
EUSB_DBG_N

PP1V8_S2

E1
D1

E4

EDP1
EDN1

RESET*

VIOSEL

DPB
DNB

VPP/VSS

VSS

C2

E5
D5

C4C3

USB_DBG_LS_P
USB_DBG_LS_N

USB_DBG_LS_P
USB_DBG_LS_N

BI

BI

58 80

58 80

PACK_OPTION=USBC_DEBUG_UPC1 PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1PACK_OPTION=USBC_DEBUG_UPC1

1058

BI

1058

BI

EUSB_DBG_P

MAKE_BASE=TRUE

EUSB_DBG_N

MAKE_BASE=TRUE

ATCRTMR1_RESET_1V8_L

58

58 54

High:Select 1,8V I2C, GPIOs.

NC_EUSB_LS1P
NC_EUSB_LS1N

PP1V8_S2

E1
D1

E4

EDP1
EDN1

RESET*

VIOSEL

VSS

CROSS

VPP/VSS

TBT LS RX/TX LEVEL SHIFTERS

PARROT 0 I2C/RESET LEVEL SHIFTERS

RF703

200K

2 1

79 58

PP3V3_S2SW_USBC0

CF710

0.1UF

2 1

10%

6.3V

CERM-X5R

0201

515355

BI

515355

BI

I2C_UPC0_ATCRTMR0_SDA
I2C_UPC0_ATCRTMR0_SCL

MF
1/20W 5% 201

VREFB_EUSBLS0

PACK_OPTION=PKGS:SMALL_PITCH

8

EN

6

B1

5

UF710

LSF0102

X2SON

RF713

VREF_AVREF_B

A1

A2B2

GND

Pull-ups on high-side
do most of the work.

PP1V8_S2

1

5.1K

5%

1/20W

MF

201

2

3

4

1

RF712

5.1K

5%
1/20W
MF
201

2

585554

1

CF711

0.1UF

10%

6.3V

2

CERM-X5R
0201

I2C_UPC0_ATCRTMR0_SDA_1V8
I2C_UPC0_ATCRTMR0_SCL_1V8

78 58

6

IN

58

58

SOC

PP1V25_S2

10%

6.3V
0201

1

2

1

2

CF730

0.1UF

CERM-X5R

CIO_ATC0_LSTX_1V2

RF730

47K

5%

1/20W

MF

201

VCCA VCCB

5

DIR

A

UF730

SN74AXC1T45

SOT-5X3

B

GND

PP3V3_S2SW_USBC0

43

BBR Retimer

1

CF731

0.1UF

10%

6.3V

2

CERM-X5R
0201

CIO_ATC0_LSTX_3V3

OUT

7958

51

79 58

525356

BI

525356

BI

PARROT 1 I2C/RESET LEVEL SHIFTERS

RF753

200K

PP3V3_S2SW_USBC1

CF760

0.1UF

2 1

10%

6.3V

CERM-X5R

0201

I2C_UPC1_ATCRTMR1_SDA
I2C_UPC1_ATCRTMR1_SCL

2 1

5%MF2011/20W

VREFB_EUSBLS1

PACK_OPTION=PKGS:SMALL_PITCH

8

EN

6

B1

5

UF760

LSF0102

VREF_AVREF_B

X2SON

GND

PP1V8_S2

RF763

5.1K

1/20W

3

A1

4

A2B2

Pull-ups on high-side
do most of the work.

1

5%
MF

201

1

2

RF762

5.1K

5%
1/20W
MF
201

2

585654

1

CF761

0.1UF

10%

6.3V

2

CERM-X5R
0201

I2C_UPC1_ATCRTMR1_SDA_1V8
I2C_UPC1_ATCRTMR1_SCL_1V8

58

58

PACK_OPTION=PKGS:LARGER_PITCH

VREF_B VREF_A

8

EN

6

B1

5

B2

CF720

0.1UF

10%

6.3V

CERM-X5R

0201

UF710

LSF0102

VSSOP

GND

1

2

A1

A2

PACK_OPTION=PKGS:SMALL_PITCH

74AUP1G07GF

53

OUT

INT_I2C_EUSBLS0_L INT_I2C_EUSBLS0_1V8_L

NC NC

4

Y A

5

NC NC

PACK_IGNORE=TRUE

3

4

VCC

UF720

SOT891

311S0508

GND

VCC

PP1V8_S2

1

RF720

1.5K

5%
1/20W
MF
201

2

2

1

PACK_IGNORE=TRUE

PACK_OPTION=PKGS:LARGER_PITCH

6

OUT

CIO_ATC0_LSRX_1V2
NOSTUFF

47K

5%

1/20W

MF

201

1

2

RF735

585554

78 58

CF740

0.1UF

10%

6.3V

CERM-X5R

47K

5%

1/20W

MF

201

0201

1

2

58

6

IN

CIO_ATC1_LSTX_1V2

RF740

78 58

SN74AUP1G17

PP1V25_S2

1

2

UF720

74AUP1G07

SOT886

4

PP1V8_S2

10%

6.3V
0201

1

2

UF725

VCC

2

GND

SN74AUP1G17

SON

4

NC

NC

NC

NC

ATCRTMR0_RESET_1V8_LATCRTMR0_RESET_L

CF725

0.1UF

CERM-X5R

5153

IN

55

585554

Y A

5

NC NC

311S00276

GND

59

2

1

NCNC

OUT

NOSTUFF

47K

5%

1/20W

MF

201

1

2

RF745

PP1V25_S2

78 58

SN74AUP1G17

UF745

SON

4 2

NC

1

CF745

0.1UF

10%

6.3V

2

CERM-X5R
0201

VCC

CIO_ATC1_LSRX_3V3CIO_ATC1_LSRX_1V2

NC

GND

PP1V25_S2

UF735

SON

4 2

NC

VCCA VCCB

5

DIR

A

IN

VCC

NC

GND

UF740

SN74AXC1T45

SOT-5X3

GND

526

1

CF735

0.1UF

10%

6.3V

2

CERM-X5R
0201

CIO_ATC0_LSRX_3V3

IN

51

8

6

5

PP1V8_S2

10%

6.3V
0201

1

2

PACK_OPTION=PKGS:SMALL_PITCH

VCC

UF770

74AUP1G07GF

SOT891

4

Y A

5

NC NC

NC NC

311S0508

GND

PACK_IGNORE=TRUE
PACK_OPTION=PKGS:LARGER_PITCH

VCC

2

1

CF770

PP3V3_S2SW_USBC1

1

CF741

0.1UF

10%

6.3V

2

CERM-X5R
0201

43

B

CIO_ATC1_LSTX_3V3

OUT

7958

53

OUT

52

INT_I2C_EUSBLS1_L INT_I2C_EUSBLS1_1V8_L

0.1UF

CERM-X5R

UF770

74AUP1G07

SOT886

Y A

4

1

10%

2

PP1V8_S2

2

VCC

GND

UF775

SN74AUP1G17

SON

4

NC

NC

NC

NC

5

NC NC

GND

ATCRTMR1_RESET_1V8_LATCRTMR1_RESET_L

58

58 56 54

CF765

0.1UF

6.3V

CERM-X5R

0201

5256

IN

2

1

PACK_OPTION=PKGS:LARGER_PITCH

VREF_B VREF_A

EN

B1

B2

NCNC

UF760

LSF0102

VSSOP

GND

1

RF770

1.5K

5%
1/20W
MF
201

2

SYNC_MASTER=ref_usbc_ace2

PAGE TITLE

A1

A2

USB-C: HS Level Shifters

PACK_IGNORE=TRUE

3

4

585654

58

BOM_COST_GROUP=USB-C

RF900

0

5%
MF

0201

21

MAKE_BASE=TRUE

55

USBC0_3V3LDO_EN USBC0_3V3LDO_EN_R

1/20W

RF901

0

5%
MF

0201

21

56

80 55

BI

USBC1_3V3LDO_EN

USB2_ATC0_LS_P

LF400

90-OHM-0.1A

EXCX4CE

SYM _VER -1

1

1/20W

4

USB2_UPC0_P1_P

USBC1_3V3LDO_EN_R

MAKE_BASE=TRUE

BI

USBC0_3V3LDO_EN_R

USBC1_3V3LDO_EN_R

51

OUTIN

52

OUTIN

80

BI

80

BI

80 56

BI

USB2_ATC0_LS_N

PLACE_NEAR=UF400:5MM

LF500

90-OHM-0.1A

EXCX4CE

SYM _VER -1

USB2_ATC1_LS_P

1

USB2_ATC1_LS_N USB2_UPC1_P1_N

PLACE_NEAR=UF500:5MM

32

4

32

USB2_UPC0_P1_N

USB2_UPC1_P1_P

BI

BI

BI

Alias Debug Reset signal to ATC0 Debug Level Shifter (UF700)

55

56

58

BI BI

ATCRTMR0_RESET_1V8_L

MAKE_BASE=TRUE

ATCRTMR0_RESET_1V8_L

58

Tie ACE2 Pin C4 (GPIO6) together and alias to UPC_FORCE_PWR.

720

UPC_FORCE_PWR

MAKE_BASE=TRUE

UPC_FORCE_PWR

UPC_FORCE_PWR

OUTIN

OUT

55

56

PAGE TITLE

USB-C: Project Specific

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

*** OK2INTEGRATE ***

RASPUTIN WIFI/BT MODULE

FOR HOSTINTERFACE TABLES REFER TO:
RDAR://PROBLEM/53187294

FOR DESIGN, DOCUMENTATION,
SYSTEM INTEGRATION QUESTIONS:

RDAR://PROBLEM/44786407

79 60

PP1V8_S2

78

PP3V3_S2_WLBT

1

CL002

10UF

2

10V
X5R-CERM
0402-8

1 CL012

10UF

20%

2

10V
X5R-CERM
0402-8

1

CL021

10UF

20%

2

10V
X5R-CERM
0402-8

CRITICAL

1

CL003

3PF

+/-0.1PF
25V

2

C0G
0201

131S00093

CRITICAL

1

CL013

3PF

+/-0.1PF
25V

2

C0G
0201

131S00093

CRITICAL

1

CL022

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICAL

1

CL004

12PF

5%20%

2

25V
NP0-C0G
0201

CRITICAL

1 CL014

12PF

5%

2

25V
NP0-C0G
0201

CRITICAL

1

CL023

12PF

5%

2

25V
NP0-C0G
0201

CRITICAL

1

CL031

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICAL

1

CL041

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICAL

1

CL051

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICAL

1

CL032

12PF

5%

2

25V
NP0-C0G
0201

CRITICAL

1

CL042

12PF

5%

2

25V
NP0-C0G
0201

CRITICAL

1

CL052

12PF

5%

2

25V
NP0-C0G
0201

PP3V3_S2_WLBT

1

CL033

10UF

20%

2

10V
X5R-CERM
0402-8

1

CL043

10UF

20%

2

10V
X5R-CERM
0402-8

1

CL053

10UF

20%

2

10V
X5R-CERM
0402-8

7960

1

TPL001
TPL002
TPL003

TPL004
TPL005
TPL006
TPL007
TPL008

TPL009

TP

TP-P55

TP

TP-P55

TP

TP-P55

TP

TP-P55

TP

TP-P55

TP

TP-P55

TP

TP-P55

TP

TP-P55

TP

TP-P55

PMU_CLK32K_WLBT

PLACE_SIDE=BOTTOM

WLBT_PWR_EN

1

PLACE_SIDE=BOTTOM

1

WLBT_WAKE

PLACE_SIDE=BOTTOM

1

1

1

1

1

1

TPT_WLAN_JTAG_TCK

TPT_WLAN_JTAG_TMS

TPT_WLAN_JTAG_TDI

TPT_WLAN_JTAG_TDO

TPT_WLAN_JTAG_TRSTN

WLAN_JTAG_SEL

34 60 61

34 60 61

34 60 61

8060

8060

806160

806160

8060

60

PP1V25_S2 7860

CRITICAL

1

CL061

12PF

OMIT_TABLE

UL000

VDDIO_ZONE2

85

LBEE5XV1YR-506

LGA

61

61

6180

76061

OUT

80 60

80 60

80 60

346061

346061

RF_ANT_0

BI

RF_ANT_1

BI

NC_RF_BT_DED

BI

NC
NC

BT_TIME_SYNC_1V8

NC_BT_GPIO_4
BT_R1_TIME_SYNC

60

NC
NC
NC
NC

NC
NC

NC_SPMI_WLBT_CLK_1V8
NC_SPMI_WLBT_DAT_1V8

NC

IN

IN

WLBT_PWR_EN

PMU_CLK32K_WLBT

27
89

44

133
124

37

123

36

38

125

39

126

507
528

517
518

48

76

153

ANT_C0
ANT_C1

BT_DEDICATED

BT_GPIO_1
BT_GPIO_2
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5

BT_I2S_DI
BT_I2S_DO
BT_I2S_CLK
BT_I2S_WS

RF_SW_CTRL_18
RF_SW_CTRL_19

LHL_GPIO0
LHL_GPIO1
LHL_GPIO2

WLBT_REG_ON

CLK_32K

GPIO HW SETTINGS:
VDDIO|RESET|POST-RESET

1.8V|HZ|NP

1.8V|HZ|PD

1.8V|HZ|PD

1.8V|HZ|PU

1.8V|HZ|PU

SYM 1 OF 4

1.8V|HZ|PD

1.8V|HZ|PU

1.8V|HZ|PU

1.8V|HZ|PU

1.8V|HZ|NP

1.8V|HZ|PU

1.8V|HZ|PD

1.2V|HZ|HZ

1.2V|PU|PU

1.2V|HZ|HZ

1.2V|PU|PU

1.8V|HZ|HZ

1.2V|HZ|HZ

1.2V|PU|PU

1.8V|HZ|HZ

1.8V|HZ|HZ

1.8V|HZ|HZ

1.8V|HZ|HZ

1.8V|HZ|HZ

1.2V|HZ|HZ

1.2V

1.2V

WLBT_HOST_WAKE

WL_GPIO_2
WL_GPIO_3
WL_GPIO_4
WL_GPIO_5
WL_GPIO_6
WL_GPIO_7
WL_GPIO_8

WL_GPIO_9
WL_GPIO_10
WL_GPIO_11
WL_GPIO_12
WL_GPIO_13
WL_GPIO_14
WL_GPIO_15
WL_GPIO_16
WL_GPIO_17
WL_GPIO_18
WL_GPIO_19
WL_GPIO_20

PCI_PME_L

PCIE_PERST_L

PCIE_CLKREQ_L

PCIE_RXD_P
PCIE_RXD_N

PCIE_TXD_P
PCIE_TXD_N

145

149
65
64
61
62
134
66
150
67
151
525
161
78
504
160
77
524
503
68

60

127
40

142
143

139
140

WLBT_WAKE

TPT_WLAN_JTAG_TCK
TPT_WLAN_JTAG_TMS

TPT_WLAN_JTAG_TDI 806160
TPT_WLAN_JTAG_TDO 806160

TPT_WLAN_JTAG_TRSTN

UART_WLAN_R2D
UART_WLAN_D2R

UART_WLAN_R2D_RTS_L

UART_WLAN_D2R_CTS_L
WLAN_TIME_SYNC_1V8
WLAN_CONTEXT_A
WLAN_CONTEXT_B

WLBT_RESET_L
WLBT_CLKREQ_R_L

PCIE_WLBT_R2D_P
PCIE_WLBT_R2D_N

PCIE_WLBT_D2R_C_P
PCIE_WLBT_D2R_C_N

2

5%
25V
NP0-C0G
0201

NC

NC
NC
NC
NC
NC
NC

NC

60

60

60

60

60

1

2

OUT

8060

8060

8060

IN

OUT

IN
OUT
OUT

IN

IN

IN

CRITICAL

CL062

3PF

+/-0.1PF
25V
C0G
0201

34 60 61

7 60

7 60

7 60

7 60

60 61

10 60 61

10 60 61

9 60 61

TPL012

TPL013

TPL014

TPL017

TPL018

TPL019

TPL020

TPL021

TPL022

TPL023

TPL024

TPL025

1

TP

TP-P55

1

TP

TP-P55 PACK_OPTION=CARLSBERG

1

TP

TP-P55

1

TP

TP-P55

1

TP

TP-P55

1

TP

TP-P55

1

TP

TP-P55

1

TP

TP-P55

1

TP

TP-P55

1

TP

TP-P55

1

TP

TP-P55 PACK_OPTION=CARLSBERG

1

TP

TP-P55 PACK_OPTION=CARLSBERG

BT_TIME_SYNC_1V8

PLACE_SIDE=BOTTOM

NC_BT_GPIO_4

PACK_IGNORE=TRUE

BT_R1_TIME_SYNC

PACK_IGNORE=TRUE
PACK_OPTION=CARLSBERG

UART_WLAN_R2D

UART_WLAN_D2R

UART_WLAN_R2D_RTS_L

UART_WLAN_D2R_CTS_L

WLAN_TIME_SYNC_1V8

PLACE_SIDE=BOTTOM

WLAN_CONTEXT_A

PLACE_SIDE=BOTTOM

WLAN_CONTEXT_B

PLACE_SIDE=BOTTOM

NC_SPMI_WLBT_CLK_1V8

PACK_IGNORE=TRUE

NC_SPMI_WLBT_DAT_1V8

PACK_IGNORE=TRUE

7 60 61

8060

60 61

7 60

7 60

7 60

7 60

60 61

10 60 61

10 60 61

8060

8060

RASPUTIN BOM TABLE:

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

RASPUTIN ALTERNATE BOM:

PART NUMBER

339S00758 RASPUTIN USI ES6.5UL000ANY339S00763

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

136

PCIE_REFCLK_P
PCIE_REFCLK_N

6061

RL005

RL003

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

CRITICALUL0001339S00763 MODULE, WLAN BT, RASPUTIN, ES6.11, M, LGA549

TABLE_ALT _HEAD

PCIE_WLBT_R2D_C_P

PCIE_WLBT_R2D_C_N

TABLE_ALT _ITEM

9

IN

9

MF 1/20W 201

10K

10K

21

5%

5%

2011/20W MF

21

GND_VOID=TRUE

CL010

0.1UF

10%6.3V 0201

CL009

0.1UF

10%6.3V 0201

GND_VOID=TRUE

WLAN_JTAG_SEL

WLBT_PACKAGE_OPTION_2

NOSTUFF

PLACE_NEAR=UL000.142:4MM

21

CERM-X5R

21

CERM-X5R

PLACE_NEAR=UL000.143:4MM

PCIE_WLBT_R2D_P

PCIE_WLBT_R2D_N

60

WLBT_CLKREQ_R_L

60

60

60

60

60

PCIE_WLBT_D2R_C_P PCIE_WLBT_D2R_P

PCIE_WLBT_D2R_C_N

PCIE_CLK100M_WLBT_P

137

PCIE_CLK100M_WLBT_N

78 60

PP1V25_S2

WLAN_TIME_SYNC_1V8

RL006

RL002

0.1UF

0.1UF

100K

5%

21

2011/20WMF

1K

1/20W MF

5%

CL008

10%

CL007

6.3V 10%

GND_VOID=TRUE

21

02016.3V

21

0201

201

21

CERM-X5R

CERM-X5R

9 60

IN

9 60

IN

UL001

VCC

2

GND

WLBT_CLKREQ_L

PLACE_NEAR=U0600.BE30:10MMGND_VOID=TRUE

PCIE_WLBT_D2R_N

PLACE_NEAR=U0600.BF30:10MM

SN74AUP1G17

SON

4

NC

NC

1

2

WLAN_TIME_SYNC

9 60 61

BI

9

OUT

9

OUTIN

CL071

0.1UF

10%

6.3V
CERM-X5R
0201

6

OUT

BOM_COST_GROUP=WIRELESS

PPL030
PPL031

TPL032

TPL033

SYNC_MASTER=ref_wireless_rasputin

PAGE TITLE

P4MM

SM

PP

P4MM

SM

PP

TP

TP-P55

TP

TP-P55

1

1

1

1

PCIE_CLK100M_WLBT_P

PCIE_CLK100M_WLBT_N

WLBT_RESET_L

PLACE_SIDE=BOTTOM

WLBT_CLKREQ_L

PLACE_SIDE=BOTTOM

WIFI/BT: MODULE

9 60

9 60

9 60 61

9 60 61

*** OK2INTEGRATE ***

RASPUTIN WIFI/BT MODULE GND

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

ANTENNA CONNECTORS

10
15
16
17
18
19
20
24
25
26
28
29
30
33
34
35
41
43
45
46
47
50
51
52
53
54
55
56
57
58
59
69
70
71
75
79
80
81
84

86
87
88
90
91
92
93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118

UL000

1
2
6
7
8
9

LBEE5XV1YR-506

LGA

SYM 2 OF 4

GND GND

119
120
121
122
128
129
130
131
132
135
138
141
144
146
147
148
154
158
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221

222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302

UL000

LBEE5XV1YR-506

SYM 3 OF 4

GND

LGA

GND

303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383

384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462

UL000

LBEE5XV1YR-506

SYM 4 OF 4

GND

LGA

GND

463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
505
506
508
509
510
511
512
513
514
515
516
519
520
521
522
523
526
527
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549

2G_C1
5G_C0
BT_C0

2G_C0
5G_C1
BT_C1

JL102

20449-001E-03

F-ST-SM

61

1

PACK_IGNORE=TRUE
PACK_OPTION=T664_IPEX

BT_C0_DED

JL122

20431-001E-01

F-ST-SM

SIGNAL

GND

WLBT DEBUG CONNECTOR

IR050D15010C

20449-001E-03

IR050D15010C

20449-001E-03

RF_BT_DED_ANT

12

RF_BT_DED_ANT

PACK_IGNORE=TRUE

PACK_OPTION=ANT_MAC_MINI

JL100

F-ST-SM

RF_ANT_0 RF_ANT_0

1

PACK_OPTION=SUNWAY

JL110

F-ST-SM

RF_ANT_0

1

PACK_IGNORE=TRUE
PACK_OPTION=IPEX

JL101

F-ST-SM

1

RF_ANT_1

PACK_OPTION=SUNWAY

JL111

F-ST-SM

1

PACK_IGNORE=TRUE
PACK_OPTION=IPEX

PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA

RL102

1/20W

1

CL101

0.3PF

+/-0.1PF
25V

2

C0G-CERM
201

NOSTUFF

PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA

61

JL103

505070-1222

M-ST-SM

14 13

0

1 2

BI

60 61

BI

5%

0201MF

1

CL102

0.3PF

+/-0.1PF
25V

2

C0G-CERM
201

NOSTUFF

PACK_IGNORE=TRUE

60 61

60 61

JL100

20449-001E-03

F-ST-SM

1

PACK_IGNORE=TRUE
PACK_OPTION=T664_IPEX

JL120

20431-001E-01

F-ST-SM

SIGNAL

GND

JL101

20449-001E-03

F-ST-SM

1

PACK_IGNORE=TRUE
PACK_OPTION=T664_IPEX

JL121

20431-001E-01

PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA

F-ST-SM

SIGNAL

GND

UL101

2.4G

1 3

0603

OUTIN

GND

2 4

12

PACK_IGNORE=TRUE

RF_ANT_1

12

PACK_IGNORE=TRUE

PACK_IGNORE=TRUEPACK_OPTION=3X_ANTENNA
PACK_OPTION=3X_ANTENNA

RF_ANT_0

PACK_OPTION=ANT_MAC_MINI

RF_ANT_1RF_ANT_1

PACK_OPTION=ANT_MAC_MINI

RF_BT_DED_FINRF_BT_DED_FOUT

60 61

60 61

60 61

60 6160 61

PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA

0

RL104

1/20W MF 0201

1

2

1 2

CL103

0.3PF

+/-0.1PF
25V
C0G-CERM
201

5%

NOSTUFF

PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA

NC_RF_BT_DED

1

CL105

0.3PF

+/-0.1PF
25V

2

C0G-CERM
201

NOSTUFF

BI

60 80

WLAN_TIME_SYNC_1V8

60

WLAN_CONTEXT_A

1060

WLAN_CONTEXT_B

1060

WLBT_WAKE

3460

WLBT_PWR_EN

3460

WLBT_RESET_L

960

2 1
4 3
6 5

8 7
10 9
12 11

16

TPT_WLAN_JTAG_TDI
TPT_WLAN_JTAG_TDO
BT_R1_TIME_SYNC

WLBT_CLKREQ_L
BT_TIME_SYNC_1V8
PMU_CLK32K_WLBT

15

BOMOPTION=WLBT_DBG

PACK_OPTION=WLBT_DBG_CONN

60

9 60

7 60

34 60

8060

8060

WIFI/BT: ANTENNA and GND

Apple Inc.

*** OK2INTEGRATE ***

NAND0 S5E0

78 62

78 63 62

PP0V88_AWAKE_NAND

1

CN010

1

CN011

20UF

10V

2

X5R
0402

2

RN010

2

1%
MF

0201

21

PP1V25_AWAKE_NAND

1/20W

PLACE_NEAR=UN000.L2:10MM

FLN000

10OHM-50%-1A-0.05OHM

0201

PLACE_NEAR=UN000.J6:10MM

The inductance from CN047, CN046, CN045, CN044 to
their S5E pins shall be less than 1100pH

20UF

20%20%
10V
X5R
0402

21

1

CN012

2.2UF

20%
10V

2

X5R
0201

1

CN047

2.2UF

20%
10V

2

X5R
0201

1

CN045

4.7UF

20%
4V

2

CER-X5R
0201

1

CN013

2.2UF

20%
10V

2

X5R
0201

65

65

1

CN046

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CN044

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CN014

2.2UF

20%
10V

2

X5R
0201

TPT_NAND0_S5E0_ANI1_VREF

TPT_NAND0_S5E0_ANI0_VREF

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

VOLTAGE=1.2V

PP1V2_NAND0_S5E0_AVDD1X_PLL

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

VOLTAGE=1.2V

PP1V2_NAND0_S5E0_PCI_AVDD_H

1

CN015

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CN016

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CN017

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CN032

20UF

20%
10V

2

X5R
0402

CN030

4.3UF

20%

4V
CERM
0402

1

4

2

3

1

CN020

20UF

20%
10V

2

X5R

1

CN034

2.2UF

20%

2

X5R
0201

1

CN022

2.2UF

20%
10V

2

X5R
0201

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

VOLTAGE=0.9V

1

2

PP0V9_NAND0_S5E0_VDD_PLL

NC_NAND0_S5E0_VPP

CN035

2.2UF

20%
10V10V
X5R
0201

1

CN023

2.2UF

20%
10V

2

X5R
0201

1

2

81

CN036

2.2UF

20%
10V
X5R
0201

1

CN024

2.2UF

20%
10V

2

X5R
0201

1

CN037

2.2UF

20%
10V

2

X5R

1

2

CN025

2.2UF

20%
10V
X5R
02010402

1

CN038

2.2UF

20%
10V

2

X5R
02010201

FLN001

10OHM-50%-1A-0.05OHM

21

0201

PLACE_NEAR=UN000.R4:10MM

1

CN039

2.2UF

20%
10V

2

X5R
0201

1

CN083

4.7UF

20%
4V

2

CER-X5R
0201

PP1V25_AWAKE_NAND

1

CN03A

2.2UF

20%
10V

2

X5R
0201

PP2V5_AWAKE_NAND

PP0V88_AWAKE_NAND

PLACE_NEAR=FLN001.2:5MM

786362

786463

7862

WP*

B3

NAND0_LPB_L

C4

NAND_BFH

B5

NAND0_BOOT2

C6

NAND0_S5E0_SWD_UID0

B7
C8

NAND0_S5E0_SWD_UID1

B9
B11

NAND0_PFN_L

D11

NAND0_BCM_L

E8

NAND0_PCIE_RESET_L

D7

SWD_NAND0_SWDIO

E6

SWD_NAND0_SWCLK

E4

NAND0_S5E0_JTAG_TDO

D5

TPT_NAND0_S5E0_JTAG_TDI

D9

NAND0_JTAG_SEL

T3

TPT_NAND0_S5E0_DROOP_L

G2

NAND0_WP_L

IN
IN

62 63

62

62

IN

IN

IN

IN

IN

OUT

IN

IN

65

IN

34 63

7 63

63 65

62 63

9 63

20

20

63

65

62 63

62 63

NAND0_CLK24M_0

IN

IN
IN

PCIE_CLK100M_NAND0_0_P
PCIE_CLK100M_NAND0_0_N

NAND0_CLKREQ0_R_L

OUT

1

CN085

10PF

5%
25V

2

C0G
0201

1

RN004

200

0.1%
1/20W
TK
0201-1

2

65

9

9

65

NAND0_S5E0_PCIE_RESREF

GND_VOID=TRUE

9

9

9

9

PCIE_NAND0_R2D_C_P<0>

IN

PCIE_NAND0_R2D_C_N<0>

IN

PCIE_NAND0_D2R_P<0>

OUT

PCIE_NAND0_D2R_N<0>

OUT

0.22UF

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

21CN003

21CN004

21CN001

21CN002

6.3V10%

6.3V

10%

10% 6.3V

10%

6.3V

X5R-CERM

X5R-CERM

X5R-CERM

X5R-CERM

763

6263

IN

IN

PCIE_NAND0_R2D_P<0>

0201

GND_VOID=TRUE

PCIE_NAND0_R2D_N<0>

0201

GND_VOID=TRUE

PCIE_NAND0_D2R_C_P<0>

0201

GND_VOID=TRUE

PCIE_NAND0_D2R_C_N<0>

0201

GND_VOID=TRUE

NAND0_RESET_L
NAND0_JTAG_TRST_L

NAND0_S5E0_ZQ_0
NAND0_S5E0_ZQ_1

PLACE_NEAR=UN000.C10:15MM

1

RN006

300

1%
1/20W
MF
201

2

PLACE_NEAR=UN000.K3:15MM

1

RN005

300

1%
1/20W
MF
201

2

M3

CLK_IN

K11

PCIE_REFCLK_P

J12

PCIE_REFCLK_N

P5

PCIE_CLKREQ*

H7

PCIE_RESREF

M11

PCIE_RX0_P

N12

PCIE_RX0_N

R12

PCIE_TX0_P

T11

PCIE_TX0_N

L4

RESET*

G10

TRST*

C10

ZQ_0

K3

ZQ_1

OMIT_TABLE

UN000

S5E-MCP-STUDY

LGA

EXT_D0/BOOT0
EXT_D1/BOOT1

EXT_D2/BOOT2/SPINAND_SCLK

EXT_D3/SWD_UID0/SPINAND_MISO

EXT_D4/SPI_CS

EXT_D5/SWD_UID1/SPINAND_MOSI

EXT_D6/BOOT3

EXT_D7/SPF

EXT_DQS/BCM*

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

DROOP*

NAND0_BOOT2

6263

NAND0_JTAG_SEL

6263

NAND0_JTAG_TRST_L

6263

1

RN000

47K

1%
1/20W
MF
201

2

1

RN002

47K

1%
1/20W
MF
201

2

1

2

Spec recommends to tie Boot2 directly to Gnd

RN021

0

5%
1/20W
MF
0201

1

RN001

0

5%
1/20W
MF

2

6263

6263

NAND0_BCM_L

NAND0_WP_L

Spec recommends to tie BCM, WP directly to 1.2V rail

PP1V25_AWAKE_NAND

1

RN007

0

5%
1/20W
MF
02010201

2

786362

62

62

NAND0_S5E0_SWD_UID0

NAND0_S5E0_SWD_UID1

1

RN009

47K

1%
1/20W
MF
201

2

1

RN008

47K

1%
1/20W
MF
201

2

STORAGE: SSD0 S5E <0>

BOM_COST_GROUP=SSD

*** OK2INTEGRATE ***

NAND0 S5E1

78 63

78 63 62

PP0V88_AWAKE_NAND

SSD_2L

1

CN110

20UF

20%
10V

2

X5R
0402

SSD_2L

1

CN111

2

SSD_2L

RN110

2

1%
MF

0201

21

PP1V25_AWAKE_NAND

1/20W

PLACE_NEAR=UN100.L2:10MM

SSD_2L

FLN100

10OHM-50%-1A-0.05OHM

0201

PLACE_NEAR=UN100.J6:10MM

The inductance from CN147, CN146, CN145, CN144 to
their S5E pins shall be less than 1100pH

20UF

20%
10V
X5R
0402

21

SSD_2L SSD_2L SSD_2L

1

CN112

2.2UF

20%
10V

2

X5R
0201

1

CN113

2.2UF

20%
10V

2

X5R
0201

65

65

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

VOLTAGE=1.2V

1

CN114

2.2UF

20%
10V

2

X5R
0201

PP1V2_NAND0_S5E1_AVDD1X_PLL

SSD_2LSSD_2L

1

CN147

2.2UF

20%
10V

2

X5R
0201

1

CN146

0.1UF

10%

6.3V

2

CERM-X5R
0201

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

VOLTAGE=1.2V

PP1V2_NAND0_S5E1_PCI_AVDD_H

SSD_2L

1

CN145

4.7UF

20%
4V

2

CER-X5R
0201

SSD_2L

1

CN144

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CN115

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CN116

0.1UF

10%

6.3V

2

CERM-X5R
0201

TPT_NAND0_S5E1_ANI1_VREF

TPT_NAND0_S5E1_ANI0_VREF

SSD_2LSSD_2LSSD_2L

1

CN117

0.1UF

10%

6.3V

2

CERM-X5R
0201

SSD_2L

1

CN132

20UF

20%
10V

2

X5R
0402

SSD_2L

CN130

4.3UF

20%

4V
CERM
0402

1

4

2

SSD_2L

1

CN134

2.2UF

20%

3

10V

2

X5R
0201

SSD_2L SSD_2L

1

CN120

20UF

20%
10V

2

X5R
0402

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

VOLTAGE=0.9V

1

CN122

2.2UF

20%
10V

2

X5R
0201

PP0V9_NAND0_S5E1_VDD_PLL

NC_NAND0_S5E1_VPP

SSD_2L SSD_2L SSD_2L SSD_2L SSD_2L

1

CN135

2.2UF

20%
10V

2

X5R
0201

1

2

SSD_2L

CN123

2.2UF

20%
10V
X5R X5R
0201

1

CN136

2.2UF

20%
10V

2

X5R
0201

1

2

1

CN137

2.2UF

20%
10V

2

X5R
0201 0201

SSD_2L

CN124

2.2UF

20%
10V 10V

0201

SSD_2L

1

CN125

2.2UF

20%

2

X5R
0201

1

CN138

2.2UF

20%
10V

2

X5R

1

CN139

2.2UF

20%
10V

2

X5R
0201

SSD_2L

FLN101

10OHM-50%-1A-0.05OHM

21

0201

81

PLACE_NEAR=UN100.R4:10MM

1

CN183

4.7UF

20%
4V

2

CER-X5R
0201

SSD_2L

PP1V25_AWAKE_NAND

SSD_2L

1

CN13A

2.2UF

20%
10V

2

X5R
0201

PP2V5_AWAKE_NAND

PP0V88_AWAKE_NAND

PLACE_NEAR=FLN101.2:5MM

786362

786462

7863

WP*

B3

NAND0_LPB_L

C4

NAND_BFH

B5

NAND0_BOOT2

C6

NAND0_S5E1_SWD_UID0

B7
C8

NAND0_S5E1_SWD_UID1

B9
B11

NAND0_PFN_LPCIE_NAND0_R2D_C_P<1>

D11

NAND0_BCM_L

E8

NAND0_PCIE_RESET_L

D7

SWD_NAND0_SWDIO

E6

SWD_NAND0_SWCLK

E4

TPT_NAND0_S5E1_JTAG_TDO

D5

NAND0_S5E0_JTAG_TDO

D9

NAND0_JTAG_SEL

T3

TPT_NAND0_S5E1_DROOP_L

G2

NAND0_WP_L

34 62

ININ

7 62

IN

62

63

63

62 659

IN

62

IN

9 62

IN

20

IN

20

IN

65

OUT

62

IN

62

IN

65

62

IN

SSD_2L

1

CN185

10PF

5%
25V

2

C0G
0201

IN

9

IN

9

9

PCIE_NAND0_R2D_C_N<1>

PCIE_NAND0_D2R_P<1>

OUT

PCIE_NAND0_D2R_N<1>

OUT

SSD_2L

1

RN104

200

0.1%
1/20W

0201-1

2

0.22UF

0.22UF

0.22UF

0.22UF

SSD_2L

GND_VOID=TRUE

21CN103

SSD_2L

GND_VOID=TRUE

21CN104

SSD_2L

GND_VOID=TRUE

21CN101

SSD_2L

GND_VOID=TRUE

21CN102

65

9

9

65

6.3V

10% 6.3V

6.3V X5R-CERM

10% 6.3V 0201

X5R-CERM

X5R-CERM

762

62

NAND0_CLK24M_1

IN
IN

PCIE_CLK100M_NAND0_1_P
PCIE_CLK100M_NAND0_1_N

NAND0_CLKREQ1_R_L

OUT

NAND0_S5E1_PCIE_RESREF

PCIE_NAND0_R2D_P<1>

0201X5R-CERM10%

PCIE_NAND0_R2D_N<1>

0201

PCIE_NAND0_D2R_C_P<1>

020110%

PCIE_NAND0_D2R_C_N<1>

IN

IN

NAND0_RESET_L
NAND0_JTAG_TRST_L

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

NAND0_S5E1_ZQ_0
NAND0_S5E1_ZQ_1

PLACE_NEAR=UN100.C10:15MM

1

RN106

300 300

1%
1/20W
MF
201

2

PLACE_NEAR=UN100.K3:15MM

1

RN105

1%
1/20W
MF
201

2

M3

CLK_IN

K11

PCIE_REFCLK_P

J12

PCIE_REFCLK_N

P5

PCIE_CLKREQ*

H7

PCIE_RESREF

M11

PCIE_RX0_P

N12

PCIE_RX0_N

R12

PCIE_TX0_P

T11

PCIE_TX0_N

L4

RESET*

G10

TRST*

C10

ZQ_0

K3

ZQ_1

OMIT_TABLE

UN100

S5E-MCP-STUDY

LGA

EXT_D0/BOOT0
EXT_D1/BOOT1

EXT_D2/BOOT2/SPINAND_SCLK

EXT_D3/SWD_UID0/SPINAND_MISO

EXT_D4/SPI_CS

EXT_D5/SWD_UID1/SPINAND_MOSI

EXT_D6/BOOT3

EXT_D7/SPF

EXT_DQS/BCM*

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

DROOP*

SSD_2L SSD_2L

PP1V25_AWAKE_NAND

1

RN108

47K

1%
1/20W
MF
201

63

63

NAND0_S5E1_SWD_UID0

NAND0_S5E1_SWD_UID1

SSD_2L

1

RN109

47K

1%
1/20W
MF
201

2

2

SSD_2L

786362

SYNC_MASTER=ref_storage_s5e

STORAGE: SSD0 S5E <1>

Apple Inc.

BOM_COST_GROUP=SSD

***OK2INTEGRATE***

THIS EXTERNAL NAND VCC DISCHARGE CIRCUITRY IS FOR SYSTEM THAT DOES NOT USE OCARINA

78 63 62

PP2V5_AWAKE_NAND

PP2V5_NAND0_DISCHARGE

83

VOLTAGE=2.5V

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

1

RN420

24.9

1%
1/10W
MF-LF
603

2

1

RN421

24.9

1%
1/10W
MF-LF
603

2

1

RN422

24.9

1%
1/10W
MF-LF
603

2

1

RN423

24.9

1%
1/10W
MF-LF
603

2

4

D

RN430

34

IN

P2V5_NAND0_DISCHARGE_EN P2V5_NAND0_DISCHARGE_EN_R

1

RN431

10K

5%
1/20W
MF
201

2

10K

1/20W

5%
MF

201

21

1

CN420

33000PF

10%

6.3V

2

X5R
201

G

1

S

32

376S00019

QN420

DMN2044UCB4

PAGE TITLE

STORAGE: NON OCARINA SUPPORT

SSD 24M CLOCK TERMINATIONS

TOPOLOGY TBD

RP000

33

5%
MF

201

21

IN

1/20W

RP001

33

5%
MF

201

21

7

IN

NAND0_CLK24M_1_R

1/20W

RP002

0

21

5%

1/20W

MF

0201

NAND0_CLK24M_0NAND0_CLK24M_0_R

NAND0_CLK24M_1

NAND0_PFN_LPMU_SYS_ALIVE

OUT

OUT

627

63

62

OUT

TPT_NAND0_S5E0_JTAG_TDI

TPT_NAND0_S5E0_JTAG_TDI

MAKE_BASE=TRUE

63

IN

TPT_NAND0_S5E1_JTAG_TDO

TPT_NAND0_S5E1_JTAG_TDO

MAKE_BASE=TRUE

62 63343582

OUTIN

62

OUT

TPT_NAND0_S5E0_ANI0_VREF

TPT_NAND0_S5E0_ANI0_VREF

MAKE_BASE=TRUE

62

IN

TPT_NAND0_S5E0_ANI1_VREF

TPT_NAND0_S5E0_ANI1_VREF

MAKE_BASE=TRUE

62

OUT

TPT_NAND0_S5E0_DROOP_L

TPT_NAND0_S5E0_DROOP_L

MAKE_BASE=TRUE

1

TP

TP-P4

1

TP

TP-P4

1

TP

TP-P4

1

TP

TP-P4

1

TP

TP-P4

TPP000

TPP001

TPP002

TPP003

TPP004

34

NC_MPMU_NAND0_RESET_L

IN

NC_MPMU_NAND0_RESET_L

MAKE_BASE=TRUE

63

OUT

TPT_NAND0_S5E1_ANI0_VREF

TPT_NAND0_S5E1_ANI0_VREF

MAKE_BASE=TRUE

63

IN

TPT_NAND0_S5E1_ANI1_VREF

TPT_NAND0_S5E1_ANI1_VREF

MAKE_BASE=TRUE

63

OUT

TPT_NAND0_S5E1_DROOP_L

TPT_NAND0_S5E1_DROOP_L

MAKE_BASE=TRUE

1

TP

TP-P4

1

TP

TP-P4

1

TP

TP-P4

TPP006

TPP007

TPP008

RP003

0

5%

1/20W

MF

0201

21

NAND0_CLKREQ0_R_LNAND0_CLKREQ0_L

629

INOUT

RP004

0

5%

1/20W

MF

0201

21

NAND0_CLKREQ1_R_LNAND0_CLKREQ1_L

639

INOUT

STORAGE: SSD Support

Apple Inc.

*** OK2INTEGRATE ***

PP3V3_S2

79

HOST SIDE

CKPLUS_WAIVE=CLK_DATA_CON

8

OUT

8

OUT

8

OUT

8

OUT

42

BI

MIPI_FTCAM_DATA_N<0>

CKPLUS_WAIVE=CLK_DATA_CON

MIPI_FTCAM_DATA_P<0>

CKPLUS_WAIVE=CLK_DATA_CON

MIPI_FTCAM_CLK_N

CKPLUS_WAIVE=CLK_DATA_CON

MIPI_FTCAM_CLK_P

I2C_CAM_1V8_SDA

PPP100

PP

SM-SP

42

BI

I2C_CAM_1V8_SCL

PPP101

PP

SM-SP

72

FTCAM_DISABLE_1V8_IC_L

IN

CAMERA SECURE DISABLE

BYPASS=UP102::5MM

1

CP102

0.1UF

10%

6.3V

2

CERM-X5R
0201

NX3DV642GU

CMN_IC

CLK+

1

CKPLUS_WAIVE=NDIFPR_BADTERM

CKPLUS_WAIVE=PDIFPR_BADTERM

CKPLUS_WAIVE=NDIFPR_BADTERM

CKPLUS_WAIVE=PDIFPR_BADTERM

1

1

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

11

CLK-

2

1D+

3

1D-

4

2D+

5

2D-

6

8

OE*

S

VCC

CRITICAL

UP102

QFN-COMBO

CLK1+

CLK2+
CLK1-

CLK2-

CONTROL

LOGIC

1D1+

1D2+
1D1-

1D2­2D1+

2D2+
2D1-

2D2-

NC
NC

17

CKPLUS_WAIVE=CLK_DATA_CON

22

GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM

16

23

GND_VOID=TRUE
CKPLUS_WAIVE=PDIFPR_BADTERM

15

20

GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM

14

21

GND_VOID=TRUE
CKPLUS_WAIVE=PDIFPR_BADTERM

13

19

12

18

7
24

MIPI_FTCAM_DATA_ISOL_N

CKPLUS_WAIVE=CLK_DATA_CON

MIPI_FTCAM_DATA_ISOL_P

CKPLUS_WAIVE=CLK_DATA_CON

MIPI_FTCAM_CLK_ISOL_N

CKPLUS_WAIVE=CLK_DATA_CON

MIPI_FTCAM_CLK_ISOL_P

I2C_FTCAM_DSBL_SDA

I2C_FTCAM_ISOL_SDA

I2C_FTCAM_DSBL_SCL

I2C_FTCAM_ISOL_SCL

NC
NC

67

IN

67

IN

67

IN

67

IN

PP1V8_S2

1

RP105

100K

5%
1/20W
MF
201

2

I2C PULL VALUES TO BE DETERMINED FROM CHARACTERIZATION

1

RP107

100K

5%
1/20W
MF
201

2

1

RP106

100K

5%
1/20W
MF
201

2

1

RP108

100K

5%
1/20W
MF
201

2

BI

BI

78

67

67

VALUE STATE

L CAMERA DISABLE
H CAMERA ENABLE

GND

SECDIS: MIPI MUX

Apple Inc.

LCD PANEL INTERFACE (eDP) + Camera (MIPI)

MIPI Clock and DataA

TABLE_5_H EAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK4117S0201

LP680,LP681,LP684,LP685

OMIT_TABLE

LP680

27NH-3%-0.140A-2.3OHM

66

MIPI_FTCAM_CLK_ISOL_N

OUT

2 1

0201

OMIT_TABLE

LP681

27NH-3%-0.140A-2.3OHM

66

MIPI_FTCAM_CLK_ISOL_P

OUT

MUX

NOSTUFF

1

CP682

7PF

+/-0.1PF
25V

2

CERM
0201

NOSTUFF

1

CP683

7PF

+/-0.1PF
25V

2

CERM
0201

2 1

0201

NOSTUFF

CP681

+/-0.1PF

OMIT_TABLE

LP684

27NH-3%-0.140A-2.3OHM

66

MIPI_FTCAM_DATA_ISOL_N

OUT

2 1

0201

OMIT_TABLE

LP685

27NH-3%-0.140A-2.3OHM

66

MIPI_FTCAM_DATA_ISOL_P

OUT

NOSTUFF

1

CP686

7PF

+/-0.1PF
25V

2

CERM
0201

NOSTUFF

1

CP687

7PF

+/-0.1PF
25V

2

CERM
0201

2 1

0201

NOSTUFF

CP685

+/-0.1PF

BOM OPTIONCRITICAL

TABLE_5_I TEM

MIPI_FTCAM_CLK_F_N

MIPI_FTCAM_CLK_F_P

NOSTUFF

7PF

25V
CERM
0201

1

2

CP680

+/-0.1PF

7PF

25V
CERM
0201

1

2

MIPI_FTCAM_DATA_F_N<0>

MIPI_FTCAM_DATA_F_P<0>

NOSTUFF

7PF

25V
CERM
0201

1

2

CP684

+/-0.1PF

7PF

25V
CERM
0201

1

2

CRITICAL

LP609

2.4GHZ

0.65X0.5X0.3MM-SM

4

3 2

SYM _VER -1

1

MIPI_FTCAM_CLK_CONN_N

MIPI_FTCAM_CLK_CONN_P

PLACE_NEAR=JP600.37:2.54MM

CRITICAL

LP607

0.65X0.5X0.3MM-SM

4

3 2

SYM _VER -1

1

MIPI_FTCAM_DATA_CONN_N<0>

MIPI_FTCAM_DATA_CONN_P<0>

PLACE_NEAR=JP600.33:2.54MM

67

67

CONNECTOR

67

67

eDP Display ConnectorG

PPVOUT_LCDBKLT

677983

867

BI

867

BI

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

LPDP_INT_AUX_C_N
LPDP_INT_AUX_C_P

LPDP_INT_DATA_C_N<0>
LPDP_INT_DATA_C_P<0>

LPDP_INT_DATA_C_N<1>
LPDP_INT_DATA_C_P<1>

LPDP_INT_DATA_C_N<2>
LPDP_INT_DATA_C_P<2>

LPDP_INT_DATA_C_N<3>
LPDP_INT_DATA_C_P<3>2.4GHZ

MIPI_FTCAM_DATA_CONN_N<0>

67

MIPI_FTCAM_DATA_CONN_P<0>

67

MIPI_FTCAM_CLK_CONN_N

67

MIPI_FTCAM_CLK_CONN_P

67

PP5V_SW_LCD PP5V_MAIN_ALSCAM_F

79 67

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

CRITICAL

JP600

20759-042E-02

F-ST-SM

PWR

SIGNAL

PWR

4443

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241

4645

516S00266

PP3V3_SW_LCD

UART_TCON_D2R
EDP_PANEL_1V8_EN
DP_INT_HPD_3V3_CONN

SPI_TCON_CS_L
SPI_TCON_MISO
SPI_TCON_MOSI
SPI_TCON_CLK

I2C_MLB2JERRY_3V3_SDA
I2C_MLB2JERRY_3V3_SCL
I2C_BKLT_SDA
I2C_BKLT_SCL

I2C_ALS_1V8_SDA
I2C_ALS_1V8_SCL
I2C_FTCAM_ISOL_SCL
I2C_FTCAM_ISOL_SDA

NC
NC

67 79

OUT

IN

67

IN

OUT

IN
IN

BI

BI

BI

BI

BI

IN

BI

IN

80

68

7

7

20

20

41

41

69

69

42

42

66

66

B

79

ALS & Camera 5V Filter

LP670

FERR-120-OHM-1.5A

PP5V_S2

77.2 mA nominal max

96.2 mA peak

0402A

CRITICAL

21

1

CP677

0.1UF

10%
16V

2

X7R-CERM
0402

PP5V_MAIN_ALSCAM_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000

VOLTAGE=5V

GND

C

67

LCD Panel AUX Straps

PP3V3_SW_LCD

RP603

RP602

2 1

2 1

1/20W5% MF 201

1M

1M

67 79

LPDP_INT_AUX_C_N

201MF1/20W5%

NO_XNET_CONNECTION=1

LPDP_INT_AUX_C_P

NO_XNET_CONNECTION=1

8 67

8 67

4847
5049
5251
5453
5655
5857
6059
6261
6463
6665
6867

1

CP664

12PF

5%
25V

2

CERM
0201

TCON HPD Voltage DividerD

RP600

0

5%
MF

0201

21

DP_INT_HPD_3V3_CONN

67

1.2V

8

LPDP_INT_HPD

OUT

1.2V

RP601

47K

5%

1/20W

MF

201

1

2

1/20W

Cowling BossesE

SHP601

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

SHP602

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

860-00974

860-00974

Backlight Desense CapacitorsF

PPVOUT_LCDBKLT

677983

PLACE_NEAR=JP600:5MM

PLACE_NEAR=JP600:5MM

PLACE_NEAR=JP600:5MM

CP604

3PF

+/-0.1PF

100V

C0G

0201

1

CP603

12PF

2

5%

100V

C0G

0201

1

2

CP602

+/-0.1PF

3PF

100V

C0G

0201

1

CP601

12PF

2

5%

100V

C0G

0201

1

CP600

1000PF

2

10%

100V

X7R

0402

1

2

eDP Display Connector

Apple Inc.

BOM_COST_GROUP=DISPLAY

*** OK2INTEGRATE ***

PP5V_S2

79

CP709

2200PF

10%
10V

X7R-CERM

0201

CRITICAL

VDD

UP700

SLG5AP1443V

LCD_PWR_SLEW

1

2

CAP

ON S

TDFN

GND

37

D

52

1

CP717

0.1UF

10%
10V

2

X5R-CERM
0201

1

CP711

0.1UF

10%
10V

2

X5R-CERM
0201

1

CP712

10UF

20%
10V

2

X5R-CERM
0402-7

PP5V_SW_LCD

79

CONSULT YOUR DISPLAY DRI FOR DETAILS
GENERAL GUIDELINE IS

3V3 FOR 2020 SYSTEMS
3V8 FOR 2021 SYSTEMS

PP3V3_S2

79

PP1V8_S2

78

BYPASS=UP710::3MM

1

CP770

0.1UF

10%
10V

2

X5R-CERM
0201

CRITICAL

VDD

UP701

SLG5AP1564V

STDFN

2 3

ON

GND

PG

1

2

D

5

S

7

NC

CP710

1.0UF

20% 6.3V
X5R

0201-1

1

CP718

0.1UF

10%
10V

2

X5R-CERM

1

CP719

10UF

20%
10V

2

X5R-CERM
0402-70201

PP3V3_SW_LCD

79

UP710

SLG4AP43605V

STQFN

IN OUT

35

IN

LCD_PWR_EN

PMU_SYS_ALIVE

NC
NC
NC
NC
NC

PANEL_EN_IN

3

SYS_ALIVE

5

NC

6

NC

7

NC

8

NC

12

NC

PANEL_EN_OUT

PANEL_PWR_EN

BLC_VDDIO_EN

BLC_5V_EN

PANEL_DISCHARGE

112

4

13

14

10

NC

EDP_PANEL_1V8_EN
EDP_PANEL_PWR_EN

EDP_BLC_5V_EN

EDP_PANEL_DISCHARGE

1

RP700

300

5%

2

1/16W
MF-LF
402

6735

PPPANEL_PANEL_DISCHARGE

3

D

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

QP700

G

1

RP701

100K

5%
1/20W
MF
201

2

1

S

2

DMN2300UFB4

X2-DFN1006-3-COMBO

SYM_VER_1

DISPLAY POWER SEQUENCER

BOM_COST_GROUP=DISPLAY

*** OK2INTEGRATE ***

BEN IC: DISPLAY/KBD BACKLIGHT BOOST CONVERTER

371S00077 (COMBO) FOOTPRINT IN LAYOUT

PPBUS_AON

79

PP5V_S2

79

45

OUT

45

OUT

34

IN

ISNS_LCDBKLT_N
ISNS_LCDBKLT_P

BL_PWR_EN

UP800.17 VIH_MIN 1.2V
VIL_MAX 0.4V

740S0159

CRITICAL

FP800

3AMP-32V

0603-COMBO

VOLTAGE=13V

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

21

PPVIN_LCDBKLT_F

RP842

0

21

5%

1/20W

MF

0201

107S00034

RP800

0.025

1%
1W
MF

0612-1

2 1
4 3

1

RP801

80.6K

1%
1/16W
MF-LF
402

2

1

RP802

63.4K

1%
1/16W
MF-LF
402

2

OMIT_TABLE

RP844

OMIT_TABLE

PLACE_NEAR=UP800.5:5MM

CP840

VOLTAGE=13V

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

PPVIN_LCDBKLT_R

1

CP800

1000PF

10%
16V

2

X7R-1
0201

LCDBKLT_EN_L

1

0

5%
1/16W
MF-LF

402

2

VOLTAGE=5V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP5V_BKLT_D

1

1UF

10%
10V

2

X5R

402-1

ALLOW_APPLE_PREFIX=Q

376S0604

CRITICAL

QP800

FDC638APZ_SBMS001

SSOT6-HF

4

3

OMIT_TABLE

PLACE_NEAR=UP800.18:5MM

1UF

10%
10V
X5R

1

2

CP841

402-1

UP TO 22V ALLOWED ON UP800.11
WITH VDDD,VDDA AT 0V

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500

BKLT_SD

BKLT_SENSE_OUT
BKLT_EN_R

BKLT_SCL
BKLT_SDA

6
5
2
1

NOSTUFF

1

CP801

0.001UF

10%
50V

2

CERM
402

CKPLUS_WAIVE=LIFECYCLE_STATUS

OMIT_TABLE

1

RP845

0

5%
1/16W
MF-LF
402

2

VOLTAGE=5V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP5V_BKLT_A

UP800

CRITICAL

LLP

LP8548B1SQ_-04

11

SD

OMIT_TABLE

9

VSENSE_N

10

VSENSE_P

19

SENSE_OUT

17
12

15
16

EN
PWM_KEYB

SCL

(5K IPU VDDD)

SDA

(5K IPU VDDD)

ISET_KEYB

KEYB1
KEYB2

SW2
FB2

VOLTAGE=13V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PPVIN_LCDBKLT_Q

83

PLACE_NEAR=LP800.1:5MM

1

CP810

4.7UF

10%
25V

2

X6S-CERM
0603

376S0678

CRITICAL

PWRPK-1212-8

SYMBOL: 353S4160

VOLTAGE=55

DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=2.0000
SW
SW
FB
GD

2
1
21
4

20

13
14

6
8

LCDBKLT_SW

LCDBKLT_FB
LCDBKLT_FET_DRV

BKLT_ISET_KEYB
BKLT_KEYB1

BKLT_KEYB2
KBDBKLT_SW2

VOUT_KEYBDLED_FB2

QP801

SI7812DN

PLACE_NEAR=LP800.1:5MM

1

CP811

4.7UF

10%
25V

2

X6S-CERM
0603

5

3 2 1

152S00253

PLACE_NEAR=QP801.5:3MM

CRITICAL

LP800

15UH-20%-1.9A-0.24OHM

PIME062D-SM

PLACE_NEAR=LP800.1:5MM

1

CP812

0.1UF

10%
25V

2

X5R
402

VOLTAGE=5

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

4

LCDBKLT_FET_DRV_R

PLACE_NEAR=UP800.1:3MM

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

70

BI

70

IN

70

IN

70

BI

70

IN

VOLTAGE=55V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
DIDT=TRUE

21

83

PPVOUT_LCDBKLT_SW

1

2

VOLTAGE=5

DIDT=TRUE

IF KEYBOARD BACKLIGHT NOT USED,
ALIAS TO NC

RP833

10

1%
1/16W
MF-LF
402

OMIT_TABLE

PLACE_NEAR=LP800:5MM

CP876

12PF

5%

100V

C0G

0201

LCDBKLT_FB_XWR

OMIT_TABLE

NO_XNET_CONNECTION=1

1

RP831

1%
1/16W
MF-LF
402

2

1

RP832

150K

1%
1/16W
MF-LF
402

2

CRITICAL

DFLS2100

PLACE_NEAR=LP800.2:4.7MM

DP800

POWERDI123-COMBO

1

2

NO_XNET_CONNECTION=1
PLACE_NEAR=DP800:2MM

1

2

KA

XWP801

SM

NOSTUFF

CP830

100PF

5%
100V
C0G-CERM
0603

PPVOUT_LCDBKLT

PLACE_NEAR=DP800.K:5MMPLACE_NEAR=DP800.K:5MMPLACE_NEAR=DP800.K:6MMPLACE_NEAR=DP800.K:5MM

1

CP860

2.2UF

10%
100V

2

X5R

2

1

1206

PLACE_NEAR=DP800.K:5MM

1

CP864

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=DP800.K:10MM PLACE_NEAR=DP800.K:8MM PLACE_NEAR=DP800.K:5.5MM

1

CP868

2.2UF

100V

2

X5R
1206

1

CP872

2.2UF

10%
100V

2

X5R
1206

1

CP861

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=DP800.K:5MM

1

CP865

2.2UF

10%
100V

2

X5R
1206

1

CP869

2.2UF

10%10%
100V

2

X5R
1206

PLACE_NEAR=DP800.K:8MMPLACE_NEAR=DP800.K:6MM

1

CP873

2.2UF

10%
100V

2

X5R
1206

1

CP862

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=DP800.K:5MM

1

CP866

2.2UF

10%
100V

2

X5R
1206

1

CP870

2.2UF

10%
100V

2

X5R
1206

1

CP863

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=DP800.K:5.5MM

1

CP867

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=DP800.K:10MM

1

CP871

2.2UF

10%
100V

2

X5R
1206

79

TO JERRY ONLY

67

IN

67

BI

I2C_BKLT_SCL

I2C_BKLT_SDA

UP800.15 VIH_MIN 1.7V
VIL_MAX 0.4V

UP800.16 VIH_MIN 1.7V

VIL_MAX 0.4V
R_ON(TYP) 11.65 OHMS
R_ON(MAX) 12.85 OHMS

1

RP852

1.8K

5%
1/20W
MF
201

2

1

RP853

1.8K

5%
1/20W
MF
201

2

PLACE_NEAR=UP800.15:10MM

RP850

0

21

1/20W 0201MF5%

RP851

0

21

5%

1/20W

MF

PLACE_NEAR=UP800.16:10MM

0201

NOSTUFF

CP842

33PF

5%

25V

NPO-C0G

0201

1

2

RP840

CKPLUS_WAIVE=LIFECYCLE_STATUS

1M

5%

1/20W

MF

201

1

2

OMIT_TABLE

RP847

10K

5%

1/20W

MF

201

1

2

XWP800

SM

THRM

PAD

21

BKLT_PWM_KEYB_3V3
GND_BKLT_SGND

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000

VOLTAGE=0

UP800.12 VIH_MIN 1.7V
VIL_MAX 0.4V

IN

IF KEYBOARD BACKLIGHT USED,
CONNECT TO CSA 239

70

70

BEN IC VERSION TO MATCH VERSION OF JERRY IC IS ON THE PANEL

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,LP8548B1-04,DC/DC CVTR,BOOST,QFN-24353S4160

1 UP800 BLC_BEN_IC:V4

353S02256

BACKLIGHT SWITCH NODE DESENSE OPTION

10K IF KEYBOARD PWM INPUT IS NOT PRESENT (J132, J213)
100K IF KEYBOARD PWM INPUT IS PRESENT (J152)

IC,LP8548B1A-07,DC/DC BOOST CVTR,QFN24 SYNC_MASTER=ref_blc_ben

1 UP800

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,C0G,12PF,5%,100V,0201131S00141

1

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 RP847 BLC_KBD_BOOST_USED:NO117S0007

RES,MF,1/20W,10K OHM,5,0201,SMD

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_I TEM TABLE_5_I TEM

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

BLC_SW_NODE_DESENSECP876

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_I TEM

RP847RES,MF,100KOHM,1,1/20W,0201 BLC_KBD_BOOST_USED:YES1118S0014

BACKLIGHT BOOST VOLTAGE LEVEL BASED ON NUMBER OF LEDS PER STRING

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 RP831114S0339 RES,MTL FILM,1/16W,18.2K,1,0402,SM,LF

1 RP831 BLC_LEDS_PER_STRING:18114S0359 RES,MTL FILM,1/16W,28.7K,1,0402,SM,LF

BOM OPTION FOR BLC 5V RC FILTER, BASED ON PER PROJECT 5V RIPPLE CHARACTERIZATION.
AS COMPARED TO BLC TEAM'S 50 MV RIPPLE SPEC FOR VDDD & VDDA, SEE <RDAR://50682542>

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

RES,MTL FILM,1/16W,10 OHM,1,0402,SMD,LF2 RP844,RP845114S0023 BLC_5V_SERIES:10_OHM

CAP,CER,X5R,1UF,10%,10V,0402 BLC_5V_CAP:1_UFCP840,CP8412138S0614

CP840,CP8412138S00070 BLC_5V_CAP:4P7_UFCAP,CER,X5R,4.7UF,20%,25V,0402

TABLE_5_H EAD

BOM OPTIONCRITICAL

BLC_LEDS_PER_STRING:16BLC_BEN_IC:V7

TABLE_5_I TEM

BEN: CONTROLLER

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

BLC_5V_SERIES:0_OHMRP844,RP845RES,MTL FILM,0 OHM,1A MAX,0402,SMD116S0004 2

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

BOM_COST_GROUP=DISPLAY

*** OK2INTEGRATE ***

79

PP5V_S2_KBDLED

1

CP940

2

1

CP941

2.2UF2.2UF

2

X5R-CERMX5R-CERM

1

CP942

0.1UF

10%10%10%
16V25V25V

2

X5R-CERM
0201603603

BEN IC: KEYBOARD LED DRIVER

THIS PAGE IS ONLY TO BE INCLUDED IF THE KEYBOARD BACKLIGHT

IS CONTROLLED BY THE BEN ON PAGE 238

LP900

10UH-20%-1.4A-0.17OHM

21

PST041H-SM

OMIT_TABLE

PLACE_NEAR=LP900:5MM

1

CP976

12PF

5%
100V

2

C0G
0201

PLACE_NEAR=LP900.2:10MM

DP900

PMEG6010ER/S500

SOD123W

KA

1

CP950

2.2UF

10%
50V

2

X5R
0603

PLACE_NEAR=DP900:5MM

1

CP951

2.2UF

50V

2

X5R
0603

PLACE_NEAR=DP900:5MMPLACE_NEAR=DP900:5MM

1

CP952

2.2UF

10%10%
50V

2

X5R
0603

PPVOUT_KBDBKLT

PLACE_NEAR=DP900:5MM

1

CP953

2.2UF

10%
50V

2

X5R
0603

79

KEYBOARD BACKLIGHT
POWER & CONTROL
SIGNALS FROM
SYSTEM

69

BI

69

BI

KBDBKLT_SW2

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.0970

SWITCH_NODE=TRUE

VOUT_KEYBDLED_FB2

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000

VOLTAGE=40V

XWP900

SM

2 1

PLACE_NEAR=CP950.1:10MM

1

CP954

2.2UF

10%
50V

2

X5R
0603

PLACE_NEAR=DP900:5MM

1

CP958

0.001UF

10%
50V

2

X7R-CERM
0402

1

CP955

2.2UF

10%
50V

2

X5R
0603

1

CP956

2

PLACE_NEAR=DP900:5MMPLACE_NEAR=DP900:5MMPLACE_NEAR=DP900:5MMPLACE_NEAR=DP900:5MM

CP957

2.2UF2.2UF

10%10%
50V50V

2

X5RX5R
06030603

KEYBOARD BACKLIGHT
CONNECTOR SIGNALS

KEYBOARD BKLT PWM LEVEL-SHIFTER

UP900.4: VOH_MIN = 2.3V
VOL_MAX = 0.1V @ PWM_KEYB I_MAX OF 1UA

79

78

6

IN OUT

PP3V3_S2
PP1V25_S2

KBD_BKLT_PWM

UP900.3:
VIH MIN = VCCA X 0.65 = 0.78V

RP901

0

5%

1/20W

MF

0201

PLACE_NEAR=UP900.1:5MMPLACE_NEAR=UP900.6:5MM

CP900

21

SOC_KBD_BKLT_PWM_RES

1

RP900

47K

5%
1/20W
MF
201

2

1

10% 10%
16V 16V

2

0201

CP901

0.1UF0.1UF

X5R-CERMX5R-CERM

0201

1

2

VCCA VCCB

5

DIR

A

GND

311S00243

UP900

SN74AXC1T45

SOT-5X3

43

B

BKLT_PWM_KEYB_3V3

1RP903

31.6K

1%
1/20W
MF
201

2

BKLT_ISET_KEYB

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0800

GND_BKLT_SGND

RP910

10

1%

21

MF-LF

402

69

BKLT_KEYB1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1/16W

KBDLED_CATHODE1

77

INOUT

RP911

10

1%

21

MF-LF

402

69

OUT

BI

BKLT_KEYB2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

69

69

69

1/16W

KBDLED_CATHODE2

IN

77

KEYBOARD SWITCH NODE DESENSE OPTION

OFF=PAGE SIGNALS ON THIS VERTICAL LINE CONNECT TO BEN UP800
ON PAGE 238

SYNC_MASTER=ref_blc_ben SYNC_DATE=11/20/2019

PAGE TITLE

BEN: KEYBOARD

DRAWING NUMBER

051-05392

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

TABLE_5_H EAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_I TEM

BLC_KBD_SW_NODE_DESENSECAP,C0G,12PF,5%,100V,0201131S00141 1 CP976

BOM_COST_GROUP=DISPLAY

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

evt-1

PAGE

239 OF 801

SHEET

70 OF 92

SIZE

D

*** OK2INTEGRATE ***

JR200

AMR-MLB-X502

OMIT_TABLE

PACK_IGNORE=TRUE
PACK_OPTION=AMR_INTERPOSER_LEFT

SM

8
7
6

1
2
3
45

JR201

AMR-MLB-X502

SM

8
7
6

1
2
3
45

PP1V8_AON

Clamshell Open = High
Clamshell Closed = Low

PP1V8_AON

Lid Detect Sensors

797571

79 75 71

RR200

PACK_OPTION=NO_AMR_INTERPOSER_LEFT

PACK_OPTION=NO_AMR_INTERPOSER_RIGHT

797571

PP1V8_AON

1

1M

5%

1/20W

MF

201

2

1

RR201

1M

5%
1/20W
MF
201

2

BYPASS=UR200::5MM

CR200

0.1UF

10%

6.3V

CERM-X5R

0201

AMR_LEFT_OR_ND_1V8

1

UR2002

6

2

1

NC

5 3

NC

74LVC1G32

SOT891

4

IPD_LID_OPEN_R_1V8

RR203

1K

5%

1/20W

MF

201

21

IPD_LID_OPEN_1V8

OUT

OUT

72 75

34 77

OMIT_TABLE

PACK_IGNORE=TRUE
PACK_OPTION=AMR_INTERPOSER_RIGHT

MGL_1V8

5%

1/20W

MF

201

1

2

RR202

100K

OUT

AMR_RIGHT_OR_ND_1V8

72

OUT

50 72

BOM_COST_GROUP=SYSTEM

SYNC_MASTER=ref_secdis_amr

PAGE TITLE

SECDIS: AMR

3

*** OK2INTEGRATE ***

CURRENT PER RAIL

UNLESS 1V8 IS NOTED, SIGNALS ARE 1.2V

78 72

PP1V8_S2

78 72

ROOM=SECURE_DISABLE

BYPASS=UR301.1::5MM

PP1V8_S2

1

CR306

0.1UF

10%

6.3V

2

CERM-X5R
0201

UR301

SLG4AP44010

RAIL TYPICAL PEAK

1.2 S2 0.8MA 33MA

1.8 S2 0.8MA 14MA

SUPER IMPORTANT PACK OPTIONS:

78 72

PP1V2_S2

ROOM=SECURE_DISABLE

NC
NC
NC
NC
NC

2
3
4

NC

6
8

CLK_2MHZ

7

CLK_2MHZ_SECDIS_1V8_R

ROOM=SECURE_DISABLE

RR314

10

5%

PLACE_NEAR=UR301.7:15MM

21

201

MF1/20W

NOTES ARE ON CSA 2 OF THE REFERENCE DESIGN
READ, LEARN, IMPLEMENT

7

IN

80

IN

7

IN

80

OUT

61034

IN

82

880

IN

10

OUT

10

OUT

80

IN

FTCAM_DISABLE_L
NC_IRCAM_ENABLE_IN_IC

DMIC_DISABLE_L
NC_DMIC_DATA2_SEC_OUT_IC
PMU_RESET_L
FTCAM_RESET_L

PDM_DMIC_DATA4
PDM_DMIC_DATA3

NC_SEP_IRCAM_DISABLE_IC_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

PACK_OPTION=PROD_SECDIS

PACK_OPTION=PROD_SECDIS

PACK_OPTION=PROD_SECDIS_NOTMIPI

PACK_OPTION=PROD_SECDIS
PACK_OPTION=PROD_SECDIS

RR313

1K

10

OUT

7

IN

LID_OPEN

MAKE_BASE=TRUE

DISABLE_STROBE

MAKE_BASE=TRUE

LID_OPEN

PACK_OPTION=PROD_SECDIS

1/20W

PACK_OPTION=PROD_SECDIS

21

5%

201MF

FTCAM_DISABLE_L

DMIC_DISABLE_L

NC_FTCAM_ENABLE_IN
PDM_DMIC_DATA4

PDM_DMIC_DATA3
SMC_LID_OPEN_R

72

SECDIS_SN_TIE_OFF

DISABLE_STROBE
PDM_DMIC_CLK4

NC

CKPLUS_WAIVE=CLK_DATA_CON

CKPLUS_WAIVE=CLK_DATA_CON

NC

NC

CKPLUS_WAIVE=SYNONYM_CHECK

DMIC_CLK1_1V8_OUT_R FTCAM_DISABLE_1V8_IC_L
DMIC_CLK0_1V8_OUT_R

CKPLUS_WAIVE=TERMSHORTED

PACK_IGNORE=TRUE
PACK_OPTION=DEV_SECDIS

PDM_DMIC_CLK3

CKPLUS_WAIVE=SYNONYM_CHECK

E7

PB3A

F7

PB3B

G7

PB5A/CSSPIN

F6

PB8A/MCLK/CCLK

F5

PB8B/SO/SPISO

E4

PB11A/PCLKT2_0

E3

PB11B/PCLKC2_0

G4

PB16A/PCLKT2_1

G3

PB16B/PCLKC2_1

F4

PB12A

F3

PB12B

G2

PB25A/SN

G1

PB25B/SI_SISPI

A7

PL2A/L_GPLLT_IN

B6

PL2B/L_GPLLC_IN

C7

PL3A/PCLKT5_0

C6

PL3B/PCLKC5_0

E6

PL5A

E5

PL5B

(IPD)*
(IPD)

(IPD)*

LCMXO2-2000ZE-1UWAP9

(IPD)

ROOM=SECURE_DISABLE

1

RR300

0

10

IN

PDM_DMIC_CLK4

MAKE_BASE=TRUE

PACK_OPTION=PROD_SECDIS

PDM_DMIC_CLK4

1 2

5%

1/20W MF

0201

RR310

47K

1%
1/20W
MF
201

2

1

RR311

47K

1%
1/20W
MF
201

2

1

RR312

47K

1%
1/20W
MF PACK_OPTION=PROD_SECDIS_3DMIC
201

2

UR300

WLCSP

OMIT_TABLE

(IPD)*

(IPD)

(IPD)

PT18C/SCL/PCLKT0_0
PT18D/SDA/PCLKC0_0

(IPD)*

(IPD)*

GND

PINS MARKED (IPD)* ONLY HAVE
INTERNAL PULLDOWNS IN THE
SECDIS_EVT VERSION OF THE PART

PT10A

PT10B
PT12C/TDO
PT12D/TDI

PT16C/TCK
PT16D/TMS

PT17A/PCLKT0_1
PT17B/PCLKC0_1

PT20A
PT20B

PT20C/JTAGENB

PT20D/PROGRAMN

PT23A
PT23B

PT24A

(IPD)

PT24C/INITN

PT24B

PT24D/DONE

D5
D4
A6
C5

B4
B5
C4
D3

B3
C3
A3
B2

F2
F1
E2
C2

C1
D2
B1
A1

NC

CLK_2MHZ_SECDIS_1V8
NC_DMIC_CLK2_1V8_OUT_R_IC80
DMIC_CLK_ENABLE

NC

NC

MGL_1V8
SECDIS_TDO_IC
PP1V8_S2

GND
PP1V8_S2

72

72

72

72

JTAG SIGNALS ARE 1.8V
INPUTS ARE HARD-TIED TO RAILS IN POR DESIGNS
THE OUTPUT (TDO) IS NC'D IN POR DESIGNS

AMR_RIGHT_OR_ND_1V8

NC_DMIC_CLK2_IN_IC

72

NC_IRCAM_ENABLE_SEC_1V8_OUT_IC

NC_FTCAM_ENABLE_SEC_1V8_OUT_IC

DMIC_DATA0_1V8_IN

DMIC_DATA1_1V8_IN

NC_DMIC_DATA2_1V8_IN_IC

AMR_LEFT_OR_ND_1V8

IN

IN
IN

OUT

OUT

IN
IN

OUT

IN
IN

71

50 71

80

80

80

75

75

66

80

71 75

ROOM=SECURE_DISABLE

RR309

10

PLACE_NEAR=UR300.C3:15MM

21

2015%

MF1/20W

PACK_IGNORE=TRUE
PACK_OPTION=PROD_SECDIS_3DMIC

DMIC_CLK2_1V8_OUT_IC

OUT

PACK_IGNORE=TRUE

PACK_OPTION=PROD_SECDIS

PACK_OPTION=PROTO_PULLDOWN_SECDIS

PACK_OPTION=PROTO_PULLDOWN_SECDIS

ROOM=SECURE_DISABLE

RR301

75

OUT

DMIC_CLK1_1V8_OUT

OMIT_TABLE

10

5%

ROOM=SECURE_DISABLE

RR302

75

OUT

DMIC_CLK0_1V8_OUT

OMIT_TABLE

CKPLUS_WAIVE=TERMSHORTED

10

5%

PACK_IGNORE=TRUE
PACK_OPTION=DEV_SECDIS

ROOM=SECURE_DISABLE

PLACE_NEAR=UR300.C6:15MM

21

201

MF1/20W

PLACE_NEAR=UR300.E6:15MM

21

201

MF1/20W

PART# DESCRIPTIONQTY

336S00038 1 IC,PLD,MACHX02,2112 LUT,1.2V,ANN,WLCSP49 SECDIS_PROTOUR300

PART# DESCRIPTIONQTY

RR303

0

5%

21

0201

10

IN

PDM_DMIC_CLK3

MAKE_BASE=TRUE

PACK_OPTION=PROD_SECDIS

PDM_DMIC_CLK3

1/20W MF

PACK_OPTION=PROTO_PULLDOWN_SECDIS

BOM OPTIONREFERENCE DESIGNATOR(S)

1 UR300336S00039 IC,PLD,MACHX02,2112 LUT,1.2V,AP5,WLCSP49 SECDIS_EVT

SECDIS_EXT_CLK336S00041 IC,PLD,MACHX02,2112 LUT,1.2V,XXX,WLCSP491 UR300

BOM OPTIONREFERENCE DESIGNATOR(S)

DMIC_CLK_10OHMRES,MF,1/20W,10 OHM,5,0201,SMD117S0004 2 RR301,RR302

DMIC_CLK_33OHMRES,MF,1/20W,33 OHM,5,0201,SMD117S0080 2 RR301,RR302

TABLE_5_H EAD

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_H EAD

TABLE_5_I TEM

TABLE_5_I TEM

78 72

PP1V2_S2

ROOM=SECURE_DISABLE

BYPASS=UR300.D7::5MM

ROOM=SECURE_DISABLE

BYPASS=UR300.G6::5MM

1

CR300

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CR301

0.1UF

10%

6.3V

2

CERM-X5R
0201

ROOM=SECURE_DISABLE

BYPASS=UR300.D1::5MM

1

CR302

0.1UF

10%

6.3V

2

CERM-X5R
0201

PACK_OPTION=PROD_SECDIS

JTAG FOR DEV & PROTO0 BOARDS ONLY

78 72

SECDIS_TDO_IC

72

PP1V8_S2

72

GND

72

PP1V8_S2

72

PP1V8_S2

APN: 516S00115

ROOM=SECURE_DISABLE

JR300

505070-1222

M-ST-SM

1413

21
43
65
87
109
1211

15

16

PACK_IGNORE=TRUE
PACK_OPTION=JTAG_SECDIS:YES

PP1V8_S2
GND
PP1V8_S2
SECDIS_TDO_IC

I HAVE ROTATIONAL SYMMETRY

78 72

PP1V2_S2

SERIAL PROGRAMMING DISABLE

72

ROOM=SECURE_DISABLE

78 72

72

72

72

72

PP1V8_S2

CKPLUS_WAIVE=TERMSHORTED

PACK_IGNORE=TRUE
PACK_OPTION=JTAG_SECDIS:YES

PP1V8_S2

72

PP1V8_S2

72

GND

72

JTAG PORT TIE-OFFS

PACK_IGNORE=TRUE
PACK_OPTION=JTAG_SECDIS:YES

CKPLUS_WAIVE=TERMSHORTED

1

RR304

4.7K

5%
1/20W
MF
201

2

1

RR306

4.7K

5%
1/20W
MF
201

2

PACK_IGNORE=TRUE
PACK_OPTION=JTAG_SECDIS:YES

PACK_OPTION=JTAG_SECDIS:NO

GND

MAKE_BASE=TRUE

ROOM=SECURE_DISABLE

PACK_OPTION=JTAG_SECDIS:NOPACK_OPTION=JTAG_SECDIS:NO

1

RR305

4.7K

5%
1/20W
MF
201

2

CKPLUS_WAIVE=TERMSHORTED

78 72

72

ROOM=SECURE_DISABLE

SECDIS_SN_TIE_OFF

PP1V8_S2

MUST BE SAME RAIL AS DMICS

DMIC_CLK_ENABLE

ROOM=SECURE_DISABLE

1

RR307

4.7K

5%
1/20W
MF
201

2

1

RR308

47K

1%
1/20W
MF
201

2

BOM_COST_GROUP=SOC

78 72

ROOM=SECURE_DISABLE

BYPASS=UR300.B7::5MM

ROOM=SECURE_DISABLE

BYPASS=UR300.A5::5MM

ROOM=SECURE_DISABLE

BYPASS=UR300.A2::5MM

PP1V8_S2

1

CR303

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_MASTER=ref_secdis_sak SYNC_DATE=04/28/2020

PAGE TITLE

1

CR304

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

CR305

0.1UF

10%

6.3V

2

CERM-X5R
0201

SECDIS: FPGA

Apple Inc.

C

Right Speaker Amplifier TDM Level TranslatorA Left Speaker Amplifier TDM Level Translator

78 73

PP1V25_AWAKE_IO

PLACE_NEAR=UR900.B4:5MM

1

CR900

0.1UF

10%
25V

2

X5R
0201

VCCAVCCB

UR900

PP1V8_AWAKE

PLACE_NEAR=UR900.B6:5MM

1

CR901

0.1UF

10%
25V

2

X5R
0201

787473

PLACE_NEAR=UR900.A7:10MM

PLACE_NEAR=UR900.A3:10MM

PLACE_NEAR=UR900.A5:10MM

78 73

SN74AVC4T234

80

IN

80

IN

80

IN

80

TDM_SPKRAMP_L_BCLK
TDM_SPKRAMP_L_FSYNC
TDM_SPKRAMP_L_R2D

SPKRAMP_RESET_L

C7
C5
C3
C1

B1
B2
B3
B4

BGA

CMN_IC

GND

A1
A2
A3
A4

A7

TDM_1V8_SPKRAMP_L_BCLK_R

A5

TDM_1V8_SPKRAMP_L_FSYNC_R

A3

TDM_1V8_SPKRAMP_L_R2D_R

A1

SPKRAMP_1V8_RESET_L

RR900
RR901
RR902

21

1/20W MF 201

5%

1/20W 201MF

5%
5% 201MF1/20W

33

21

33

21

33

TDM_1V8_SPKRAMP_L_BCLK
TDM_1V8_SPKRAMP_L_FSYNC
TDM_1V8_SPKRAMP_L_R2D

80

OUT

80

OUT

80 50 80

OUT

50 74

OUTIN

80

IN

80

IN

80

IN

TDM_SPKRAMP_R_BCLK
TDM_SPKRAMP_R_FSYNC
TDM_SPKRAMP_R_R2D

PP1V25_AWAKE_IO

PLACE_NEAR=UR930.B4:5MM

1

CR930

0.1UF

10%
25V

2

X5R
0201

C7
C5
C3
C1

UR930

SN74AVC4T234

B1
B2
B3
B4

CMN_IC

VCCAVCCB

BGA

GND

PP1V8_AWAKE

PLACE_NEAR=UR930.B6:5MM

1

CR931

0.1UF

10%
25V

2

X5R
0201

A7

A1
A2
A3
A4

TDM_1V8_SPKRAMP_R_BCLK_R TDM_1V8_SPKRAMP_R_BCLK

A5

TDM_1V8_SPKRAMP_R_FSYNC_R TDM_1V8_SPKRAMP_R_FSYNC

A3

TDM_1V8_SPKRAMP_R_R2D_R TDM_1V8_SPKRAMP_R_R2D

A1

NC

787473

PLACE_NEAR=UR930.A3:10MMPLACE_NEAR=UR930.A5:10MM

PLACE_NEAR=UR930.A7:10MM

RR930
RR931
RR932

21

5% 1/20W MF 201
5% 1/20W MF 201

33

21

33

21

33

201MF5% 1/20W

OUT
OUT
OUT

50 80

50 80

78 73

SPKRAMP_LVL_DTQ

33

OUT OUT

PACK_IGNORE=TRUE

SPKRAMP_LVL_DTQ

7380

TDM_SPKRAMP_L_D2R

OUT

PACK_IGNORE=TRUE

SPKRAMP_LVL_DEA

RR910

RR910

1 2

PACK_IGNORE=TRUE
SPKRAMP_LVL_DEA

33

1 2

PLACE_NEAR=UR910.3:10MM

PLACE_NEAR=UR910.3:10MM

TDM_SPKRAMP_L_D2R_R

73

TDM_SPKRAMP_L_D2R_R

73

PP1V25_AWAKE_IO

1

2

201MF5% 1/20W

78 73

201

MF5% 1/20W

PLACE_NEAR=UR910.1:5MM

CR910

0.1UF

10%
25V
X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_LVL_DTQ

PP1V25_AWAKE_IO

PLACE_NEAR=UR910.1:5MM

1

CR910

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_LVL_DEA

VCCA VCCB

5

DIR

CMN_IC

3 4

A

VCCA VCCB

5

DIR

CMN_IC

3 4

A

PP1V8_AWAKE

PACK_IGNORE=TRUE
SPKRAMP_LVL_DTQ

311S00212

UR910

SN74AXC1T45

X2SON

B

GND

PP1V8_AWAKE

GND

TDM_1V8_SPKRAMP_L_D2R

PACK_IGNORE=TRUE
SPKRAMP_LVL_DEA

311S00273

UR910

SN74AXC1T45

X2SON-1

B

TDM_1V8_SPKRAMP_L_D2R

787473

PLACE_NEAR=UR910.6:5MM

1

CR911

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_LVL_DTQ

787473

IN

73 80

DLeft Speaker Amplifier TDM Output Level TranslatorB

73807380

Right Speaker Amplifier TDM Output Level Translator

PP1V8_AWAKE

PACK_IGNORE=TRUE
SPKRAMP_LVL_DTQ

311S00212

UR940

SN74AXC1T45

X2SON

B

GND

PP1V8_AWAKE

GND

TDM_1V8_SPKRAMP_R_D2R

PACK_IGNORE=TRUE
SPKRAMP_LVL_DEA

311S00273

UR940

SN74AXC1T45

X2SON-1

43

B

TDM_1V8_SPKRAMP_R_D2R

TDM_SPKRAMP_R_D2RTDM_SPKRAMP_L_D2R

SPKRAMP_LVL_DTQ

PACK_IGNORE=TRUE

7380

TDM_SPKRAMP_R_D2R

OUT

PACK_IGNORE=TRUE

SPKRAMP_LVL_DEA PLACE_NEAR=UR940.3:10MM

PACK_IGNORE=TRUE
SPKRAMP_LVL_DTQ

RR940

PACK_IGNORE=TRUE
SPKRAMP_LVL_DEA

RR940

33

1 2

33

78 73

73

PLACE_NEAR=UR940.3:10MM

21

TDM_SPKRAMP_R_D2R_R

PP1V25_AWAKE_IO

TDM_SPKRAMP_R_D2R_R

201

MF5% 1/20W

201

MF5% 1/20W

SPKRAMP_LVL_DTQ

PLACE_NEAR=UR940.1:5MM

1

CR940

0.1UF

10%
25V

2

X5R
0201

78 73

PP1V25_AWAKE_IO

PACK_IGNORE=TRUE

SPKRAMP_LVL_DEA

PLACE_NEAR=UR940.1:5MM

1

CR940

0.1UF

10%

PACK_IGNORE=TRUE

25V

2

X5R
0201

VCCA VCCB

5

DIR

CMN_IC

3 4

A

VCCA VCCB

5

DIR

CMN_IC

A

787473

PLACE_NEAR=UR940.6:5MM

1

CR941

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_LVL_DTQ

787473

50 73 8073 80

IN

50 73 80

78 73

PP1V25_AWAKE_IO

PLACE_NEAR=UR910.6:5MM

1

CR910

0.1UF

10%
25V

2

X5R
0201

SPKRAMP_LVL_SON

SPKRAMP_LVL_SON

78 73

CMN_IC

311S00246

UR910

SPKRAMP_LVL_SON

7380

TDM_SPKRAMP_L_D2R

OUT

SPKRAMP_LVL_SON

RR910

21

TDM_SPKRAMP_L_D2R_R

1/20W5% MF33201

PLACE_NEAR=UR910.4:10MM

SN74AUP1G17

SON

4

VCC

2

NC

NC

GND

TDM_1V8_SPKRAMP_L_D2R

73 80

7380

OUT

TDM_SPKRAMP_R_D2R

SPKRAMP_LVL_SON

RR940

SPKRAMP_LVL_SON

33

21

TDM_SPKRAMP_R_D2R_R

73

PLACE_NEAR=UR940.4:10MM

MF5% 1/20W

201

PP1V25_AWAKE_IO

PLACE_NEAR=UR940.6:5MM

1

CR940

0.1UF

10%
25V

2

X5R
0201

SPKRAMP_LVL_SON

SPKRAMP_LVL_SON

SN74AUP1G17

CMN_IC

311S00246

UR940

SON

4

VCC

2

NC

NC

GND

TDM_1V8_SPKRAMP_R_D2R

50 73 80

BOM_COST_GROUP=AUDIO

SYNC_DATE=11/18/2019SYNC_MASTER=ref_spkramp_tas5770

Audio Level Shifters

*** OK2INTEGRATE ***

78 74 73

PP1V8_AWAKE

507374

IN

41

BI

41

IN

75074

80

IN

80

80

IN

80

IN

SPKRAMP_1V8_RESET_L

SPKRAMP_A

I2C_1V8_SPKRAMP_L_SDA

SPKRAMP_A

I2C_1V8_SPKRAMP_L_SCL

SPKRAMP_A

SPKRAMP_INT_L

OUT

SPKRAMP_A

SPKRAMP_A_ADDR

74

TDM_1V8_SPKRAMP_L_R2D

SPKRAMP_A

TDM_1V8_SPKRAMP_L_D2R

OUT

SPKRAMP_A

TDM_1V8_SPKRAMP_L_FSYNC

SPKRAMP_A

TDM_1V8_SPKRAMP_L_BCLK

SPKRAMP_A

SPKRAMP_A
PLACE_NEAR=UR600.C1:6MM PLACE_NEAR=UR600.C1:4MM

1

CR600

1UF

20%
16V

2

CER-X5R
0201

SPKRAMP_A

1

CR601

0.1UF

10%
25V

2

X5R
0201

RR600

33

21

SPKRAMP_A
PLACE_NEAR=UR600.D2:6MM

1

CR602

1UF

20%
16V

2

CER-X5R
0201

PLACE_NEAR=UR600.E1:10MMSPKRAMP_A

TDM_SPKRAMP_A_D2R_R

1/20W

201MF5%

SPKRAMP_A
PLACE_NEAR=UR600.D2:4MM

1

CR603

0.1UF

10%
25V

2

X5R
0201

C3

SDZ*

F3

SDA

F4

SCL

D4

IRQZ

MODE

F2

SDIN

E1

SDOUT

E2

FSYNC

F1

SBCLK

E4

PDMD0

E3

PDMCK0

E5

PDMD1

F5

PDMCK1

AVDD IOVDD

UR600

TAS5770AC0

DSBGA

SPKRAMP_A

GND

PGND

VBAT

BST_P
OUT_P
OUT_P

VSNS_P

BST_N
OUT_N
OUT_N

VSNS_N

AREG

DREG

B2
A3
B3
A1

A2
A5D3
B5
B1

D5

D1

SPKRAMP_A

PLACE_NEAR=UR600.C5:5MM

1

CR604

10%
25V

2

X5R
0201

SPKRAMP_A_BOOTP

MIN_LINE_WIDTH=0.1000

SPKRAMP_A_OUTP_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SPKRAMP_A_BOOTN

MIN_LINE_WIDTH=0.1000

SPKRAMP_A_OUTN_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SPKRAMP_A_AREG
SPKRAMP_A_DREG

SPKRAMP_A

PLACE_NEAR=UR600.D1:3 MM

1

CR613

0.1UF

10%
25V

2

X5R
0201

SPKRAMP_A

PLACE_NEAR=UR600.C5:10MM

1

CR605

10UF

20%
25V

2

X5R-CERM
0603

BYPASS=UR600.B2:B3:10MM
NO_XNET_CONNECTION=1

CR609

CR610

BYPASS=UR600.A2:A5:10MM
NO_XNET_CONNECTION=1

SPKRAMP_A

PLACE_NEAR=UR600.D1:5 MM

1

CR614

1UF

20%
16V

2

CER-X5R

0.1UF

25V

0.1UF

25V

SPKRAMP_A

PLACE_NEAR=UR600.C5:10MM

1

CR606

10UF

20%
25V

2

X5R-CERM
0603

10%

21

21

SPKRAMP_A

0201

X5R

* SEE NOTE

10%

SPKRAMP_A

0201

X5R

* SEE NOTE

SPKRAMP_A

PLACE_NEAR=UR600.D5:3 MM

1

CR615

0.1UF

10%
25V

2

X5R
0201

SPKRAMP_A

PLACE_NEAR=UR600.C5:10MM

1

CR607

10UF0.1UF

20%
25V

2

X5R-CERM
0603

RR601

0

21

0%
MF 1/4W

SPKRAMP_A

0603

RR602

0

0%
MF

SPKRAMP_A

21

0603
1/4W

SPKRAMP_A

PLACE_NEAR=UR600.D5:5 MM

1

CR616

1UF

20%
16V

2

CER-X5R
0201

1

2

* SEE NOTE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

* SEE NOTE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SPKRAMP_A

CR611

NOSTUFF

PPBUS_AON_L_SPKRAMP

MAX CURRENT EDC = 4A (PER AMP)

SPKRAMP_A

PLACE_NEAR=UR600.C5:10MM

CR608

10UF

20%
35V
X5R-CERM
0603

SPKRAMP_A_OUTP

SPKRAMP_A_VSENSEP

* SEE NOTE

SPKRAMP_A_OUTN

SPKRAMP_A_VSENSEN

* SEE NOTE

SPKRAMP_A

1

CR612

220PF

10%
25V

2

X7R-CERM
201

NOSTUFF

220PF

10%
25V

X7R-CERM

201

1

2

79

AMP A

SPKRAMP_A

SPKRAMP_A

SPKRAMP_A

SPKRAMP_A

OUT

OUT

IN

IN

78 74 73

75

75

75

75

PP1V8_AWAKE

SPKRAMP_A_ADDR

74

0X62

SPKRAMP_B_ADDR

74

0X64

SPKRAMP_C_ADDR

74

0X66

SPKRAMP_A

PACK_IGNORE=TRUE
SPKRAMP_B

SPKRAMP_C

RR605

RR635

PACK_IGNORE=TRUE

RR664

2 1

0

5%

1/20W

MF

0201

470

5%

1/20W

MF

201

470

5%

1/20W

MF

201

21

21

78 74 73

PP1V8_AWAKE

SPKRAMP_1V8_RESET_L

507374

75074

74

PACK_IGNORE=TRUE

IN

SPKRAMP_B

=I2C_1V8_SPKRAMP_B_SDA

PACK_IGNORE=TRUE

BI

SPKRAMP_B

=I2C_1V8_SPKRAMP_B_SCL

PACK_IGNORE=TRUE

IN

SPKRAMP_B

SPKRAMP_INT_L

PACK_IGNORE=TRUE

OUT

SPKRAMP_B

SPKRAMP_B_ADDR

=TDM_1V8_SPKRAMP_B_R2D

PACK_IGNORE=TRUE

IN

SPKRAMP_B

=TDM_1V8_SPKRAMP_B_D2R

PACK_IGNORE=TRUE

OUT

SPKRAMP_B

=TDM_1V8_SPKRAMP_B_FSYNC

PACK_IGNORE=TRUE

IN

SPKRAMP_B

=TDM_1V8_SPKRAMP_B_BCLK

PACK_IGNORE=TRUE

IN

SPKRAMP_B

PACK_IGNORE=TRUE
SPKRAMP_B
PLACE_NEAR=UR630.C1:6MM

1

CR630

1UF

20%
16V

2

CER-X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_B
PLACE_NEAR=UR630.C1:4MM

1

CR631

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE

RR630

33

21

PACK_IGNORE=TRUE
SPKRAMP_B
PLACE_NEAR=UR630.D2:6MM

1

CR632

1UF

20%
16V

2

CER-X5R
0201

PLACE_NEAR=UR630.E1:10MMSPKRAMP_B

TDM_SPKRAMP_B_D2R_R

201MF1/20W5%

PACK_IGNORE=TRUE
SPKRAMP_B
PLACE_NEAR=UR630.D2:4MM

1

CR633

0.1UF

10%
25V

2

X5R
0201

C3

SDZ*

F3

SDA

F4

SCL

D4

IRQZ

MODE

F2

SDIN

E1

SDOUT

E2

FSYNC

F1

SBCLK

E4

PDMD0

E3

PDMCK0

E5

PDMD1

F5

PDMCK1

AVDD IOVDD

UR630

TAS5770AC0

DSBGA

PACK_IGNORE=TRUE
SPKRAMP_B

GND

PGND

VBAT

BST_P
OUT_P
OUT_P

VSNS_P

BST_N
OUT_N
OUT_N

VSNS_N

AREG

DREG

B2
A3
B3
A1

A2
A5D3
B5
B1

D5

D1

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.C5:5MM

1

CR634

0.1UF

10%
25V

2

X5R
0201

SPKRAMP_B_BOOTP

MIN_LINE_WIDTH=0.0970

SPKRAMP_B_OUTP_R

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

SPKRAMP_B_BOOTN

MIN_LINE_WIDTH=0.0970

SPKRAMP_B_OUTN_R

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

SPKRAMP_B_AREG
SPKRAMP_B_DREG

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.D1:3 MM

1

CR643

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.C5:10MM

1

CR635

10UF

20%
25V

2

X5R-CERM
0603

BYPASS=UR630.B2:B3:10MM
NO_XNET_CONNECTION=1

CR639

CR640 SPKRAMP_B

BYPASS=UR630.A2:A5:10MM
NO_XNET_CONNECTION=1

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.D1:5 MM

1

CR644

1UF

20%
16V

2

CER-X5R
0201

0.1UF

25V

0.1UF

25V

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.C5:10MM

1

CR636

10UF

20%
25V

2

X5R-CERM
0603

PACK_IGNORE=TRUE

10%

21

21

SPKRAMP_B

0201

X5R

* SEE NOTE

PACK_IGNORE=TRUE

10%

0201

X5R

* SEE NOTE

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.D5:3 MM

1

CR645

0.1UF

10%
25V

2

X5R
0201

RR631

0

0%

PACK_IGNORE=TRUE
SPKRAMP_B

21

RR632

0

0%
MF

PACK_IGNORE=TRUE
SPKRAMP_B

21

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.D5:5 MM

1

2

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.C5:10MM

1

CR637

10UF

20%
25V

2

X5R-CERM
0603

0603
1/4WMF

0603

* SEE NOTE

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

* SEE NOTE

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

CR646

1UF

20%
16V
CER-X5R
0201

=PPBUS_AON_B_SPKRAMP

MAX CURRENT EDC = 4A (PER AMP)

PACK_IGNORE=TRUE
SPKRAMP_B

PLACE_NEAR=UR630.C5:10MM

1

CR638

10UF

20%
35V

2

X5R-CERM
0603

PACK_IGNORE=TRUE
SPKRAMP_B

10%
25V

201

1

2

CR641

220PF

X7R-CERM

NOSTUFF

AMP B

SPKRAMP_B_OUTP

SPKRAMP_B_VSENSEP

* SEE NOTE

SPKRAMP_B_OUTN

SPKRAMP_B_VSENSEN

* SEE NOTE

PACK_IGNORE=TRUE
SPKRAMP_B

1

CR642

220PF

10%
25V

2

X7R-CERM
201

NOSTUFF

PACK_IGNORE=TRUE
SPKRAMP_B

PACK_IGNORE=TRUE
SPKRAMP_B

PACK_IGNORE=TRUE
SPKRAMP_B

PACK_IGNORE=TRUE
SPKRAMP_B

OUT

IN

OUT

IN

PP1V25_AWAKE_IO

78

PACK_IGNORE=TRUE
SPKRAMP_EXT_PU

75074

507374

IN

SPKRAMP_INT_L

OUT

SPKRAMP_1V8_RESET_L

PACK_IGNORE=TRUE
SPKRAMP_EXT_PU

1

RR691

47K

5%
1/20W
MF
201

2

1

RR692

47K

5%
1/20W
MF
201

2

78 74 73

PP1V8_AWAKE

SPKRAMP_1V8_RESET_L

507374

75074

74

PACK_IGNORE=TRUE

IN

SPKRAMP_C

=I2C_1V8_SPKRAMP_C_SDA

PACK_IGNORE=TRUE

BI

SPKRAMP_C

=I2C_1V8_SPKRAMP_C_SCL

PACK_IGNORE=TRUE

IN

SPKRAMP_C

SPKRAMP_INT_L

PACK_IGNORE=TRUE

OUT

SPKRAMP_C

SPKRAMP_C_ADDR

=TDM_1V8_SPKRAMP_C_R2D

PACK_IGNORE=TRUE

IN

SPKRAMP_C

=TDM_1V8_SPKRAMP_C_D2R

PACK_IGNORE=TRUE

OUT

SPKRAMP_C

=TDM_1V8_SPKRAMP_C_FSYNC

PACK_IGNORE=TRUE

IN

SPKRAMP_C

=TDM_1V8_SPKRAMP_C_BCLK

PACK_IGNORE=TRUE

IN

SPKRAMP_C

PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.C1:6MM

1

CR660

1UF

20%
16V

2

CER-X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.C1:4MM

1

CR661

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE

RR660

33

21

PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.D2:6MM

1

CR662

1UF

20%
16V

2

CER-X5R
0201

PLACE_NEAR=UR660.E1:10MMSPKRAMP_C

TDM_SPKRAMP_C_D2R_R

5% 1/20W 201

MF

PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.D2:4MM

1

CR663

0.1UF

10%
25V

2

X5R
0201

C3

SDZ*

F3

SDA

F4

SCL

D4

IRQZ

MODE

F2

SDIN

E1

SDOUT

E2

FSYNC

F1

SBCLK

E4

PDMD0

E3

PDMCK0

E5

PDMD1

F5

PDMCK1

AVDD IOVDD

UR660

TAS5770AC0

DSBGA

PACK_IGNORE=TRUE
SPKRAMP_C

GND

PGND

VBAT

BST_P
OUT_P
OUT_P

VSNS_P

BST_N
OUT_N
OUT_N

VSNS_N

AREG

DREG

B2
A3
B3
A1

A2
A5D3
B5
B1

D5

D1

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.C5:5MM

1

CR664

0.1UF

10%
25V

2

X5R
0201

SPKRAMP_C_BOOTP

MIN_LINE_WIDTH=0.0970

SPKRAMP_C_OUTP_R

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

SPKRAMP_C_BOOTN

MIN_LINE_WIDTH=0.0970

SPKRAMP_C_OUTN_R

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

SPKRAMP_C_AREG
SPKRAMP_C_DREG

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.D1:3 MM

1

CR673

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.C5:10MM

1

CR665

10UF

20%
25V

2

X5R-CERM
0603

BYPASS=UR660.B2:B3:10MM
NO_XNET_CONNECTION=1

CR669

CR670

BYPASS=UR660.A2:A5:10MM
NO_XNET_CONNECTION=1

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.D1:5 MM

1

CR674

1UF

20%
16V

2

CER-X5R
0201

0.1UF

25V

0.1UF

25V

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.C5:10MM

1

CR666

10UF

20%
25V

2

X5R-CERM
0603

PACK_IGNORE=TRUE

10%

21

21

SPKRAMP_C

0201

X5R

* SEE NOTE

PACK_IGNORE=TRUE

10%

SPKRAMP_C

0201

X5R

* SEE NOTE

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.D5:3 MM

1

CR675

0.1UF

10%
25V

2

X5R
0201

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.C5:10MM

1

CR667

10UF

20%
25V

2

X5R-CERM
0603

RR661

0

0%
MF 1/4W

PACK_IGNORE=TRUE
SPKRAMP_C

21

0603

RR662

0

0%
MF

PACK_IGNORE=TRUE
SPKRAMP_C

21

0603
1/4W

PACK_IGNORE=TRUE
SPKRAMP_C

PLACE_NEAR=UR660.D5:5 MM

1

CR676

1UF

20%
16V

2

CER-X5R
0201

1

2

* SEE NOTE

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

* SEE NOTE

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.0970

PACK_IGNORE=TRUE
SPKRAMP_C

CR671

NOSTUFF

=PPBUS_AON_C_SPKRAMP

PACK_IGNORE=TRUE

MAX CURRENT EDC = 4A (PER AMP)

SPKRAMP_C

PLACE_NEAR=UR660.C5:10MM

CR668

10UF

20%
35V
X5R-CERM
0603

AMP C

SPKRAMP_C_OUTP

SPKRAMP_C_VSENSEP

* SEE NOTE

SPKRAMP_C_OUTN

SPKRAMP_C_VSENSEN

PACK_IGNORE=TRUE

* SEE NOTE

SPKRAMP_C

220PF

10%
25V

X7R-CERM

201

1

2

1

CR672

220PF

10%
25V

2

X7R-CERM
201

NOSTUFF

PACK_IGNORE=TRUE
SPKRAMP_C

PACK_IGNORE=TRUE
SPKRAMP_C

PACK_IGNORE=TRUE
SPKRAMP_C

PACK_IGNORE=TRUE
SPKRAMP_C

OUT

IN

OUT

IN

NOTES:

- CHECK THAT SPKRAMP_INT_L
HAS IPU ON SOC SIDE.

- VSENSEP/N SIGNALS CONNECT
TO OUTP/N SIGNALS AT THE
SPEAKER CONNECTOR PINS.

- THE FOLLOWING SIGNALS SHOULD
HAVE A VERY LOW DCR PATH:

- SPKRAMP_XX_OUTP/N_R

- SPKRAMP_XX_OUTP/N

- PVDD SUPPLY

- FOR THERMALS PGND PINS MUST
CONNECT TO GND LAYERS USING
COPIOUS AMOUNT OF VIAS.

SYNC_MASTER=ref_spkramp_tas5770

PAGE TITLE

AUDIO AMPLIFIERS (1/2)

BOM_COST_GROUP=AUDIO

A Left Speaker Amplifier Bulk Capacitors

PPBUS_AON_L_SPKRAMP

CRITICAL

1

CR810

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CRITICAL

1

CR811

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CRITICAL

1

CR812

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

B Left Speaker Connector

74

74

IN

7

74

IN

74

SPKRAMP_A_VSENSEP

OUT

SPKRAMP_A_OUTP
SPKR_ID0

OUT

SPKRAMP_A_OUTN

SPKRAMP_A_VSENSEN

OUT

78 75 35

XWR820

XWR821

PP1V25_AWAKE_IO

NOSTUFF

SM

21

SM

21

RR820

47K

5%

1/20W

MF

201

1

CR820

3PF

+/-0.1PF
25V

2

C0G
0201

79

1

JR820

78171-0004

M-RT-SM

5

2

1

CR821

3PF

+/-0.1PF
25V

2

C0G
0201

1
2
3
4

6

518S0521

C Right Speaker ID

78 75 35

7

PP1V25_AWAKE_IO

SPKR_ID1

OUT

NOSTUFF

RR830

47K

5%

1/20W

MF

201

1

2

D Audio Jack CODEC Pull-Ups

PP1V25_S2

PP1V8_S2

NOSTUFF NOSTUFF

1

RR840

5%
1/20W
MF
201

2

1

RR841

47K47K

5%
1/20W
MF
201

2

CODEC_WAKE_L
CODEC_INT_L

7850

78

34 50

IN

7 50

IN

E DMic Connector

72

IN

72

OUT

78

79 71

7172

OUT

72

IN

72

OUT

DMIC_CLK1_1V8_OUT
DMIC_DATA1_1V8_IN
PP1V8_S2
PP1V8_AON
AMR_LEFT_OR_ND_1V8

DMIC_CLK0_1V8_OUT
DMIC_DATA0_1V8_IN

CR851

100PF

5%
25V
C0G

0201

JR850

FF18-8A-R11AD-B-3H

1

2

1

CR850

100PF

5%
25V

2

C0G
0201

F-RT-SM1

1
2
3
4
5
6
7
8

518S00170

DESIGN: T651/MLB
LAST CHANGE: Fri Oct 11 18:06:02 2019

SYNC_MASTER=tga_140

PAGE TITLE

BOM_COST_GROUP=AUDIO

Audio Connectors

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

Trackpad SPI Bus Level Shifter (+1.2V to +3.3V)A

78 76

7

IN

20

IN

20

IN

7 77

OUT

SPI_IPD_MISO SPI_IPD_MISO_R SPI_IPD_MISO_CONN

PP1V25_AWAKE_IO

RT304

5%

PLACE_NEAR=UT360.5:2MM

20

21

RT305

RT303

47K

5%

1/20W

MF

201

201MF1/20W

1

5%

1/20W

MF

201

2

1

2

RT306

BYPASS=UT360::5MM

1

47K47K

5%
MF

201

2

CT360

0.1UF

10%

6.3V

CERM-X5R

0201

SPI_IPD_CS_L

SPI_IPD_CLK

SPI_IPD_MOSI

47K

1/20W1/20W

201

1

5%
MF

2

RT307

BYPASS=UT360::5MM

1

2

VCCBVCCA

UT360

SN74AVC4T774-COMBO

15

16

1

A1
DIR1

2

A2
DIR2

3

A3

5

DIR3

4

A4

6

DIR4

7

OE*

QFN

CMN_IC

GND

B1

B2

B3

B4

12

11

10

9

1

CT361

0.1UF

10%

6.3V

2

CERM-X5R
0201

SPI_IPD_CS_CONN_L

RT374

100K

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

1

2

1

2

RT373

100K

1

2

RT371

100K

PP3V3_S2SW_IPD

5%

1/20W

MF

201

1

2

RT372

100K

797776

RT375

PLACE_NEAR=UT360.9:2MM

RT376

1/20W MF 2015%

PLACE_NEAR=UT360.8:2MM

20

20

21

MF5% 2011/20W

21

OUT

SPI_IPD_CLK_CONNSPI_IPD_CLK_CONN_R

SPI_IPD_MOSI_CONNSPI_IPD_MOSI_CONN_R

OUT

OUT

IN

77

77

77

PP1V25_S2

78

80

Trackpad I2C Bus Level Shifter

RT363

10K

5%

1/20W

MF

201

PP3V3_S2SW_IPD

1

1

VCC

UT365

2

IPD_SPI_INT_L

NC NC

74AUP1G07GF

SOT891

4

Y A

5

NC NC

GND

2

1

CT365

0.1UF

10%

6.3V

2

CERM-X5R
0201

CB

BYPASS=UT365::5MM

IPD_SPI_INT_CONN_L

Trackpad Wake Level Shifter

1

RT364

100K

5%
1/20W
MF
201

2

797776

77

INOUT

78 40 37

78 76

43

BI

43

IN

I2C_SMC_IPD_SDA
I2C_SMC_IPD_SCL

PP1V25_AWAKE_IO

VREF_A VREF_B

3

A1

4

A2 B2

CMN_IC

VBIAS_I2CIPD

UT310

LSF0102

X2SON

GND

EN

B1

PP3V3_S2SW_IPD

1

RT311

200K

5%
1/20W
MF
201

8

6

5

2

1

CT310

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

RT312

4.7K

5%
1/20W
MF
201

2

1

RT313

4.7K

5%
1/20W
MF
201

2

I2C_SMC_IPD_3V3_SDA
I2C_SMC_IPD_3V3_SCL

BI

OUT

797776

77

77

35

OUT

PP1V8_AON_MPMU

IPD_WAKE_L

RT365

100K

5%

1/20W

MF

201

1

2

NC

VCC

UT330

74AUP1G07GF

SOT891

Y A

4

5

NC NC

GND

1

CT330

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=UT330::2MM

2

1

NC

IPD controller output is not fail-safe.
It pulls down this signal when un-powered
through the ESD diode.

1

RT330

100K

5%
1/20W
MF
201

2

PP3V3_S2SW_IPD

IPD_WAKE_3V3_L

797776

77

IN

D

BYPASS=UT310::5MM

Trackpad SPI Enable Level Shifter

78 76

81 77

IN OUT

PP1V25_AWAKE_IO

BYPASS=UT355::5MM

10%

6.3V
0201

1

SON

GND

VCC_B

42

B

2

NC

VCC_A

SN74AUP1T34-COMBO

5

UT355

A

NC

CT355

0.1UF

CERM-X5R

IPD_SPI_EN IPD_SPI_EN_CONN

47K

5%

1/20W

MF

201

1

2

RT352

BYPASS=UT355::5MM

1

CT356

0.1UF

10%

6.3V

2

CERM-X5R
0201

PP3V3_S2SW_IPD

NOSTUFF

1

RT354

100K

5%
1/20W
MF
201

2

1

RT353

100K

5%
1/20W
MF
201

2

797776

Trackpad Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

BOM_COST_GROUP=TRACKPAD

5

A B IPD Power Filters C IPD Desense

IPD B2B CONNECTOR

Bottom side contacts used
Pinout reversed from flex

PPBUS_AONSW_IPD

79

77

70

777983

70

77

76

76

76

76

76

77

PP3V3_AON_IPD_F
KBDLED_CATHODE1
PPVOUT_KBDBKLT
KBDLED_CATHODE2
PP3V3_S2_IPD_F
I2C_SMC_IPD_3V3_SCL

SPI_IPD_MISO_CONN
SPI_IPD_CS_CONN_L

IPD_SPI_EN_CONN
IPD_WAKE_3V3_L

PP5V_S2_IPD_F

CRITICAL

LT400

30-OHM-5A

0603

CT400

21

0.1UF

10%
25V
X5R

0201

CRITICAL

LT401

FERR-120-OHM-1.5A

PPBUS_AON_IPD_FLT

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000

VOLTAGE=13.1V

1

516S0784

2

CRITICAL

JT400

PP3V3_AON_IPD_F

77

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000

VOLTAGE=3.3V

CT401

0.1UF

10%
10V

X5R-CERM

0201

2 1

0402-LF

1

2

PP3V3_AON

15mA

(mostly Capslock LED)

7977

79 76

79 77

AA03-S042VA1

F-ST-SM

NC

NC
NC

4443

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241

4645

PMU_RSLOC_RST_L

PPVOUT_KBDBKLT

PP3V3_S2_IPD_F
I2C_SMC_IPD_3V3_SDA
SPI_IPD_CLK_CONN

SPI_IPD_MOSI_CONN
IPD_SPI_INT_CONN_L

NC

IPD_LID_OPEN_1V8

34 35 77 82

77 79 83

77

76

76

76

76

PP3V3_S2_IPD_F

77

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000

CT402

0.1UF

10%
10V

X5R-CERM

0201

FERR-120-OHM-1.5A

1

2

FERR-120-OHM-1.5A

PP5V_S2_IPD_F

77

34 71 77 34 35 77 82

MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.1000

CT403

0.1UF

10%
10V

X5R-CERM

0201

1

2

CRITICAL

LT402

2 1

0402-LF

CRITICAL

LT403

2 1

0402-LF

PP3V3_S2SW_IPD

300mA

PP5V_S2SW_IPD

200mA

79

79

PP3V3_S2SW_IPD
PP3V3_AON

IPD ControlD

BYPASS=JT400.2::1.5MM

1

CT410

100PF

5%
25V

2

C0G
0201

CT475

PMU_RSLOC_RST_L

1

2

1

CT476

3PF

+/-0.1PF
25V

2

C0G

12PF

5%

25V
CERM
0201

1

2

IPD_LID_OPEN_1V8

BYPASS=JT400.30::1.5MM

CT412

100PF

5%
25V
C0G
0201

CT477

34 71 77

12PF

5%

25V
CERM
02010201

1

2

1

CT478

3PF

+/-0.1PF
25V

2

C0G
0201

F IPD Connector Bosses

860-01262860-01262

SHT400

BOSS-3.05OD1.15ID-1.11H-SM

1

SHT401

BOSS-3.05OD1.15ID-1.11H-SM

1

BOM_COST_GROUP=TRACKPAD

IPD Combined Connector

SERA BUCK0 (ACTIVE)

PPVDD_PCPU_AWAKE

MAKE_BASE=TRUE

VOLTAGE=1.06V

PPVDD_PCPU_AWAKE
PPVDD_PCPU_AWAKE

SERA BUCK1 (SW CTRL)

PPVDD_GPU_AWAKE

83

MAKE_BASE=TRUE

VOLTAGE=1.06V

PPVDD_GPU_AWAKE
PPVDD_GPU_AWAKE

SERA BUCK2 (SLEEP1)

PPVDD_SOC_S1

83

MAKE_BASE=TRUE

VOLTAGE=0.86V

PPVDD_SOC_S1
PPVDD_SOC_S1

SERA BUCK3 (SLEEP3)

PP1V8_S2

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S2

72

PP1V8_S2

21

PP1V8_S2

54

PP1V8_S2

78 54

PP1V8_S2

78 75

PP1V8_S2

78 54

PP1V8_S2

60

PP1V8_S2

49

PP1V8_S2

49

PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2

PP1V8_S2

PP1V8_S2
PP1V8_S2
PP1V8_S2
PP1V8_S2

SIMETRA BUCK4 (SLEEP3)

PP1V06_S2SW_DRAM

83

MAKE_BASE=TRUE

VOLTAGE=1.1V

PP1V06_S2SW_DRAM

PP1V06_S2SW_DRAM

PP1V06_S2SW_DRAM

32

1813

32

1813

3532

13

33

54

54

29

28

32

40

33

7875

75

2423

68

42

66

42

43

28

1811

29

75 50

SIMETRA BUCK13 (ACTIVE)

PP1V25_S2

82

MAKE_BASE=TRUE

VOLTAGE=1.25V

PP1V25_S2

42

PP1V25_S2

42

PP1V25_S2

76

PP1V25_S2

49

PP1V25_S2

43

PP1V25_S2

43

PP1V25_S2

43

PP1V25_S2

41

PP1V25_S2
PP1V25_S2

34

PP1V25_S2

60

PP1V25_S2

58

SERA BUCK14 (ACTIVE)

PP1V4_LDO_PREREG

MAKE_BASE=TRUE

VOLTAGE=1.40V

POWER CONNECTIONS

PP1V25_S2
PP1V25_S2
PP1V25_S2
PP1V25_S2
PP1V25_S2
PP1V25_S2
PP1V25_S2
PP1V25_S2 28
PP1V25_S2
PP1V25_S2
PP1V25_S2 32
PP1V25_S2
PP1V25_S2
PP1V25_S2
PP1V25_S2

PP1V25_S2

PP1V4_LDO_PREREG
PP1V4_LDO_PREREG

28

1210

12

15

15

15

21

3029

33

565553

24

70

29

35

35

35

SIMETRA LDO8 (SLEEP2)

PP1V2_AWAKE_PLL

83

MAKE_BASE=TRUE

VOLTAGE=1.2V

SERA LDO9 (ACTIVE)

PP1V8_AON_MPMU

MAKE_BASE=TRUE

SERA LDO10 (ACTIVE)

SIMETRA LDO11 (SLEEP2)

PP0V855_S2SW_CIO

MAKE_BASE=TRUE

VOLTAGE=0.86V

PP1V2_AWAKE_PLL

PP1V2_AWAKE_PLL
PP1V2_AWAKE_PLL
PP1V2_AWAKE_PLL
PP1V2_AWAKE_PLL

PP1V8_AON_MPMU
PP1V8_AON_MPMU
PP1V8_AON_MPMU
PP1V8_AON_MPMU
PP1V8_AON_MPMU

PP0V855_S2SW_CIO
PP0V855_S2SW_CIO
PP0V855_S2SW_CIO

29

15

11

15

15

34

3430

24

36

764037

SERA SW1 (ACTIVE)

PP1V8_AWAKE

MAKE_BASE=TRUE

29

15

15

PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE

33

12

7473

5

19

19

50

41

SIMETRA BUCK5 (SLEEP1)

PP0V764_S1_SRAM

MAKE_BASE=TRUE

VOLTAGE=0.8V

PP0V764_S1_SRAM
PP0V764_S1_SRAM

SIMETRA BUCK6 (ACTIVE)

PP2V5_AWAKE_NAND

3183

MAKE_BASE=TRUE

VOLTAGE=2.63V

PP2V5_AWAKE_NAND
PP2V5_AWAKE_NAND

SERA BUCK7 (ACTIVE)

PPVDD_CPU_SRAM_AWAKE

MAKE_BASE=TRUE

VOLTAGE=1.1V

PPVDD_CPU_SRAM_AWAKE
PPVDD_CPU_SRAM_AWAKE

SERA BUCK8 (SW CTRL)

PPVDD_DISP_S1

83

MAKE_BASE=TRUE

VOLTAGE=0.94V

PPVDD_DISP_S1
PPVDD_DISP_S1

SERA BUCK9 (SLEEP1)

PPVDD_DCS_S1

MAKE_BASE=TRUE

VOLTAGE=0.85V

PPVDD_DCS_S1
PPVDD_DCS_S1

28

1814

SIMETRA LDO12 (SLEEP2)

PP0V805_S1_VDD_FIXED

83

MAKE_BASE=TRUE

SERA LDO1 (SLEEP2)

NC_MPMU_VLDO1

28

646362

33

1814

33

1813

33

1814

MAKE_BASE=TRUE

SERA LDO2 (SLEEP2)

NC_MPMU_VLDO1

34

VOLTAGE=0.805V

SERA LDO13 (SW CTRL)

PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED

PP0V805_S1_VDD_FIXED

29

1815

15

15

15

1815

15

15

15

15

SERA SW3 (ACTIVE)

PP1V25_AWAKE_IO

83

MAKE_BASE=TRUE

PP1V25_AWAKE_IO

PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO

PP1V25_AWAKE_IO

PP1V25_AWAKE_IO

PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO

PP1V25_AWAKE_IO

PP1V25_AWAKE_IO

PP1V25_AWAKE_IO

33

15

129765

15

15

15

74

15

15

7535

76

73

50

5

19

41

41

41

SIMETRA BUCK10 (SLEEP1)

PP0V6_S1_VDDQL

83

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S1_VDDQL
PP0V6_S1_VDDQL

SERA BUCK11 (ACTIVE)

PPVDD_ECPU_AWAKE

83

MAKE_BASE=TRUE

VOLTAGE=1.06V

PPVDD_ECPU_AWAKE
PPVDD_ECPU_AWAKE

SIMETRA BUCK12 (ACTIVE)

PP0V88_S1

MAKE_BASE=TRUE

VOLTAGE=0.88V

PP0V88_S1
PP0V88_S1

SERA LDO3 (SLP_S2R)

PP1V2_S2

28

1811

33

1813

MAKE_BASE=TRUE

VOLTAGE=1.2V

PP1V2_S2

PP1V2_S2

34

72

SERA LDO16 (SW CTRL)

SIMETRA SW4 (SLEEP2)
SIMETRA SW5 (SLEEP2)

PP1V25_AWAKE_NAND

83

MAKE_BASE=TRUE

VOLTAGE=1.25V

PP1V25_AWAKE_NAND

PP1V25_AWAKE_NAND

29

6362

SERA LDO19 (SPARE)

SIMETRA SW6 (SLEEP2) PARALLEL

28

29

SIMETRA LDO4 (SW CTRL)

PP0V72_S2_VDD_LOW

83

MAKE_BASE=TRUE

VOLTAGE=0.72V

PP0V72_S2_VDD_LOW

PP0V72_S2_VDD_LOW
PP0V72_S2_VDD_LOW
PP0V72_S2_VDD_LOW
PP0V72_S2_VDD_LOW
PP0V72_S2_VDD_LOW

29

1815

15

15

15

15

SIMETRA LDO20 (SW CTRL)

PP1V2_S2_CIO

83

MAKE_BASE=TRUE

PP1V2_S2_CIO
PP1V2_S2_CIO
PP1V2_S2_CIO

29

15

15

SIMETRA SW7 (SLEEP2) PARALLEL

PP0V88_AWAKE_NAND

83

MAKE_BASE=TRUE

VOLTAGE=0.88V

PP0V88_AWAKE_NAND
PP0V88_AWAKE_NAND
PP0V88_AWAKE_NAND

Power Aliases - 1

29

62

63

SERA LDO7 (SW CTRL)

PP3V3_S2_UPC

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S2_UPC

PP3V3_S2_UPC

34

565553

PBUS Rails

3V3 Rails

UXXXX - 3V3_S2U7000 - PBUS

23

PPBUS_AON

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_AON
PPBUS_AON

27

69

PP3V3_S2

39

Sourced from PBus
Enabled by ????

PPBUS_AON 46
PPBUS_AON
PPBUS_AON
PPBUS_AON
PPBUS_AON
PPBUS_AON

50

40

44

2625

32

PPBUS_AON 44
PPBUS_AON 44

PPBUS_5VS2_VIN44

PPBUS_3V3S2_VIN44

PPBUS_5VS2_VIN

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_5VS2_VIN
PPBUS_3V3S2_VIN

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PP3V3_S2_WLBT46

38

PP3V3_S2PPBUS_AON

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S2
PP3V3_S2
PP3V3_S2
PP3V3_S2
PP3V3_S2
PP3V3_S2
PP3V3_S2
PP3V3_S2
PP3V3_S2

PP3V3_S2_WLBT

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S2_WLBT

8283

46

37

66

70

40

68

40

39

43

60

PPBUS_AON_L_SPKRAMP46

PPBUS_AONSW_IPD40

PPDCIN_AONSW

53

U7550 - 5V G3S

PP5V_S2

38

Sourced from PBus
Enabled by P5VG3S_EN

PP5V_S2_KBDLED

46

PP5V_AON_P3V8VRLDO

25

PPBUS_3V3S2_VIN

PPBUS_AON_L_SPKRAMP

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_AON_L_SPKRAMP
PPBUS_AON_L_SPKRAMP

PPBUS_AONSW_IPD

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_AONSW_IPD

PPDCIN_AONSW

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=20V
MAKE_BASE=TRUE

PPDCIN_AONSW
PPDCIN_AONSW

PP5V_S2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_S2
PP5V_S2
PP5V_S2
PP5V_S2
PP5V_S2
PP5V_S2
PP5V_S2
PP5V_S2
PP5V_S2
PP5V_S2

PP5V_S2_KBDLED

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_S2_KBDLED

PP5V_AON_P3V8VRLDO

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_AON_P3V8VRLDO

39

83

75

74

PP3V3_S2SW_SNS40

PP3V3_S2SW_IPD40

77

23

44

83

37

46

67

69

38

68

5655

5655

40

27

83

70

PP3V3_SW_LCD68

PP3V3_AON

36

Sourced from PBus

PP1V8_AON

MAKE_BASE=TRUE

25

PP3V3_S2SW_SNS

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S2SW_SNS

PP3V3_S2SW_IPD

MIN_LINE_WIDTH=0.0970
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S2SW_IPD
PP3V3_S2SW_IPD

PP3V3_SW_LCD

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_SW_LCD

PP3V3_AON

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_AON
PP3V3_AON

PP3V3_AON

PP1V8_AON
PP1V8_AON

464544

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000
VOLTAGE=55V
MAKE_BASE=TRUE

PPVOUT_LCDBKLT

7776

77

67

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=40V

41

MAKE_BASE=TRUE

PPVOUT_KBDBKLT

82

PP3V3_S2SW_USBC0

MAKE_BASE=TRUE

PP3V3_S2SW_USBC0

77

43

PP3V3_S2SW_USBC0
PP3V3_S2SW_USBC0
PP3V3_S2SW_USBC0
PP3V3_S2SW_USBC0

35

PPVOUT_LCDBKLT

PPVOUT_KBDBKLT

67 83

69

77 83

70

51

5351

5351

58

58

PP3V3_S2SW_USBC1

MAKE_BASE=TRUE

PP3V3_S2SW_USBC1
PP3V3_S2SW_USBC1
PP3V3_S2SW_USBC1
PP3V3_S2SW_USBC1

36
50VOLTAGE=1.8V

PP3V3_S2SW_USBC1

52

5352

5352

58

58

PP5V_SW_LCD

68

PP5V_S2SW_IPD

40

CHARGER MAIN

PP3V8_AON_VDDMAIN

8283

MAKE_BASE=TRUE

VOLTAGE=3.8V

PP5V_SW_LCD

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
MAKE_BASE=TRUE

67

PP5V_S2SW_IPD

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_S2SW_IPD
PP5V_S2SW_IPD

PP3V8_AON_VDDMAIN

77

46

26

PP3V8_AON_VDDMAIN 353432
PP3V8_AON_VDDMAIN 2928

PP3V8_AON_VDDMAIN

PP3V8_AON_VDDMAIN
PP3V8_AON_VDDMAIN
PP3V8_AON_VDDMAIN

PP3V8_AON_VDDMAIN

PP3V8_AON_VDDMAIN
PP3V8_AON_VDDMAIN

PP3V8_AON_VDDMAIN
PP3V8_AON_VDDMAIN
PP3V8_AON_VDDMAIN
PP3V8_AON_VDDMAIN

50

40

36

36

27

21

51

52

22

32

37

PP1V8_S2SW_VDD1

MAKE_BASE=TRUE

VOLTAGE=1.8V

NEED TO CHECK THE SPLIT

TO DIFFERENT SWITCH OUTPUTS.

Digital Ground

GND

VOLTAGE=0V
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0800

PP1V8_AON
PP1V8_AON
PP1V8_AON

PP1V8_S2SW_VDD1
PP1V8_S2SW_VDD1

40

35

7571

40

1811

Power Aliases - 2

NC_DFR_1V8_DISP_INT

7

NC_DFR_1V8_DISP_RESET_L

7

NC_DFR_1V8_TOUCH_RESET_L

7

NC_DFR_DISP_TE

8

NC_DFR_PWR_EN

7

NC_HDMI_CEC_AOP_RX

10

NC_HDMI_CEC_AOP_TX

10

NC_HDMI_HPD_AOP

10

NC_MIPI_DFR_CLKN

8

NC_MIPI_DFR_CLKP

8

NC_MIPI_DFR_DATAN

8

NC_MIPI_DFR_DATAP

8

NC_PCIE_CLK100M_ENETN

9

NC_PCIE_CLK100M_ENETP

9

NC_PCIE_CLK100M_USBHCN

9

NC_PCIE_CLK100M_USBHCP

9 NO_TEST=1

NC_PCIE_ENET_D2RN

9

NC_PCIE_ENET_D2RP

9

NC_PCIE_ENET_R2DCN

9

NC_PCIE_ENET_R2DCP

9

NC_PCIE_USBHC_D2RN

9

NC_PCIE_USBHC_D2RP

9

NC_PCIE_USBHC_R2DCN

9

NC_PCIE_USBHC_R2DCP

9

NC_SMC_FAN_PWM_SMC_SIL_LED_PWM

10

NC_SMC_FAN_TACH

10

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_DFR_1V8_DISP_INT
NC_DFR_1V8_DISP_RESET_L
NC_DFR_1V8_TOUCH_RESET_L

NC_DFR_DISP_TE
NC_DFR_PWR_EN
NC_HDMI_CEC_AOP_RX
NC_HDMI_CEC_AOP_TX
NC_HDMI_HPD_AOP
NC_MIPI_DFR_CLKN
NC_MIPI_DFR_CLKP
NC_MIPI_DFR_DATAN
NC_MIPI_DFR_DATAP
NC_PCIE_CLK100M_ENETN
NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_USBHCN
NC_PCIE_CLK100M_USBHCP
NC_PCIE_ENET_D2RN
NC_PCIE_ENET_D2RP
NC_PCIE_ENET_R2DCN
NC_PCIE_ENET_R2DCP
NC_PCIE_USBHC_D2RN
NC_PCIE_USBHC_D2RP
NC_PCIE_USBHC_R2DCN
NC_PCIE_USBHC_R2DCP
NC_SMC_FAN_PWM_SMC_SIL_LED_PWM
NC_SMC_FAN_TACH

USB2_ATC0_LS_P

58

USB2_ATC0_LS_N

58

USB2_ATC1_LS_P

58

USB2_ATC1_LS_N

58

USB_DBG_LS_P

58

USB_DBG_LS_N

58

CHGR_INT_L

10

USBC_ATC0_R2D_P<1>

51

USBC_ATC0_R2D_N<1>

51

USBC0_D2R_P<1>

51

USBC0_D2R_N<1>

51

USBC_ATC0_R2D_P<2>

51

USBC_ATC0_R2D_N<2>

51

USBC0_D2R_P<2>

51

USBC0_D2R_N<2>

51

USBC_ATC0_D2R_C_P<1>

51

USBC_ATC0_D2R_C_N<1>

51

USBC0_R2D_CR_P<1>

51

USBC0_R2D_CR_N<1>

51

USBC_ATC0_D2R_C_P<2>

51

USBC_ATC0_D2R_C_N<2>

51

USBC0_R2D_CR_P<2>

51

USBC0_R2D_CR_N<2>

51

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

USB2_ATC0_LS_P
USB2_ATC0_LS_N
USB2_ATC1_LS_P
USB2_ATC1_LS_N
USB_DBG_LS_P
USB_DBG_LS_N

CHGR_INT_L

USBC_ATC0_R2D_P<1>
USBC_ATC0_R2D_N<1>
USBC0_D2R_P<1>
USBC0_D2R_N<1>
USBC_ATC0_R2D_P<2>
USBC_ATC0_R2D_N<2>
USBC0_D2R_P<2>
USBC0_D2R_N<2>
USBC_ATC0_D2R_C_P<1>
USBC_ATC0_D2R_C_N<1>
USBC0_R2D_CR_P<1>
USBC0_R2D_CR_N<1>
USBC_ATC0_D2R_C_P<2>
USBC_ATC0_D2R_C_N<2>
USBC0_R2D_CR_P<2>
USBC0_R2D_CR_N<2>

59

59

59

59

54

54

24

51

51

57

57

51

51

57

57

51

51

57

57

51

51

57

57

61 60

NC_SPI_DISP_BKLT_MOSI

8

NC_SPI_DISP_BKLT_MISO

8

NC_SPI_DP2HDMI_HOLD_L

10

NC_NUB_SWD_TMS1

10

NC_I2C_SE_SCL

21

NC_I2C_SE_SDA

21

NC_DFR_TOUCH_INT_L

7

NC_UART_TCON_R2D

7

NC_ACDC_BURST_EN_L

10

NC_ACDC_ID

10

NC_CCG_SMC_I2C_INT_L

10

NC_BKLT_FAULT_INT_L

8

NC_DISP_BKLT_LSYNC

8

NC_ENET_CLKREQ_L

9

NC_ENET_RESET_L

9

NC_USBHC_RESET_L

9

NC_DFR_TOUCH_CLK32K_RESET_L

10

NC_AOP_FUNC0

10

NC_AOP_FUNC3

10

NC_AOP_FUNC2

10

NC_SPI_R1_CS_L

10

NC_BKLT_PWR_ON

10

NC_RF_BT_DED
NC_MIPI_FTCAM_DATA1P

8

NC_MIPI_FTCAM_DATA1N

8

NC_DMIC_CLK2_1V8_OUT_R_IC

72

NC_DMIC_CLK2_IN_IC

72

NC_DMIC_DATA2_1V8_IN_IC

72

NC_DMIC_DATA2_SEC_OUT_IC

72

NC_FTCAM_ENABLE_SEC_1V8_OUT_IC

72

NC_IRCAM_ENABLE_IN_IC

72

NC_IRCAM_ENABLE_SEC_1V8_OUT_IC

72

FTCAM_RESET_L

872

NC_SEP_IRCAM_DISABLE_IC_L

72

NC_FTCAM_ENABLE_IN

72

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_SPI_DISP_BKLT_MOSI
NC_SPI_DISP_BKLT_MISO

NC_SPI_DP2HDMI_HOLD_L
NC_NUB_SWD_TMS1

NC_I2C_SE_SCL
NC_I2C_SE_SDA

NC_DFR_TOUCH_INT_L

NC_UART_TCON_R2D
NC_ACDC_BURST_EN_L
NC_ACDC_ID
NC_CCG_SMC_I2C_INT_L
NC_BKLT_FAULT_INT_L
NC_DISP_BKLT_LSYNC
NC_ENET_CLKREQ_L
NC_ENET_RESET_L
NC_USBHC_RESET_L
NC_DFR_TOUCH_CLK32K_RESET_L
NC_AOP_FUNC0
NC_AOP_FUNC3
NC_AOP_FUNC2
NC_SPI_R1_CS_L

NC_BKLT_PWR_ON
NC_RF_BT_DED
NC_MIPI_FTCAM_DATA1P
NC_MIPI_FTCAM_DATA1N

NC_DMIC_CLK2_1V8_OUT_R_IC
NC_DMIC_CLK2_IN_IC
NC_DMIC_DATA2_1V8_IN_IC
NC_DMIC_DATA2_SEC_OUT_IC
NC_FTCAM_ENABLE_SEC_1V8_OUT_IC
NC_IRCAM_ENABLE_IN_IC
NC_IRCAM_ENABLE_SEC_1V8_OUT_IC
FTCAM_RESET_L
NC_SEP_IRCAM_DISABLE_IC_L

NC_FTCAM_ENABLE_IN

USBC_ATC1_R2D_P<1>

52

USBC_ATC1_R2D_N<1>

52

USBC1_D2R_P<1>

52

USBC1_D2R_N<1>

52

USBC_ATC1_R2D_P<2>

52

USBC_ATC1_R2D_N<2>

52

USBC1_D2R_P<2>

52

USBC1_D2R_N<2>

52

USBC_ATC1_D2R_C_P<1>

52

USBC_ATC1_D2R_C_N<1>

52

USBC1_R2D_CR_P<1>

52

USBC1_R2D_CR_N<1>

52

USBC_ATC1_D2R_C_P<2>

52

USBC_ATC1_D2R_C_N<2>

52

USBC1_R2D_CR_P<2>

52

USBC1_R2D_CR_N<2>

52

UART_TCON_D2R

7

IPD_SPI_INT_L

10

SOC_DOCK_CONNECT

IN OUT

SPKRAMP_RESET_L

73

TDM_SPKRAMP_L_BCLK

73

TDM_SPKRAMP_L_FSYNC

73

TDM_SPKRAMP_L_R2D

73

TDM_SPKRAMP_L_D2R

73

TDM_1V8_SPKRAMP_L_BCLK

74

TDM_1V8_SPKRAMP_L_FSYNC

74

TDM_1V8_SPKRAMP_L_R2D

74

TDM_1V8_SPKRAMP_L_D2R

74

TDM_SPKRAMP_R_BCLK

73

TDM_SPKRAMP_R_FSYNC

73

TDM_SPKRAMP_R_R2D

73

TDM_SPKRAMP_R_D2R

73

TDM_1V8_SPKRAMP_R_BCLK
TDM_1V8_SPKRAMP_R_FSYNC
TDM_1V8_SPKRAMP_R_R2D
TDM_1V8_SPKRAMP_R_D2R

TPT_WLAN_JTAG_TCK

60

TPT_WLAN_JTAG_TMS

60

TPT_WLAN_JTAG_TRSTN

60

61 60

61 60

TPT_WLAN_JTAG_TDI
TPT_WLAN_JTAG_TDO

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

USBC_ATC1_R2D_P<1>
USBC_ATC1_R2D_N<1>
USBC1_D2R_P<1>
USBC1_D2R_N<1>
USBC_ATC1_R2D_P<2>
USBC_ATC1_R2D_N<2>
USBC1_D2R_P<2>
USBC1_D2R_N<2>
USBC_ATC1_D2R_C_P<1>
USBC_ATC1_D2R_C_N<1>
USBC1_R2D_CR_P<1>
USBC1_R2D_CR_N<1>
USBC_ATC1_D2R_C_P<2>
USBC_ATC1_D2R_C_N<2>
USBC1_R2D_CR_P<2>
USBC1_R2D_CR_N<2>

UART_TCON_D2R
IPD_SPI_INT_L

SOC_DOCK_CONNECT

SPKRAMP_RESET_L

TDM_SPKRAMP_L_BCLK
TDM_SPKRAMP_L_FSYNC
TDM_SPKRAMP_L_R2D
TDM_SPKRAMP_L_D2R
TDM_1V8_SPKRAMP_L_BCLK
TDM_1V8_SPKRAMP_L_FSYNC
TDM_1V8_SPKRAMP_L_R2D
TDM_1V8_SPKRAMP_L_D2R
TDM_SPKRAMP_R_BCLK
TDM_SPKRAMP_R_FSYNC
TDM_SPKRAMP_R_R2D
TDM_SPKRAMP_R_D2R
TDM_1V8_SPKRAMP_R_BCLK
TDM_1V8_SPKRAMP_R_FSYNC
TDM_1V8_SPKRAMP_R_R2D
TDM_1V8_SPKRAMP_R_D2R

TPT_WLAN_JTAG_TCK
TPT_WLAN_JTAG_TMS
TPT_WLAN_JTAG_TRSTN
TPT_WLAN_JTAG_TDI
TPT_WLAN_JTAG_TDO

52

52

57

57

52

52

57

57

52

52

57

57

52

52

57

57

67

76

7

20

20

20

7

73

73

73

73

20

20

20

7

50 73

50 73

50 73

50 73

1054

B

NC_ENET_SYNC_1588

7

NC_SPI_DFR_CS_L

7

NC_SWD_UPC_SWDIO1

7

NC_ALS_INT_L

10

NC_SOC_TRIGGER2

7

NC_BT_GPIO_4

60

NC_SPMI_WLBT_CLK_1V8

60

NC_SPMI_WLBT_DAT_1V8

60 NO_TEST=1

TOUCHID_PWR_EN

7

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1

NC_ENET_SYNC_1588
NC_SPI_DFR_CS_L
NC_SWD_UPC_SWDIO1
NC_ALS_INT_L
NC_SOC_TRIGGER2

NC_BT_GPIO_4
NC_SPMI_WLBT_CLK_1V8
NC_SPMI_WLBT_DAT_1V8

TOUCHID_PWR_EN

TPT_P3V8AON_PU_RAIL

50

MAKE_BASE=TRUE

TPT_P3V8AON_PU_RAIL

25

Signal Aliases 1

NC_FPWM2

6

NC_SWD_TMS3

6

NC_SWD_TMS4

6

NC_I2S3_BCLK

7

NC_I2S3_D2R

7

NC_I2S3_LRCLK

7

NC_I2S3_MCLK

7

NC_I2S3_R2D

7

NC_SOC_GPIO01

7

IPD_SPI_EN

7

NC_SOC_GPIO09

7

NC_SOC_GPIO10

7

NC_SOC_GPIO15

7

NC_SOC_GPIO16

7

NC_SOC_I2S0_MCK

7

NC_SOC_I2S1_MCK

7

NC_SOC_I2S2_MCK

7

NC_SOC_SPI2_SSIN

7

NC_SPMI2_CLK

7

NC_SPMI2_DATA

7

NC_SSPI0_MOSI

7

NC_UART3_D2R

7

NC_UART3_D2R_CTS_L

7

NC_UART3_R2D

7

NC_UART3_R2D_RTS_L

7

NC_UART4_D2R

7

NC_UART4_D2R_CTS_L

7

NC_UART4_R2D

7

NC_UART4_R2D_RTS_L

7

NC_UART7_RXD

7

NC_UART7_TXD

7

NC_DISP_FSYNC

8

NC_DISP_SPMI_CLK

8

NC_DISP_SPMI_DATA

8

NC_DISP_TOUCH_BSYNC0

8

NC_DISP_TOUCH_BSYNC1

8

NC_DISP_TOUCH_EB

8

NC_DISPLAY_POL

8

NC_ISP_GPIO1

8

NC_ISP_GPIO2

8

NC_ISP_GPIO3

8

NC_ISP_I2C0_SCL

8

NC_ISP_I2C0_SDA

8

NC_ISP_I2C1_SCL

8

NC_ISP_I2C1_SDA

8

NC_ISP_I2C3_SCL

8

NC_ISP_I2C3_SDA

8

NC_ISP_SPMI0_CLK

8

NC_ISP_SPMI0_DATA

8

NC_ISP_SPMI1_CLK

8

NC_ISP_SPMI1_DATA

8

NC_LPDP_TX4N

8

NC_LPDP_TX4P

8

NC_LPDP_TX5N

8

NC_LPDP_TX5P

8

NC_LPDPRX_AUX0

8

NC_LPDPRX_AUX1

8

NC_LPDPRX_AUX2

8

NC_LPDPRX_AUX3

8 NO_TEST=1

NC_LPDPRX_AUX4

8

NC_LPDPRX_AUX5

8

NC_LPDPRX_AUX6

8

NC_LPDPRX_AUX7

8

NC_LPDPRX_AUX8

8

NC_LPDPRX_AUX9

8

NC_LPDPRX_AUX10

8

NC_LPDPRX_AUX11

8

NC_MIPI0C_CLKN

8

NC_MIPI0C_CLKP

8

NC_MIPI0C_DATAN0

8

NC_MIPI0C_DATAN1

8

NC_MIPI0C_DATAP0

8

NC_MIPI0C_DATAP1

8

NC_SENSOR0_CLK

8

NC_SENSOR1_CLK

8

NC_SENSOR2_CLK

8

NC_SENSOR3_CLK

8

NC_NAND0_PCIE_RESET1_L

9

NC_PAD_MTR_ANALOG_TEST_NEG

9

NC_PAD_MTR_ANALOG_TEST_POS

9

NC_PAD_MTR_VREF_NEG

9

NC_PAD_MTR_VREF_POS

9

NC_AON_SLEEP1_RESET_L

10

NC_AOP_FUNC1

10

NC_AOP_FUNC5

10

NC_AOP_FUNC10

10

NC_AOP_FUNC14

10

NC_AOP_SPMI0_SCLK

10

NC_AOP_SPMI0_SDATA

10

NC_AOP_UART2_D2R

10

NC_AOP_UART2_R2D

10

MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1 NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_FPWM2
NC_SWD_TMS3
NC_SWD_TMS4
NC_I2S3_BCLK
NC_I2S3_D2R
NC_I2S3_LRCLK
NC_I2S3_MCLK
NC_I2S3_R2D
NC_SOC_GPIO01
IPD_SPI_EN
NC_SOC_GPIO09
NC_SOC_GPIO10
NC_SOC_GPIO15
NC_SOC_GPIO16
NC_SOC_I2S0_MCK
NC_SOC_I2S1_MCK
NC_SOC_I2S2_MCK
NC_SOC_SPI2_SSIN
NC_SPMI2_CLK
NC_SPMI2_DATA
NC_SSPI0_MOSI
NC_UART3_D2R
NC_UART3_D2R_CTS_L
NC_UART3_R2D
NC_UART3_R2D_RTS_L
NC_UART4_D2R
NC_UART4_D2R_CTS_L
NC_UART4_R2D
NC_UART4_R2D_RTS_L
NC_UART7_RXD
NC_UART7_TXD
NC_DISP_FSYNC
NC_DISP_SPMI_CLK
NC_DISP_SPMI_DATA
NC_DISP_TOUCH_BSYNC0
NC_DISP_TOUCH_BSYNC1
NC_DISP_TOUCH_EB
NC_DISPLAY_POL
NC_ISP_GPIO1
NC_ISP_GPIO2
NC_ISP_GPIO3
NC_ISP_I2C0_SCL
NC_ISP_I2C0_SDA
NC_ISP_I2C1_SCL
NC_ISP_I2C1_SDA
NC_ISP_I2C3_SCL
NC_ISP_I2C3_SDA
NC_ISP_SPMI0_CLK
NC_ISP_SPMI0_DATA
NC_ISP_SPMI1_CLK
NC_ISP_SPMI1_DATA
NC_LPDP_TX4N
NC_LPDP_TX4P
NC_LPDP_TX5N
NC_LPDP_TX5P
NC_LPDPRX_AUX0
NC_LPDPRX_AUX1
NC_LPDPRX_AUX2
NC_LPDPRX_AUX3
NC_LPDPRX_AUX4
NC_LPDPRX_AUX5
NC_LPDPRX_AUX6
NC_LPDPRX_AUX7
NC_LPDPRX_AUX8
NC_LPDPRX_AUX9
NC_LPDPRX_AUX10
NC_LPDPRX_AUX11
NC_MIPI0C_CLKN
NC_MIPI0C_CLKP
NC_MIPI0C_DATAN0
NC_MIPI0C_DATAN1
NC_MIPI0C_DATAP0
NC_MIPI0C_DATAP1
NC_SENSOR0_CLK
NC_SENSOR1_CLK
NC_SENSOR2_CLK
NC_SENSOR3_CLK
NC_NAND0_PCIE_RESET1_L
NC_PAD_MTR_ANALOG_TEST_NEG
NC_PAD_MTR_ANALOG_TEST_POS
NC_PAD_MTR_VREF_NEG
NC_PAD_MTR_VREF_POS
NC_AON_SLEEP1_RESET_L
NC_AOP_FUNC1
NC_AOP_FUNC5
NC_AOP_FUNC10
NC_AOP_FUNC14
NC_AOP_SPMI0_SCLK
NC_AOP_SPMI0_SDATA
NC_AOP_UART2_D2R
NC_AOP_UART2_R2D

NC_CHGR_CBC_ON

23

NC_CHGR_EN_VR1

23

NC_CHGR_SMC_RST_L

23

NC_EUSB_LS1N

58

NC_EUSB_LS1P

58

NC_SE_GPIO0

21

NC_SMBUS_ATCRTMR0_SCL

51

NC_SMBUS_ATCRTMR0_SDA

51

76

NC_SMBUS_ATCRTMR1_SCL

52

NC_SMBUS_ATCRTMR1_SDA

52

NC_USB_LS1N

58

NC_USB_LS1P

58

NC_LPDPRX_RXN0

8

NC_LPDPRX_RXN1

8

NC_LPDPRX_RXN2

8

NC_LPDPRX_RXN3

8

NC_LPDPRX_RXN4

8

NC_LPDPRX_RXN5

8

NC_LPDPRX_RXN6

8

NC_LPDPRX_RXN7

8

NC_LPDPRX_RXN8

8

NC_LPDPRX_RXN9

8

NC_LPDPRX_RXN10

8

NC_LPDPRX_RXN11

8

NC_LPDPRX_RXP0

8

NC_LPDPRX_RXP1

8

NC_LPDPRX_RXP2

8

NC_LPDPRX_RXP3

8

NC_LPDPRX_RXP4

8

NC_LPDPRX_RXP5

8

NC_LPDPRX_RXP6

8

NC_LPDPRX_RXP7

8

NC_LPDPRX_RXP8

8

NC_LPDPRX_RXP9

8

NC_LPDPRX_RXP10

8

NC_LPDPRX_RXP11

8 NO_TEST=1

NC_NAND0_S5E0_VPP

62

NC_NAND0_S5E1_VPP

63

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1

NC_CHGR_CBC_ON
NC_CHGR_EN_VR1
NC_CHGR_SMC_RST_L
NC_EUSB_LS1N
NC_EUSB_LS1P
NC_SE_GPIO0
NC_SMBUS_ATCRTMR0_SCL
NC_SMBUS_ATCRTMR0_SDA
NC_SMBUS_ATCRTMR1_SCL
NC_SMBUS_ATCRTMR1_SDA

NC_USB_LS1N
NC_USB_LS1P
NC_LPDPRX_RXN0
NC_LPDPRX_RXN1
NC_LPDPRX_RXN2
NC_LPDPRX_RXN3
NC_LPDPRX_RXN4
NC_LPDPRX_RXN5
NC_LPDPRX_RXN6
NC_LPDPRX_RXN7
NC_LPDPRX_RXN8
NC_LPDPRX_RXN9
NC_LPDPRX_RXN10
NC_LPDPRX_RXN11
NC_LPDPRX_RXP0
NC_LPDPRX_RXP1
NC_LPDPRX_RXP2
NC_LPDPRX_RXP3
NC_LPDPRX_RXP4
NC_LPDPRX_RXP5
NC_LPDPRX_RXP6
NC_LPDPRX_RXP7
NC_LPDPRX_RXP8
NC_LPDPRX_RXP9
NC_LPDPRX_RXP10
NC_LPDPRX_RXP11

NC_NAND0_S5E0_VPP
NC_NAND0_S5E1_VPP

NC_PDM_CLK1

10

NC_PDM_CLK2

10

NC_PDM_CLK5

10

NC_PDM_CLK6

10

NC_PDM_DATA1

10

NC_PDM_DATA2

10

NC_SMC_GPIO1

10

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

Signal Aliases 2

NC_PDM_CLK1
NC_PDM_CLK2
NC_PDM_CLK5
NC_PDM_CLK6
NC_PDM_DATA1
NC_PDM_DATA2
NC_SMC_GPIO1

C Battery Sub-System Debug ConnectorB Debug LED ControlA Debug Push-Buttons

78

PP1V25_S2

DEVELOPMENT

SWV011

STO-060A16AE

SM

21

SWV012

STO-060A16AE

DEVELOPMENT
DEVELOPMENT

SM

21

SWV013

STO-060A16AE

DEVELOPMENT

SM

21

SWV001

STO-060A16AE

SM

21

DEVELOPMENT

RV020

1K

SOC_FORCE_DFU_R SOC_FORCE_DFU

PMU_RSLOC_RST_L

2 1

5%

1/20W

MF

201

34 35 77

PMU_ONOFF_L

34 35 50

6 34 54

Debug LED Latch

Press button once to engage.
Remove power to disengage.

PP3V8_AON_VDDMAIN

798283

P-CHN

SOT-963

NTUD3169CZ

QV080

DEVELOPMENT

DBGLED_LCH

DEVELOPMENT

RV083

100K

1/20W

201

5%
MF

Debug LED Enable

DEVELOPMENT

DEVELOPMENT

I2C_SMC_PWR_3V3_SDA

43 22

I2C_SMC_PWR_3V3_SCL

DEVELOPMENT

1

RV081

100K

5%

4

S

G

5

D

3

1/20W
MF
201

2

DBGLED_RTN

6

DEVELOPMENT

D

QV080

2

1

2

G

1

NTUD3169CZ

SOT-963

S

N-CHN

376S0820

DEVELOPMENT

RV082

0

21

5%

1/20W

MF

0201

NOSTUFF

RV080

1/20W

117S0201

5%
MF

0201

DBGLED_RETURN

82

DEVELOPMENT

SWV080

1

0

2

STO-060A16AE

43 22

AARDVARKANOID CONN

D Thermal Diode Test Points

51

IN

51

IN PP

52

IN

52

IN PP

ATCRTMR0_THERM_DP
ATCRTMR0_THERM_DN
ATCRTMR1_THERM_DP
ATCRTMR1_THERM_DN

RV001
RV002

0201

117S0201

117S0201

DEVELOPMENT

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

21

0

21

0

5%MF 1/20W

1/20WMF 5%0201

BATT_DBG_SDA
BATT_DBG_SCL

ATCRTMR0_THERM_DP

NO_TEST=1

ATCRTMR0_THERM_DN

NO_TEST=1

ATCRTMR1_THERM_DP

NO_TEST=1

ATCRTMR1_THERM_DN

NO_TEST=1

1

PP

1

1

PP

1

JV001

505070-1222

M-ST-SM

15

PPV000
PPV001
PPV002
PPV003

SM

P4MMSM
P4MMSM
P4MMSM
P4MM

1413

21
43
65
87
109
1211

16

E Debug LEDs

AON LED

IN

PP3V3_AON

79

G

1

LED_PWR_AON_QR

3

D

DEVELOPMENT

QV010

S

2

DBGLED_RETURN

SSM3K16CTAP

SOT883L

DEVELOPMENT

RV010

DEVELOPMENT

RV011

82

6.8K

1%

1/20W

MF

201

6.8K

1%

1/20W

MF

201

PP3V8_AON_VDDMAIN

798283

21

LED_PWR_AON_R

21

LED_PWR_AON_R2

DEVELOPMENT

DV010

K A

BLUE-22.5MCD-2MA

SM

DEVELOPMENT

DV011

K A

BLUE-22.5MCD-2MA

SM

PP3V8_AON_VDDMAIN

798283

DEVELOPMENT

DEVELOPMENT

RV014

10K

21

PMU RESET LED

3

D

6103472

PMU_RESET_L

IN

G

1

S

2

DBGLED_RETURN

DEVELOPMENT

QV014

SSM3K16CTAP

SOT883L

82

DEVELOPMENT

5%

1/20W

MF

201

RV015

10K

5%

1/20W

MF

201

LED_PMU_RST_QR

LED_PMU_RST_R

21

LED_PMU_RST_R2

DV014

K A

GREEN-90MCD-2MA

SM

DEVELOPMENT

DV015

K A

GREEN-90MCD-2MA

SM

DEVELOPMENT

RV030

LED_SOC_DFU_QR

6.8K

DFU LED

3

D

62054

SOC_DFU_STATUS

IN

G

1

S

2

DBGLED_RETURN

DEVELOPMENT

QV030

SSM3K16CTAP

SOT883L

82

1/20W

DEVELOPMENT

RV031

6.8K

1/20W

1%
MF

201

1%
MF

201

21

LED_SOC_DFU_R

21

LED_SOC_DFU_R2

PP3V8_AON_VDDMAIN

798283

DEVELOPMENT

DV030

K A

WHITE-57MCD-2MA

SM

DEVELOPMENT

DV031

K A

WHITE-57MCD-2MA

SM

DEVELOPMENT

RV012

LED_PWR_S2_QR

8.2K

S2 LED

3

D

IN

PP3V3_S2

79

G

1

S

2

DBGLED_RETURN

DEVELOPMENT

QV012

SSM3K16CTAP

SOT883L

82

1/20W

DEVELOPMENT

RV013

8.2K

1/20W

1%
MF

201

1%
MF

201

21

LED_PWR_S2_R

21

LED_PWR_S2_R2

DEVELOPMENT

DV012

K A

MAGENTA-45MCD-2MA

SM

DEVELOPMENT

DV013

K A

MAGENTA-45MCD-2MA

SM

SYS_ALIVE LED

LED_SYS_ALIVE_QR

3

D

343565

PMU_SYS_ALIVE

IN

G

1

S

2

DBGLED_RETURN

DEVELOPMENT

QV016

SSM3K16CTAP

SOT883L

82

DEVELOPMENT

RV016

6.8K

1/20W

DEVELOPMENT

1%
MF

201

21

RV017

6.8K

1/20W

1%
MF

201

21

LED_SYS_ALIVE_R

LED_SYS_ALIVE_R2

DEVELOPMENT

RV018

LED_ACTV_RDY_QR

ACTIVE_READY LED

3

D

63453

PMU_ACTIVE_READY

IN

G

1

S

2

DBGLED_RETURN

DEVELOPMENT

QV018

SSM3K16CTAP

SOT883L

82

6.8K

1/20W

DEVELOPMENT

RV019

6.8K

1/20W

1%
MF

201

1%
MF

201

21

LED_ACTV_RDY_R

21

LED_ACTV_RDY_R2

DEVELOPMENT

DV016

K A

ORANGE-11.5MCD-2MA

SM

DEVELOPMENT

DV017

K A

ORANGE-11.5MCD-2MA

SM

DEVELOPMENT

DV018

K A

WHITE-57MCD-2MA

SM

DEVELOPMENT

DV019

K A

WHITE-57MCD-2MA

SM

DEVELOPMENT

RV032

LED_SOC_SWDBG_QR

DBG LED

3

D

10

SOC_SW_DBG

IN

G

1

S

2

DBGLED_RETURN

DEVELOPMENT

QV032

SSM3K16CTAP

SOT883L

82

6.8K

1/20W

DEVELOPMENT

RV033

6.8K

1/20W

1%
MF

201

1%
MF

201

21

LED_SOC_SWDBG_R

21

LED_SOC_SWDBG_R2

DEVELOPMENT

DV032

K A

RED-11.5MCD-2MA

SM

DEVELOPMENT

DV033

K A

RED-11.5MCD-2MA

SM

BOM_COST_GROUP=DEBUG

DEBUG

PP3V8_AON_VDDMAIN

7982

CW100

NP0-C0G

12PF

5%

25V

0201

48

PP2V5_NAND0_DISCHARGE

64

25V

0201

25V

0201

1

CW102

12PF

2

1

NP0-C0G

CW10C

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

CW103

3.0PF

+/-0.1PF

NP0-C0G

CW10D

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

1

CW104

12PF

2

1

NP0-C0G

CW10E

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

CW105

3.0PF

+/-0.1PF

NP0-C0G

CW10F

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

1

CW106

12PF

2

1

NP0-C0G

CW116

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

CW107

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

CW108

12PF

2

NP0-C0G

5%

25V

0201

1

2

CW109

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

5%

25V

0201

5%

25V

0201

1

2

1

2

CW161

3.0PF

+/-0.1PF

NP0-C0G

CW171

3.0PF

+/-0.1PF

NP0-C0G

CW160

2

PP2V5_AWAKE_NAND

3178

12PF

NP0-C0G

CW170

12PF

NP0-C0G

25V

0201

25V

0201

1

2

1

CW172

12PF

2

NP0-C0G

5%

25V

0201

1

2

CW173

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

CW174

12PF

2

NP0-C0G

5%

25V

0201

1

2

CW175

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

CW176

12PF

2

NP0-C0G

5%

25V

0201

1

2

CW177

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

CW178

12PF

2

NP0-C0G

5%

25V

0201

1

2

CW179

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

2

1

2

CW101

3.0PF

+/-0.1PF

NP0-C0G

CW10B

3.0PF

+/-0.1PF

NP0-C0G

PPBUS_AON

79

PPVOUT_LCDBKLT

6779

5%

25V

0201

5%

25V

0201

5%

100V

C0G

0201

1

2

1

2

1

2

CW11A

12PF

NP0-C0G

CW136

12PF 3.0PF

NP0-C0G

CW18A

12PF

CW11B

CW137

CW18B

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

+/-0.1PF

25V

NP0-C0G

0201

3PF

+/-0.1PF

100V

C0G

0201

5%

25V

0201

5%

25V

0201

5%

100V

C0G

0201

1

CW11E

12PF

2

25V

0201

3PF

100V

C0G

0201

1

2

1

2

1

2

1

2

CW139

3.0PF

+/-0.1PF

NP0-C0G

CW18D

+/-0.1PF +/-0.1PF

NP0-C0G

CW13A

12PF

NP0-C0G

CW18E

1

CW11C

12PF

2

1

NP0-C0G

CW138

12PF

2

1

NP0-C0G

CW18C

12PF 12PF

2

5%

25V

0201

5%

25V

0201

5%

100V

C0G

0201

1

2

1

2

1

2

CW11F

3.0PF

+/-0.1PF

NP0-C0G

CW13B

3.0PF

+/-0.1PF

NP0-C0G

CW18F

25V

0201

25V

0201

3PF

100V

C0G

0201

1

CW122

12PF

2

1

NP0-C0G

CW13C

12PF

2

1

NP0-C0G

CW194

12PF

2

5%

25V

0201

5%

25V

0201

5%

100V

C0G

0201

1

CW123

3.0PF

2

1

2

1

2

NP0-C0G

CW13D

3.0PF

+/-0.1PF

NP0-C0G

CW195

+/-0.1PF

25V

0201

25V

0201

3PF

100V

C0G

0201

1

CW124

12PF

2

1

NP0-C0G

CW13E

12PF

2

1

NP0-C0G

CW196

12PF

2

5%+/-0.1PF

25V

0201

5%

25V

0201

5%

100V

C0G

0201

1

2

1

2

1

2

CW125

3.0PF

+/-0.1PF

NP0-C0G

CW13F

3.0PF

+/-0.1PF

NP0-C0G

CW197

+/-0.1PF

25V

0201

25V

0201

3PF

100V

C0G

0201

1

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

CW181

+/-0.1PF

NP0-C0G

CW191

3.0PF

+/-0.1PF

NP0-C0G

CW1A1

3.0PF

+/-0.1PF

NP0-C0G

CW180

2

PP1V25_AWAKE_NAND

78

1

CW117

12PF

2

1

NP0-C0G

5%

25V

0201

1

CW118

12PF

2

NP0-C0G

5%

25V

0201

1

CW119

12PF

2

NP0-C0G

5%

25V

0201

1

2

PP0V88_AWAKE_NAND

78

12PF

NP0-C0G

CW190

12PF

NP0-C0G

CW1A0

2

12PF

NP0-C0G

25V

0201

25V

0201

25V

0201

1

CW182

12PF3.0PF

2

1

NP0-C0G

CW192

12PF

2

1

NP0-C0G

CW1A2

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

CW183

3.0PF

+/-0.1PF

NP0-C0G

CW193

3.0PF

+/-0.1PF

NP0-C0G

CW1A3

3.0PF

+/-0.1PF

NP0-C0G

25V

25V

0201

25V

0201

1

CW184

12PF

2

1

2

1

NP0-C0G

CW1A4

12PF

2

NP0-C0G

5%

25V

02010201

5%

25V

0201

1

2

1

2

CW185

3.0PF

+/-0.1PF

NP0-C0G

CW1A5

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

1

CW186

12PF

2

1

NP0-C0G

CW1A6

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

CW187

3.0PF

+/-0.1PF

NP0-C0G

CW1A7

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

1

CW188

12PF

2

1

2

NP0-C0G

5%

25V

0201

1

2

CW189

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

2

PPVOUT_LCDBKLT_SW

69

CW198

CW110

NP0-C0G

PPVDD_DISP_S1

78

12PF

5%

100V

C0G

0201

12PF

5%

25V

0201

PPVIN_LCDBKLT_Q

69

PPVDD_SOC_S1

78

3PF

100V

C0G

0201

25V

0201

1

CW19A

12PF

2

5%

25V

0201

1

2

CW113

3.0PF

+/-0.1PF

NP0-C0G

1

CW112

12PF

2

NP0-C0G

5%

C0G

0201

25V

0201

1

2

1

CW19B

+/-0.1PF

CW114

12PF

2

NP0-C0G

3PF

100V

C0G

0201

5%

25V

0201

1

CW19C

12PF

2

1

2

CW115

3.0PF

+/-0.1PF

NP0-C0G

5%

100V100V

C0G

0201

25V

0201

1

2

1

2

CW19D

+/-0.1PF

PPVOUT_KBDBKLTPP1V2_S2_CIO

777978

3PF

100V

C0G

0201

1

2

CW19E

12PF

CW1AA

12PF

5%

100V

C0G

0201

5%

100V

C0G

0201

1

2

1

2

CW19F

+/-0.1PF

CW1AB

3PF

+/-0.1PF

100V

C0G

0201 0201

1

3PF

100V

2

C0G

0201 0201

1

2

CW1A8

12PF

CW1AC

12PF

5%

100V

C0G

0201

5%

100V

C0G

0201

1

2

1

2

CW1A9

3PF

+/-0.1PF

CW1AD

3PF

+/-0.1PF

100V

C0G

100V

C0G

1

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

25V

0201

25V

0201

1

CW1B8

12PF

2

1

2

NP0-C0G

1

2

1

2

CW1B7

3.0PF

+/-0.1PF

NP0-C0G

CW1C1

3.0PF

+/-0.1PF

NP0-C0G

5%

25V

0201

1

CW1BA

12PF

2

5%

25V

0201

1

2

CW162

12PF

NP0-C0G

NP0-C0G

CW163

3.0PF

+/-0.1PF

NP0-C0G

0201

25V

0201

25V

5%

1

2

1

2

CW1BB

+/-0.1PF

NP0-C0G

25V

0201

1

2

CW1BC

12PF3.0PF

NP0-C0G

CW164

12PF

NP0-C0G

0201

25V

0201

5%

25V

5%

1

2

1

2

CW1BD

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

CW1BE

12PF

2

NP0-C0G

5%

25V

0201

1

2

CW1BF

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

2

CW1B0

2

PP1V06_S2SW_DRAM

78

12PF

NP0-C0G

CW1B6

12PF

NP0-C0G

1

2

PP0V72_S2_VDD_LOW P3V8AON_VSW1 PP3V8AON_PH1

78 26 26

CW1C0

12PF

NP0-C0G

1

2

1

2

CW199

+/-0.1PF

CW111

3.0PF

+/-0.1PF

NP0-C0G

CW130

12PF

5%

25V

NP0-C0G

0201 0201

PPVDD_ECPU_AWAKE

7883

CW134

12PF 3.0PF

5%

25V

NP0-C0G

0201

PP1V25_AWAKE_IO

78

CW140

12PF 3.0PF

5%

25V

NP0-C0G

0201

PP0V805_S1_VDD_FIXED

78

1

2

1

2

1

2

CW131

3.0PF

+/-0.1PF

NP0-C0G

CW135

+/-0.1PF

NP0-C0G

CW141

+/-0.1PF

NP0-C0G

25V

25V

0201

25V

0201

1

CW132

12PF

2

1

2

1

NP0-C0G

78

CW142

12PF

2

NP0-C0G

1

5%

25V

2

0201

PPVDD_GPU_AWAKE

CW126

12PF

5%

25V

NP0-C0G

0201

5%

25V

0201

1

2

CW143

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

CW133

12PF

NP0-C0G

1

2

1

2

CW127

3.0PF

+/-0.1PF

NP0-C0G

79

3738

1

5%

25V

2

0201

1

25V

2

0201

PP5V_S2

P5VS2_SW

PP1V2_AWAKE_PLL

78

5%

25V

0201

1

2

CW1C3

12PF

NP0-C0G

CW120

12PF

5%

25V

NP0-C0G

0201

CW1C4

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

PPBUS_AON_L_SPKRAMP

79

5%

25V

0201

1

2

CW14C

3.0PF

+/-0.1PF

NP0-C0G

26

26

1

CW14B

12PF

25V

2

0201

1

25V

2

0201 0201

1

25V

2

NP0-C0G

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

CW147

12PF

NP0-C0G

25V

0201

5%

25V

0201

1

2

P3V8AON_SW2

2526

CW166

12PF

NP0-C0G

1

2

CW1C6

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

2

P3V8AON_SW3

2526

CW16E

12PF

NP0-C0G

PP5V_S2_KBDLED

79

1

2

1

CW121

3.0PF

+/-0.1PF

NP0-C0G

CW1C5

12PF

2

NP0-C0G

CW148

3.0PF 12PF

+/-0.1PF

NP0-C0G

CW167

3.0PF 12PF

+/-0.1PF

NP0-C0G

CW16F

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

25V

0201

1

2

1

2

1

CW149

NP0-C0G

CW168

NP0-C0G

CW17A

12PF3.0PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

1

2

CW14A

3.0PF

+/-0.1PF

NP0-C0G

CW169

3.0PF

+/-0.1PF

NP0-C0G

CW17B

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

2

CW14D

NP0-C0G

PP3V8AON_PH2

PP3V8AON_PH3

CW17C

NP0-C0G

12PF

12PF

5%

25V

0201

5%

25V

02010201

1

2

25V

25V

1

2

1

2

CW16B

3.0PF 12PF

+/-0.1PF

NP0-C0G

1

2

CW17D

+/-0.1PF

NP0-C0G

CW16C

NP0-C0G

CW17E

12PF3.0PF

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

CW145

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

2

CW146

PP0V6_S1_VDDQL

78

CW150

PPVDD_ECPU_AWAKE

7883

CW156

12PF

5%

25V

NP0-C0G

0201

12PF

5%

25V

NP0-C0G

0201

12PF

5%

25V

NP0-C0G

0201

1

2

25V

0201

1

CW152

12PF

2

NP0-C0G

1

2

1

2

CW151

3.0PF

+/-0.1PF

NP0-C0G

5%

25V

0201

1

2

CW153

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

2

CW154

12PF

5%

25V

NP0-C0G

0201

1

2

CW1C7

NP0-C0G

CW155

3.0PF 12PF

+/-0.1PF

NP0-C0G

5%

25V

0201

25V

0201

1

2

1

2

CW1C8

3.0PF12PF

+/-0.1PF

25V

NP0-C0G

0201

CW15A

25V

NP0-C0G

0201

2

5%

1

2

CW1C9

12PF

NP0-C0G

CW15B

3.0PF

+/-0.1PF

NP0-C0G

5%

25V

0201

0201

25V

1

2

1

2

CW1CA

3.0PF

+/-0.1PF

NP0-C0G

CW15C

NP0-C0G

25V

0201

12PF

5%

25V

0201

1

CW1CB

12PF

2

25V

0201

1

2

1

2

CW15D

3.0PF

+/-0.1PF

NP0-C0G

NP0-C0G

CW15E

12PF

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

CW1CC

3.0PF

+/-0.1PF

NP0-C0G

CW15F

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

1

2

1

2

Desense

BOM_COST_GROUP=DESENSE

SCSET RULES

DIELECTRIC BASED SPACING RULES

RULE DEFINITION

A_DIELECTRIC_(N) X

shor test dist ance is us ed un less 'L'i s def ined

A_DIELECTRIC_(N) XD XV,XVL,X

Calc ulate s di elect ric d istan ce f rom H ybrid Tabl e an d
stac kup, shor test dista nce i s us ed un less 'L' d efin ed

A_DIELECTRIC_(N) XIN_(N)XOUT

Calc ulate s di elect ric d istan ce f rom s tacku p,
shor test dist ance is us ed un less 'L' is de fined

LIST OF VALUES

EXAM PLE: 1,3- 5,7L, 8L-10 L

2-10Calc ulate s die lectr ic di stan ce fr om st ackup ,

EXAM PLE: 2,1D L,3D- 5D,7V ,8VL- 10VL

PLEASE USE HYBRID TABLE

EXAM PLE: 2_4, 3L_5L

17.2 RULES

PHYSICAL CONSTRAINT SET, CLASS ASSIGNMENT PHYSICAL CONSTRAINT SET, NET ASSIGNMENT

CLASS DEFINITIONS

DOMAIN

E,P,S

CONSTRAINT SETCLASS NAME

COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR*

*SMB*SCL*,*SMB*SDA*,*I2C*SCL*,*I2C*SDA*,*I2C*INT*A_45_OHM_SEP YI2C

A_45_OHM_SEP Y*SPI*MISO*,*SPI*MOSI*,*SPI*CLK*,*SPI*CS*SPI

SPMI Y*SPMI*P A_45_OHM_SE

SWD SWD_NAND*,SWD_NUB* YP A_45_OHM_SE

*JTAG*SEL,*JTAG*TCK,*JTAG*TDI,*JTAG*TDO,*JTAG*TMSP YA_45_OHM_SEJTAG

SOC_XTAL24M*,SOC_24M_O_R,NAND0_CLK24M*P A_45_OHM_SE YCLOCK_24M

P YPMU_CLK32K*CLOCK_32K A_45_OHM_SE

TDM_LEFT P A_45_OHM_SE TDM_SPKRAMP_L* Y

TDM_SPKRAMP_R*TDM_RIGHT YP A_45_OHM_SE

TDM_CODEC A_45_OHM_SE TDM_CODEC* YP

A_45_OHM_SESPKR_ICC SPKRAMP_ICC,SPKRAMP_*_ICC_R YP

PUART A_45_OHM_SE YUART_*

RESETS *RST*,*RESET*,*PERST*A_45_OHM_SEP Y

A_45_OHM_SE YP SOC_WDOGWDOG
A_45_OHM_SESOCHOT SOC_SOCHOT_LP Y

A_45_OHM_SEFAULT *FAULT* YP

P YA_85_OHM_DIFFCIO_D2R DP:DP_USBC*_D2R*

DP:DP_USBC*_R2D*P YA_85_OHM_DIFFCIO_R2D

P YA_85_OHM_DIFFPCIE_NAND_D2R DP:DP_PCIE_NAND*_D2R*

DP:DP_PCIE_NAND*_R2D*P YA_85_OHM_DIFFPCIE_NAND_R2D

P DP:DP_PCIE_WLBT*_R2D* YA_85_OHM_DIFFPCIE_WLBT_D2R

DP:DP_PCIE_WLBT*_D2R*P YA_85_OHM_DIFFPCIE_WLBT_R2D

P YLPDP DP:DP_LPDP_INT_DATA*A_85_OHM_DIFF

P *CLKREQ* YA_45_OHM_SEPCIE_CLKREQ

A_85_OHM_DIFF YPMIPI_DATA DP:DP_MIPI_FTCAM_DATA*,DP_MIPI_DATA*

P YA_85_OHM_DIFF DP:DP_EUSB*EUSB

GROUND P YDEFAULT GND

POWER PP* YP POWER

CLEA R

OVER RIDE

Y/NDP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:)

YA_45_OHM_SEP *PMU_ONOFF*POWER_BUTTON

YDMIC_PDM A_45_OHM_SEP PDM_DMIC_DATA*,DMIC_DATA*,PDM_DMIC_CLK*,DMIC_CLK*

YDP:DP_PCIE_CLK100M*PCIE_CLK P A_85_OHM_DIFF

YPMIPI_CLK DP:DP_MIPI_FTCAM_CLK*,DP_MIPI_CLOCK*A_85_OHM_DIFF

DOMA IN

(E, P,S)

CONSTRAINT SET

NET RULE ASSIGNMENT

COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* )

17.2 PHYSICAL CSETS

SPACING CONSTRAINT SET, CLASS ASSIGNMENT

CLASS DEFINITIONS

DOMAIN

E,P,S

CONSTRAINT SETCLASS NAME

COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR*

CLOCK_24M
CLOCK_32K

CIO_D2R
CIO_R2D

A_DIELECTRIC_9X =S Y

A_DIELECTRIC_9X Y=S
PCIE_NAND_D2R
PCIE_NAND_R2D
PCIE_WLBT_D2R
PCIE_WLBT_R2D

LPDP

MIPI_CLK

MIPI_DATA

GROUND

POWER YDEFAULT =

S

S

CLEA R

OVER RIDE

Y/NDP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:)

= YS A_DIELECTRIC_3X
= YS A_DIELECTRIC_3X

=S YA_DIELECTRIC_9X
=S YA_DIELECTRIC_9X

YS =A_DIELECTRIC_7X

=S YA_DIELECTRIC_7X

YS =A_DIELECTRIC_6XPCIE_CLK
YS =A_DIELECTRIC_6X

= YS A_DIELECTRIC_5X
= YS A_DIELECTRIC_5X

YS =EUSB A_DIELECTRIC_5X
YDEFAULTS =

RF_ANT* YRFRF

17.2 SPACING CSETS, ISO

SPACING CONSTRAINT SET ASSIGNMENT, CLASS-CLASS

CLASS TO CLASS SPACING

CLASS NAME CONSTRAINT SET

CIO_R2D GROUND DEFAULT_WITH_4X_TO_SHAPE

LPDP GROUND DEFAULT_WITH_4X_TO_SHAPE

CIO_D2R A_DIELECTRIC_4XPCIE_NAND_D2R

CIO_D2R MIPI_CLK A_DIELECTRIC_4X
CIO_D2R MIPI_DATA A_DIELECTRIC_4X
CIO_D2R CIO_R2D A_DIELECTRIC_7X

PCIE_WLBT_D2R PCIE_WLBT_R2D A_DIELECTRIC_4X
PCIE_WLBT_D2R MIPI_DATA A_DIELECTRIC_4X
PCIE_WLBT_D2R MIPI_CLK A_DIELECTRIC_4X

MIPI_DATA A_DIELECTRIC_2XMIPI_CLK

CIO_R2D LPDP A_DIELECTRIC_4X

PCIE_NAND_R2D A_DIELECTRIC_4XPCIE_NAND_R2D

PCIE_NAND_R2D A_DIELECTRIC_4XPCIE_CLK
PCIE_NAND_R2D A_DIELECTRIC_4XLPDP
PCIE_WLBT_R2D A_DIELECTRIC_4XPCIE_CLK
PCIE_WLBT_R2D A_DIELECTRIC_4XLPDP

PCIE_CLK A_DIELECTRIC_4XPCIE_CLK
PCIE_CLK A_DIELECTRIC_4XLPDP

CLASS NAME

GROUND DEFAULT_WITH_4X_TO_SHAPECIO_D2R

DEFAULT_WITH_4X_TO_SHAPEGROUNDPCIE_CLK
DEFAULT_WITH_4X_TO_SHAPEPCIE_NAND_D2R GROUND
DEFAULT_WITH_4X_TO_SHAPEPCIE_NAND_R2D GROUND
DEFAULT_WITH_4X_TO_SHAPEPCIE_WLBT_D2R GROUND
DEFAULT_WITH_4X_TO_SHAPEPCIE_WLBT_R2D GROUND
DEFAULT_WITH_4X_TO_SHAPEGROUNDMIPI_DATA

DEFAULT_WITH_4X_TO_SHAPEMIPI_CLK GROUND
POWER DEFAULT_WITH_4X_TO_SHAPECIO_D2R
POWERCIO_R2D DEFAULT_WITH_4X_TO_SHAPE

DEFAULT_WITH_4X_TO_SHAPEPOWERLPDP
POWERPCIE_CLK DEFAULT_WITH_4X_TO_SHAPE

DEFAULT_WITH_4X_TO_SHAPEPOWERPCIE_NAND_D2R

DEFAULT_WITH_4X_TO_SHAPEPOWERPCIE_NAND_R2D

DEFAULT_WITH_4X_TO_SHAPEPOWERPCIE_WLBT_D2R

DEFAULT_WITH_4X_TO_SHAPEPOWERPCIE_WLBT_R2D
POWERMIPI_DATA DEFAULT_WITH_4X_TO_SHAPE

DEFAULT_WITH_4X_TO_SHAPEPOWERMIPI_CLK

A_DIELECTRIC_4XCIO_D2R CIO_D2R

A_DIELECTRIC_4XPCIE_WLBT_D2RCIO_D2R

A_DIELECTRIC_4XPCIE_NAND_D2RPCIE_NAND_D2R
A_DIELECTRIC_4XPCIE_WLBT_D2RPCIE_NAND_D2R

MIPI_DATA A_DIELECTRIC_4XPCIE_NAND_D2R

MIPI_CLK A_DIELECTRIC_4XPCIE_NAND_D2R

A_DIELECTRIC_7XPCIE_NAND_D2R PCIE_NAND_R2D

CIO_R2DCIO_R2D A_DIELECTRIC_4X
PCIE_NAND_R2DCIO_R2D A_DIELECTRIC_4X
PCIE_WLBT_R2D A_DIELECTRIC_4XCIO_R2D

PCIE_CLKCIO_R2D A_DIELECTRIC_4X

A_DIELECTRIC_4XPCIE_WLBT_R2DPCIE_NAND_R2D

A_DIELECTRIC_3XLPDPLPDP

17.2 SPACING CSETS, CLASS-CLASS

CPU NAND Landing 0

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

A1 BEST

TABLE_ALT _ITEM

998-21412 ALL998-21413 SCK

998-21415 998-21414 ALL SCK

CPU:SOC_A1_HYNIX_8GB_BEST

SOC,TGA A1+8G,1Y,8C,DEV,CX,M,ATK,MCM2502

CPU:SOC_A1_MICRON_8GB_BEST

U0600 CRITICAL1998-21414

TABLE_ALT _ITEM

998-21416 CRITICALU0600SOC,TGA A1+16G,1Y,8C,DEV,DX,H,ATK,MC25021

TABLE_ALT _ITEM

998-21417 998-21416 SCK

1998-21418 CRITICAL

998-21420 SCKALL998-21418

CPU:SOC_A1_HYNIX_16GB_BEST

SOC,TGA A1+16G,1X,8C,DEV,DX,M,ATK,MC2502 CPU:SOC_A1_MICRON_16GB_BEST

CPU:SOC_A1_MICRON_16GB_BEST

ALL

U0600

TABLE_ALT _ITEM

A1 GOOD

998-21421 SOC,TGA A1+8G,1Y,7C,DEV,CX,H,ATK,MCM25021 CRITICALU0600

TABLE_ALT _ITEM

998-21421998-21422 SCKALL
998-21421998-21412 ALL
998-21421 SCK998-21413 ALL

CPU:SOC_A1_HYNIX_8GB_GOOD

CPU:SOC_A1_HYNIX_8GB_GOOD

CPU:SOC_A1_HYNIX_8GB_GOOD

TABLE_ALT _ITEM

ACK

TABLE_ALT _ITEM

CRITICALU0600PCBA,KANHA,X17111939-08813

NAND,3DV4,128GBT,XXX,S5E,256G,T,SLGA110

CRITICAL998-21412 U0600SOC,TGA A1+8G,1Y,8C,DEV,CX,H,ATK,MCM25021

CPU:SOC_A1_HYNIX_8GB_BEST

CPU:SOC_A1_MICRON_8GB_BEST

CPU:SOC_A1_HYNIX_16GB_BEST

1 UN000 CRITICAL335S00474 NAND_L0:ITLC_1P0T_SD

NAND,3DV4,128GBT,XXX,S5E,256G,SD,SLGA110

UN0001335S00437 NAND,3DV5,128GB,S5E,512G,H,SLGA110 NAND_L0:ITLC_256G_HY
UN0001 CRITICAL335S00489 NAND,3DV4,160GBT,XXX,S5E,256G,SD,SLGA110 NAND_L0:ITLC_256G_SD

NAND,3DV4,160GBT,XXX,S5E,256G,K,SLGA110

NAND,3DV5,320GB,S5E,512G,H,SLGA110

NAND,3DV4,288GBT,XXX,S5E,256G,K,SLGA110

NAND,3DV4,512GBT,XXX,S5E,256G,SD,SLGA110

CRITICALUN0001998-18368 IC,NAND,S5E MCP ROUTING STUDY,LGA110 NAND_L0:S5E_STUDYCPU:INTERPOSER
CRITICALUN0001335S00462 NAND_L0:ITLC_128G_TO
CRITICALUN0001335S00470 NAND_L0:ITLC_128G_SD
CRITICAL

CRITICALUN0001335S00480 NAND_L0:ITLC_256G_TO
CRITICALUN0001335S00482 NAND_L0:ITLC_512G_HY
CRITICALUN0001335S00481 NAND_L0:ITLC_512G_TO

UN0001 CRITICAL335S00466 NAND,3DV4,512GBT,XXX,S5E,256G,T,SLGA110 NAND_L0:ITLC_1P0T_TO
UN0001 CRITICAL335S00468 NAND,3DV4,1TBT,XXX,S5E,512G,T,SLGA110 NAND_L0:ITLC_2P0T_TO

NAND,3DV5,1024GBT,S5E,512G,H,SLGA110 CRITICALUN0001335S00458 NAND_L0:ITLC_2P0T_HY

CPU:SOC_A1_HYNIX_8GB_GOOD

CRITICALUN000PCBA,BANDIPUR,X17111939-08815 NAND_L0:INTERPOSER

998-21423 SCKALL998-21424

998-21415 998-21423 ALL SCK

998-21427 998-21426 SCK

998-21426998-21416 ALL
998-21426 SCKALL998-21417

998-21428 ALL SCK998-21429
998-21428998-21418 ALL
998-21428

CPU:SOC_A1_MICRON_8GB_GOOD

CPU:SOC_A1_MICRON_8GB_GOOD

CPU:SOC_A1_MICRON_8GB_GOOD

CPU:SOC_A1_HYNIX_16GB_GOOD

CPU:SOC_A1_HYNIX_16GB_GOOD

CPU:SOC_A1_HYNIX_16GB_GOOD

SOC,TGA A1+16G,1X,7C,DEV,DX,M,ATK,MC25021 U0600 CRITICAL998-21428

CPU:SOC_A1_MICRON_16GB_GOOD

CPU:SOC_A1_MICRON_16GB_GOOD

CPU:SOC_A1_MICRON_16GB_GOOD

ALL998-21414 998-21423

ALL

ALL998-21420

B0 BEST

ACK

ACK

ACK
SCK

U0600 CRITICAL1998-21423 SOC,TGA A1+8G,1Y,7C,DEV,CX,M,ATK,MCM2502

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

U0600SOC,TGA A1+16G,1Y,7C,DEV,DX,H,ATK,MC2502998-21426 1 CRITICAL

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

CPU:SOC_A1_MICRON_8GB_GOOD

CPU:SOC_A1_HYNIX_16GB_GOOD

CPU:SOC_A1_MICRON_16GB_GOOD

NAND Landing 1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALUN1001998-18368 IC,NAND,S5E MCP ROUTING STUDY,LGA110 NAND_L1:S5E_STUDY
CRITICALUN1001335S00437 NAND,3DV5,128GB,S5E,512G,H,SLGA110 NAND_L1:ITLC_256G_HY
CRITICALUN1001335S00470 NAND,3DV4,128GBT,XXX,S5E,256G,SD,SLGA110 NAND_L1:ITLC_256G_SD

UN1001335S00462 NAND,3DV4,128GBT,XXX,S5E,256G,T,SLGA110 NAND_L1:ITLC_256G_TOCRITICAL

CRITICALUN1001335S00438 NAND,3DV5,256GB,S5E,512G,H,SLGA110 NAND_L1:ITLC_512G_HY
CRITICALUN1001335S00464 NAND_L1:ITLC_512G_TONAND,3DV4,256GBT,XXX,S5E,256G,T,SLGA110
CRITICALUN1001335S00474 NAND_L1:ITLC_1P0T_SDNAND,3DV4,512GBT,XXX,S5E,256G,SD,SLGA110

998-22388

1 U0600 CRITICAL

998-22387 998-22388

998-22386

1 CRITICALU0600

998-22385 998-22386

998-22392 SOC,TGA B0+16G,1Y,8C,LP,DEV,DX,H,A,M2502

1 U0600 CRITICAL

998-22391 998-22392

SOC,TGA B0+8G,1Y,8C,LP,DEV,CX,H,A,M2502

CPU:SOC_HYNIX_8GB_BEST

SOC,TGA B0+8G,1Y,8C,LP,DEV,CX,M,A,M2502

CPU:SOC_MICRON_8GB_BEST

CPU:SOC_HYNIX_16GB_BEST

ALL

998-22390 SOC,TGA B0+16G,1X,8C,LP,DEV,DX,M,A,M2502

998-22389 998-22390

CPU:SOC_MICRON_16GB_BEST

ALL SCK

B0 GOOD

998-22404

998-22403
998-22388
998-22387

998-22404
998-22404
998-22404

998-22402 SOC,TGA B0+8G,1Y,7C,LP,DEV,CX,M,A,M2502

998-22401
998-22386
998-22385

998-22402
998-22402

998-22409 SOC,TGA B0+16G,1Y,7C,LP,DEV,DX,H,A,M2502

998-22408
998-22392
998-22391

998-22409
998-22409
998-22409

SOC,TGA B0+8G,1Y,7C,LP,DEV,CX,H,A,M2502

CPU:SOC_HYNIX_8GB_GOOD

ALL SCK
ALLCPU:SOC_HYNIX_8GB_GOOD
ALL SCKCPU:SOC_HYNIX_8GB_GOOD

CPU:SOC_MICRON_8GB_GOOD ALL SCK
CPU:SOC_MICRON_8GB_GOOD ALL
CPU:SOC_MICRON_8GB_GOOD998-22402

ALLCPU:SOC_HYNIX_16GB_GOOD
ALL SCKCPU:SOC_HYNIX_16GB_GOOD

SCK

SCKALL

SCKALL

ACK

ACK
SCKALL

SCKALLCPU:SOC_HYNIX_16GB_GOOD
ACK

CPU:SOC_HYNIX_8GB_BEST

TABLE_ALT _ITEM

CPU:SOC_MICRON_8GB_BEST

TABLE_ALT _ITEM

CPU:SOC_HYNIX_16GB_BEST

TABLE_ALT _ITEM

CRITICALU06001

TABLE_ALT _ITEM

CPU:SOC_MICRON_16GB_BEST

U0600 CRITICAL1 CPU:SOC_HYNIX_8GB_GOOD

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

CPU:SOC_MICRON_8GB_GOOD1 CRITICALU0600

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

CRITICAL1 CPU:SOC_HYNIX_16GB_GOODU0600

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

939-08815 1 PCBA,BANDIPUR,X1711 NAND_L1:INTERPOSERUN100 CRITICAL

SPMU

998-20066 1 IC,PMU,SPMU,A0,OTP-JPC,WLCSP196 U7700 SPMU_IC:DEVCRITICAL

MPMU

998-22614

IC,PMU,SIMETRA,A1,OTP-JPE,WLCSP196998-22526

IC,PMU,SERA,B0,OTP-JPF,WLCSP440

UN1001335S00466 NAND_L1:ITLC_1P0T_TOCRITICALNAND,3DV4,512GBT,XXX,S5E,256G,T,SLGA110

CRITICALUN1001335S00468 NAND_L1:ITLC_2P0T_TONAND,3DV4,1TBT,XXX,S5E,512G,T,SLGA110

UN1001335S00458 NAND_L1:ITLC_2P0T_HYNAND,3DV5,1024GBT,S5E,512G,H,SLGA110 CRITICAL

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALU77001

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL MPMU_IC:DEVU8100IC,PMU,MPMU,A0,OTP-JPE,WLCSP4401998-20064

SPMU_IC:A1

MPMU_IC:B01 U8100 CRITICAL

998-22407 SOC,TGA B0+16G,1X,7C,LP,DEV,DX,M,A,M2502

998-22406
998-22390
998-22389

998-22407
998-22407
998-22407

CPU:SOC_MICRON_16GB_GOOD SCKALL

ALLCPU:SOC_MICRON_16GB_GOOD

CPU:SOC_MICRON_16GB_GOODCRITICALU06001

TABLE_ALT _ITEM

TABLE_ALT _ITEM

ACK

TABLE_ALT _ITEM

SCKCPU:SOC_MICRON_16GB_GOOD ALL

BOM OPTION TABLES

NAND BOM GROUPS

BOM GROUP BOM OPTIONS

NANDCFG:ITLC_S5E_2P0T_TO

NANDCFG:ITLC_S5E_2P0T_HY

NANDCFG:INTERPOSER

NANDCFG:NONE

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_128G_TONANDCFG:ITLC_S5E_128G_TO

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_128G_SDNANDCFG:ITLC_S5E_128G_SD

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_256G_HY,NAND_L1:ITLC_256G_HY,PARTS_SSDNAND1NANDCFG:ITLC_S5E_256G_HY

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_256G_SD,NAND_L1:ITLC_256G_SD,PARTS_SSDNAND1NANDCFG:ITLC_S5E_256G_SD

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_256G_TO,NAND_L1:ITLC_256G_TO,PARTS_SSDNAND1NANDCFG:ITLC_S5E_256G_TO

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_512G_HY,NAND_L1:ITLC_512G_HY,PARTS_SSDNAND1NANDCFG:ITLC_S5E_512G_HY

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_512G_TO,NAND_L1:ITLC_512G_TO,PARTS_SSDNAND1NANDCFG:ITLC_S5E_512G_TO

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_1P0T_SD,NAND_L1:ITLC_1P0T_SD,PARTS_SSDNAND1NANDCFG:ITLC_S5E_1P0T_SD

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_1P0T_TO,NAND_L1:ITLC_1P0T_TO,PARTS_SSDNAND1NANDCFG:ITLC_S5E_1P0T_TO

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_2P0T_TO,NAND_L1:ITLC_2P0T_TO,PARTS_SSDNAND1

TABLE_BOM GROUP_ITEM

NAND_L0:ITLC_2P0T_HY,NAND_L1:ITLC_2P0T_HY,PARTS_SSDNAND1

TABLE_BOM GROUP_ITEM

NAND_L0:INTERPOSER,NAND_L1:INTERPOSER,PARTS_SSDNAND1

TABLE_BOM GROUP_ITEM

NAND_L0:OFF,NAND_L1:OFF,PARTS_SSDNAND1

BOM GROUPS

Alternates

PART NUMBER

353S01346

138S0738

376S1053

353S01320 ALL

ALL rdar://problem/59471401138S1101

138S0811

376S0604

ALL138S0846

ALL

152S00359 152S00253 ALL

740S0159

371S00077

376S1106 ALL

376S0678 rdar://problem/59442581

ALL740S00041

ALL371S00180

107S00033 107S00034 ALL

138S00087

152S00812 rdar://problem/59465659

138S1086 ALL

152S1701

ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

rdar://problem/57736570

rdar://problem/59474499

rdar://problem/59475163

rdar://problem/57204466

rdar://problem/59438907

rdar://problem/59475330

rdar://problem/59471007

rdar://problem/59439865

371S00079 ALL371S00217 rdar://problem/57739774

376S0948

128S00031

128S00026

128S00087

128S0445 128S0436

128S0364

376S00076 ALL rdar://problem/59134310

ALL128S00011

rdar://problem/59071370

ALL rdar://problem/59071370128S00011

rdar://problem/59071370

rdar://problem/59071568

rdar://problem/59071705ALL128S0264

128S00067

ALL128S00011

ALL

ALL rdar://problem/59072397128S00094

128S00038 ALL rdar://problem/59075402128S00039

128S00038 ALL rdar://problem/59075402128S0302

ALL152S00198 rdar://problem/59075547152S00680

152S00198 ALL rdar://problem/59075547152S00383

ALL rdar://problem/59075783152S00708 152S00265

rdar://problem/59076041152S01248 ALL152S00367

376S00204 ALL376S00203 rdar://problem/59076791

ALL376S00203 rdar://problem/59076791376S00226

ALL376S00227 376S00203 rdar://problem/59076791

rdar://problem/59077240ALL376S00228 376S1179

376S00007 ALL376S1179 rdar://problem/59077240

rdar://problem/59077463ALL376S00303 376S00012

ALL

138S00332

138S00073

rdar://problem/59077684376S1147 376S00281

rdar://problem/59078523ALL107S00071 107S00053

rdar://problem/59081345ALL107S00087107S00029

rdar://problem/59112527ALL138S00328

rdar://problem/59118124138S00047 ALL

rdar://problem/59118514138S0853138S0863 ALL

ALL rdar://problem/59119189138S00077 138S00035

rdar://problem/59119189138S00035138S00093 ALL

138S00116 rdar://problem/59119528138S00071 ALL

rdar://problem/59119528138S00117 138S00071 ALL

rdar://problem/59123589138S00107138S00229 ALL

rdar://problem/59124126138S0801138S00022 ALL

152S00398 ALL152S00204 rdar://problem/59129606

rdar://problem/59129928ALL152S00885152S00963

rdar://problem/59130255152S00343 ALL152S00839

152S01317 ALL rdar://problem/59130415152S01268

152S00476 ALL152S00997 rdar://problem/59130875

152S01090 rdar://problem/59131117ALL152S01085

rdar://problem/59082308107S00055 107S00090 ALL

rdar://problem/59081538107S00365 ALL107S00373

rdar://problem/59353109ALL152S00883152S01344

ALL152S00874152S00979 rdar://problem/59364196

197S00036 rdar://problem/59408673ALL197S00046

rdar://problem/59408673ALL197S00036197S00047

197S00036 rdar://problem/59408673ALL197S00048

rdar://problem/59408752138S0835 ALL138S00181

ALL138S0835 rdar://problem/59408752138S00291

rdar://problem/59407974ALL377S00160377S00166

rdar://problem/59408911138S00081 ALL138S00330

740S00028 rdar://problem/59408586ALL740S0118

rdar://problem/59407768ALL377S00031377S00123

ALL377S00060 rdar://problem/59407847377S00186

TABLE_ALT _HEAD

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

Alternate

Primary

Vendor
On Semi
Samsung

NXP

Murata On Semi
Samsung Murata
Diodes Inc
Chilisin
Bourns
NXP
On Semi

On Semi

Cyntec

LittleFuse

Diodes Inc

Vishay
TFT Cyntec
Taiyo Yuden
Chilisin
ROHM CORP
Diodes Inc
ROHM CORP
NEC/Kemet
Panasonic
Panasonic

Murata

Cyntec

Nexperia

Toshiba

Kemet

Kemet

Kemet

Kemet

PanasonicKemet

PanasonicTokin/Kemet
NEC/Kemet
Panasonic
Chilisin

Kemet

Kemet

Cyntec
Vishay Cyntec
Chilisin
NEC
Diodes Inc
Vishay
Fairchild
On Semi
AOS
Diodes Inc

Cyntec

Cyntec

Vishay

Vishay

Vishay

Vishay

Vishay

TI

AOSOn Semi
Yageo Cyntec
TFT
Kyocera
Taiyo
Taiyo
Taiyo

Yageo

Murata

Murata

Murata

Murata

MurataKyocera
Taiyo
Kyocera
Kyocera
Taiyo
Taiyo
Taiyo

Murata

Murata

Murata

Murata

Cyntec

Cyntec

CyntecMurata
Taiyo Cyntec
Chilisin
Chilisin
Cyntec

Murata

Murata

TFT

TFTCyntec

CyntecChilisin
Taiyo Cyntec
Epson
Kyocera
Murata
Samsung
Kyocera
Semtech

TXC

TXC

TXC

Murata

Murata

On Semi

MurataSEMCO
Polytronics
Semtech
Semtech

Bussmann

On Semi

ST Micro

PART NUMBER

371S00181

371S00085

353S00852

311S00156 rdar://problem/59489090

376S1080

138S00049

311S00269

311S00176

311S00178

376S1128

376S00224

128S00093

128S00103

128S00106

371S00190

353S4262

311S00129

376S0820

138S0831

311S00234

311S00153

311S00177

376S00282

376S00282

128S00009

128S00009

128S00009

128S00107 128S00009

128S00110 ALL rdar://problem/59361958

128S00009

376S00019

107S00102

107S0276

107S00017

107S00020

107S00371107S00370

107S00372

107S00298

107S0150

116S00007 ALL

107S00371

107S0208

107S0208

116S00006

ALL rdar://problem/59404055371S00220

ALL rdar://problem/59403423

ALL

ALL rdar://problem/59489026

ALL

ALL rdar://problem/59489341

ALL

ALL

ALL rdar://problem/59489044

ALL

ALL rdar://problem/59125761

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

rdar://problem/59404601ALL

rdar://problem/59408798

rdar://problem/59489111ALL

rdar://problem/59489119

rdar://problem/59489044

rdar://problem/59125761

rdar://problem/59361958

rdar://problem/59361958

rdar://problem/59489062376S1137

TBD107S00101 107S00005 ALL

TBD

TBD

TBD

TBD

TBD

TBD

TBD

ALL132S00064 TBD132S0409

132S0401 ALL132S00012

TBD

138S00084 ALL138S00060 TBD

TBD138S00097138S0750 ALL

138S00136 TBD138S00284 ALL

TBD138S0852 ALL138S0818

TBD138S0941138S0789 ALL

TBD155S00188155S0275 ALL

TBD155S0706 ALL155S0302

TBD155S0361 ALL155S0741

TBDALL155S0823 155S0644

TBD155S0667155S00007 ALL

TBD155S00190 ALL155S0914

rdar://problem/59571431138S0706 138S0739 ALL

ALL311S00267 TBD311S00244

ALL TBD311S00246311S00268

311S00060 ALL TBD311S0273

ALL311S00013 TBD311S0508

353S1429 ALL TBD353S02402

353S3698353S02440 rdar://problem/59682314ALL

740S00028 TBD740S0144 ALL

rdar://problem/60090733138S00343 138S00329 ALL

rdar://problem/60290671376S00292 376S1140 ALL

rdar://problem/60394183740S00081 740S00053 ALL

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

TABLE_ALT _ITEM

Alternate
VendorVendor

On Semi

Primary
Vendor

Diodes Inc

Diodes Inc
On Semi
Nexperia
Diodes Inc
Kyocera
Nexperia
Diodes Inc
On Semi

Diodes Inc

TI

On Semi

Murata

TI

TI

TI

On SemiDiodes Inc
Nexperia
Tokin/Kemet
Samsung
Tokin/Kemet
Kemet
Samsung
Vishay

On Semi

Kemet

Kemet

Kemet

Kemet

Kemet

Diodes Inc
Yageo Cyntec

CyntecYageo
Cyntec
Yageo
Vishay
TDK
Panasonic
Vishay
Taiyo Yuden
Murata
Taiyo Yuden
Murata
Kyocera
Samsung
Samsung
Taiyo Yuden
Taiyo Yuden
Murata
TDK and Taiyo
Taiyo Yuden
Taiyo Yuden
Murata
Nexperia
Nexperia
Diodes Inc
Diodes Inc
ON Semi
ON Semi
Bussman
Kyocera
Nexperia
Bourns

TFT

Cyntec

Cyntec

Murata

Murata

Yageo

Murata

Taiyo Yuden

Murata

Taiyo Yuden

Murata

Murata

Murata

Murata

Murata

TDK

Murata

Panasonic

Panasonic

Samsung

TI

TI

Philips

NXP

TI

TI

LittleFuse

Murata

Diodes Inc.

AEMI

BOM Alternates

EEEE

PP22

Pxxx

BOM NUMBER BOM NAME BOM OPTIONS

685-00339
685-00377
939-08408

COMMON PARTS,MLB,X1757

PARTS,SSDNAND1,MLB,X1757

PCBA,MLB,DCDC,X1757
DEV PARTS,MLB,X1757985-01176

PCBA,MLB,MSQ,X1757939-10388

MLB_COMMON

SSD_2L

DCDC_COMMON,DEV_PARTS_BOM,ALTERNATE,NANDCFG:INTERPOSER,CPU:INTERPOSER

MLB_DEV

CMN_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_512G_HY

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

SOC (BEST), Hynix and Micron 8GB

EEEE
PNR5
Q1P6
PNR7
Q1P7
Q1P8
Q1P9
PNR9
Q1PC
PNRD
PNRG
Q1PD

BOM NUMBER BOM NAME BOM OPTIONS

639-10741
639-11700
639-10743
639-11701

PCBA,MLB,BEST,SOC,HY-8G,SD-128G,X1757
PCBA,MLB,BEST,SOC,HY-8G,TO-128G,X1757
PCBA,MLB,BEST,SOC,HY-8G,HY-256G,X1757
PCBA,MLB,BEST,SOC,HY-8G,SD-256G,X1757
PCBA,MLB,BEST,SOC,HY-8G,TO-256G,X1757639-11702
PCBA,MLB,BEST,SOC,HY-8G,HY-512G,X1757639-11703

639-11704

PCBA,MLB,BEST,SOC,HY-8G,SD-1P0T,X1757

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_512G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_512G_TOPCBA,MLB,BEST,SOC,HY-8G,TO-512G,X1757639-10745

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_1P0T_TOPCBA,MLB,BEST,SOC,HY-8G,TO-1P0T,X1757639-10747
CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_2P0T_HYPCBA,MLB,BEST,SOC,HY-8G,HY-2P0T,X1757639-10749
CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_BEST,NANDCFG:ITLC_S5E_2P0T_TOPCBA,MLB,BEST,SOC,HY-8G,TO-2P0T,X1757639-11705

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

SOC (BEST), Hynix and Micron 16GB

EEEE
PNR6
Q1PQ
PNR8
Q1PR
Q1PT
Q1PV
PNRC
Q1PW
PNRF
PNRH
Q1PX

BOM NUMBER BOM NAME BOM OPTIONS

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_128G_SDPCBA,MLB,BEST,SOC,HY-16G,SD-128G,X1757639-10742

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_128G_TOPCBA,MLB,BEST,SOC,HY-16G,TO-128G,X1757639-11715

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_256G_HYPCBA,MLB,BEST,SOC,HY-16G,HY-256G,X1757639-10744

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_256G_SDPCBA,MLB,BEST,SOC,HY-16G,SD-256G,X1757639-11716

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_256G_TOPCBA,MLB,BEST,SOC,HY-16G,TO-256G,X1757639-11717

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_512G_HYPCBA,MLB,BEST,SOC,HY-16G,HY-512G,X1757639-11718

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_512G_TOPCBA,MLB,BEST,SOC,HY-16G,TO-512G,X1757639-10746

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_1P0T_SDPCBA,MLB,BEST,SOC,HY-16G,SD-1P0T,X1757639-11719

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_1P0T_TOPCBA,MLB,BEST,SOC,HY-16G,TO-1P0T,X1757639-10748

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_2P0T_HYPCBA,MLB,BEST,SOC,HY-16G,HY-2P0T,X1757639-10750

TABLE_BOM GROUP_ITEM

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_BEST,NANDCFG:ITLC_S5E_2P0T_TOPCBA,MLB,BEST,SOC,HY-16G,TO-2P0T,X1757639-11720

EEEE
PVD4
Q1PF
PVD6
Q1PG
Q1PH
Q1PJ
Q1PK
Q1PL
Q1PM
Q1PN
Q1PP

BOM NUMBER BOM NAME BOM OPTIONS

639-10924 PCBA,MLB,BEST,SOC,MI-8G,SD-128G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_128G_SD

PCBA,MLB,BEST,SOC,MI-8G,TO-128G,X1757639-11706 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_128G_TO

639-10926 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_256G_HY

PCBA,MLB,BEST,SOC,MI-8G,HY-256G,X1757
639-11707 PCBA,MLB,BEST,SOC,MI-8G,SD-256G,X1757
639-11708 PCBA,MLB,BEST,SOC,MI-8G,TO-256G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_256G_TO
639-11709 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_512G_HY

PCBA,MLB,BEST,SOC,MI-8G,HY-512G,X1757
639-11710 PCBA,MLB,BEST,SOC,MI-8G,TO-512G,X1757

PCBA,MLB,BEST,SOC,MI-8G,SD-1P0T,X1757639-11711 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_1P0T_SD
639-11712 PCBA,MLB,BEST,SOC,MI-8G,TO-1P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_1P0T_TO
639-11713 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_2P0T_HY

PCBA,MLB,BEST,SOC,MI-8G,HY-2P0T,X1757
639-11714 PCBA,MLB,BEST,SOC,MI-8G,TO-2P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_2P0T_TO

SOC (GOOD), Hynix and Micron 8GB

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_BEST,NANDCFG:ITLC_S5E_512G_TO

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

EEEE
PVD5
Q1PY
PVD7
Q1Q0
Q1Q1
Q1Q2
Q1Q3
Q1Q4
Q1Q5
Q1Q6
Q1Q7

BOM NUMBER BOM NAME BOM OPTIONS

PCBA,MLB,BEST,SOC,MI-16G,SD-128G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_128G_SD639-10925
639-11721 PCBA,MLB,BEST,SOC,MI-16G,TO-128G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_128G_TO
639-10927 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_256G_HYPCBA,MLB,BEST,SOC,MI-16G,HY-256G,X1757
639-11722 PCBA,MLB,BEST,SOC,MI-16G,SD-256G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_256G_SD
639-11723 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_256G_TOPCBA,MLB,BEST,SOC,MI-16G,TO-256G,X1757
639-11724 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_512G_HYPCBA,MLB,BEST,SOC,MI-16G,HY-512G,X1757
639-11725 PCBA,MLB,BEST,SOC,MI-16G,TO-512G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_512G_TO
639-11726 PCBA,MLB,BEST,SOC,MI-16G,SD-1P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_1P0T_SD
639-11727 PCBA,MLB,BEST,SOC,MI-16G,TO-1P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_1P0T_TO
639-11728 PCBA,MLB,BEST,SOC,MI-16G,HY-2P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_2P0T_HY
639-11729 PCBA,MLB,BEST,SOC,MI-16G,TO-2P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_BEST,NANDCFG:ITLC_S5E_2P0T_TO

SOC (GOOD), Hynix and Micron 16GB

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

EEEE
Q2D9
Q2DC
Q2DD
Q2DF
Q2DG
Q2DH
Q2DJ
Q2DK
Q2DL
Q2DM
Q2DN

EEEE
Q2DP
Q2DQ
Q2DR
Q2DT
Q2DV
Q2DW
Q2DX
Q2DY
Q2F0
Q2F1
Q2F2

BOM NUMBER BOM NAME BOM OPTIONS

PCBA,MLB,GOOD,SOC,HY-8G,SD-128G,X1757639-11752 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_128G_SD,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,TO-128G,X1757639-11753 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_128G_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,HY-256G,X1757639-11754 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_256G_HY,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,SD-256G,X1757639-11755 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_256G_SD,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,TO-256G,X1757639-11756 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_256G_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,HY-512G,X1757639-11757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_512G_HY,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,TO-512G,X1757639-11758 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_512G_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,SD-1P0T,X1757639-11759 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_1P0T_SD,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,TO-1P0T,X1757639-11760 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_1P0T_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,HY-2P0T,X1757639-11761 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_2P0T_HY,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,HY-8G,TO-2P0T,X1757639-11762 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_8GB_GOOD,NANDCFG:ITLC_S5E_2P0T_TO,SOC_SEL:GOOD

BOM NUMBER BOM NAME BOM OPTIONS

PCBA,MLB,GOOD,SOC,MI-8G,SD-128G,X1757639-11763 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_128G_SD,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,TO-128G,X1757639-11764 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_128G_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,HY-256G,X1757639-11765

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_256G_HY,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-8G,SD-256G,X1757639-11766 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_256G_SD,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,TO-256G,X1757639-11767 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_256G_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,HY-512G,X1757639-11768 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_512G_HY,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,TO-512G,X1757639-11769 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_512G_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,SD-1P0T,X1757639-11770 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_1P0T_SD,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,TO-1P0T,X1757639-11771 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_1P0T_TO,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,HY-2P0T,X1757639-11772 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_2P0T_HY,SOC_SEL:GOOD
PCBA,MLB,GOOD,SOC,MI-8G,TO-2P0T,X1757639-11773 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_8GB_GOOD,NANDCFG:ITLC_S5E_2P0T_TO,SOC_SEL:GOOD

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

EEEE
Q2F3
Q2F4
Q2F5
Q2F6
Q2F7
Q2F8
Q2F9
Q2FC
Q2FD
Q2FF
Q2FG

EEEE
Q2FH
Q2FJ
Q2FK
Q2FL
Q2FM
Q2FN
Q2FP
Q2FQ
Q2FR
Q2FT
Q2FV

BOM NUMBER BOM NAME BOM OPTIONS

PCBA,MLB,GOOD,SOC,HY-16G,SD-128G,X1757639-11774 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_128G_SD,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,HY-16G,TO-128G,X1757639-11775 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_128G_TO,SOC_SEL:GOOD
639-11776 PCBA,MLB,GOOD,SOC,HY-16G,HY-256G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_256G_HY,SOC_SEL:GOOD
639-11777 PCBA,MLB,GOOD,SOC,HY-16G,SD-256G,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_256G_SD,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,HY-16G,TO-256G,X1757639-11778 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_256G_TO,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,HY-16G,HY-512G,X1757639-11779 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_512G_HY,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,HY-16G,TO-512G,X1757639-11780 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_512G_TO,SOC_SEL:GOOD
639-11781 PCBA,MLB,GOOD,SOC,HY-16G,SD-1P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_1P0T_SD,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,HY-16G,TO-1P0T,X1757639-11782 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_1P0T_TO,SOC_SEL:GOOD
639-11783 PCBA,MLB,GOOD,SOC,HY-16G,HY-2P0T,X1757 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_2P0T_HY,SOC_SEL:GOOD
639-11784 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_HYNIX_16GB_GOOD,NANDCFG:ITLC_S5E_2P0T_TO,SOC_SEL:GOODPCBA,MLB,GOOD,SOC,HY-16G,TO-2P0T,X1757

BOM NUMBER BOM NAME BOM OPTIONS

639-11785 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_128G_SD,SOC_SEL:GOODPCBA,MLB,GOOD,SOC,MI-16G,SD-128G,X1757

PCBA,MLB,GOOD,SOC,MI-16G,TO-128G,X1757639-11786 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_128G_TO,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,HY-256G,X1757639-11787

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_256G_HY,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,SD-256G,X1757639-11788 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_256G_SD,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,TO-256G,X1757639-11789 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_256G_TO,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,HY-512G,X1757639-11790 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_512G_HY,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,TO-512G,X1757639-11791 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_512G_TO,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,SD-1P0T,X1757639-11792 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_1P0T_SD,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,TO-1P0T,X1757639-11793 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_1P0T_TO,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,HY-2P0T,X1757639-11794 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_2P0T_HY,SOC_SEL:GOOD

PCBA,MLB,GOOD,SOC,MI-16G,TO-2P0T,X1757639-11795 CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU:SOC_MICRON_16GB_GOOD,NANDCFG:ITLC_S5E_2P0T_TO,SOC_SEL:GOOD

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

BOM Variants

End of Schematic

PAGE TITLE

SYNC_DATE=11/22/2019SYNC_MASTER=JOHNO

----

SIZEDRAWING NUMBER

051-05392