Apple Macbook Air A2337 Schematic

X1757/MLB

LAST_MODIFICATION=Tue May 5 21:26:43 2020LAST_MODIFICATION=Tue May 5 21:26:43 2020

DATESYNCCSAPAGEDATESYNCCONTENTSCSAPAGE

1
2
3
4
5
6

8
9
10
11
12
13
14

1
2
3
4
5
6
7

9
10
11
12
13
14

Table of Contents
BOM Configuration
BOM Configuration
PD Parts
SOC: Support

SOC: AP I/Os
SOC: LPDP & MIPI
SOC: PCIE
SOC: AOP
SOC: POWER (DDR,SRAM)
SOC: POWER (IO)
SOC: POWER (SOC, CPU, GPU)
SOC: POWER (SRAM)

eli 08/27/2019

06/06/2019
06/06/2019
06/06/2019

ref_soc_h13g

ref_soc_h13g
ref_soc_h13g
ref_soc_h13g 54
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g

05/04/2020
05/04/2020
05/04/20207
05/04/20208
05/04/2020
05/04/2020
05/04/2020
05/04/2020
05/04/2020
05/04/2020

46
47
48
49

52
53

55
56
57
58
59

138
140
141
144

SENSORS: POWER LOW SIDE (1/2) t668
SENSORS: POWER SUPPORT
Sensors: Thermal

SENSORS: MOTION
14950 RIO Connector
150
151
152
153
154
155
156
157
159

USB-C: High Speed ATC051ref_soc_h13gSOC: CIO, USB, RESETS, CLOCKS, SWD

USB-C: High Speed ATC1

USB-C: Support 1 ATC01

USB-C: Support 2 ATC01

USB-C: Port Controller ATC0

USB-C: Port Controller ATC1 ref_usbc_ace2

USB-C: Connector(s)

USB-C: HS Level Shifters

USB-C: Project Specific

08/27/2019

t668

t668 09/27/2019
tga_140
ref_usbc_ace2
ref_usbc_ace2
ref_usbc_ace2
ref_usbc_ace2
ref_usbc_ace2

ref_usbc_ace2
ref_usbc_ace2 04/24/2020

08/27/2019

05/31/2019
04/24/2020
04/24/2020
04/24/2020
04/24/2020
04/24/2020
04/24/2020
09/26/2019

15

15

1616
17
18

17

18
19 19
20

21
21 ref_se_ceres50
22
23
24
25
26
27
28

51

52

53

57

58 ref_vr_iceman

59

77

SOC: POWER (Fixed, PLL's, Filtered)
SOC: GND
SOC: GND-2
SOC: DESENSE CAPS
SPI NOR
SOC: Project Support
Secure Element
BMU Connector, Btn Logic
PBUS SUPPLY & BATTERY CHARGER
BATTERY CHARGER SUPPORT
POWER: 3V8 AON (1/2)
POWER: 3V8 AON (2/2)
POWER: 3V8 AON SUPPORT
PMU: SLAVE INPUT PWR & BUCKS

ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g
ref_soc_h13g

tga_140
ref_charger_suona
ref_charger_suona
ref_vr_iceman

T585_REF_VR_ICEMAN_0.36.0
ref_pmu_sera_simetra

05/04/2020
05/04/2020 ref_wireless_rasputin
05/04/2020
10/08/2019
05/04/2020

03/29/2020
05/31/2019
05/02/2020
05/02/2020
04/20/2020
04/20/2020
10/11/2019
04/28/2020

60
61

201

WIFI/BT: MODULE

WIFI/BT: ANTENNA and GND 04/28/2020
62 220 STORAGE: SSD0 S5E <0>
63 STORAGE: SSD0 S5E <1>
64
65

221
224
230

STORAGE: NON OCARINA SUPPORT

STORAGE: SSD Support

23166 SECDIS: MIPI MUX ref_secdis_mipimux 10/07/2019
67
68

236

237

23869
70 239
71
72
73

242

243

244

eDP Display Connector
DISPLAY POWER SEQUENCER ref_panelpwr_bnj
BEN: CONTROLLER
BEN: KEYBOARD
SECDIS: AMR
SECDIS: FPGA
Audio Level Shifters

ref_wireless_rasputin200

ref_storage_s5e
ref_storage_non_ocarina_support
T668

tga_140

ref_blc_ben
ref_blc_ben
ref_secdis_amr
ref_secdis_sak
ref_spkramp_tas5770

04/28/2020

05/02/2020ref_storage_s5e
05/02/2020
02/17/2020
08/01/2019

05/31/2019
05/02/2020
11/20/2019
11/20/2019
10/21/2019
04/28/2020
11/18/2019

29
30

78

79
31 80
32
33
34
35
36
37
38
39
40
41
42

81

82

83

84

121

122

123

127

128

130

131

PMU: SLAVE LDO
PMU: SLAVE GPIO & GND
PMU: Slave extra
PMU: MASTER INPUT PWR & BUCKS
PMU: MASTER BUCKS & GND
PMU: MASTER LDO & GPIO
PMU: Master extra
Power: LDOs
POWER: 5V, 3V3 Support
POWER: 5V S2
POWER: 3V3 S2
Power: Load Switches
I2C: SIO, DISP
I2C: ISP, AOP

ref_pmu_sera_simetra
ref_pmu_sera_simetra

ref_pmu_sera_simetra

ref_pmu_sera_simetra

tga_140

ref_vr_5v_lt8642s
ref_vr_3v3_tps62135
tga_140
eli
T668

04/28/2020
04/28/2020

04/28/2020
04/28/2020ref_pmu_sera_simetra
04/28/2020

05/31/2019

04/20/2020
01/02/2020
05/31/2019
10/15/2019
08/01/2019

74
75

246
248

AUDIO AMPLIFIERS (1/2)

Audio Connectors
76 253 Trackpad Support
77 254
78
79
80
81

260 Power Aliases - 1 tga_140 05/31/2019
261
263

264 Signal Aliases 2
82 270
83
84
85

281

500

501
86 502
87

503

IPD Combined Connector

Power Aliases - 2
Signal Aliases 1

DEBUG
Desense

17.2 RULES

17.2 PHYSICAL CSETS

17.2 SPACING CSETS, ISO

ref_spkramp_tas5770
tga_140
ref_ipd_oregano 08/01/2019
card_ipd_oregano 08/01/2019

tga_140

tga_140

eli
eli
eli 10/15/2019
eli17.2 SPACING CSETS, CLASS-CLASS

04/20/2020
05/31/2019

05/31/2019

05/31/2019

10/15/2019
10/15/2019

10/15/2019

43
44
45

132
135
136

I2C: SMC
SENSORS: POWER HIGH SIDE (1/2) 11/01/2019t668
SENSORS: POWER HIGH SIDE (2/2)

T668
t668
t668

08/01/2019
08/27/2019
08/27/2019

88
89
90

601

602

610 BOM Alternates

BOM OPTION TABLES
BOM GROUPS

t668

11/01/2019

Programmable PartsBModule PartsA

TBT Burnside Bridge

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

338S00561 CRITICAL TBT_BB:PRQA12 UF000,UF100

IC,TBT,BBR,SLMN7,PRQ,A1,BGA105

Ace2

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123353S02158 UF400,UF500 ACE2:B2_BGA2 CRITICAL

eUSB Level Shifter

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

2 CRITICAL EUSB_LS:B0_OTP6998-20641 UF700,UF750IC,PARROT,CD2E224,B0,OTP-6,CSP25

Secure Element

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

338S00630

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_I TEM

CRITICAL2 EUSB_LS:B0_LSB1_OTP6338S00628 UF700,UF750IC,PARROT,CD2E226B,B0 LSB1,OTP-6,CSP25

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TBT ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART# BOM OPTIONCRITICAL

335S00133

IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8 CRITICAL TBT_ROM:BLANK1 UF260

PART NUMBER

ROM,TBT/ACE (V31.5) PROTO-1,X1757

ROM,TBT/ACE (V2.45.0.7) PROTO-1,X1757

UF260 CRITICAL1 TBT_ROM:PP1341S01676

SOC ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART# BOM OPTIONCRITICAL

998-20613 1 CRITICAL SOC_ROM:BLANK_ORIGU1970

335S00500 rdar://problem/59964804U1970335S00494

IC,SPI SERIAL FLASH,64MBIT,1.8V,XSON8

IC,SPI SERIAL FLASH,64MBIT,1.8V,4X3,SON8 SOC_ROM:BLANKU1970 CRITICAL1335S00494

PART NUMBER

SOC_ROM:BLANK

TABLE_ALT _HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT _ITEM

rdar://problem/50598337TBT_ROM:BLANK335S00232 UF260335S00133

CRITICAL1341S01617 TBT_ROM:PP0UF260

TABLE_ALT _HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT _ITEM

CRITICALU5000 SE:DEV_SW_V71998-19915 IC,SN210V,B1,CERES,DEV KY,SW=V7,WLCSP81

TABLE_5_I TEM

CRITICALU5000 SE:DEV_SW_H31998-21255 IC,SN210V,B1,CERES,DEV,SW=H3,WLCSP81

TABLE_5_I TEM

SE:PROD_SW_MUCRITICALU50001 IC,SN210V,B1,CERES,PROD,VER=MU,WLCSP81

BOM Configuration

A

BOM Groups

BOM GROUP BOM OPTIONS

MLB_COMMON

MLB_USBC

MLB_PROGPARTS

MLB_POWER

MLB_WIRELESS

MLB_MECH
MLB_MISC

MLB_DEV
MLB_BLC

SCHEM,PCBF,ALTERNATE,COMMON,CMN_IC,MLB_PROGPARTS,MLB_USBC,MLB_POWER,MLB_WIRELESS,MLB_MECH,MLB_MISC,MLB_BLC,EVT,SECDIS_EXT_CLK,DMIC_CLK_10OHM

TBT_BB:PRQA1,ACE2:B2_BGA,UPC_ATCRTMR_INT,UPC_EUSBLS_INT,EUSB_LS:B0_LSB1_OTP6

WFBT_ROM:BLANK,SOC_ROM:BLANK,TBT_ROM:PP1,SE:PROD_SW_MU

PBUS_3S,MPMU_IC:B0,SPMU_IC:A1,P3V8AON_IC:A1_R0B0

WLBT:ES6_3_M

SHLD_CAN_BSB:EVT,SHLD_CAN_ICE:EVT

BOARD_ID,SYSDET:FET,BOOT_CONFIG2,LOADISNS

DEVELOPMENT,WLBT_DBG,USBC_DBG

BLC_BEN_IC:V7,BLC_LEDS_PER_STRING:16,BLC_5V_CAP:4P7_UF,BLC_5V_SERIES:10_OHM,BLC_KBD_BOOST_USED:YES

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 CRITICALCBOMCOMMON PARTS,MLB,X1757 CMN_PARTS_BOM685-00339

CRITICAL1 PARTS_SSDNAND1PARTS,SSDNAND1,MLB,X1757685-00377 P1BOM

CRITICAL1 DEV1985-01176 DEV PARTS,MLB,X1757 DEV_PARTS_BOM

051-05392 SCHEMSCHEMSCHEM,MLB,X17571 CRITICAL

CRITICAL820-02016 PCBF PCBF1 PCBF,MLB,X1757

TABLE_5_H EAD

BOM OPTIONCRITICAL

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

TABLE_5_I TEM

B

Build Specific Groups

BOM GROUP BOM OPTIONS

BOARDID1,BOARDID2BOARD_ID
PROTO0
PROTO1 BOARD_REV3,BOARD_REV2,BOARD_REV1

BOARD_REV3,BOARD_REV2,BOARD_REV1,BOARD_REV0

BOARD_REV3,BOARD_REV2,BOARD_REV0EVT

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

Pull-ups: 0x0000110

TABLE_BOM GROUP_ITEM

Pull-downs: 0x0000

TABLE_BOM GROUP_ITEM

Pull-downs: 0x0001

TABLE_BOM GROUP_ITEM

Pull-downs: 0x0002

C

DC/DC BOM Groups

BOM GROUP BOM OPTIONS

DCDC_COMMON

DCDC_USBC UPC_ATCRTMR_INT,UPC_EUSBLS_INT

D

Reference Design Pack Options

PACK_OPTIONS TO INCLUDE IN NETLIST

USBC_SPI_UPC0

USBC_DEBUG_UPC0

USBC01_VR5V_LOCAL_NO

USBC_LAPTOP

NO_DFR

FTCAM

HAS_LID

5V_S2_PBUS-D12
3V3_S2_PBUS-D2

3V8_AON_PBUS-B12

3V8_AON_I2C-DEV

NO_AMR_INTERPOSER_LEFT

NO_AMR_INTERPOSER_RIGHT

PKGS:SMALL_PITCH

ACE2_SS_CAP

SCHEM,PCBF,COMMON,DCDC_USBC,MLB_POWER,MLB_MECH,MLB_MISC,MLB_BLC,EVT

PACK_OPTIONS TO INCLUDE IN NETLISTPACK_OPTIONS TO INCLUDE IN NETLIST

PROD_SECDIS

JTAG_SECDIS:NO

PROTO_PULLDOWN_SECDIS

80UM_STEN

INTERNAL_DISPLAY

CHGR_40W

PACK_OPTIONS TO INCLUDE IN NETLIST

SUNWAY

WLBT_DBG_CONN

SPKRAMP_A

PORTABLE

SMALL_NOR

SPKRAMP_LVL_SON

TABLE_BOM GROUP_HEAD

TABLE_BOM GROUP_ITEM

TABLE_BOM GROUP_ITEM

PACK_OPTIONS TO INCLUDE IN NETLIST

CHGR_TP

CHGR_TP_BOT

3V8_EXT_DIODE

BOM Configuration

Mounting HolesA

Burnside Bridge Shield CanD

SH0400

TH-NSP TH-NSP

1

SL-3.41X2.0-5.91X4.5

998-11113

SH0402

4.6R1.7-NSP

1

998-19374998-19374

SH0401

1

SL-3.41X2.0-5.91X4.5

998-11114

SH0403

4.6X5.2R1.7X2.3-NSP

1

E

Plated slots for shield can

SH0430

TH-NSP

1

SL-0.5X1.28-1.25X2.03

Sled, Thermal Module

SHLD1SHIELD CAN,BURNSIDE BRIDGE,X1419806-19070 CRITICAL SHLD_CAN_BSB1

SH0431

TH-NSP

1

SL-0.5X1.28-1.25X2.03

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SHLD_CAN_BSB:EVTSHIELD CAN,BURNSIDE BRIDGE,X1739806-26240 1 CRITICALSHLD1

Heatsink Mounting HolesB

998-6473

SH0410

4P0R3P15-NSP

1

998-21888

SH0412

4.45R3.6-NSP

1

998-22161

SH0411

TH-NSP

1

SL-3.65X3.15-4.45X4.0

998-21888

SH0413

4.45R3.6-NSP

1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SLD1,SLD22 CRITICAL806-25230 SLED,SOLDER,X1757

C

Antenna Cowling Bosses

860-01273

SH0420

5.25X2.8R-1.4ID-1.81H-SM

1

F

Inductor Shield Fence

SHIELD FENCE,ICEMAN,INDUCTORS,X1739806-27192 SHLD2 SHLD_CAN_ICE1 CRITICAL

Plated slots for shield can

998-1681

SH0440

TH

1

SL-0.4X1.20

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

998-1681

SH0441

TH

1

SL-0.4X1.20

SHLD_CAN_ICE:EVTSHIELD,FENCE,INDUCTORS,X1739806-27475 CRITICAL1 SHLD2

PD Parts

**OK2INTEGRATE**

BOOT CONFIG ID

720

720

720

BOOT_CONFIG2

OUT

BOOT_CONFIG1

OUT

BOOT_CONFIG0

OUT

BOOT_CFG[2:0]

000
001
010
011

POR ---> 100

101
110
111

78 12 9 7 6 5

PP1V25_AWAKE_IO

MODE
SPI1 NOR (12 MHZ)
SPI1 NOR (12 MHZ) TESTMODE
SPI0 NAND
SPI0 NAND TESTMODE
SPI1 NOR (40 MHZ)
SPI1 NOR (40 MHZ) TESTMODE
SPI1 NOR (6 MHZ)
SPI1 NOR (6MHZ) TESTMODE

1

R0502

4.7K

5%
1/20W
MF
201

2

1

R0501

4.7K

5%
1/20W
MF
201

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

BOOT_CONFIG0BOOT_CONFIG1BOOT_CONFIG2

1

R0500

4.7K

5%
1/20W
MF
201

2

R0533

10K

5%

1/20W

MF

201

R0534

10K

5%

1/20W

MF

201

21

SOC_JTAG_SEL

21

SOC_TESTMODE

OUT

OUT

10

6

BOARD ID

78 12 9 7 6 5

7

7

7

7

7

BOARD_ID4

OUT

BOARD_ID3

OUT

BOARD_ID2

OUT

BOARD_ID1

OUT

BOARD_ID0

OUT

PP1V25_AWAKE_IO

BOARDID4

1

R0514

1K

5%
1/20W
MF
201

2

1

R0513

1K

5%
1/20W
MF
201

2

1

R0512

1K

5%
1/20W
MF
201

2

BOARDID0BOARDID1BOARDID2BOARDID3

1

R0511

1K

5%
1/20W
MF
201

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

1

R0510

1K

2

5%
1/20W
MF
201

PP1V25_AWAKE_IO

78

SEP EEPROM (128-Kbit)

PP1V8_AWAKE

1

R0540

2.2K

5%
1/20W
MF
201

2

R0535

10K

5%

1/20W

MF

201

SOC_HOLD_RESET

21

R0536

10K

1/20W

(Write: 0xA2, Read 0xA3)

21

SOC_KIS_DFU_SELECT

5%
MF

201

APN:335S00455

1

R0541

2.2K

5%
1/20W
MF
201

2

VCC

U0500

STOCT

DFN

OUT

OUT

6

6

1

C0500

1.0UF

20%
4V

2

X6S
0201

REFERENCE DESIGN ATOR

U0600

PIN DELAY MAPPING FILE

PIN DELAY CSV FI LE NAME

TGA_PINDELAY_2020_03_26.csv

BOARD REVISION

7

OUT

7

OUT

7

OUT

7

OUT

BOARD_REV0
BOARD_REV1
BOARD_REV2
BOARD_REV3

BOARD_REV3

1

R0523

1K

5%
1/20W
MF
201

2

NOTE: STUFFING RESISTOR MEANS 0

BOARD_REV0BOARD_REV1BOARD_REV2

1

R0522

1K

5%
1/20W
MF
201

2

1

R0521

1K

5%
1/20W
MF
201

2

R0520

1K

5%
1/20W
MF
201

2

I2C_SEEPROM_SCL

7

I2C_SEEPROM_SDA

7

OCELOT I2C pulls

7

SCL

6

SDA

VSS EPAD

VIO

NC

5

2

NC

3

NC

4

NC

board rev should start at 0b0000 and increment each rev.

S/W READ FLOW

1. SET GPIO AS INPUT

2. ENABLE PU AND DISABLE PD

3. READ

PAGE TITLE

SOC: Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

5 OF 801

SHEET

5 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

D

2

1

8

**OK2INTEGRATE**

SOC: CIO, USB, DRAM, RESETS, CLOCKS, SWD, FPWM

OMIT_TABLE

U0600

TMLR68A0-B09

BGA

SYM 1 OF 23

10347282

IN

6345482

5

IN

345382

IN

5

IN

PMU_RESET_L

SOC_FORCE_DFU
SOC_REQUEST_DFU1

6

SOC_REQUEST_DFU2

6

SOC_TESTMODE

PMU_ACTIVE_READY

SOC_HOLD_RESET

R2

AA49
AK55
AJ54

AD2

AL54

AC1

LP4_IN_RESET_N

FORCE_DFU
REQUEST_DFU1
REQUEST_DFU2

TESTMODE

CFSB

HOLD_RESET

IPD

IPD

RESET

DFU_STATUS

V51

SOC_DFU_STATUS

OUTIN

20 54 82

AMUX_OUT can go to TP or to AMUX_IN on PMU

SOC_KIS_DFU_SELECT

5

20

BI

20

BI

58

IN

58

OUT

EUSB_ATC0_P
EUSB_ATC0_N

CIO_ATC0_LSRX_1V2
CIO_ATC0_LSTX_1V2

SOC_ATC0_USB_RESREF

6

AB49

BB54
BB55

BE18
BE13

BB53

KIS_DFU_SELECT

ATC0_USB_EDP
ATC0_USB_EDM

USB_C0_LSRX
USB_C0_LSTX

ATC0_USB_RESREF

CLOCKS

XI0
XO0

TST_CLKOUT

BE36
BF36

P54

SOC_XTAL24M_IN
SOC_XTAL24M_OUT

TPT_TST_CLKOUT

20

SOC_ATCPHY0_RCAL_POS

6

SOC_ATCPHY0_RCAL_NEG

6

SOC_ATCPHY1_RCAL_POS

6

SOC_ATCPHY1_RCAL_NEG

6

1

R0600

200

1%
1/20W
MF
201

2

1

C0600

10PF

5%
25V

2

C0G
0201

1

R0601

200

1%
1/20W
MF
201

2

1

C0601

10PF

5%
25V

2

C0G
0201

TPT_TMU_CLK_OUT0

20

20

BI

20

BI

58

IN

58

OUT

51

BI

51

BI

51

OUT

51

OUT

51

BI

51

BI

51

OUT

51

OUT

51

BI

51

BI

52

BI

52

BI

52

OUT

52

OUT

52

BI

52

BI

52

OUT

52

OUT

EUSB_ATC1_P
EUSB_ATC1_N

CIO_ATC1_LSRX_1V2
CIO_ATC1_LSTX_1V2

SOC_ATC1_USB_RESREF

6

TPT_TMU_CLK_OUT1

20

USB_VBUS_DETECT

6

USBC_ATC0_D2R_P<1>
USBC_ATC0_D2R_N<1>
USBC_ATC0_R2D_C_P<1>
USBC_ATC0_R2D_C_N<1>

USBC_ATC0_D2R_P<2>
USBC_ATC0_D2R_N<2>
USBC_ATC0_R2D_C_P<2>
USBC_ATC0_R2D_C_N<2>

USBC_ATC0_AUX_P
USBC_ATC0_AUX_N

SOC_ATCPHY0_RCAL_POS

6

SOC_ATCPHY0_RCAL_NEG

6

USBC_ATC1_D2R_P<1>
USBC_ATC1_D2R_N<1>
USBC_ATC1_R2D_C_P<1>
USBC_ATC1_R2D_C_N<1>

USBC_ATC1_D2R_P<2>
USBC_ATC1_D2R_N<2>
USBC_ATC1_R2D_C_P<2>
USBC_ATC1_R2D_C_N<2>

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

V48

BC54
BC55

BD3

BE10

BC53

R48

AG1

BE50
BF50
BC49
BD49

BE48
BF48
BC47
BD47

AY51
AY52

BE52
BF52

BF44
BE44

BF46
BE46
BD45
BC45

USB_C0_HPD/TMU_CLK_OUT0

ATC1_USB_EDP
ATC1_USB_EDM

USB_C1_LSRX
USB_C1_LSTX

ATC1_USB_RESREF

USB_C1_HPD/TMU_CLK_OUT1

EUSB_VBUS_DETECT

ATCPHY0_RX0_P
ATCPHY0_RX0_N
ATCPHY0_TX0_P
ATCPHY0_TX0_N

ATCPHY0_RX1_P
ATCPHY0_RX1_N
ATCPHY0_TX1_P
ATCPHY0_TX1_N

ATCPHY0_AUX_P
ATCPHY0_AUX_N

ATCPHY0_RCAL_P
ATCPHY0_RCAL_N

ATCPHY1_RX0_P
ATCPHY1_RX0_N
ATCPHY1_TX0_P
ATCPHY1_TX0_N

ATCPHY1_RX1_P
ATCPHY1_RX1_N
ATCPHY1_TX1_P
ATCPHY1_TX1_N

ATC

SWD

FPW

ANALOGMUX_OUT

SWD_TCK_OUT1

SWD_TMS2
SWD_TMS3
SWD_TMS4

FPWM0/MASTER_SYNC_GEN_0

FPWM1
FPWM2

AL48

AJ1
U54
V54
AH3

V50
Y49

SOC_AMUX_OUT

SWD_NAND0_SWCLK
SWD_NAND0_SWDIO
NC_SWD_TMS3
NC_SWD_TMS4

IPD

WLAN_TIME_SYNC
KBD_BKLT_PWM
NC_FPWM2

78 12 9 7 6 5

6

PP1V25_AWAKE_IO

SOC_REQUEST_DFU1

OUT

OUT

BI

81

81

IN

OUT

81

1

2

20

20

20

60

70

78 12 9 7 6 5

R0630

10K

5%
1/20W
MF
201

499

1%

1/20W

MF

201

1

2

R0651

SOC_24M_O_R

CRITICAL

1

C0650

15PF

5%
50V

2

C0G
0201

PP1V25_AWAKE_IO

SOC_REQUEST_DFU2

6

CRITICAL

Y0600

1.60X1.20MM

24.000MHZ-20PPM-9.5PF-60OHM

31

42

SOC_FORCE_DFU

6345482

1

R0631

10K

5%
1/20W
MF
201

2

CRITICAL

1

C0651

15PF

5%
50V

2

C0G
0201

1

R0632

47K

5%
1/20W
MF
201

2

78 12 9 7 6 5

PP1V25_AWAKE_IO

USB_VBUS_DETECT

6

1

R0639

0

5%
1/20W
MF
0201

2

52

BI

52

BI

USBC_ATC1_AUX_P
USBC_ATC1_AUX_N

SOC_ATCPHY1_RCAL_POS

6

SOC_ATCPHY1_RCAL_NEG

6

BA52
BA51

BF42
BE42

ATCPHY1_AUX_P
ATCPHY1_AUX_N

ATCPHY1_RCAL_P
ATCPHY1_RCAL_N

SOC_ATC0_USB_RESREF

6

1

R0641

200

1%
1/20W
MF
201

2

SOC_ATC1_USB_RESREF

6

1

R0640

200

1%
1/20W
MF
201

2

PAGE TITLE

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SOC: CIO, USB, RESETS, CLOCKS, SWD

SIZE

D

PART NUMBER

197S0591 EPSON,24MHZ.XTAL197S0590 Y0600
197S0591 TXC,24MHZ,XTAL197S0588 Y0600

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

BOM_COST_GROUP=SOC

TABLE_ALT _HEAD

TABLE_ALT _ITEM

TABLE_ALT _ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

6 OF 801

SHEET

6 OF 92

2

13

6

**OK2INTEGRATE**

all signals are 1.2 unless otherwise specified.
all signals on this page reference PP1V2_AWAKE_GRP if they are 1.2V
if they are 1.8V they reference PP1V8_AWAKE_GRP

SOC: I/Os

U0600

TMLR68A0-B09

BGA

SYM 3 OF 23

20

OUT

80

IN

20

OUT

20

OUT

TDM_SPKRAMP_L_BCLK_R
TDM_SPKRAMP_L_D2R
TDM_SPKRAMP_L_R2D_R
TDM_SPKRAMP_L_FSYNC_R
NC_SOC_I2S0_MCK

81

AK4
AJ3
AJ5
AJ4
AK3

I2S0_BCLK
I2S0_DIN
I2S0_DOUT
I2S0_LRCK
I2S0_MCK

IPD

IPD

IPD

SPI0_MISO
SPI0_MOSI
SPI0_SCLK

SPI1_MISO
SPI1_MOSI

20

OUT

80

IN

20

OUT

20

OUT

TDM_SPKRAMP_R_BCLK_R
TDM_SPKRAMP_R_D2R
TDM_SPKRAMP_R_R2D_R
TDM_SPKRAMP_R_FSYNC_R
NC_SOC_I2S1_MCK

81

AG3
AF3
AG4
AF2
AG2

I2S1_BCLK
I2S1_DIN
I2S1_DOUT
I2S1_LRCK
I2S1_MCK

IPD

I2S

SPI

IPD

SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK

50

OUT

50

IN

50

OUT

50

OUT

TDM_CODEC_BCLK_R
TDM_CODEC_D2R
TDM_CODEC_R2D_R
TDM_CODEC_FSYNC_R
NC_SOC_I2S2_MCK

81

AK5
AL6
AJ7
AM4
AK6

I2S2_BCLK
I2S2_DIN
I2S2_DOUT
I2S2_LRCK
I2S2_MCK

SPI2_SSIN

IPD

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

NC_I2S3_BCLK

81

NC_I2S3_D2R

81

NC_I2S3_R2D

81

NC_I2S3_LRCLK

81

NC_I2S3_MCLK

81

AH6
AH4
AG5
AJ6
AF5

I2S3_BCLK
I2S3_DIN
I2S3_DOUT
I2S3_LRCK
I2S3_MCK

IPD

SPI4_MISO
SPI4_MOSI
SPI4_SCLK
SPI4_SSIN

AL4
AK2
AK1

AD4
AE4
AF4
AE3

AF53
AF54
AF55
AF52

Y1
W1
AB1
AA1

AC4
AB4
AA4
AB3

BOOT_CONFIG2
BOOT_CONFIG1
BOOT_CONFIG0

SPI_SOCROM_MISO
SPI_SOCROM_MOSI_R
SPI_SOCROM_CLK_R
SPI_SOCROM_CS_L

SPI_1V8_TOUCHID_MISO
SPI_1V8_TOUCHID_MOSI_R
SPI_1V8_TOUCHID_CLK_R
NC_SOC_SPI2_SSIN

SPI_IPD_MISO
SPI_IPD_MOSI_R
SPI_IPD_CLK_R
SPI_IPD_CS_L

SPI_TCON_MISO
SPI_TCON_MOSI_R
SPI_TCON_CLK_R
SPI_TCON_CS_L

5 20

IN

5 20

OUT

5 20

OUT

19

IN

19

OUT

19

OUT

19

OUT

50

IN

50

OUT

50

OUT

81

76

IN

20

OUT

20

OUT

76

OUT

67

IN

20

OUT

20

OUT

67

OUT

1.8V IO

1.8V IO

41

OUT

41

BI

41

OUT

41

BI

41

OUT

41

BI

I2C_UPC_SCL
I2C_UPC_SDA

I2C_SPKRAMP_L_SCL
I2C_SPKRAMP_L_SDA

NC_I2C_CODEC_SCL
NC_I2C_CODEC_SDA

W52
V52

AA48

Y48

AB50

Y50

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

I2C2_SCL
I2C2_SDA

I2C

SEP

SGPIO0
SGPIO1

SI2C0_SCL
SI2C0_SDA

SSPI0_MISO
SSPI0_MOSI
SSPI0_SCLK

41

OUT

41

BI

41

OUT

41

BI

I2C_SPKRAMP_R_CODEC_SCL
I2C_SPKRAMP_R_CODEC_SDA

NC_I2C_DFR_SCL
NC_I2C_DFR_SDA

AF6
AE6

AF50
AG49

I2C3_SCL
I2C3_SDA

I2C4_SCL
I2C4_SDA

THROTTLE

IPU FOR ALL

THROTTLE_TRIGGER

THROTTLE_TRIGGER0/MTR_ADC_DOUT

SOCHOT1

THROTTLE_TRIGGER1/MTR_ADC_CLKOUT

THROTTLE_TRIGGER2/PLL_DIGOBS_0
THROTTLE_TRIGGER3/PLL_DIGOBS_1

THROTTLE_TRIGGER4

NC_SPMI2_CLK

81

NC_SPMI2_DATA

81

AK7

AP_SPMI2_SCLK

AL7

AP_SPMI2_SDATA

SPMI

AC3
AC2

Y5
Y4

AC5
AD5
AD6

AK52

AK53
AL53
AJ55
AJ53
AJ49

DBL_CLICK_DET
DISABLE_STROBE

I2C_SEEPROM_SCL
I2C_SEEPROM_SDA

FTCAM_DISABLE_L
NC_SSPI0_MOSI
DMIC_DISABLE_L

SOC_SOCHOT_L

BUCK1_THERMAL_THROTTLE_L
BUCK0_THERMAL_THROTTLE_L
NC_SOC_TRIGGER2
PMU_VDDHI_UVWARN_L
PMU_VDDMAIN_UVWARN_L

PORTABLES SHOULD NC TRIGGER2

81

OUT

OUT

OUT

OUT

OUT

IN
IN
IN
IN
IN

IN

BI

34

72

5

5

72

72

7 34

34 35

34 35

80

35

34 35

78 12 9 6 5

PP1V25_AWAKE_IO

SOC_SOCHOT_L

734

1

R0790

47K

5%
1/20W
MF
201

2

UPC_FORCE_PWR will likely be

removed in the future

TOUCHID_PWR_EN gets
pulled up to S2 on
TOUCHID page
This is OK because
the GPIO is failsafe

PD needed on DFR PAGE

U0600

TMLR68A0-B09

BGA

SYM 2 OF 23

41

IN

75

IN

75

IN

80

OUT

5074

IN

5075

IN

53

OUT

20

IN

81

IN

5

IN

5

IN

5

IN

5

IN

81

IN

53

BI

80

BI

80

IN

81

OUT

50

IN

80

OUT

2059

OUT

80

OUT

80

OUT

80

IN

UPC_I2C_INT_L
NC_SOC_GPIO01

81

SPKR_ID0
SPKR_ID1
SPKRAMP_RESET_L
SPKRAMP_INT_L
CODEC_INT_L
SWD_UPC_SWCLK
GPU_CFG_L
NC_SOC_GPIO09

81

NC_SOC_GPIO10
BOARD_REV0
BOARD_REV1
BOARD_REV2
BOARD_REV3
NC_SOC_GPIO15 NC_UART3_D2R
NC_SOC_GPIO16

81

SWD_UPC_SWDIO0
NC_SWD_UPC_SWDIO1
NC_DFR_TOUCH_INT_L
IPD_SPI_EN
TOUCHID_INT
TOUCHID_PWR_EN
UPC_FORCE_PWR
NC_DFR_PWR_EN
NC_SPI_DFR_CS_L
NC_ENET_SYNC_1588

AJ51
AA50

V53
U53
T53
W53
W50
U52

AC48

R53
R52
N55

AH54

Y52

AA51

R54

AC50

U51

AK50

T52

V49
AJ52
AJ50
AC49

R51
AL49
AF49

GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]

IPU
IPU

IPU
IPU

IPU

GPIO

UART

IPD
IPDIPU

IPU
IPU

UART0_RXD
UART0_TXD

UART1_CTSN
UART1_RTSN

UART1_RXD
UART1_TXD

UART2_CTSN
UART2_RTSN

UART2_RXD
UART2_TXD

UART3_CTSN
UART3_RTSN

UART3_RXD
UART3_TXD

UART4_CTSN
UART4_RTSN

UART4_RXD
UART4_TXD

UART6_RXD
UART6_TXD

UART7_RXD
UART7_TXD

5

IN

5

IN

5

IN

5

IN

5

IN

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4

W49

BOARD_ID0/SOC_DEBUG1

R55

BOARD_ID1/SOC_DEBUG2

T55

BOARD_ID2/SOC_DEBUG3

V55

BOARD_ID3/SPI0_SSIN

U55

BOARD_ID4

BOARD ID

NAND

NAND_SYS_CLK0
NAND_SYS_CLK1

SSD_BFH

SSD_RESETN

AB53
AC53

AC54
AA53
AA54
AC55

W55
Y54
Y53
Y55

AC51
AC52
AF48
AB52

AJ48
AK48
AL52
AL50

AF51
AG50

AM2
AJ2

AG52
AH53

AH51
AG53

UART_DEBUGPRT_D2R
UART_DEBUGPRT_R2D

NC_DFR_1V8_TOUCH_RESET_L
NC_DFR_1V8_DISP_RESET_L
NC_DFR_1V8_DISP_INT
BT_TIME_SYNC_1V8

UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L
UART_WLAN_D2R
UART_WLAN_R2D

NC_UART3_D2R_CTS_L
NC_UART3_R2D_RTS_L

NC_UART3_R2D

NC_UART4_D2R_CTS_L
NC_UART4_R2D_RTS_L
NC_UART4_D2R
NC_UART4_R2D

UART_TCON_D2R
NC_UART_TCON_R2D

NC_UART7_RXD
NC_UART7_TXD

NAND0_CLK24M_0_R
NAND0_CLK24M_1_R

NAND_BFH
NAND0_RESET_L

81

81

81

81

81

81

81

81

81

81

IN

OUT

OUT
OUT

IN
IN

IN

OUT

IN

OUT

IN

OUT

OUT
OUT

OUT
OUT

54

54

80

80

80

60 61

60

60

60

60

80

80

65

65

62 63

7 62 63

1.8V IO

1.8V IO

Use UART2 if your wireless module is 1.2V IO

R2D is for desktop only

NAND0_RESET_L

6263

NOSTUFF

1

R0791

47K

5%
1/20W
MF
201

2

BOM_COST_GROUP=SOC

PAGE TITLE

SOC: AP I/Os

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

7 OF 801

SHEET

7 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

A

D

**OK2INTEGRATE**

SOC: LPDP & MIPI

NC_LPDPRX_AUX0

81

NC_LPDPRX_AUX1

81

NC_LPDPRX_AUX2

81

NC_LPDPRX_AUX3

81

NC_LPDPRX_AUX4

81

NC_LPDPRX_AUX5

81

NC_LPDPRX_AUX6

81

NC_LPDPRX_AUX7

81

NC_LPDPRX_AUX8

81

NC_LPDPRX_AUX9

81

NC_LPDPRX_AUX10

81

NC_LPDPRX_AUX11

81

NC_LPDPRX_RXP0

81

NC_LPDPRX_RXN0

81

NC_LPDPRX_RXP1

81

NC_LPDPRX_RXN1

81

NC_LPDPRX_RXP2

81

NC_LPDPRX_RXN2

81

NC_LPDPRX_RXP3

81

NC_LPDPRX_RXN3

81

NC_LPDPRX_RXP4

81

NC_LPDPRX_RXN4

81

NC_LPDPRX_RXP5

81

NC_LPDPRX_RXN5

81

NC_LPDPRX_RXP6

81

NC_LPDPRX_RXN6

81

NC_LPDPRX_RXP7

81

NC_LPDPRX_RXN7

81

NC_LPDPRX_RXP8

81

NC_LPDPRX_RXN8

81

AP7

LPDPRX_AUX_D0_P

AR7

LPDPRX_AUX_D1_P

AT7

LPDPRX_AUX_D2_P

AV7

LPDPRX_AUX_D3_P

AW7

LPDPRX_AUX_D4_P

AY7

LPDPRX_AUX_D5_P

AP8

LPDPRX_AUX_D6_P

AR8

LPDPRX_AUX_D7_P

AT8

LPDPRX_AUX_D8_P

AV8

LPDPRX_AUX_D9_P

AW8

LPDPRX_AUX_D10_P

AY8

LPDPRX_AUX_D11_P

AP1

LPDPRX_RX_D0_P

AP2

LPDPRX_RX_D0_N

AR1

LPDPRX_RX_D1_P

AR2

LPDPRX_RX_D1_N

AT1

LPDPRX_RX_D2_P

AT2

LPDPRX_RX_D2_N

AV1

LPDPRX_RX_D3_P

AV2

LPDPRX_RX_D3_N

AW1

LPDPRX_RX_D4_P

AW2

LPDPRX_RX_D4_N

AY1

LPDPRX_RX_D5_P

AY2

LPDPRX_RX_D5_N

AP4

LPDPRX_RX_D6_P

AP5

LPDPRX_RX_D6_N

AR4

LPDPRX_RX_D7_P

AR5

LPDPRX_RX_D7_N

AT4

LPDPRX_RX_D8_P

AT5

LPDPRX_RX_D8_N

U0600

TMLR68A0-B09

BGA

SYM 4 OF 23

IPD

LPDP_TX0P
LPDP_TX0N

LPDP_TX1P
LPDP_TX1N

LPDP_TX2P
LPDP_TX2N

LPDP_TX3P
LPDP_TX3N

LPDP_TX4P
LPDP_TX4N

LPDP_TX5P
LPDP_TX5N

LPDP_AUX_P
LPDP_AUX_N

LPDP_RCAL_P
LPDP_RCAL_N

DISP_HPD

DISP_POL

DISP_SPI_MISO/DWI_CLK

DISP_SPI_MOSI/DWI_DO
DISP_SPI_SCLK/DISP_I2C_SCL
DISP_SPI_SSIN/DISP_I2C_SDA

DISP_SPMI_SCLK

DISP_SPMI_SDATA

DISP_FSYNC

DISP_LSYNC

GND_VOID=TRUE

AR55
AR54

AT55
AT54

AU54
AU55

AV55
AV54

AW55
AW54

AY55
AY54

AU52
AU51

AV52
AV51

AG55

AH55

AC6
AC7
AD7
AB6

W4
W3

T49

R50

LPDP_INT_DATA_C_P<0>
LPDP_INT_DATA_C_N<0>

GND_VOID=TRUE
GND_VOID=TRUE

LPDP_INT_DATA_C_P<1>
LPDP_INT_DATA_C_N<1>

GND_VOID=TRUE
GND_VOID=TRUE

LPDP_INT_DATA_C_P<2>
LPDP_INT_DATA_C_N<2>

GND_VOID=TRUE
GND_VOID=TRUE

LPDP_INT_DATA_C_P<3>
LPDP_INT_DATA_C_N<3>

GND_VOID=TRUE

NC_LPDP_TX4P
NC_LPDP_TX4N

NC_LPDP_TX5P
NC_LPDP_TX5N

LPDP_INT_AUX_C_P
LPDP_INT_AUX_C_N

SOC_LPDP_INT_RCAL_POS
SOC_LPDP_INT_RCAL_NEG

LPDP_INT_HPD

NC_DISPLAY_POL

NC_SPI_DISP_BKLT_MISO
NC_SPI_DISP_BKLT_MOSI
I2C_DISP_BKLT_SCL
I2C_DISP_BKLT_SDA

NC_DISP_SPMI_CLK
NC_DISP_SPMI_DATA

NC_DISP_FSYNC

NC_DISP_BKLT_LSYNC

81

81

81

81

8

8

81

81

81

81

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

OUT

BI
BI

U0600

TMLR68A0-B09

BGA

SYM 5 OF 23

NC_ISP_I2C0_SCL

42

BI

81

NC_ISP_I2C0_SDA

81

NC_ISP_I2C1_SCL

81

NC_ISP_I2C1_SDA

81

I2C_CAM_SCL

OUT

I2C_CAM_SDA

BI

NC_ISP_I2C3_SCL

81

NC_ISP_I2C3_SDA

81

FTCAM_RESET_L

OUT

NC_ISP_GPIO1

81

NC_ISP_GPIO2

81

NC_ISP_GPIO3

81

NC_ISP_SPMI0_CLK81
NC_ISP_SPMI0_DATA

81

NC_ISP_SPMI1_CLK

81

NC_ISP_SPMI1_DATA

81

NC_SENSOR0_CLK

81

NC_SENSOR1_CLK

81

NC_SENSOR2_CLK

81

NC_SENSOR3_CLK

81

80

80

41

41

67

67

67

67

67

67

67

67

67

67

67

80

42

7280

IN
OUT
OUT

Y2

ISP_I2C0_SCL/ISP_GPIO_8

Y3

ISP_I2C0_SDA/ISP_GPIO_9

AA5

ISP_I2C1_SCL/ISP_GPIO_10

AA6

ISP_I2C1_SDA/ISP_GPIO_11

AA3

ISP_I2C2_SCL

AA2

ISP_I2C2_SDA

AA7

ISP_I2C3_SCL

AB7

ISP_I2C3_SDA

Y6

ISP_GPIO_0

W6

ISP_GPIO_1

Y7

ISP_GPIO_2

W7

ISP_GPIO_3

AG7

ISP_SPMI0_SCLK/ISP_GPIO_5

AF7

ISP_SPMI0_SDATA/ISP_GPIO_4

AG6

ISP_SPMI1_SCLK/ISP_GPIO_7

AH7

ISP_SPMI1_SDATA/ISP_GPIO_6

AD1

SENSOR0_CLK

AE1

SENSOR1_CLK

AD3

SENSOR2_CLK

AF1

SENSOR3_CLK

ISP SPMI

MIPI0C_DPCLK
MIPI0C_DNCLK

MIPI0C_DPDATA0
MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPID_DPCLK
MIPID_DNCLK

MIPID_DPDATA0
MIPID_DNDATA0

MIPI_D

MIPI0C_REXT
MIPI1C_REXT

MIPID_REXT

L15

NC_MIPI0C_CLKP

L14

NC_MIPI0C_CLKN

K15

NC_MIPI0C_DATAP0

K14

NC_MIPI0C_DATAN0

M14

NC_MIPI0C_DATAP1

M15

NC_MIPI0C_DATAN1

GND_VOID=TRUE

L11

MIPI_FTCAM_CLK_P

L12

MIPI_FTCAM_CLK_N

GND_VOID=TRUE

M12

MIPI_FTCAM_DATA_P<0>

M11

MIPI_FTCAM_DATA_N<0>

GND_VOID=TRUE

K11

NC_MIPI_FTCAM_DATA1P

K12

NC_MIPI_FTCAM_DATA1N

GND_VOID=TRUE

GND_VOID=TRUE

K9

NC_MIPI_DFR_CLKP

K8

NC_MIPI_DFR_CLKN

GND_VOID=TRUE
GND_VOID=TRUE

L9

NC_MIPI_DFR_DATAP

L8

NC_MIPI_DFR_DATAN

GND_VOID=TRUE

K17
L17

SOC_MIPI1C_REXT

M9

GND

GND_VOID=TRUE

GND_VOID=TRUE

81

81

81

81

81

81

66

IN

66

IN

66

IN

66

IN

80

IN

80

IN

80

OUT

80

OUT

80

OUT

80

OUT

8

8

NC_LPDPRX_RXP9

81

NC_LPDPRX_RXN9

81

NC_LPDPRX_RXP10

81

NC_LPDPRX_RXN10

81

NC_LPDPRX_RXP11

81

NC_LPDPRX_RXN11

81

NO_TEST=1

NC_LPDPRX0_RCAL_POS
NC_LPDPRX0_RCAL_NEG

NO_TEST=1
NO_TEST=1

NC_LPDPRX1_RCAL_POS
NC_LPDPRX1_RCAL_NEG

NO_TEST=1

AV4

LPDPRX_RX_D9_P

AV5

LPDPRX_RX_D9_N

AW4

LPDPRX_RX_D10_P

AW5

LPDPRX_RX_D10_N

AY4

LPDPRX_RX_D11_P

AY5

LPDPRX_RX_D11_N

AU1

LPDPRX0_RCAL_P

AU2

LPDPRX0_RCAL_N

AU4

LPDPRX1_RCAL_P

AU5

LPDPRX1_RCAL_N

DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1

DISP_TOUCH_EB

DFR_BSYNC/DISP_INT

DFR_DISP_TE

T50
R49
U49

AM5

AL51

NC_DISP_TOUCH_BSYNC0
NC_DISP_TOUCH_BSYNC1
NC_DISP_TOUCH_EB

NC_BKLT_FAULT_INT_L

NC_DFR_DISP_TE

81

81

81

80

IN

80

IN

SOC_MIPI1C_REXT

8

GND

8

PLACE_NEAR=U0600.K17:6MM
PACK_IGNORE=TRUE
PACK_OPTION=DFR

1

R0800

200

1%

2

1/20W
MF
201

MAKE_BASE=TRUE MAKE_BASE=TRUE

PACK_OPTION=NO_FTCAMPACK_OPTION=NO_DFR

PLACE_NEAR=U0600.L17:6MM
PACK_OPTION=FTCAM

1

R0820

200

1%
1/20W
MF
201

2

SOC_LPDP_INT_RCAL_POS

8

SOC_LPDP_INT_RCAL_NEG

8

1

R0895

200

1%
1/20W
MF
201

2

1

C0895

10PF

5%
25V

2

C0G
0201

BOM_COST_GROUP=SOC

SYNC_MASTER=ref_soc_h13g SYNC_DATE=05/04/2020

PAGE TITLE

SOC: LPDP & MIPI

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

8 OF 801

SHEET

8 OF 92

1

A

**OK2INTEGRATE**

SOC: PCIE

78 12 7 6 5

80 9

PP1V25_AWAKE_IO

NAND0_CLKREQ1_L

965

WLBT_CLKREQ_L

96061

NAND0_CLKREQ0_L

965

NC_ENET_CLKREQ_L
USBHC_CLKREQ_L

9

PER PCISIG SPEC, AC COUPLING CAPS SHOULD BE BETWEEN
75 NF AND 265 NF FOR GEN1/2 AND BETWEEN

176 NF AND 265 NF FOR GEN 3/4

R0970 IS NEEDED DUE TO RDAR://53793006

1

R0930

47K

5% 5%
1/20W
MF

2

1

R0940

47K

1/20W
MF
201

2

1

R0950

47K

5%
1/20W
MF
201201

2

1

R0960

47K

5%
1/20W
MF
201

2

PACK_IGNORE=TRUE
PACK_OPTION=ENET

1

R0970

47K

5%
1/20W
MF
201

2

U0600

TMLR68A0-B09

BGA

SYM 6 OF 23

GND_VOID=TRUE

62

IN

62

IN

62

OUT

62

OUT

62

OUT

62

OUT

965

BI

962

OUT

63

63

IN

63

IN

63

OUT

63

OUT

63

OUT

63

OUT

PCIE_NAND0_D2R_P<0>
PCIE_NAND0_D2R_N<0>

PCIE_NAND0_R2D_C_P<0>
PCIE_NAND0_R2D_C_N<0>

PCIE_CLK100M_NAND0_0_P
PCIE_CLK100M_NAND0_0_N

NAND0_CLKREQ0_L

NAND0_PCIE_RESET_L

PCIE_NAND0_D2R_P<1>
PCIE_NAND0_D2R_N<1>

PCIE_NAND0_R2D_C_P<1>
PCIE_NAND0_R2D_C_N<1>

PCIE_CLK100M_NAND0_1_P
PCIE_CLK100M_NAND0_1_N

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

BE26
BF26

BC27
BD27

BB37
BC37

AH50

AH52

BE28
BF28

BC29
BD29

BB38
BC38

ST_PCIE_RX0_P
ST_PCIE_RX0_N

ST_PCIE_TX0_P
ST_PCIE_TX0_N

ST_PCIE_REF_CLK0_P
ST_PCIE_REF_CLK0_N

ST_PCIE_CLKREQ0_N

ST_PCIE_PERST0_N

ST_PCIE_RX1_P
ST_PCIE_RX1_N

ST_PCIE_TX1_P
ST_PCIE_TX1_N

ST_PCIE_REF_CLK1_P
ST_PCIE_REF_CLK1_N

GP_PCIE_RX0_P
GP_PCIE_RX0_N

GP_PCIE_TX0_P
GP_PCIE_TX0_N

GP_PCIE_REF_CLK0_P
GP_PCIE_REF_CLK0_N

GP_PCIE_CLKREQ0_N

GP_PCIE_PERST0_N

GP_PCIE_RX1_P
GP_PCIE_RX1_N

GP_PCIE_TX1_P
GP_PCIE_TX1_N

GP_PCIE_REF_CLK1_P
GP_PCIE_REF_CLK1_N

GND_VOID=TRUE

BE30
BF30

BC31
BD31

BE40
BF40

AB55

AA52

BE32
BF32

BC33
BD33

BE38
BF38

PCIE_WLBT_D2R_P
PCIE_WLBT_D2R_N

GND_VOID=TRUE
GND_VOID=TRUE

PCIE_WLBT_R2D_C_P
PCIE_WLBT_R2D_C_N

GND_VOID=TRUE

PCIE_CLK100M_WLBT_P
PCIE_CLK100M_WLBT_N

WLBT_CLKREQ_L

WLBT_RESET_L

GND_VOID=TRUE

NC_PCIE_USBHC_D2RP
NC_PCIE_USBHC_D2RN

GND_VOID=TRUE
GND_VOID=TRUE

NC_PCIE_USBHC_R2DCP
NC_PCIE_USBHC_R2DCN

GND_VOID=TRUE

NC_PCIE_CLK100M_USBHCP
NC_PCIE_CLK100M_USBHCN

IN
IN

OUT
OUT

OUT
OUT

BI

OUT

IN
IN

OUT
OUT

OUT
OUT

60

60

60

60

60

60

9 60 61

9 60 61

80

80

80

80

80

80

TO BE CHECKED WITH SEG- DO NOT MATCH WITH SILVAL

IS THE PULL-UP VOLTAGE CORRECT?

965

BI

NAND0_CLKREQ1_L

NC_NAND0_PCIE_RESET1_L

81

AH49

AH48

ST_PCIE_CLKREQ1_N

ST_PCIE_PERST1_N

GP_PCIE_CLKREQ1_N

GP_PCIE_PERST1_N

GP_PCIE_RX2_P
GP_PCIE_RX2_N

GP_PCIE_TX2_P
GP_PCIE_TX2_N

GP_PCIE_REF_CLK2_P
GP_PCIE_REF_CLK2_N

GP_PCIE_CLKREQ2_N

GP_PCIE_PERST2_N

AA55

P55

BE34
BF34

BC35
BD35

BE39
BF39

AH1

AE7

USBHC_CLKREQ_L

NC_USBHC_RESET_L

GND_VOID=TRUE

NC_PCIE_ENET_D2RP
NC_PCIE_ENET_D2RN

GND_VOID=TRUE
GND_VOID=TRUE

NC_PCIE_ENET_R2DCP
NC_PCIE_ENET_R2DCN

GND_VOID=TRUE

NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_ENETN

NC_ENET_CLKREQ_L

NC_ENET_RESET_L

BI

OUT

IN
IN

OUT
OUT

OUT
OUT

BI

OUT

9

9 80

80

80

80

80

80

80

9 80

9 80

SOC_ST_PCIE_RCAL_POS

9

SOC_ST_PCIE_RCAL_NEG

9

SOC_GP_PCIE_RCAL_POS

9

SOC_GP_PCIE_RCAL_NEG

9

1

R0990

200

1%
1/20W
MF
201

2

1

C0990

10PF

5%
25V

2

C0G
0201

1

R0991

200

1%
1/20W
MF
201

2

1

C0991

10PF

5%
25V

2

C0G
0201

NC_USBHC_RESET_L

80 9

NC_ENET_RESET_L

80 9

NAND0_PCIE_RESET_L

96263

WLBT_RESET_L

96061

SOC_ST_PCIE_RCAL_POS

9 9

SOC_ST_PCIE_RCAL_NEG

9

NC_PAD_MTR_ANALOG_TEST_POS

81

NC_PAD_MTR_ANALOG_TEST_NEG

81

NC_PAD_MTR_VREF_POS

81

NC_PAD_MTR_VREF_NEG

81

1

R0941

47K

5%
1/20W
MF
201

2

1

R0951

47K

5%
1/20W
MF
201

2

1

R0961

47K

5%
1/20W
MF
201

2

PACK_IGNORE=TRUE
PACK_OPTION=ENET

BC24
BB24

AM3
AL3

AL1
AM1

ST_PCIE_RCAL_P
ST_PCIE_RCAL_N

PAD_MTR_ANALOG_TEST_P
PAD_MTR_ANALOG_TEST_N

PAD_MTR_VREF_P
PAD_MTR_VREF_N

1

R0971

47K

5%
1/20W
MF
201

2

PACK_IGNORE=TRUE
PACK_OPTION=USBHC

GP_PCIE_RCAL_P
GP_PCIE_RCAL_N

BC25
BB25

SOC_GP_PCIE_RCAL_POS
SOC_GP_PCIE_RCAL_NEG

9

SYNC_MASTER=ref_soc_h13g SYNC_DATE=05/04/2020

PAGE TITLE

SOC: PCIE

SIZE

D

BOM_COST_GROUP=SOC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

9 OF 801

SHEET

9 OF 92

2

1

568

**OK2INTEGRATE**

72

IN

output if gyro, input for radar

LID_OPEN

MAKE_BASE=TRUE

I2C0 is ALS for portables

PACK_OPTION=HAS_LID

AOP, NUB, and SMC GPIO's are referenced to PP1V25_S2_AOP

NC_AOP_FUNC0

80

NC_AOP_FUNC1

81

NC_AOP_FUNC2

80

NC_AOP_FUNC3

80

NC_SPI_R1_CS_L

80

NC_AOP_FUNC5

81

49

OUT

49

IN

49

IN

SPI_GYRO_CS_L
GYRO_INT
GYRO_MOTION_INT
LID_OPEN
NC_AOP_FUNC10

81

6061

OUT

6061

OUT

80

IN

42

OUT

42

BI

42

OUT

42

BI

72

72

WLAN_CONTEXT_A
WLAN_CONTEXT_B
NC_ALS_INT_L
NC_AOP_FUNC14

81

I2C_AOP_ALS_SCL
I2C_AOP_ALS_SDA

NC_I2C_AOP_ENET_SCL
NC_I2C_AOP_ENET_SDA

NC_PDM_CLK1

81

NC_PDM_CLK2

81

PDM_DMIC_CLK3

OUT

PDM_DMIC_CLK4

OUT

NC_PDM_CLK5

81

NC_PDM_CLK6

81

BB18
BC16
BC12
BC13
BA16
BA13
BA15
BD13
BD16
BA14
BB12
BD20
BA11
BD18
BA10

BC20
BB19

BB16
BE15

BB9
BC9
BC6
BD9
BC8
BD8

AOP_FUNC[0]
AOP_FUNC[1]
AOP_FUNC[2]
AOP_FUNC[3]
AOP_FUNC[4]
AOP_FUNC[5]
AOP_FUNC[6]
AOP_FUNC[7]
AOP_FUNC[8]
AOP_FUNC[9]

IPD

AOP_FUNC[10]
AOP_FUNC[11]
AOP_FUNC[12]
AOP_FUNC[13]
AOP_FUNC[14]

AOP_I2CM0_SCL
AOP_I2CM0_SDA

AOP_I2CM1_SCL
AOP_I2CM1_SDA

AOP_PDM_IN_CLK1/AOP_I2S1_BCLK
AOP_PDM_IN_CLK2/AOP_I2S0_MCK
AOP_PDM_IN_CLK3/AOP_I2S0_LRCK
AOP_PDM_IN_CLK4/AOP_I2S0_DOUT
AOP_PDM_IN_CLK5/AOP_I2S0_DIN
AOP_PDM_IN_CLK6/AOP_I2S0_BCLK

SOC: AOP

U0600

TMLR68A0-B09

BGA

SYM 7 OF 23

AOP GPIO

NUB GPIO

AOP I2C

NUB SPMI

NUB SWD

AOP PDM

NUB_CLK_OUT0

NUB_DOCK_ATTENTION/CTM_TRIGGER

NUB_DOCK_CONNECT

NUB_GPIO_0/AOP_FUNC15/NUB_CLK_OUT1

NUB_GPIO_1/AOP_PDM_IN_CLK0
NUB_GPIO_2/AOP_PDM_IN_DATA0
NUB_GPIO_3/AOP_LEAP_MADI_IN

IPU

NUB_GPIO_4/AOP_LEAP_MADI_OUT

NUB_GPIO_5/AOP_PDM_OUT_CLK0

NUB_GPIO_6/AOP_PDM_OUT_DATA0/AOP_FUNC16

NUB_GPIO_7/AOP_FUNC17
NUB_GPIO_8/AOP_FUNC18
NUB_GPIO_9/AOP_FUNC19

NUB_GPIO_10/AOP_FUNC20
NUB_GPIO_11/KIS_GPIO0/AOP_FUNC21
NUB_GPIO_12/KIS_GPIO1/AOP_FUNC22

NUB_SPMI0_SCLK

NUB_SPMI0_SDATA

NUB_SPMI1_SCLK

NUB_SPMI1_SDATA

NUB_SWD_TCK_OUT0

NUB_SWD_TMS0
NUB_SWD_TMS1

BA17
BC15
BC17

BD14
BD15
BD21
BD17
BB13
BD19
BD22
BB10
BD12
BD11
BC10
BB7
BD10

BB15
BC14

BA12
BC11

BC18
BC19
BC21

NC_DFR_TOUCH_CLK32K_RESET_L
TPT_SOC_DOCK_ATTENTION
SOC_DOCK_CONNECT

NC_BKLT_PWR_ON
CODEC_RESET_L
SOC_SW_DBG
IPD_SPI_INT_L
SMC_FIXTURE_MODE_L
CHGR_INT_L
NC_CCG_SMC_I2C_INT_L
NC_ACDC_ID
NC_ACDC_BURST_EN_L
NC_SPI_DP2HDMI_HOLD_L
NC_HDMI_CEC_AOP_TX
NC_HDMI_CEC_AOP_RX
NC_HDMI_HPD_AOP

SPMI_NUB_MPMU_CLK_R
SPMI_NUB_MPMU_DATA_R

SPMI_NUB_SPMU_CLK_R
SPMI_NUB_SPMU_DATA_R

SWD_NUB_SWCLK
SWD_NUB_PMU_SWDIO
NC_NUB_SWD_TMS1

80

OUT

20

10 80

IN

80

OUT

50

OUT

82

OUT

80

IN

20

IN

80

IN

80

IN

80

IN

80

OUT

80

OUT

80

OUT

80

IN

80

IN

20

OUT

20

BI

20

OUT

20

BI

30 34

OUT

30 34

BI

80

DOC_ATTENTION should be a TP
for non dev programs,

SOC_SW_DBG SHOULD GO TO
A LED IF POSSIBLE.
NEEDS A TEST POINT AT MINIMUM

FIXTURE_MODE_L should be aliased to a TP
for non dev programs,
The TP is required

1080

SOC_DOCK_CONNECT

R1066

47K

5%

1/20W

MF

201

1

2

78 12 10

6347282

IN

PP1V25_S2

PMU_RESET_L

R1083

10K

5%

1/20W

MF

201

NC_PDM_DATA1

81

NC_PDM_DATA2

81

IPD

72

IPD

72

20

IN

20

OUT

20

OUT

PDM_DMIC_DATA3

IN

PDM_DMIC_DATA4

IN

SPI_AOP_GYRO_MISO
SPI_AOP_GYRO_MOSI_R
SPI_AOP_GYRO_CLK_R

CKPLUS_WAIVE=CLK_DATA_CON
CKPLUS_WAIVE=CLK_DATA_CON

BE21
BE16
BE19

BD5

BF15
BF14
BF17

AOP_PDM_IN_DATA1/AOP_I2S1_MCK
AOP_PDM_IN_DATA2/AOP_I2S1_LRCK
AOP_PDM_IN_DATA3/AOP_I2S1_DOUT/AOP_PDM_IN_CLK7
AOP_PDM_IN_DATA4/AOP_I2S1_DIN/AOP_PDM_IN_CLK8

AOP_SPI0_MISO
AOP_SPI0_MOSI
AOP_SPI0_SCLK

AOP SPI

JTAG

IPU
IPU

IPU
IPD

JTAG_SEL
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRSTN

SMC_I2CM0_SCL

NC_AOP_SPMI0_SCLK

81

NC_AOP_SPMI0_SDATA

81

20

OUT

20

BI

SPMI_SE_CLK_R
SPMI_SE_DATA_R

BF18
BF19

BF20
BF21

AOP_SPMI0_SCLK/AOP_UART0_TXD
AOP_SPMI0_SDATA/AOP_UART0_RXD

AOP_SPMI1_SCLK/AOP_UART1_TXD
AOP_SPMI1_SDATA/AOP_UART1_RXD

AOP SPMI

SMC_I2CM0_SDA

SMC_I2CM1_SCL/SMC_UART1_TXD
SMC_I2CM1_SDA/SMC_UART1_RXD

SMC_I2CM2_SCL

NC_AOP_UART2_D2R

81

NC_AOP_UART2_R2D

81

BB3

AOP_UART2_RXD

BB4

AOP_UART2_TXD

AOP UART

SMC I2C

SMC_I2CM2_SDA

SMC_I2CM3_SCL
SMC_I2CM3_SDA

1

2

34

PMU_CLK32K_SOC

IN

BE6

BF10

BB5

RT_CLK32768

CFSB_AON

COLD_RESETN

AOP RESET

SMC UART

IPU

SMC_I2CM4_SCL
SMC_I2CM4_SDA

SMC_UART0_RXD
SMC_UART0_TXD

BE4
BF5
BF16
BC1
BB1
BF7

BC3
BC2

BD4
BB2

BD6
BC5

BC7
BD7

BE7
BF9

BF4
BF8

SOC_JTAG_SEL
SWD_SOC_SWCLK
TPT_JTAG_SOC_TDI
TPT_JTAG_SOC_TDO
SWD_SOC_SWDIO
TPT_JTAG_SOC_TRST_L

I2C_SMC_PWR_SCL
I2C_SMC_PWR_SDA

I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA

NC_I2C_SMC_SNS1_SCL
NC_I2C_SMC_SNS1_SDA

I2C_SMC_IPD_SCL
I2C_SMC_IPD_SDA

NC_I2C_SMC_SNS0_SCL
NC_I2C_SMC_SNS0_SDA

UART_SMC_DEBUGPRT_D2R
UART_SMC_DEBUGPRT_R2D

5

IN

54

IN

20

20

54

BI

20

43

OUT

43

BI

43

OUT

43

BI

43

OUT

43

BI

43

OUT

43

BI

43

OUT

43

BI

54

IN

54

OUT

78 12 10

PP1V25_S2

81

34

OUT

XW1022

SHORT-14L-0.1MM-SM

21

58

BI

58

BI

NC_AON_SLEEP1_RESET_L

SOC_WDOG

SOC_DBG_PROBE_VALID

EUSB_DBG_P
EUSB_DBG_N

SOC_USBDBG_RESREF

1

R1042

200

1%
1/20W
MF
201

2

BB21

BF12

BF6

BF24
BE24

BE23

AON_SLEEP1_RESETN

WDOG

DBG_PROBE_VALID

DBG_USB_EDP
DBG_USB_EDM

DBG_USB_RESREF

AOP DEBUG

SMC GPIO

IPU

SMC_GPIO0
SMC_GPIO1

SMC_FPWM0
SMC_FPWM1

BF11
BF13

BE12
BE9

UPC_SMC_I2C_INT_L
NC_SMC_GPIO1

NC_SMC_FAN_PWM_SMC_SIL_LED_PWM
NC_SMC_FAN_TACH

43

IN

81

80

OUT

80

IN

BOM_COST_GROUP=SOC

SYNC_MASTER=ref_soc_h13g SYNC_DATE=05/04/2020

PAGE TITLE

SOC: AOP

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

10 OF 801

SHEET

10 OF 92

1

2

1

**OK2INTEGRATE**

78 18 11

PP1V8_S2SW_VDD1

18

PP1V2_AWAKE_PLL

78

78 18 11

PP0V6_S1_VDDQL

DDR0_ZQ

11

DDR1_ZQ

11

DDR4_ZQ

11

DDR5_ZQ

11

CRITICAL

1

C1100

1.0UF

20%
4V

2

X6S
0201 0201 0201

1

2

1

C1113

0.22UF

20%

6.3V

2

X6S-CERM

PP1V06_S2SW_DRAM

1

R1161

240

1%
1/20W
MF
201

2

PLACE_NEAR=U0600.A5:5MM
PLACE_NEAR=U0600.A7:5MM
PLACE_NEAR=U0600.A33:5MM
PLACE_NEAR=U0600.A35:5MM

CRITICAL

C1101

1.0UF

20%
4V
X6S

1

2

1

C1112

0.1UF

10%

6.3V

2

X6S
0201

1

C1111

2.2UF

20%
4V

2

X6S-CERM
0201

1

R1162

240

1%
1/20W
MF
201

2

CRITICAL

C1102

1.0UF

20%
4V
X6S

C1105

11UF

1

1

R1163

240

1%
1/20W
MF
201

2

1

C1103

12PF

5%
25V

2

NP0-C0G

C1106

20%

2.5V
X6T

0402 0402

3

4

2

1

C1110

0.1UF

10%

6.3V

2

X6S
02010201

1

C1115

1.0UF

20%
4V

2

X6S
0201

DDR0_RREF

11

DDR1_RREF

11

DDR2_RREF

11

DDR3_RREF

11

DDR4_RREF

11

DDR5_RREF

11

DDR6_RREF

11

DDR7_RREF

11

DDR0_ZQ

11

DDR1_ZQ

11

DDR4_ZQ

11

DDR5_ZQ

11

DDR0_ZQ1

11

DDR1_ZQ1

11

DDR4_ZQ1

11

DDR5_ZQ1

11

11UF

20%

2.5V
X6T

1

2

1

R1164

240

1%
1/20W
MF
201

2

3

4

1

2

C1107

1

1

C1114

0.01UF

10%
25V

2

X7R
0201

C1104

3PF

+/-0.1PF
25V
C0G
0201

11UF

20%

2.5V
X6T

0402

3

4

2

1

R1165

240

1%
1/20W
MF
201

2

D21
D22
D48
D49

D7

D8
E21
E35
E48

E8
D34
D35

AJ19
AG19
AE13

T25

AA29

Y31
T33

AC43

AJ14
AH14
AC14

R25
T29
T30
T36

AA42

J1

H1

G1
A26
A31
A32
G55
H55

A5

A7
A33
A35

A6

A8
A34
A36

1

R1166

240

1%
1/20W
MF
201

2

SOC: POWER (DDR,SRAM)

U0600

TMLR68A0-B09

BGA

SYM 9 OF 23

VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2

VDDIO12_PLL_DDR0
VDDIO12_PLL_DDR1
VDDIO12_PLL_DDR2
VDDIO12_PLL_DDR3
VDDIO12_PLL_DDR4
VDDIO12_PLL_DDR5
VDDIO12_PLL_DDR6
VDDIO12_PLL_DDR7

VDDIO11_RET_DDR0_S2
VDDIO11_RET_DDR1_S2
VDDIO11_RET_DDR2_S2
VDDIO11_RET_DDR3_S2
VDDIO11_RET_DDR4_S2
VDDIO11_RET_DDR5_S2
VDDIO11_RET_DDR6_S2
VDDIO11_RET_DDR7_S2

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF
DDR4_RREF
DDR5_RREF
DDR6_RREF
DDR7_RREF

DDR0_ZQ[0]
DDR1_ZQ[0]
DDR4_ZQ[0]
DDR5_ZQ[0]

DDR0_ZQ[1]
DDR1_ZQ[1]
DDR4_ZQ[1]
DDR5_ZQ[1] VDD2_S2

1

R1167

240

1%
1/20W
MF
201

2

1

R1168

240

1%
1/20W
MF
201

2

VDD2_S2
VDD2_S2

VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2

B30
B31

B52
F23
F25
F50
F52
G24
G26
G51
G53
H23
H25
H50
H52
J24
J26
J51
J53
P5
P24
P32
P51
B4
B3
B25
B26
B53
F4
F6
F31
F33
G3
G5
G30
G32
H4
H6
H31
H33
J3
J5
J30
J32
P6
P23
P33
P50

PP1V06_S2SW_DRAM

3

3

C1121

4.3UF

20%

2.5V
X6T

0402

1

2

C1126

4.3UF

20%

2.5V
X6T

0402

1

2

C1120

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1125

4.3UF

20%

2.5V
X6T

0402

1

4

2

TABLE_ALT _HEAD

PART NUMBER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT _ITEM

138S00138 ALL 4.7UF 20% 4V 0201138S00139

TABLE_ALT _ITEM

138S00138138S00164 ALL 4.7UF 20% 4V 0201

PP0V6_S1_VDDQL78 18 11

1

U0600

TMLR68A0-B09

781811

AA14
AA16
AA40
AB15
AB41
AC16
AC40
AD15
AE16
AF15
AG14
AH15
AK15
AL14
AL16
AM15
AM17

3

3

C1123

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1128

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1122

4.3UF

20%

2.5V
X6T

0402

3

4

4

2

C1127

4.3UF

20%

2.5V
X6T

0402

1

3

4

4

2

3

3

C1124

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1129

4.3UF

20%

2.5V
X6T

0402

1

4

2

3

3

B21
B23
B33
B35
B50

B6

B8
C22
C24

C3
C32
C34
C49

C5
C51
C53

C7
D23
D25
D31
D33

D4
D50
D52

D6
E24
E26

E3
E30
E32
E51
E53
K24
K26

K3
K30
K32

K5
K51

VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1

BGA

SYM 8 OF 23

VDDQL S1

VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1

K53
L23
L25
L31
L33
L4
L50
L52
L6
M24
M26
M3
M30
M32
M5
M51
M53
N25
N31
N4
N52
T16
T18
T20
T22
T26
T28
T32
T38
T40
U14
U15
U17
U19
U21
U23
U25
U27
U29
U31
U33
U35
U37
U39
V16
V22
V24
V26
V32
V34
V40
W14
W40
Y15

C1150

12PF

25V

2

NP0-C0G
0201

C1133

4.3UF

20%

2.5V
X6T

0402

1

2

C1140

4.3UF

20%

2.5V
X6T

0402

1

2

3

4

3

4

1

2

C1134

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1141

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1151

3PF

+/-0.1PF
25V0201
C0G
0201

C1131

4.3UF

2.5V
0402

1

2

C1135

4.3UF

2.5V
0402

1

3

2

C1142

4.3UF

2.5V
0402

1

3

2

20%
X6T

20%
X6T

20%
X6T

C1132

4.3UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

C1136

4.3UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

B

3

4

78 18 11

DDR0_ZQ1

11

DDR1_ZQ1

11

DDR4_ZQ1

11

DDR5_ZQ1

11

PP0V6_S1_VDDQL

DDR0_RREF

11

DDR1_RREF

11

DDR2_RREF

11

DDR3_RREF

11

DDR4_RREF

11

DDR5_RREF

11

DDR6_RREF

11

DDR7_RREF

11

PLACE_NEAR=U0600.A6:5MM
PLACE_NEAR=U0600.A8:5MM
PLACE_NEAR=U0600.A34:5MM
PLACE_NEAR=U0600.A36:5MM

1

R1169

240

1%
1/20W
MF
201

2

PLACE_NEAR=U0600.J1:5MM
PLACE_NEAR=U0600.H1:5MM
PLACE_NEAR=U0600.G1:5MM
PLACE_NEAR=U0600.A26:5MM
PLACE_NEAR=U0600.A31:5MM
PLACE_NEAR=U0600.A32:5MM
PLACE_NEAR=U0600.G55:5MM
PLACE_NEAR=U0600.H55:5MM

1

R1170

240

1%
1/20W
MF
201

2

1

R1171

240

1%
1/20W
MF
201

2

1

R1172

240

1%
1/20W
MF
201

2

1

R1173

240

1%
1/20W
MF
201

2

1

R1174

240

1%
1/20W
MF
201

2

1

R1175

240

1%
1/20W
MF
201

2

1

R1176

240

1%
1/20W
MF
201

2

BOM_COST_GROUP=SOC

PAGE TITLE

SOC: POWER (DDR,SRAM)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

11 OF 801

SHEET

11 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

D

2

1

8

**OK2INTEGRATE**

Internally generated rail

PP0V6_S2_GRP1

4UF

20%

2.5V
X6S

0201

1

2

C1200

VOLTAGE=0.6V

PP0V6_S2_GRP2

C1201

4UF

20%

2.5V
X6S

0201

SOC: POWER (IO)

VOLTAGE=0.6V

1

2

78 10

PP1V25_S2

PP1V25_S2

78

desense recomends an additional 3 pF cap on PP1v25_awake_grp3
J313 can't fit it so it should go on a project specific page

78 9 7 6 5

PP1V25_AWAKE_IO

20%

6.3V
0402

1

2

C1233

10UF

CER-X6S

XW1232

SM

21

C1232

2.2UF

20%

4V

X6S-CERM

0201

1

C1213

2.2UF

20%
4V

2

X6S-CERM
0201 0201

XW1231

SM

C1231

2.2UF

20%

4V

X6S-CERM

0201

21

1

2

VOLTAGE=1.25V

PP1V25_AWAKE_GRP4

C1236

NP0-C0G

PP1V25_AWAKE_GRP5

1

2

1

C1210

2.2UF

20%
4V

2

X6S-CERM

12PF

5%

25V

0201

1

2

1

C1211

0.1UF

10%

6.3V

2

X6S
0201

C1234

2.2UF

X6S-CERM

0201

XW1230

SM

C1237

3PF

+/-0.1PF

25V
C0G

0201

VOLTAGE=1.25V

20%

4V

1

C1241

12PF

2

VOLTAGE=1.25V

21

PP1V25_AWAKE_GRP3

C1230

2.2UF

1

2

X6S-CERM

NP0-C0G

20%

4V

0201

25V

0201

1

2

C1238

12PF

25V

NP0-C0G

0201

5%

1

C1242

2

C1235

NP0-C0G

1

2

3PF

+/-0.1PF

25V
C0G

0201

12PF

5%

25V

0201

C1239

3PF

+/-0.1PF

0201

1

2

25V
C0G

U0600

TMLR68A0-B09

BGA

SYM 14 OF 23

AR40
AP40

BB22

AY23

1

2

1

2

AY25
AY27
BA24
BA26

AP39

AF41
AG42
AH40
AL40
AN40

AT40
AV40

AP16
AR17
AT16
AU17
AV16
AW17

VDD06_GRP1_S2
VDD06_GRP2_S2 VDD2_S2_SENSE2

VDDDIO_HIB_S4

VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_S2

VDDIO12_GRP1_S2

VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3

VDDIO12_GRP4
VDDIO12_GRP4

VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5

VDD2_S2_SENSE1

VDD_PCPU_SENSE
VDD_ECPU_SENSE

VDD_GPU_SENSE

VDD_SOC_S1_SENSE

VDD_DISP_S1_SENSE

VDD_DCS_SENSE

VDDQL_SENSE

VSS_PCPU_SENSE

VSS_DDR_SENSE

VSS_SENSE1

VSS_SENSE2

B10
B37

AD36
AN23
AC23
AH22
Y17
AN17
AN15

AD37
AN16
B9
B36

VSNS_VDD2_1
VSNS_VDD2_2

VSNS_VDD_PCPU
VSNS_VDD_ECPU
VSNS_VDD_GPU
VSNS_VDD_SOC
VSNS_VDD_DISP
VSNS_VDD_DCS
VSNS_VDDQL

VSNS_VSS_PCPU
VSNS_VSS_DDR
VSNS_VSS_1
VSNS_VSS_2

47

47

47

47

47

47

47

47

47

47

47

47

47

PP1V8_AWAKE

78

C1243

12PF

5%

25V

NP0-C0G

0201

1

2

C1244

3PF

+/-0.1PF

25V
C0G

0201

AP41
AR41

1

C1240

2.2UF

2

X6S-CERM

20%

4V

0201

1

2

VDDIO18_GRP1
VDDIO18_GRP1

BOM_COST_GROUP=SOC

PAGE TITLE

SOC: POWER (IO)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

12 OF 801

SHEET

12 OF 92

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

D

**OK2INTEGRATE**

3458

SOC: POWER (CPU, GPU)

78 18 13

C1310

11UF

20%

2.5V
X6T

0402

1

4

2

C1318

11UF

20%

2.5V
X6T

0402

1

3

3

C1311

11UF

20%

2.5V
X6T

0402

1

4

2

C1312

11UF

1

3

2

C1319

11UF

20%

2.5V
X6T

0402

1

PPVDD_PCPU_AWAKE

C1300

+/-0.1PF

C1313

11UF

20%

2.5V
X6T

0402

3

3

4

20%

2.5V
X6T

0402

1

4

2

3PF

25V
C0G

0201

3

1

2

C1301

C1314

11UF

20%

2.5V
X6T

0402

1

4

2

12PF

NP0-C0G

3

1

5%

25V

2

0201

C1315

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1316

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1317

11UF

20%

2.5V
X6T

0402

1

4

2

0.575V @ 4400MA

U0600

TMLR68A0-B09

BGA

SYM 11 OF 23

AE33
AE35
AE36
AE37
AF33
AF36
AF39
AG34
AG38
AH34
AH39
AJ33
AJ34
AK29
AK33
AK35
AK36
AK38
AK40
AK41
AK42
AK43
AK44
AK45
AK46
AL30
AL32
AL37
AL41
AL42
AL43
AL44
AL45
AL46
AM29
AM34
AM38
AM41
AM42
AM43
AM44
AM45
AM46
AM47
AM48
AM49
AM50
AM51
AM52
AM53
AM54
AM55
AN33
AN34
AN38
AN42
AN43
AN44
AN45
AN46
AN47
AN48
AN49
AN50
AN51

3

AN52
AN53
AN54
AN55
AP29
AP33
AP38
AP43
AP44

VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU

VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU

VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU

VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1

AP45
AP46
AP47
AP48
AP49
AP50
AP51
AP52
AR30
AR32
AR33
AR35
AR36
AR37
AR39

AK25
AL26
AL28
AL29
AN24
AN29
AP25
AR26
AR28

AB23
AC33
AC38
AE23
AE32
AE38
AF28
AG23
AG39
AJ20
AJ22
AJ24
AJ26
AJ28
AJ30
AJ32
AL20
AL22
AL24
AM39
AN18
AN20
AN22
AR18
AR22
AR24
AT33
AT35
AT37
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU38
Y21
Y26
Y36

PPVDD_PCPU_AWAKE

PPVDD_ECPU_AWAKE

C1320

11UF

20%

2.5V
X6T

0402

1

4

2

PPVDD_SOC_S1

C1330

11UF

20%

2.5V
X6T

0402

1

2

C1334

11UF

20%

2.5V
X6T

0402

1

4

2

4

3

C1331

1

3

C1335

11UF

20%

2.5V
X6T

0402

1

2

3

11UF

20%

2.5V
X6T

0402

2

3

4

C1321

11UF

20%

2.5V
X6T

0402

1

2

3

4

C1336

11UF

20%

2.5V
X6T

0402

1

2

C1322

1

3

4

C1332

11UF

20%

2.5V
X6T

0402

1

4

2

3

4

11UF

2

3

C1337

1

781813

20%

2.5V
X6T

0402

4

C1333

11UF

1

11UF

20%

2.5V
X6T

0402

4

2

78 18 13

3

20%

2.5V
X6T

0402

2

3

PPVDD_GPU_AWAKE

C1323

11UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

78

1

2

C1324

11UF

20%

2.5V
X6T

0402

1

4

2

C1340

12PF

5%
25V
NP0-C0G
0201

3

C1350

11UF

20%

2.5V
X6T

0402

1

4

2

1

C1341

3PF

+/-0.1PF
25V

2

C0G
0201

C1325

11UF

20%

2.5V
X6T

0402

1

4

2

C1351

11UF

1

3

2

3

20%

2.5V
X6T

0402

AA24
AA26
AA28
AA31
AA33
AA35
AA37
AB25
AB27
AB28
AB30
AB32
AB34
AB36
AC24

7818

AC26
AC31
AC35
AC37
AD25
AD27
AD32
AD34
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD50
AD51
AD52
AD53
AD54
AD55
AE24

VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU

C1352

11UF

20%

2.5V
X6T

0402

1

3

4

3

4

2

U0600

TMLR68A0-B09

BGA

SYM 12 OF 23

VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU

VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1

AE26
AE27
AE29
AE30
AE31
AE42
AE43
AE44
AE45
AE46
AE47
AE48
AE49
AE50
AE51
AE52
AE53
AE54
AE55
AF24
AF32
AG25
AG27
AG31
AG33

AA19
AA21
AA23
AB22
AC19
AD22
AE19
AE21
AG21

PPVDD_GPU_AWAKE

C1353

11UF

20%

2.5V
X6T

0402

1

4

2

1

C1370

12PF

5%
25V

2

NP0-C0G
0201

C1354

11UF

20%

2.5V
X6T

0402

1

3

3

4

2

PPVDD_DISP_S1

C1361

11UF

20%

2.5V
X6T

0402

1

3

4

2

C1365

11UF

20%

2.5V
X6T

0402

1

4

2

C1355

11UF

20%

2.5V
X6T

0402

1

4

2

C1362

11UF

20%

2.5V
X6T

0402

1

4

2

3

1

3

1

3

C1366

1

C1356

11UF

20%

2.5V
X6T

0402

4

2

C1363

11UF

20%

2.5V
X6T

0402

4

2

11UF

20%

2.5V
X6T

0402

3

4

2

3

3

C1357

11UF

20%

2.5V
X6T

0402

1

4

2

C1364

11UF

20%

2.5V
X6T

0402

1

4

2

781813

3

7818

3

4

4

2

2

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

PAGE TITLE

SOC: POWER (SOC, CPU, GPU)

SIZE

D

BOM_COST_GROUP=SOC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

13 OF 801

SHEET

13 OF 92

1

**OK2INTEGRATE**

78 18

PPVDD_CPU_SRAM_AWAKE

C1400

11UF

20%

2.5V
X6T

0402

1

4

2

SOC: POWER (SRAM, SOC)

U0600

TMLR68A0-B09

BGA

SYM 10 OF 23

AE34

1

C1406

12PF

5%
25V

2

NP0-C0G
0201

3

C1402

11UF

20%

2.5V
X6T

0402

1

4

2

C1401

11UF

20%

2.5V
X6T

0402

3

1

4

2

PPVDD_DCS_S1

78 18

C1410

11UF

20%

2.5V
X6T

0402

1

3

4

2

3

C1411

1

C1403

11UF

20%

2.5V
X6T

0402

1

4

2

11UF

20%

2.5V
X6T

0402

3

4

2

3

C1404

11UF

20%

2.5V
X6T

0402

1

4

2

C1412

11UF

20%

2.5V
X6T

0402

1

4

2

3

3

C1405

11UF

20%

2.5V
X6T

0402

1

4

2

C1413

11UF

20%

2.5V
X6T

0402

1

4

2

3

3

1

C1407

3PF

+/-0.1PF
25V

2

C0G
0201

AE39
AG36
AH35
AH37
AJ36
AJ38
AK27
AK31
AK37
AL33
AL35
AL38
AM25
AM26
AM31
AM36
AN26
AN27
AN30
AN32
AN35
AN37
AP27
AP36
AR31
AR34
AR38

AA39
AB17
AB38
AC18
AC39
AD17
AE18
AF17
AG18
AJ18
AK17
AL18

VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM

VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1

W17

VDD_DCS_S1

W22

VDD_DCS_S1

W24

VDD_DCS_S1

W26

VDD_DCS_S1

W31

VDD_DCS_S1

W33

VDD_DCS_S1

W35

VDD_DCS_S1

W39

VDD_DCS_S1

Y18

VDD_DCS_S1

Y20

VDD_DCS_S1

Y23

VDD_DCS_S1

Y25

VDD_DCS_S1

Y27

VDD_DCS_S1

Y29

VDD_DCS_S1

Y32

VDD_DCS_S1

Y34

VDD_DCS_S1

Y38

VDD_DCS_S1

VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1

AA18
AA32
AB20
AB24
AB31
AB35
AC21
AC28
AC30
AD20
AD21
AD24
AD28
AD30
AD35
AF20
AF22
AF26
AF30
AG28
AH19
AH21
AH23
AH25
AH27
AH29
AH31
AK19
AK21
AK23
AM19
AM21
AM23
AP21
AP23
AT19
AT21
AT23
AT25
AT27
AT29
AT31
AT39
AU36
AV37

PP0V764_S1_SRAM

C1420

11UF

20%

2.5V
X6T

0402

1

4

2

7818

C1423

11UF

20%

2.5V
X6T

0402

1

4

2

3

3

C1422

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1421

11UF

20%

2.5V
X6T

0402

3

1

4

2

C1424

11UF

20%

2.5V
X6T

0402

1

4

2

3

C1425

11UF

20%

2.5V
X6T

0402

1

4

2

3

PAGE TITLE

SOC: POWER (SRAM)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

**OK2INTEGRATE**

PP0V805_S1_VDD_FIXED

78

LPDP_RX Power may be grounded,
Wait until Dev Bringup is complete before grounding it.

Until then connect it to PP1V2_AWAKE

PP0V805_S1_VDD_FIXED

78

20%

4V

0201

1

2

C1508

78 15

78 15

C1507

2.2UF

X6S-CERM

PP0V805_S1_VDD_FIXED

PP0V805_S1_VDD_FIXED

C1513

4.3UF

20%

2.5V
X6T

0402

1

3

4

2

120OHM-25%-0.25A-0.5OHM

78 15

78 18

78 18

PP0V805_S1_VDD_FIXED

PP0V805_S1_VDD_FIXED

78

PP0V805_S1_VDD_FIXED

PP0V72_S2_VDD_LOW

C1520

3PF

+/-0.1PF

25V
C0G

0201

1

2

1

C1510

2.2UF

20%
4V

2

X6S-CERM
0201

C1521

2.2UF

20%

X6S-CERM

0201

C1530

4.3UF

20%

2.5V
X6T

0402

3

4

2

PP0V72_S2_VDD_LOW

78

PP0V72_S2_VDD_LOW

78

1

78 18

0.1UF

6.3V
0201

1

4V

2

PP0V805_S1_VDD_FIXED

C1505

0.1UF

10%

6.3V 4V
X6S

0201 0201

10%
X6S

1

2

R1500

C1514

78 15

FL1510

21

PP0V805_S1_SOC_VDDFIXEDPLL_F

0201

20%

4V

0201

1

2

C1511

2.2UF

X6S-CERM

C1531

4.3UF

20%

2.5V
X6T

0402

1

3

4

2

PP0V805_S1_VDD_FIXED

78

1

2

0

5%

1/20W

MF

0201

0.1UF

C1506

2.2UF

X6S-CERM

78

VOLTAGE=0.805V

21

PP0V805_S1_SOC_VDDFIXEDPCIE_R

1

10%

6.3V
2

X6S

1

20%

2

PP0V805_S1_VDD_FIXED

C1515

0.1UF

6.3V
02010201

PP0V805_S1_VDD_FIXED

C1502

0.1UF

VOLTAGE=0.805V

C1512

0.1UF

R1590

10

5%

1/20W

MF

201

21

1

10%

6.3V
2

X6S

0201

VOLTAGE=0.805V

PP0V805_S1_SOC_VDDFIXEDXTAL_R

1

2

R1535

10

2 1

5%

1/20W

MF

201

R1536

49.9

1/20W

78

21
1%
MF

201

PP0V72_S2_VDD_LOW

5%

25V

0201

C1500

0.1UF

6.3V

1

2

2.2UF

X6S-CERM

10%
X6S

C1519

20%

4V

0201

1

2

C1517

0.22UF

20%

6.3V

X6S-CERM

02010201

3PF

+/-0.1PF

25V
C0G

0201

1

2

C1504

2.2UF

X6S-CERM

1

2

C1501

1

10%

2

X6S

1

10%

6.3V
2

X6S

C1516

0.1UF

6.3V

C1518

12PF

NP0-C0G

C1503

1

10%

2

X6S

C1590

4UF

20%

2.5V
X6S
0201

VOLTAGE=0.72V

PP0V72_S2_VDD_LOWFLPLL_R

C1535

0.22UF

X6S-CERM

VOLTAGE=0.72V

PP0V72_S2_VDD_LOWULPPLL_R

1

20%

6.3V
2

0201

1

C1536

4UF

20%

2.5V

2

X6S
0201

1

2

0.1UF

6.3V
0201

20%

4V

020102010201

10%
X6S

1

2

5

U0600

PP0V855_S2SW_CIO

TMLR68A0-B09

BGA

SYM 13 OF 23

C1540

0.1UF

AM28

AW19
AW20
AW21

BA37
BA38
BA39

1

2

AY18

AV33

AV29
AV30
AV31
AV32

AL34

AT32

AF29

AR20

AH13
AG13
AC13

AC42

BA32

AD40
AG40
AJ39
AP17
AU32
AV39
AY16

AV23
AV25
AV27
AW26
AY26
BA23

AW24

AW22

AW28

BA22

VDD_FIXED_ECPU_S1

VDD_FIXED_LPDP_RX_S1
VDD_FIXED_LPDP_RX_S1
VDD_FIXED_LPDP_RX_S1

VDD_FIXED_LPDP_TX_S1
VDD_FIXED_LPDP_TX_S1
VDD_FIXED_LPDP_TX_S1

R11

VDD_FIXED_MIPIC_S1

R12

VDD_FIXED_MIPIC_S1

R13

VDD_FIXED_MIPIC_S1

R10

VDD_FIXED_MIPID_PLL_S1

P9

VDD_FIXED_MIPID_S1

R9

VDD_FIXED_MIPID_S1

VDD_FIXED_MTR_S1

VDD_FIXED_PCIE_REFBUF_S1

VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1

VDD_FIXED_PCPU_S1

VDD_FIXED_PLL_ANE_S1

VDD_FIXED_PLL_GPU_S1

VDD_FIXED_PLL_SOC_S1

VDD_FIXED_PLL_DDR0_S1
VDD_FIXED_PLL_DDR1_S1
VDD_FIXED_PLL_DDR2_S1

T24

VDD_FIXED_PLL_DDR3_S1

R28

VDD_FIXED_PLL_DDR4_S1

R29

VDD_FIXED_PLL_DDR5_S1

T34

VDD_FIXED_PLL_DDR6_S1
VDD_FIXED_PLL_DDR7_S1

VDD_FIXED_XTAL_S1

VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1

V17

VDD_FIXED_S1

VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2

VDD_LOW_FLPPLL_S2

VDD_LOW_ULPPLL_S2

VDD_LOW_USB_DEBUG_S2

VDD_HIB_S4

VDD_CIO
VDD_CIO
VDD_CIO

VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2

VDD_CIO_USB

VDD12_CIO_USB_S2

VDD12_AMUX_S2

VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX

VDD12_LPDP_TX
VDD12_LPDP_TX
VDD12_LPDP_TX

VDD12_MIPIC
VDD12_MIPIC
VDD12_MIPIC

VDD12_MIPID
VDD12_MIPID

VDD12_MTR

VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE

VDD12_PCIE_REFBUF

VDD12_PLL_ANE

VDD12_PLL_CPU

VDD12_PLL_GPU

VDD12_PLL_SOC

VDD12_TSADC_CPU

VDD12_TSADC_SOC0
VDD12_TSADC_SOC1
VDD12_TSADC_SOC2
VDD12_TSADC_SOC3
VDD12_TSADC_SOC4

VDD12_ULPPLL_S2

VDD12_USB_DEBUG_S2

VDD12_XTAL

AV34
AV36
AW35

AU42
AU43
AV42
AV43
AY34
AY36
BA35

AU34

AU35

AT42

AV11
AV20
AW11
AW13
AY13
AY19
AY20
AY21

AW37
AW38
AW39

P11
P12
P13

P8
R8

AW18

AY29
AY30
AY31
AY32
AY43
BA42
BA43

AW33

AP31

AK34

AG29

AP19

AK32

U20
Y33
AH32
AY15
AE40

AW23

AY28

BA33

PP1V2_S2_CIO

C1544

PP0V855_S2SW_CIO
PP1V2_S2_CIO
PP1V25_S2
PP1V25_AWAKE_IO

PP1V2_AWAKE_PLL

C1563

+/-0.1PF

PP1V25_AWAKE_IO

10%

6.3V
X6S

C1554

1

2

0.1UF

C1560

2.2UF

X6S-CERM

1

20%

4V

0201 0201

C1561

0.1UF

PP1V25_AWAKE_IO

PP1V2_AWAKE_PLL

C1553

0.1UF

VOLTAGE=1.2V

1

10%

6.3V
2

X6S

0201 0201

PP1V2_AWAKE_PLL_PCIE_R

PP1V2_AWAKE_PLL

PP1V25_AWAKE_IO

VOLTAGE=1.25V

PP1V25_S2_ULPPLL_R

PP1V25_S2

1

C1582

0.1UF

10%

6.3V

2

X6S
0201

0.1UF

6.3V

C1573

1

10%

6.3V
2

X6S

1

10%

6.3V
2

X6S

0201 0201

1

3PF

25V

2

C0G

0201

C15622

10%

2

X6S

1

0.1UF

10%

6.3V 4V
X6S

0201 0201

C1541

C1545

C1564

NP0-C0G

2.2UF

20%

4V

X6S-CERM

0201

C1574

X6S-CERM

0.1UF

0.1UF

12PF

5%

25V

0201

1

2

2.2UF

C1570

78

78

1

10%

6.3V
2

X6S

02010201

1

10%

6.3V
2

X6S

1

C1550

2.2UF

2

X6S-CERM

20%

4V

0201

1

C1551

0.1UF

2

R1574

0

21

5%

1

20%

2

0.1UF

10%

6.3V 4V
X6S

0201 02010201

1/20W

MF

0201

1

C1571

0.1UF

2

10%

6.3V
X6S

1

2

R1584

1

C1584

4.7UF

20%

6.3V

2

CER
0402

49.9

1/20W

1%
MF

201

21

PP1V25_S2

1

10%

6.3V
2

X6S

0201

C1572

2.2UF

20%

X6S-CERM

Wait until Dev Bringup is complete before grounding it.

C1555

4.3UF

20%

2.5V
X6T

0402

1

1

2

3

4

2

C1542

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1546

4.3UF

20%

2.5V
X6T

0402

1

4

2

3

3

78

78

78

78

78

LPDP_RX Power may be grounded,

Until then connect it to PP1V2_AWAKE

78

78

C1556

4.3UF

1

2

78

78

20%

2.5V
X6T

0402

4

C1543

4.3UF

20%

2.5V
X6T

0402

1

4

2

C1547

4.3UF

20%

2.5V
X6T

0402

1

4

2

3

3

3

FL1580

VDD12_EFUSE1
VDD12_EFUSE2
VDD12_EFUSE3

VDD12_FMON

AU40
AT20
AB43

AU19

VOLTAGE=1.25V

PP1V25_AWAKE_XTAL_F

VOLTAGE=1.25V

PP1V25_AWAKE_FMON_R

1

C1583

2.2UF

20%
4V

2

X6S-CERM
0201

240-OHM-0.2A-0.9-OHM

2 1

0201

1

C1580

0.1UF

10%

6.3V

2

X6S
0201

R1583

49.9

1/20W

1%
MF

201

2

1

C1581

2.2UF

20%
4V

2

X6S-CERM
0201

PP1V25_AWAKE_IO

PP1V25_AWAKE_IO

78

78

PAGE TITLE

SOC: POWER (Fixed, PLL's, Filtered)

78

78

78

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

SIZE

A

PP0V72_S2_VDD_LOW

78

C1537

0.1UF

10%

6.3V
X6S

0201

1

2

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

**OK2INTEGRATE**

SOC: GND (1)

A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

A2
A20
A21
A22
A23
A24
A25
A27
A28
A29

A3
A30
A37
A38
A39

A4
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54

A9

AA10
AA11
AA12
AA13
AA15
AA17
AA20
AA22
AA25
AA27
AA30
AA34
AA36
AA38
AA41
AA43
AA44
AA45
AA46
AA47

AA8
AA9

AB10
AB11
AB12
AB13
AB14
AB16
AB18
AB19

AB2

AB21
AB26
AB29
AB33
AB37
AB39
AB40

U0600

TMLR68A0-B09

SYM 15 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB42
AB44
AB45
AB46
AB47
AB48
AB5
AB51
AB54
AB8
AB9
AC10
AC11
AC12
AC15
AC17
AC20
AC22
AC25
AC27
AC29
AC32
AC34
AC36
AC41
AC44
AC45
AC46
AC47
AC8
AC9
AD10
AD11
AD12
AD13
AD14
AD16
AD18
AD19
AD23
AD26
AD29
AD31
AD33
AD38
AD39
AD8
AD9
AE10
AE11
AE12
AE14
AE15
AE17
AE2
AE20
AE22
AE25
AE28
AE41
AE5
AE8
AE9
AF10
AF11
AF12
AF13
AF14
AF16
AF18
AF19
AF21
AF23
AF25
AF27
AF31
AF34
AF35
AF37
AF38

AF40
AF42
AF43
AF44
AF45
AF46
AF47

AF8

AF9
AG10
AG11
AG12
AG15
AG20
AG22
AG24
AG26
AG30
AG32
AG35
AG37
AG41
AG43
AG44
AG45
AG46
AG47
AG48
AG51
AG54

AG8

AG9
AH10
AH11
AH12
AH18

AH2
AH20
AH24
AH26
AH28
AH30
AH33
AH36
AH38
AH41
AH42
AH43
AH44
AH45
AH46
AH47

AH5

AH8

AH9
AJ10
AJ11
AJ12
AJ13
AJ15
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ35
AJ37
AJ40
AJ41
AJ42
AJ43
AJ44
AJ45
AJ46
AJ47

AJ8

AJ9
AK10
AK11

U0600

TMLR68A0-B09

SYM 16 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK12
AK13
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AK39
AK47
AK49
AK51
AK54
AK8
AK9
AL10
AL11
AL12
AL13
AL15
AL17
AL19
AL2
AL21
AL23
AL25
AL27
AL31
AL36
AL39
AL47
AL5
AL55
AL8
AL9
AM10
AM11
AM12
AM13
AM14
AM16
AM18
AM20
AM22
AM24
AM27
AM30
AM32
AM33
AM35
AM37
AM40
AM6
AM7
AM8
AM9
AN1
AN10
AN11
AN12
AN13
AN14
AN19
AN2
AN21
AN25
AN28
AN3
AN31
AN36
AN39
AN4
AN41
AN5
AN6
AN7
AN8

AN9
AP10
AP11
AP12
AP13
AP14
AP15
AP18
AP20
AP22
AP24
AP26
AP28

AP3
AP30
AP32
AP34
AP35
AP37
AP42
AP53
AP54
AP55

AP6

AP9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR19
AR21
AR23
AR25
AR27
AR29

AR3
AR42
AR43
AR44
AR45
AR46
AR47
AR48
AR49
AR50
AR51
AR52
AR53

AR6

AR9
AT10
AT11
AT12
AT13
AT14
AT15
AT17
AT18
AT22
AT24
AT26
AT28

AT3
AT30
AT34
AT36
AT38
AT41
AT43
AT44
AT45
AT46
AT47
AT48
AT49
AT50
AT51

U0600

TMLR68A0-B09

SYM 17 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AT52
AT53
AT6
AT9
AU10
AU11
AU12
AU13
AU14
AU15
AU16
AU21
AU23
AU25
AU27
AU29
AU3
AU31
AU33
AU37
AU39
AU41
AU44
AU45
AU46
AU47
AU48
AU49
AU50
AU53
AU6
AU7
AU8
AU9
AV10
AV12
AV13
AV14
AV15
AV17
AV18
AV19
AV21
AV22
AV24
AV26
AV28
AV3
AV35
AV38
AV41
AV44
AV45
AV46
AV47
AV48
AV49
AV50
AV53
AV6
AV9
AW10
AW12
AW14
AW15
AW16
AW25
AW27
AW29
AW3
AW30
AW31
AW32
AW34
AW36
AW40
AW41
AW42
AW43
AW44

AW45
AW46
AW47
AW48
AW49
AW50
AW51
AW52
AW53

AW6

AW9
AY10
AY11
AY12
AY14
AY17
AY22
AY24

AY3
AY33
AY35
AY37
AY38
AY39
AY40
AY41
AY42
AY44
AY45
AY46
AY47
AY48
AY49
AY50
AY53

AY6

AY9

B1
B11
B12
B13
B14
B15
B16
B17
B18
B19

B2
B20
B22
B24
B27
B28
B29
B32
B34
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B49

B5
B51
B54
B55

B7
BA1

BA18
BA19

BA2

BA20
BA21
BA25
BA27

U0600

U0600

TMLR68A0-B09 TMLR68A0-B09

BGA

SYM 19 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SYM 18 OF 23

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA28
BA29
BA3
BA30
BA31
BA34
BA36
BA4
BA40
BA41
BA44
BA45
BA46
BA47
BA48
BA49
BA5
BA50
BA53
BA54
BA55
BA6
BA7
BA8
BA9
BB11
BB14
BB17
BB20
BB23
BB26
BB27
BB28
BB29
BB30
BB31
BB32
BB33
BB34
BB35
BB36
BB39
BB40
BB41
BB42
BB43
BB44
BB45
BB46
BB47
BB48
BB49
BB50
BB51
BB52
BB6
BB8
BC22
BC23
BC26
BC28
BC30
BC32
BC34
BC36
BC39
BC4
BC40
BC41
BC42
BC44
BC46
BC48
BC50
BC51
BC52
BD1
BD2
BD23
BD24

BD25
BD26
BD28
BD30
BD32
BD34
BD36
BD37
BD38
BD39
BD40
BD41
BD42
BD44
BD46
BD48
BD50
BD51
BD52
BD53
BD54
BD55

BE1
BE11
BE14
BE17

BE2
BE20
BE22
BE25
BE27
BE29

BE3
BE31
BE33
BE35
BE37
BE41
BE43
BE45
BE47
BE49

BE5
BE51
BE53
BE54
BE55

BE8

BF2
BF22
BF23
BF25
BF27
BF29

BF3
BF31
BF33
BF35
BF37
BF41
BF43
BF45
BF47
BF49
BF51
BF53
BF54

C1
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19

C2
C20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C21
C23
C25
C26
C27
C28
C29
C30
C31
C33
C35
C36
C37
C38
C39
C4
C40
C41
C42
C43
C44
C45
C46
C47
C48
C50
C52
C54
C55
C6
C8
C9
D1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D2
D20
D24
D26
D27
D28
D29
D3
D30
D32
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D5
D51
D53
D54
D55
D9
E1
E10
E11
E12
E13
E14
E15
E16
E17

PAGE TITLE

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

A

BOM_COST_GROUP=SOC

2

SOC: GND

1

8

**OK2INTEGRATE**

SOC: GND (2)

E18
E19

E2
E20
E22
E23
E25
E27
E28
E29
E31
E33
E34
E36
E37
E38
E39

E4
E40
E41
E42
E43
E44
E45
E46
E47
E49

E5
E50
E52
E54
E55

E6

E7

E9

F1
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19

F2
F20
F21
F22
F24
F26
F27
F28
F29

F3
F30
F32
F34
F35
F36
F37
F38
F39
F40
F41
F42
F43
F44
F45
F46
F47
F48
F49

F5
F51
F53
F54
F55

F7

U0600

TMLR68A0-B09

SYM 20 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F8
F9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G2
G20
G21
G22
G23
G25
G27
G28
G29
G31
G33
G34
G35
G36
G37
G38
G39
G4
G40
G41
G42
G43
G44
G45
G46
G47
G48
G49
G50
G52
G54
G6
G7
G8
G9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H2
H20
H21
H22
H24
H26
H27
H28
H29
H3
H30
H32
H34
H35
H36
H37
H38
H39
H40
H41
H42
H43
H44

H45
H46
H47
H48
H49

H5
H51
H53
H54

H7

H8

H9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19

J2
J20
J21
J22
J23
J25
J27
J28
J29
J31
J33
J34
J35
J36
J37
J38
J39

J4
J40
J41
J42
J43
J44
J45
J46
J47
J48
J49
J50
J52
J54
J55

J6

J7

J8

J9

K1
K10
K13
K16
K18
K19

K2
K20
K21
K22
K23
K25
K27
K28
K29
K31
K33
K34
K35
K36
K37
K38

U0600

TMLR68A0-B09

SYM 21 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K39
K4
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K50
K52
K54
K55
K6
K7
L1
L10
L13
L16
L18
L19
L2
L20
L21
L22
L24
L26
L27
L28
L29
L3
L30
L32
L34
L35
L36
L37
L38
L39
L40
L41
L42
L43
L44
L45
L46
L47
L48
L49
L5
L51
L53
L54
L55
L7
M1
M10
M13
M16
M17
M18
M19
M2
M20
M21
M22
M23
M25
M27
M28
M29
M31
M33
M34
M35
M36
M37

M38
M39

M4
M40
M41
M42
M43
M44
M45
M46
M47
M48
M49
M50
M52
M54
M55

M6

M7

M8

N1
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19

N2
N20
N21
N22
N23
N24
N26
N27
N28
N29

N3
N30
N32
N33
N34
N35
N36
N37
N38
N39
N40
N41
N42
N43
N44
N45
N46
N47
N48
N49

N5
N50
N51
N53
N54

N6

N7

N8

N9

P1
P10
P14
P15
P16
P17
P18
P19

P2
P20

U0600

TMLR68A0-B09

SYM 22 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P21
P22
P25
P26
P27
P28
P29
P3
P30
P31
P34
P35
P36
P37
P38
P39
P4
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P52
P53
P7
R1
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R26
R27
R3
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R4
R40
R41
R42
R43
R44
R45
R46
R47
R5
R6
R7
T1
T10
T11
T12
T13
T14
T15
T17
T19
T2
T21
T23
T27

T3
T31
T35
T37
T39

T4
T41
T42
T43
T44
T45
T46
T47
T48

T5
T51
T54

T6

T7

T8

T9

U1
U10
U11
U12
U13
U16
U18

U2
U22
U24
U26
U28

U3
U30
U32
U34
U36
U38

U4
U40
U41
U42
U43
U44
U45
U46
U47
U48

U5

U6

U7

U8

U9

V1
V10
V11
V12
V13
V14
V15

V2
V21
V23
V25
V27

V3
V31
V33
V35
V39

V4
V41
V42
V43
V44
V45
V46
V47

V5

U0600

TMLR68A0-B09

SYM 23 OF 23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

V6
V7
V8
V9
W10
W11
W12
W13
W15
W16
W2
W21
W23
W25
W27
W32
W34
W41
W42
W43
W44
W45
W46
W47
W48
W5
W51
W54
W8
W9
Y10
Y11
Y12
Y13
Y14
Y16
Y19
Y22
Y24
Y28
Y30
Y35
Y37
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y51
Y8
Y9
B48

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

PAGE TITLE

SOC: GND-2

79 11

PP1V8_S2SW_VDD1

78 15

PP0V72_S2_VDD_LOW

78 11

78 11

5%

25V

0201

1

2

C1801

3.0PF

+/-0.1PF

NP0-C0G

C1800

12PF

NP0-C0G

PP1V06_S2SW_DRAM

5%

25V

0201

1

2

C1811

3.0PF

+/-0.1PF

NP0-C0G

C1810

12PF

NP0-C0G

PP0V6_S1_VDDQL

5%

25V

0201

1

2

C1821

3.0PF

+/-0.1PF

NP0-C0G

C1820

12PF

NP0-C0G

25V

0201

25V

0201

25V

0201

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

C1805

3.0PF

+/-0.1PF

NP0-C0G

C1815

3.0PF

+/-0.1PF

NP0-C0G

C1825

3.0PF

+/-0.1PF

NP0-C0G

1

C1802

12PF

2

1

NP0-C0G

C1812

12PF

2

1

NP0-C0G

C1822

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

C1803

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1813

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1823

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

C1804

12PF

2

1

NP0-C0G

C1814

12PF

2

1

NP0-C0G

C1824

12PF

2

NP0-C0G

25V

0201

25V

0201

25V

0201

1

C1870

12PF

2

78 13

1

PPVDD_ECPU_AWAKE

NP0-C0G

C1872

12PF

2

78 13

1

2

PPVDD_DISP_S1

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

C1871

3.0PF

+/-0.1PF

NP0-C0G

C1873

3.0PF

+/-0.1PF

NP0-C0G

C1874

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

25V

0201

25V

0201

1

2

1

2

1

2

78 13

78 13

78 14

PPVDD_PCPU_AWAKE

5%

25V

0201

1

2

C1831

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1830

12PF

NP0-C0G

PPVDD_GPU_AWAKE

5%

25V

0201

1

2

C1841

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1840

12PF

NP0-C0G

PPVDD_CPU_SRAM_AWAKE

1

C1832

12PF

2

1

NP0-C0G

C1842

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

C1833

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1843

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

C1834

12PF

2

1

NP0-C0G

C1844

12PF

2

NP0-C0G

5%

25V

0201

5%

25V

0201

1

2

1

2

C1835

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1845

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

2

1

2

78 14

78 14

1

2

C1851

3.0PF

+/-0.1PF

NP0-C0G

C1850

12PF

5%

25V

NP0-C0G

0201

PPVDD_DCS_S1

5%

25V

0201

1

2

C1855

3.0PF

+/-0.1PF

NP0-C0G

C1854

12PF

NP0-C0G

PP0V764_S1_SRAM

1

2

C1861

3.0PF

+/-0.1PF

NP0-C0G

C1860

12PF

5%

25V

NP0-C0G

0201

25V

0201

25V

0201

25V

0201

5%

25V

0201

5%

25V

0201

5%

25V

0201

1

2

1

2

1

2

C1853

3.0PF

+/-0.1PF

NP0-C0G

C1857

3.0PF

+/-0.1PF

NP0-C0G

C1863

3.0PF

+/-0.1PF

NP0-C0G

1

C1852

12PF

2

1

NP0-C0G

C1856

12PF

2

1

NP0-C0G

C1862

12PF

2

NP0-C0G

25V

0201

25V

0201

25V

0201

1

2

1

2

1

2

78 15

78 15

PP0V805_S1_VDD_FIXED

PP0V805_S1_VDD_FIXED

C1864

12PF

5%

25V

NP0-C0G

0201

C1866

12PF

5%

25V

NP0-C0G

0201

2

1

2

C1865

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

C1867

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

2

1

SYNC_DATE=10/08/2019SYNC_MASTER=ref_soc_h13g

PAGE TITLE

2

SOC: DESENSE CAPS

DRAWING NUMBER

051-05392

Apple Inc.

REVISION

SIZE

D

4.0.0

BRANCH

evt-1

PAGE

18 OF 801

SHEET

18 OF 92

BOM_COST_GROUP=DESENSE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

1

8

**OK2INTEGRATE**

SPI NOR (1.8V 64 M-BIT)

PP1V8_AWAKE

78

78 19

R1974

7

SPI_SOCROM_MOSI_R

IN

R1975

7

SPI_SOCROM_CLK_R

IN

1

R1972

47K

5%
1/20W

201

2

1

R1973

47K

5%
1/20W
MFMF
201

2

78 19

PP1V25_AWAKE_IO

33

21

5%

1/20W

MF

201

33

5%

1/20W

MF

201

21

SPI_SOCROM_MOSI
SPI_SOCROM_CLK

PP1V8_AWAKE

1

C1974

0.1UF

10%

6.3V

2

X6S

U1974

74AVC2T45

1A
2A

5

DIR

VSSOP

GND

PP1V8_AWAKE

VCCBVCCA

72

1B
2B

SPI_SOCROM_1V8_MOSI_R

63

SPI_SOCROM_1V8_CLK_R

PP1V25_AWAKE_IO

7819

1

C1975 2

0.1UF

10%

6.3V

2

X6S
02010201

7819

R1976

33

5%

1/20W

MF

201

R1977

33

5%

1/20W

MF

201

21

SPI_SOCROM_1V8_MOSI

21

SPI_SOCROM_1V8_CLK

19

19

19

19

1

C1970

0.1UF

10%

6.3V
X6S
0201

R1971

SPI_SOCROM_1V8_CLK

SPI_SOCROM_1V8_CS_L

10K

5%

1/20W

MF

201

1

2

R1970

100K

5%

1/20W

MF

201

SPI_SOCROM_WP_L

1

VCC

2

U1970

W25Q64JWUUIQ

64MB-1.8V

6

CLK

1

CS*

3

WP*/IO2

7

HOLD*/RESET*/(IO3)

USON

DI(IO0)

DO(IO1)

EPADGND

5

SPI_SOCROM_1V8_MOSI

2

SPI_SOCROM_1V8_MISO_R

19

19

SPI_SOCROM_1V8_MISO_R

19

1

R1980

100K

5%
1/20W
MF
201

2

R1983

33

5%

1/20W

MF

201

78 19

1

C1983

0.1UF

10%

6.3V

2

X6S
0201

21

SPI_SOCROM_1V8_MISO

PP1V25_AWAKE_IO

1

C1992

0.1UF

10%

6.3V

2

X6S
0201

1

R1992

47K

5%
1/20W
MF
201

2

VCCA VCCB

5

DIR

A

VCCA VCCB

5

DIR

GND

U1983

SN74AXC1T45

SOT-5X3

43

B

PP1V8_AWAKE

U1992

SN74AXC1T45

SOT-5X3

1

C1984

0.1UF

10%

6.3V

2

X6S
0201

1

C1993

0.1UF

10%

6.3V

2

X6S
0201

R1984

33

21

SPI_SOCROM_MISOSPI_SOCROM_MISO_R

5%

1/20W

MF

201

7819

OUT

7

43

7

IN

A

GND

B

SPI_SOCROM_1V8_CS_LSPI_SOCROM_CS_L

19

SYNC_DATE=05/04/2020SYNC_MASTER=ref_soc_h13g

PAGE TITLE

SPI NOR

SIZE

D

BOM_COST_GROUP=SOC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

19 OF 801

SHEET

19 OF 92

2

1

A Series Terminations D Test Points

TCON SPI Interface

7 67

IN

IN OUT

SPI_TCON_CLK_R SPI_TCON_CLK

SPI_TCON_MOSI_R

R2101

R2102

2 1

2 1

MF 5%

20

5%MF

1/20W201

20

1/20W201

SPI_TCON_MOSI

Speaker Amp TDM Interface

7

IN OUT

7

IN OUT

7

IN OUT

TDM_SPKRAMP_L_BCLK_R

TDM_SPKRAMP_L_R2D_R

TDM_SPKRAMP_L_FSYNC_R

R2110

201 1/20W

R2111

201 1/20W

R2112

201 1/20W

2 1

MF 5%

2 1

MF 5%

2 1

MF 5%

20

20

20

TDM_SPKRAMP_L_BCLK

TDM_SPKRAMP_L_R2D

TDM_SPKRAMP_L_FSYNC

OUT

10

OUT

6

IN

10

IN

677

6

IN

80

80

80

6

IN

6

IN

SMC_FIXTURE_MODE_L
SOC_AMUX_OUT
TPT_SOC_DOCK_ATTENTION

TPT_SOC_DOCK_ATTENTION

MAKE_BASE=TRUE

TPT_TST_CLKOUT

TPT_TST_CLKOUT

MAKE_BASE=TRUE

TPT_TMU_CLK_OUT0

TPT_TMU_CLK_OUT0

MAKE_BASE=TRUE

TPT_TMU_CLK_OUT1

TPT_TMU_CLK_OUT1

MAKE_BASE=TRUE

1

TP
TP
TP

TP

TP

TP

TP-P4
TP-P4
TP-P4

TP-P4

TP-P4

TP-P4

1
1

1

1

1

TP2101
TP2102
TP2103

TP2104

TP2105

TP2106

7

IN

7

7

IN

TDM_SPKRAMP_R_BCLK_R

TDM_SPKRAMP_R_R2D_R

TDM_SPKRAMP_R_FSYNC_R

R2162

R2163

201 5%MF

R2164

20

21

1/20WMF201 5%

20

21

1/20W

20

21

1/20W201 MF 5%

TDM_SPKRAMP_R_BCLK

TDM_SPKRAMP_R_R2D

TDM_SPKRAMP_R_FSYNC

Trackpad SPI Interface

7 76

IN

7

IN

SPI_IPD_MOSI_R SPI_IPD_MOSI

SPI_IPD_CLK_R

R2113

201 1/20W

R2114

201

2 1

MF 5%

2 1

20

20

5%MF

1/20W

SPI_IPD_CLK

Master PMU SPI Interface

10 34

IN OUT

10 34

BI BI

SPMI_NUB_MPMU_CLK_R SPMI_NUB_MPMU_CLK

SPMI_NUB_MPMU_DATA_R SPMI_NUB_MPMU_DATA

R2115

R2116

201 1/20W

2 1

2 1

MF 5%

20

5%MF

1/20W201

20

OUT

OUTIN

OUT

OUT

OUT

10

80

80

80

IN

10

IN

10

IN

TPT_JTAG_SOC_TDI

TPT_JTAG_SOC_TDI

MAKE_BASE=TRUE

TPT_JTAG_SOC_TDO

TPT_JTAG_SOC_TDO

MAKE_BASE=TRUE

TPT_JTAG_SOC_TRST_L

TPT_JTAG_SOC_TRST_L

MAKE_BASE=TRUE

1

TP

TP-P4

1

TP

TP-P4

1

TP

TP-P4

TP2107

TP2108

TP2109

Place near level shifterPlace near SOC

76

6

6

6

EUSB_ATC0_P

BI

BI

BI

EUSB_ATC0_N

EUSB_ATC1_P

PP2190

PP2191

PP2192

PP

PP

PP

1

P4MM

P4MM

1

P4MM

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

EUSB_ATC0_P
EUSB_ATC0_P

EUSB_ATC0_N

EUSB_ATC0_N

EUSB_ATC1_P

EUSB_ATC1_P

TP-P4

TP-P4

TP-P4

58

BI

1

TP

1

TP

1

TP

TP2194

TP2195

TP2196

BI

BI

58

58

Slave PMU SPI Interface

10 30

IN OUT

10

BI

SPMI_NUB_SPMU_CLK_R SPMI_NUB_SPMU_CLK

SPMI_NUB_SPMU_DATA_R

R2117

R2118

201 1/20W

2 1

MF 5%

2 1

20

1/20W201

20

5%MF

SPMI_NUB_SPMU_DATA

SPMI Interface

10

IN

10 21

BI

SPMI_SE_CLK_R

SPMI_SE_DATA_R SPMI_SE_DATA

R2119

201 1/20W

R2120

2 1

2 1

MF 5%

20

5%MF

SPMI_SE_CLK

20

1/20W201

AOP Gyro SPI Interface

IN

SPI_AOP_GYRO_MOSI_R

SPI_AOP_GYRO_MOSI_R

MAKE_BASE=TRUE

IN OUT

SPI_AOP_GYRO_CLK_R

SPI_AOP_GYRO_CLK_R

MAKE_BASE=TRUE

49

OUT

SPI_AOP_GYRO_MISO

R2121

201 1/20W

10

R2122

201 1/20W

10

2 1

2 1

20

5%MF

20

5%MF

SPI_AOP_GYRO_MOSI

SPI_AOP_GYRO_CLK

SPI_AOP_GYRO_MISO

MAKE_BASE=TRUE

10

BI

OUT

BI

OUT

6

BI

30

21

EUSB_ATC1_N

PP2193

PP

1

P4MM

MAKE_BASE=TRUE

EUSB_ATC1_N

EUSB_ATC1_N

TP-P4

58

BI

1

TP

TP2197

E Pull Down Resistors

UPC_FORCE_PWR

759

49

49

SOC_DFU_STATUS

65482

1

R2170

47K

5%
1/20W
MF
201

2

1

R2175

47K

5%
1/20W
MF
201

2

GPU_CFG_L

7

SOC_SEL:GOOD

1

R2176

1K

5%
1/20W
MF
201

2

B BOOT Config Aliases

57

OUT

57

OUT

57

OUT

BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2

SSD S5E Data/Clock AliasesC

SWD_NAND0_SWCLK

6

MAKE_BASE=TRUE

SWD_NAND0_SWDIO

6

MAKE_BASE=TRUE

BOOT_CONFIG0

MAKE_BASE=TRUE

BOOT_CONFIG1

MAKE_BASE=TRUE

BOOT_CONFIG2

MAKE_BASE=TRUE

SWD_NAND0_SWCLK
SWD_NAND0_SWCLK

SWD_NAND0_SWDIO
SWD_NAND0_SWDIO

62

63

62

63

SOC: Project Support

Apple Inc.

Timing Requirements:

- VBAT supply ramp time: 20ms

Ceres - Secure Element

*** OK2INTEGRATE ***

Per TGA Power Block Diagram v0.3

U5000.B5:3mm

C5008

0.22UF

6.3V
0201

X5R

PP1V8_S2

78

IccMax SE only: 125mA IccMax SE only: 10mA

U5000.F9:3mm

C5014

1.0UF

6.3V

0201-1

20%
X5R

U5000.F8:3mm

20%

6.3V
X5R

0201

0

1

2

21

VUP_SEVDDBOOST_SE

5%0201

1

C5002

0.22UF

2

R5030

MF1/20W

U5000.E7:3mm

C5003

0.22UF

6.3V
0201

20%
X5R

1

2

PP1V25_S2

VDDPLL_SE
VDDNV_SE
VDDC_SE

20%
10V
X5R

0201

1

2

C5051

U5000.E8:3mm

1

2

C5009

0.22UF

20%20%
X5R

0201

1

2

U5000.E9:3mm

C5010

0.22UF

6.3V6.3V
0201

20%
X5R

2

2.2UF

PP3V8_AON_VDDMAIN 7921

IccMax: 100mA

78

Based on SPMI only use case

As per NXP preliminary estimate, final pending

NC

D4

NFC_CLK_32K

H6

NC

SE_CTLR_FW_DWLD

21

NC_SE_GPIO0

81

NC
NC
NC

R5042

MF1/20W 201

R5041

1/20W MF 201

20

20

BI

SPMI_SE_CLK

IN

SPMI_SE_DATA

1

R5050

1M

5% 5%
1/20W
MF
201

2

5%

5%

47K

47K

1

R5051

1M

1/20W
MF
201

2

21

UART_SE_R2D_RTS_L
NC_UART_SE_D2R_CTS_L

NO_TEST

21

UART_SE_R2D
NC_UART_SE_D2R

21

SE_DEV_WAKE

NO_TEST

NC
NC

NC

NC
NC

NC

NFC_CLK_REQ

A6

NFC_CLK_XTAL1

G4

NFC_DWL_REQ

F6

NFC_GPIO0

J7

NFC_GPIO1

J5

NFC_GPIO2_AO

H4

NFC_GPIO3_AO

E6

NFC_HSU_CTS

F5

NFC_HSU_RTS

G5

NFC_HSU_RX

E5

NFC_HSU_TX

E4

NFC_I2C_SCL

F4

NFC_I2C_SDA

J6

NFC_IRQ

G9

NFC_SIM_SWIO1

J8

NFC_SIM_SWIO2

H7

NFC_SPMI_SCLK

G7

NFC_SPMI_SDATA

H5

NFC_WKUP_REQ

B6

NFC_XTAL2

G6

TM

A3

RXP

A4

RXN

50K internal pull-down

U5000

SN210VUK/B101V7

WLCSP

OMIT_TABLE

NC

NCNCNC

TX1
TX2

VHV

VEN

H3

NC

F3

NC

G1
H1

F2

NC

F1

NC

G3

NC

G2

NC

J2

NC

H2

NC

E2

NC

D2

NC

D1

NC

B3

NC

C2

NC

A1

NC

C1

NC

D7

NC

C7

NC

B8
B9

B7

VHV_SE

D3

NC

D5

SE_PWR_EN

C5

VREF_SE

Pulls to be added in system, can be NC'd if unused

NC_I2C_SE_SCL
NC_I2C_SE_SDA

IN
BI

80

80

PP3V8_AON_VDDMAIN

34

IN

7921

SE_GPIO0
SE_GPIO1

SE_I2C_SCL
SE_I2C_SDA

SE_ISO_CLK

SE_ISO_IO

SE_ISO_RST

SE_SPI_CLK

SE_SPI_CS
SE_SPI_MISO
SE_SPI_MOSI

TXVCASCP
TXVCASCN

RXVCM
TXVCM

VCASCHI
VCASCLO

BOOST_LX
BOOST_LX

VTUNE

VREF

R5000
R5006

47K
47K

21

5% MF

21

2011/20W

MF1/20W5% 201

SE_CTLR_FW_DWLD
SE_DEV_WAKE

1

C5004

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C5017

0.22UF

20%

6.3V

2

X5R
0201

SYNC_DATE=03/29/2020SYNC_MASTER=ref_se_ceres

Secure Element

DRAWING NUMBER

051-05392

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

21

21

<rdar://problem/52067756> [SN200V] Wired Mode SE Only Reference Design Material
<rdar://problem/45108950> Mac - Venus Reference guide and De-coupling requirements

BOM_COST_GROUP=SECURE ELEMENT

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

evt-1

PAGE

50 OF 801

SHEET

21 OF 92

SIZE

D

8

CRITICAL

J5150

RCPT-BMU-ANGLED-X1764

STRUCTURE ONLY
STRUCTURE ONLY

Mates with x

F-RT-TH

PWR

PWR
SIGNAL
SIGNAL
SIGNAL

PWR

PWR

1
2
3
4
5
6
7
8
9

518-00040

1

C5150

0.1UF

10%
25V

2

X7R-CERM-1
0402

OMIT_TABLE

1

C5151

1UF

10%
16V
CER-X6S
0402

D51502

SC-75

RCLAMP2402B

PPVBAT_AON_CONN
I2C_SMC_PWR_3V3_SCL
I2C_SMC_PWR_3V3_SDA
SYS_DETECT_L

SYSDET:AON

1

R5150

10K

5%
1/20W
MF
201

2

23

43 82

IN

43 82

BI

3

SYSDET:FET

D

Q5155

NTNS4CS69N

XDFN

SYM_VER_2

376S00282

1

2

GS

PP3V8_AON_VDDMAIN

SYSDET:FET

1

R5155

10K

5%
1/20W
MF
201

2

79

SYS_DETECT

BMU output is enabled after power is
supplied by other means, such as USBC connector.
MLB is thus unpowered during system assembly.

BMU Connector, Btn Logic

8

*** OK2INTEGRATE ***

PPDCIN_AON_CHGR_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1800

VOLTAGE=20V

FROM USB-C SOURCE

79 23

PACK_OPTION=CHGR_TP_TOP

PPDCIN_AONSW

PP5201

P2MM

SM

1

23

PP

PLACE_SIDE=TOP

PACK_IGNORE=TRUE

CHGR_GATE_Q1

CRITICAL

1

C5201

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

CRITICAL

1

C5204

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PP5211

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

CRITICAL

1

C5202

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

CRITICAL

1

C5205

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

CRITICAL

1

C5203

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

CRITICAL

1

C5206

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

CRITICAL

1

C520A

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

1

C5205

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

R5220

0.01

0.5%

0.5W
MF

0306

NO_XNET_CONNECTION=1

(AMON)
2-CELL: 0.02 OHM
3-CELL: 0.01 OHM

107S00053

21
43

CRITICAL

1

C520B

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

1

C5206

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

1

C520C

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

1

C5207

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

1

C520D

2.2UF

20%
35V

2

X5R-CERM
0402

CRITICAL

L5230

2.7UH-20%-12.5A-0.0196OHM

CHGR_PHASE1

23 23

DIDT=TRUE
SWITCH_NODE=TRUE SWITCH_NODE=TRUE

CRITICAL

ALLOW_APPLE_PREFIX=Q

IHLP4040BD-PIMA102D-COMBO

152S00198

21

CRITICAL

ALLOW_APPLE_PREFIX=Q

CHGR_PHASE2

23

PPVBAT_AON_CHGR_REG

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=13.05V

CKPLUS_WAIVE=CAPDERATE

CKPLUS_WAIVE=CAPDERATE

CRITICAL

1

C5250

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

1

2

CRITICAL

1

C5254

33UF

20%
16V

2

TANT
CASED12-SM

CAPMAT=POLY-TANT

PACK_OPTION=CHGR_40W

1

2

CKPLUS_WAIVE=CAPDERATE

CRITICAL

C5251

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W

1

2

CRITICAL

C5255

33UF

20%
16V
TANT
CASED12-SM

CAPMAT=POLY-TANT

PACK_OPTION=CHGR_40W

1

2

CRITICAL

F5200

12A-32V-0.0045OHM

CKPLUS_WAIVE=CAPDERATE

CRITICAL

C5252

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

1

2

CRITICAL

C5256

2.2UF

20%
25V
X5R
0402-1

1206

21

1

2

CRITICAL

C5253

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W

CRITICAL

C5257

2.2UF

20%
25V
X5R
0402-1

TO SYSTEM

PPBUS_AON

1

2

C5258

1000PF

10%
25V
X7R
0201

79

PP5202

P2MM

SM

1

23

PP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PLACE_SIDE=TOP

PACK_OPTION=CHGR_TP_TOP

PACK_OPTION=CHGR_TP

PACK_OPTION=CHGR_TP

79 23

PACK_IGNORE=TRUE

PP5203

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5204

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5205

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5206

P2MM

SM

PP

PACK_IGNORE=TRUE

PP5207

P2MM

SM

PP

PP5208

P2MM

SM

PP

PPDCIN_AONSW

CHGR_GATE_Q2

1

23

CHGR_GATE_Q3

1

23

CHGR_GATE_Q4

1

23

CHGR_PHASE1

1

23

CHGR_PHASE2

1

CHGR_EN_MVR

1

CHGR_INT_1V8_L

78 24

PP1V8_S2

PP5212

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5213

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5214

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5215

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

PP5216

P2MM

SM

1

PP

PLACE_SIDE=BOTTOM

PACK_OPTION=CHGR_TP_BOT

23 24

23 24

1

R5215

750K

1%
1/20W
MF
201

2

NOSTUFF

C5216

0.01UF

X5R-CERM

1

10%
25V

2

0201

C5280

1.0UF

20%

6.3V
X5R

0201-1

1

2

PPVBAT_AON_CHGR_REG

23

C5278

2.2UF

X5R-CERM

CHGR_AUX_DET

1

R5216

255K

1%
1/20W
MF
201

2

CHGR_CSI_P CHGR_CSI_N

PLACE_NEAR=U5200.D5:2MM

R5221

1.00

1/20W
MF-LF

0201

CHGR_CSI_FILT_P

CRITICAL

1

10%
50V

2

0402

NO_XNET_CONNECTION=1

20%
35V

0402

C5221

0.047UF

CER-X7R

1

2

1%

2

CRITICAL

C5220

0.47UF

20%

4V

CERM-X5R-1

201

CRITICAL

C5270

0.12UF

10%
10V
X5R

0402

PLACE_NEAR=U5200.C5:2MM

1

R5222

1.00

1%
1/20W
MF-LF
0201

2

CHGR_CSI_FILT_N

CRITICAL

1

C5222

0.047UF

10%
50V

2

CER-X7R
0402

21

43

43

35

I2C_SMC_PWR_1V8_SDA

BI

I2C_SMC_PWR_1V8_SCL

IN

CHGR_RST_IN

IN

CHGR_COMP

NOSTUFF

CRITICAL

1

2

C5271

0.12UF

10%
10V
X5R

0402

PPVBAT_AON_CHGR_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

CHGR_GATE_Q1

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

CRITICAL

1

C5230

0.1UF

2

CHGR_GATE_Q2

2323 23

DIDT=TRUE
GATE_NODE=TRUE

2

XW5240

SMSM

1

10%
25V
X7R-CERM-1
0402

2

XW5230

1

CHGR_GATE_Q3

DIDT=TRUE

GATE_NODE=TRUE

CHGR_LX2

SWITCH_NODE=TRUE

CRITICAL

X7R-CERM-1

DIDT=TRUE

C5240

0.1UF

10%
25V

0402

1

2

CHGR_BOOT1_RC CHGR_BOOT2_RC

DIDT=TRUE
SWITCH_NODE=TRUE

1

R5230

0

5%
1/16W
MF-LF
402

2

CHGR_BOOT1

DIDT=TRUE
SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

R5240

0

5%
1/16W
MF-LF

402

CHGR_BOOT2

DIDT=TRUE

1

2

R5275

VOLTAGE=5V

24

PPCHGR_VDDA

CRITICAL

1

C5275

2.2UF

20%
25V

2

X5R-CERM
0402-1

4.7

5%

1/20W

MF

201

21

VOLTAGE=5V

PPCHGR_VDDP

CRITICAL

C5277

10UF

20%
10V
X5R

0603-1

1

2

XW5260

SM

21

PLACE_NEAR=Q5240.3:2MM

PLACE_NEAR=U5200.A4:2MM

CHGR_CSO_FILT_P

U5200

B5

P_IN

C5

CSIN

D5

CSIP

A5

PBUS_PWR

D3

AUX_DET

F5

VDDIO1P8

G5

SDA

H5

SCL

G2

SMC_RST_IN

G3

HPWR_EN*

E5

COMP

G4

B2
C2
E4

CELL

NC0
NC1

H:3-CELL

L:2-CELL

1

ISL9240HI

WCSP

CRITICAL

SCH SYMBOL

353S01525

(5V)

(OD)

GATE_Q1

BOOT1

LX1
GATE_Q2
GATE_Q3

LX2

BOOT2

GATE_Q4

PBUS
CSOP
CSON

BGATE

VBAT

EN_VR1

SMC_RST*

IRQ*
CBC_ON
EN_MVR
AUX_OK

AMON

BMONNC2

H1
F1
G1
E1
D1
B1
C1
A1
A3
A4
B4
B3
C3
F2
H4
H3
H2
F4
F3
D4
C4

CHGR_PBUS_SNS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CHGR_BGATE
CHGR_VBAT

NC_CHGR_EN_VR1

NC_CHGR_SMC_RST_L

CHGR_INT_1V8_L

NC_CHGR_CBC_ON
CHGR_EN_MVR
CHGR_AUX_OK
CHGR_AMON
CHGR_BMON

CHGR_GATE_Q4

DIDT=TRUE
SWITCH_NODE=TRUE

NO_XNET_CONNECTION=1

23

CRITICAL

R5260

0.005

0612-8

1 2
3 4

(BMON)
2-CELL: 0.010 OHM

1%

3-CELL: 0.005 OHM

1W
MF

107S00087

CHGR_CSO_P CHGR_CSO_N

1

PLACE_NEAR=U5200.B4:2MM

1

R5261

1.00 1.00

1%

2

1/20W
MF-LF

0201

R5262

1%
1/20W
MF-LF
0201

2

CHGR_CSO_FILT_N

CRITICAL

C5261

0.047UF

10%
50V

CER-X7R

0402

1

2

CRITICAL

1

C5262

0.047UF

10%
50V

2

CER-X7R
0402

CRITICAL

C5260

0.47UF

21

20% 4V

CERM-X5R-1

201

NO_XNET_CONNECTION=1

81

81

23 24

OUT

81

23 24

OUT

24

OUT

44

OUT

44

OUT

CRITICAL

Q5265

SI7655DN-COMBO

PWRPK-1212-8

SYM-VER-2

S

3
2
1

G

4

C5264

1000PF

21

10%
25V
X7R

0201

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

NTNS4CS69N

1

R5263

1K

5%
1/20W
MF
201

2

D

1

C5263

4700PF

10%
25V

2

CER-X5R
0201

CRITICAL

Q5270

SYM_VER_1

SAVE_BAT_S SAVE_BAT_G

CRITICAL

1

C5265

2.2UF

20%
25V

2

X5R
0402-1

5

XDFN

R5270

24K

1/20W

5%
MF

201

3

D

G

S

2

1

2

CRITICAL

1

C5266

2.2UF

20%
25V

2

X5R
0402-1

1

C5269

0.1UF

10%
25V

2

X5R
0201

<rdar://37259372&39763505>

1

CRITICAL

D5270

DFN0201

ALLOW_APPLE_PREFIX=D

GDZ5V6LP3-55

SYNC_MASTER=ref_charger_suona SYNC_DATE=05/02/2020

PAGE TITLE

PBUS SUPPLY & BATTERY CHARGER

CRITICAL

1

C5267

0.1UF

10%
25V

2

X5R
0201

CRITICAL

1

C5268

0.01UF

10%
25V

2

X5R-CERM
0201

PPDCIN_AONSW

1

R5271

200K

1%
1/20W
MF
201

2

TO/FROM BATTERY

PPVBAT_AON_CONN

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

7923

22

Apple Inc.

2

*** OK2INTEGRATE ***

CHGR I2C Level Translation

SMBUS_CHGR_1V8_[SCL/SDA]: Level translation circuit to be placed in project specific I2C page.

CHGR_INT_L Level Translation

Stuff R5320 in case, glitch during power sequencing is a concern.

78 23

PP1V8_S2

NOSTUFF

1

R5320

47K

5%
1/20W
MF
201

2

PP1V25_S2

78

PLACE_NEAR=U5320.6:5MM

1

C5320

0.1UF

10%

6.3V

2

CERM-X5R
0201

U5320

SN74AUP1G17

GND

SON

Y

4

CHGR_INT_L

VCC

23 80

CHGR_INT_1V8_L

2

A

NC

NC

CHGR_AUX_OK Pull Up

Pull up to MPMU LDO9, or rely on MPMU internal pull up.
OK, to completely remove pull up , but consult PMU architecture and check OTP before that.

PP1V8_AON_MPMU

78

NOSTUFF

1

R5330

47K

5%
1/20W
MF
201

2

>> SOC NUB_GPIO_5

OUTIN

23

IN

CHGR_AUX_OK

Delay for 3.8V VR Enable

RDAR://59315467
R5340 and C5340 might need tweaking afer charz.

R5342

2.2K

1/20W

R5340

23

IN

CHGR_EN_MVR

200K

1/20W

5%
MF

201

1%
MF

201

21

CHGR_EN_MVR_A

21

CHGR_EN_MVR_DLY

1

C5340

1UF

20%
10V

2

X5R
0201

CHGR_AUX_OK

MAKE_BASE=TRUE

D5340

X3DFN2

KA

NSR01L30MXT5G-COMBO

PPCHGR_VDDA

23

PLACE_NEAR=U5340.5:2MM

1

C5341

0.1UF

10%

6.3V

2

CERM-X5R
0201

>> MPMU GPIO2

34

OUT

NOSTUFF

R5341

0

5%

1/20W

MF

0201

2

NC

21

5

1 3

U5340

74LVC1G17

X2SON5

4

PLACE_NEAR=U5200:5MM

P3V8AON_PWR_EN

OUT

25

BOM_COST_GROUP=BATTERY

PAGE TITLE

BATTERY CHARGER SUPPORT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

53 OF 801

SHEET

24 OF 92

1

SYNC_DATE=05/02/2020SYNC_MASTER=ref_charger_suona

SIZE

D

*** OK2RELEASE ***

3V8 AON CONTROLLER

79 26

5.5 < VIN < 13.5 V

27

4.75 < VDRV < 5.5 V
VDRV IS EXTERNAL OPTION TO
POWER IC INSTEAD OF VIN
TO SAVE POWER

79

4.75 < LDO5 < 5.25 V
MAX I_OUT TYP 160 MA
LDO5 NOT TO BE USED BY
SYSTEM IN 30A DESIGNS

26

PPBUS_AON

1

C5704

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

BYPASS=U5700.8::15MM

PP5V_S2_P3V8AON_VDRV

1

C5700

10UF

20%
16V

2

X6S
0603-1

138S00248

BYPASS=U5700.6::15MM

0603 SIZE REQUESTED BY DCDC

PP5V_AON_P3V8VRLDO

1

C5702

10UF

20%
16V

2

X6S
0603-1

138S00248

BYPASS=U5700.7::15MM

0603 SIZE REQUESTED BY DCDC

P3V8AON_PVCC

8

6

7

5

VIN

VDRV

LDO5

PVCC

U5700

RAA225501A-BOM1

OMIT_TABLE

"BOM1" SCH SYMBOL

FOR 30A OTP

APN OF SYMBOL

353S02326

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

BOOT3

UGATE3

PHASE3

LGATE3

4

3

2

1

29

30

31

32

28

27

26

25

F_SW IS REGISTER CONTROLLED
ICCMAX 30A DESIGN: 1 MHZ

P3V8AON_BST1
P3V8AON_DRVH1
P3V8AON_SW1
P3V8AON_DRVL1

P3V8AON_BST2
P3V8AON_DRVH2
P3V8AON_SW2
P3V8AON_DRVL2

P3V8AON_BST3
P3V8AON_DRVH3
P3V8AON_SW3
P3V8AON_DRVL3

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

26

26

26 27

26

26

26

26 83

26

26

26

26 83

26

1

ONLY FOR USE BY GATE
DRIVE CIRCUITRY

R5710

0

5%
MF

0201

21

24

IN

P3V8AON_PWR_EN

1/20W

C5701

10UF

20%
16V

2

X6S
0603-1

138S00248

BYPASS=U5700.5::15MM

0603 SIZE REQUESTED BY DCDC

27

P3V8AON_PWR_EN_R

VIH_MAX 1.07 V
VIL_MIN 0.63 V

ENABLE

(9M PD)

VSEN

VRTN

15

16

P3V8AON_VSENSE

P3V8AON_VRTN

IN

IN

26 27

26

R5711

0

5%
MF

0201

21

35

IN

P3V8AON_LPM

1/20W

27

P3V8AON_LPM_R

VIH_MAX 1.1 V
VIL_MIN 0.5 V

P3V8AON_LPM

79

27

PP5V_AON_P3V8VRLDO

PU TO INT LDO5 OR OTHER RAIL

P3V8AON_FAULT_L

1

R5712

47K

5%
1/20W
MF
201

2

25

25

I2C_P3V8AON_SCL
I2C_P3V8AON_SDA

VIH_MAX 1.1 V
VIL_MIN 0.5 V
GND'ED FOR POR (DATASHEET TABLE 1.5)

FAULT PULL DOWN CURRENT 1-2 MA TYPICAL

13

10

9

14

LPM

SCL

SDA

FAULT*

(9M PD)

(OD)

CSP1

CSN1

CSP2

CSN2

19

20

21

22

P3V8AON_ISEN1_P
P3V8AON_ISEN1_N

P3V8AON_ISEN2_P
P3V8AON_ISEN2_N

IN

IN

IN

IN

26

26

26

26

P3V8AON_IMON

IMON NOT TO BE USED SYSTEM SIDE
<RDAR://58648650>
IMON IS 2.52 V @ 30 A
VENDOR REQUIRES R > 1M, C < 50 PF

1

C5751

10PF

5%
25V

2

C0G
0201

131S00003

NOSTUFF

1

R5751

2.21K

1%
1/20W
MF
201

2

118S0199

R5750

1M

5%

1/20W

MF

201

117S0009

21

P3V8AON_IMON_P3V8AON

P3V8AON_GPIO

OPEN FOR PRODUCTION APPLICATION
PER DATASHEET REV 1.0

P3V8AON_SS

LONG STARTUP TIME SO INRUSH

NOSTUFF

1

R5700

100K

5%
1/20W
MF
201

2

BELOW 0.5A USB LIMIT

1

C5703

0.22UF

10%
25V

2

X5R
0201-1

18

IMON

11

GPIO

17

SOFTSTART

(0-4.5V)

CSP3

CSN3

EPAD

23

24

P3V8AON_ISEN3_P

P3V8AON_ISEN3_N

IN

IN

26

26

132S00202

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 U5700 CRITICAL353S02472 IC,RAA225501B,ICE,BOM1,A1,OTP-R0B0,QFN32 P3V8AON_IC:A1_R0B0

BOM OPTIONCRITICAL

P3V8AON_IC:A0CRITICALU57001353S02326 IC,RAA225501,3-PH VOLT REG,TQFN32

TABLE_5_H EAD

TABLE_5_I TEM

TABLE_5_I TEM

3V8_AON_I2C-DEV

NOSTUFF

1

R5760

1K

5%
1/20W
MF
201

2

3V8_AON_I2C-DEV

1

R5762

0

5%
1/20W
MF
0201

2

80

TPT_P3V8AON_PU_RAIL

3V8_AON_I2C-DEV

NOSTUFF

1

R5761

1K

5%
1/20W
MF
201

2

3V8_AON_I2C-DEV

1

R5763

0

5%
1/20W
MF
0201

2

TP5700

1

TP

TP-P5

3V8_AON_I2C-DEV

GND

MAKE_BASE=TRUE

CKPLUS_WAIVE=I2C_PULLUP

I2C_P3V8AON_SCL

CKPLUS_WAIVE=I2C_PULLUP

I2C_P3V8AON_SDA

3V8_AON_I2C-POR3V8_AON_I2C-POR

GND

MAKE_BASE=TRUE

SYNC_MASTER=ref_vr_iceman SYNC_DATE=04/20/2020

PAGE TITLE

25

25

051-05392

SIZEDRAWING NUMBER

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

BOM_COST_GROUP=PLATFORM POWER

5 478

8

*** OK2RELEASE ***

79 26 25

PPBUS_AON

CRITICAL

R5804

2.2

5%
MF

201

21

C5811

0.1UF

21

10%
25V

X7R-CERM-1

0402

132S0438

P3V8AON_DRVH1_R

27

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_SW1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

25 27

OUT

CRITICAL

Q5800

CSD58889Q3D

376S00012

3

TG

4

TGR

Q3D

VIN

VSW

1

6
7
8

83 83

25

IN

P3V8AON_DRVH1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

1/20W

117S0056

<RDAR://59524111>

R5803

0

5%
MF

0201

21

25

OUT

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

1/20W

117S0201

NOSTUFF

P3V8AON_BST1_RCP3V8AON_BST1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

D5800

SOD523

KA

5

BG

R5805

1

5%
1/16W
MF-LF

402

116S0006

21

P3V8AON_DRVL1_R

27

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

2526

25

IN

P3V8AON_PVCC

P3V8AON_DRVL1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

SBR1A30T5

371S00245

3V8_EXT_DIODE

1

C5800

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

P3V8AON_VSW1 PP3V8AON_PH1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

116S0007

1

R5809

1.5

5%
1/16W
MF-LF
402

2

P3V8AON_SNUB1

SWITCH_NODE=TRUE
DIDT=TRUE

CRITICAL

C5801

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

CRITICAL

1

C5800

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D12

1

2

NOSTUFF

C5814

220PF

5%
50V
C0G
0201-1

CRITICAL

1

C5801

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D12

1UH-20%-11A-0.0127OHM

NO_XNET_CONNECTION=1

1

C5810

5600PF

10%
10V

2

CERM-X7R
0201

132S0370

CRITICAL

1

C5800

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

CRITICAL

L5800

PIHA052D-SM

152S00265

R5801

2 1

118S0744

R5802

131S0514

1

C5809

150PF

5%
50V

2

C0G-CERM
0402

<RDAR://59524111>

25

OUT

P3V8AON_ISEN1_P

NOSTUFF

1

C5815

220PF

5%
50V

2

C0G
0201-1

118S0744

CRITICAL

1

C5801

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

21

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=5V

1.00

1%
1/20W
MF-LF

0201

1.00

1%
1/20W
MF-LF

0201

P3V8AON_ISNS1_P

21

P3V8AON_ISNS1_N

1

C5804

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

MIRROR_WITH=C5804

1

C5805

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

107S00373

R5800

0.004

1%

1/3W

LF

0306

NO_XNET_CONNECTION=1

21
43

27

ICCMAX = 30 A

PP3V8_AON_VDDMAIN

CRITICAL

1

C5890

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

MIRROR_WITH=C5887

1

C5886

2.2UF

20%
25V

2

27

X6S-CERM
0402

CRITICAL

1

C5891

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

1

C5887

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042138S00042

CRITICAL

1

C5892

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

MIRROR_WITH=C5889

1

C5888

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

1

C5893

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

1

C5889

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

1

C5894

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

CRITICAL

1

C5895

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

128S00067

CKPLUS_WAIVE=CAPDERATE

79

79 26 25

25

OUT

P3V8AON_ISEN1_N

PPBUS_AON

CRITICAL

1

C5820

ALLOW_APPLE_PREFIX=Q

R5824

1.5

5%

1/8W

TK

0402

21

25

IN

P3V8AON_DRVH2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_DRVH2_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

Q5820

AONE36196

DFN

376S00281

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

CRITICAL

1

C5821

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

CRITICAL

1

C5820

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D12

107S00371

8

D1

R5823

0

25

OUT

P3V8AON_BST2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

1/16W

MTL-FILM

21

0%

0402

116S00006

P3V8AON_BST2_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

C5831

0.22UF

21

10%
25V
X7R

0402

132S0401

P3V8AON_SW2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

25 26 83

OUT

1

G1

2
3

D2/S1

4

NOSTUFF

D5820

SOD523

0.100

1%

1/4W

MF

0402

KA

R5826

21

P3V8AON_DRVL2_R

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

0.100

1%

1/4W

MF

0402

104S0050

21

P3V8AON_DRVL2_RR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

VER-1

2526

P3V8AON_PVCC

SBR1A30T5

371S00245

3V8_EXT_DIODE

R5825

25

IN

25

OUT

25

OUT

P3V8AON_DRVL2

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_ISEN2_P
P3V8AON_ISEN2_N

104S0050

D1

G2

9

SAME SW NET
ON BOTH SIDES

252683

IN

7

P3V8AON_SW2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

1

R5829

2.2

5%
1/16W
MF-LF
402

2

NOSTUFF

DIDT=TRUE
SWITCH_NODE=TRUE

P3V8AON_SNUB2

1

C5829

100PF

5%
50V

2

C0G
0402

NOSTUFF

CRITICAL

1

C5820

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

NOSTUFF

1

C5834

220PF

5%
50V

2

C0G
0201-1

NOSTUFF

1

C5835

220PF

5%
50V

2

C0G
0201-1

MIRROR_WITH=C5824

1

C5824

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

1

C5825

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

L5820

0.56UH-20%-22.0A-0.0067OHM

21

PP3V8AON_PH2

83

PILA062D-SM-COMBO

152S01248

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=5V

R5821

2 1

NO_XNET_CONNECTION=1

1

C5830

5600PF

10%
10V

2

CERM-X7R
0201

132S0370

118S0744

R5822

118S0744

1.00

1%
1/20W
MF-LF

0201

1.00

1%
1/20W
MF-LF

0201

P3V8AON_ISNS2_P

21

P3V8AON_ISNS2_N

107S00090

R5820

0.001

1%

1/3W

MF

0306

NO_XNET_CONNECTION=1

21
43

27

27

79 26 25

PPBUS_AON

CRITICAL

ALLOW_APPLE_PREFIX=Q

R5844

1.5

5%

1/8W

TK

0402

21

25

IN

P3V8AON_DRVH3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_DRVH3_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

Q5840 2

AONE36196

DFN

376S00281

107S00371

8

D1

9

R5843

0

25

OUT

P3V8AON_BST3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

1

0%

1/16W

MTL-FILM

0402

116S00006

P3V8AON_BST3_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

DIDT=TRUE
SWITCH_NODE=TRUE

C5851

0.22UF

21

10%
25V
X7R

0402

132S0401

P3V8AON_SW3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

25 26 83

OUT

1

G1

2
3

D2/S1

4

D1

NOSTUFF

D5840

SOD523

0.100

1%

1/4W

MF

0402

KA

G2

7

R5846

21

P3V8AON_DRVL3_R

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

0.100

1%

1/4W

MF

0402

104S0050

21

P3V8AON_DRVL3_RR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

VER-1

2526

P3V8AON_PVCC

SBR1A30T5

371S00245

3V8_EXT_DIODE

R5845

25

IN

25

OUT

25

OUT

P3V8AON_DRVL3

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

GATE_NODE=TRUE
DIDT=TRUE

P3V8AON_ISEN3_P
P3V8AON_ISEN3_N

104S0050

1

C5840

33UF

20%
16V
TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12

252683

IN

SAME SW NET
ON BOTH SIDES

P3V8AON_SW3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
DIDT=TRUE

1

R5849

2.2

5%
1/16W
MF-LF
402

2

P3V8AON_SNUB3

1

C5849

100PF

5%
50V

2

C0G
0402

CRITICAL

1

C5841

33UF

20%
16V

2

TANT
CASE-T

128S00009

CKPLUS_WAIVE=CAPDERATE

3V8_AON_PBUS-B12 3V8_AON_PBUS-D12

NOSTUFF

DIDT=TRUE
SWITCH_NODE=TRUE

NOSTUFF

CRITICAL

1

C5840

33UF

20%
16V

2

TANT
CASED12-SM

128S0436

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE

CRITICAL

1

C5840

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

128S0264

CKPLUS_WAIVE=CAPDERATE

PACK_IGNORE=TRUE
3V8_AON_PBUS-D2

NOSTUFF

1

C5854

220PF

5%
50V

2

C0G
0201-1

NOSTUFF

1

C5855

220PF

5%
50V

2

C0G
0201-1

MIRROR_WITH=C5844

1

C5844

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

1

C5845

2.2UF

20%
25V

2

X6S-CERM
0402

138S00042

CRITICAL

L5840

0.56UH-20%-22.0A-0.0067OHM

21

PP3V8AON_PH3

83

PILA062D-SM-COMBO

152S01248

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=5V

R5841

2 1

NO_XNET_CONNECTION=1

1

C5850

5600PF

10%
10V

2

CERM-X7R
0201

132S0370

118S0744

R5842

118S0744

1.00

1%
1/20W
MF-LF

0201

1.00

1%
1/20W
MF-LF

0201

P3V8AON_ISNS3_P

21

P3V8AON_ISNS3_N

107S00090

R5840

0.001

1%

1/3W

MF

0306

NO_XNET_CONNECTION=1

21
43

27

NO_XNET_CONNECTION=1

XW5870

2 1

SM

NO_XNET_CONNECTION=1

P3V8AON_VSNS_XW_P

27

XW5871

2 1

SM

27

P3V8AON_VSNS_XW_N

BOM_COST_GROUP=PLATFORM POWER

NO_XNET_CONNECTION=1

R5870

0

21

5%

1/20W

MF

0201

117S0201

NO_XNET_CONNECTION=1

R5871

0

21

5%

1/20W

MF

0201

NOSTUFF

1

C5870

1UF

20%
10V

2

X6S-CERM
0201

138S00044

NO_XNET_CONNECTION=1

P3V8AON_VSENSE

P3V8AON_VRTN

OUT

OUT

25 27

25

117S0201

SYNC_MASTER=ref_vr_iceman SYNC_DATE=04/20/2020

PAGE TITLE

POWER: 3V8 AON (2/2)

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

58 OF 801

SHEET

26 OF 92

PP5V_S2 to PP3V8_AON VDRV Connection

R5900

0

79

PP5V_S2

5%
1/16W
MF-LF

402

21

PP5V_S2_P3V8AON_VDRV

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000

PP5V_S2_P3V8AON_VDRV

CBA PPBUS_AON Bulk CapacitancePP3V8_AON Probe Points

PPBUS_AON

998-0955

25

PP5900

SM

PP

1

P4MM

P3V8AON_DRVH1_R

26

PP5901

P4MM

SM

PP

1

P3V8AON_SW1

25 26

PP5902

P4MM

SM

PP

1

GND

PP5903

SM

PP

1

P4MM

PP5904

SM

PP

1

P4MM

PP5905

SM

PP

1

P4MM

P3V8AON_DRVL1_R

P3V8AON_PWR_EN_R

P3V8AON_FAULT_L

26

25

25

PP5906

SM

PP

1

P4MM

PP5907

SM

PP

1

P4MM

PP5908

SM

PP

1

P4MM

P3V8AON_LPM_R

P3V8AON_VSNS_XW_P

P3V8AON_VSENSE

25

26

25 26

79

NOSTUFFNOSTUFFNOSTUFFNOSTUFFNOSTUFF

1

C5960

68UF 68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C5961

2

20%
16V
POLY-TANT
CASE-D2E-SM

1

C5962

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C5963

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C5964

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

D

PP3V8_AON Current Sense

NO_XNET_CONNECTION=1

26

IN

26

IN

26

IN

26

IN

26

IN

26

IN

P3V8AON_ISNS3_P

P3V8AON_ISNS2_P

P3V8AON_ISNS1_P

P3V8AON_ISNS1_N

P3V8AON_ISNS2_N

P3V8AON_ISNS3_N

R5924

NO_XNET_CONNECTION=1

R5922

NO_XNET_CONNECTION=1

R5920

NO_XNET_CONNECTION=1

R5921

NO_XNET_CONNECTION=1

R5923

NO_XNET_CONNECTION=1

R5925

1/20W 0.1%

0.1% MF-LF1/20W 0201

118S0714

0.1%1/20W 0201

118S0714

0.1% 0201MF 103S03171/20W

0.1%

103S0317

0.1%1/20W

118S0714

118S0714

21

5K

21

5K

MF-LF

21

20K

21

20K

MF1/20W

21

5K

21

5K

MF-LF 0201

P3V8AON_ISNSP

0201

0201MF-LF

117S0201

R5912

R5913

5%1/20W MF 0201

117S0201

P3V8AON_ISNS_SH

79 27

21

0

MF1/20W 5%

21

0

27

P3V8AON_ISNS_RP

0201

P3V8AON_ISNS_RNP3V8AON_ISNSN

1

R5914

324K

0.1%
1/20W
MF
0201

2

103S00053

1

R5916

0

5%
1/20W
MF
0201

2

117S0201

PP3V8_AON_VDDMAIN

1

+

3

-

R5911

0.1%

1/20W

103S00053

NO_XNET_CONNECTION=1

21

324K

353S1429

U5910

OPA333DCKG4

5

SC70-5-COMBO

V+

V-

2

P3V8AON_ISNS_FB

MF

0201

1

2

P3V8AON_ISUM_IOUT

R5917

5%

1/20W 0201

0

117S0201

BYPASS=U5910.5::5MM

C5910

1UF

20%
10V
X6S-CERM
0201

138S00044

21

MF

PLACE_NEAR=U8100.E14:5MM

118S0385

R5915

1

R5910

100K

5%
1/20W
MF
201

2

117S0008

1% MF1/20W

21

45.3K

201

NOSTUFF

1

R5918

3.32M

1%
1/20W
MF-LF
0201

2

118S0759

P3V8AON_IMEAS

1

C5915

2.2UF

20%
10V

2

X5R
0201

138S00136

VSS_SENSOR_MPMU

47

OUT

4744

E

LTSpice:

344044

PP3V8_AON Current Sense Cal Control Circuit

PP3V8_AON_VDDMAIN

79 27

IN

SENSOR_PWR_EN

1/20W MF5%

R5930

0

21

SENSOR_PWR_EN_R

0201

376S0855

DMN5L06VK-7

Q5930

SOT563

VER-3

2

SENSOR_PWR_EN_CAL

6

D

SG

1

117S0008

R5931

100K

5%

1/20W

MF

201

1

2

DMN5L06VK-7

NOSTUFF

1

C5930

47PF

5%
25V

2

C0G
0201

131S0806

P3V8AON_ISNS_RP

27

376S0855

Q5930

SOT563

VER-3

5

PLACE_NEAR=R5912.2:5MM

NOSTUFF

118S0176

R5932

P3V8AON_ISNS_CAL

3

D

SG

4

200K

1%

1/20W

MF

201

1

2

$X1757GHUB/mlb/sim/ltspice/pp3v8_aon_vddmain/pp3v8_aon_vddmain_current_sense.asc

BOM_COST_GROUP=PLATFORM POWER

PAGE TITLE

POWER: 3V8 AON SUPPORT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/11/2019SYNC_MASTER=T585_REF_VR_ICEMAN_0.36.0

DRAWING NUMBER

051-05392

REVISION

4.0.0

BRANCH

evt-1

PAGE

59 OF 801

SHEET

27 OF 92

SIZE

D

2

1

SLAVE PMU BUCKS

PP3V8_AON_VDDMAIN

29 28

79

1

C7700

10UF

20%

6.3V

2

0402 0402 0402 0402

1

C770A

1UF

10V

2

X6S-CERM

1

C7701

10UF

20%

6.3V

2

1

C770B

1UF

10V

2

X6S-CERM

1

C7702

10UF

20%

6.3V

2

CER-X6S
0402

1

C770C

1UF

10V

2

X6S-CERM

1

C770K

1UF

20%
10V

2

X6S-CERM

1

C7703

10UF

20%

6.3V

2

1

C770D

1UF

20%
10V

2

X6S-CERM

PLACE_NEAR=U7700.L1:5MM

1

C770L

10V 25V

2

X6S-CERM
02010201

1

C7704

10UF

20%

6.3V

2

0402

1

C770E

1UF

20% 20%20%20%20%20%20%20%20%
10V

2

X6S-CERM
0201 020102010201020102010201020102010201

PLACE_NEAR=U7700.L1:5MM

1

C770M

12PF

5%20%
25V

2

NP0-C0G
0201

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C7705

10UF

20%

6.3V

2

CER-X6SCER-X6SCER-X6SCER-X6SCER-X6S

1

C770F

1UF

10V

2

X6S-CERM

PLACE_NEAR=U7700.C13:5MM

1

C770N

3PF

+/-0.1PF 5%
25V

2

C0G
0201

1

C7706

1UF

10V

2

X6S-CERM
0201

1

C770G

1UF

10V

2

X6S-CERM

PLACE_NEAR=U7700.C13:5MM

1

C771M

12PF

25V

2

NP0-C0G
0201

1

C7707

1UF

10V

2

X6S-CERM
0201 0201

1

C770H

1UF

10V

2

X6S-CERM

1

C771N

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7708

1UF

20%20%20%

2

X6S-CERM

1

C770I

1

2

1

1UF

10V

2

X6S-CERM

PLACE_NEAR=U7700.G13:5MM

PLACE_NEAR=U7700.G13:5MM

1

C772M

12PF1UF

5%

2

NP0-C0G
0201

2

1

2

C7709

1UF

20%
10V10V
X6S-CERM
0201

C770J

1UF

10V
X6S-CERM

C772N

3PF

+/-0.1PF
25V
C0G
0201

C13

VDD_BUCK5_4_10

C14

VDD_BUCK5_4_10

G13

VDD_BUCK5_4_10

G14

VDD_BUCK5_4_10

M2

VDD_BUCK6

N2

VDD_BUCK6

P2

VDD_BUCK6

N6

VDD_BUCK12

P6

VDD_BUCK12

L13

VDD_BUCK13

L14

VDD_BUCK13

L1

VDD_MAIN_BUCK6

U7700

SIM

BGA

SYM 1 OF 4

OMIT_TABLE

BUCK4_LX0

BUCK4_LX1
BUCK4_LX1

BUCK4_FB

BUCK4_VSS_FB

BUCK5_LX_0
BUCK5_LX_1

BUCK5_FB

BUCK5_VSS_FB

F14

D13
D14

F11

PLACE_NEAR=U7700.F11:5MM

F12

H13
H14

H11

H12

31

SWITCH_NODE=TRUE

31

SWITCH_NODE=TRUE

BUCK4_FB

31

BUCK5_FB

PLACE_NEAR=U7700.H12:5MM

BUCK4_LX0

DIDT=TRUE

BUCK4_LX1

DIDT=TRUE

R770A

5%

VSS_ANA_SPMU

BUCK5_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

R770B

1/20W MF

5%

0

MF1/20W

0

CRITICAL

L7740

1.0UH-20%-4A-0.038OHM

PIKA20161B-COMBO

CRITICAL

L7741

0.22UH-20%-6.7A-0.023OHM

PINA20121T-SM

21

BUCK4_FB_R

0201

313028

CRITICAL

L7750

NO_XNET_CONNECTION=1

0.47UH-20%-4A-0.027OHM

2012

XW7701

SHORT-14L-0.1MM-SM

21

BUCK5_FB_R

0201

NO_XNET_CONNECTION=1

21

21

XW7700

SHORT-14L-0.1MM-SM

21

21

21

CRITICAL

CRITICAL

1

C7750

15UF

20%
2V

2

X6S
0402

CRITICAL

1

C7740

15UF

20%
2V

2

X6S
0402

1

C7713

15UF

20%
2V

2

X6S
0402

1

C7751

15UF

20%
2V

2

X6S
0402 0402

1

C7741

15UF

20%

2

X6S
0402

1

C7712

15UF

20%
2V

2

X6S
0402

1

C7752

15UF

20%
2V

2

CRITICAL CRITICAL

1

C7742

15UF

20%
2V

2

X6S
0402

1

2

CRITICALCRITICALCRITICALCRITICAL

1

C7711

15UF

20%
2V

2

X6S
0402

1

C7753

15UF

20%
2V

2

X6S
0402

1

2

1

C7754

15UF

20%
2V

2

0402

C7743

15UF 15UF

20%
2V
X6S
0402

C7710

15UF

20%
2V
X6S
0402

1

C7744

20%
2V

2

X6S
0402

PLACE_NEAR=L7740.2:5MM

1

C777M

12PF

5%
25V

2

NP0-C0G
0201

1

C7755

15UF

20%
2V

2

X6SX6SX6S
0402

1

C7745

15UF

20%
2V

2

X6S
0402

PLACE_NEAR=L7741.2:5MM

1

C777N

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7756

15UF

20%
2V

2

X6S
0402

PP1V06_S2SW_DRAM

CRITICAL

1

C7746

15UF

20%
2V2V

2

X6S
0402

PP0V764_S1_SRAM

PLACE_NEAR=L7750.2:5MM

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C7757

15UF

20%
2V

2

X6S
0402

1

C778M

12PF

5%
25V

2

NP0-C0G
0201

CRITICALCRITICALCRITICALCRITICAL

1

C7747

15UF

20%
2V

2

X6S
0402

1

C778N

3PF

+/-0.1PF
25V

2

C0G
0201

78

78

PLACE_NEAR=U7700.M2:5MM

PLACE_NEAR=U7700.M2:5MM

1

C773M

12PF

5%
25V 25V25V

2

NP0-C0G
0201

FED BY SPMU BUCK13 (1.2V)POWER ALIAS=>

FED BY MPMU BUCK3 (1.8V)POWER ALIAS=>

1

C773N

3PF

+/-0.1PF
25V

2

C0G
0201

PLACE_NEAR=U7700.N6:5MM

PLACE_NEAR=U7700.N6:5MM

1

C774M

1

12PF

2

NP0-C0G

PLACE_NEAR=U7700.D4:5MM

2

29

PLACE_NEAR=U7700.G10:5MM

PLACE_NEAR=U7700.L13:5MM

PLACE_NEAR=U7700.L13:5MM

1

C774N

3PF

+/-0.1PF
25V
C0G
0201

C775M

12PF

5%5%

2

NP0-C0G
02010201

PP1V5_VLDOINT_SPMU

29

79 29 28

PP5V_BSTLQ_SPMU

VOLTAGE=5V

PP1V25_S2

78

PP1V8_S2

78

PLACE_NEAR=U7700.D9:5MM

1

C775N

3PF

+/-0.1PF
25V

2

C0G
0201

1

2

PP3V8_AON_VDDMAIN

CRITICALCRITICAL CRITICAL

1

C7717

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U7700.L7:5MM

1

2

CRITICAL

1

C7716

0.1UF

10%
10V

2

X6S-CERM
0201

PLACE_NEAR=U7700.D9:5MM

31 30 28

1

C776N

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7715

0.1UF

10%
10V

2

X6S-CERM
0201

VSS_ANA_SPMU

C776M

12PF

5%
25V
NP0-C0G
0201

PLACE_NEAR=U7700.C9:5MM

C7714

0.1UF

10%
10V
X6S-CERM
0201

CRITICAL

1

C771A

0.1UF

10%
10V

2

X6S-CERM
0201

L9

E8

D2
E2

D8

E10

C12

D3
E7

G12

K3
L8

L12

M6

D5

D10

J3

J10

D9

B2
C2

E9

D4
L4

L7
M10
J11
A11

C9

G10

H10

K6

PLACE_NEAR=U7700.H10:5MM

VDD_MAIN_SOUTH

VDD_MAIN

VDD_MAIN_LDO
VDD_MAIN_LDO

VDD_MAIN_SNS

VDD_SNS_SPARE

VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA

VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG

VDD_BOOST

VDD_BOOST_LDO
VDD_BOOST_LDO

VDD_BOOST_SNS

VDD_HI_INT1
VDD_HI_INT2
VDD_HI_INT3
VDD_HI_INT4
VDD_HI_INT5
VDD_HI_INT6
VDD_HI_INT7

VDDIO_1V2

VDDIO_BUCK3

VPP

BUCK6_LX_0
BUCK6_LX_1
BUCK6_LX_2

BUCK6_FB

BUCK6_VSS_FB

BUCK6_VOUT_0
BUCK6_VOUT_1
BUCK6_VOUT_2

BUCK10_LX_0
BUCK10_LX_1

BUCK10_FB

BUCK10_VSS_FB

BUCK12_LX_0
BUCK12_LX_1

BUCK12_FB

BUCK12_VSS_FB

BUCK13_LX_0
BUCK13_LX_1

BUCK13_FB

BUCK13_VSS_FB

M3
N3

P3

L3

K2

M1
N1
P1

B13
B14

B11

B12

N5
P5

L5

M5

K13
K14

K11

K12

31

BUCK6_FB

31

BUCK10_FB

PLACE_NEAR=U7700.B11:5MM

31

BUCK12_FB

PLACE_NEAR=U7700.L5:5MM

31

BUCK13_FB

PLACE_NEAR=U7700.K11:5MM

VSS_ANA_SPMU

BUCK6_LX0

R770C

1/20W

PLACE_NEAR=U7700.L3:5MM

5%

VSS_ANA_SPMU

PP2V5_AWAKE_NAND

BUCK10_LX0

DIDT=TRUE

SWITCH_NODE=TRUE

R770D

5%

VSS_ANA_SPMU

BUCK12_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

R770E

1/20W0MF

5%

VSS_ANA_SPMU

0.47UH-20%-4A-0.027OHM

BUCK13_LX0

DIDT=TRUE
SWITCH_NODE=TRUE

R770F

1/20W

VSS_ANA_SPMU

313028

DIDT=TRUE

SWITCH_NODE=TRUE

0

21

BUCK6_FB_R

MF

0201

313028

0.47UH-20%-4A-0.027OHM

0

21

BUCK10_FB_R

MF1/20W

0201

313028

21

BUCK12_FB_R

0201

313028

L77D0

2012

0

21

BUCK13_FB_R

MF5% 0201

313028

CRITICAL

L7760

0.47UH-20%-6.9A-0.022OHM

21

PIUA25201B-SM

XW7760

SHORT-14L-0.1MM-SM

21

NO_XNET_CONNECTION=1

7828

CRITICAL

L77A0

21

2012

XW77A0

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

L77C0

0.47UH-20%-4A-0.027OHM

CRITICAL

XW77C0

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

CRITICAL

21

XW77D0

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

2012

21

PLACE_NEAR=L7750.2:5MM

PP2V5_AWAKE_NAND 7828

CRITICALCRITICAL

1

C7760

10UF

20%

6.3V

2

CER-X6S
0402

1

C7761

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1

C7766

10UF 10UF

20%

6.3V

2

CER-X6S
0402

1

C7767

20%

6.3V

2

CER-X6S
0402

1

C7768

20%

6.3V

2

CER-X6S
0402

CRITICAL CRITICAL CRITICAL

1

C7762

10UF

20%

6.3V

2

CER-X6S
0402

1

C7769

20%

6.3V

2

CER-X6S
0402

1

C7763

10UF

20%

6.3V

2

CER-X6S
0402

1

C776A

20%

6.3V

2

CER-X6S
0402

1

C7764

10UF

20%

6.3V

2

CER-X6S
0402

1

C776B

10UF10UF 10UF 10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL CRITICAL

1

C7765

10UF

20%

6.3V

2

CER-X6S
0402

1

C776E

10UF

20%

6.3V

2

CER-X6S
0402

1

C776C

10UF

20%

6.3V

2

0402

PLACE_NEAR=L7760.2:5MM

1

C776F

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C776D

10UF

20%

6.3V

2

CER-X6SCER-X6S
0402

PLACE_NEAR=L7760.2:5MM

1

C779M

12PF

5%
25V

2

NP0-C0G
0201

1

C779N

3PF

+/-0.1PF
25V

2

C0G
0201

CRITICAL CRITICAL

PP0V6_S1_VDDQL

PLACE_NEAR=L77A0.2:5MM

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C77A0

15UF

20%
2V

2

21

21

21

X6S
0402

CRITICAL CRITICAL

1

C77C0

15UF

20%
2V

2

X6S X6SX6S X6SX6S
0402

PLACE_NEAR=L77C0.2:5MM

1

C77A1

20%
2V

2

X6S
0402

CRITICAL

NOSTUFF

1

C77C1

15UF

20%
2V

2

0402

PLACE_NEAR=L77C0.2:5MM

1

C7792

12PF

5%
25V

2

NP0-C0G
0201

1

C77A2

15UF15UF

20%
2V

2

X6S
0402

CRITICAL

1

C77C2

15UF

20%
2V

2

0402

1

C7793

3PF

+/-0.1PF
25V

2

C0G
0201

1

C77A3

15UF

20%
2V

2

X6S
0402

CRITICAL

NOSTUFF

1

C77C3

15UF

20%
2V

2

1

C7723

15UF

20%
2V

2

X6S
0402

1

C7719

15UF

20%
2V

2

04020402

1

C7722

15UF

20%
2V

2

X6S
0402

CRITICAL

1

C7718

15UF

20%
2V

2

X6S X6S X6S

CRITICALCRITICALCRITICALCRITICALCRITICALCRITICAL

1

C77D6

15UF

20%
2V

2

X6S
0402

1

C77D3

15UF

20%
2V

2

X6S
0402

1

C77D4

15UF

20%

2

X6S
0402

1

C77D5

15UF

20%
2V2V

2

X6S
0402

1

C77D7

15UF

20%
2V

2

X6S
0402

1

C77D8

15UF

20%
2V

2

X6S
0402

1

C7794

12PF

5%
25V

2

NP0-C0G
0201 0201

PLACE_NEAR=L77D0.2:5MM

PLACE_NEAR=L77A0.2:5MM

1

C7790

12PF

5%
25V

2

NP0-C0G
0201

PP0V88_S1

1

C7721

15UF

20%
2V

2

CRITICAL

PP1V25_S2

1

C7791

3PF

+/-0.1PF
25V

2

C0G
0201

1

C7720

15UF

20%

CRITICAL

2V

2

040204020402

1

C7795

3PF

+/-0.1PF
25V

2

C0G

PLACE_NEAR=L77D0.2:5MM

78

78

B

78

BOM_COST_GROUP=PLATFORM POWER

SYNC_DATE=04/28/2020SYNC_MASTER=ref_pmu_sera_simetra

PAGE TITLE

PMU: SLAVE INPUT PWR & BUCKS

SIZEDRAWING NUMBER