Apple MacBook Air A1465 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK APPD

DATE

2012-02-23

J11 MLB PIB SCHEMATIC

2.6.0

D

C

B

Page Sync

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

1

Table of Contents

2

2 3 4

7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

40 41 42 43 44 45

System Block Diagram

3

Revision History

4

K78 BOM Variants

5

BOM Configuration

7

Functional Test / No Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU GROUNDS

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIe/CLK/LPC/SPI

19

PCH DMI/FDI/PM/Graphics

20

PCH PCI/USB/TP/RSVD

21

PCH GPIO/MISC/NCTF

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

USB HUB & MUX

27

Clock (CK505) and Chipset Support

28

CPU Memory S3 Support

29

DDR3 DRAM CHANNEL A (0-31)

30

DDR3 DRAM CHANNEL A (32-63)

31

DDR3 DRAM CHANNEL B (0-31)

32

DDR3 DRAM CHANNEL B (32-63)

33

FSB/DDR3/FRAMEBUF Vref Margining

34

DDR3 DRAM Channel B (32-63)

36

Thunderbolt Host (1 of 2)

37

Thunderbolt Host (2 of 2)

38

TBT Power Support

40

X21 WIRELESS CONNECTOR

45

SSD CONNECTOR

46

External A USB3 Connector

47

LIO CONNECTORS

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Voltage & Load Side Current Sensing

54

High Side Current Sensing

Contents

MASTER1

J13_MLB

K21_MLB J11_MLB_NON_POR5 (K99_MLB)6

K91_MLB

J13_MLB

K21_MLB

J11_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

J13_MLB N/A39

J30_MLB

J13_MLB

K21_MLB

J13_MLB

02/23/12

Date

MASTER

11/18/2011

11/16/2010

11/09/2011

(02/16/2010)

05/15/2010

10/13/2011

09/22/2011

12/13/2010

10/18/2011

12/13/2010

08/16/2011

12/13/2010

02/20/2012

10/06/2011

09/22/2011

02/23/2012

09/22/2011

08/12/2011

11/18/2011

08/04/2011

08/12/2011

11/18/2011

08/29/2011

11/18/2011

12/13/2010

02/22/2012

09/01/2011

11/18/2011

10/06/2011

11/18/2011

10/06/2011

N/A

07/26/2011

10/06/2011

12/13/2010

10/05/2011

09/15/2011

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Page

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

(.csa)

55

Thermal Sensors

56

Fan

57

IPD / KBD Backlight

61

SPI ROM

62

AUDI0: SPEAKER AMP

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPU VCCIO (1.05V) Power Supply

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

90

Internal DisplayPort Connector

94

Thunderbolt Connector A

97

LCD Backlight Driver

100

CPU Constraints

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

105

Thunderbolt Constraints

106

SMC Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

Contents

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

CONSTRAINTS

Sync

Date

08/30/2011

12/13/2010

10/13/2011

12/13/2010

11/11/2010

10/10/2011

09/01/2011

11/18/2011

10/07/2011

09/22/2011

12/13/2010

09/01/2011

12/13/2010

11/18/2011

12/13/2010

11/18/2011

10/13/2011

01/11/2012

D

C

B

A

Schematic / PCB #’s

PART NUMBER

051-9276 CRITICAL

820-3208 CRITICAL

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Thu Feb 23 12:05:40 2012

QTY

SIZE

A

D

DRAWING TITLE

SCHEM,MLB,J11

DESCRIPTION

1

SCHEM,MLB,J11

PCBF,MLB,J11

REFERENCE DES

SCH

PCB

CRITICAL

BOM OPTION

PRODUCT SAFETY REQUIREMENTS: PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94. PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

Apple Inc.

R

3

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

1 OF 109

SHEET

1 OF 72

1245678

8 7 6 5 4 3

12

64-bit

Misc

PG 19

SPI

PG 16

LPC

PG 16

8

7

6

5

4

3

(UP TO 10 DEVICES)

2

1

0

432 9

PG 18

1

PG 40

J2500

CPU

XDP CONN

PG 23

J5100

LPC+SPI

CONN

PG 43

USB CAMERA

U3100-U3130 U3200-U3230

MEMORY

x8

PG 29,30

U2900-U2930 U3000-U3030

MEMORY

x8

PG 27,28

U4700

USB3

Re-DRIVER

PG 40

U6100

SPI

Boot ROM

PG 50

U2660

XHCI/EHCI2

MUX

PG 24

LEFT USB EXTB

U2600

USB HUB

U4650

MOJO SMC

DEBUG MUX

PG 39

SPK

U4900

SERIAL PORT

PM_SLP S3/S4

PG 24

I2C

LID

J6950,U7000

CHARGER

PG 52,53

U5510

CPU TEMP SENSOR

U5410

TBT/MLBBOT/INLET TEMP SENSOR

VOLTAGE/CURRENT SENSOR

J5600

FAN CONN

SMB_1SMB_5

SMB_3

FAN0

ADC

SMC

PG 41

USB

J5700

PG 46,47

PG 45,46

PG 48

KBDLED

LID

SMB_2

PG 47

POWER CIRCUIT

PG 54-60

U5750

KBD DRIVER

PG 49

J5715

KBD CONN

PG 49

D

C

TRACKPAD

PG 49

U5700

USB MUX

PG 49

3 4 2 1

J4600

EXTERNAL

USB A

PG 39

U6210

SPEAKER

AMP

PG 51

J6903

RIGHT SPEAKER

CONN

PG 52

J4001

Bluetooth

(ON AP)

PG 37

B

J9000

EDP

CONN

PG 63

U3690

EEPROM

U4510

MUX

PG 38

32KHz

U2700

SYSTEM

CLOCK

25MHz

Xtal

U3600

TBT Host

PA_AUX

PA_DPSRC_1 PA_DPSRC_3

PA_LSTX/LSRX

PA_CIO1 PA_CIO0

SPI

PG 34,35 37

PG 34

J4001

X21

WIRELESS

CONN

PG 37

PCIe x4

SNK0

SNK1

PG 25

BUFFER

25MHz

SATA0

SATA

UP TO 6

LVDS OUT

RGB OUT

TMDS OUT HDMI OUT

DVI OUT

x4

DPB

x4

DPC

7 4

5 38 16

2

J4501

D

C

J9400

DISPLAY PORT

/ TBT

PG 64

SATA Conn

HDD

PG 38

U9420

AUXIO

DPMLO

MUX

PG 64

B

JTAG

J2550

PCH

XDP CONN

PG 23

RTC

PG 16

CLK

PG 16

DP OUT

PG 17

PG 16

DP0, x1

EDP

PCIE1

PCIE0

UP TO 8 LANES

PCI-E

EDP

PG 9

PCI-E

PG 9

PANTHER POINT - MPCH

SMBUS

PG 16

U1000

INTEL CPU

IVY BRIDGE 2C-35W

AXG=GT2, ULV, 1023P

FDI

PG 9 PG 9

FDI

PG 17

INTEL

U1800 1017P

PCI

PG 18

JTAG

PG 10

B

A

DUAL Channel

MEMORY

DMI

PG 17

HDA

PG 16

J4700

HDA

DDR3-1600MHZ

PG 11

GPIOs

PG 19

PWR

CTRL

PG 17

USB

PG 18

USB 3

LEFT L/O CONN

U6201

CodecAudio

PG

A

U6620

SPEAKER

AMP

PG 10

J6702

LEFT SPEAKER

CONN

PG 11

LINE IN FILTER

PG

J6700

HEADPHONE/

LINE IN JACK

HEADPHONE Filter

PG 11

PG 9

J6701

MIC

CONN

PG 11

J4720

CAMERA +ALS CONN

6 3

I2C

PG 7

LIO BOARD

J4610

USB PORT B

(LEFT PORT)

U4730

PG 6

THERMAL

SENSOR

PG 7

J4750

I2C

HALL

EFFECT

PG 7

SIZE

A

D

SYNC_MASTER=J13_MLB

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

2 OF 109

SHEET

2 OF 72

124578

8 7 6 5 4 3

12

J11 POWER SYSTEM ARCHITECTURE

D

J6900

F6901

AC

ADAPTER

DCIN(14.5V)

IN

J6950

2S3P

C

(6 TO 8.4V)

SMC

U4900

P60

(PAGE 41)

SLP_S5#(E4)

COUGAR-POINT

SLP_SUS#

(PCH)

B

A

U1800

(PAGE 16~21)

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

SLP_S4#(H4)

SLP_S3#(F4)

PM_SLP_S3_R_L

1V05_S0_LDO_EN

CPUVCCIOS0_EN

PVCCSA_EN

P1V5S0_EN

P1V8S0_EN

6A FUSE

PPVBATT_G3H_CONN

6

SMC_PM_G2_EN

PM_SLP_SUS_L

21 21

22 19

17

4

RC

DELAY

PM_SLP_S5_L

U7940

RC

DELAY

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

R7978

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

SMC_DCIN_ISENSE

SMC_RESET_L

P3V3S5_EN

PG 17

P5V_3V3_SUS_EN

P3V3S3_EN

DDRREG_EN

USB_PWR_EN

P5VS3_EN

PG 17

PG62

14-1 14-1 14-1

PPDCIN_G3H_OR_PBUS

V

1

R7020

A

CHGR_BGATE

7

11

10-1

PG61

PG62

13

PG62

15

PG62

13-2 13 14

Q5310

SMC_GFX_VSENSE

D7005

U7000

VIN

ISL6259HRTZ

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 53)

Q7055

&&

1

PPVBAT_G3H_CHGR_R

F9700

3A 32V

LCD_BKLT_EN

BKLT_PLT_RST_L

BKL_EN

PBUSVSENS_EN

T29_A_HV_EN

R6905

VOUT

Q9706

EN

Q5300

Q3880

TBTBST_EN_UVLO

ENABLE

PP5V5_CHRG_VDDP

LT3470A

U7090

(PAGE 53)

PPVBAT_G3H_CHRG_RET

R7050

SMC_BATT_ISENSE

Q5300

SMC_PBUS_VSENSE

V

R5430

A

13-1

7

VIN

LP8550

U9701

(PAGE 65)

LT3957

U3890

EN/UVLO

(PAGE 36)

6 3

PP5V5_CHAR_VDDP

1

A

PPVIN_S5_P5VP3V3

P5VS3_EN

P3V3S5_EN

PPVOUT_SW_LCDBKLT

VOUT

SMC_PBUS_VSENSE

VIN

PP15V_T29_REG

VOUT

PPVIN_G3H_P3V42G3H

F7040

PPBUS_G3H

VIN

5V

EN1

(L/H)

3.3V

EN2

(R/H)

TPS51980

U7201

(PAGE 55)

PGOOD

P5VS3_PGOOD

P3V3S5_PGOOD

VOUT1

VOUT2

R0954

PP5V_S3_REG

PP3V3_S5_REG

14-1

9

A

R6906

PP3V3_S5

P5V_3V3_SUS_EN

Q7830

P3V3S0_EN

14

Q7820

Q7810

P3V3S3_EN

Q7840

D6905

22

8

10-3

PP3V3_SUS_FET

PP3V3_S3_FET

PP5V_SUS_FET

2

15

PP5V_S0_CPUVCCIOS0.

CPUVCCIOS0_EN

21

24

CPUIMVP_VR_ON

DDRREG_EN

DDRVTT_EN

PP5V_S0_VCCSA

PVCCSA_EN

CPU_VCCSA_VID<1> CPU_VCCSA_VID<0>

14

TPS720105

U7740

14-1

10-2

R7831

A

Q7860

P5VS0_EN

(PAGE 60)

PP3V3_S0

P1V8_S0_EN

17

T29_PWR_EN

ENABLE

VCC

EN

(PAGE 59)

MAX15120

VR_ON

(PAGE 57)

S5

S3

(PAGE 56)

VCC

EN

VID1

VID0

R4599

A

1.05V

ISL95870

TPS51916

3.425V G3HOT

LT3470A

U6990

(PAGE 52)

VIN

VOUT

U7600

PGOOD

VIN

VOUT

CPU VCORE

U7400

VOUT

PGOOD

PGOODG

VIN

VLDOIN

1.5V

VOUT1

0.75V

VOUT2

U7300

PGOOD

ISL95870AH

U7100

(PAGE 54)

PGOOD

PP5V_S0_KBDLED

SMC_SYS_KBDLED

10-4

PP1V05_SUS_LDO

16

ISL8014A

EN

U7720

(PAGE 60)

TPS22924

EN

U3810

(PAGE 36)

PP3V3_S0_SSD_R

PP3V42_G3H_REG

CPUVCCIOS0_PGOOD

CPUIMVP_PGOOD

CPUIMVP_AXG_PGOOD

PPVTT_S0_DDR_LDO

16-1

DDRREG_PGOOD

PPVCCSA_S0_REG

VOUT

PVCCSA_PGOOD

PP5V_S0_FET

VIN

EN

PP5V_S0_VMON PP1V5_S3RS0_VMON

PP1V05_S0_VMON

PP1V8_S0_REG

1V05_S0_LDO_EN

PP3V3_T29_FET

R7640

A

SMC_CPU_FSB_ISENSE

R7510

SMC_CPU_ISENSE

A

R7550

SMC_GFX_ISENSE

A

P1V5CPU_EN

15

U5750

MIC2292

OUT

PAGE49

PP3V3_S0_VMON

P1V8S0_PGOOD

PPCPUVCCIO_S0_REG

22-1

PPVCORE_S0_CPU_REG

PPVCORE_S0_AXG_REG

25-1

R7350

PPDDR_S3_REG

A

23-1

KBDLED_ANPDE

6

VDD

V2MON

U7960

ISL88042IRTEZ

V3MON

V4MON

(PAGE 62)

18

TPS720105

EN

U7780

(PAGE 60)

U7770

TPS72015

(PAGE 60)

EN

PP1V5S0_EN

3

16

Q7801

PP1V5_S3RS0_FET

R7140

PP1V05_S0_LDO.

SMC POWER

SN0903048

U5010

(PAGE 42)

U3816/U3820

25

ALL_SYS_PWRGD

23

P1V8S0_PGOOD

P5VS3_PGOOD

P3V3S5_PGOOD

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

R7962

4

PP1V5_S0_REG

22

TPS22920

(PAGE 36)

EN

26

U2750

ALL_SYS_PWRGD

19

SMC_RESET_L

PP1V05_TBTCIO_FET

TBT_PWR_EN

PM_S0_PGOOD

SMC_DELAYED_PWRGD

25

S5_PWRGD

SMC_ONOFF_L

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

4

COUGAR-POINT

27

PM_PCH_PWRGD

U2760

(PAGE 16~21)

CPU

U1000

(PAGE 9~13)

SMC

PWRGD(P12)

9

RSMRST_IN(P13)

PWR_BUTTON(P90)

5

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

(PAGE 41)

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

PWRBTN#

(PCH)

SYS_RERST#

RSMRST#

U1800

DPWROK

PLTRST#

PROCPWRGD

DRAMPWROK

SM_DRAMPWROK

UNCOREPWRGOOD

RESET*

P15

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

SYSRST(PA2)

P17(BTN_OUT)

RST*

U4900

Apple Inc.

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

30

PM_DSW_PWRGD

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PM_DSW_PWRGD

29

28

10

12

26 6-1

4

SYNC_DATE=11/18/2011

Revision History

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

3 OF 109

SHEET

3 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

BOM Variants

BOM NUMBER

639-3469

639-3470

639-3473

639-3659

639-3471

639-3472

639-3775

639-3474

639-3774

639-3660

639-3776

639-3778

639-3780

639-3777

639-3779

639-3781

085-3937

607-9089

939-0479

BOM NAME

PCBA,MLB,1.5GHZ,HY 4GB,J11

PCBA,MLB,1.5GHZ,SA 4GB,J11

PCBA,MLB,1.5GHZ,HY 8GB,J11

PCBA,MLB,1.5GHZ,EL 8GB,J11

PCBA,MLB,1.7GHZ,HY 4GB,J11

PCBA,MLB,1.7GHZ,SA 4GB,J11

PCBA,MLB,1.7GHZ,EL 4GB,J11

PCBA,MLB,1.7GHZ,HY 8GB,J11

PCBA,MLB,1.7GHZ,SA 8GB,J11

PCBA,MLB,1.7GHZ,EL 8GB,J11

PCBA,MLB,2.0GHZ,HY 4GB,J11

PCBA,MLB,2.0GHZ,SA 4GB,J11

PCBA,MLB,2.0GHZ,EL 4GB,J11

PCBA,MLB,2.0GHZ,HY 8GB,J11

PCBA,MLB,2.0GHZ,SA 8GB,J11

PCBA,MLB,2.0GHZ,EL 8GB,J11

J11 MLB DEVELOPMENT BOM

CMN PTS,PCBA,MLB,J11

PCBA,MLB,1.9GHZ,HY 4GB,J11

BOM OPTIONS

J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKL,DDR3:HYNIX_4GB

J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKH,DDR3:SAMSUNG_4GB

J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKJ,DDR3:HYNIX_8GB

J11_CMNPTS,CPU:1.5GHZ,EEEE:F0V3,DDR3:ELPIDA_8GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKK,DDR3:HYNIX_4GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKF,DDR3:SAMSUNG_4GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:F27J,DDR3:ELPIDA_4GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKG,DDR3:HYNIX_8GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:F27D,DDR3:SAMSUNG_8GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:F0V4,DDR3:ELPIDA_8GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27K,DDR3:HYNIX_4GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27G,DDR3:SAMSUNG_4GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27H,DDR3:ELPIDA_4GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27C,DDR3:HYNIX_8GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27F,DDR3:SAMSUNG_8GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F279,DDR3:ELPIDA_8GB

J11_DEVEL:ENG

J11_COMMON

J11_CMNPTS,CPU:1.9GHZ,EEEE:DYKL,DDR3:HYNIX_4GB

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEEE #’s

PART NUMBER

825-7670

825-7670 CRITICAL

QTY

1

DESCRIPTION

LABEL,TEXT,MLB,K21/K78

REFERENCE DES

[EEEE_DYKL]

[EEEE_DYKH]

[EEEE_DYKK]

[EEEE_DYKF]

[EEEE_DYKJ]

[EEEE_DYKG]

[EEEE_F0V3]

[EEEE_F0V4]

[EEEE_F279]

[EEEE_F27C]

[EEEE_F27D]

[EEEE_F27F]

[EEEE_F27G]

[EEEE_F27H]

[EEEE_F27J]

[EEEE_F27K]

CRITICAL

CRITICAL825-7670

BOM OPTION

EEEE:DYKL

EEEE:DYKH

EEEE:DYKK

EEEE:DYKF

EEEE:DYKJ

EEEE:DYKG

EEEE:F0V3

EEEE:F0V4

EEEE:F279

EEEE:F27C

EEEE:F27D

EEEE:F27F

EEEE:F27G

EEEE:F27H

EEEE:F27J

EEEE:F27K

D

C

B

A

Sub-BOMs

PART NUMBER

085-3937

QTY

B

SIZE

A

D

SYNC_MASTER=K21_MLB

PAGE TITLE

K78 BOM Variants

DESCRIPTION

1

J11 MLB DEVELOPMENT BOM

CMN PTS,PCBA,MLB,J11

REFERENCE DES

DEVEL

CMNPTS

CRITICAL

CRITICAL607-9089

BOM OPTION

DEVEL_BOM

J11_CMNPTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=11/16/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

4 OF 109

SHEET

4 OF 72

124578

8 7 6 5 4 3

12

J11 BOM GROUPS

BOM GROUP

J11_PROGPARTS J11_DEVEL:ENG

J11_DEVEL:PVT

D

J11_DEBUG:ENG

J11_DEBUG:PVT

J11_DEBUG:PROD

DDR3:HYNIX_4GB

DDR3:HYNIX_8GB

DDR3:SAMSUNG_4GB

DDR3:SAMSUNG_8GB

DDR3:ELPIDA_4GB

DDR3:ELPIDA_8GB

Programmable Parts

PART NUMBER

335S0865

341S3526

338S1098

341S3434

C

335S0809

335S0803

341S3527

Alternate Parts

PART NUMBER

376S0977

371S0709

B

138S0671 138S0673

152S1085

152S1462 152S1295

138S0684 138S0660

138S0703 138S0648

152S1493

152S0586 152S1301

353S3238 353S1428

372S0186 372S0185

197S0431

376S0903 376S0796

371S0713

128S0333

128S0357 998-4435

998-4715 998-4435

998-4716

A

J11_COMMON

J11_MISC

ALTERNATE FOR PART NUMBER

376S0613376S0855

376S0859

376S0612376S0972

138S0691138S0676

371S0652

152S1307

152S1300

197S0432

376S0604376S1053

376S0613376S0855

371S0558

998-4435

QTY

1

IC,EEPROM,Cactus Ridge (V1.2) PIB, J11/J13

1

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA

1

BOM OPTION

BOM OPTIONS

ALTERNATE,COMMON,J11_MISC,J11_DEBUG:ENG,J11_PROGPARTS,USBHUB2513B,EDP:YES,PCH_C1

HUB_3NONREM,TBT,MPM5:YES,CPUMEM_SLG:NO,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTICS:NO

BOOTROM_PROG,SMC_PROG,TBTROM:PROG

ALTERNATE,BKLT:ENG,XDP_CONN,XDP_PCH,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

XDP_CONN

DEVEL_BOM,MOJO:YES,XDP,XDP_CPU:BPM,LPCPLUS

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS,VREFDQ:LDO,VREFCA:LDO,XDP_CPU:BPM,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

BKLT:PROD,MOJO:YES,XDP,LPCPLUS,VREFDQ:LDO,VREFCA:LDO,XDP_CPU:BPM,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DESCRIPTION

EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN

IC,SMC,PIB,J11

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

IC,EFI ROM,PIB,J11/J13

REF DES

COMMENTS:

Diodes alt to Toshiba

ALL

Diodes alt to Toshiba

ALL

Rohm alt to Toshiba

Murata alt to Samsung

ALL

NXP alt to NXP

ALL

Taiyo alt to Murata

ALL

Toko alt to Cyntec

ALL

Toko alt to NEC inductor

Murata alt to Taiyo Yuden

ALL

Murata alt to Taiyo Yuden

ALL

Coilcraft MA5274 alt to Murata

Dale/Vishay alt to Cyntec

ALL

Intersil alt to OPA2333

ALL

NXP alt to Diodes

200uW Epson alt to NDK

ALL

Diodes alt to Fairchild

ALL

Diodes alt to Toshiba

ALL

Fairchild alt to Siliconix

ALL

Diodes alt to ST Micro

ALL

Sanyo alt to Kemet

Sanyo High Voltage Polymer alt

ALL

Kemet Rectangular Design alt

ALL

Kemet Flute Design alt

ALL

REFERENCE DES

U3690

U4900

U6100

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL

BOM OPTION

TBTROM:BLANK

TBTROM:PROG

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_PROG

6 3

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DRAM CFG CHART

VENDOR

HYNIX

SAMSUNG

MICRON

ELPIDA

SIZE

4GB

8GB

CFG 1

0

1

0

1

CFG 2

0

1

CFG 0

Module Parts

PART NUMBER

337S4197

337S4299

337S4296

337S4198

337S4299

337S4296

337S4297

337S4165

337S4180

337S4235

337S4275

338S1108

333S0622

QTY

1

4

333S0622

333S0625

333S0623

333S0642

333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA

333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

333S0629

4

DESCRIPTION

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

IVB,QC9E,QS,L1,1.7,17W,2+2,1.05,3M,ULVBG

IVB,QC9B,QS,L1,2.0,17W,2+2,1.15,4M,ULVBG

IVB,QBTP,ES2,K0,1.5,17W,2+2,0.95,4M,ULVBGA

IVB,QC9E,QS,L1,1.7,17W,2+2,1.05,3M,ULVBG

IVB,QC9B,QS,L1,2.0,17W,2+2,1.15,4M,ULVBG

IVB,QC9C,QS,L1,1.9,17W,2+2,1.15,4M,ULVBG

IC,PCH,PPT-MB,SFF,ES1

IC,PCH,PPT-MB,SFF,ES2,B0

IC,PCH,PPT-MB,SFF,P-QS,C0

IC,PCH,PPT-MB,QS77,C1,QS

IC,TBT,CR-4C,LP,ES3,288 FCBGA,12X12MM

IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA

IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA333S0622

IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA

IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FBGA

IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FGBA

IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FBGA

IC,SDRAM,2GBIT,DDR3-1600,D35,78P FBGA

IC,SDRAM,2GBIT,DDR3-1600,D35,78P FGBA

IC,SDRAM,2GBIT,DDR3-1600,D35,78P FBGA

IC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FBGA

IC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FGBA

IC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FBGA

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

REFERENCE DES

U1000 CPU:1.5GHZ

U1000 CPU:1.7GHZ

CRITICAL

U1000

U1800

U3600

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

CRITICAL

BOM OPTION

CPU:2.0GHZU1000

CPU:1.5GHZTDP

CPU:1.7GHZTDP

CPU:2.0GHZTDP

CPU:1.9GHZ

PCH_ES1

PCH_ES2

PCH_C0

PCH_C1

PCH_C1TDP

TBT

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_8GB

DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:ELPIDA_8GB

D

C

B

607-6811

353S2929

946-3116

1

PD Module Parts

806-3706

806-3705

0

1

DIE REV

A

B

CFG 3

0

1

806-3214

806-3216

806-3083

806-3142

806-3215

1

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28

MLB,DYMAX UV EB 0.22 GRAM,K78

CAN,TOPSIDE,COVER,ALT,J11/J13

CAN,TOPSIDE,FENCE,ALT,J11/J13

CAN,TOPSIDE,J11/J13

CAN,MDP,J11/J13

SHLD,USB,MLB,J11/J13

CAN,TBT,J11/J13

CAN,COVER,TBT,J11/J13

J6955

U7000

GLUE

TBTTOPSIDE_2P_COVER

TBTTOPSIDE_2P_FENCE

TBTTOPSIDE_1P

MDPCAN

USBCAN

TBTCOVER

SYNC_MASTER=J11_MLB_NON_POR

PAGE TITLE

CRITICAL

CRITICALTBTFENCE

CRITICAL

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/09/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

5 OF 109

SHEET

5 OF 72

SIZE

A

D

124578

8 7 6 5 4 3

Misc Voltages & Control Signals

Functional Test Points

J4001: AirPort / BT Connector

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

D

C

B

A

TRUE TRUE

TRUE

TRUE TRUE

TRUE

J4501: SATA SSD Connector

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

PP3V3_WLAN_F WIFI_EVENT_L PCIE_AP_R2D_N PCIE_AP_R2D_P PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P USB_BT_CONN_P USB_BT_CONN_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_WAKE_L AP_RESET_CONN_L AP_CLKREQ_Q_L PP3V3_S3RS4_BT_F (Need to add 8 GND TPs)

PP3V3_S0_SSD_FLT SATA_SSD_D2R_P SATA_SSD_D2R_N SATA_SSD_R2D_N SATA_SSD_R2D_P SMC_OOB1_RX_L SMC_OOB1_TX_L PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1> PCIE_SSD_R2D_N<1> PCIE_SSD_R2D_P<1> PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P SSD_CLKREQ_L SSD_RESET_L SATA_PCIE_SEL SSD_P3V3S0_EN

(Need to add 6 GND TPs)

J4700: LIO Connector

=PP3V42_G3H_ONEWIRE =PP3V3_S0_AUDIO =PP3V3R1V5_S0_AUDIO SYS_ONEWIRE SMC_BC_ACOK =USB_PWR_EN =I2C_LIO_SDA =I2C_LIO_SCL =I2C_MIKEY_SCL =I2C_MIKEY_SDA AUD_IPHS_SWITCH_EN AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L AUD_GPIO_3 SPKRAMP_INR_N SPKRAMP_INR_P USB_EXTB_N USB_EXTB_P USB_CAMERA_N USB_CAMERA_P HDA_SDOUT HDA_BIT_CLK HDA_SDIN0 USB_EXTB_OC_L HDA_RST_L HDA_SYNC USB3_EXTB_RX_RC_N USB3_EXTB_RX_RC_P USB3_EXTB_TX_C_P USB3_EXTB_TX_C_N

(Need to add 5 GND TPs)

J5100: LPC+SPI Connector

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD<3..0> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO TP_SMC_TRST_L TP_SMC_MD1 SMC_TX_L LPC_CLK33M_LPCPLUS SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L LPCPLUS_GPIO

(Need to add 6 GND TPs)

(Need 6 TPs)

(Need 5 TPs)

36 41

36 40 41

36 68

16 36 68

36 67

16 36 68

17 36

36

37

37 67

37 40

37 40 41

8

37 65

8

37 65

16 37 65

16 37

25 37

37

7

39

7

39

7

39

39 40

39 40 41

38 39 61

39 43

25 39

18 39

39 50

39 50 71

24 39 67

18 39 67

16 39 68

23 39

16 39 68

39 67

7

42

7

42

16 40 42 68

42

16 40 42 68

17 40 42

40 41 42

25 42 68

40 41 42

42

40 41 42

25 42 68

19 42 49

42

16 40 42

17 25 40 42

40 41 42

40 41 42 52

41 42

40 41 42

19 42

J5600: Fan Connector

FUNC_TEST

TRUE TRUE

TRUE

J5700: IPD Flex Connector

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

J6900: DC-In Connector

FUNC_TEST

TRUE

J6903: Speaker Connector

FUNC_TEST

TRUE

J6950: Battery Connector

FUNC_TEST

TRUE TRUE

TRUE

J9000: Internal DP Connector

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

FUNC_TEST

TRUE TRUE

FUNC_TEST

TRUE

=PP5V_S0_FAN FAN_RT_TACH FAN_RT_PWM

(Need to add 1 GND TP)

SMC_PME_S4_WAKE_L

PP5V_TPAD_FILT =PP3V42_G3H_TPAD PP3V3_TPAD_CONN USB_TPAD_P USB_TPAD_N =I2C_TPAD_SDA =I2C_TPAD_SCL SMC_ONOFF_L SMC_LID SMC_TPAD_RST_L

(Need to add 5 GND TPs)

=PP18V5_DCIN_CONN =PP5V_S3_LIO_CONN

(Need to add 5 GND TPs)

SPKRAMP_ROUT_P SPKRAMP_ROUT_N

(Need to add 3 GND TPs)

PPVBAT_G3H_CONN =SMBUS_BATT_SCL =SMBUS_BATT_SDA SYS_DETECT_L

(Need to add 4 GND TPs near J6950 and 1 for shield)

PPVOUT_SW_LCDBKLT PP3V3_SW_LCD I2C_TCON_SDA_R LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1 DP_INT_HPD_CONN DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P DP_INT_ML_F_P<0> DP_INT_ML_F_N<0> I2C_TCON_SCL_R

(Need to add 5 GND TPs)

J5715: KB BKLT Connector

KBDLED_FB KBDLED_ANODE

(Need to add 2 GND TPs)

J6955: HALL EFFECT Connector

SMC_LID_R =PP3V42_G3H_HALL

7

47

40 41 48

48

7

48

48 67

43 48

40 41 48

40 41 48 51

41 48

7

51

7

51

50 51 71

51 52

43 51

51

62 64

62

62 64

62

62 65

62

48

51

7

51

(Need 4 TPs) (Need 3 TPs)

(Need 4 TPs)

(Need 2 TPs) (Need 2 TPs)

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

POWER SIGNALS

I641

I642 I643

I644

NO_TEST

TP_CRT_IG_BLUE NC_CRT_IG_BLUE

17

TP_CRT_IG_GREEN NC_CRT_IG_GREEN

17

TP_CRT_IG_RED

17

TP_CRT_IG_DDC_CLK

17

TP_CRT_IG_DDC_DATA NC_CRT_IG_DDC_DATA

17

TP_CRT_IG_HSYNC NC_CRT_IG_HSYNC

17

TP_CRT_IG_VSYNC

17

TP_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLK TP_LVDS_IG_CTRL_DATA NC_LVDS_IG_CTRL_DATA

TP_PCH_LVDS_VBG NC_PCH_LVDS_VBG

TP_HDA_SDIN1

16

TP_HDA_SDIN2

16

TP_HDA_SDIN3

16

TP_PCI_PME_L

18

TP_PCI_CLK33M_OUT3

18

TP_CLINK_CLK

16

TP_CLINK_DATA

16

TP_CLINK_RESET_L NC_CLINK_RESET_L

16

TP_PCIE_CLK100M_PEBN

16

TP_PCIE_CLK100M_PEBP

16

TP_SDVO_TVCLKINN

17

TP_SDVO_TVCLKINP

TP_SDVO_STALLN

17

TP_SDVO_STALLP

17

TP_SDVO_INTN

17

TP_SDVO_INTP

17

23

16

PPBUS_G3H PPVIN_SW_TBTBST PPBUS_S5_HS_COMPUTING_ISNS PPDCIN_G3H PP3V42_G3H PPVRTC_G3H PP5V_S5 PP5V_SUS PP3V3_S5 PP3V3_SUS PP3V3_S3 PP1V8_S0 PP3V3_S0 PP1V5_S3 PP1V5_S3RS0 PP1V5_S0 PP1V05_S0 PPVTTDDR_S3 PP0V75_S0_DDRVTT PPVCCSA_S0_CPU PP1V05_SUS PP15V_TBT PP3V3_TBTLC PP1V05_TBTLC PP1V05_S0_PCH_VCCADPLL PPVCORE_S0_CPU PPVCORE_S0_AXG PP1V5_S3_CPU_VCCDQ PP1V05_S0_CPU_VCCPQE PP1V8_S0_CPU_VCCPLL_R PP1V05_TBTCIO PPBUS_S5_HS_OTHER_ISNS PPDCIN_G3H_ISOL PP5V_S3 PP5V_S0 PP3V3_S4

NO_TEST Nets

VCCSAS0_SREF

TRUE

VCCSAS0_SET1_R

TRUE

VCCSAS0_SET0

TRUE

VCCSAS0_SET1

TRUE

TP_XDP_PCH_OBSFN_A<0..1> TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK2

TP_XDPPCH_HOOK3 TP_XDP_PCH_OBSFN_D<0..1>

TP_XDP_PCH_HOOK4

TP_XDP_PCH_HOOK5

TP_PCH_GPIO64_CLKOUTFLEX0 TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2 TP_PCH_GPIO67_CLKOUTFLEX3

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK

NC_CRT_IG_VSYNC

NC_HDA_SDIN1 NC_HDA_SDIN2

NC_HDA_SDIN3

NC_PCI_PME_L

NC_PCI_CLK33M_OUT3

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

7

51

35

7

71

7

71

7

66

7

66

7

(Need to add 27 GND TPs)

7

35

7

NC_CLINK_CLK

NC_CLINK_DATA

NC_PCIE_CLK100M_PEBN

NC_PCIE_CLK100M_PEBP

NC_SDVO_TVCLKINN

NC_SDVO_TVCLKINP

NC_SDVO_STALLN

NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

NC_TP_XDP_PCH_OBSFN_A<0..1> NC_TP_XDP_PCH_OBSFN_B<0..1>

NC_TP_XDPPCH_HOOK2

NC_TP_XDPPCH_HOOK3 NC_TP_XDP_PCH_OBSFN_D<0..1>

NC_TP_XDP_PCH_HOOK4

NC_TP_XDP_PCH_HOOK5

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3

NC_EDP_TXP<0..3>

MAKE_BASE=TRUE

NC_EDP_TXN<0..3>

MAKE_BASE=TRUE

NC_EDP_AUXP

MAKE_BASE=TRUE

NC_EDP_AUXN

MAKE_BASE=TRUE

NC_CPU_THERMDA

MAKE_BASE=TRUE

NC_CPU_THERMDC

MAKE_BASE=TRUE

NC_CPU_RSVD<30..45>

MAKE_BASE=TRUE

NC_CPU_RSVD<8..27>

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..2>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..2>

MAKE_BASE=TRUE

NC_PEG_D2RP<15..2>

MAKE_BASE=TRUE

NC_PEG_D2RN<15..2>

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N

16

TP_PCIE_CLK100M_PE4P

16

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE7P

TP_PSOC_P1_3 TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_B_R2D_CN TP_SATA_B_R2D_CP

TP_SATA_D_D2RN

16

TP_SATA_D_D2RP

16

TP_SATA_D_R2D_CN

16

TP_SATA_D_R2D_CP

16

TP_SATA_E_D2RN

16

TP_SATA_E_D2RP

16

TP_SATA_E_R2D_CN

16

TP_SATA_E_R2D_CP

16

TP_SATA_F_D2RN

16

TP_SATA_F_D2RP

16

TP_SATA_F_R2D_CN

16

TP_SATA_F_R2D_CP

16

TP_PCH_TP18

TP_PCH_TP17

TP_PCH_TP16 TP_PCH_TP15

TP_PCH_TP14

TP_PCH_TP13 TP_PCH_TP12

TP_PCH_TP10 TP_PCH_TP9

TP_PCH_TP8 TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5 TP_PCH_TP4

TP_PCH_TP3

TP_PCH_TP2 TP_PCH_TP1

TP_LVDS_IG_B_CLKN

8

TP_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKP

8

TP_LVDS_IG_BKL_PWM NC_LVDS_IG_BKL_PWM

SYNC_MASTER=(K99_MLB)

PAGE TITLE

TRUE

SMC_BS_ALRT_L

TP_EDP_TX_P<0..3>

TP_EDP_TX_N<0..3>

TP_EDP_AUX_P

TP_EDP_AUX_N

TP_CPU_THERMDA

TP_CPU_THERMDC

TP_CPU_RSVD<30..45>

TP_CPU_RSVD<8..27>

=PEG_R2D_C_P<15..2>

=PEG_R2D_C_N<15..2>

=PEG_D2R_P<15..2>

=PEG_D2R_N<15..2>

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

Functional Test / No Test

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

6 3

12

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_PE5N

NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE7P

NC_PSOC_P1_3 NC_SATA_B_D2RN

NC_SATA_B_D2RP

NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP

NC_SATA_D_D2RN

NC_SATA_D_D2RP NC_SATA_D_R2D_CN

NC_SATA_D_R2D_CP NC_SATA_E_D2RN

NC_SATA_E_D2RP

NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP

NC_SATA_F_D2RN

NC_SATA_F_D2RP NC_SATA_F_R2D_CN

NC_SATA_F_R2D_CP

NC_PCH_TP18

NC_PCH_TP17

NC_PCH_TP16 NC_PCH_TP15

NC_PCH_TP14

NC_PCH_TP13 NC_PCH_TP12

NC_PCH_TP10 NC_PCH_TP9

NC_PCH_TP8 NC_PCH_TP7

NC_PCH_TP6

NC_PCH_TP5 NC_PCH_TP4

NC_PCH_TP3

NC_PCH_TP2 NC_PCH_TP1

NC_LVDS_IG_B_CLKN

NC_SMC_BS_ALRT_L

SYNC_DATE=(02/16/2010)

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

SHEET

124578

9

2.7.0

7 OF 109

6 OF 72

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PPBUS_G3H

52

PPVIN_SW_TBTBST

6

35

VOLTAGE=12.8V

=PPVIN_S5_HS_COMPUTING_ISNS

8

D

=PPVIN_S5_HS_OTHER_ISNS

45

=PP18V5_DCIN_ISOL

51

=PP18V5_DCIN_CONN

6

51

C

"G3Hot" (Always-Present) Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE

=PPBUS_S0_LCDBKLT =PPBUS_S0_VSENSE =PPVIN_SW_TBTBST

=PPVIN_S5_HS_COMPUTING_ISNS_R =PPVIN_S5_HS_OTHER_ISNS_R

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE

=PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_VCCSAS0 =PPVIN_S0_CPUAXG

PPBUS_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE

=PPVIN_S5_P5VP3V3

PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

=PPDCIN_S5_CHGR_ISOL =PPDCIN_S5_VSENSE

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

6

52

44

6

52

6

64

44

8

45

6

56 57

55

58

53

57

6

54

51

=PP3V3_S5_REG

54

=PP3V3_S4_FET

60

=PP3V3_SUS_FET

60

=PP3V3_S4_TBTAPWR

=PP3V42_G3H_REG

51

=PPVRTC_G3_OUT

25

B

A

=PP5V_S5_LDO

54

=PP5V_SUS_FET

60

=PP5V_S3_REG

54

=PP5V_S0_FET

60

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

=PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_HALL =PP3V42_G3H_CHGR =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3H_SYSCLK =PP3V42_G3H_ONEWIRE

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE

=PPVRTC_G3_PCH

5V Rails

PP5V_S5

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S5_P1V5DDRFET =PP5V_S5_P5VSUSFET =PP5V_S5_TPAD

PP5V_SUS

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_SUS_PCH

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG

=PP5V_S3_MEMRESET

=PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN

PP5V_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSA =PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_KBDLED

6

40 41

6

52

61

43

38

6

41

25

6

16 17 20

6

60

48

6

22

6

50

55

26

60

38

6

64

56

58

6

47

6

42

53

22 25

61

48

42

51

48

39

51

=PP3V3_S3_FET

60

=PP3V3_S0_FET

60

3.3V Rails

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

=PP3V3_S3_USB_HUB

=PP3V3_S0_SSD =PP3V3_S0_HDDISNS =PP3V3_S0_VMON

PP3V3_S5

=PP3V3_S5_XDP =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET =PP3V3_S5_CPU_VCCDDR

=PP3V3_S5_LCD =PP3V3_S5_PCH =PP3V3_S5_PCHPWRGD

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S5_PCH_GPIO =PP3V3_S5_P3V3SUSFET =PP3V3_S4_P3V3S4FET =PP3V3_S4_TBTAPWRSW

PP3V3_S4

=PP3V3_S4_SMC =PP3V3_S4_TPAD

=PP3V3_S4_BT

PP3V3_SUS

=PP3V3_SUS_ROM =PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_PCH_GPIO =PP3V3_SUS_PCH =PP3V3_SUS_PWRCTL =PP3V3_SUS_P1V05SUSLDO =PP3V3_SUS_SMC =PP3V3_SUS_PCH_VCC_SPI =PP3V3_SUS_PCH_VCCSUS_USB

PP3V3_SW_TBTAPWR

VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S4_TBT

PP3V3_S3

=PP3V3_S3_BT =PP3V3_S3_MEMRESET =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_WLANISNS =PP3V3_S3_PCH_GPIO =PP3V3_S3_USBMUX =PP3V3_S3_1V5S3ISNS =PP3V3_S3_DBGLEDS

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO =PP3V3_S0_BKL_VDDIO =PP3V3_S0_HS_COMPUTING_ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_DP_DDC =PP3V3_S0_FAN =PP3V3_S0_P3V3TBTFET

=PP3V3_S0_P1V8S0 =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_SATAMUX =PP3V3_S0_PCH_VCC3_3 =PP3V3_S0_HS_OTHER_ISNS =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC

=PP3V3_S0_P1V5S0 =PP3V3_S0_TBTPWRCTL =PP3V3_S0_3V3S0ISNS =PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_BKLTISNS =PP3V3_S0_SYSCLKGEN =PP3V3_S0_SAISNS =PP3V3_S0_PCH_STRAPS

VOLTAGE=3.3V MAKE_BASE=TRUE

63

33 34 35

6

71

23

60

26 35

62

17

25

41

20 22

25

61

19

60

63

6

41

48

36

6

49

20 22

16 17 18 19

22

61

59

41

20 22

6

36

26

43

8

24

31

36

45

18 25

24

45

51

6

71

22

44

6

39

64

45

46

12

8

47

35

59

16 22

16 17 18 19 25 35

37

20 22

45

22

61

25

43

41

37

45

61

59

35

44

59

44

23

45

25

44

19

=PP1V8_S0_REG

59

2A max supply

=PPDDR_S3_REG

55

=PP1V5_S3RS0_FET

60

=PP1V5_S0_REG

59

=PPVTT_S3_DDR_BUF

31 55

=PPVTT_S0_DDR_LDO

55

=PPVCCSA_S0_REG

53

=PP1V05_SUS_LDO

59

=PPCPUVCCIO_S0_REG

58

? mA

1.8V/1.5V/1.2V/1.05V Rails

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

=PP1V8_S0_CPU_VCCPLL =PP1V8_S0_PCH_VCC_DFTERM =PP1V8_S0_P1V05S0LDO =PP1V8R1V5_S0_PCH_VCCVRM =PPVDDIO_S0_SBCLK =PP1V8_S0_P1V5S0

PP1V5_S3

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_MEMRESET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO =PPDDR_S3_MEMVREF

PP1V5_S3RS0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_CPU_VCCDDR =PP1V5_S3RS0_VMON

PP1V5_S0

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP3V3R1V5_S0_AUDIO =PP3V3R1V5_S0_PCH_VCCSUSHDA

PPVTTDDR_S3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.9V MAKE_BASE=TRUE

=PPVCCSA_S0_CPU =PPVCCSA_S0_VSENSE

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_VMON

=PPVCCIO_S0_CPUIMVP =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCC_DMI

=PPVCCIO_S0_XDP =PPVCCIO_S0_SMC =PP1V05_S0_P1V05TBTFET

6

14

19 20 22

59

20

25

59

6

66

26

27 28 32

29 30 32

60

31

6

66

10 12 15 26

61

6

39

20 22 25

6

32

26

6

12 15

44

6

23

6

9

10 12 14

16 22

20 22

17

16 22

20 22

61

56

16 20 22

20 22

23

41

35

=PP15V_TBT_REG

35

=PP3V3_TBTLC_FET

35

=PP1V05_TBTLC_FET

35 55

=PP1V05_TBTCIO_FET

=PP1V05_S0_LDO

59

=PPVCORE_S0_CPU_REG

57

=PPVCORE_S0_AXG_REG

57

=PP1V5_S3_CPU_VCCDQ

12 15

=PP1V05_S0_CPU_VCCPQE

12 14

=PP1V8_S0_CPU_VCCPLL_R

12 14

TBT Rails (off when no cable)

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE

=PPHV_SW_TBTAPWRSW

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PPVDDIO_TBT_CLK =PP3V3_TBTLC_RTR =PP3V3_TBT_PCH_GPIO

PP1V05_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_TBTLC_RTR

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_TBTCIO_RTR

1V05 S0 LDO

PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCADPLL

Chipset "VCore" Rails

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE

=PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PPVCORE_S0_CPU_VCCAXG =PPGFXVCORE_S0_VSENSE

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

SYNC_MASTER=K91_MLB

PAGE TITLE

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

12

6

63

6

25

33 34 35

19

6

34

6

34

SYNC_DATE=05/15/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

8 OF 109

SHEET

7 OF 72

124578

D

35

6

22

C

6

9

12 14

44

6

9

12 15

44

6

B

6

A

SIZE

D

8 7 6 5 4 3

CPU Heat Sink Mounting Bosses

Z0913

D

STDOFF-4.5OD1.8H-SM

Z0911

1

4x 860-1327

Fan Boss

Z0905

1

860-1327

EMI I/O Pogo Pins

DisplayPort Pogo

CRITICAL

ZS0905

POGO-2.0OD-3.6H-K86-K87

SM

1

870-1938

C

SL0901

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691 998-2691

SL0903

TH-NSP

1

B

SL-1.1X0.45-1.4x0.75

998-3975

SL0905

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691

SL0907

TH-NSP

1

SL-1.1X0.45-1.4x0.75

998-3975

SL0909

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691

A

Digital Ground

GND

VOLTAGE=0V MIN_NECK_WIDTH=0.075MM MIN_LINE_WIDTH=0.6MM

Z0910

STDOFF-4.5OD1.8H-SM

1

Z0912

STDOFF-4.5OD1.8H-SM

1

X21 Boss

Z0914

1

860-1327

Can Slots

SL-1.1X0.4-1.4x0.7

SL-1.1X0.45-1.4x0.75

SL-1.1X0.4-1.4x0.7

998-2691

SL-1.1X0.45-1.4x0.75

SL-1.1X0.4-1.4x0.7

SSD Boss

Z0915

STDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.8H-SM

1

860-1327

USB/SD Card Pogo

CRITICAL

ZS0907

POGO-2.0OD-2.95H-K86-K87

SL0902

TH-NSP

1

SL0904

TH-NSP

1

998-3975

SL0906

TH-NSP

1

SL0908

TH-NSP

1

998-3975

SL0910

TH-NSP

1

998-2691

SM

1

870-1940

2x MDP connector

2x USB connector

2x TBT pin diodes

2x TBT chip

2x CPU Vcore

DP_TBTSNK0_AUXCH_C_P

33 68

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_N

33 68

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_N

16

PCIE_CLK100M_ENET_P

16

PCIE_EXCARD_D2R_N

16

PCIE_EXCARD_D2R_P

16

PCIE_EXCARD_R2D_C_N

16

PCIE_EXCARD_R2D_C_P

16

PCIE_CLK100M_EXCARD_N

16

PCIE_CLK100M_EXCARD_P

16

PEG_CLK100M_P

16 68

PEG_CLK100M_N

16 68

TP_PCH_CLKOUT_DPN

16

TP_PCH_CLKOUT_DPP

16

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

11 66

MEM_B_CLK_P<1>

11 66

MEM_B_CLK_N<1>

11 66

USB_EXTC_P

18

USB_EXTC_N

18

USB3_EXTC_RX_P

18

USB3_EXTC_RX_N

18

USB3_EXTC_TX_P

18

USB3_EXTC_TX_N

18

USB3_EXTD_RX_P

18

USB3_EXTD_RX_N

18

USB3_EXTD_TX_P

18

USB3_EXTD_TX_N

18

USB_EXTD_EHCI_P

18

USB_EXTD_EHCI_N

18

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_N<0>

33 69

TBT_B_R2D_C_P<1>

33 69

TBT_B_R2D_C_N<1>

33 69

TBT_B_D2R_P<0>

33 69

TBT_B_D2R_N<0>

33 69

TBT_B_D2R_P<1>

33 69

TBT_B_D2R_N<1>

33 69

TBT_B_LSTX

33

DP_TBTPB_ML_C_P<1>

33 69

DP_TBTPB_ML_C_N<1>

33 69

DP_TBTPB_ML_C_P<3>

33 69

DP_TBTPB_ML_C_N<3>

33 69

PCIE_CLK100M_FW_N

16

PCIE_CLK100M_FW_P

16

=PEG_D2R_P<1..0>

9

=PEG_D2R_N<1..0>

9

=PEG_R2D_C_P<1..0>

9

=PEG_R2D_C_N<1..0>

9

PCIE_ENET_D2R_N

16

PCIE_ENET_D2R_P

16

PCIE_ENET_R2D_C_N

16

PCIE_ENET_R2D_C_P

16

PCIE_FW_D2R_N

16

PCIE_FW_D2R_P

16

PCIE_FW_R2D_C_N

16

PCIE_FW_R2D_C_P

16

CPU signals

MEMVTT_EN

26 26 55

MAKE_BASE=TRUE

DPA_IG_AUX_CH_P

DPA_IG_AUX_CH_N

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

DPLL_REF_CLK_N

DPLL_REF_CLK_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CP<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CN<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CP<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CN<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RP<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RN<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RP<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RN<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_LSTX

TRUE

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CP<1>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CN<1>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CP<3>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CN<3>

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWN

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWP

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<1..0>

MAKE_BASE=TRUE

PCIE_SSD_D2R_N<1..0>

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_N<1..0>

MAKE_BASE=TRUE

NC_PCIE_ENET_D2RN

TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_D2RN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CN

NC_PCIE_FW_R2D_CP

TP_MEM_A_CLKP<1> TP_MEM_A_CLKN<1>

TP_MEM_B_CLKP<1> TP_MEM_B_CLKN<1>

NC_USB_EXTCP NC_USB_EXTCN NC_USB3_EXTC_RXP NC_USB3_EXTC_RXN NC_USB3_EXTC_TXP NC_USB3_EXTC_TXN NC_USB3_EXTD_RXP NC_USB3_EXTD_RXN NC_USB3_EXTD_TXP NC_USB3_EXTD_TXN NC_USB_EXTD_EHCIP NC_USB_EXTD_EHCIN

=DDRVTT_EN

17

NC_PCIE_CLK100M_ENETN NC_PCIE_CLK100M_ENETP NC_PCIE_EXCARD_D2RN NC_PCIE_EXCARD_D2RP NC_PCIE_EXCARD_R2D_CN NC_PCIE_EXCARD_R2D_CP NC_PCIE_CLK100M_EXCARDN NC_PCIE_CLK100M_EXCARDP

NC_PEG_CLK100MP NC_PEG_CLK100MN

DPLL_REF_CLKN

DPLL_REF_CLKP

6

37 65

6

37 65

10 65

19 23

16 23

TP_DP_IG_D_CTRL_CLK

17

TP_DP_IG_D_CTRL_DATA

17

DP_TBTSNK0_DDC_CLK

63

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_DATA

63

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

33

MAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWR

64

MAKE_BASE=TRUE

ISNS_LCDBKLT_P

45 71

OUT

ISNS_LCDBKLT_N

45 71

OUT

=PPVIN_S5_HS_COMPUTING_ISNS

7 7

OUT

ISNS_HS_COMPUTING_N

45 71

OUT

ISNS_HS_COMPUTING_P

45 71

OUT

UNUSED SDCARD USB Aliases

=PP3V3_S3_USB_HUB

7

24

USB_SDCARD_N

24 67

OUT

USB_SDCARD_P

24 67

OUT

TBT_B_CIO_SEL

33

DP_TBTPB_HPD

33

TBT_B_CONFIG2_RC

33

TBT_B_CONFIG1_BUF

33

TBT_B_LSRX

33

1

R0916

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH XDP_DC3_PCH_GPIO19_SATARDRVR_EN

10K

5%

1/20W

MF

201

2

MLB_RAMCFG3

19

MLB_RAMCFG2

19

MLB_RAMCFG1

19

MLB_RAMCFG0

19

R0917

MAKE_BASE=TRUE

R0901

10K

1/20W

201

1

R0918

10K

5%

1/20W

MF

201 201

2

1

5%

MF

2

10K

1/20W

RAMCFG3:L

7 8

CRITICAL

R0910

0.01

0.5% 1W MF 0612-1

1 2 3 4

CRITICAL

R0954

1

R0902

10K

5% 1/20W MF 201

2

1

R0919

5% MF

2

ENET_LOW_PWR_PCH SATARDRVR_EN

R0950

10K

5%

1/20W

MF

201

=PP3V3_S0_DP_DDC

1

R0920

2.2K

1/20W

R0921

2.2K

5% MF

201

5%

1/20W

MF

201

2

DPB_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK DP_IG_D_CTRL_DATA

=PP3V3_S0_DP_DDC

1

R0924

DPA_IG_DDC_CLK

470K

1/20W

R0925

5% MF

201

2

DPA_IG_DDC_DATA

DPA_IG_HPD

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=12.6V MAKE_BASE=TRUE

=PPBUS_SW_BKL

0.002

1%

1W

MF

0612

12

=PPVIN_S5_HS_COMPUTING_ISNS_R

34

1

10K

5%

1/20W

MF

201

2

1

2

1

R0914

10K

5%

1/20W

MF

201

2

RAMCFG2:L RAMCFG1:L

1

R0951

10K

5% 1/20W MF 201

2

NOSTUFF

1

R0922

2.2K

1/20W

2

DPB_IG_DDC_DATA

1

470K

5%

1/20W

MF

201

2

6 3

NOSTUFF

1

R0923

2.2K

5%

1/20W

MF

201

17

201

2

64

1

R0952

10K

5% 1/20W 1/20W MF 201

2

12

TBT DP Ports

DPB_IG_HPD

1

5% MF

2

17

IN

17

TP_DP_IG_C_MLP<3..0>

17

TP_DP_IG_C_MLN<3..0>

17

DPB_IG_AUX_CH_P

17

DPB_IG_AUX_CH_N

17

TP_DP_IG_D_HPD

17

DP_TBTPB_AUXCH_C_P

33 69

DP_TBTPB_AUXCH_C_N

33 69

TP_DP_IG_B_MLP<3..0> TP_DP_IG_B_MLN<3..0>

17

NC_PCIE_5_R2D_CP

16

NC_PCIE_6_R2D_CP

16

NC_PCIE_7_R2D_CP

16

NC_PCIE_8_R2D_CP

16

NC_PCIE_5_R2D_CN

16

NC_PCIE_6_R2D_CN

16

NC_PCIE_7_R2D_CN

16

NC_PCIE_8_R2D_CN

16

NC_PCIE_5_D2RP

16

NC_PCIE_6_D2RP

16

NC_PCIE_7_D2RP

16

NC_PCIE_8_D2RP

16

NC_PCIE_5_D2RN

16

NC_PCIE_6_D2RN

16

NC_PCIE_7_D2RN NC_PCIE_8_D2RN

16

TP_LVDS_IG_B_CLKP

6

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

6

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

LCD_IG_PWR_EN

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

LVDS Aliases

NO_TEST=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<0..3>

LVDS_IG_B_DATA_N<0..3>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_BKL_PWM

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

DP_IG_D_HPD

NC_DP_TBTPB_AUXCH_CP NC_DP_TBTPB_AUXCH_CN

DP_TBTSNK0_ML_C_P<3..0> DP_TBTSNK0_ML_C_N<3..0>

PCIE_TBT_R2D_C_P<0> PCIE_TBT_R2D_C_P<1> PCIE_TBT_R2D_C_P<2> PCIE_TBT_R2D_C_P<3> PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_N<3>

PCIE_TBT_D2R_P<0> PCIE_TBT_D2R_P<1> PCIE_TBT_D2R_P<2> PCIE_TBT_D2R_P<3> PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_N<3>

33

33 68

1

R0909

100K

5%

1/20W

D

MF

33 68 17

201

33 68

33 68 16

33 68

2

33 68

C

17 64

17 62

17 64

SATA Aliases

16

IN

16

IN

16

OUT

16

OUT

40

IN

40

OUT

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SMC_SYS_LED

IR_RX_OUT_RC

Unused SATA ODD Signals

SMC Aliases

Unused SMC Signals

NC_SATA_ODD_R2DCP

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_SYS_LED

NO_TEST=TRUE

NC_IR_RX_OUT_RC

NO_TEST=TRUE

B

Unused PGOOD signal

19

16

RAMCFG0:L

1

R0953

10K

5% MF

201

2

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

SYNC_MASTER=K91_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

P1V5S3RS0_RAMP_DONE

DDRREG_PGOOD

Signal Aliases

Apple Inc.

R

60

IN

55

IN

SYNC_DATE=05/15/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

9 OF 109

SHEET

8 OF 72

SIZE

A

D

124578

8 7 6 5 4 3

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

12

DMI_S2N_N<0>

17 65

IN

DMI_S2N_N<1>

17 65

IN

DMI_S2N_N<2>

17 65

IN

DMI_S2N_N<3>

17 65

IN

DMI_S2N_P<0>

17 65

D

C

=PP1V05_S0_CPU_VCCIO

7 9

10 12 14

R1030

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=U1000.AF3:12.7MM

B

Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating even if internal Graphics is disabled since they are shared with other interfaces.

NOTE: The EDP_HPD processor input is a low voltage active low signal. Therefore, an inverting level shifter is required on the motherboard to convert the active high signal from Embedded DisplayPort sink device to low voltage signals for the processor

(refer to latest Processor EDS for DC specifications).

If HPD is disabled while eDP interface is still enabled, connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard. This signal can be left as no-connect if entire eDP interface is disabled.

IN

DMI_S2N_P<1>

17 65

IN

DMI_S2N_P<2>

17 65

IN

DMI_S2N_P<3>

17 65

IN

DMI_N2S_N<0>

17 65

OUT

DMI_N2S_N<1>

17 65

OUT

DMI_N2S_N<2>

17 65

OUT

DMI_N2S_N<3>

17 65

OUT

DMI_N2S_P<0>

17 65

OUT

DMI_N2S_P<1>

17 65

OUT

DMI_N2S_P<2>

17 65

OUT

DMI_N2S_P<3>

17 65

OUT

FDI_DATA_N<0>

17 65

OUT

FDI_DATA_N<1>

17 65

OUT

FDI_DATA_N<2>

17 65

OUT

FDI_DATA_N<3>

17 65

OUT

FDI_DATA_N<4>

17 65

OUT

FDI_DATA_N<5>

17 65

OUT

FDI_DATA_N<6>

17 65

OUT

FDI_DATA_N<7>

17 65

OUT

FDI_DATA_P<0>

17 65

OUT

FDI_DATA_P<1>

17 65

OUT

FDI_DATA_P<2>

17 65

OUT

FDI_DATA_P<3>

17 65

OUT

FDI_DATA_P<4>

17 65

OUT

FDI_DATA_P<5>

17 65

OUT

FDI_DATA_P<6>

17 65

OUT

FDI_DATA_P<7>

17 65

OUT

FDI_FSYNC<0>

17 65

IN

FDI_FSYNC<1>

17 65

IN

FDI_INT

17 65

IN

FDI_LSYNC<0>

17 65

IN

FDI_LSYNC<1>

17 65

IN

EDP_COMP

65

EDP_HPD_L

9

DP_INT_AUX_CH_N

62 65

DP_INT_AUX_CH_P

62 65

DP_INT_ML_N<0>

62 65

TP_EDP_TX_N<1>

6

TP_EDP_TX_N<2>

6

TP_EDP_TX_N<3>

6

DP_INT_ML_P<0>

62 65

TP_EDP_TX_P<1>

6

TP_EDP_TX_P<2>

6

TP_EDP_TX_P<3>

6

P10

P11

W11

AA6

AC9

W10

AA7

AA3 AC8

AA11 AC12

U11

AA10

AG8

AD2 AF3

AG11

AG4 AF4

AC3 AC4

AE11

AE7

AC1 AA4

AE10

AE6

M2 P6 P1

N3 P7 P3

K1 M8 N4 R2

K3 M7 P4 T3

U7

W1

W6 V4 Y2

U6

W3

W7 T4

DMI_RX_0* DMI_RX_1* DMI_RX_2* DMI_RX_3*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3*

DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3

FDI0_TX_0* FDI0_TX_1* FDI0_TX_2* FDI0_TX_3*

FDI1_TX_0* FDI1_TX_1* FDI1_TX_2* FDI1_TX_3*

FDI0_TX_0 FDI0_TX_1 FDI0_TX_2 FDI0_TX_3

FDI1_TX_0 FDI1_TX_1 FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

EDP_ICOMPO EDP_COMPIO

EDP_HPD

EDP_AUX* EDP_AUX

EDP_TX_0* EDP_TX_1* EDP_TX_2* EDP_TX_3*

EDP_TX_0 EDP_TX_1 EDP_TX_2 EDP_TX_3

OMIT_TABLE

CRITICAL

U1000

IVY-BRIDGE

2C-35W

BGA

(1 OF 9)

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8*

PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15*

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9*

PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

CPU_PEG_COMP

65

PLACE_NEAR=U1000.G3:12.7MM

=PEG_D2R_N<0> =PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3> =PEG_D2R_N<4> =PEG_D2R_N<5> =PEG_D2R_N<6> =PEG_D2R_N<7> =PEG_D2R_N<8> =PEG_D2R_N<9> =PEG_D2R_N<10> =PEG_D2R_N<11> =PEG_D2R_N<12> =PEG_D2R_N<13> =PEG_D2R_N<14> =PEG_D2R_N<15>

=PEG_D2R_P<0> =PEG_D2R_P<1> =PEG_D2R_P<2> =PEG_D2R_P<3> =PEG_D2R_P<4> =PEG_D2R_P<5> =PEG_D2R_P<6> =PEG_D2R_P<7> =PEG_D2R_P<8> =PEG_D2R_P<9> =PEG_D2R_P<10> =PEG_D2R_P<11> =PEG_D2R_P<12> =PEG_D2R_P<13> =PEG_D2R_P<14> =PEG_D2R_P<15>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7> =PEG_R2D_C_N<8> =PEG_R2D_C_N<9> =PEG_R2D_C_N<10> =PEG_R2D_C_N<11> =PEG_R2D_C_N<12> =PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1> =PEG_R2D_C_P<2> =PEG_R2D_C_P<3> =PEG_R2D_C_P<4> =PEG_R2D_C_P<5> =PEG_R2D_C_P<6> =PEG_R2D_C_P<7> =PEG_R2D_C_P<8> =PEG_R2D_C_P<9> =PEG_R2D_C_P<10> =PEG_R2D_C_P<11> =PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14> =PEG_R2D_C_P<15>

R1010

24.9

1 2

1%

1/20W

MF

201

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

=PP1V05_S0_CPU_VCCIO

8

6

PLACE_NEAR=U1000.H43:50.8MM

6

PLACE_SIDE=BOTTOM

6

8

6

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

8

6

8

6

=PPVCORE_S0_CPU

NOSTUFF

R1064

R1065

NOTE: Intel validation sense lines per

=PPVCORE_S0_CPU_VCCAXG

NOSTUFF

1

R1070

49.9

1/16W MF-LF

NOSTUFF

49.9

1/16W MF-LF

PLACE_NEAR=U1000.K43:50.8MM PLACE_SIDE=BOTTOM

49.9

1%

1/16W MF-LF 402

402

2

PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM

Note. VOLTAGE=1.25V Note. VOLTAGE=0V

Note. VOLTAGE=1.05V Note. VOLTAGE=0V

NOSTUFF

1

R1071

49.9

1%

1/16W MF-LF 402

402

2

PLACE_NEAR=U1000.K45:50.8MM PLACE_SIDE=BOTTOM

7 9

10 12 14

7

12 14

CPU_CFG<0>

9

23 65

IN

CPU_CFG<1>

9

23 65

IN

CPU_CFG<2>

9

23 65

IN

CPU_CFG<3>

9

23 65

IN

CPU_CFG<4>

9

23 65

IN

CPU_CFG<5>

9

23 65

IN

CPU_CFG<6>

9

23 65

IN

CPU_CFG<7>

9

23 65

IN

CPU_CFG<8>

23 65

IN

CPU_CFG<9>

23 65

IN

CPU_CFG<10>

23 65

IN

CPU_CFG<11>

23 65

IN

23 65

23

IN IN IN IN

9

IN IN

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>

7

12 15

CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N

TP_CPU_VCC_DIE_SENSE

CPU_THERMD_P

46 71

OUT

CPU_THERMD_N

46 71

NOTE: Intel does not recommend to use this alnalog sense due to accuracy concern.

OUT

B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53

H43 K43

H45 K45

F48

H48 K48

BA19

NC

AV19

NC

AT21

NC

BB21

NC

BB19

NC

AY21

NC

BA22

NC

AY22

NC

AU19

NC

AU21

NC

BD21

NC

BD22

NC

BD25

NC

BD26

NC

BG22

NC

BE22

NC

BG26

NC

BE26

NC

BF23

NC

BE24

NC

OMIT_TABLE

CRITICAL

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17

VCC_VAL_SENSE VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

U1000

VCC_DIE_SENSE

RSVD_6 RSVD_7

RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26 RSVD_27

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

BGA

(5 OF 9) RESERVED

2C-35W

IVY-BRIDGE

RSVD_30 RSVD_31 RSVD_32 RSVD_33

RSVD_34 RSVD_35 RSVD_36 RSVD_37 RSVD_38

RSVD_39 RSVD_40

RSVD_41 RSVD_42 RSVD_43 RSVD_44

RSVD_45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

VOLTAGE=0.75V

PPCPU_MEM_VREFDQ_A PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

NC

VOLTAGE=0.75V

NC NC NC

NC NC NC NC NC

NC NC

NC NC NC NC

NC

TP_CPU_DC_TEST_A4 CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_D1 TP_CPU_DC_TEST_A58 CPU_DC_TEST_C59_A59

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_D61 TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BE59_BE61

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BG58 TP_CPU_DC_TEST_BG4 CPU_DC_TEST_C4_BE3_BG3

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

31

OUT

31

OUT

D

C

B

CPU_CFG<16>

9

CPU_CFG<7>

9

23 65

CPU_CFG<6>

9

23 65

CPU_CFG<5>

9

23 65

CPU_CFG<4>

9

23 65

CPU_CFG<2>

9

23 65

NOSTUFF

EDP:YES

NOSTUFF

1

R1044

R1042

1K

5% 5%

1/16W

MF-LF

A

402

2

1

1K

5%

402

2

R1045

R1046

1K

5%

1/16W

MF-LF

402

2

1

R1047

1K

5%

1/16W MF-LF

402

2

FOR IVYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

23

CPU_CFG<3>

9

23 65

CPU_CFG<1>

9

23 65

CPU_CFG<0>

9

23 65

R1041

NOSTUFF

R1043

1

1K

5% 1/16W MF-LF

402

2

1

1K

5% 1/16W MF-LF

402

2

NOSTUFF

R1040

These can be Placed close to J2500 and Only for debug access

NOSTUFF

1

1K

5% 1/16W MF-LF

402

2

=PP1V05_S0_CPU_VCCIO

7 9

NOSTUFF

R1049

10 12 14

1

1K

1/16W MF-LF

402

2

DP_INT_HPD

62

PLACE_NEAR=U1000.AG11:12.7MM

1

R1031

1K

5% 1/20W MF 201

2

D

3

1 G

S

2

EDP_HPD_L

Q1031

2N7002TXG

SOT-523-3

EDP:YES

CR SFF Intel doc #460452 Rise/Fall time <6ns

9

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/13/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

10 OF 109

SHEET

9 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP1V05_S0_CPU_VCCIO

7 9

10 12 14

NOSTUFF

1

R1115

4.99K

1% 1/20W MF 201

2

NOSTUFF

1

R1102

1K

5% 1/20W MF 201201

2

C57

NC

F49

C49

A48

C45

D45

C48

B46

BE45

D44

AT30

BF44 BE43 BG43

PLACE_NEAR=U1000.B46:12.7MM

1

R1111

10K

5% 1/20W MF 201

2

PROC_DETECT*

PROC_SELECT*

CATERR*

PECI

PROCHOT*

THERMTRIP*

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET*

SM_DRAMRST*

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

NOSTUFF

1

R1100

1

R1101

62

5% 1/20W MF 201

2

R1103

56

CPU_PROCHOT_L

40 41 56 65

BI

=PP1V5_S3_CPU_VCCDDR

7

12 15 26

C

17 26 65

IN

=PP1V05_S0_CPU_VCCIO

7 9

10 12 14

23 25

IN

PLACE_NEAR=R1121.2:1MM

PM_MEM_PWRGD

CPU_RESET_L

R1120

200

1/20W

1

1%

MF

201

2

R1126

1/20W

1

75

1% MF

201

2

1 2

5%

1/20W

MF

201

PLACE_NEAR=U1000.BE45:12.7MM

R1121

130

1 2

1%

1/20W

MF

201

R1125

43.2

1 2

1%

1/20W

MF

201

CPU_PROCHOT_R_L

19

OUT

40 65

OUT

19 41 65

BI

19 41 65

OUT

17 65

IN

19 23 65

IN

26

OUT

PM_MEM_PWRGD_R

1K

5%

1/20W

MF

201

2

CPU_PROC_SEL_L

CPU_CATERR_L

CPU_PECI

PM_THRMTRIP_L

PM_SYNC CPU_PWRGD

PLT_RESET_LS1V1_L

=MEM_RESET_L

1

2

R1113

R1112

25.5

140

1%

1/20W

MF

201

2

PLACE_NEAR=U1000.BF44:12.7MM PLACE_NEAR=U1000.BE43:12.7MM PLACE_NEAR=U1000.BG43:12.7MM

NOSTUFF

1

R1104

51

5% 1/20W MF

2

CPU_SM_RCOMP<0>

65

CPU_SM_RCOMP<1>

65

CPU_SM_RCOMP<2>

65

1

R1114

200

1% 1/20W MF 201

2

Intel Doc 460452 ChiefRiver SFF DG rev1.0 section 2.7.11 recommendation R1115.

OMIT_TABLE

CRITICAL

U1000

IVY-BRIDGE

2C-35W

BGA

(2 OF 9)

THERMAL

PWR MGMT

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

CLOCKS

BCLK_ITP*

(IPU) (IPU)

(IPU) (IPU) (IPU)

(IPU)

(IPU) (IPU)

JTAG & BPM

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

BCLK

BCLK*

PRDY* PREQ*

TCK TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

J3 H2

AG3 AG1

N59 N58

N53 N55

L56 L55 J58

M60 L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

DPLL_REF_CLKP DPLL_REF_CLKN

ITPCPU_CLK100M_P ITPCPU_CLK100M_N

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

16 65

IN

16 65

IN

8

65

IN

8

65

IN

16 65

IN

16 65

IN

23 65

OUT

23 65

IN

23 65

IN

23 65

IN

23 65

IN

23 65

IN

23 65

OUT

23 25 65

OUT

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=J13_MLB

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/22/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

11 OF 109

SHEET

10 OF 72

124578

8 7 6 5 4 3

12

MEM_A_DQ<0>

27 66

BI

MEM_A_DQ<1>

27 66

BI

MEM_A_DQ<2>

27 66

BI

MEM_A_DQ<3>

27 66

BI

MEM_A_DQ<4>

27 66

D

C

B

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L

AG6 AJ6

AP11

AL6

AJ10

AJ8 AL8 AL7

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS* SA_RAS* SA_WE*

U1000

BGA

(3 OF 9)

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

MEMORY CHANNEL A

SA_CK_0

SA_CK_0*

SA_CKE_0

SA_CK_1

SA_CK_1*

SA_CKE_1

SA_CS_0* SA_CS_1*

SA_ODT_0 SA_ODT_1

SA_DQS_0* SA_DQS_1* SA_DQS_2* SA_DQS_3* SA_DQS_4* SA_DQS_5* SA_DQS_6* SA_DQS_7*

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

AU36 AV36

AY26

AT40 AU40

BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

27 28 32 66

8

66

8

66

27 28 32 66

27 66

28 66

27 66

28 66

27 28 32 66

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9

BD9 BD13 BF12

BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS* SB_RAS* SB_WE*

2C-35W

SB_CK_0

SB_CK_0*

SB_CKE_0

SB_CK_1

SB_CK_1*

U1000

BGA

(4 OF 9)

SB_CKE_1

IVY-BRIDGE

OMIT_TABLE

CRITICAL

SB_CS_0* SB_CS_1*

SB_ODT_0 SB_ODT_1

SB_DQS_0* SB_DQS_1* SB_DQS_2* SB_DQS_3* SB_DQS_4* SB_DQS_5* SB_DQS_6* SB_DQS_7*

SB_DQS_0

MEMORY CHANNEL B

SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

BA34 AY34

AR22

BA36 BB36

BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI

29 30 32 66

8

66

8

66

29 30 32 66

29 66

30 66

29 66

30 66

29 30 32 66

D

C

B

A

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

12 OF 109

SHEET

11 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

=PPVCORE_S0_CPU_VCCAXG

7 9

12 15

=PPVCORE_S0_CPU

7 9

12 14

A26

VCC_1

A29

D

C

B

A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76

OMIT_TABLE

CRITICAL

U1000

BGA

(6 OF 9)

IVY-BRIDGE

CORE SUPLLY

VCCIO_1 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7

2C-35W

VCCIO_8

VCCIO_9 VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14 VCCIO_15 VCCIO_16 VCCIO_17 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29

VCCIO_30 VCCIO_31 VCCIO_32

PEG AND DDR

VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36 VCCIO_37 VCCIO_38 VCCIO_39 VCCIO_40 VCCIO_41 VCCIO_42 VCCIO_43 VCCIO_44 VCCIO_45 VCCIO_46 VCCIO_47 VCCIO_48 VCCIO_49

VCCIO_50 VCCIO_51

VCCIO_SEL

VCCPQE_1 VCCPQE_2

RAIL

VIDALERT*

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

LINES

SENSE SVID QUIET

VCCIO_SENSE

VSS_SENSE_VCCIO

A

=PP1V05_S0_CPU_VCCIO

(NOT controlled by VCCIO_SEL)

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

Fixed at 1.05V

For Future Compatibility

CPU_VCCIO_SEL

=PP1V05_S0_CPU_VCCPQE

CPU_VIDALERT_L_R CPU_VIDSCLK_R CPU_VIDSOUT_R

CPU_VCCSENSE_P CPU_VCCSENSE_N

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

=PP3V3_S0_CPU_VCCIO_SEL

NOSTUFF

1

R1320

10K

5%

1/20W

MF

201

2

7

14

7

1

R1302

130

1%

PLACE_NEAR=U1000.C44:2.54mm 1/20W MF 201

2

PLACE_NEAR=U1000.F43:50.8mm

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACE_NEAR=U1000.G43:50.8mm

R1310

1 2

1/20W

201

PLACE_NEAR=U1000.A44:38mm

R1311

1 2

1/20W

201

0

R1312

1 2

1/20W

201

PLACE_SIDE=BOTTOM

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=U7400.17:2.54mm

1

R1300

75

1% 1/20W MF 201

5% MF

5%

MF

MF05%

100

1/16W MF-LF

100

1/16W MF-LF

2

1

R1362

100

1%

1/16W MF-LF 402

402

2

1

R1363

100

1%

1% 1/16W MF-LF

402

2

43

R1360

R1361

7 9

10 12 14

CPU_VIDALERT_L

CPU_VIDSCLK

OUT

CPU_VIDSOUT

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=BOTTOM

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

56 65

OUT

56 65

OUT

58 65

OUT

58 65

OUT

PLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=BOTTOM

AA46

VAXG_1

AB47

VAXG_2

AB50

VAXG_3

AB51

VAXG_4

AB52

VAXG_5

AB53

VAXG_6

AB55

VAXG_7

AB56

VAXG_8

AB58

VAXG_9

AB59

VAXG_10

AC61

VAXG_11

AD47

VAXG_12

AD48

VAXG_13

AD50

VAXG_14

AD51

VAXG_15

AD52

VAXG_16

AD53

VAXG_17

AD55

VAXG_18

AD56

VAXG_19

AD58

VAXG_20

AD59

VAXG_21

AE46

VAXG_22

N45

VAXG_23

P47

VAXG_24

P48

VAXG_25

P50

VAXG_26

P51

VAXG_27

P52

VAXG_28

P53

VAXG_29

P55

VAXG_30

P56

VAXG_31

P61

VAXG_32

T48

VAXG_33

T58

VAXG_34

T59

VAXG_35

T61

VAXG_36

U46

VAXG_37

V47

VAXG_38

V48

VAXG_39

V50

VAXG_40

V51

VAXG_41

V52

VAXG_42

V53

VAXG_43

V55

VAXG_44

V56

VAXG_45

V58

VAXG_46

V59

VAXG_47

W50

=PPVCORE_S0_CPU_VCCAXG

7 9

12 15

1

R1370

100

1/16W MF-LF

1

1%

402

2

1% 1/16W MF-LF 402

2

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

=PPVCCSA_S0_CPU

7

12 15

PLACE_NEAR=U1000.F45:50.8mm

56 65

IN

56 65

OUT

56 65

BI

56 65

OUT

7 9

12 14

7 9

10 12 14

PLACE_NEAR=U1000.G45:50.8mm

PLACE_SIDE=BOTTOM

CPU_AXG_SENSE_P CPU_AXG_SENSE_N

=PP1V8_S0_CPU_VCCPLL_R

7

14

R1371

PLACE_SIDE=BOTTOM

W51 W52 W53 W55 W56 W61 Y48 Y61

F45 G45

BB3 BC1 BC4

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20

VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_1 VCCSA_2 VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13 VCCSA_14 VCCSA_15 VCCSA_16

U1000

(7 OF 9)

OMIT_TABLE

CRITICAL

(IPU)

BGA

2C-35W

IVY-BRIDGE

GRPHICS

DDR3-1.5V RAILS

RAIL

QUIET

VSS_SENSE_VDDQ

LINE

SENSE

(IPU)

LINE

SENSE

1.8V

RAIL

SA RAIL

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

AY43

R1314

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

PLACE_NEAR=U1000.AY43:2.54mm

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

=PP1V5_S3_CPU_VCCDDR

7

10 12 15 26

PLACE_NEAR=U1000.U10:50.8mm

PLACE_NEAR=U1000.BC43:50.8mm

PLACE_SIDE=BOTTOM

=PP1V5_S3_CPU_VCCDQ

CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N

CPU_VCCSASENSE CPU_VCCSA_VID<0>

CPU_VCCSA_VID<1>

1

R1313

10K

5%

1/20W

5% 1/20W

MF

201

2

10 12 15 26

SYNC_MASTER=J11_MLB

PAGE TITLE

CPU_DDR_VREF

VOLTAGE=0.75V

PLACE_NEAR=U1000.BA43:50.8mm

PLACE_SIDE=BOTTOM

=PP1V5_S3_CPU_VCCDDR

7

12

R1330

1/20W

R1331

53

1K

5%

MF

201

1K

5%

1/20W

MF

201

CPU POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

=PPVCCSA_S0_CPU

7

12 15

R1380

7

Note. VOLTAGE=1.05V Note. VOLTAGE=0V

OUT

R1381

1

2

1

2

PLACE_NEAR=U1000.AY43:2.54mm

6 3

1/20W

15

1/20W

100

201

53

100

201

1% MF

1

2

12

R1382

100

1%

1/20W

MF

1

201

2

1

2

CPU_DDR_VREF

C1330

0.1UF

10% 16V X5R-CERM 0201

SYNC_DATE=10/18/2011

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

13 OF 109

SHEET

12 OF 72

124578

1

2

OUT

2.7.0

D

C

53

B

12

A

SIZE

D

8 7 6 5 4 3

12

A9

VSS

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 AA1

AA8 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AB16 AB18 AB21 AB48 AB61

AC6 AC10 AC14 AC46

AD4 AD17 AD20 AD61

AE8 AE13

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG7 AG10 AG14 AG18 AG47 AG52 AG61

AH4 AH58

AJ7 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM4 AM13 AM20 AM22 AM26 AM30

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M11 M15 M58 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P9 P14 P16 P18 P21 P58 P59 R4 R17 R20 R46 T1 T47 T50 T51 T52 T53 T55 T56 U8 U13 V20 V61 W8 W13 W15 W18 W21 W46 Y4 Y47 Y58 Y59

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

BG13

VSS

BG17

VSS

BG21

VSS

BG24

VSS

BG28

VSS

D

C

B

BG37 BG41 BG45 BG49 BG53

C29 C35 C40

D10 D14 D18 D22 D26 D29 D35 D40 D43 D46 D50 D54 D58

E25 E29 E35 E40 F13 F15 F19 F29 F35 F40 F55

G48 G51 G61

H10 H14 H17 H21 H53 H58

J49 J55

K11 K21 K51 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

VSS VSS VSS VSS VSS VSS VSS VSS

D4

VSS

D6

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G6

VSS VSS VSS VSS

H4

VSS VSS VSS VSS VSS VSS VSS

J1

VSS VSS VSS

K8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M4

VSS

M6

VSS

U1000

BGA

(9 OF 9)

VSS

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

A

U1000

BGA

(8 OF 9)

VSS

IVY-BRIDGE

OMIT_TABLE

CRITICAL

2C-35W

6 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AM34 AM38 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP7 AP10 AP51 AP55 AR7 AR13 AR17 AR21 AR41 AR48 AR61 AT4 AT14 AT19 AT36 AT45 AT52 AT58 AU1 AU7 AU11 AU28 AU32 AU51 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW7 AW13 AW43 AW61 AY4 AY9 AY14 AY19 AY30 AY36 AY41 AY45 AY49 AY55 AY58 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC5 BC13 BC57 BD8 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BE5 BG9

PAGE TITLE

CPU GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

14 OF 109

SHEET

13 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

12

CPU VCORE DECOUPLING

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

=PPVCORE_S0_CPU

7 9

12

D

C

CRITICAL

1

C1600

1UF

20%

6.3V

2

X5R 0201 0201

CRITICAL

1

C1616

1UF

20%

6.3V

2

X5R

0201

PLACEMENT_NOTE (C1655-C1666): Place close to U1000 on top side.

CRITICAL

1

C1655

10UF

20%

6.3V

2

CERM-X5R CERM-X5R 0402-1

PLACEMENT_NOTE (C1667-C1679):

CRITICAL

1

C1601

1UF

20%

6.3V

2

X5R

CRITICAL

1

C1617

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1656

10UF

20%

6.3V

2

0402-1

CRITICAL

1

C1602

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1618

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1657

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1603

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1619

1UF

20%

6.3V

2

X5R 0201

1

2

CRITICAL

1

C1604

2

CRITICAL

1

2

CRITICAL

C1658

10UF

20%

6.3V CERM-X5R 0402-1

1UF

20%

6.3V X5R 0201

C1620

1UF

20%

6.3V X5R 0201

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

C1659

10UF

20%

6.3V

2

CERM-X5R 0402-1

C1605

1UF

20%

6.3V X5R 0201

C1621

1UF

20%

6.3V X5R 0201

CRITICAL

1

C1606

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1622

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1660

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1607

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1623

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1661

10UF

20%

6.3V

2

CERM-X5R 0402-1

Processor Load Line : -2.9 mOhms

CRITICAL

1

C1608

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

2

C1624

1UF

20%

6.3V X5R 0201

CRITICAL

1

C1662

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1609

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1625

1UF

20%

6.3V

2

X5R 0201

1

2

CRITICAL

1

C1610

1UF

20%

6.3V

2

X5R 0201

CRITICAL CRITICAL

1

C1626

1UF

20%

6.3V

2

X5R 0201

CRITICAL

C1663

10UF

20%

6.3V CERM-X5R 0402-1

1

C1664

2

10UF

20%

6.3V CERM-X5R 0402-1

CRITICAL

1

C1611

1UF

20%

6.3V

2

X5R 0201

1

C1627

2

CRITICAL

1UF

20%

6.3V X5R 0201

CRITICAL CRITICAL

1

C1665

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1612

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1628

1UF

20%

6.3V

2

X5R 0201

1

C1666

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1613

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1629

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1614

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

2

CRITICAL

1

C1630

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1667

10UF 10UF

20%

6.3V

2

CERM-X5R 0402-1

1

2

C1615

1UF

20%

6.3V X5R 0201

CRITICAL

1

C1631

1UF

20%

6.3V

2

X5R 0201

CRITICAL

C1668

20%

6.3V CERM-X5R 0402-1

CRITICAL

1

C1640

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1632

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1669

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1641

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1633

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1670

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1642

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1634

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1635

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1636

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1637

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1638

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1639

1UF

20%

6.3V

2

X5R 0201

D

C

PLACEMENT_NOTE (C1640-C1645):

1

C1680

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1681

270UF

20% 2V

2

TANT CASE-B2-SM CASE-B2-SM

1

C1682

270UF

20% 2V

2

TANT

1

C1683

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1679

270UF

20% 2V

2

TANT CASE-B2-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

PLACEMENT_NOTE (C1684-C167F):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

=PP1V05_S0_CPU_VCCIO

7 9

10 12

B

A

Place on bottom side of U1000

1

C1684

1UF

10% 10V

2

X5R 402

1

C1697

1UF

10% 10V

2

X5R 402

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom sidePlace near U1000 on bottom side

Place near U1000 on bottom side

1

C161E

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167D

270UF

20% 2V

2

TANT CASE-B2-SM

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

1 2

1%

1/4W

MF

0603

1

C1685

1UF

10% 10V

2

X5R 402

1

C1698

1UF 1UF

10% 10V

2

X5R 402

1

C161F

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167E

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1686

1UF

10% 10V

2

X5R 402

1

C1699

10% 10V

2

X5R 402

1

C162A

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167G

270UF

20% 2V 2V

2

TANT CASE-B2-SM

=PP1V05_S0_CPU_VCCPQE

1

C167F

1UF

10%

Note:The smallest 10mOhm available in the library are 0805s

10V

2

X5R 402

1

C1687

2

1

C169A

1UF

10% 10V

2

X5R 402

1

C162B

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167H

270UF

20%

2

TANT CASE-B2-SM

7

12

1UF

10% 10V X5R 402

1

C1688

1UF

10% 10V

2

X5R 402

1

C169B

1UF

10% 10V

2

X5R 402

1

C162C

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1689

1UF

10% 10V

2

X5R 402

1

C169C

1UF

10% 10V

2

X5R 402

1

C162D

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1690

2

1

C169D

1UF

10% 10V

2

X5R 402

1

C162E

10UF

20%

6.3V

2

CERM-X5R 0402-1

1UF

10% 10V X5R 402

1

C1691

2

1

C169E

1UF

10% 10V

2

X5R 402

1

C167A

10UF

20%

6.3V

2

CERM-X5R 0402-1

1UF

10% 10V X5R 402

1

2

1

2

1

C167B

10UF

20%

6.3V

2

CERM-X5R 0402-1

C1692

1UF

10% 10V X5R 402

C169F

1UF

10% 10V X5R 402

1

2

1

2

1

C167C

10UF

20%

6.3V

2

CERM-X5R 0402-1

C1693

1UF

10% 10V X5R 402

C161A

1UF

10% 10V X5R 402

1

C1694

1UF

10% 10V

2

X5R 402

1

C161B

1UF

10% 10V

2

X5R 402

1

C1695

1UF

10% 10V

2

X5R 402

1

C161C

1UF

10% 10V

2

X5R 402

1

C1696

1UF

10% 10V

2

X5R 402

1

C161D

1UF

10% 10V

2

X5R 402

=PP1V8_S0_CPU_VCCPLL

7

6 3

CPU VCCPLL DECOUPLING

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

PLACEMENT_NOTE (C1646-C1671):

Place near U1000 on top side

R1600

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

CPU VCCPLL Low pass filter

=PP1V8_S0_CPU_VCCPLL_R

1

C160X

1UF

10% 10V

2

X5R 402

SYNC_MASTER=J13_MLB

PAGE TITLE

1

C160Y

1UF

10% 10V

2

X5R 402

PLACE_NEAR=U1000.BC2:5mm

1

C160Z

270UF

20% 2V

2

TANT CASE-B2-SM

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=08/16/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

16 OF 109

SHEET

14 OF 72

124578

7

12

B

A

SIZE

D

8 7 6 5 4 3

12

VAXG DECOUPLING

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

=PPVCORE_S0_CPU_VCCAXG

7 9

12

D

C

PLACEMENT_NOTE (C1700-C1710):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

CRITICAL

1

C1700

1UF

10% 10V

2

X5R 402

PLACEMENT_NOTE (C1711-C1716):

1

2

CRITICAL CRITICAL

1

C1711

10UF

20%

6.3V

2

CERM-X5R 0402-1

PLACEMENT_NOTE (C1717-C1722):

CRITICAL

AXG_ACOUSTICS:NO

1

C1717

22UF 22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

AXG_ACOUSTICS:YES

1

C1727

22UF

20% 4V

2

X5R 402

PLACEMENT_NOTE (C1723-C1724):

1

2

1

2

AXG_ACOUSTICS:YES

1

2

CRITICAL

C1701

1UF

10% 10V X5R 402

C1712

10UF

20%

6.3V CERM-X5R 0402-1

CRITICAL

AXG_ACOUSTICS:NO

C1718

20%

6.3V X5R-CERM1 0603

CRITICAL

C1728

22UF

20% 4V X5R 402

CRITICAL

1

C1702

1UF

10% 10V

2

X5R 402

CRITICAL

1

C1713

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

AXG_ACOUSTICS:NO

1

C1719

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

AXG_ACOUSTICS:YES AXG_ACOUSTICS:YES

1

C1729

22UF

20% 4V

2

X5R 402

1

C1703

1UF

10% 10V

2

X5R 402

CRITICAL

1

C1714

10UF

20%

6.3V

2

CERM-X5R 0402-1

AXG_ACOUSTICS:NO

1

C1720

22UF

20%

6.3V

2

X5R-CERM1 0603

1

C1730

22UF

20% 4V

2

X5R 402

CRITICAL

1

C1704

1UF

10% 10V

2

X5R 402

CRITICAL

1

C1715

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

AXG_ACOUSTICS:NO

1

C1721

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

AXG_ACOUSTICS:YES AXG_ACOUSTICS:YES

1

C1731

22UF

20% 4V

2

X5R 402

Graphics Load Line : -3.9 mOhms

1

2

1

C1705

1UF

10% 10V

2

X5R 402

CRITICAL

C1716

10UF

20%

6.3V CERM-X5R 0402-1

AXG_ACOUSTICS:NO

1

C1722

2

1

C1732

2

CRITICAL

22UF

20%

6.3V X5R-CERM1 0603

CRITICAL

22UF

20% 4V X5R 402

1

2

CRITICAL

C1706

1UF

10% 10V X5R 402

1

2

CRITICAL

C1707

1UF

10% 10V X5R 402

1

2

CRITICAL

C1708

1UF

10% 10V X5R 402

1

2

CRITICAL

C1709

1UF

10% 10V X5R 402

1

2

CRITICAL

C1710

1UF

10% 10V X5R 402

D

C

1

C1723

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1724

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1725

270UF

20% 2V

2

TANT CASE-B2-SM

CPU VCCSA DECOUPLING

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

PLACEMENT_NOTE (C1758-C1762):

=PPVCCSA_S0_CPU

7

12

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

B

=PP1V5_S3_CPU_VCCDDR

7

10 12 26

A

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U100.

1

C1738

1UF

10% 10V

2

X5R 402

Place close to U1000 on bottom side

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

Place close to U1000 on bottom side

1

C1748

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1756

270UF

20% 2V

2

TANT

CASE-B2-SM

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1702

1 2

0.010

1

C1739

1UF

10% 10V

2

X5R 402

1

C1749

10UF

20%

6.3V

2

CERM-X5R 0402-1 0402-1

=PP1V5_S3_CPU_VCCDQ

1%

1/4W

MF

0603

1

C1757

1UF

10% 10V

2

X5R 402

1

2

1

2

C1750

10UF

20%

6.3V CERM-X5R 0402-1

C1740

1UF

10% 10V X5R 402

1

C1741

1UF

10% 10V

2

X5R 402

1

C1751

10UF

20%

6.3V

2

CERM-X5R

7

12

1

C1742

1UF

10% 10V 10V

2

X5R 402

1

C1752

10UF

20%

6.3V

2

CERM-X5R 0402-1 0402-1

1

C1743

1UF

10%

2

X5R X5R 402

1

C1753

10UF

20%

6.3V

2

CERM-X5R

1

2

1

2

C1754

10UF

20%

6.3V CERM-X5R 0402-1

C1744

1UF

10% 10V

402

1

C1745

1UF

10% 10% 10V

2

X5R 402

1

C1755

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

2

C1746

1UF

10V X5R 402

1

2

C1747

1UF

10% 10V X5R 402

6 3

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1758

1UF

10% 10V

2

X5R 402

1

C1763

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1768

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1759

1UF

10% 10V

2

X5R 402

1

C1764

10UF

20%

6.3V

2

CERM-X5R 0402-1 0402-1

1

2

1

2

C1765

10UF

C1760

20%

6.3V CERM-X5R

1UF

10% 10V X5R 402

1

C1761

1UF

10% 10V

2

X5R 402

1

C1766

10UF 10UF

20%

6.3V

2

CERM-X5R 0402-1

SYNC_MASTER=K21_MLB

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

1

C1762

1UF

10% 10V

2

X5R 402

1

C1767

20%

6.3V

2

CERM-X5R 0402-1

CPU DECOUPLING-II

Apple Inc.

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

17 OF 109

SHEET

15 OF 72

124578

SIZE

B

A

D

8 7 6 5 4 3

SYSCLK_CLK32K_RTC

25 68

IN

RTC_RESET_L

16

PCH_SRTCRST_L

16

PCH_INTRUDER_L

D

VSel strap not functional (VCCVRM = 1.8V)

C

16

16 68

16

16 68

6

39 68

IN

6

16 25 68

19

OUT

16

IN

23 68

IN

23 68

IN

23 68

IN

23 68

OUT

42 68

OUT

42 68

OUT

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_SYNC_R

PCH_SPKR

HDA_RST_R_L

HDA_SDIN0 TP_HDA_SDIN1 TP_HDA_SDIN2 TP_HDA_SDIN3

HDA_SDOUT_R

JTAG_ISP_TMS ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

XDP_PCH_TMS

XDP_PCH_TDI

XDP_PCH_TDO

SPI_CLK_R

SPI_CS0_R_L

TP_SPI_CS1_L

SPI_MOSI_R

42 68

OUT

SPI_MISO

42 68

IN

=PPVRTC_G3_PCH

7

17 20

R1800

B

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

R1877 R1878

R1834 R1833

R1842 R1869 R1844 R1845 R1847

A

R1814 R1815 R1843

R1846 R1848 R1853 R1854 R1855

R1879

OMIT_TABLE

QP8D-MM915462

(IPD) (IPD) (IPD) (IPD)

(IPD-BOOT)

(IPD)

(IPU)

(IPD-BOOT)

(IPU)

U1800

BGA

(1 OF 10)

RTCSPI

IHDA

JTAG

(IPU)

16

FWH4/LFRAME*

LPC

LDRQ1*/GPIO23

(IPU)

SATA

SATA0GP/GPIO21 SATA1GP/GPIO19

16

16 16

16

16 68

16 25 68

(IPU)

SATAICOMPO SATAICOMPI

SATA3RCOMPO

SATA3COMPI SATA3RBIAS

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>RTC_RESET_L LPC_FRAME_R_L

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_RST_R_L

HDA_SDOUT_R

16

23 25

8

16

16 36

16

16 35

6

16

16 24

16

A19 C19

NC

F19

A23

K22

C21

H35

H37

F35

D36 B36 C35 A35

K37

K35 M35

M17

M15

U12

M12

AD12

AB8

AB6

1

20K

20%

X5R

1

R1803

20K

5%

5% 1/20W

MF

2

1

2

MF 201

2

PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L

1

C1803

2

201

MF5% MF

201

MF5%

201

MF

201

MF

201 201

MF

201

MF

201

MF

201

MF5%

201

MF

201

MF

201

MF

201

MF

201

R1802

R1801

1M

5% 1/20W MF 201

1/20W

C1802

1.0UF

6.3V

0201-MUR

7

17 18 19

7

17 18 19 25 35

5% MF

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W 1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

1

330K

5%

1/20W

MF

201

2

4.7K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

2 1

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V. If HDA = S0, must also ensure that signal cannot be high in S3.

PCH-PPT-MB-SFF-ES1

RTCX1 RTCX2

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

(IPD-BOOT)

N1

SPKR

(IPD-PLTRST#)

HDA_RST*

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0*

SPI_CS1*

W8

SPI_MOSI

Y2

SPI_MISO

1.0UF

20%

6.3V

X5R 0201-MUR

PCH_SPKR PCH_SATALED_L

DP_AUXCH_ISOL SATARDRVR_EN

FW_CLKREQ_L AP_CLKREQ_L EXCARD_CLKREQ_L JTAG_DPMUXUC_TRST_L ENET_CLKREQ_L PEG_CLKREQ_L TBT_CLKREQ_L SSD_CLKREQ_L

PEGCLKRQA_L_GPIO47 PEGCLKRQB_L_GPIO56 SMBUS_PCH_ALERT_L USB_EXTB_SEL_XHCI USB_EXTD_SEL_XHCI

ENET_MEDIA_SENSE_RDIV

LDRQ0*

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED*

A37 A39 C39 C37 K40

H40 F37

Y4

AN3 AN1 AU3 AU1

AN6 AN8 AR3 AR1

AD4 AD2 AL3 AL1

AD8 AD6 AG3 AG1

AE3 AE1 AH8 AH6

AC3 AC1 AJ3 AJ1

AB10 AB12

AF10 AF12 AH4

W10

M2 R1

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

(IPU)

PLACE_NEAR=U1800.H35:1.27mm

PLACE_NEAR=U1800.H37:1.27mm

PLACE_NEAR=U1800.F35:1.27mm

PLACE_NEAR=U1800.K37:1.27mm

16 37

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> LPC_FRAME_R_L

TP_LPC_DREQ0_L TBT_PWR_EN_PCH

LPC_SERIRQ

SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P

SATA_ODD_D2R_N SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_C_D2RN TP_SATA_C_D2RP TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP

TP_SATA_D_D2RN TP_SATA_D_D2RP TP_SATA_D_R2D_CN TP_SATA_D_R2D_CP

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP

TP_SATA_F_D2RN TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

PCH_SATAICOMP

67

PCH_SATA3COMP PCH_SATA3RBIAS

PCH_SATALED_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

33

R1860 R1861 R1862 R1863 R1864

R1810 R1811 R1812 R1813

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

16

OUT

IN

IN OUT OUT

IN

IN OUT OUT

6

16

5%

25

37 67

8

MF5%

1/20W

MF

1/20W

MF5%

1/20W

MF

1/20W

MF

1/20W

MF5%

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

ITPCPU_CLK100M_N

10 65

ITPCPU_CLK100M_P

10 65

=PP3V3_S0_PCH

1

R1820

10K

5% 1/20W MF 201

2

6

40 42

BI

=PP1V05_S0_PCH_VCCIO_SATA

PLACE_NEAR=U1800.AB10:2.54mm

1

R1830

37.4

1% 1/20W MF 201

2

=PP1V05_S0_PCH

1

R1831

49.9

1% 1/20W MF 201

2

PLACE_NEAR=U1800.AF12:2.54mm

23

OUT

8

23

OUT

LPC_AD<0>

201

LPC_AD<1>

201

LPC_AD<2>

201

LPC_AD<3>

201

LPC_FRAME_L

201

HDA_BIT_CLK

201

HDA_SYNC

201

HDA_RST_L

201

HDA_SDOUT

201

7

22

PLACE_NEAR=U1800.AH4:2.54mm

1

R1832

750

1% 1/20W MF 201

2

NO STUFF

R1841

0

1 2

5%

1/20W

MF

201

7

22

7

22

6

40 42 68

BI

6

40 42 68

BI

6

40 42 68

BI

6

40 42 68

BI

6

40 42 68

OUT

6

39 68

OUT

6

39 68

OUT

6

39 68

OUT

6

39 68

OUT

NO STUFF

R1840

0

1 2

5%

1/20W

MF

201

8

IN

8

IN

8

OUT

8

OUT

6

36 68

IN

6

36 68

IN

36 68

OUT

36 68

OUT

8

IN

8

IN

8

OUT

8

OUT

8

IN

8

IN

8

OUT

8

OUT

8

OUT

8

OUT

6

16 37

IN

8

16

6

36 68

OUT

6

36 68

OUT

16 36

IN

8

OUT

8

OUT

16

IN

16

OUT

37 65

6

OUT

6

37 65

OUT

16

IN

68

8

OUT

8

68

OUT

16

IN

33 68

OUT

33 68

OUT

16 35

IN

23 65

PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RN

8

NC_PCIE_5_D2RP

8

NC_PCIE_5_R2D_CN

8

NC_PCIE_5_R2D_CP

8

NC_PCIE_6_D2RN

8

NC_PCIE_6_D2RP

8

NC_PCIE_6_R2D_CN

8

NC_PCIE_6_R2D_CP

8

NC_PCIE_7_D2RN

8

NC_PCIE_7_D2RP

8

NC_PCIE_7_R2D_CN

8

NC_PCIE_7_R2D_CP

8

NC_PCIE_8_D2RN

8

NC_PCIE_8_D2RP

8

NC_PCIE_8_R2D_CN

8

NC_PCIE_8_R2D_CP

8

PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P SSD_CLKREQ_L

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P FW_CLKREQ_L

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P AP_CLKREQ_L

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4N

6

TP_PCIE_CLK100M_PE4P

6

JTAG_DPMUXUC_TRST_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN

6

TP_PCIE_CLK100M_PEBP

6

PEGCLKRQB_L_GPIO56

16

PEG_CLK100M_N PEG_CLK100M_P PEG_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P TBT_CLKREQ_L

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

25 68

IN

Unused clock terminations for FCIM Mode

10K

PCH_CLK96M_DOT_P

16 67

PCH_CLK96M_DOT_N

16 67

PCH_CLK100M_SATA_P

16 67

PCH_CLK100M_SATA_N

16 67

PCIE_CLK100M_PCH_P

16 67

PCIE_CLK100M_PCH_N

16 67

PCH_CLK14P3M_REFCLK

16 67

PCH_CLKIN_GNDP1

16

PCH_CLKIN_GNDN1

16

R1891 R1892

R1893 R1894

R1895 R1896

R1897

R1870 R1871

10K

10K 10K

10K

10K 10K

1 2 1 2

1 2

1 2 1 2

6 3

BJ33

PERN1

BL33

PERP1

BB30

PETN1

AY30

PETP1

BJ35

PERN2

BL35

PERP2

BB33

PETN2

AY33

PETP2

BH36

PERN3

BK36

PERP3

BF33

PETN3

BD33

PETP3

BJ37

PERN4

BL37

PERP4

BD35

PETN4

BF35

PETP4

BJ39

PERN5

BL39

PERP5

AY35

PETN5

BB35

PETP5

BH40

PERN6

BK40

PERP6

BD37

PETN6

BF37

PETP6

BJ41

PERN7

BL41

PERP7

AY37

PETN7

BB37

PETP7

BJ43

PERN8

BL43

PERP8

AY40

PETN8

BB40

PETP8

AD48

CLKOUT_PCIE0N

AD50

CLKOUT_PCIE0P

M4

PCIECLKRQ0*/GPIO73

AE49

CLKOUT_PCIE1N

AE51

CLKOUT_PCIE1P

U8

PCIECLKRQ1*/GPIO18

AD40

CLKOUT_PCIE2N

AD42

CLKOUT_PCIE2P

T4

PCIECLKRQ2*/GPIO20

AA49

CLKOUT_PCIE3N

AA51

CLKOUT_PCIE3P

B8

PCIECLKRQ3*/GPIO25

Y48

CLKOUT_PCIE4N

Y50

CLKOUT_PCIE4P

M19

PCIECLKRQ4*/GPIO26

AB40

CLKOUT_PCIE5N

AB42

CLKOUT_PCIE5P

K8

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

PEG_B_CLKRQ*/GPIO56

AB44

CLKOUT_PCIE6N

AB46

CLKOUT_PCIE6P

J3

PCIECLKRQ6*/GPIO45

W44

CLKOUT_PCIE7N

W46

CLKOUT_PCIE7P

H4

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

AR12

CLKOUT_ITPXDP_N

AR10

CLKOUT_ITPXDP_P

SYSCLK_CLK25M_SB

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

OMIT_TABLE

U1800

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

(2 OF 10)

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

C-LINK

PCI-E*

Controlled by PCIECLKRQ5#

CLOCKS

FLEX

CLOCKS

R1885

1 2

201

PLACE_NEAR=U1800.W49:5.1mm

1%

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

604

MF

1/20W

SMBALERT*/GPIO11

SML0ALERT*/GPIO60

(IPU/IPD) (IPU/IPD)

PEG_A_CLKRQ*/GPIO47

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1 CL_DATA1 CL_RST1*

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

(IPD-PWROK)

CLKOUTFLEX1/GPIO65

(IPD-PWROK)

CLKOUTFLEX2/GPIO66

(IPD-PWROK)

CLKOUTFLEX3/GPIO67

(IPD-PWROK)

SYSCLK_CLK25M_SB_R

1.8V -> 1.1V

1

R1886

1K

1% 1/20W MF 201

2

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

12

H12 F17 F10

H22 K12 A9

C9 D12 C11

L3 J1 M8

R8 AF44 AF46

BB24 AY24

AN10 AN12

BD17 BF17

BB26 AY26

M24 K24

AK8 AK6

J49

E51

W49 W51

AC49

H50

D48

G49

J51

PCH SATA/PCIe/CLK/LPC/SPI

SMBUS_PCH_ALERT_L SMBUS_PCH_CLK SMBUS_PCH_DATA

USB_EXTB_SEL_XHCI SML_PCH_0_CLK SML_PCH_0_DATA

USB_EXTD_SEL_XHCI SML_PCH_1_CLK SML_PCH_1_DATA

TP_CLINK_CLK TP_CLINK_DATA TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47 TP_PCIE_CLK100M_PEGAN TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

DOES THIS NEED LENGTH MATCH???

SYSCLK_CLK25M_SB_R

NC

=PP1V05_S0_PCH_VCCDIFFCLK

7

20 22

PLACE_NEAR=U1800.AC49:2.54mm

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

16 68

Apple Inc.

R

16

6

16

OUT OUT

16

16 68

SYNC_DATE=02/20/2012

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

18 OF 109

SHEET

124578

43 68

OUT

43 68

BI

16 24

OUT

43 68

OUT

43 68

BI

16

OUT

43 68

OUT

43 68

BI

10 65

8

OUT

8

OUT

16 67

IN

16 67

IN

16 67

IN

16 67

IN

16 67

IN

16 67

IN

16 67

IN

25 68

IN

1

R1890

90.9

1%

1/20W

MF

201

2

6

2.7.0

16 OF 72

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

=PP3V3_SUS_PCH_GPIO =PP1V05_S0_PCH_VCCIO_PCIE

PLACE_NEAR=U1800.BF19:12.7mm

1

10K

R1900

49.9

1%

5%

1/20W MF

MF

201

2

DMI_N2S_N<0>

9

65

IN

DMI_N2S_N<1>

9

65

IN

DMI_N2S_N<2>

9

65

IN

DMI_N2S_N<3>

9

65

IN

DMI_N2S_P<0>

9

65

IN

DMI_N2S_P<1>

9

65

IN

DMI_N2S_P<2>

9

65

IN

DMI_N2S_P<3>

9

65

IN

DMI_S2N_N<0>

9

65

OUT

DMI_S2N_N<1>

9

65

OUT

DMI_S2N_N<2>

9

65

OUT

DMI_S2N_N<3>

9

65

OUT

DMI_S2N_P<0>

9

65

OUT

DMI_S2N_P<1>

9

65

OUT

DMI_S2N_P<2>

9

65

OUT

DMI_S2N_P<3>

9

65

OUT

R1905

1/20W

D

PCH_DMI_COMP

25 40

IN

23 25 40

IN

25

IN

25

IN

10 26 65

OUT

61

IN

17 23 40

IN

40 41 61

IN

41

IN

PCH_DMI2RBIAS

PCH_SUSACK_L

17

PM_SYSRST_L

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PM_PCH_APWROK

PM_MEM_PWRGD

PM_RSMRST_L

PCH_SUSWARN_L

17

PM_PWRBTN_L

SMC_ADAPTER_EN

PM_BATLOW_L

PLACE_NEAR=U1800.BK20:2.54mm

1

R1920

750

1% 1/20W MF

C

201

2

PCH_RI_L

B

16 17 18 19

7

OMIT_TABLE

U1800

PCH-PPT-MB-SFF-ES1 PCH-PPT-MB-SFF-ES1

BL21

DMI0RXN

BL23

DMI1RXN

BJ19

DMI2RXN

BL17

DMI3RXN

BJ21

DMI0RXP

BJ23

DMI1RXP

BL19

DMI2RXP

BJ17

DMI3RXP

BD22

DMI0TXN

BB22

DMI1TXN

BB19

DMI2TXN

BB17

DMI3TXN

BF22

DMI0TXP

AY22

DMI1TXP

AY19

DMI2TXP

AY17

DMI3TXP

BF19

DMI_ZCOMP

BD19

DMI_IRCOMP

BK20

DMI2RBIAS

F15

SUSACK*

L1

SYS_RESET*

M10

SYS_PWROK

M22

PWROK

G3

APWROK

B12

DRAMPWROK

B20

RSMRST*

C13

SUSWARN*/SUSPWRDNACK/GPIO30

K19

PWRBTN*

H19

ACPRESENT/GPIO31

(IPD-DeepS4/S5)

H10

BATLOW*/GPIO72

F12

RI*

QP8D-MM915462

(IPU)

BGA

(3 OF 10)

FDI

DMI

CLKRUN*/GPIO32

MANAGEMENT

SYSTEM POWER

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

(IPU)

SLP_LAN*/GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE*

SLP_S4* SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10

BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10

BB10

BH12 BK8

BK12 BH8

F22

A21

D8

T2

G6

D3

F6 K10 D4

C7

A15

BB8

A7

FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7>

FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3> FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7>

FDI_INT

FDI_FSYNC<0> FDI_FSYNC<1>

FDI_LSYNC<0> FDI_LSYNC<1>

PCH_DSWVRMEN

PM_DSW_PWRGD

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

PM_SYNC

MEM_VDD_SEL_1V5_L

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

6

17 36

IN

6

BI

6

OUT

41 68

OUT

17 40 61

OUT

17 26 36 40 48 61

OUT

17 26 40 61

OUT

17 61

OUT

10 65

OUT

17 55

OUT

65

17 40 42

25 40 42

=PPVRTC_G3_PCH

1

R1915

390K

5% 1/20W MF 201

2

40

IN

1

R1909

100K

5% 1/20W MF 201

2

8

R1955

100K

1/20W

16 20

7

OUT

1

5% MF

201

2

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

8

OUT

LVDS_IG_BKL_PWM

8

OUT

TP_CRT_IG_BLUE

6

TP_CRT_IG_GREEN

6

TP_CRT_IG_RED

6

TP_CRT_IG_DDC_CLK

6

TP_CRT_IG_DDC_DATA

6

TP_CRT_IG_HSYNC

6

TP_CRT_IG_VSYNC

6

PCH_DAC_IREF

PLACE_NEAR=U1800.R51:2.54mm

1

R1951

1K

5% 1/20W

MF

201

2

M44

L_BKLTEN

M42

L_VDD_EN

L49

L_BKLTCTL

L51 K46

R42 M40

AH42 AH40

AG51 AG49

AK44 AK46

AR46 AN49 AN44 AK40

AR44 AN51 AN46 AK42

AH46 AH44

AM50 AL49 AJ51 AH50

AM48 AL51 AJ49 AH48

M46 R46 U46

R49 N49

M50 N51

R51 T48

L_DDC_CLK L_DDC_DATA

(IPD-PLTRST#)

L_CTRL_CLK L_CTRL_DATA

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK* LVDSA_CLK

LVDSA_DATA0* LVDSA_DATA1* LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK* LVDSB_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

NC NC

NC NC NC NC

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(4 OF 10)

SDVO_TVCLKINN

(IPD)

SDVO_TVCLKINP

(IPD)

SDVO_STALLN

(IPD)

SDVO_STALLP

(IPD)

SDVO_INTN

(IPD)

SDVO_INTP

(IPD)

SDVO_CTRLCLK

SDVO_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P

LVDS

DIGITAL DISPLAY INTERFACE

CRT

DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AU40 AU42

AR51 AR49

AT50 AT48

W42 R44

AW51 AW49 AY42

AY48 AY50 AY44 AY46 BB44 BB46 BA49 BA51

T50 U44

AU51 AU49 BE46

BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51

M48 U42

AU46 AU44 BK44

BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45

TP_SDVO_TVCLKINN TP_SDVO_TVCLKINP

TP_SDVO_STALLN TP_SDVO_STALLP

TP_SDVO_INTN TP_SDVO_INTP

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N DPA_IG_AUX_CH_P DPA_IG_HPD

TP_DP_IG_B_MLN<0> TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2> TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

DPB_IG_DDC_CLK DPB_IG_DDC_DATA

DPB_IG_AUX_CH_N DPB_IG_AUX_CH_P DPB_IG_HPD

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1> TP_DP_IG_C_MLP<1> TP_DP_IG_C_MLN<2> TP_DP_IG_C_MLP<2> TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXN TP_DP_IG_D_AUXP TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0> TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1> TP_DP_IG_D_MLP<1> TP_DP_IG_D_MLN<2> TP_DP_IG_D_MLP<2> TP_DP_IG_D_MLN<3> TP_DP_IG_D_MLP<3>

6

8

D

C

B

=PP3V3_SUS_PCH_GPIO

7

16 17 18 19

1

R1983

10K

5%

1/20W

MF

201

R1986

2

0

12

1/20W

5% MF

201

PCH_SUSACK_L

17

17 23 40

6

17 40 42

17 55

6

17 36

17 26 40 61

17 26 36 40 48 61

17 40 61

17 61

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH DMI/FDI/PM/Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/06/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

19 OF 109

SHEET

17 OF 72

124578

SIZE

A

D

PCH_SUSWARN_L

17

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO =PP3V3_S5_PCH

R1985 R1991

A

R1982 R1925

R1924 R1921 R1922 R1923

1K

8.2K

10K

100K 100K 100K 100K

1 2

2 1 2 1 2 1 2 1

7

16 17 18 19

7

16 18 19 25 35

7

1/20W

5%

5% MF

5% MF1K201

5%

5% 5%

1/20W

1/20W 1/20W

MF

MF MF

PM_PWRBTN_L

201

PM_CLKRUN_L

201

MEM_VDD_SEL_1V5_L

201

PCIE_WAKE_L

PM_SLP_S3_L

201

PM_SLP_S4_L

201

PM_SLP_S5_L

201

PM_SLP_SUS_L

201

8 7 6 5 4 3

12

BH24 BK24 BH20 BK16 BH16 AN42 AN40 AR40 AR42

AD10

AD44 AD46 BJ48

BH49 BB42

BJ25 BJ27 BJ31 BJ29

BL25 BL27 BL31 BL29

BF26 BB28 BF28 BF30

BD26 AY28 BD28 BD30

D20 M30

AM4 AT4 AT2

B24 D24

BL7 W40 K30

D49 C48 C47 C45

G46 K44 F46

F42 H42 D44

A47 C41 F45 F40

G51 E49 H48 J43 G45

E3

H2

F7

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24

TP41 TP42

USB3RN1 USB3RN2 USB3RN3 USB3RN4

USB3RP1 USB3RP2 USB3RP3 USB3RP4

USB3TN1 USB3TN2 USB3TN3 USB3TN4

USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA* PIRQB* PIRQC* PIRQD*

REQ1*/GPIO50 REQ2*/GPIO52 REQ3*/GPIO54

GNT1*/GPIO51 GNT2*/GPIO53 GNT3*/GPIO55

(IPU-PCIERST#)

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

PME*

PLTRSTB*

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

NC NC NC NC NC NC NC NC NC NC

D

TP_PCH_TP23

NC NC NC NC NC NC NC NC NC NC NC NC

NC

USB3_EXTA_RX_N

38 67

IN

USB3_EXTB_RX_N

39 67

IN

USB3_EXTC_RX_N

8

IN

USB3_EXTD_RX_N

8

IN

USB3_EXTA_RX_P

38 67

IN

USB3_EXTB_RX_P

39 67

C

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

R2010 R2011 R2012 R2013

B

R2054

=PP3V3_SUS_PCH_GPIO =PP3V3_S3_PCH_GPIO =PP3V3_S0_PCH_GPIO

R2016 R2017 R2018

R2030

R2014 R2031

A

R2033

R2069 R2060

R2061 R2062 R2068

R2067

10K 10K 10K

10K

10K 10K

10K

10K 10K 10K 10K

10K

7

16 17 19

7

25

7

16 17 18 19 25 35

1 2

NO STUFF

1 2

NO STUFF

1 2

1 2 1 2

2 1

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

Redundant to pull-down on audio page

5%

1/20W 1/20W

5% MF

Redundant to pull-up on audio page

5%

1/20W

5%

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1/20W

1/20W 1/20W

1/20W

JTAG_GMUX_TMS

201

MF

BLC_I2C_MUX_SEL

201

PCH_GPIO54

201

MF

BLC_GPIO

201

MF

AUD_IP_PERIPHERAL_DET

MF

201

TBT_PWR_REQ_L

201

AUD_I2C_INT_L

201

MF

201

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

201

MF5%

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

MF5%

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

201

MF5%

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

MF

201

AP_PWR_EN

201

MF

10K 10K 10K 10K

10K

1 2

1 2 1 2

1 2

NO STUFF

2 1

18

6

18 39

18 33

6

18 39

23 36 61

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

18 23

IN

8

IN

8

IN

38 67

OUT

39 67

OUT

8

OUT

8

OUT

38 67

OUT

39 67

OUT

8

OUT

8

OUT

MF

201

MF

201

MF

201

18

OUT

18

OUT

18

OUT

201

MF

18

IN

6

18 39

IN

18 33

IN

6

18 39

IN

6

25 26

OUT

25 68

OUT

25 68

OUT

6

25 68

OUT

USB3_EXTC_RX_P USB3_EXTD_RX_P

USB3_EXTA_TX_N USB3_EXTB_TX_N USB3_EXTC_TX_N USB3_EXTD_TX_N

USB3_EXTA_TX_P USB3_EXTB_TX_P USB3_EXTC_TX_P USB3_EXTD_TX_P

PCI_INTA_L PCI_INTB_L PCI_INTC_L PCI_INTD_L

JTAG_GMUX_TMS BLC_I2C_MUX_SEL PCH_GPIO54

TP_PCH_STRP_BBS1 TP_PCH_STRP_ESI_L PCH_STRP_TOPBLK_SWP_L

BLC_GPIO AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L AUD_I2C_INT_L

TP_PCI_PME_L

PLT_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

U1800

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

(5 OF 10)

USB

PCI

(IPU)

(IPD)

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

USBRBIAS*

6 3

RSVD

USBP0N USBP0P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP13N USBP13P

(IPD)

USBRBIAS

AU6 AU8 AW1 AW3 AY2 AY4 AY6 AY8 BA1 BA3 BB6 BC1 BC3 BD2 BD4 BE1 BE3 BE6 BF6 BF7 BG1 BG3 BH3 BH4 BJ4 BJ5 BJ7 BK6 BL5

F24 H24

C25 A25

C27 A27

H28 F28

M26 K26

D28 B28

H26 F26

D32 B32

M28 K28

C29 A29

C31 A31

H33 F33

H30 F30

M33 K33

C33 A33

C17 A17 A13 D16 A11 B16 C23 H15

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

USB_EXTA_N USB_EXTA_P

USB_EXTB_XHCI_N USB_EXTB_XHCI_P

USB_EXTC_N USB_EXTC_P

USB_EXTD_XHCI_N USB_EXTD_XHCI_P

TP_USB_4N TP_USB_4P TP_USB_SDN

BI BI

TP_USB_SDP

TP_USB_WLANN

TP_USB_WLANP

USB_HUB_UP_N USB_HUB_UP_P

USB_CAMERA_N USB_CAMERA_P

USB_EXTB_EHCI_N USB_EXTB_EHCI_P

USB_EXTD_EHCI_N USB_EXTD_EHCI_P

TP_USB_BT_HSN TP_USB_BT_HSP

TP_USB_12N TP_USB_12P

TP_USB_13N TP_USB_13P

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L XDP_DB2_PCH_GPIO10_AP_PWR_EN XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

BI BI

38 67

24 67

BI

24 67

BI

8

BI

8

BI

24 67

BI

24 67

BI

24 67

6

39 67

6

39 67

24 67

8

PCH_USB_RBIAS

67

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Ext D (XHCI) (Mobiles: Trackpad?)

Unused

RSVD: SD

RSVD: WiFi

USB Hub (All LS/FS Devices)

Camera

Ext B (EHCI)

Ext D (EHCI)

RSVD: BT (HS)

Unused

PLACE_NEAR=U1800.A33:2.54mm

1

R2070

2

22.6

1% 1/20W MF 201

18 23

IN

18 23

IN

18 23

IN

18 23

IN

23

IN

23

IN

23

OUT

18 23

IN

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH PCI/USB/TP/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/22/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

20 OF 109

SHEET

18 OF 72

124578

SIZE

D

C

B

A

D

OMIT_TABLE

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

12

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

(TBT_CIO_PLUG_EVENT_ISOL)

XDP_FC1_PCH_GPIO0

19 23

FW_PME_L

19

IN

DPMUX_UC_IRQ

19

IN

SMC_RUNTIME_SCI_L

19 40

IN

TP_PCH_GPIO8

WOL_EN

19

OUT

XDP_FC0_PCH_GPIO15

23

IN

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

23

OUT

LPCPLUS_GPIO

6

19 42

BI

ODD_PWR_EN_L

19

OUT

TBT_GO2SX_BIDIR

19 33

SMC_WAKE_SCI_L

19 40

IN

0

35

OUT

TBT_SW_RESET_L

R2180

1 2

5% MF

C

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L TBT_SW_RESET_R_L

19

1/20W

201

19 23

OUT

23

OUT

19

IN

19

OUT

19

OUT

8

23

OUT

6

19 42 49

BI

XDP_DC1_PCH_GPIO35_MXM_GOOD

23

OUT

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK JTAG_ISP_TDO JTAG_ISP_TDI FW_PWR_EN_PCH XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH SPIROM_USE_MLB

W1

BMBUSY*/GPIO0

B40

GPIO1

C43

GPIO6

A45

GPIO7

H17

GPIO8

C5

LAN_PHY_PWR_CTRL/GPIO12

K6

GPIO15

AA3

SATA4GP/GPIO16

B44

GPIO17

W3

SCLOCK/GPIO22

K15

GPIO24

C15

GPIO27

G1

GPIO28

R3

STP_PCI*/GPIO34

W12

GPIO35

W6

SATA2GP/GPIO36

(IPD-PLTRST#)

M6

SATA3GP/GPIO37

(IPD-PLTRST#)

N3

SLOAD/GPIO38

U10

SDATAOUT0/GPIO39

U1

SDATAOUT1/GPIO48

AA1

SATA5GP/GPIO49

K17

GPIO57

A4

A5 A48 A49 A51 BH1

BH51

VSS_NCTF

BJ1 BJ3

BJ49 BJ51

BL1 BL3 BL4

Systems with chip-down memory should add pull-downs on another page and set straps per software.

(IPU-RSMRST#)

(IPU)

(IPU-DeepS4/S5)

(IPU-RSMRST#)

U1800

QP8D-MM915462

(6 OF 10)

PCH-PPT-MB-SFF-ES1

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

OMIT_TABLE

BGA

GPIO

CPU/MISC

NCTF

GPIO68 GPIO69 GPIO70 GPIO71

A20GATE

(IPD)

RCIN*

PROCPWRGD

THRMTRIP*

INIT3_3V*

(IPU)

DF_TVS

(IPD-PLTRST#?)

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

VSS_NCTF

PECI

NC_1

K42 A43 D40 A41

U3

AU12

U6

AU10

BC9

R6

BC7

AK10 AH12 AK12 AH10

U40

BL48 BL49 BL51 C3 C49 C51 D1 D51 E1

41

NC

MLB_RAMCFG3

8

MLB_RAMCFG2

8

MLB_RAMCFG1

8

MLB_RAMCFG0

8

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

PCH_INIT3V3_L

PCH_DF_TVS

NO STUFF

R2130

1/20W

RAMCFG3:H

R2172

1/20W 1/20W

19

1

1K

This has internal pull up and should not pulled low.

5%

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

MF

201

2

10K

5%

MF

201

R2170

R2140

R2156

RAMCFG2:H

1

2

390

R2173

10K

5%

MF 201

43

0

NO STUFF

1 2

RAMCFG1:H RAMCFG0:H

1

R2174

10K

5%

1/20W

MF

201

2

CPU_PECI

1/20W

5%

201

MF

CPU_PWRGD

5%

1/20W

MF

201

PM_THRMTRIP_L

1/20W

5%

201

MF

1

R2175

10K

5% 1/20W MF 201

2

D

10 41 65

BI

10 23 65 23

OUTOUT

10 41 65

IN

R2178

1K

5%

1/20W

MF

201

=PP1V8_S0_PCH_VCC_DFTERM

1

R2179

2.2K

5% 1/20W MF 201

2

12

CPU_PROC_SEL_L DF_TVS:DMI & FDI Term Voltage Set to Vss when Low Set to Vcc when High

10

7

20 22

C

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

TBT_PWR_EN goes high for JTAG Programming

B

JTAG Isolation due to glitch in and out of sleep

NOTE: TCK from PCH is Push-Pull CMOS NOTE: TMS/TDI from PCH is Open Drain

=PP3V3_S5_PCH_GPIO =PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

Stuff R2160 or R2574, not both

R2160 R2185 R2196 R2190

R2197 R2184

R2150 R2155

A

R2194 R2192 R2193

R2191 R2111

R2195 R2112 R2198

R2116

10K 10K 10K

100K

10K 10K

100K

10K

20K

100K

10K 10K

10K

NO STUFF

1 2

1 2 1 2

NO STUFF

1 2 1 2

1 2

1 2 1 2

1 2

2 1 2 1 2 1 2 1

2 1

7

16 17 18

7

16 17 18 19 25 35

1/20W

5% 5%

1/20W

Must stuff R2197 when R2180 NO STUFFed.

1/20W

5%

1/20W

5% MF

5%

1/20W

5%

1/20W

5% MF

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

5% MF

XDP_FC1_PCH_GPIO0

MF5%

201

FW_PME_L

201

MF

SMC_RUNTIME_SCI_L

MF

201

LPCPLUS_GPIO

MF5%

201

TBT_SW_RESET_R_L

MF5%

201

FW_PWR_EN_PCH

MF

201

PCH_A20GATE

201

PCH_RCIN_L

201

MF

WOL_EN

MF

201

TBT_GO2SX_BIDIR

201

SPIROM_USE_MLB

201

SMC_WAKE_SCI_L

201

MF

DPMUX_UC_IRQ

MF

201

AUD_IPHS_SWITCH_EN_PCH

201

MF

ODD_PWR_EN_L

201

MF

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

201

ENET_LOW_PWR_PCH

201

19 23

19

19 40

6

19 42

19

19 33

6

19 42 49

19 40

19

23 25

19

19 23

8

=PP3V3_S0_PCH_STRAPS

7

19

JTAG_ISP_TMS

16 33

IN

=PP3V3_S0_PCH_STRAPS

7

19

JTAG_ISP_TDI

19 33

IN

=PP3V3_S0_PCH_STRAPS

7

19

JTAG_ISP_TDO

19

OUT

NOTE: TDO from CR is Push-Pull CMOS

CRITICAL

5% 1/20W MF 201

Q2160

SSM6N15AFE

SOT563

D

6

1

R2188

10K

2

CRITICAL

R2199

10K

5% 1/20W MF 201

Q2160

SSM6N15AFE

SOT563

CRITICAL

Q2162

SSM3K15FV

SOD-VESM-HF

D

3

1

2

1

R2186

10K

5%

MF 201

2

=PP3V3_TBT_PCH_GPIO

1

2

S G

1

R2163

10K

5% 1/20W MF 201

2

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

1

5

D

3

S G

4

R2161

10K

5% 1/20W MF 201

2

JTAG_TBT_TDI

=PP3V3_TBT_PCH_GPIO

1

GS

2

R2162

10K

5% 1/20W1/20W MF 201

2

JTAG_TBT_TDO

7

19

OUT

7

19

TBT_CIO_PLUG_EVENT

33

IN

OUT

7

19

33

IN

TBT_PWR_EN

25 33

JTAG_ISP_TCK

23

1

R2113

10K

5% 1/20W MF 201

2

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

1

R2166

10K

5% 1/20W MF 201

2

6 3

C2114

0.1UF

X5R-CERM

C2113

0.1UF

X5R-CERM

10% 16V

0201

1

10% 16V

2

0201

2

U2100

1

NC

5

6

08

3

CRITICAL

74LVC1G08

SOT891

4

JTAG_TBT_TCK

33

OUT

B

NC

1

2

U2101

1

NC

5

NC

6

08

3

CRITICAL

74LVC1G08

SOT891

4

TBT_CIO_PLUG_EVENT_ISOL

NO STUFF

1

R2167

10K

5% 1/20W MF 201

2

23

OUT

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH GPIO/MISC/NCTF

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/23/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

21 OF 109

SHEET

19 OF 72

SIZE

A

D

124578

8 7 6 5 4 3

12

D

PLACE_NEAR=U1800.R15:2.54mm

C2210

X5R-CERM

C

C2222

X5R-CERM

7

16 17

PLACE_NEAR=U1800.N16:2.54mm

B

VCCACLK pin left as NC per DG

PCH output, for decoupling only

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

10% 16V

2

0201

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

=PPVRTC_G3_PCH

PLACE_NEAR=U1800.U17:2.54mm

10% 16V

2

0201

C2231

1UF

6.3V 0201

VCCAPLLDMI2 pin left as NC per DG

AL24 left as NC per DG

22

1

20% X5R

2

PLACE_NEAR=U1800.N16:2.54mm

PCH output, for decoupling only

=PP3V3_S5_PCH_VCCDSW

7

22

TP_PPVOUT_PCH_DCPSUSBYP

PPVOUT_G3_PCH_DCPRTC

PP1V05_S0_PCH_VCCADPLLA_F

22

PP1V05_S0_PCH_VCCADPLLB_F

22

=PP1V05_S0_PCH_VCCDIFFCLK

7

16 22

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCSSC

7

22

PPVOUT_S0_PCH_DCPSST

PP1V05_S0_PCH_VCCCLKDMI_F

22

=PP1V05_S0_PCH_V_PROC_IO

7

22

=PP1V05_S0_PCH_VCCASW

7

C2232

0.1UF

10% 16V X5R-CERM 0201

1

C2233

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=U1800.N16:2.54mm

D

AC51

R12

R10

AW31

R15 U15

BF40 BD40

AC37 AE37 AE39

AC35

U17

AP39

AM17

N16

AB27 AB29 AB31 AC27 AC29 AC31 AE27 AE29 AE31

R19 U19 U21 V19 V21 V23 V25 Y21 Y23

Y25

Y27 Y29 Y31

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCCAPLLDMI2

DCPRTC

VCCADPLLA VCCADPLLB

VCCDIFFCLKN

VCCSSC

DCPSST

VCCCLKDMI

V_PROC_IO

VCCRTC

VCCASW

NC

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(8 OF 10)

USB

PCI/GPIO/LPC

SATA

HDA

CLK/MISC

CPURTC

V5REF_SUS

VCCPUSB

VCCAPLL_SATA3

VCCSUSHDA

VCCSUS3_3

V5REF

VCCIO

DCPSUS

VCCVRM

M37

=PP5V_SUS_PCH_V5REFSUS

U27

=PP3V3_SUS_PCH_VCCSUS_USB

U29

N36

=PP5V_S0_PCH_V5REF

AM2

NC

NC-ed per DG

V31

=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

AA13

=PP1V05_S0_PCH_VCCIO AB15 AC13 AC15 AF15 AG13 AG15 AJ17 AK21 N18 R23 R25 U23 U25

AM27

=PP3V3_SUS_PCH_VCCSUS N27 R27 R29 R33 R35 U33 U35

AR33

NC

AU31

NC

AU33

NC

V13

NC

AC39

=PP1V8R1V5_S0_PCH_VCCVRM AE19 AF17 AW18 AW21

22

7

22

7

22 25

7

20 22

7

22

7

20

=PP1V05_S0_PCH_VCC_CORE

7

22

1.44 A Max, 474mA Idle

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCCIO

7

20 22

AB21 AB23 AC21 AC23 AE21 AE23 AF21 AF23 AG21 AG23 AG25 AG27 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AK29 AK31 AK33 AM33 AM35

AP19

AM21 AP27 AR15 AR23 AR25 AR27 AR29 AT13 AU23 AU25 AU27 AU29 AU35 AW34

PCH-PPT-MB-SFF-ES1PCH-PPT-MB-SFF-ES1

VCCCORE

VCCAPLLEXP

VCCIO

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(7 OF 10)

CRTFDI

VCC CORE

LVDS

DMI

DFT/SPI

VCCIO

VCCADAC

VSSA_DAC

VCCALVDS

VSSALVDS

VCCTX_LVDS

VCCDMI

VCCADMI_VRM

VCCDFTERM

VCCSPI

VCCAFDIPLL

VCCAFDI_VRM

VCC3_3

U51

PP3V3_S0_PCH_VCCA_DAC_F

V50

AF33 AG33 AC33 AE33

AF37 AG37 AG39 AJ37

AM23

=PP1V05_S0_PCH_VCC_DMI AU15 AW16 AU21

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_PCH_VCC_DFTERM AJ13 AJ15 AK15 AL13

Y19

=PP3V3_SUS_PCH_VCC_SPI

AP13

NC

AP15

NC

AU19

=PP1V8R1V5_S0_PCH_VCCVRM

AB19

=PP3V3_S0_PCH_VCC3_3

AC19 AF6 BK28 R40 T39 U37 V37

PP3V3_S0_PCH_VCC3_3_CLK_F

V39

22

7

22

7

20

7

19 22

7

22

7

20

7

22

C

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/22/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

22 OF 109

SHEET

20 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

AA7 AA9

PCH-PPT-MB-SFF-ES1

AA11 AA39 AA41 AA43 AA45

D

C

B

A

AB2

AB4 AB17 AB25 AB33 AB35 AB37 AB48 AB50

AC7

AC9 AC11 AC17 AC25 AC41 AC43 AC45

AE7

AE9 AE11 AE13 AE15 AE17 AE25 AE35 AE41 AE43 AE45

AF2

AF4

AF8 AF19 AF25 AF27 AF29 AF31 AF35 AF48 AF50

AG7

AG9 AG11 AG17 AG19 AG29 AG31 AG35 AG41 AG43 AG45

AH2

AJ7

AJ9 AJ11 AJ19 AJ33 AJ35 AJ39 AJ41 AJ43 AJ45

AK2

AK4 AK17 AK19 AK23 AK25 AK27 AK35 AK37 AK48 AK50

AL7

AL9 AL11 AL39 AL41 AL43 AL45 AM15 AM19 AM25 AM29 AM31 AM37

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(9 OF 10)

AP2 AP4 AP7 AP9 AP11 AP17 AP21 AP23 AP25 AP29 AP31 AP33 AP35 AP37 AP41 AP43 AP45 AP48 AP50 AR6 AR8 AR17 AR19 AR21 AR31 AR35 AR37 AT7 AT9 AT11 AT39 AT41 AT43 AT45 AU17 AU37 AV2 AV4 AV48 AV50 AW7 AW9

VSSVSS

AW11 AW13 AW23 AW25 AW27 AW29 AW36 AW39 AW41 AW43 AW45 AY10 B6 B10 B14 B18 B22 B26 B30 B34 B38 B42 B46 BA7 BA9 BA11 BA13 BA16 BA18 BA21 BA23 BA25 BA27 BA29 BA31 BA34 BA36 BA39 BA41 BA43 BA45 BB2 BB4 BB48 BB50 BC11 BC13 BC16 BC18 BC21

BC23 BC25

PCH-PPT-MB-SFF-ES1

BC27 BC29 BC31 BC34 BC36 BC39 BC41 BC43 BC45 BD15 BD24

BE7

BE9 BE11 BE13 BE16 BE18 BE21 BE23 BE25 BE27 BE29 BE31 BE34 BE36 BE39 BE41 BE43 BE45

BF2

BF4 BF15 BF24 BF48 BF50

BH6 BH10 BH14 BH18 BH22 BH26 BH28 BH30 BH32 BH34 BH38 BH42 BH44 BH46 BH48 BK10 BK14 BK18 BK22 BK26 BK30 BK32 BK34 BK38 BK42 BK46

D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46

F2

F4 F48 F50

G7

G9 G11 G13 G16 G18 G21 G23 G25 G27 G29 G31 G34 G36

6 3

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(10 OF 10)

G39 G41 G43 J7 J9 J11 J13 J16 J18 J21 J23 J25 J27 J29 J31 J34 J36 J39 J41 J45 K2 K4 K48 K50 L7 L9 L11 L13 L16 L18 L21 L23 L25 L27 L29 L31 L34 L36 L39 L41

VSSVSS

L43 L45 N7 N9 N11 N13 N21 N23 N25 N29 N31 N34 N39 N41 N43 N45 P2 P4 P48 P50 R17 R21 R31 R37 T7 T9 T11 T13 T41 T43 T45 U31 U49 V2 V4 V7 V9 V11 V15 V17 V27 V29 V33 V35 V41 V43 V45 V48 Y15 Y17 Y33 Y35 Y37

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=08/12/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

23 OF 109

SHEET

21 OF 72

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

PCH VCCIO BYPASS

L2406

=PP1V05_S0_PCH

7

16

10UH-0.12A-0.36OHM

1 2

0603

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

PLACE_NEAR=U1800.AP39:2.54mm

R2415

0

1 2

5%

1/20W

MF

201

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE

1

C2411

10UF

20%

6.3V

2

CERM-X5R 0402-2

20

PLACE_NEAR=U1800.R27:2.54mm

D

7

20

PLACE_NEAR=U1800.AM17:2.54mm PLACE_NEAR=U1800.AM17:2.54mm PLACE_NEAR=U1800.AM17:2.54mm

=PP3V3_S0_PCH_VCCADAC

7

R2450

0

1 2

5%

1/20W

MF

201

C2450

10UF

20%

6.3V

CERM-X5R

0402-2

PLACE_NEAR=U1800.U51:2.54mm PLACE_NEAR=U1800.U51:2.54mm PLACE_NEAR=U1800.U51:2.54mm

1

2

C2451

0.1UF

10% 16V

X5R-CERM

0201

PP3V3_S0_PCH_VCCA_DAC_F

0.01UF

X5R-CERM

0201

10% 16V

1

2

1

2

C2455

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

20

C

=PP3V3_S0_PCH

7

16

=PP5V_S0_PCH

7

25

1 mA

R2405

C2439

PLACE_NEAR=U1800.N36:2.54mm

=PP3V3_SUS_PCH

7

=PP5V_SUS_PCH

7

1 mA S0-S5

B

PLACE_NEAR=U1800.M37:2.54mm

=PP3V3_S0_PCH_VCC3_3

7

20 22

1

C2421

0.1UF

10% 16V

2

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

A

=PP3V3_S0_PCH_VCC3_3

7

20 22

PLACE_NEAR=U1800.T39:2.54mm

0201

100

1/20W

201

1UF

10% 10V X5R 402

R2404

1/20W

C2438

0.1UF

20% 10V

CERM

402

1

C2424

0.1UF

10% 16V

2

X5R-CERM 0201

12

5% MF

1

2

12

10

5% MF

201

1

2

20 22

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

1

5

D2400

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)

4

2

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S0_PCH_VCC3_3

7

PLACE_NEAR=U1800.AF6:2.54mm

NEED PWR CONSTRAINT

<1 MA

20

NEED PWR CONSTRAINT

1

C2423

0.1UF

10% 16V

2

X5R-CERM 0201

=PP3V3_S0_PCH_VCC3_3

7

20 22

20

=PP3V3_S0_PCH_VCC3_3

7

20 22

PLACE_NEAR=U1800.AB19:2.54mm

1

C2485

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=U1800.R40:2.54mm

=PP3V3_S0_PCH_VCC3_3_CLK

7

PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)

=PP3V3_SUS_PCH_VCCSUS

7

20 22

1

C2484

0.1UF

10% 16V

2

X5R-CERM 0201

=PP1V05_S0_PCH_V_PROC_IO

C2416

=PP1V05_S0_PCH_VCC_DMI

7

20 22

PLACE_NEAR=U1800.AM23:2.54mm

=PP1V05_S0_PCH_VCC_DMI

7

20 22

PLACE_NEAR=U1800.AW16:2.54mm

R2451

=PP1V05_S0_PCH_VCCADPLL

1

C2422

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2413

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=U1800.N27:2.54mm

1

C2417

4.7UF

20%

6.3V X5R 402

1

1 2

5% 1/16W MF-LF

402

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2419

1UF

20%

6.3V

2

X5R 0201

1

C2418

1UF

20%

6.3V

2

X5R 0201

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

R2460

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1800.BF40:2.54MM

R2465

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1800.BD40:2.54MM

1

C2430

2

1

C2402

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2465

0.1UF

10% 16V

2

X5R-CERM 0201

0.1UF

10% 16V X5R-CERM 0201

=PP1V8_S0_PCH_VCC_DFTERM

7

19 20

PLACE_NEAR=U1800.AJ13:2.54mm

PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

=PP3V3R1V5_S0_PCH_VCCSUSHDA

7

20 25

PLACE_NEAR=U1800.V31:2.54mm

=PP3V3_SUS_PCH_VCC_SPI

7

20

PLACE_NEAR=U1800.Y19:2.54mm

=PP3V3_S5_PCH_VCCDSW

7

20

PLACE_NEAR=U1800.R12:2.54mm

L2451

10UH-0.12A-0.36OHM

1 2

0603

PLACE_NEAR=U1800.V37:2.54mm

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C2461

1UF

20%

6.3V

2

X5R 0201

PCH VCCADPLLB Filter (PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C2466

1UF

20%

6.3V

2

X5R 0201

PP3V3_S0_PCH_VCC3_3_CLK_F

20

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

10UF

20%

6.3V

CERM-X5R

0402-1

PLACE_NEAR=U1800.V37:2.54mm

1

2

C2453

PLACE_NEAR=U1800.BF40:2.54MM

PLACE_NEAR=U1800.BD40:2.54MM

C2499

0.1UF

X5R-CERM

0201

68 mA

69 mA

10% 16V

1

2

1

C2441

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2442

1UF

20%

6.3V

2

X5R 0201

1

2

20

C2440

0.1UF

10% 16V X5R-CERM 0201

C2486

1UF

10% 10V X5R 402

1

2

=PP1V05_S0_PCH_VCCIO_SATA

7

16

1

C2444

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AB15:2.54mm

=PP1V05_S0_PCH_VCCSSC

7

20

PLACE_NEAR=U1800.AC35:2.54mm

=PP1V05_S0_PCH_VCCDIFFCLK

7

16 20

PLACE_NEAR=U1800.AC37:2.54mm

=PP1V05_S0_PCH_VCC_CORE

7

20

=PP1V05_S0_PCH_VCCIO

7

20 22

1

C2429

1UF

20%

6.3V

2

X5R 0201

=PP1V05_S0_PCH_VCCASW

7

20

1

2

1

C2452

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AG13:2.54mm

1

C2481

1UF

20%

6.3V

2

X5R 0201

1

C2414

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AR25:2.54mm PLACE_NEAR=U1800.AU25:2.54mm PLACE_NEAR=U1800.AU29:2.54mm PLACE_NEAR=U1800.AR29:2.54mm PLACE_NEAR=U1800.AU27:2.54mm

1

C2426

1UF

20%

6.3V X5R 0201

C2456

1UF

20%

6.3V

2

X5R 0201

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

(PCH USB 1.05V PWR)

7

20

1

C2475

1UF

20%

6.3V

2

X5R 0201

1

C2434

1UF

20%

6.3V

2

X5R 0201

1

C2482

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AB21:2.54mm PLACE_NEAR=U1800.AB21:2.54mm PLACE_NEAR=U1800.AB21:2.54mm PLACE_NEAR=U1800.AB21:2.54mm

1

C2407

1UF

20%

6.3V

2

X5R 0201

1

C2496

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm

R

=PP3V3_SUS_PCH_VCCSUS_USB

PLACE_NEAR=U1800.U27:2.54mm

=PP3V3_SUS_PCH_VCCSUS

7

20 22

PLACE_NEAR=U1800.R33:2.54mm

=PP1V05_S0_PCH_VCCIO

7

20 22

PLACE_NEAR=U1800.AJ17:2.54mm

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)

1

C2483

1UF

20%

6.3V

2

X5R 0201

1

C2463

1UF

20%

6.3V

2

X5R 0201

C2428

X5R-CERM1

22UF

6.3V 0603

C2460

CERM-X5R

20%

PCH DECOUPLING

Apple Inc.

6 3

10UF

20%

6.3V

0402-2

C2401

CERM-X5R

1

C2420

2

X5R-CERM1

10UF

6.3V

0402-2

22UF

1

2

20%

12

20%

6.3V 0603

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

1

C2446

1UF

20%

6.3V

2

X5R 0201

1

C2476

1UF

20%

6.3V

2

X5R 0201

1

C2469

1UF

20%

6.3V

2

X5R 0201

1

2

1

2

SYNC_DATE=11/18/2011

051-9276

2.7.0

24 OF 109

22 OF 72

SIZE

D

C

B

A

D

Apple MacBook Air A1465 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual