Apple MacBook Air A1465 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK APPD

DATE

2012-02-23

J11 MLB PIB SCHEMATIC

2.6.0

D

C

B

Page Sync

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

1

Table of Contents

2

2 3 4

7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

40 41 42 43 44 45

System Block Diagram

3

Revision History

4

K78 BOM Variants

5

BOM Configuration

7

Functional Test / No Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU GROUNDS

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIe/CLK/LPC/SPI

19

PCH DMI/FDI/PM/Graphics

20

PCH PCI/USB/TP/RSVD

21

PCH GPIO/MISC/NCTF

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

USB HUB & MUX

27

Clock (CK505) and Chipset Support

28

CPU Memory S3 Support

29

DDR3 DRAM CHANNEL A (0-31)

30

DDR3 DRAM CHANNEL A (32-63)

31

DDR3 DRAM CHANNEL B (0-31)

32

DDR3 DRAM CHANNEL B (32-63)

33

FSB/DDR3/FRAMEBUF Vref Margining

34

DDR3 DRAM Channel B (32-63)

36

Thunderbolt Host (1 of 2)

37

Thunderbolt Host (2 of 2)

38

TBT Power Support

40

X21 WIRELESS CONNECTOR

45

SSD CONNECTOR

46

External A USB3 Connector

47

LIO CONNECTORS

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Voltage & Load Side Current Sensing

54

High Side Current Sensing

Contents

MASTER1

J13_MLB

K21_MLB J11_MLB_NON_POR5 (K99_MLB)6

K91_MLB

J13_MLB

K21_MLB

J11_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

J13_MLB N/A39

J30_MLB

J13_MLB

K21_MLB

J13_MLB

02/23/12

Date

MASTER

11/18/2011

11/16/2010

11/09/2011

(02/16/2010)

05/15/2010

10/13/2011

09/22/2011

12/13/2010

10/18/2011

12/13/2010

08/16/2011

12/13/2010

02/20/2012

10/06/2011

09/22/2011

02/23/2012

09/22/2011

08/12/2011

11/18/2011

08/04/2011

08/12/2011

11/18/2011

08/29/2011

11/18/2011

12/13/2010

02/22/2012

09/01/2011

11/18/2011

10/06/2011

11/18/2011

10/06/2011

N/A

07/26/2011

10/06/2011

12/13/2010

10/05/2011

09/15/2011

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Page

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

(.csa)

55

Thermal Sensors

56

Fan

57

IPD / KBD Backlight

61

SPI ROM

62

AUDI0: SPEAKER AMP

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPU VCCIO (1.05V) Power Supply

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

90

Internal DisplayPort Connector

94

Thunderbolt Connector A

97

LCD Backlight Driver

100

CPU Constraints

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

105

Thunderbolt Constraints

106

SMC Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

Contents

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

K21_MLB

J13_MLB

CONSTRAINTS

Sync

Date

08/30/2011

12/13/2010

10/13/2011

12/13/2010

11/11/2010

10/10/2011

09/01/2011

11/18/2011

10/07/2011

09/22/2011

12/13/2010

09/01/2011

12/13/2010

11/18/2011

12/13/2010

11/18/2011

10/13/2011

01/11/2012

D

C

B

A

Schematic / PCB #’s

PART NUMBER

051-9276 CRITICAL

820-3208 CRITICAL

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Thu Feb 23 12:05:40 2012

QTY

SIZE

A

D

DRAWING TITLE

SCHEM,MLB,J11

DESCRIPTION

1

SCHEM,MLB,J11

PCBF,MLB,J11

REFERENCE DES

SCH

PCB

CRITICAL

BOM OPTION

PRODUCT SAFETY REQUIREMENTS: PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94. PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

Apple Inc.

R

3

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

1 OF 109

SHEET

1 OF 72

1245678

8 7 6 5 4 3

12

64-bit

Misc

PG 19

SPI

PG 16

LPC

PG 16

8

7

6

5

4

3

(UP TO 10 DEVICES)

2

1

0

432 9

PG 18

1

PG 40

J2500

CPU

XDP CONN

PG 23

J5100

LPC+SPI

CONN

PG 43

USB CAMERA

U3100-U3130 U3200-U3230

MEMORY

x8

PG 29,30

U2900-U2930 U3000-U3030

MEMORY

x8

PG 27,28

U4700

USB3

Re-DRIVER

PG 40

U6100

SPI

Boot ROM

PG 50

U2660

XHCI/EHCI2

MUX

PG 24

LEFT USB EXTB

U2600

USB HUB

U4650

MOJO SMC

DEBUG MUX

PG 39

SPK

U4900

SERIAL PORT

PM_SLP S3/S4

PG 24

I2C

LID

J6950,U7000

CHARGER

PG 52,53

U5510

CPU TEMP SENSOR

U5410

TBT/MLBBOT/INLET TEMP SENSOR

VOLTAGE/CURRENT SENSOR

J5600

FAN CONN

SMB_1SMB_5

SMB_3

FAN0

ADC

SMC

PG 41

USB

J5700

PG 46,47

PG 45,46

PG 48

KBDLED

LID

SMB_2

PG 47

POWER CIRCUIT

PG 54-60

U5750

KBD DRIVER

PG 49

J5715

KBD CONN

PG 49

D

C

TRACKPAD

PG 49

U5700

USB MUX

PG 49

3 4 2 1

J4600

EXTERNAL

USB A

PG 39

U6210

SPEAKER

AMP

PG 51

J6903

RIGHT SPEAKER

CONN

PG 52

J4001

Bluetooth

(ON AP)

PG 37

B

J9000

EDP

CONN

PG 63

U3690

EEPROM

U4510

MUX

PG 38

32KHz

U2700

SYSTEM

CLOCK

25MHz

Xtal

U3600

TBT Host

PA_AUX

PA_DPSRC_1 PA_DPSRC_3

PA_LSTX/LSRX

PA_CIO1 PA_CIO0

SPI

PG 34,35 37

PG 34

J4001

X21

WIRELESS

CONN

PG 37

PCIe x4

SNK0

SNK1

PG 25

BUFFER

25MHz

SATA0

SATA

UP TO 6

LVDS OUT

RGB OUT

TMDS OUT HDMI OUT

DVI OUT

x4

DPB

x4

DPC

7 4

5 38 16

2

J4501

D

C

J9400

DISPLAY PORT

/ TBT

PG 64

SATA Conn

HDD

PG 38

U9420

AUXIO

DPMLO

MUX

PG 64

B

JTAG

J2550

PCH

XDP CONN

PG 23

RTC

PG 16

CLK

PG 16

DP OUT

PG 17

PG 16

DP0, x1

EDP

PCIE1

PCIE0

UP TO 8 LANES

PCI-E

EDP

PG 9

PCI-E

PG 9

PANTHER POINT - MPCH

SMBUS

PG 16

U1000

INTEL CPU

IVY BRIDGE 2C-35W

AXG=GT2, ULV, 1023P

FDI

PG 9 PG 9

FDI

PG 17

INTEL

U1800 1017P

PCI

PG 18

JTAG

PG 10

B

A

DUAL Channel

MEMORY

DMI

PG 17

HDA

PG 16

J4700

HDA

DDR3-1600MHZ

PG 11

GPIOs

PG 19

PWR

CTRL

PG 17

USB

PG 18

USB 3

LEFT L/O CONN

U6201

CodecAudio

PG

A

U6620

SPEAKER

AMP

PG 10

J6702

LEFT SPEAKER

CONN

PG 11

LINE IN FILTER

PG

J6700

HEADPHONE/

LINE IN JACK

HEADPHONE Filter

PG 11

PG 9

J6701

MIC

CONN

PG 11

J4720

CAMERA +ALS CONN

6 3

I2C

PG 7

LIO BOARD

J4610

USB PORT B

(LEFT PORT)

U4730

PG 6

THERMAL

SENSOR

PG 7

J4750

I2C

HALL

EFFECT

PG 7

SIZE

A

D

SYNC_MASTER=J13_MLB

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

2 OF 109

SHEET

2 OF 72

124578

8 7 6 5 4 3

12

J11 POWER SYSTEM ARCHITECTURE

D

J6900

F6901

AC

ADAPTER

DCIN(14.5V)

IN

J6950

2S3P

C

(6 TO 8.4V)

SMC

U4900

P60

(PAGE 41)

SLP_S5#(E4)

COUGAR-POINT

SLP_SUS#

(PCH)

B

A

U1800

(PAGE 16~21)

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

SLP_S4#(H4)

SLP_S3#(F4)

PM_SLP_S3_R_L

1V05_S0_LDO_EN

CPUVCCIOS0_EN

PVCCSA_EN

P1V5S0_EN

P1V8S0_EN

6A FUSE

PPVBATT_G3H_CONN

6

SMC_PM_G2_EN

PM_SLP_SUS_L

21 21

22 19

17

4

RC

DELAY

PM_SLP_S5_L

U7940

RC

DELAY

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

R7978

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

SMC_DCIN_ISENSE

SMC_RESET_L

P3V3S5_EN

PG 17

P5V_3V3_SUS_EN

P3V3S3_EN

DDRREG_EN

USB_PWR_EN

P5VS3_EN

PG 17

PG62

14-1 14-1 14-1

PPDCIN_G3H_OR_PBUS

V

1

R7020

A

CHGR_BGATE

7

11

10-1

PG61

PG62

13

PG62

15

PG62

13-2 13 14

Q5310

SMC_GFX_VSENSE

D7005

U7000

VIN

ISL6259HRTZ

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 53)

Q7055

&&

1

PPVBAT_G3H_CHGR_R

F9700

3A 32V

LCD_BKLT_EN

BKLT_PLT_RST_L

BKL_EN

PBUSVSENS_EN

T29_A_HV_EN

R6905

VOUT

Q9706

EN

Q5300

Q3880

TBTBST_EN_UVLO

ENABLE

PP5V5_CHRG_VDDP

LT3470A

U7090

(PAGE 53)

PPVBAT_G3H_CHRG_RET

R7050

SMC_BATT_ISENSE

Q5300

SMC_PBUS_VSENSE

V

R5430

A

13-1

7

VIN

LP8550

U9701

(PAGE 65)

LT3957

U3890

EN/UVLO

(PAGE 36)

6 3

PP5V5_CHAR_VDDP

1

A

PPVIN_S5_P5VP3V3

P5VS3_EN

P3V3S5_EN

PPVOUT_SW_LCDBKLT

VOUT

SMC_PBUS_VSENSE

VIN

PP15V_T29_REG

VOUT

PPVIN_G3H_P3V42G3H

F7040

PPBUS_G3H

VIN

5V

EN1

(L/H)

3.3V

EN2

(R/H)

TPS51980

U7201

(PAGE 55)

PGOOD

P5VS3_PGOOD

P3V3S5_PGOOD

VOUT1

VOUT2

R0954

PP5V_S3_REG

PP3V3_S5_REG

14-1

9

A

R6906

PP3V3_S5

P5V_3V3_SUS_EN

Q7830

P3V3S0_EN

14

Q7820

Q7810

P3V3S3_EN

Q7840

D6905

22

8

10-3

PP3V3_SUS_FET

PP3V3_S3_FET

PP5V_SUS_FET

2

15

PP5V_S0_CPUVCCIOS0.

CPUVCCIOS0_EN

21

24

CPUIMVP_VR_ON

DDRREG_EN

DDRVTT_EN

PP5V_S0_VCCSA

PVCCSA_EN

CPU_VCCSA_VID<1> CPU_VCCSA_VID<0>

14

TPS720105

U7740

14-1

10-2

R7831

A

Q7860

P5VS0_EN

(PAGE 60)

PP3V3_S0

P1V8_S0_EN

17

T29_PWR_EN

ENABLE

VCC

EN

(PAGE 59)

MAX15120

VR_ON

(PAGE 57)

S5

S3

(PAGE 56)

VCC

EN

VID1

VID0

R4599

A

1.05V

ISL95870

TPS51916

3.425V G3HOT

LT3470A

U6990

(PAGE 52)

VIN

VOUT

U7600

PGOOD

VIN

VOUT

CPU VCORE

U7400

VOUT

PGOOD

PGOODG

VIN

VLDOIN

1.5V

VOUT1

0.75V

VOUT2

U7300

PGOOD

ISL95870AH

U7100

(PAGE 54)

PGOOD

PP5V_S0_KBDLED

SMC_SYS_KBDLED

10-4

PP1V05_SUS_LDO

16

ISL8014A

EN

U7720

(PAGE 60)

TPS22924

EN

U3810

(PAGE 36)

PP3V3_S0_SSD_R

PP3V42_G3H_REG

CPUVCCIOS0_PGOOD

CPUIMVP_PGOOD

CPUIMVP_AXG_PGOOD

PPVTT_S0_DDR_LDO

16-1

DDRREG_PGOOD

PPVCCSA_S0_REG

VOUT

PVCCSA_PGOOD

PP5V_S0_FET

VIN

EN

PP5V_S0_VMON PP1V5_S3RS0_VMON

PP1V05_S0_VMON

PP1V8_S0_REG

1V05_S0_LDO_EN

PP3V3_T29_FET

R7640

A

SMC_CPU_FSB_ISENSE

R7510

SMC_CPU_ISENSE

A

R7550

SMC_GFX_ISENSE

A

P1V5CPU_EN

15

U5750

MIC2292

OUT

PAGE49

PP3V3_S0_VMON

P1V8S0_PGOOD

PPCPUVCCIO_S0_REG

22-1

PPVCORE_S0_CPU_REG

PPVCORE_S0_AXG_REG

25-1

R7350

PPDDR_S3_REG

A

23-1

KBDLED_ANPDE

6

VDD

V2MON

U7960

ISL88042IRTEZ

V3MON

V4MON

(PAGE 62)

18

TPS720105

EN

U7780

(PAGE 60)

U7770

TPS72015

(PAGE 60)

EN

PP1V5S0_EN

3

16

Q7801

PP1V5_S3RS0_FET

R7140

PP1V05_S0_LDO.

SMC POWER

SN0903048

U5010

(PAGE 42)

U3816/U3820

25

ALL_SYS_PWRGD

23

P1V8S0_PGOOD

P5VS3_PGOOD

P3V3S5_PGOOD

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

R7962

4

PP1V5_S0_REG

22

TPS22920

(PAGE 36)

EN

26

U2750

ALL_SYS_PWRGD

19

SMC_RESET_L

PP1V05_TBTCIO_FET

TBT_PWR_EN

PM_S0_PGOOD

SMC_DELAYED_PWRGD

25

S5_PWRGD

SMC_ONOFF_L

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

4

COUGAR-POINT

27

PM_PCH_PWRGD

U2760

(PAGE 16~21)

CPU

U1000

(PAGE 9~13)

SMC

PWRGD(P12)

9

RSMRST_IN(P13)

PWR_BUTTON(P90)

5

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

(PAGE 41)

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

PWRBTN#

(PCH)

SYS_RERST#

RSMRST#

U1800

DPWROK

PLTRST#

PROCPWRGD

DRAMPWROK

SM_DRAMPWROK

UNCOREPWRGOOD

RESET*

P15

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

SYSRST(PA2)

P17(BTN_OUT)

RST*

U4900

Apple Inc.

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

30

PM_DSW_PWRGD

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PM_DSW_PWRGD

29

28

10

12

26 6-1

4

SYNC_DATE=11/18/2011

Revision History

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

3 OF 109

SHEET

3 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

BOM Variants

BOM NUMBER

639-3469

639-3470

639-3473

639-3659

639-3471

639-3472

639-3775

639-3474

639-3774

639-3660

639-3776

639-3778

639-3780

639-3777

639-3779

639-3781

085-3937

607-9089

939-0479

BOM NAME

PCBA,MLB,1.5GHZ,HY 4GB,J11

PCBA,MLB,1.5GHZ,SA 4GB,J11

PCBA,MLB,1.5GHZ,HY 8GB,J11

PCBA,MLB,1.5GHZ,EL 8GB,J11

PCBA,MLB,1.7GHZ,HY 4GB,J11

PCBA,MLB,1.7GHZ,SA 4GB,J11

PCBA,MLB,1.7GHZ,EL 4GB,J11

PCBA,MLB,1.7GHZ,HY 8GB,J11

PCBA,MLB,1.7GHZ,SA 8GB,J11

PCBA,MLB,1.7GHZ,EL 8GB,J11

PCBA,MLB,2.0GHZ,HY 4GB,J11

PCBA,MLB,2.0GHZ,SA 4GB,J11

PCBA,MLB,2.0GHZ,EL 4GB,J11

PCBA,MLB,2.0GHZ,HY 8GB,J11

PCBA,MLB,2.0GHZ,SA 8GB,J11

PCBA,MLB,2.0GHZ,EL 8GB,J11

J11 MLB DEVELOPMENT BOM

CMN PTS,PCBA,MLB,J11

PCBA,MLB,1.9GHZ,HY 4GB,J11

BOM OPTIONS

J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKL,DDR3:HYNIX_4GB

J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKH,DDR3:SAMSUNG_4GB

J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKJ,DDR3:HYNIX_8GB

J11_CMNPTS,CPU:1.5GHZ,EEEE:F0V3,DDR3:ELPIDA_8GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKK,DDR3:HYNIX_4GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKF,DDR3:SAMSUNG_4GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:F27J,DDR3:ELPIDA_4GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKG,DDR3:HYNIX_8GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:F27D,DDR3:SAMSUNG_8GB

J11_CMNPTS,CPU:1.7GHZ,EEEE:F0V4,DDR3:ELPIDA_8GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27K,DDR3:HYNIX_4GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27G,DDR3:SAMSUNG_4GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27H,DDR3:ELPIDA_4GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27C,DDR3:HYNIX_8GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27F,DDR3:SAMSUNG_8GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F279,DDR3:ELPIDA_8GB

J11_DEVEL:ENG

J11_COMMON

J11_CMNPTS,CPU:1.9GHZ,EEEE:DYKL,DDR3:HYNIX_4GB

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEEE #’s

PART NUMBER

825-7670

825-7670 CRITICAL

QTY

1

DESCRIPTION

LABEL,TEXT,MLB,K21/K78

REFERENCE DES

[EEEE_DYKL]

[EEEE_DYKH]

[EEEE_DYKK]

[EEEE_DYKF]

[EEEE_DYKJ]

[EEEE_DYKG]

[EEEE_F0V3]

[EEEE_F0V4]

[EEEE_F279]

[EEEE_F27C]

[EEEE_F27D]

[EEEE_F27F]

[EEEE_F27G]

[EEEE_F27H]

[EEEE_F27J]

[EEEE_F27K]

CRITICAL

CRITICAL825-7670

BOM OPTION

EEEE:DYKL

EEEE:DYKH

EEEE:DYKK

EEEE:DYKF

EEEE:DYKJ

EEEE:DYKG

EEEE:F0V3

EEEE:F0V4

EEEE:F279

EEEE:F27C

EEEE:F27D

EEEE:F27F

EEEE:F27G

EEEE:F27H

EEEE:F27J

EEEE:F27K

D

C

B

A

Sub-BOMs

PART NUMBER

085-3937

QTY

B

SIZE

A

D

SYNC_MASTER=K21_MLB

PAGE TITLE

K78 BOM Variants

DESCRIPTION

1

J11 MLB DEVELOPMENT BOM

CMN PTS,PCBA,MLB,J11

REFERENCE DES

DEVEL

CMNPTS

CRITICAL

CRITICAL607-9089

BOM OPTION

DEVEL_BOM

J11_CMNPTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=11/16/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

4 OF 109

SHEET

4 OF 72

124578

8 7 6 5 4 3

12

J11 BOM GROUPS

BOM GROUP

J11_PROGPARTS J11_DEVEL:ENG

J11_DEVEL:PVT

D

J11_DEBUG:ENG

J11_DEBUG:PVT

J11_DEBUG:PROD

DDR3:HYNIX_4GB

DDR3:HYNIX_8GB

DDR3:SAMSUNG_4GB

DDR3:SAMSUNG_8GB

DDR3:ELPIDA_4GB

DDR3:ELPIDA_8GB

Programmable Parts

PART NUMBER

335S0865

341S3526

338S1098

341S3434

C

335S0809

335S0803

341S3527

Alternate Parts

PART NUMBER

376S0977

371S0709

B

138S0671 138S0673

152S1085

152S1462 152S1295

138S0684 138S0660

138S0703 138S0648

152S1493

152S0586 152S1301

353S3238 353S1428

372S0186 372S0185

197S0431

376S0903 376S0796

371S0713

128S0333

128S0357 998-4435

998-4715 998-4435

998-4716

A

J11_COMMON

J11_MISC

ALTERNATE FOR PART NUMBER

376S0613376S0855

376S0859

376S0612376S0972

138S0691138S0676

371S0652

152S1307

152S1300

197S0432

376S0604376S1053

376S0613376S0855

371S0558

998-4435

QTY

1

IC,EEPROM,Cactus Ridge (V1.2) PIB, J11/J13

1

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA

1

BOM OPTION

BOM OPTIONS

ALTERNATE,COMMON,J11_MISC,J11_DEBUG:ENG,J11_PROGPARTS,USBHUB2513B,EDP:YES,PCH_C1

HUB_3NONREM,TBT,MPM5:YES,CPUMEM_SLG:NO,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTICS:NO

BOOTROM_PROG,SMC_PROG,TBTROM:PROG

ALTERNATE,BKLT:ENG,XDP_CONN,XDP_PCH,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

XDP_CONN

DEVEL_BOM,MOJO:YES,XDP,XDP_CPU:BPM,LPCPLUS

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS,VREFDQ:LDO,VREFCA:LDO,XDP_CPU:BPM,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

BKLT:PROD,MOJO:YES,XDP,LPCPLUS,VREFDQ:LDO,VREFCA:LDO,XDP_CPU:BPM,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DESCRIPTION

EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN

IC,SMC,PIB,J11

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

IC,EFI ROM,PIB,J11/J13

REF DES

COMMENTS:

Diodes alt to Toshiba

ALL

Diodes alt to Toshiba

ALL

Rohm alt to Toshiba

Murata alt to Samsung

ALL

NXP alt to NXP

ALL

Taiyo alt to Murata

ALL

Toko alt to Cyntec

ALL

Toko alt to NEC inductor

Murata alt to Taiyo Yuden

ALL

Murata alt to Taiyo Yuden

ALL

Coilcraft MA5274 alt to Murata

Dale/Vishay alt to Cyntec

ALL

Intersil alt to OPA2333

ALL

NXP alt to Diodes

200uW Epson alt to NDK

ALL

Diodes alt to Fairchild

ALL

Diodes alt to Toshiba

ALL

Fairchild alt to Siliconix

ALL

Diodes alt to ST Micro

ALL

Sanyo alt to Kemet

Sanyo High Voltage Polymer alt

ALL

Kemet Rectangular Design alt

ALL

Kemet Flute Design alt

ALL

REFERENCE DES

U3690

U4900

U6100

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL

BOM OPTION

TBTROM:BLANK

TBTROM:PROG

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_PROG

6 3

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DRAM CFG CHART

VENDOR

HYNIX

SAMSUNG

MICRON

ELPIDA

SIZE

4GB

8GB

CFG 1

0

1

0

1

CFG 2

0

1

CFG 0

Module Parts

PART NUMBER

337S4197

337S4299

337S4296

337S4198

337S4299

337S4296

337S4297

337S4165

337S4180

337S4235

337S4275

338S1108

333S0622

QTY

1

4

333S0622

333S0625

333S0623

333S0642

333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA

333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

333S0629

4

DESCRIPTION

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

IVB,QC9E,QS,L1,1.7,17W,2+2,1.05,3M,ULVBG

IVB,QC9B,QS,L1,2.0,17W,2+2,1.15,4M,ULVBG

IVB,QBTP,ES2,K0,1.5,17W,2+2,0.95,4M,ULVBGA

IVB,QC9E,QS,L1,1.7,17W,2+2,1.05,3M,ULVBG

IVB,QC9B,QS,L1,2.0,17W,2+2,1.15,4M,ULVBG

IVB,QC9C,QS,L1,1.9,17W,2+2,1.15,4M,ULVBG

IC,PCH,PPT-MB,SFF,ES1

IC,PCH,PPT-MB,SFF,ES2,B0

IC,PCH,PPT-MB,SFF,P-QS,C0

IC,PCH,PPT-MB,QS77,C1,QS

IC,TBT,CR-4C,LP,ES3,288 FCBGA,12X12MM

IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA

IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA333S0622

IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA

IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FBGA

IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FGBA

IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FBGA

IC,SDRAM,2GBIT,DDR3-1600,D35,78P FBGA

IC,SDRAM,2GBIT,DDR3-1600,D35,78P FGBA

IC,SDRAM,2GBIT,DDR3-1600,D35,78P FBGA

IC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FBGA

IC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FGBA

IC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FBGA

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

REFERENCE DES

U1000 CPU:1.5GHZ

U1000 CPU:1.7GHZ

CRITICAL

U1000

U1800

U3600

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

CRITICAL

BOM OPTION

CPU:2.0GHZU1000

CPU:1.5GHZTDP

CPU:1.7GHZTDP

CPU:2.0GHZTDP

CPU:1.9GHZ

PCH_ES1

PCH_ES2

PCH_C0

PCH_C1

PCH_C1TDP

TBT

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_8GB

DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:ELPIDA_8GB

D

C

B

607-6811

353S2929

946-3116

1

PD Module Parts

806-3706

806-3705

0

1

DIE REV

A

B

CFG 3

0

1

806-3214

806-3216

806-3083

806-3142

806-3215

1

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28

MLB,DYMAX UV EB 0.22 GRAM,K78

CAN,TOPSIDE,COVER,ALT,J11/J13

CAN,TOPSIDE,FENCE,ALT,J11/J13

CAN,TOPSIDE,J11/J13

CAN,MDP,J11/J13

SHLD,USB,MLB,J11/J13

CAN,TBT,J11/J13

CAN,COVER,TBT,J11/J13

J6955

U7000

GLUE

TBTTOPSIDE_2P_COVER

TBTTOPSIDE_2P_FENCE

TBTTOPSIDE_1P

MDPCAN

USBCAN

TBTCOVER

SYNC_MASTER=J11_MLB_NON_POR

PAGE TITLE

CRITICAL

CRITICALTBTFENCE

CRITICAL

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/09/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

5 OF 109

SHEET

5 OF 72

SIZE

A

D

124578

8 7 6 5 4 3

Misc Voltages & Control Signals

Functional Test Points

J4001: AirPort / BT Connector

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

D

C

B

A

TRUE TRUE

TRUE

TRUE TRUE

TRUE

J4501: SATA SSD Connector

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

PP3V3_WLAN_F WIFI_EVENT_L PCIE_AP_R2D_N PCIE_AP_R2D_P PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P USB_BT_CONN_P USB_BT_CONN_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_WAKE_L AP_RESET_CONN_L AP_CLKREQ_Q_L PP3V3_S3RS4_BT_F (Need to add 8 GND TPs)

PP3V3_S0_SSD_FLT SATA_SSD_D2R_P SATA_SSD_D2R_N SATA_SSD_R2D_N SATA_SSD_R2D_P SMC_OOB1_RX_L SMC_OOB1_TX_L PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1> PCIE_SSD_R2D_N<1> PCIE_SSD_R2D_P<1> PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P SSD_CLKREQ_L SSD_RESET_L SATA_PCIE_SEL SSD_P3V3S0_EN

(Need to add 6 GND TPs)

J4700: LIO Connector

=PP3V42_G3H_ONEWIRE =PP3V3_S0_AUDIO =PP3V3R1V5_S0_AUDIO SYS_ONEWIRE SMC_BC_ACOK =USB_PWR_EN =I2C_LIO_SDA =I2C_LIO_SCL =I2C_MIKEY_SCL =I2C_MIKEY_SDA AUD_IPHS_SWITCH_EN AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L AUD_GPIO_3 SPKRAMP_INR_N SPKRAMP_INR_P USB_EXTB_N USB_EXTB_P USB_CAMERA_N USB_CAMERA_P HDA_SDOUT HDA_BIT_CLK HDA_SDIN0 USB_EXTB_OC_L HDA_RST_L HDA_SYNC USB3_EXTB_RX_RC_N USB3_EXTB_RX_RC_P USB3_EXTB_TX_C_P USB3_EXTB_TX_C_N

(Need to add 5 GND TPs)

J5100: LPC+SPI Connector

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD<3..0> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO TP_SMC_TRST_L TP_SMC_MD1 SMC_TX_L LPC_CLK33M_LPCPLUS SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L LPCPLUS_GPIO

(Need to add 6 GND TPs)

(Need 6 TPs)

(Need 5 TPs)

36 41

36 40 41

36 68

16 36 68

36 67

16 36 68

17 36

36

37

37 67

37 40

37 40 41

8

37 65

8

37 65

16 37 65

16 37

25 37

37

7

39

7

39

7

39

39 40

39 40 41

38 39 61

39 43

25 39

18 39

39 50

39 50 71

24 39 67

18 39 67

16 39 68

23 39

16 39 68

39 67

7

42

7

42

16 40 42 68

42

16 40 42 68

17 40 42

40 41 42

25 42 68

40 41 42

42

40 41 42

25 42 68

19 42 49

42

16 40 42

17 25 40 42

40 41 42

40 41 42 52

41 42

40 41 42

19 42

J5600: Fan Connector

FUNC_TEST

TRUE TRUE

TRUE

J5700: IPD Flex Connector

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

J6900: DC-In Connector

FUNC_TEST

TRUE

J6903: Speaker Connector

FUNC_TEST

TRUE

J6950: Battery Connector

FUNC_TEST

TRUE TRUE

TRUE

J9000: Internal DP Connector

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

FUNC_TEST

TRUE TRUE

FUNC_TEST

TRUE

=PP5V_S0_FAN FAN_RT_TACH FAN_RT_PWM

(Need to add 1 GND TP)

SMC_PME_S4_WAKE_L

PP5V_TPAD_FILT =PP3V42_G3H_TPAD PP3V3_TPAD_CONN USB_TPAD_P USB_TPAD_N =I2C_TPAD_SDA =I2C_TPAD_SCL SMC_ONOFF_L SMC_LID SMC_TPAD_RST_L

(Need to add 5 GND TPs)

=PP18V5_DCIN_CONN =PP5V_S3_LIO_CONN

(Need to add 5 GND TPs)

SPKRAMP_ROUT_P SPKRAMP_ROUT_N

(Need to add 3 GND TPs)

PPVBAT_G3H_CONN =SMBUS_BATT_SCL =SMBUS_BATT_SDA SYS_DETECT_L

(Need to add 4 GND TPs near J6950 and 1 for shield)

PPVOUT_SW_LCDBKLT PP3V3_SW_LCD I2C_TCON_SDA_R LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1 DP_INT_HPD_CONN DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P DP_INT_ML_F_P<0> DP_INT_ML_F_N<0> I2C_TCON_SCL_R

(Need to add 5 GND TPs)

J5715: KB BKLT Connector

KBDLED_FB KBDLED_ANODE

(Need to add 2 GND TPs)

J6955: HALL EFFECT Connector

SMC_LID_R =PP3V42_G3H_HALL

7

47

40 41 48

48

7

48

48 67

43 48

40 41 48

40 41 48 51

41 48

7

51

7

51

50 51 71

51 52

43 51

51

62 64

62

62 64

62

62 65

62

48

51

7

51

(Need 4 TPs) (Need 3 TPs)

(Need 4 TPs)

(Need 2 TPs) (Need 2 TPs)

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

POWER SIGNALS

I641

I642 I643

I644

NO_TEST

TP_CRT_IG_BLUE NC_CRT_IG_BLUE

17

TP_CRT_IG_GREEN NC_CRT_IG_GREEN

17

TP_CRT_IG_RED

17

TP_CRT_IG_DDC_CLK

17

TP_CRT_IG_DDC_DATA NC_CRT_IG_DDC_DATA

17

TP_CRT_IG_HSYNC NC_CRT_IG_HSYNC

17

TP_CRT_IG_VSYNC

17

TP_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLK TP_LVDS_IG_CTRL_DATA NC_LVDS_IG_CTRL_DATA

TP_PCH_LVDS_VBG NC_PCH_LVDS_VBG

TP_HDA_SDIN1

16

TP_HDA_SDIN2

16

TP_HDA_SDIN3

16

TP_PCI_PME_L

18

TP_PCI_CLK33M_OUT3

18

TP_CLINK_CLK

16

TP_CLINK_DATA

16

TP_CLINK_RESET_L NC_CLINK_RESET_L

16

TP_PCIE_CLK100M_PEBN

16

TP_PCIE_CLK100M_PEBP

16

TP_SDVO_TVCLKINN

17

TP_SDVO_TVCLKINP

TP_SDVO_STALLN

17

TP_SDVO_STALLP

17

TP_SDVO_INTN

17

TP_SDVO_INTP

17

23

16

PPBUS_G3H PPVIN_SW_TBTBST PPBUS_S5_HS_COMPUTING_ISNS PPDCIN_G3H PP3V42_G3H PPVRTC_G3H PP5V_S5 PP5V_SUS PP3V3_S5 PP3V3_SUS PP3V3_S3 PP1V8_S0 PP3V3_S0 PP1V5_S3 PP1V5_S3RS0 PP1V5_S0 PP1V05_S0 PPVTTDDR_S3 PP0V75_S0_DDRVTT PPVCCSA_S0_CPU PP1V05_SUS PP15V_TBT PP3V3_TBTLC PP1V05_TBTLC PP1V05_S0_PCH_VCCADPLL PPVCORE_S0_CPU PPVCORE_S0_AXG PP1V5_S3_CPU_VCCDQ PP1V05_S0_CPU_VCCPQE PP1V8_S0_CPU_VCCPLL_R PP1V05_TBTCIO PPBUS_S5_HS_OTHER_ISNS PPDCIN_G3H_ISOL PP5V_S3 PP5V_S0 PP3V3_S4

NO_TEST Nets

VCCSAS0_SREF

TRUE

VCCSAS0_SET1_R

TRUE

VCCSAS0_SET0

TRUE

VCCSAS0_SET1

TRUE

TP_XDP_PCH_OBSFN_A<0..1> TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK2

TP_XDPPCH_HOOK3 TP_XDP_PCH_OBSFN_D<0..1>

TP_XDP_PCH_HOOK4

TP_XDP_PCH_HOOK5

TP_PCH_GPIO64_CLKOUTFLEX0 TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2 TP_PCH_GPIO67_CLKOUTFLEX3

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK

NC_CRT_IG_VSYNC

NC_HDA_SDIN1 NC_HDA_SDIN2

NC_HDA_SDIN3

NC_PCI_PME_L

NC_PCI_CLK33M_OUT3

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

7

51

35

7

71

7

71

7

66

7

66

7

(Need to add 27 GND TPs)

7

35

7

NC_CLINK_CLK

NC_CLINK_DATA

NC_PCIE_CLK100M_PEBN

NC_PCIE_CLK100M_PEBP

NC_SDVO_TVCLKINN

NC_SDVO_TVCLKINP

NC_SDVO_STALLN

NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

NC_TP_XDP_PCH_OBSFN_A<0..1> NC_TP_XDP_PCH_OBSFN_B<0..1>

NC_TP_XDPPCH_HOOK2

NC_TP_XDPPCH_HOOK3 NC_TP_XDP_PCH_OBSFN_D<0..1>

NC_TP_XDP_PCH_HOOK4

NC_TP_XDP_PCH_HOOK5

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3

NC_EDP_TXP<0..3>

MAKE_BASE=TRUE

NC_EDP_TXN<0..3>

MAKE_BASE=TRUE

NC_EDP_AUXP

MAKE_BASE=TRUE

NC_EDP_AUXN

MAKE_BASE=TRUE

NC_CPU_THERMDA

MAKE_BASE=TRUE

NC_CPU_THERMDC

MAKE_BASE=TRUE

NC_CPU_RSVD<30..45>

MAKE_BASE=TRUE

NC_CPU_RSVD<8..27>

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..2>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..2>

MAKE_BASE=TRUE

NC_PEG_D2RP<15..2>

MAKE_BASE=TRUE

NC_PEG_D2RN<15..2>

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N

16

TP_PCIE_CLK100M_PE4P

16

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE7P

TP_PSOC_P1_3 TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_B_R2D_CN TP_SATA_B_R2D_CP

TP_SATA_D_D2RN

16

TP_SATA_D_D2RP

16

TP_SATA_D_R2D_CN

16

TP_SATA_D_R2D_CP

16

TP_SATA_E_D2RN

16

TP_SATA_E_D2RP

16

TP_SATA_E_R2D_CN

16

TP_SATA_E_R2D_CP

16

TP_SATA_F_D2RN

16

TP_SATA_F_D2RP

16

TP_SATA_F_R2D_CN

16

TP_SATA_F_R2D_CP

16

TP_PCH_TP18

TP_PCH_TP17

TP_PCH_TP16 TP_PCH_TP15

TP_PCH_TP14

TP_PCH_TP13 TP_PCH_TP12

TP_PCH_TP10 TP_PCH_TP9

TP_PCH_TP8 TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5 TP_PCH_TP4

TP_PCH_TP3

TP_PCH_TP2 TP_PCH_TP1

TP_LVDS_IG_B_CLKN

8

TP_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKP

8

TP_LVDS_IG_BKL_PWM NC_LVDS_IG_BKL_PWM

SYNC_MASTER=(K99_MLB)

PAGE TITLE

TRUE

SMC_BS_ALRT_L

TP_EDP_TX_P<0..3>

TP_EDP_TX_N<0..3>

TP_EDP_AUX_P

TP_EDP_AUX_N

TP_CPU_THERMDA

TP_CPU_THERMDC

TP_CPU_RSVD<30..45>

TP_CPU_RSVD<8..27>

=PEG_R2D_C_P<15..2>

=PEG_R2D_C_N<15..2>

=PEG_D2R_P<15..2>

=PEG_D2R_N<15..2>

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

Functional Test / No Test

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

6 3

12

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_PE5N

NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE7P

NC_PSOC_P1_3 NC_SATA_B_D2RN

NC_SATA_B_D2RP

NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP

NC_SATA_D_D2RN

NC_SATA_D_D2RP NC_SATA_D_R2D_CN

NC_SATA_D_R2D_CP NC_SATA_E_D2RN

NC_SATA_E_D2RP

NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP

NC_SATA_F_D2RN

NC_SATA_F_D2RP NC_SATA_F_R2D_CN

NC_SATA_F_R2D_CP

NC_PCH_TP18

NC_PCH_TP17

NC_PCH_TP16 NC_PCH_TP15

NC_PCH_TP14

NC_PCH_TP13 NC_PCH_TP12

NC_PCH_TP10 NC_PCH_TP9

NC_PCH_TP8 NC_PCH_TP7

NC_PCH_TP6

NC_PCH_TP5 NC_PCH_TP4

NC_PCH_TP3

NC_PCH_TP2 NC_PCH_TP1

NC_LVDS_IG_B_CLKN

NC_SMC_BS_ALRT_L

SYNC_DATE=(02/16/2010)

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

SHEET

124578

9

2.7.0

7 OF 109

6 OF 72

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PPBUS_G3H

52

PPVIN_SW_TBTBST

6

35

VOLTAGE=12.8V

=PPVIN_S5_HS_COMPUTING_ISNS

8

D

=PPVIN_S5_HS_OTHER_ISNS

45

=PP18V5_DCIN_ISOL

51

=PP18V5_DCIN_CONN

6

51

C

"G3Hot" (Always-Present) Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE

=PPBUS_S0_LCDBKLT =PPBUS_S0_VSENSE =PPVIN_SW_TBTBST

=PPVIN_S5_HS_COMPUTING_ISNS_R =PPVIN_S5_HS_OTHER_ISNS_R

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE

=PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_VCCSAS0 =PPVIN_S0_CPUAXG

PPBUS_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.4V MAKE_BASE=TRUE

=PPVIN_S5_P5VP3V3

PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

=PPDCIN_S5_CHGR_ISOL =PPDCIN_S5_VSENSE

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

6

52

44

6

52

6

64

44

8

45

6

56 57

55

58

53

57

6

54

51

=PP3V3_S5_REG

54

=PP3V3_S4_FET

60

=PP3V3_SUS_FET

60

=PP3V3_S4_TBTAPWR

=PP3V42_G3H_REG

51

=PPVRTC_G3_OUT

25

B

A

=PP5V_S5_LDO

54

=PP5V_SUS_FET

60

=PP5V_S3_REG

54

=PP5V_S0_FET

60

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

=PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_HALL =PP3V42_G3H_CHGR =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3H_SYSCLK =PP3V42_G3H_ONEWIRE

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE

=PPVRTC_G3_PCH

5V Rails

PP5V_S5

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S5_P1V5DDRFET =PP5V_S5_P5VSUSFET =PP5V_S5_TPAD

PP5V_SUS

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_SUS_PCH

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG

=PP5V_S3_MEMRESET

=PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN

PP5V_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSA =PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_KBDLED

6

40 41

6

52

61

43

38

6

41

25

6

16 17 20

6

60

48

6

22

6

50

55

26

60

38

6

64

56

58

6

47

6

42

53

22 25

61

48

42

51

48

39

51

=PP3V3_S3_FET

60

=PP3V3_S0_FET

60

3.3V Rails

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

=PP3V3_S3_USB_HUB

=PP3V3_S0_SSD =PP3V3_S0_HDDISNS =PP3V3_S0_VMON

PP3V3_S5

=PP3V3_S5_XDP =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET =PP3V3_S5_CPU_VCCDDR

=PP3V3_S5_LCD =PP3V3_S5_PCH =PP3V3_S5_PCHPWRGD

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S5_PCH_GPIO =PP3V3_S5_P3V3SUSFET =PP3V3_S4_P3V3S4FET =PP3V3_S4_TBTAPWRSW

PP3V3_S4

=PP3V3_S4_SMC =PP3V3_S4_TPAD

=PP3V3_S4_BT

PP3V3_SUS

=PP3V3_SUS_ROM =PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_PCH_GPIO =PP3V3_SUS_PCH =PP3V3_SUS_PWRCTL =PP3V3_SUS_P1V05SUSLDO =PP3V3_SUS_SMC =PP3V3_SUS_PCH_VCC_SPI =PP3V3_SUS_PCH_VCCSUS_USB

PP3V3_SW_TBTAPWR

VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S4_TBT

PP3V3_S3

=PP3V3_S3_BT =PP3V3_S3_MEMRESET =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_WLANISNS =PP3V3_S3_PCH_GPIO =PP3V3_S3_USBMUX =PP3V3_S3_1V5S3ISNS =PP3V3_S3_DBGLEDS

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO =PP3V3_S0_BKL_VDDIO =PP3V3_S0_HS_COMPUTING_ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_DP_DDC =PP3V3_S0_FAN =PP3V3_S0_P3V3TBTFET

=PP3V3_S0_P1V8S0 =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_SATAMUX =PP3V3_S0_PCH_VCC3_3 =PP3V3_S0_HS_OTHER_ISNS =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC

=PP3V3_S0_P1V5S0 =PP3V3_S0_TBTPWRCTL =PP3V3_S0_3V3S0ISNS =PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_BKLTISNS =PP3V3_S0_SYSCLKGEN =PP3V3_S0_SAISNS =PP3V3_S0_PCH_STRAPS

VOLTAGE=3.3V MAKE_BASE=TRUE

63

33 34 35

6

71

23

60

26 35

62

17

25

41

20 22

25

61

19

60

63

6

41

48

36

6

49

20 22

16 17 18 19

22

61

59

41

20 22

6

36

26

43

8

24

31

36

45

18 25

24

45

51

6

71

22

44

6

39

64

45

46

12

8

47

35

59

16 22

16 17 18 19 25 35

37

20 22

45

22

61

25

43

41

37

45

61

59

35

44

59

44

23

45

25

44

19

=PP1V8_S0_REG

59

2A max supply

=PPDDR_S3_REG

55

=PP1V5_S3RS0_FET

60

=PP1V5_S0_REG

59

=PPVTT_S3_DDR_BUF

31 55

=PPVTT_S0_DDR_LDO

55

=PPVCCSA_S0_REG

53

=PP1V05_SUS_LDO

59

=PPCPUVCCIO_S0_REG

58

? mA

1.8V/1.5V/1.2V/1.05V Rails

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

=PP1V8_S0_CPU_VCCPLL =PP1V8_S0_PCH_VCC_DFTERM =PP1V8_S0_P1V05S0LDO =PP1V8R1V5_S0_PCH_VCCVRM =PPVDDIO_S0_SBCLK =PP1V8_S0_P1V5S0

PP1V5_S3

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_MEMRESET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO =PPDDR_S3_MEMVREF

PP1V5_S3RS0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_CPU_VCCDDR =PP1V5_S3RS0_VMON

PP1V5_S0

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP3V3R1V5_S0_AUDIO =PP3V3R1V5_S0_PCH_VCCSUSHDA

PPVTTDDR_S3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.9V MAKE_BASE=TRUE

=PPVCCSA_S0_CPU =PPVCCSA_S0_VSENSE

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_VMON

=PPVCCIO_S0_CPUIMVP =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCC_DMI

=PPVCCIO_S0_XDP =PPVCCIO_S0_SMC =PP1V05_S0_P1V05TBTFET

6

14

19 20 22

59

20

25

59

6

66

26

27 28 32

29 30 32

60

31

6

66

10 12 15 26

61

6

39

20 22 25

6

32

26

6

12 15

44

6

23

6

9

10 12 14

16 22

20 22

17

16 22

20 22

61

56

16 20 22

20 22

23

41

35

=PP15V_TBT_REG

35

=PP3V3_TBTLC_FET

35

=PP1V05_TBTLC_FET

35 55

=PP1V05_TBTCIO_FET

=PP1V05_S0_LDO

59

=PPVCORE_S0_CPU_REG

57

=PPVCORE_S0_AXG_REG

57

=PP1V5_S3_CPU_VCCDQ

12 15

=PP1V05_S0_CPU_VCCPQE

12 14

=PP1V8_S0_CPU_VCCPLL_R

12 14

TBT Rails (off when no cable)

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE

=PPHV_SW_TBTAPWRSW

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PPVDDIO_TBT_CLK =PP3V3_TBTLC_RTR =PP3V3_TBT_PCH_GPIO

PP1V05_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_TBTLC_RTR

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_TBTCIO_RTR

1V05 S0 LDO

PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCADPLL

Chipset "VCore" Rails

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE

=PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PPVCORE_S0_CPU_VCCAXG =PPGFXVCORE_S0_VSENSE

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

SYNC_MASTER=K91_MLB

PAGE TITLE

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

12

6

63

6

25

33 34 35

19

6

34

6

34

SYNC_DATE=05/15/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

8 OF 109

SHEET

7 OF 72

124578

D

35

6

22

C

6

9

12 14

44

6

9

12 15

44

6

B

6

A

SIZE

D

8 7 6 5 4 3

CPU Heat Sink Mounting Bosses

Z0913

D

STDOFF-4.5OD1.8H-SM

Z0911

1

4x 860-1327

Fan Boss

Z0905

1

860-1327

EMI I/O Pogo Pins

DisplayPort Pogo

CRITICAL

ZS0905

POGO-2.0OD-3.6H-K86-K87

SM

1

870-1938

C

SL0901

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691 998-2691

SL0903

TH-NSP

1

B

SL-1.1X0.45-1.4x0.75

998-3975

SL0905

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691

SL0907

TH-NSP

1

SL-1.1X0.45-1.4x0.75

998-3975

SL0909

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691

A

Digital Ground

GND

VOLTAGE=0V MIN_NECK_WIDTH=0.075MM MIN_LINE_WIDTH=0.6MM

Z0910

STDOFF-4.5OD1.8H-SM

1

Z0912

STDOFF-4.5OD1.8H-SM

1

X21 Boss

Z0914

1

860-1327

Can Slots

SL-1.1X0.4-1.4x0.7

SL-1.1X0.45-1.4x0.75

SL-1.1X0.4-1.4x0.7

998-2691

SL-1.1X0.45-1.4x0.75

SL-1.1X0.4-1.4x0.7

SSD Boss

Z0915

STDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.8H-SM

1

860-1327

USB/SD Card Pogo

CRITICAL

ZS0907

POGO-2.0OD-2.95H-K86-K87

SL0902

TH-NSP

1

SL0904

TH-NSP

1

998-3975

SL0906

TH-NSP

1

SL0908

TH-NSP

1

998-3975

SL0910

TH-NSP

1

998-2691

SM

1

870-1940

2x MDP connector

2x USB connector

2x TBT pin diodes

2x TBT chip

2x CPU Vcore

DP_TBTSNK0_AUXCH_C_P

33 68

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_N

33 68

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_N

16

PCIE_CLK100M_ENET_P

16

PCIE_EXCARD_D2R_N

16

PCIE_EXCARD_D2R_P

16

PCIE_EXCARD_R2D_C_N

16

PCIE_EXCARD_R2D_C_P

16

PCIE_CLK100M_EXCARD_N

16

PCIE_CLK100M_EXCARD_P

16

PEG_CLK100M_P

16 68

PEG_CLK100M_N

16 68

TP_PCH_CLKOUT_DPN

16

TP_PCH_CLKOUT_DPP

16

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

11 66

MEM_B_CLK_P<1>

11 66

MEM_B_CLK_N<1>

11 66

USB_EXTC_P

18

USB_EXTC_N

18

USB3_EXTC_RX_P

18

USB3_EXTC_RX_N

18

USB3_EXTC_TX_P

18

USB3_EXTC_TX_N

18

USB3_EXTD_RX_P

18

USB3_EXTD_RX_N

18

USB3_EXTD_TX_P

18

USB3_EXTD_TX_N

18

USB_EXTD_EHCI_P

18

USB_EXTD_EHCI_N

18

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_N<0>

33 69

TBT_B_R2D_C_P<1>

33 69

TBT_B_R2D_C_N<1>

33 69

TBT_B_D2R_P<0>

33 69

TBT_B_D2R_N<0>

33 69

TBT_B_D2R_P<1>

33 69

TBT_B_D2R_N<1>

33 69

TBT_B_LSTX

33

DP_TBTPB_ML_C_P<1>

33 69

DP_TBTPB_ML_C_N<1>

33 69

DP_TBTPB_ML_C_P<3>

33 69

DP_TBTPB_ML_C_N<3>

33 69

PCIE_CLK100M_FW_N

16

PCIE_CLK100M_FW_P

16

=PEG_D2R_P<1..0>

9

=PEG_D2R_N<1..0>

9

=PEG_R2D_C_P<1..0>

9

=PEG_R2D_C_N<1..0>

9

PCIE_ENET_D2R_N

16

PCIE_ENET_D2R_P

16

PCIE_ENET_R2D_C_N

16

PCIE_ENET_R2D_C_P

16

PCIE_FW_D2R_N

16

PCIE_FW_D2R_P

16

PCIE_FW_R2D_C_N

16

PCIE_FW_R2D_C_P

16

CPU signals

MEMVTT_EN

26 26 55

MAKE_BASE=TRUE

DPA_IG_AUX_CH_P

DPA_IG_AUX_CH_N

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

DPLL_REF_CLK_N

DPLL_REF_CLK_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CP<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CN<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CP<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_CN<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RP<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RN<0>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RP<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2RN<1>

TRUE

MAKE_BASE=TRUE

NC_TBT_B_LSTX

TRUE

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CP<1>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CN<1>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CP<3>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_CN<3>

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWN

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWP

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<1..0>

MAKE_BASE=TRUE

PCIE_SSD_D2R_N<1..0>

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_N<1..0>

MAKE_BASE=TRUE

NC_PCIE_ENET_D2RN

TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_D2RN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CN

NC_PCIE_FW_R2D_CP

TP_MEM_A_CLKP<1> TP_MEM_A_CLKN<1>

TP_MEM_B_CLKP<1> TP_MEM_B_CLKN<1>

NC_USB_EXTCP NC_USB_EXTCN NC_USB3_EXTC_RXP NC_USB3_EXTC_RXN NC_USB3_EXTC_TXP NC_USB3_EXTC_TXN NC_USB3_EXTD_RXP NC_USB3_EXTD_RXN NC_USB3_EXTD_TXP NC_USB3_EXTD_TXN NC_USB_EXTD_EHCIP NC_USB_EXTD_EHCIN

=DDRVTT_EN

17

NC_PCIE_CLK100M_ENETN NC_PCIE_CLK100M_ENETP NC_PCIE_EXCARD_D2RN NC_PCIE_EXCARD_D2RP NC_PCIE_EXCARD_R2D_CN NC_PCIE_EXCARD_R2D_CP NC_PCIE_CLK100M_EXCARDN NC_PCIE_CLK100M_EXCARDP

NC_PEG_CLK100MP NC_PEG_CLK100MN

DPLL_REF_CLKN

DPLL_REF_CLKP

6

37 65

6

37 65

10 65

19 23

16 23

TP_DP_IG_D_CTRL_CLK

17

TP_DP_IG_D_CTRL_DATA

17

DP_TBTSNK0_DDC_CLK

63

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_DATA

63

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

33

MAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWR

64

MAKE_BASE=TRUE

ISNS_LCDBKLT_P

45 71

OUT

ISNS_LCDBKLT_N

45 71

OUT

=PPVIN_S5_HS_COMPUTING_ISNS

7 7

OUT

ISNS_HS_COMPUTING_N

45 71

OUT

ISNS_HS_COMPUTING_P

45 71

OUT

UNUSED SDCARD USB Aliases

=PP3V3_S3_USB_HUB

7

24

USB_SDCARD_N

24 67

OUT

USB_SDCARD_P

24 67

OUT

TBT_B_CIO_SEL

33

DP_TBTPB_HPD

33

TBT_B_CONFIG2_RC

33

TBT_B_CONFIG1_BUF

33

TBT_B_LSRX

33

1

R0916

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH XDP_DC3_PCH_GPIO19_SATARDRVR_EN

10K

5%

1/20W

MF

201

2

MLB_RAMCFG3

19

MLB_RAMCFG2

19

MLB_RAMCFG1

19

MLB_RAMCFG0

19

R0917

MAKE_BASE=TRUE

R0901

10K

1/20W

201

1

R0918

10K

5%

1/20W

MF

201 201

2

1

5%

MF

2

10K

1/20W

RAMCFG3:L

7 8

CRITICAL

R0910

0.01

0.5% 1W MF 0612-1

1 2 3 4

CRITICAL

R0954

1

R0902

10K

5% 1/20W MF 201

2

1

R0919

5% MF

2

ENET_LOW_PWR_PCH SATARDRVR_EN

R0950

10K

5%

1/20W

MF

201

=PP3V3_S0_DP_DDC

1

R0920

2.2K

1/20W

R0921

2.2K

5% MF

201

5%

1/20W

MF

201

2

DPB_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK DP_IG_D_CTRL_DATA

=PP3V3_S0_DP_DDC

1

R0924

DPA_IG_DDC_CLK

470K

1/20W

R0925

5% MF

201

2

DPA_IG_DDC_DATA

DPA_IG_HPD

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=12.6V MAKE_BASE=TRUE

=PPBUS_SW_BKL

0.002

1%

1W

MF

0612

12

=PPVIN_S5_HS_COMPUTING_ISNS_R

34

1

10K

5%

1/20W

MF

201

2

1

2

1

R0914

10K

5%

1/20W

MF

201

2

RAMCFG2:L RAMCFG1:L

1

R0951

10K

5% 1/20W MF 201

2

NOSTUFF

1

R0922

2.2K

1/20W

2

DPB_IG_DDC_DATA

1

470K

5%

1/20W

MF

201

2

6 3

NOSTUFF

1

R0923

2.2K

5%

1/20W

MF

201

17

201

2

64

1

R0952

10K

5% 1/20W 1/20W MF 201

2

12

TBT DP Ports

DPB_IG_HPD

1

5% MF

2

17

IN

17

TP_DP_IG_C_MLP<3..0>

17

TP_DP_IG_C_MLN<3..0>

17

DPB_IG_AUX_CH_P

17

DPB_IG_AUX_CH_N

17

TP_DP_IG_D_HPD

17

DP_TBTPB_AUXCH_C_P

33 69

DP_TBTPB_AUXCH_C_N

33 69

TP_DP_IG_B_MLP<3..0> TP_DP_IG_B_MLN<3..0>

17

NC_PCIE_5_R2D_CP

16

NC_PCIE_6_R2D_CP

16

NC_PCIE_7_R2D_CP

16

NC_PCIE_8_R2D_CP

16

NC_PCIE_5_R2D_CN

16

NC_PCIE_6_R2D_CN

16

NC_PCIE_7_R2D_CN

16

NC_PCIE_8_R2D_CN

16

NC_PCIE_5_D2RP

16

NC_PCIE_6_D2RP

16

NC_PCIE_7_D2RP

16

NC_PCIE_8_D2RP

16

NC_PCIE_5_D2RN

16

NC_PCIE_6_D2RN

16

NC_PCIE_7_D2RN NC_PCIE_8_D2RN

16

TP_LVDS_IG_B_CLKP

6

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

6

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

LCD_IG_PWR_EN

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

LVDS Aliases

NO_TEST=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<0..3>

LVDS_IG_B_DATA_N<0..3>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_BKL_PWM

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

DP_IG_D_HPD

NC_DP_TBTPB_AUXCH_CP NC_DP_TBTPB_AUXCH_CN

DP_TBTSNK0_ML_C_P<3..0> DP_TBTSNK0_ML_C_N<3..0>

PCIE_TBT_R2D_C_P<0> PCIE_TBT_R2D_C_P<1> PCIE_TBT_R2D_C_P<2> PCIE_TBT_R2D_C_P<3> PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_N<3>

PCIE_TBT_D2R_P<0> PCIE_TBT_D2R_P<1> PCIE_TBT_D2R_P<2> PCIE_TBT_D2R_P<3> PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_N<3>

33

33 68

1

R0909

100K

5%

1/20W

D

MF

33 68 17

201

33 68

33 68 16

33 68

2

33 68

C

17 64

17 62

17 64

SATA Aliases

16

IN

16

IN

16

OUT

16

OUT

40

IN

40

OUT

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SMC_SYS_LED

IR_RX_OUT_RC

Unused SATA ODD Signals

SMC Aliases

Unused SMC Signals

NC_SATA_ODD_R2DCP

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_SYS_LED

NO_TEST=TRUE

NC_IR_RX_OUT_RC

NO_TEST=TRUE

B

Unused PGOOD signal

19

16

RAMCFG0:L

1

R0953

10K

5% MF

201

2

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

SYNC_MASTER=K91_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

P1V5S3RS0_RAMP_DONE

DDRREG_PGOOD

Signal Aliases

Apple Inc.

R

60

IN

55

IN

SYNC_DATE=05/15/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

9 OF 109

SHEET

8 OF 72

SIZE

A

D

124578

8 7 6 5 4 3

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

12

DMI_S2N_N<0>

17 65

IN

DMI_S2N_N<1>

17 65

IN

DMI_S2N_N<2>

17 65

IN

DMI_S2N_N<3>

17 65

IN

DMI_S2N_P<0>

17 65

D

C

=PP1V05_S0_CPU_VCCIO

7 9

10 12 14

R1030

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=U1000.AF3:12.7MM

B

Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating even if internal Graphics is disabled since they are shared with other interfaces.

NOTE: The EDP_HPD processor input is a low voltage active low signal. Therefore, an inverting level shifter is required on the motherboard to convert the active high signal from Embedded DisplayPort sink device to low voltage signals for the processor

(refer to latest Processor EDS for DC specifications).

If HPD is disabled while eDP interface is still enabled, connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard. This signal can be left as no-connect if entire eDP interface is disabled.

IN

DMI_S2N_P<1>

17 65

IN

DMI_S2N_P<2>

17 65

IN

DMI_S2N_P<3>

17 65

IN

DMI_N2S_N<0>

17 65

OUT

DMI_N2S_N<1>

17 65

OUT

DMI_N2S_N<2>

17 65

OUT

DMI_N2S_N<3>

17 65

OUT

DMI_N2S_P<0>

17 65

OUT

DMI_N2S_P<1>

17 65

OUT

DMI_N2S_P<2>

17 65

OUT

DMI_N2S_P<3>

17 65

OUT

FDI_DATA_N<0>

17 65

OUT

FDI_DATA_N<1>

17 65

OUT

FDI_DATA_N<2>

17 65

OUT

FDI_DATA_N<3>

17 65

OUT

FDI_DATA_N<4>

17 65

OUT

FDI_DATA_N<5>

17 65

OUT

FDI_DATA_N<6>

17 65

OUT

FDI_DATA_N<7>

17 65

OUT

FDI_DATA_P<0>

17 65

OUT

FDI_DATA_P<1>

17 65

OUT

FDI_DATA_P<2>

17 65

OUT

FDI_DATA_P<3>

17 65

OUT

FDI_DATA_P<4>

17 65

OUT

FDI_DATA_P<5>

17 65

OUT

FDI_DATA_P<6>

17 65

OUT

FDI_DATA_P<7>

17 65

OUT

FDI_FSYNC<0>

17 65

IN

FDI_FSYNC<1>

17 65

IN

FDI_INT

17 65

IN

FDI_LSYNC<0>

17 65

IN

FDI_LSYNC<1>

17 65

IN

EDP_COMP

65

EDP_HPD_L

9

DP_INT_AUX_CH_N

62 65

DP_INT_AUX_CH_P

62 65

DP_INT_ML_N<0>

62 65

TP_EDP_TX_N<1>

6

TP_EDP_TX_N<2>

6

TP_EDP_TX_N<3>

6

DP_INT_ML_P<0>

62 65

TP_EDP_TX_P<1>

6

TP_EDP_TX_P<2>

6

TP_EDP_TX_P<3>

6

P10

P11

W11

AA6

AC9

W10

AA7

AA3 AC8

AA11 AC12

U11

AA10

AG8

AD2 AF3

AG11

AG4 AF4

AC3 AC4

AE11

AE7

AC1 AA4

AE10

AE6

M2 P6 P1

N3 P7 P3

K1 M8 N4 R2

K3 M7 P4 T3

U7

W1

W6 V4 Y2

U6

W3

W7 T4

DMI_RX_0* DMI_RX_1* DMI_RX_2* DMI_RX_3*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3*

DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3

FDI0_TX_0* FDI0_TX_1* FDI0_TX_2* FDI0_TX_3*

FDI1_TX_0* FDI1_TX_1* FDI1_TX_2* FDI1_TX_3*

FDI0_TX_0 FDI0_TX_1 FDI0_TX_2 FDI0_TX_3

FDI1_TX_0 FDI1_TX_1 FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

EDP_ICOMPO EDP_COMPIO

EDP_HPD

EDP_AUX* EDP_AUX

EDP_TX_0* EDP_TX_1* EDP_TX_2* EDP_TX_3*

EDP_TX_0 EDP_TX_1 EDP_TX_2 EDP_TX_3

OMIT_TABLE

CRITICAL

U1000

IVY-BRIDGE

2C-35W

BGA

(1 OF 9)

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8*

PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15*

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9*

PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

CPU_PEG_COMP

65

PLACE_NEAR=U1000.G3:12.7MM

=PEG_D2R_N<0> =PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3> =PEG_D2R_N<4> =PEG_D2R_N<5> =PEG_D2R_N<6> =PEG_D2R_N<7> =PEG_D2R_N<8> =PEG_D2R_N<9> =PEG_D2R_N<10> =PEG_D2R_N<11> =PEG_D2R_N<12> =PEG_D2R_N<13> =PEG_D2R_N<14> =PEG_D2R_N<15>

=PEG_D2R_P<0> =PEG_D2R_P<1> =PEG_D2R_P<2> =PEG_D2R_P<3> =PEG_D2R_P<4> =PEG_D2R_P<5> =PEG_D2R_P<6> =PEG_D2R_P<7> =PEG_D2R_P<8> =PEG_D2R_P<9> =PEG_D2R_P<10> =PEG_D2R_P<11> =PEG_D2R_P<12> =PEG_D2R_P<13> =PEG_D2R_P<14> =PEG_D2R_P<15>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7> =PEG_R2D_C_N<8> =PEG_R2D_C_N<9> =PEG_R2D_C_N<10> =PEG_R2D_C_N<11> =PEG_R2D_C_N<12> =PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1> =PEG_R2D_C_P<2> =PEG_R2D_C_P<3> =PEG_R2D_C_P<4> =PEG_R2D_C_P<5> =PEG_R2D_C_P<6> =PEG_R2D_C_P<7> =PEG_R2D_C_P<8> =PEG_R2D_C_P<9> =PEG_R2D_C_P<10> =PEG_R2D_C_P<11> =PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14> =PEG_R2D_C_P<15>

R1010

24.9

1 2

1%

1/20W

MF

201

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

=PP1V05_S0_CPU_VCCIO

8

6

PLACE_NEAR=U1000.H43:50.8MM

6

PLACE_SIDE=BOTTOM

6

8

6

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

8

6

8

6

=PPVCORE_S0_CPU

NOSTUFF

R1064

R1065

NOTE: Intel validation sense lines per

=PPVCORE_S0_CPU_VCCAXG

NOSTUFF

1

R1070

49.9

1/16W MF-LF

NOSTUFF

49.9

1/16W MF-LF

PLACE_NEAR=U1000.K43:50.8MM PLACE_SIDE=BOTTOM

49.9

1%

1/16W MF-LF 402

402

2

PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM

Note. VOLTAGE=1.25V Note. VOLTAGE=0V

Note. VOLTAGE=1.05V Note. VOLTAGE=0V

NOSTUFF

1

R1071

49.9

1%

1/16W MF-LF 402

402

2

PLACE_NEAR=U1000.K45:50.8MM PLACE_SIDE=BOTTOM

7 9

10 12 14

7

12 14

CPU_CFG<0>

9

23 65

IN

CPU_CFG<1>

9

23 65

IN

CPU_CFG<2>

9

23 65

IN

CPU_CFG<3>

9

23 65

IN

CPU_CFG<4>

9

23 65

IN

CPU_CFG<5>

9

23 65

IN

CPU_CFG<6>

9

23 65

IN

CPU_CFG<7>

9

23 65

IN

CPU_CFG<8>

23 65

IN

CPU_CFG<9>

23 65

IN

CPU_CFG<10>

23 65

IN

CPU_CFG<11>

23 65

IN

23 65

23

IN IN IN IN

9

IN IN

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>

7

12 15

CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N

TP_CPU_VCC_DIE_SENSE

CPU_THERMD_P

46 71

OUT

CPU_THERMD_N

46 71

NOTE: Intel does not recommend to use this alnalog sense due to accuracy concern.

OUT

B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53

H43 K43

H45 K45

F48

H48 K48

BA19

NC

AV19

NC

AT21

NC

BB21

NC

BB19

NC

AY21

NC

BA22

NC

AY22

NC

AU19

NC

AU21

NC

BD21

NC

BD22

NC

BD25

NC

BD26

NC

BG22

NC

BE22

NC

BG26

NC

BE26

NC

BF23

NC

BE24

NC

OMIT_TABLE

CRITICAL

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17

VCC_VAL_SENSE VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

U1000

VCC_DIE_SENSE

RSVD_6 RSVD_7

RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26 RSVD_27

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

BGA

(5 OF 9) RESERVED

2C-35W

IVY-BRIDGE

RSVD_30 RSVD_31 RSVD_32 RSVD_33

RSVD_34 RSVD_35 RSVD_36 RSVD_37 RSVD_38

RSVD_39 RSVD_40

RSVD_41 RSVD_42 RSVD_43 RSVD_44

RSVD_45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

VOLTAGE=0.75V

PPCPU_MEM_VREFDQ_A PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

NC

VOLTAGE=0.75V

NC NC NC

NC NC NC NC NC

NC NC

NC NC NC NC

NC

TP_CPU_DC_TEST_A4 CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_D1 TP_CPU_DC_TEST_A58 CPU_DC_TEST_C59_A59

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_D61 TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BE59_BE61

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BG58 TP_CPU_DC_TEST_BG4 CPU_DC_TEST_C4_BE3_BG3

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

31

OUT

31

OUT

D

C

B

CPU_CFG<16>

9

CPU_CFG<7>

9

23 65

CPU_CFG<6>

9

23 65

CPU_CFG<5>

9

23 65

CPU_CFG<4>

9

23 65

CPU_CFG<2>

9

23 65

NOSTUFF

EDP:YES

NOSTUFF

1

R1044

R1042

1K

5% 5%

1/16W

MF-LF

A

402

2

1

1K

5%

402

2

R1045

R1046

1K

5%

1/16W

MF-LF

402

2

1

R1047

1K

5%

1/16W MF-LF

402

2

FOR IVYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

23

CPU_CFG<3>

9

23 65

CPU_CFG<1>

9

23 65

CPU_CFG<0>

9

23 65

R1041

NOSTUFF

R1043

1

1K

5% 1/16W MF-LF

402

2

1

1K

5% 1/16W MF-LF

402

2

NOSTUFF

R1040

These can be Placed close to J2500 and Only for debug access

NOSTUFF

1

1K

5% 1/16W MF-LF

402

2

=PP1V05_S0_CPU_VCCIO

7 9

NOSTUFF

R1049

10 12 14

1

1K

1/16W MF-LF

402

2

DP_INT_HPD

62

PLACE_NEAR=U1000.AG11:12.7MM

1

R1031

1K

5% 1/20W MF 201

2

D

3

1 G

S

2

EDP_HPD_L

Q1031

2N7002TXG

SOT-523-3

EDP:YES

CR SFF Intel doc #460452 Rise/Fall time <6ns

9

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/13/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

10 OF 109

SHEET

9 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP1V05_S0_CPU_VCCIO

7 9

10 12 14

NOSTUFF

1

R1115

4.99K

1% 1/20W MF 201

2

NOSTUFF

1

R1102

1K

5% 1/20W MF 201201

2

C57

NC

F49

C49

A48

C45

D45

C48

B46

BE45

D44

AT30

BF44 BE43 BG43

PLACE_NEAR=U1000.B46:12.7MM

1

R1111

10K

5% 1/20W MF 201

2

PROC_DETECT*

PROC_SELECT*

CATERR*

PECI

PROCHOT*

THERMTRIP*

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET*

SM_DRAMRST*

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

NOSTUFF

1

R1100

1

R1101

62

5% 1/20W MF 201

2

R1103

56

CPU_PROCHOT_L

40 41 56 65

BI

=PP1V5_S3_CPU_VCCDDR

7

12 15 26

C

17 26 65

IN

=PP1V05_S0_CPU_VCCIO

7 9

10 12 14

23 25

IN

PLACE_NEAR=R1121.2:1MM

PM_MEM_PWRGD

CPU_RESET_L

R1120

200

1/20W

1

1%

MF

201

2

R1126

1/20W

1

75

1% MF

201

2

1 2

5%

1/20W

MF

201

PLACE_NEAR=U1000.BE45:12.7MM

R1121

130

1 2

1%

1/20W

MF

201

R1125

43.2

1 2

1%

1/20W

MF

201

CPU_PROCHOT_R_L

19

OUT

40 65

OUT

19 41 65

BI

19 41 65

OUT

17 65

IN

19 23 65

IN

26

OUT

PM_MEM_PWRGD_R

1K

5%

1/20W

MF

201

2

CPU_PROC_SEL_L

CPU_CATERR_L

CPU_PECI

PM_THRMTRIP_L

PM_SYNC CPU_PWRGD

PLT_RESET_LS1V1_L

=MEM_RESET_L

1

2

R1113

R1112

25.5

140

1%

1/20W

MF

201

2

PLACE_NEAR=U1000.BF44:12.7MM PLACE_NEAR=U1000.BE43:12.7MM PLACE_NEAR=U1000.BG43:12.7MM

NOSTUFF

1

R1104

51

5% 1/20W MF

2

CPU_SM_RCOMP<0>

65

CPU_SM_RCOMP<1>

65

CPU_SM_RCOMP<2>

65

1

R1114

200

1% 1/20W MF 201

2

Intel Doc 460452 ChiefRiver SFF DG rev1.0 section 2.7.11 recommendation R1115.

OMIT_TABLE

CRITICAL

U1000

IVY-BRIDGE

2C-35W

BGA

(2 OF 9)

THERMAL

PWR MGMT

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

CLOCKS

BCLK_ITP*

(IPU) (IPU)

(IPU) (IPU) (IPU)

(IPU)

(IPU) (IPU)

JTAG & BPM

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

BCLK

BCLK*

PRDY* PREQ*

TCK TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

J3 H2

AG3 AG1

N59 N58

N53 N55

L56 L55 J58

M60 L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

DPLL_REF_CLKP DPLL_REF_CLKN

ITPCPU_CLK100M_P ITPCPU_CLK100M_N

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

16 65

IN

16 65

IN

8

65

IN

8

65

IN

16 65

IN

16 65

IN

23 65

OUT

23 65

IN

23 65

IN

23 65

IN

23 65

IN

23 65

IN

23 65

OUT

23 25 65

OUT

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

23 65

BI

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=J13_MLB

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/22/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

11 OF 109

SHEET

10 OF 72

124578

8 7 6 5 4 3

12

MEM_A_DQ<0>

27 66

BI

MEM_A_DQ<1>

27 66

BI

MEM_A_DQ<2>

27 66

BI

MEM_A_DQ<3>

27 66

BI

MEM_A_DQ<4>

27 66

D

C

B

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

27 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

28 66

BI

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

27 28 32 66

OUT

MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L

AG6 AJ6

AP11

AL6

AJ10

AJ8 AL8 AL7

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS* SA_RAS* SA_WE*

U1000

BGA

(3 OF 9)

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

MEMORY CHANNEL A

SA_CK_0

SA_CK_0*

SA_CKE_0

SA_CK_1

SA_CK_1*

SA_CKE_1

SA_CS_0* SA_CS_1*

SA_ODT_0 SA_ODT_1

SA_DQS_0* SA_DQS_1* SA_DQS_2* SA_DQS_3* SA_DQS_4* SA_DQS_5* SA_DQS_6* SA_DQS_7*

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

AU36 AV36

AY26

AT40 AU40

BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

27 28 32 66

8

66

8

66

27 28 32 66

27 66

28 66

27 66

28 66

27 28 32 66

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

29 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

30 66

BI

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

29 30 32 66

OUT

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9

BD9 BD13 BF12

BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS* SB_RAS* SB_WE*

2C-35W

SB_CK_0

SB_CK_0*

SB_CKE_0

SB_CK_1

SB_CK_1*

U1000

BGA

(4 OF 9)

SB_CKE_1

IVY-BRIDGE

OMIT_TABLE

CRITICAL

SB_CS_0* SB_CS_1*

SB_ODT_0 SB_ODT_1

SB_DQS_0* SB_DQS_1* SB_DQS_2* SB_DQS_3* SB_DQS_4* SB_DQS_5* SB_DQS_6* SB_DQS_7*

SB_DQS_0

MEMORY CHANNEL B

SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

BA34 AY34

AR22

BA36 BB36

BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI

29 30 32 66

8

66

8

66

29 30 32 66

29 66

30 66

29 66

30 66

29 30 32 66

D

C

B

A

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

12 OF 109

SHEET

11 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

=PPVCORE_S0_CPU_VCCAXG

7 9

12 15

=PPVCORE_S0_CPU

7 9

12 14

A26

VCC_1

A29

D

C

B

A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76

OMIT_TABLE

CRITICAL

U1000

BGA

(6 OF 9)

IVY-BRIDGE

CORE SUPLLY

VCCIO_1 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7

2C-35W

VCCIO_8

VCCIO_9 VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14 VCCIO_15 VCCIO_16 VCCIO_17 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29

VCCIO_30 VCCIO_31 VCCIO_32

PEG AND DDR

VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36 VCCIO_37 VCCIO_38 VCCIO_39 VCCIO_40 VCCIO_41 VCCIO_42 VCCIO_43 VCCIO_44 VCCIO_45 VCCIO_46 VCCIO_47 VCCIO_48 VCCIO_49

VCCIO_50 VCCIO_51

VCCIO_SEL

VCCPQE_1 VCCPQE_2

RAIL

VIDALERT*

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

LINES

SENSE SVID QUIET

VCCIO_SENSE

VSS_SENSE_VCCIO

A

=PP1V05_S0_CPU_VCCIO

(NOT controlled by VCCIO_SEL)

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

Fixed at 1.05V

For Future Compatibility

CPU_VCCIO_SEL

=PP1V05_S0_CPU_VCCPQE

CPU_VIDALERT_L_R CPU_VIDSCLK_R CPU_VIDSOUT_R

CPU_VCCSENSE_P CPU_VCCSENSE_N

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

=PP3V3_S0_CPU_VCCIO_SEL

NOSTUFF

1

R1320

10K

5%

1/20W

MF

201

2

7

14

7

1

R1302

130

1%

PLACE_NEAR=U1000.C44:2.54mm 1/20W MF 201

2

PLACE_NEAR=U1000.F43:50.8mm

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACE_NEAR=U1000.G43:50.8mm

R1310

1 2

1/20W

201

PLACE_NEAR=U1000.A44:38mm

R1311

1 2

1/20W

201

0

R1312

1 2

1/20W

201

PLACE_SIDE=BOTTOM

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=U7400.17:2.54mm

1

R1300

75

1% 1/20W MF 201

5% MF

5%

MF

MF05%

100

1/16W MF-LF

100

1/16W MF-LF

2

1

R1362

100

1%

1/16W MF-LF 402

402

2

1

R1363

100

1%

1% 1/16W MF-LF

402

2

43

R1360

R1361

7 9

10 12 14

CPU_VIDALERT_L

CPU_VIDSCLK

OUT

CPU_VIDSOUT

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=BOTTOM

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

56 65

OUT

56 65

OUT

58 65

OUT

58 65

OUT

PLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=BOTTOM

AA46

VAXG_1

AB47

VAXG_2

AB50

VAXG_3

AB51

VAXG_4

AB52

VAXG_5

AB53

VAXG_6

AB55

VAXG_7

AB56

VAXG_8

AB58

VAXG_9

AB59

VAXG_10

AC61

VAXG_11

AD47

VAXG_12

AD48

VAXG_13

AD50

VAXG_14

AD51

VAXG_15

AD52

VAXG_16

AD53

VAXG_17

AD55

VAXG_18

AD56

VAXG_19

AD58

VAXG_20

AD59

VAXG_21

AE46

VAXG_22

N45

VAXG_23

P47

VAXG_24

P48

VAXG_25

P50

VAXG_26

P51

VAXG_27

P52

VAXG_28

P53

VAXG_29

P55

VAXG_30

P56

VAXG_31

P61

VAXG_32

T48

VAXG_33

T58

VAXG_34

T59

VAXG_35

T61

VAXG_36

U46

VAXG_37

V47

VAXG_38

V48

VAXG_39

V50

VAXG_40

V51

VAXG_41

V52

VAXG_42

V53

VAXG_43

V55

VAXG_44

V56

VAXG_45

V58

VAXG_46

V59

VAXG_47

W50

=PPVCORE_S0_CPU_VCCAXG

7 9

12 15

1

R1370

100

1/16W MF-LF

1

1%

402

2

1% 1/16W MF-LF 402

2

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

=PPVCCSA_S0_CPU

7

12 15

PLACE_NEAR=U1000.F45:50.8mm

56 65

IN

56 65

OUT

56 65

BI

56 65

OUT

7 9

12 14

7 9

10 12 14

PLACE_NEAR=U1000.G45:50.8mm

PLACE_SIDE=BOTTOM

CPU_AXG_SENSE_P CPU_AXG_SENSE_N

=PP1V8_S0_CPU_VCCPLL_R

7

14

R1371

PLACE_SIDE=BOTTOM

W51 W52 W53 W55 W56 W61 Y48 Y61

F45 G45

BB3 BC1 BC4

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20

VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_1 VCCSA_2 VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13 VCCSA_14 VCCSA_15 VCCSA_16

U1000

(7 OF 9)

OMIT_TABLE

CRITICAL

(IPU)

BGA

2C-35W

IVY-BRIDGE

GRPHICS

DDR3-1.5V RAILS

RAIL

QUIET

VSS_SENSE_VDDQ

LINE

SENSE

(IPU)

LINE

SENSE

1.8V

RAIL

SA RAIL

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

AY43

R1314

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

PLACE_NEAR=U1000.AY43:2.54mm

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

=PP1V5_S3_CPU_VCCDDR

7

10 12 15 26

PLACE_NEAR=U1000.U10:50.8mm

PLACE_NEAR=U1000.BC43:50.8mm

PLACE_SIDE=BOTTOM

=PP1V5_S3_CPU_VCCDQ

CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N

CPU_VCCSASENSE CPU_VCCSA_VID<0>

CPU_VCCSA_VID<1>

1

R1313

10K

5%

1/20W

5% 1/20W

MF

201

2

10 12 15 26

SYNC_MASTER=J11_MLB

PAGE TITLE

CPU_DDR_VREF

VOLTAGE=0.75V

PLACE_NEAR=U1000.BA43:50.8mm

PLACE_SIDE=BOTTOM

=PP1V5_S3_CPU_VCCDDR

7

12

R1330

1/20W

R1331

53

1K

5%

MF

201

1K

5%

1/20W

MF

201

CPU POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

=PPVCCSA_S0_CPU

7

12 15

R1380

7

Note. VOLTAGE=1.05V Note. VOLTAGE=0V

OUT

R1381

1

2

1

2

PLACE_NEAR=U1000.AY43:2.54mm

6 3

1/20W

15

1/20W

100

201

53

100

201

1% MF

1

2

12

R1382

100

1%

1/20W

MF

1

201

2

1

2

CPU_DDR_VREF

C1330

0.1UF

10% 16V X5R-CERM 0201

SYNC_DATE=10/18/2011

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

13 OF 109

SHEET

12 OF 72

124578

1

2

OUT

2.7.0

D

C

53

B

12

A

SIZE

D

8 7 6 5 4 3

12

A9

VSS

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 AA1

AA8 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AB16 AB18 AB21 AB48 AB61

AC6 AC10 AC14 AC46

AD4 AD17 AD20 AD61

AE8 AE13

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG7 AG10 AG14 AG18 AG47 AG52 AG61

AH4 AH58

AJ7 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM4 AM13 AM20 AM22 AM26 AM30

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M11 M15 M58 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P9 P14 P16 P18 P21 P58 P59 R4 R17 R20 R46 T1 T47 T50 T51 T52 T53 T55 T56 U8 U13 V20 V61 W8 W13 W15 W18 W21 W46 Y4 Y47 Y58 Y59

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

BG13

VSS

BG17

VSS

BG21

VSS

BG24

VSS

BG28

VSS

D

C

B

BG37 BG41 BG45 BG49 BG53

C29 C35 C40

D10 D14 D18 D22 D26 D29 D35 D40 D43 D46 D50 D54 D58

E25 E29 E35 E40 F13 F15 F19 F29 F35 F40 F55

G48 G51 G61

H10 H14 H17 H21 H53 H58

J49 J55

K11 K21 K51 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

VSS VSS VSS VSS VSS VSS VSS VSS

D4

VSS

D6

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G6

VSS VSS VSS VSS

H4

VSS VSS VSS VSS VSS VSS VSS

J1

VSS VSS VSS

K8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M4

VSS

M6

VSS

U1000

BGA

(9 OF 9)

VSS

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

A

U1000

BGA

(8 OF 9)

VSS

IVY-BRIDGE

OMIT_TABLE

CRITICAL

2C-35W

6 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AM34 AM38 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP7 AP10 AP51 AP55 AR7 AR13 AR17 AR21 AR41 AR48 AR61 AT4 AT14 AT19 AT36 AT45 AT52 AT58 AU1 AU7 AU11 AU28 AU32 AU51 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW7 AW13 AW43 AW61 AY4 AY9 AY14 AY19 AY30 AY36 AY41 AY45 AY49 AY55 AY58 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC5 BC13 BC57 BD8 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BE5 BG9

PAGE TITLE

CPU GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

14 OF 109

SHEET

13 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

12

CPU VCORE DECOUPLING

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

=PPVCORE_S0_CPU

7 9

12

D

C

CRITICAL

1

C1600

1UF

20%

6.3V

2

X5R 0201 0201

CRITICAL

1

C1616

1UF

20%

6.3V

2

X5R

0201

PLACEMENT_NOTE (C1655-C1666): Place close to U1000 on top side.

CRITICAL

1

C1655

10UF

20%

6.3V

2

CERM-X5R CERM-X5R 0402-1

PLACEMENT_NOTE (C1667-C1679):

CRITICAL

1

C1601

1UF

20%

6.3V

2

X5R

CRITICAL

1

C1617

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1656

10UF

20%

6.3V

2

0402-1

CRITICAL

1

C1602

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1618

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1657

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1603

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1619

1UF

20%

6.3V

2

X5R 0201

1

2

CRITICAL

1

C1604

2

CRITICAL

1

2

CRITICAL

C1658

10UF

20%

6.3V CERM-X5R 0402-1

1UF

20%

6.3V X5R 0201

C1620

1UF

20%

6.3V X5R 0201

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

C1659

10UF

20%

6.3V

2

CERM-X5R 0402-1

C1605

1UF

20%

6.3V X5R 0201

C1621

1UF

20%

6.3V X5R 0201

CRITICAL

1

C1606

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1622

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1660

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1607

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1623

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1661

10UF

20%

6.3V

2

CERM-X5R 0402-1

Processor Load Line : -2.9 mOhms

CRITICAL

1

C1608

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

2

C1624

1UF

20%

6.3V X5R 0201

CRITICAL

1

C1662

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1609

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1625

1UF

20%

6.3V

2

X5R 0201

1

2

CRITICAL

1

C1610

1UF

20%

6.3V

2

X5R 0201

CRITICAL CRITICAL

1

C1626

1UF

20%

6.3V

2

X5R 0201

CRITICAL

C1663

10UF

20%

6.3V CERM-X5R 0402-1

1

C1664

2

10UF

20%

6.3V CERM-X5R 0402-1

CRITICAL

1

C1611

1UF

20%

6.3V

2

X5R 0201

1

C1627

2

CRITICAL

1UF

20%

6.3V X5R 0201

CRITICAL CRITICAL

1

C1665

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1612

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1628

1UF

20%

6.3V

2

X5R 0201

1

C1666

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1613

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1629

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1614

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

2

CRITICAL

1

C1630

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1667

10UF 10UF

20%

6.3V

2

CERM-X5R 0402-1

1

2

C1615

1UF

20%

6.3V X5R 0201

CRITICAL

1

C1631

1UF

20%

6.3V

2

X5R 0201

CRITICAL

C1668

20%

6.3V CERM-X5R 0402-1

CRITICAL

1

C1640

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1632

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1669

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1641

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1633

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1670

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1642

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1634

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1635

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1636

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1637

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1638

1UF

20%

6.3V

2

X5R 0201

CRITICAL

1

C1639

1UF

20%

6.3V

2

X5R 0201

D

C

PLACEMENT_NOTE (C1640-C1645):

1

C1680

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1681

270UF

20% 2V

2

TANT CASE-B2-SM CASE-B2-SM

1

C1682

270UF

20% 2V

2

TANT

1

C1683

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1679

270UF

20% 2V

2

TANT CASE-B2-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

PLACEMENT_NOTE (C1684-C167F):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

=PP1V05_S0_CPU_VCCIO

7 9

10 12

B

A

Place on bottom side of U1000

1

C1684

1UF

10% 10V

2

X5R 402

1

C1697

1UF

10% 10V

2

X5R 402

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom sidePlace near U1000 on bottom side

Place near U1000 on bottom side

1

C161E

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167D

270UF

20% 2V

2

TANT CASE-B2-SM

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

1 2

1%

1/4W

MF

0603

1

C1685

1UF

10% 10V

2

X5R 402

1

C1698

1UF 1UF

10% 10V

2

X5R 402

1

C161F

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167E

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1686

1UF

10% 10V

2

X5R 402

1

C1699

10% 10V

2

X5R 402

1

C162A

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167G

270UF

20% 2V 2V

2

TANT CASE-B2-SM

=PP1V05_S0_CPU_VCCPQE

1

C167F

1UF

10%

Note:The smallest 10mOhm available in the library are 0805s

10V

2

X5R 402

1

C1687

2

1

C169A

1UF

10% 10V

2

X5R 402

1

C162B

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C167H

270UF

20%

2

TANT CASE-B2-SM

7

12

1UF

10% 10V X5R 402

1

C1688

1UF

10% 10V

2

X5R 402

1

C169B

1UF

10% 10V

2

X5R 402

1

C162C

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1689

1UF

10% 10V

2

X5R 402

1

C169C

1UF

10% 10V

2

X5R 402

1

C162D

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1690

2

1

C169D

1UF

10% 10V

2

X5R 402

1

C162E

10UF

20%

6.3V

2

CERM-X5R 0402-1

1UF

10% 10V X5R 402

1

C1691

2

1

C169E

1UF

10% 10V

2

X5R 402

1

C167A

10UF

20%

6.3V

2

CERM-X5R 0402-1

1UF

10% 10V X5R 402

1

2

1

2

1

C167B

10UF

20%

6.3V

2

CERM-X5R 0402-1

C1692

1UF

10% 10V X5R 402

C169F

1UF

10% 10V X5R 402

1

2

1

2

1

C167C

10UF

20%

6.3V

2

CERM-X5R 0402-1

C1693

1UF

10% 10V X5R 402

C161A

1UF

10% 10V X5R 402

1

C1694

1UF

10% 10V

2

X5R 402

1

C161B

1UF

10% 10V

2

X5R 402

1

C1695

1UF

10% 10V

2

X5R 402

1

C161C

1UF

10% 10V

2

X5R 402

1

C1696

1UF

10% 10V

2

X5R 402

1

C161D

1UF

10% 10V

2

X5R 402

=PP1V8_S0_CPU_VCCPLL

7

6 3

CPU VCCPLL DECOUPLING

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

PLACEMENT_NOTE (C1646-C1671):

Place near U1000 on top side

R1600

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

CPU VCCPLL Low pass filter

=PP1V8_S0_CPU_VCCPLL_R

1

C160X

1UF

10% 10V

2

X5R 402

SYNC_MASTER=J13_MLB

PAGE TITLE

1

C160Y

1UF

10% 10V

2

X5R 402

PLACE_NEAR=U1000.BC2:5mm

1

C160Z

270UF

20% 2V

2

TANT CASE-B2-SM

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=08/16/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

16 OF 109

SHEET

14 OF 72

124578

7

12

B

A

SIZE

D

8 7 6 5 4 3

12

VAXG DECOUPLING

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

=PPVCORE_S0_CPU_VCCAXG

7 9

12

D

C

PLACEMENT_NOTE (C1700-C1710):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

CRITICAL

1

C1700

1UF

10% 10V

2

X5R 402

PLACEMENT_NOTE (C1711-C1716):

1

2

CRITICAL CRITICAL

1

C1711

10UF

20%

6.3V

2

CERM-X5R 0402-1

PLACEMENT_NOTE (C1717-C1722):

CRITICAL

AXG_ACOUSTICS:NO

1

C1717

22UF 22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

AXG_ACOUSTICS:YES

1

C1727

22UF

20% 4V

2

X5R 402

PLACEMENT_NOTE (C1723-C1724):

1

2

1

2

AXG_ACOUSTICS:YES

1

2

CRITICAL

C1701

1UF

10% 10V X5R 402

C1712

10UF

20%

6.3V CERM-X5R 0402-1

CRITICAL

AXG_ACOUSTICS:NO

C1718

20%

6.3V X5R-CERM1 0603

CRITICAL

C1728

22UF

20% 4V X5R 402

CRITICAL

1

C1702

1UF

10% 10V

2

X5R 402

CRITICAL

1

C1713

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

AXG_ACOUSTICS:NO

1

C1719

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

AXG_ACOUSTICS:YES AXG_ACOUSTICS:YES

1

C1729

22UF

20% 4V

2

X5R 402

1

C1703

1UF

10% 10V

2

X5R 402

CRITICAL

1

C1714

10UF

20%

6.3V

2

CERM-X5R 0402-1

AXG_ACOUSTICS:NO

1

C1720

22UF

20%

6.3V

2

X5R-CERM1 0603

1

C1730

22UF

20% 4V

2

X5R 402

CRITICAL

1

C1704

1UF

10% 10V

2

X5R 402

CRITICAL

1

C1715

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

AXG_ACOUSTICS:NO

1

C1721

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

AXG_ACOUSTICS:YES AXG_ACOUSTICS:YES

1

C1731

22UF

20% 4V

2

X5R 402

Graphics Load Line : -3.9 mOhms

1

2

1

C1705

1UF

10% 10V

2

X5R 402

CRITICAL

C1716

10UF

20%

6.3V CERM-X5R 0402-1

AXG_ACOUSTICS:NO

1

C1722

2

1

C1732

2

CRITICAL

22UF

20%

6.3V X5R-CERM1 0603

CRITICAL

22UF

20% 4V X5R 402

1

2

CRITICAL

C1706

1UF

10% 10V X5R 402

1

2

CRITICAL

C1707

1UF

10% 10V X5R 402

1

2

CRITICAL

C1708

1UF

10% 10V X5R 402

1

2

CRITICAL

C1709

1UF

10% 10V X5R 402

1

2

CRITICAL

C1710

1UF

10% 10V X5R 402

D

C

1

C1723

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1724

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1725

270UF

20% 2V

2

TANT CASE-B2-SM

CPU VCCSA DECOUPLING

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

PLACEMENT_NOTE (C1758-C1762):

=PPVCCSA_S0_CPU

7

12

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

B

=PP1V5_S3_CPU_VCCDDR

7

10 12 26

A

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U100.

1

C1738

1UF

10% 10V

2

X5R 402

Place close to U1000 on bottom side

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

Place close to U1000 on bottom side

1

C1748

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1756

270UF

20% 2V

2

TANT

CASE-B2-SM

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1702

1 2

0.010

1

C1739

1UF

10% 10V

2

X5R 402

1

C1749

10UF

20%

6.3V

2

CERM-X5R 0402-1 0402-1

=PP1V5_S3_CPU_VCCDQ

1%

1/4W

MF

0603

1

C1757

1UF

10% 10V

2

X5R 402

1

2

1

2

C1750

10UF

20%

6.3V CERM-X5R 0402-1

C1740

1UF

10% 10V X5R 402

1

C1741

1UF

10% 10V

2

X5R 402

1

C1751

10UF

20%

6.3V

2

CERM-X5R

7

12

1

C1742

1UF

10% 10V 10V

2

X5R 402

1

C1752

10UF

20%

6.3V

2

CERM-X5R 0402-1 0402-1

1

C1743

1UF

10%

2

X5R X5R 402

1

C1753

10UF

20%

6.3V

2

CERM-X5R

1

2

1

2

C1754

10UF

20%

6.3V CERM-X5R 0402-1

C1744

1UF

10% 10V

402

1

C1745

1UF

10% 10% 10V

2

X5R 402

1

C1755

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

2

C1746

1UF

10V X5R 402

1

2

C1747

1UF

10% 10V X5R 402

6 3

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1758

1UF

10% 10V

2

X5R 402

1

C1763

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1768

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1759

1UF

10% 10V

2

X5R 402

1

C1764

10UF

20%

6.3V

2

CERM-X5R 0402-1 0402-1

1

2

1

2

C1765

10UF

C1760

20%

6.3V CERM-X5R

1UF

10% 10V X5R 402

1

C1761

1UF

10% 10V

2

X5R 402

1

C1766

10UF 10UF

20%

6.3V

2

CERM-X5R 0402-1

SYNC_MASTER=K21_MLB

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

1

C1762

1UF

10% 10V

2

X5R 402

1

C1767

20%

6.3V

2

CERM-X5R 0402-1

CPU DECOUPLING-II

Apple Inc.

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

17 OF 109

SHEET

15 OF 72

124578

SIZE

B

A

D

8 7 6 5 4 3

SYSCLK_CLK32K_RTC

25 68

IN

RTC_RESET_L

16

PCH_SRTCRST_L

16

PCH_INTRUDER_L

D

VSel strap not functional (VCCVRM = 1.8V)

C

16

16 68

16

16 68

6

39 68

IN

6

16 25 68

19

OUT

16

IN

23 68

IN

23 68

IN

23 68

IN

23 68

OUT

42 68

OUT

42 68

OUT

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_SYNC_R

PCH_SPKR

HDA_RST_R_L

HDA_SDIN0 TP_HDA_SDIN1 TP_HDA_SDIN2 TP_HDA_SDIN3

HDA_SDOUT_R

JTAG_ISP_TMS ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

XDP_PCH_TMS

XDP_PCH_TDI

XDP_PCH_TDO

SPI_CLK_R

SPI_CS0_R_L

TP_SPI_CS1_L

SPI_MOSI_R

42 68

OUT

SPI_MISO

42 68

IN

=PPVRTC_G3_PCH

7

17 20

R1800

B

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

R1877 R1878

R1834 R1833

R1842 R1869 R1844 R1845 R1847

A

R1814 R1815 R1843

R1846 R1848 R1853 R1854 R1855

R1879

OMIT_TABLE

QP8D-MM915462

(IPD) (IPD) (IPD) (IPD)

(IPD-BOOT)

(IPD)

(IPU)

(IPD-BOOT)

(IPU)

U1800

BGA

(1 OF 10)

RTCSPI

IHDA

JTAG

(IPU)

16

FWH4/LFRAME*

LPC

LDRQ1*/GPIO23

(IPU)

SATA

SATA0GP/GPIO21 SATA1GP/GPIO19

16

16 16

16

16 68

16 25 68

(IPU)

SATAICOMPO SATAICOMPI

SATA3RCOMPO

SATA3COMPI SATA3RBIAS

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>RTC_RESET_L LPC_FRAME_R_L

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_RST_R_L

HDA_SDOUT_R

16

23 25

8

16

16 36

16

16 35

6

16

16 24

16

A19 C19

NC

F19

A23

K22

C21

H35

H37

F35

D36 B36 C35 A35

K37

K35 M35

M17

M15

U12

M12

AD12

AB8

AB6

1

20K

20%

X5R

1

R1803

20K

5%

5% 1/20W

MF

2

1

2

MF 201

2

PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L

1

C1803

2

201

MF5% MF

201

MF5%

201

MF

201

MF

201 201

MF

201

MF

201

MF

201

MF5%

201

MF

201

MF

201

MF

201

MF

201

R1802

R1801

1M

5% 1/20W MF 201

1/20W

C1802

1.0UF

6.3V

0201-MUR

7

17 18 19

7

17 18 19 25 35

5% MF

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W 1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

1

330K

5%

1/20W

MF

201

2

4.7K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

2 1

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V. If HDA = S0, must also ensure that signal cannot be high in S3.

PCH-PPT-MB-SFF-ES1

RTCX1 RTCX2

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

(IPD-BOOT)

N1

SPKR

(IPD-PLTRST#)

HDA_RST*

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0*

SPI_CS1*

W8

SPI_MOSI

Y2

SPI_MISO

1.0UF

20%

6.3V

X5R 0201-MUR

PCH_SPKR PCH_SATALED_L

DP_AUXCH_ISOL SATARDRVR_EN

FW_CLKREQ_L AP_CLKREQ_L EXCARD_CLKREQ_L JTAG_DPMUXUC_TRST_L ENET_CLKREQ_L PEG_CLKREQ_L TBT_CLKREQ_L SSD_CLKREQ_L

PEGCLKRQA_L_GPIO47 PEGCLKRQB_L_GPIO56 SMBUS_PCH_ALERT_L USB_EXTB_SEL_XHCI USB_EXTD_SEL_XHCI

ENET_MEDIA_SENSE_RDIV

LDRQ0*

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED*

A37 A39 C39 C37 K40

H40 F37

Y4

AN3 AN1 AU3 AU1

AN6 AN8 AR3 AR1

AD4 AD2 AL3 AL1

AD8 AD6 AG3 AG1

AE3 AE1 AH8 AH6

AC3 AC1 AJ3 AJ1

AB10 AB12

AF10 AF12 AH4

W10

M2 R1

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

(IPU)

PLACE_NEAR=U1800.H35:1.27mm

PLACE_NEAR=U1800.H37:1.27mm

PLACE_NEAR=U1800.F35:1.27mm

PLACE_NEAR=U1800.K37:1.27mm

16 37

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> LPC_FRAME_R_L

TP_LPC_DREQ0_L TBT_PWR_EN_PCH

LPC_SERIRQ

SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P

SATA_ODD_D2R_N SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_C_D2RN TP_SATA_C_D2RP TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP

TP_SATA_D_D2RN TP_SATA_D_D2RP TP_SATA_D_R2D_CN TP_SATA_D_R2D_CP

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP

TP_SATA_F_D2RN TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

PCH_SATAICOMP

67

PCH_SATA3COMP PCH_SATA3RBIAS

PCH_SATALED_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

33

R1860 R1861 R1862 R1863 R1864

R1810 R1811 R1812 R1813

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

16

OUT

IN

IN OUT OUT

IN

IN OUT OUT

6

16

5%

25

37 67

8

MF5%

1/20W

MF

1/20W

MF5%

1/20W

MF

1/20W

MF

1/20W

MF5%

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

ITPCPU_CLK100M_N

10 65

ITPCPU_CLK100M_P

10 65

=PP3V3_S0_PCH

1

R1820

10K

5% 1/20W MF 201

2

6

40 42

BI

=PP1V05_S0_PCH_VCCIO_SATA

PLACE_NEAR=U1800.AB10:2.54mm

1

R1830

37.4

1% 1/20W MF 201

2

=PP1V05_S0_PCH

1

R1831

49.9

1% 1/20W MF 201

2

PLACE_NEAR=U1800.AF12:2.54mm

23

OUT

8

23

OUT

LPC_AD<0>

201

LPC_AD<1>

201

LPC_AD<2>

201

LPC_AD<3>

201

LPC_FRAME_L

201

HDA_BIT_CLK

201

HDA_SYNC

201

HDA_RST_L

201

HDA_SDOUT

201

7

22

PLACE_NEAR=U1800.AH4:2.54mm

1

R1832

750

1% 1/20W MF 201

2

NO STUFF

R1841

0

1 2

5%

1/20W

MF

201

7

22

7

22

6

40 42 68

BI

6

40 42 68

BI

6

40 42 68

BI

6

40 42 68

BI

6

40 42 68

OUT

6

39 68

OUT

6

39 68

OUT

6

39 68

OUT

6

39 68

OUT

NO STUFF

R1840

0

1 2

5%

1/20W

MF

201

8

IN

8

IN

8

OUT

8

OUT

6

36 68

IN

6

36 68

IN

36 68

OUT

36 68

OUT

8

IN

8

IN

8

OUT

8

OUT

8

IN

8

IN

8

OUT

8

OUT

8

OUT

8

OUT

6

16 37

IN

8

16

6

36 68

OUT

6

36 68

OUT

16 36

IN

8

OUT

8

OUT

16

IN

16

OUT

37 65

6

OUT

6

37 65

OUT

16

IN

68

8

OUT

8

68

OUT

16

IN

33 68

OUT

33 68

OUT

16 35

IN

23 65

PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RN

8

NC_PCIE_5_D2RP

8

NC_PCIE_5_R2D_CN

8

NC_PCIE_5_R2D_CP

8

NC_PCIE_6_D2RN

8

NC_PCIE_6_D2RP

8

NC_PCIE_6_R2D_CN

8

NC_PCIE_6_R2D_CP

8

NC_PCIE_7_D2RN

8

NC_PCIE_7_D2RP

8

NC_PCIE_7_R2D_CN

8

NC_PCIE_7_R2D_CP

8

NC_PCIE_8_D2RN

8

NC_PCIE_8_D2RP

8

NC_PCIE_8_R2D_CN

8

NC_PCIE_8_R2D_CP

8

PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P SSD_CLKREQ_L

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P FW_CLKREQ_L

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P AP_CLKREQ_L

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4N

6

TP_PCIE_CLK100M_PE4P

6

JTAG_DPMUXUC_TRST_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN

6

TP_PCIE_CLK100M_PEBP

6

PEGCLKRQB_L_GPIO56

16

PEG_CLK100M_N PEG_CLK100M_P PEG_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P TBT_CLKREQ_L

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

25 68

IN

Unused clock terminations for FCIM Mode

10K

PCH_CLK96M_DOT_P

16 67

PCH_CLK96M_DOT_N

16 67

PCH_CLK100M_SATA_P

16 67

PCH_CLK100M_SATA_N

16 67

PCIE_CLK100M_PCH_P

16 67

PCIE_CLK100M_PCH_N

16 67

PCH_CLK14P3M_REFCLK

16 67

PCH_CLKIN_GNDP1

16

PCH_CLKIN_GNDN1

16

R1891 R1892

R1893 R1894

R1895 R1896

R1897

R1870 R1871

10K

10K 10K

10K

10K 10K

1 2 1 2

1 2

1 2 1 2

6 3

BJ33

PERN1

BL33

PERP1

BB30

PETN1

AY30

PETP1

BJ35

PERN2

BL35

PERP2

BB33

PETN2

AY33

PETP2

BH36

PERN3

BK36

PERP3

BF33

PETN3

BD33

PETP3

BJ37

PERN4

BL37

PERP4

BD35

PETN4

BF35

PETP4

BJ39

PERN5

BL39

PERP5

AY35

PETN5

BB35

PETP5

BH40

PERN6

BK40

PERP6

BD37

PETN6

BF37

PETP6

BJ41

PERN7

BL41

PERP7

AY37

PETN7

BB37

PETP7

BJ43

PERN8

BL43

PERP8

AY40

PETN8

BB40

PETP8

AD48

CLKOUT_PCIE0N

AD50

CLKOUT_PCIE0P

M4

PCIECLKRQ0*/GPIO73

AE49

CLKOUT_PCIE1N

AE51

CLKOUT_PCIE1P

U8

PCIECLKRQ1*/GPIO18

AD40

CLKOUT_PCIE2N

AD42

CLKOUT_PCIE2P

T4

PCIECLKRQ2*/GPIO20

AA49

CLKOUT_PCIE3N

AA51

CLKOUT_PCIE3P

B8

PCIECLKRQ3*/GPIO25

Y48

CLKOUT_PCIE4N

Y50

CLKOUT_PCIE4P

M19

PCIECLKRQ4*/GPIO26

AB40

CLKOUT_PCIE5N

AB42

CLKOUT_PCIE5P

K8

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

PEG_B_CLKRQ*/GPIO56

AB44

CLKOUT_PCIE6N

AB46

CLKOUT_PCIE6P

J3

PCIECLKRQ6*/GPIO45

W44

CLKOUT_PCIE7N

W46

CLKOUT_PCIE7P

H4

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

AR12

CLKOUT_ITPXDP_N

AR10

CLKOUT_ITPXDP_P

SYSCLK_CLK25M_SB

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

OMIT_TABLE

U1800

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

(2 OF 10)

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

C-LINK

PCI-E*

Controlled by PCIECLKRQ5#

CLOCKS

FLEX

CLOCKS

R1885

1 2

201

PLACE_NEAR=U1800.W49:5.1mm

1%

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

604

MF

1/20W

SMBALERT*/GPIO11

SML0ALERT*/GPIO60

(IPU/IPD) (IPU/IPD)

PEG_A_CLKRQ*/GPIO47

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1 CL_DATA1 CL_RST1*

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

(IPD-PWROK)

CLKOUTFLEX1/GPIO65

(IPD-PWROK)

CLKOUTFLEX2/GPIO66

(IPD-PWROK)

CLKOUTFLEX3/GPIO67

(IPD-PWROK)

SYSCLK_CLK25M_SB_R

1.8V -> 1.1V

1

R1886

1K

1% 1/20W MF 201

2

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

12

H12 F17 F10

H22 K12 A9

C9 D12 C11

L3 J1 M8

R8 AF44 AF46

BB24 AY24

AN10 AN12

BD17 BF17

BB26 AY26

M24 K24

AK8 AK6

J49

E51

W49 W51

AC49

H50

D48

G49

J51

PCH SATA/PCIe/CLK/LPC/SPI

SMBUS_PCH_ALERT_L SMBUS_PCH_CLK SMBUS_PCH_DATA

USB_EXTB_SEL_XHCI SML_PCH_0_CLK SML_PCH_0_DATA

USB_EXTD_SEL_XHCI SML_PCH_1_CLK SML_PCH_1_DATA

TP_CLINK_CLK TP_CLINK_DATA TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47 TP_PCIE_CLK100M_PEGAN TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

DOES THIS NEED LENGTH MATCH???

SYSCLK_CLK25M_SB_R

NC

=PP1V05_S0_PCH_VCCDIFFCLK

7

20 22

PLACE_NEAR=U1800.AC49:2.54mm

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

16 68

Apple Inc.

R

16

6

16

OUT OUT

16

16 68

SYNC_DATE=02/20/2012

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

18 OF 109

SHEET

124578

43 68

OUT

43 68

BI

16 24

OUT

43 68

OUT

43 68

BI

16

OUT

43 68

OUT

43 68

BI

10 65

8

OUT

8

OUT

16 67

IN

16 67

IN

16 67

IN

16 67

IN

16 67

IN

16 67

IN

16 67

IN

25 68

IN

1

R1890

90.9

1%

1/20W

MF

201

2

6

2.7.0

16 OF 72

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

=PP3V3_SUS_PCH_GPIO =PP1V05_S0_PCH_VCCIO_PCIE

PLACE_NEAR=U1800.BF19:12.7mm

1

10K

R1900

49.9

1%

5%

1/20W MF

MF

201

2

DMI_N2S_N<0>

9

65

IN

DMI_N2S_N<1>

9

65

IN

DMI_N2S_N<2>

9

65

IN

DMI_N2S_N<3>

9

65

IN

DMI_N2S_P<0>

9

65

IN

DMI_N2S_P<1>

9

65

IN

DMI_N2S_P<2>

9

65

IN

DMI_N2S_P<3>

9

65

IN

DMI_S2N_N<0>

9

65

OUT

DMI_S2N_N<1>

9

65

OUT

DMI_S2N_N<2>

9

65

OUT

DMI_S2N_N<3>

9

65

OUT

DMI_S2N_P<0>

9

65

OUT

DMI_S2N_P<1>

9

65

OUT

DMI_S2N_P<2>

9

65

OUT

DMI_S2N_P<3>

9

65

OUT

R1905

1/20W

D

PCH_DMI_COMP

25 40

IN

23 25 40

IN

25

IN

25

IN

10 26 65

OUT

61

IN

17 23 40

IN

40 41 61

IN

41

IN

PCH_DMI2RBIAS

PCH_SUSACK_L

17

PM_SYSRST_L

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PM_PCH_APWROK

PM_MEM_PWRGD

PM_RSMRST_L

PCH_SUSWARN_L

17

PM_PWRBTN_L

SMC_ADAPTER_EN

PM_BATLOW_L

PLACE_NEAR=U1800.BK20:2.54mm

1

R1920

750

1% 1/20W MF

C

201

2

PCH_RI_L

B

16 17 18 19

7

OMIT_TABLE

U1800

PCH-PPT-MB-SFF-ES1 PCH-PPT-MB-SFF-ES1

BL21

DMI0RXN

BL23

DMI1RXN

BJ19

DMI2RXN

BL17

DMI3RXN

BJ21

DMI0RXP

BJ23

DMI1RXP

BL19

DMI2RXP

BJ17

DMI3RXP

BD22

DMI0TXN

BB22

DMI1TXN

BB19

DMI2TXN

BB17

DMI3TXN

BF22

DMI0TXP

AY22

DMI1TXP

AY19

DMI2TXP

AY17

DMI3TXP

BF19

DMI_ZCOMP

BD19

DMI_IRCOMP

BK20

DMI2RBIAS

F15

SUSACK*

L1

SYS_RESET*

M10

SYS_PWROK

M22

PWROK

G3

APWROK

B12

DRAMPWROK

B20

RSMRST*

C13

SUSWARN*/SUSPWRDNACK/GPIO30

K19

PWRBTN*

H19

ACPRESENT/GPIO31

(IPD-DeepS4/S5)

H10

BATLOW*/GPIO72

F12

RI*

QP8D-MM915462

(IPU)

BGA

(3 OF 10)

FDI

DMI

CLKRUN*/GPIO32

MANAGEMENT

SYSTEM POWER

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

(IPU)

SLP_LAN*/GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE*

SLP_S4* SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10

BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10

BB10

BH12 BK8

BK12 BH8

F22

A21

D8

T2

G6

D3

F6 K10 D4

C7

A15

BB8

A7

FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7>

FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3> FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7>

FDI_INT

FDI_FSYNC<0> FDI_FSYNC<1>

FDI_LSYNC<0> FDI_LSYNC<1>

PCH_DSWVRMEN

PM_DSW_PWRGD

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

PM_SYNC

MEM_VDD_SEL_1V5_L

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

6

17 36

IN

6

BI

6

OUT

41 68

OUT

17 40 61

OUT

17 26 36 40 48 61

OUT

17 26 40 61

OUT

17 61

OUT

10 65

OUT

17 55

OUT

65

17 40 42

25 40 42

=PPVRTC_G3_PCH

1

R1915

390K

5% 1/20W MF 201

2

40

IN

1

R1909

100K

5% 1/20W MF 201

2

8

R1955

100K

1/20W

16 20

7

OUT

1

5% MF

201

2

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

8

OUT

LVDS_IG_BKL_PWM

8

OUT

TP_CRT_IG_BLUE

6

TP_CRT_IG_GREEN

6

TP_CRT_IG_RED

6

TP_CRT_IG_DDC_CLK

6

TP_CRT_IG_DDC_DATA

6

TP_CRT_IG_HSYNC

6

TP_CRT_IG_VSYNC

6

PCH_DAC_IREF

PLACE_NEAR=U1800.R51:2.54mm

1

R1951

1K

5% 1/20W

MF

201

2

M44

L_BKLTEN

M42

L_VDD_EN

L49

L_BKLTCTL

L51 K46

R42 M40

AH42 AH40

AG51 AG49

AK44 AK46

AR46 AN49 AN44 AK40

AR44 AN51 AN46 AK42

AH46 AH44

AM50 AL49 AJ51 AH50

AM48 AL51 AJ49 AH48

M46 R46 U46

R49 N49

M50 N51

R51 T48

L_DDC_CLK L_DDC_DATA

(IPD-PLTRST#)

L_CTRL_CLK L_CTRL_DATA

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK* LVDSA_CLK

LVDSA_DATA0* LVDSA_DATA1* LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK* LVDSB_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

NC NC

NC NC NC NC

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(4 OF 10)

SDVO_TVCLKINN

(IPD)

SDVO_TVCLKINP

(IPD)

SDVO_STALLN

(IPD)

SDVO_STALLP

(IPD)

SDVO_INTN

(IPD)

SDVO_INTP

(IPD)

SDVO_CTRLCLK

SDVO_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P

LVDS

DIGITAL DISPLAY INTERFACE

CRT

DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AU40 AU42

AR51 AR49

AT50 AT48

W42 R44

AW51 AW49 AY42

AY48 AY50 AY44 AY46 BB44 BB46 BA49 BA51

T50 U44

AU51 AU49 BE46

BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51

M48 U42

AU46 AU44 BK44

BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45

TP_SDVO_TVCLKINN TP_SDVO_TVCLKINP

TP_SDVO_STALLN TP_SDVO_STALLP

TP_SDVO_INTN TP_SDVO_INTP

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N DPA_IG_AUX_CH_P DPA_IG_HPD

TP_DP_IG_B_MLN<0> TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2> TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

DPB_IG_DDC_CLK DPB_IG_DDC_DATA

DPB_IG_AUX_CH_N DPB_IG_AUX_CH_P DPB_IG_HPD

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1> TP_DP_IG_C_MLP<1> TP_DP_IG_C_MLN<2> TP_DP_IG_C_MLP<2> TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXN TP_DP_IG_D_AUXP TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0> TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1> TP_DP_IG_D_MLP<1> TP_DP_IG_D_MLN<2> TP_DP_IG_D_MLP<2> TP_DP_IG_D_MLN<3> TP_DP_IG_D_MLP<3>

6

8

D

C

B

=PP3V3_SUS_PCH_GPIO

7

16 17 18 19

1

R1983

10K

5%

1/20W

MF

201

R1986

2

0

12

1/20W

5% MF

201

PCH_SUSACK_L

17

17 23 40

6

17 40 42

17 55

6

17 36

17 26 40 61

17 26 36 40 48 61

17 40 61

17 61

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH DMI/FDI/PM/Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/06/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

19 OF 109

SHEET

17 OF 72

124578

SIZE

A

D

PCH_SUSWARN_L

17

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO =PP3V3_S5_PCH

R1985 R1991

A

R1982 R1925

R1924 R1921 R1922 R1923

1K

8.2K

10K

100K 100K 100K 100K

1 2

2 1 2 1 2 1 2 1

7

16 17 18 19

7

16 18 19 25 35

7

1/20W

5%

5% MF

5% MF1K201

5%

5% 5%

1/20W

1/20W 1/20W

MF

MF MF

PM_PWRBTN_L

201

PM_CLKRUN_L

201

MEM_VDD_SEL_1V5_L

201

PCIE_WAKE_L

PM_SLP_S3_L

201

PM_SLP_S4_L

201

PM_SLP_S5_L

201

PM_SLP_SUS_L

201

8 7 6 5 4 3

12

BH24 BK24 BH20 BK16 BH16 AN42 AN40 AR40 AR42

AD10

AD44 AD46 BJ48

BH49 BB42

BJ25 BJ27 BJ31 BJ29

BL25 BL27 BL31 BL29

BF26 BB28 BF28 BF30

BD26 AY28 BD28 BD30

D20 M30

AM4 AT4 AT2

B24 D24

BL7 W40 K30

D49 C48 C47 C45

G46 K44 F46

F42 H42 D44

A47 C41 F45 F40

G51 E49 H48 J43 G45

E3

H2

F7

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24

TP41 TP42

USB3RN1 USB3RN2 USB3RN3 USB3RN4

USB3RP1 USB3RP2 USB3RP3 USB3RP4

USB3TN1 USB3TN2 USB3TN3 USB3TN4

USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA* PIRQB* PIRQC* PIRQD*

REQ1*/GPIO50 REQ2*/GPIO52 REQ3*/GPIO54

GNT1*/GPIO51 GNT2*/GPIO53 GNT3*/GPIO55

(IPU-PCIERST#)

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

PME*

PLTRSTB*

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

NC NC NC NC NC NC NC NC NC NC

D

TP_PCH_TP23

NC NC NC NC NC NC NC NC NC NC NC NC

NC

USB3_EXTA_RX_N

38 67

IN

USB3_EXTB_RX_N

39 67

IN

USB3_EXTC_RX_N

8

IN

USB3_EXTD_RX_N

8

IN

USB3_EXTA_RX_P

38 67

IN

USB3_EXTB_RX_P

39 67

C

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

R2010 R2011 R2012 R2013

B

R2054

=PP3V3_SUS_PCH_GPIO =PP3V3_S3_PCH_GPIO =PP3V3_S0_PCH_GPIO

R2016 R2017 R2018

R2030

R2014 R2031

A

R2033

R2069 R2060

R2061 R2062 R2068

R2067

10K 10K 10K

10K

10K 10K

10K

10K 10K 10K 10K

10K

7

16 17 19

7

25

7

16 17 18 19 25 35

1 2

NO STUFF

1 2

NO STUFF

1 2

1 2 1 2

2 1

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

Redundant to pull-down on audio page

5%

1/20W 1/20W

5% MF

Redundant to pull-up on audio page

5%

1/20W

5%

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1/20W

1/20W 1/20W

1/20W

JTAG_GMUX_TMS

201

MF

BLC_I2C_MUX_SEL

201

PCH_GPIO54

201

MF

BLC_GPIO

201

MF

AUD_IP_PERIPHERAL_DET

MF

201

TBT_PWR_REQ_L

201

AUD_I2C_INT_L

201

MF

201

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

201

MF5%

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

MF5%

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

201

MF5%

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

MF

201

AP_PWR_EN

201

MF

10K 10K 10K 10K

10K

1 2

1 2 1 2

1 2

NO STUFF

2 1

18

6

18 39

18 33

6

18 39

23 36 61

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

18 23

IN

8

IN

8

IN

38 67

OUT

39 67

OUT

8

OUT

8

OUT

38 67

OUT

39 67

OUT

8

OUT

8

OUT

MF

201

MF

201

MF

201

18

OUT

18

OUT

18

OUT

201

MF

18

IN

6

18 39

IN

18 33

IN

6

18 39

IN

6

25 26

OUT

25 68

OUT

25 68

OUT

6

25 68

OUT

USB3_EXTC_RX_P USB3_EXTD_RX_P

USB3_EXTA_TX_N USB3_EXTB_TX_N USB3_EXTC_TX_N USB3_EXTD_TX_N

USB3_EXTA_TX_P USB3_EXTB_TX_P USB3_EXTC_TX_P USB3_EXTD_TX_P

PCI_INTA_L PCI_INTB_L PCI_INTC_L PCI_INTD_L

JTAG_GMUX_TMS BLC_I2C_MUX_SEL PCH_GPIO54

TP_PCH_STRP_BBS1 TP_PCH_STRP_ESI_L PCH_STRP_TOPBLK_SWP_L

BLC_GPIO AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L AUD_I2C_INT_L

TP_PCI_PME_L

PLT_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

U1800

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

(5 OF 10)

USB

PCI

(IPU)

(IPD)

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

USBRBIAS*

6 3

RSVD

USBP0N USBP0P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP13N USBP13P

(IPD)

USBRBIAS

AU6 AU8 AW1 AW3 AY2 AY4 AY6 AY8 BA1 BA3 BB6 BC1 BC3 BD2 BD4 BE1 BE3 BE6 BF6 BF7 BG1 BG3 BH3 BH4 BJ4 BJ5 BJ7 BK6 BL5

F24 H24

C25 A25

C27 A27

H28 F28

M26 K26

D28 B28

H26 F26

D32 B32

M28 K28

C29 A29

C31 A31

H33 F33

H30 F30

M33 K33

C33 A33

C17 A17 A13 D16 A11 B16 C23 H15

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

USB_EXTA_N USB_EXTA_P

USB_EXTB_XHCI_N USB_EXTB_XHCI_P

USB_EXTC_N USB_EXTC_P

USB_EXTD_XHCI_N USB_EXTD_XHCI_P

TP_USB_4N TP_USB_4P TP_USB_SDN

BI BI

TP_USB_SDP

TP_USB_WLANN

TP_USB_WLANP

USB_HUB_UP_N USB_HUB_UP_P

USB_CAMERA_N USB_CAMERA_P

USB_EXTB_EHCI_N USB_EXTB_EHCI_P

USB_EXTD_EHCI_N USB_EXTD_EHCI_P

TP_USB_BT_HSN TP_USB_BT_HSP

TP_USB_12N TP_USB_12P

TP_USB_13N TP_USB_13P

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L XDP_DB2_PCH_GPIO10_AP_PWR_EN XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

BI BI

38 67

24 67

BI

24 67

BI

8

BI

8

BI

24 67

BI

24 67

BI

24 67

6

39 67

6

39 67

24 67

8

PCH_USB_RBIAS

67

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Ext D (XHCI) (Mobiles: Trackpad?)

Unused

RSVD: SD

RSVD: WiFi

USB Hub (All LS/FS Devices)

Camera

Ext B (EHCI)

Ext D (EHCI)

RSVD: BT (HS)

Unused

PLACE_NEAR=U1800.A33:2.54mm

1

R2070

2

22.6

1% 1/20W MF 201

18 23

IN

18 23

IN

18 23

IN

18 23

IN

23

IN

23

IN

23

OUT

18 23

IN

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH PCI/USB/TP/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/22/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

20 OF 109

SHEET

18 OF 72

124578

SIZE

D

C

B

A

D

OMIT_TABLE

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

12

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

(TBT_CIO_PLUG_EVENT_ISOL)

XDP_FC1_PCH_GPIO0

19 23

FW_PME_L

19

IN

DPMUX_UC_IRQ

19

IN

SMC_RUNTIME_SCI_L

19 40

IN

TP_PCH_GPIO8

WOL_EN

19

OUT

XDP_FC0_PCH_GPIO15

23

IN

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

23

OUT

LPCPLUS_GPIO

6

19 42

BI

ODD_PWR_EN_L

19

OUT

TBT_GO2SX_BIDIR

19 33

SMC_WAKE_SCI_L

19 40

IN

0

35

OUT

TBT_SW_RESET_L

R2180

1 2

5% MF

C

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L TBT_SW_RESET_R_L

19

1/20W

201

19 23

OUT

23

OUT

19

IN

19

OUT

19

OUT

8

23

OUT

6

19 42 49

BI

XDP_DC1_PCH_GPIO35_MXM_GOOD

23

OUT

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK JTAG_ISP_TDO JTAG_ISP_TDI FW_PWR_EN_PCH XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH SPIROM_USE_MLB

W1

BMBUSY*/GPIO0

B40

GPIO1

C43

GPIO6

A45

GPIO7

H17

GPIO8

C5

LAN_PHY_PWR_CTRL/GPIO12

K6

GPIO15

AA3

SATA4GP/GPIO16

B44

GPIO17

W3

SCLOCK/GPIO22

K15

GPIO24

C15

GPIO27

G1

GPIO28

R3

STP_PCI*/GPIO34

W12

GPIO35

W6

SATA2GP/GPIO36

(IPD-PLTRST#)

M6

SATA3GP/GPIO37

(IPD-PLTRST#)

N3

SLOAD/GPIO38

U10

SDATAOUT0/GPIO39

U1

SDATAOUT1/GPIO48

AA1

SATA5GP/GPIO49

K17

GPIO57

A4

A5 A48 A49 A51 BH1

BH51

VSS_NCTF

BJ1 BJ3

BJ49 BJ51

BL1 BL3 BL4

Systems with chip-down memory should add pull-downs on another page and set straps per software.

(IPU-RSMRST#)

(IPU)

(IPU-DeepS4/S5)

(IPU-RSMRST#)

U1800

QP8D-MM915462

(6 OF 10)

PCH-PPT-MB-SFF-ES1

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

OMIT_TABLE

BGA

GPIO

CPU/MISC

NCTF

GPIO68 GPIO69 GPIO70 GPIO71

A20GATE

(IPD)

RCIN*

PROCPWRGD

THRMTRIP*

INIT3_3V*

(IPU)

DF_TVS

(IPD-PLTRST#?)

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

VSS_NCTF

PECI

NC_1

K42 A43 D40 A41

U3

AU12

U6

AU10

BC9

R6

BC7

AK10 AH12 AK12 AH10

U40

BL48 BL49 BL51 C3 C49 C51 D1 D51 E1

41

NC

MLB_RAMCFG3

8

MLB_RAMCFG2

8

MLB_RAMCFG1

8

MLB_RAMCFG0

8

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

PCH_INIT3V3_L

PCH_DF_TVS

NO STUFF

R2130

1/20W

RAMCFG3:H

R2172

1/20W 1/20W

19

1

1K

This has internal pull up and should not pulled low.

5%

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

MF

201

2

10K

5%

MF

201

R2170

R2140

R2156

RAMCFG2:H

1

2

390

R2173

10K

5%

MF 201

43

0

NO STUFF

1 2

RAMCFG1:H RAMCFG0:H

1

R2174

10K

5%

1/20W

MF

201

2

CPU_PECI

1/20W

5%

201

MF

CPU_PWRGD

5%

1/20W

MF

201

PM_THRMTRIP_L

1/20W

5%

201

MF

1

R2175

10K

5% 1/20W MF 201

2

D

10 41 65

BI

10 23 65 23

OUTOUT

10 41 65

IN

R2178

1K

5%

1/20W

MF

201

=PP1V8_S0_PCH_VCC_DFTERM

1

R2179

2.2K

5% 1/20W MF 201

2

12

CPU_PROC_SEL_L DF_TVS:DMI & FDI Term Voltage Set to Vss when Low Set to Vcc when High

10

7

20 22

C

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

TBT_PWR_EN goes high for JTAG Programming

B

JTAG Isolation due to glitch in and out of sleep

NOTE: TCK from PCH is Push-Pull CMOS NOTE: TMS/TDI from PCH is Open Drain

=PP3V3_S5_PCH_GPIO =PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

Stuff R2160 or R2574, not both

R2160 R2185 R2196 R2190

R2197 R2184

R2150 R2155

A

R2194 R2192 R2193

R2191 R2111

R2195 R2112 R2198

R2116

10K 10K 10K

100K

10K 10K

100K

10K

20K

100K

10K 10K

10K

NO STUFF

1 2

1 2 1 2

NO STUFF

1 2 1 2

1 2

1 2 1 2

1 2

2 1 2 1 2 1 2 1

2 1

7

16 17 18

7

16 17 18 19 25 35

1/20W

5% 5%

1/20W

Must stuff R2197 when R2180 NO STUFFed.

1/20W

5%

1/20W

5% MF

5%

1/20W

5%

1/20W

5% MF

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

5% MF

XDP_FC1_PCH_GPIO0

MF5%

201

FW_PME_L

201

MF

SMC_RUNTIME_SCI_L

MF

201

LPCPLUS_GPIO

MF5%

201

TBT_SW_RESET_R_L

MF5%

201

FW_PWR_EN_PCH

MF

201

PCH_A20GATE

201

PCH_RCIN_L

201

MF

WOL_EN

MF

201

TBT_GO2SX_BIDIR

201

SPIROM_USE_MLB

201

SMC_WAKE_SCI_L

201

MF

DPMUX_UC_IRQ

MF

201

AUD_IPHS_SWITCH_EN_PCH

201

MF

ODD_PWR_EN_L

201

MF

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

201

ENET_LOW_PWR_PCH

201

19 23

19

19 40

6

19 42

19

19 33

6

19 42 49

19 40

19

23 25

19

19 23

8

=PP3V3_S0_PCH_STRAPS

7

19

JTAG_ISP_TMS

16 33

IN

=PP3V3_S0_PCH_STRAPS

7

19

JTAG_ISP_TDI

19 33

IN

=PP3V3_S0_PCH_STRAPS

7

19

JTAG_ISP_TDO

19

OUT

NOTE: TDO from CR is Push-Pull CMOS

CRITICAL

5% 1/20W MF 201

Q2160

SSM6N15AFE

SOT563

D

6

1

R2188

10K

2

CRITICAL

R2199

10K

5% 1/20W MF 201

Q2160

SSM6N15AFE

SOT563

CRITICAL

Q2162

SSM3K15FV

SOD-VESM-HF

D

3

1

2

1

R2186

10K

5%

MF 201

2

=PP3V3_TBT_PCH_GPIO

1

2

S G

1

R2163

10K

5% 1/20W MF 201

2

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

1

5

D

3

S G

4

R2161

10K

5% 1/20W MF 201

2

JTAG_TBT_TDI

=PP3V3_TBT_PCH_GPIO

1

GS

2

R2162

10K

5% 1/20W1/20W MF 201

2

JTAG_TBT_TDO

7

19

OUT

7

19

TBT_CIO_PLUG_EVENT

33

IN

OUT

7

19

33

IN

TBT_PWR_EN

25 33

JTAG_ISP_TCK

23

1

R2113

10K

5% 1/20W MF 201

2

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 25 35

1

R2166

10K

5% 1/20W MF 201

2

6 3

C2114

0.1UF

X5R-CERM

C2113

0.1UF

X5R-CERM

10% 16V

0201

1

10% 16V

2

0201

2

U2100

1

NC

5

6

08

3

CRITICAL

74LVC1G08

SOT891

4

JTAG_TBT_TCK

33

OUT

B

NC

1

2

U2101

1

NC

5

NC

6

08

3

CRITICAL

74LVC1G08

SOT891

4

TBT_CIO_PLUG_EVENT_ISOL

NO STUFF

1

R2167

10K

5% 1/20W MF 201

2

23

OUT

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH GPIO/MISC/NCTF

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/23/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

21 OF 109

SHEET

19 OF 72

SIZE

A

D

124578

8 7 6 5 4 3

12

D

PLACE_NEAR=U1800.R15:2.54mm

C2210

X5R-CERM

C

C2222

X5R-CERM

7

16 17

PLACE_NEAR=U1800.N16:2.54mm

B

VCCACLK pin left as NC per DG

PCH output, for decoupling only

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

10% 16V

2

0201

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

=PPVRTC_G3_PCH

PLACE_NEAR=U1800.U17:2.54mm

10% 16V

2

0201

C2231

1UF

6.3V 0201

VCCAPLLDMI2 pin left as NC per DG

AL24 left as NC per DG

22

1

20% X5R

2

PLACE_NEAR=U1800.N16:2.54mm

PCH output, for decoupling only

=PP3V3_S5_PCH_VCCDSW

7

22

TP_PPVOUT_PCH_DCPSUSBYP

PPVOUT_G3_PCH_DCPRTC

PP1V05_S0_PCH_VCCADPLLA_F

22

PP1V05_S0_PCH_VCCADPLLB_F

22

=PP1V05_S0_PCH_VCCDIFFCLK

7

16 22

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCSSC

7

22

PPVOUT_S0_PCH_DCPSST

PP1V05_S0_PCH_VCCCLKDMI_F

22

=PP1V05_S0_PCH_V_PROC_IO

7

22

=PP1V05_S0_PCH_VCCASW

7

C2232

0.1UF

10% 16V X5R-CERM 0201

1

C2233

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=U1800.N16:2.54mm

D

AC51

R12

R10

AW31

R15 U15

BF40 BD40

AC37 AE37 AE39

AC35

U17

AP39

AM17

N16

AB27 AB29 AB31 AC27 AC29 AC31 AE27 AE29 AE31

R19 U19 U21 V19 V21 V23 V25 Y21 Y23

Y25

Y27 Y29 Y31

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCCAPLLDMI2

DCPRTC

VCCADPLLA VCCADPLLB

VCCDIFFCLKN

VCCSSC

DCPSST

VCCCLKDMI

V_PROC_IO

VCCRTC

VCCASW

NC

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(8 OF 10)

USB

PCI/GPIO/LPC

SATA

HDA

CLK/MISC

CPURTC

V5REF_SUS

VCCPUSB

VCCAPLL_SATA3

VCCSUSHDA

VCCSUS3_3

V5REF

VCCIO

DCPSUS

VCCVRM

M37

=PP5V_SUS_PCH_V5REFSUS

U27

=PP3V3_SUS_PCH_VCCSUS_USB

U29

N36

=PP5V_S0_PCH_V5REF

AM2

NC

NC-ed per DG

V31

=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

AA13

=PP1V05_S0_PCH_VCCIO AB15 AC13 AC15 AF15 AG13 AG15 AJ17 AK21 N18 R23 R25 U23 U25

AM27

=PP3V3_SUS_PCH_VCCSUS N27 R27 R29 R33 R35 U33 U35

AR33

NC

AU31

NC

AU33

NC

V13

NC

AC39

=PP1V8R1V5_S0_PCH_VCCVRM AE19 AF17 AW18 AW21

22

7

22

7

22 25

7

20 22

7

22

7

20

=PP1V05_S0_PCH_VCC_CORE

7

22

1.44 A Max, 474mA Idle

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCCIO

7

20 22

AB21 AB23 AC21 AC23 AE21 AE23 AF21 AF23 AG21 AG23 AG25 AG27 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AK29 AK31 AK33 AM33 AM35

AP19

AM21 AP27 AR15 AR23 AR25 AR27 AR29 AT13 AU23 AU25 AU27 AU29 AU35 AW34

PCH-PPT-MB-SFF-ES1PCH-PPT-MB-SFF-ES1

VCCCORE

VCCAPLLEXP

VCCIO

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(7 OF 10)

CRTFDI

VCC CORE

LVDS

DMI

DFT/SPI

VCCIO

VCCADAC

VSSA_DAC

VCCALVDS

VSSALVDS

VCCTX_LVDS

VCCDMI

VCCADMI_VRM

VCCDFTERM

VCCSPI

VCCAFDIPLL

VCCAFDI_VRM

VCC3_3

U51

PP3V3_S0_PCH_VCCA_DAC_F

V50

AF33 AG33 AC33 AE33

AF37 AG37 AG39 AJ37

AM23

=PP1V05_S0_PCH_VCC_DMI AU15 AW16 AU21

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_PCH_VCC_DFTERM AJ13 AJ15 AK15 AL13

Y19

=PP3V3_SUS_PCH_VCC_SPI

AP13

NC

AP15

NC

AU19

=PP1V8R1V5_S0_PCH_VCCVRM

AB19

=PP3V3_S0_PCH_VCC3_3

AC19 AF6 BK28 R40 T39 U37 V37

PP3V3_S0_PCH_VCC3_3_CLK_F

V39

22

7

22

7

20

7

19 22

7

22

7

20

7

22

C

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/22/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

22 OF 109

SHEET

20 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

AA7 AA9

PCH-PPT-MB-SFF-ES1

AA11 AA39 AA41 AA43 AA45

D

C

B

A

AB2

AB4 AB17 AB25 AB33 AB35 AB37 AB48 AB50

AC7

AC9 AC11 AC17 AC25 AC41 AC43 AC45

AE7

AE9 AE11 AE13 AE15 AE17 AE25 AE35 AE41 AE43 AE45

AF2

AF4

AF8 AF19 AF25 AF27 AF29 AF31 AF35 AF48 AF50

AG7

AG9 AG11 AG17 AG19 AG29 AG31 AG35 AG41 AG43 AG45

AH2

AJ7

AJ9 AJ11 AJ19 AJ33 AJ35 AJ39 AJ41 AJ43 AJ45

AK2

AK4 AK17 AK19 AK23 AK25 AK27 AK35 AK37 AK48 AK50

AL7

AL9 AL11 AL39 AL41 AL43 AL45 AM15 AM19 AM25 AM29 AM31 AM37

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(9 OF 10)

AP2 AP4 AP7 AP9 AP11 AP17 AP21 AP23 AP25 AP29 AP31 AP33 AP35 AP37 AP41 AP43 AP45 AP48 AP50 AR6 AR8 AR17 AR19 AR21 AR31 AR35 AR37 AT7 AT9 AT11 AT39 AT41 AT43 AT45 AU17 AU37 AV2 AV4 AV48 AV50 AW7 AW9

VSSVSS

AW11 AW13 AW23 AW25 AW27 AW29 AW36 AW39 AW41 AW43 AW45 AY10 B6 B10 B14 B18 B22 B26 B30 B34 B38 B42 B46 BA7 BA9 BA11 BA13 BA16 BA18 BA21 BA23 BA25 BA27 BA29 BA31 BA34 BA36 BA39 BA41 BA43 BA45 BB2 BB4 BB48 BB50 BC11 BC13 BC16 BC18 BC21

BC23 BC25

PCH-PPT-MB-SFF-ES1

BC27 BC29 BC31 BC34 BC36 BC39 BC41 BC43 BC45 BD15 BD24

BE7

BE9 BE11 BE13 BE16 BE18 BE21 BE23 BE25 BE27 BE29 BE31 BE34 BE36 BE39 BE41 BE43 BE45

BF2

BF4 BF15 BF24 BF48 BF50

BH6 BH10 BH14 BH18 BH22 BH26 BH28 BH30 BH32 BH34 BH38 BH42 BH44 BH46 BH48 BK10 BK14 BK18 BK22 BK26 BK30 BK32 BK34 BK38 BK42 BK46

D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46

F2

F4 F48 F50

G7

G9 G11 G13 G16 G18 G21 G23 G25 G27 G29 G31 G34 G36

6 3

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(10 OF 10)

G39 G41 G43 J7 J9 J11 J13 J16 J18 J21 J23 J25 J27 J29 J31 J34 J36 J39 J41 J45 K2 K4 K48 K50 L7 L9 L11 L13 L16 L18 L21 L23 L25 L27 L29 L31 L34 L36 L39 L41

VSSVSS

L43 L45 N7 N9 N11 N13 N21 N23 N25 N29 N31 N34 N39 N41 N43 N45 P2 P4 P48 P50 R17 R21 R31 R37 T7 T9 T11 T13 T41 T43 T45 U31 U49 V2 V4 V7 V9 V11 V15 V17 V27 V29 V33 V35 V41 V43 V45 V48 Y15 Y17 Y33 Y35 Y37

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=08/12/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

23 OF 109

SHEET

21 OF 72

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

PCH VCCIO BYPASS

L2406

=PP1V05_S0_PCH

7

16

10UH-0.12A-0.36OHM

1 2

0603

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

PLACE_NEAR=U1800.AP39:2.54mm

R2415

0

1 2

5%

1/20W

MF

201

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE

1

C2411

10UF

20%

6.3V

2

CERM-X5R 0402-2

20

PLACE_NEAR=U1800.R27:2.54mm

D

7

20

PLACE_NEAR=U1800.AM17:2.54mm PLACE_NEAR=U1800.AM17:2.54mm PLACE_NEAR=U1800.AM17:2.54mm

=PP3V3_S0_PCH_VCCADAC

7

R2450

0

1 2

5%

1/20W

MF

201

C2450

10UF

20%

6.3V

CERM-X5R

0402-2

PLACE_NEAR=U1800.U51:2.54mm PLACE_NEAR=U1800.U51:2.54mm PLACE_NEAR=U1800.U51:2.54mm

1

2

C2451

0.1UF

10% 16V

X5R-CERM

0201

PP3V3_S0_PCH_VCCA_DAC_F

0.01UF

X5R-CERM

0201

10% 16V

1

2

1

2

C2455

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

20

C

=PP3V3_S0_PCH

7

16

=PP5V_S0_PCH

7

25

1 mA

R2405

C2439

PLACE_NEAR=U1800.N36:2.54mm

=PP3V3_SUS_PCH

7

=PP5V_SUS_PCH

7

1 mA S0-S5

B

PLACE_NEAR=U1800.M37:2.54mm

=PP3V3_S0_PCH_VCC3_3

7

20 22

1

C2421

0.1UF

10% 16V

2

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

A

=PP3V3_S0_PCH_VCC3_3

7

20 22

PLACE_NEAR=U1800.T39:2.54mm

0201

100

1/20W

201

1UF

10% 10V X5R 402

R2404

1/20W

C2438

0.1UF

20% 10V

CERM

402

1

C2424

0.1UF

10% 16V

2

X5R-CERM 0201

12

5% MF

1

2

12

10

5% MF

201

1

2

20 22

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

1

5

D2400

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)

4

2

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S0_PCH_VCC3_3

7

PLACE_NEAR=U1800.AF6:2.54mm

NEED PWR CONSTRAINT

<1 MA

20

NEED PWR CONSTRAINT

1

C2423

0.1UF

10% 16V

2

X5R-CERM 0201

=PP3V3_S0_PCH_VCC3_3

7

20 22

20

=PP3V3_S0_PCH_VCC3_3

7

20 22

PLACE_NEAR=U1800.AB19:2.54mm

1

C2485

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=U1800.R40:2.54mm

=PP3V3_S0_PCH_VCC3_3_CLK

7

PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)

=PP3V3_SUS_PCH_VCCSUS

7

20 22

1

C2484

0.1UF

10% 16V

2

X5R-CERM 0201

=PP1V05_S0_PCH_V_PROC_IO

C2416

=PP1V05_S0_PCH_VCC_DMI

7

20 22

PLACE_NEAR=U1800.AM23:2.54mm

=PP1V05_S0_PCH_VCC_DMI

7

20 22

PLACE_NEAR=U1800.AW16:2.54mm

R2451

=PP1V05_S0_PCH_VCCADPLL

1

C2422

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2413

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=U1800.N27:2.54mm

1

C2417

4.7UF

20%

6.3V X5R 402

1

1 2

5% 1/16W MF-LF

402

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2419

1UF

20%

6.3V

2

X5R 0201

1

C2418

1UF

20%

6.3V

2

X5R 0201

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

R2460

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1800.BF40:2.54MM

R2465

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1800.BD40:2.54MM

1

C2430

2

1

C2402

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2465

0.1UF

10% 16V

2

X5R-CERM 0201

0.1UF

10% 16V X5R-CERM 0201

=PP1V8_S0_PCH_VCC_DFTERM

7

19 20

PLACE_NEAR=U1800.AJ13:2.54mm

PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

=PP3V3R1V5_S0_PCH_VCCSUSHDA

7

20 25

PLACE_NEAR=U1800.V31:2.54mm

=PP3V3_SUS_PCH_VCC_SPI

7

20

PLACE_NEAR=U1800.Y19:2.54mm

=PP3V3_S5_PCH_VCCDSW

7

20

PLACE_NEAR=U1800.R12:2.54mm

L2451

10UH-0.12A-0.36OHM

1 2

0603

PLACE_NEAR=U1800.V37:2.54mm

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C2461

1UF

20%

6.3V

2

X5R 0201

PCH VCCADPLLB Filter (PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C2466

1UF

20%

6.3V

2

X5R 0201

PP3V3_S0_PCH_VCC3_3_CLK_F

20

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

10UF

20%

6.3V

CERM-X5R

0402-1

PLACE_NEAR=U1800.V37:2.54mm

1

2

C2453

PLACE_NEAR=U1800.BF40:2.54MM

PLACE_NEAR=U1800.BD40:2.54MM

C2499

0.1UF

X5R-CERM

0201

68 mA

69 mA

10% 16V

1

2

1

C2441

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2442

1UF

20%

6.3V

2

X5R 0201

1

2

20

C2440

0.1UF

10% 16V X5R-CERM 0201

C2486

1UF

10% 10V X5R 402

1

2

=PP1V05_S0_PCH_VCCIO_SATA

7

16

1

C2444

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AB15:2.54mm

=PP1V05_S0_PCH_VCCSSC

7

20

PLACE_NEAR=U1800.AC35:2.54mm

=PP1V05_S0_PCH_VCCDIFFCLK

7

16 20

PLACE_NEAR=U1800.AC37:2.54mm

=PP1V05_S0_PCH_VCC_CORE

7

20

=PP1V05_S0_PCH_VCCIO

7

20 22

1

C2429

1UF

20%

6.3V

2

X5R 0201

=PP1V05_S0_PCH_VCCASW

7

20

1

2

1

C2452

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AG13:2.54mm

1

C2481

1UF

20%

6.3V

2

X5R 0201

1

C2414

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AR25:2.54mm PLACE_NEAR=U1800.AU25:2.54mm PLACE_NEAR=U1800.AU29:2.54mm PLACE_NEAR=U1800.AR29:2.54mm PLACE_NEAR=U1800.AU27:2.54mm

1

C2426

1UF

20%

6.3V X5R 0201

C2456

1UF

20%

6.3V

2

X5R 0201

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

(PCH USB 1.05V PWR)

7

20

1

C2475

1UF

20%

6.3V

2

X5R 0201

1

C2434

1UF

20%

6.3V

2

X5R 0201

1

C2482

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AB21:2.54mm PLACE_NEAR=U1800.AB21:2.54mm PLACE_NEAR=U1800.AB21:2.54mm PLACE_NEAR=U1800.AB21:2.54mm

1

C2407

1UF

20%

6.3V

2

X5R 0201

1

C2496

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm PLACE_NEAR=U1800.AB27:2.54mm

R

=PP3V3_SUS_PCH_VCCSUS_USB

PLACE_NEAR=U1800.U27:2.54mm

=PP3V3_SUS_PCH_VCCSUS

7

20 22

PLACE_NEAR=U1800.R33:2.54mm

=PP1V05_S0_PCH_VCCIO

7

20 22

PLACE_NEAR=U1800.AJ17:2.54mm

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)

1

C2483

1UF

20%

6.3V

2

X5R 0201

1

C2463

1UF

20%

6.3V

2

X5R 0201

C2428

X5R-CERM1

22UF

6.3V 0603

C2460

CERM-X5R

20%

PCH DECOUPLING

Apple Inc.

6 3

10UF

20%

6.3V

0402-2

C2401

CERM-X5R

1

C2420

2

X5R-CERM1

10UF

6.3V

0402-2

22UF

1

2

20%

12

20%

6.3V 0603

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

1

C2446

1UF

20%

6.3V

2

X5R 0201

1

C2476

1UF

20%

6.3V

2

X5R 0201

1

C2469

1UF

20%

6.3V

2

X5R 0201

1

2

1

2

SYNC_DATE=11/18/2011

051-9276

2.7.0

24 OF 109

22 OF 72

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

=PPVCCIO_S0_XDP

7

23

=PP3V3_S0_XDP

7

XDP_CPU_PREQ_L

10 65

BI

XDP_CPU_PRDY_L

10 65

D

(R2560-R2563)

XDP_CPU:BPM

0

10 65

IN

10 65

IN

10 65

IN

10 65

IN

9

65

IN

9

65

IN

9

65

IN

9

65

IN

10 19 65

IN

17 23 40

OUT

9

23 65

OUT

17 25 40

OUT

XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_PWRGD

PM_PWRBTN_L

CPU_CFG<0>

PLACE_NEAR=U1000.B46:2.54mm

PLACE_NEAR=U4900.J3:2.54mm

PLACE_NEAR=U1000.B50:2.54mm

PM_PCH_SYS_PWROK

R2560 R2561 R2562 R2563

PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM

R2564 R2565 R2566 R2567

R2500 R2502

R2501 R2504

1 2

0

1 2

0

1 2

0

1 2

(R2564-R2567)

XDP_CPU:CFG

0

1 2

0

1 2

0

1 2

0

1 2

XDP

1K

1 2

XDP

0

1 2

XDP

1K

1 2

XDP

330

1 2

1/16W 1/16W MF-LF

5%

1/16W MF-LF

5%

1/16W

5%

1/16W

5% 402 5%

1/16W MF-LF 1/16W MF-LF

5%

1/16W

5%

1/20W

1/16W MF-LF

MF-LF

MF 2015%

MF5%

4025% 402 402 402

402 402 402

201

4025%

C

XDP SIGNALS

XDP_DA0_USB_EXTA_OC_L

23

OUT

XDP_DA1_USB_EXTB_OC_L

23

OUT

XDP_DA2_USB_EXTC_OC_L

23

OUT

XDP_DA3_USB_EXTD_OC_L

23

OUT

XDP_DB0_USB_EXTB_OC_EHCI_L

23

OUT

XDP_DB1_USB_EXTD_OC_EHCI_L

23

OUT

XDP_DB2_AP_PWR_EN

23

IN

XDP_DB3_SDCONN_STATE_CHANGE

23

OUT

XDP_FC0

23

OUT

XDP_FC1

23

OUT

XDP_DC0_ISOLATE_CPU_MEM_L

23

IN

XDP_DC1_MXM_GOOD

23

IN

XDP_DC2_DP_AUXCH_ISOL

23

IN

XDP_DC3_SATARDRVR_EN

23

IN

XDP_DD0_DP_GPU_TBT_SEL

23

IN

XDP_DD1_JTAG_ISP_TCK

23

IN

XDP_DD2_AUD_IPHS_SWITCH_EN

23

IN

XDP_DD3_ENET_LOW_PWR

23

IN

B

PCH/XDP Signal Isolation Notes:

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3 doc id 404081. Initially, stuffing both 33 and 0 ohms and validate whether it is functional in that state, else add BOM options.

- For isolated GPIOs:

- ’Output’ non-XDP signals require pulls.

- ’Output’ PCH/XDP signals require pulls.

R252x, R253x, R257x and R259x should be placed where signal path needs to split between route from PCH to J2550 and path to non-XDP signal destination.

ALL_SYS_PWRGD

25 40 51 61

IN

17 23 40

OUT

PM_PWRBTN_L

PLACE_NEAR=J2550.40:2.54mm

PLACE_NEAR=U4900.J3:2.54mm

R2584

R2585

R2520 R2521 R2522 R2523

R2524 R2525 R2526 R2527 R2528

R2529 R2530

R2531 R2532 R2533 R2534 R2535

R2536 R2537

(R2520-R2537)

33 33 33 33

33 33 33 33 33

33 33

33 33 33 33 33

33 33

XDP

1K

1 2

XDP

0

1 2

XDP

1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

PCH SIGNALS

MF 2015%

1/20W 1/20W

MF5% MF 2015%

1/20W

MF 2015%

1/20W

1/20W 5% 5%

5%

1/20W

MF 2015% MF 201

1/20W

MF 201

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 201

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

MF 201

1/20W

MF 2015%

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

A

1/20W

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

23 43

16 23 68

IN

XDP_BPM_L<0>

10 65

IN

XDP_BPM_L<1>

10 65

IN

XDP_BPM_L<2>

10 65

IN

XDP_BPM_L<3>

10 65

IN

CPU_CFG<10>

9

65

IN

CPU_CFG<11>

9

65

IN

XDP_OBSDATA_B<0>

65

XDP_OBSDATA_B<1>

65

XDP_OBSDATA_B<2>

65

XDP_OBSDATA_B<3>

65

XDP_CPU_PWRGD XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0> XDP_VR_READY

=SMBUS_XDP_SDA

23 43

BI

=SMBUS_XDP_SCL

23 43

IN

XDP_CPU_TCK

10 23 65

OUT

R2581

1 2

201

1/20W

5% MF

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_FC0_PCH_GPIO15

XDP_FC1_PCH_GPIO0

XDP_DC1_PCH_GPIO35_MXM_GOOD

TP_XDP_PCH_OBSFN_A<0>

6

TP_XDP_PCH_OBSFN_A<1>

6

XDP_DA0_USB_EXTA_OC_L

23

XDP_DA1_USB_EXTB_OC_L

23

XDP_DA2_USB_EXTC_OC_L

23

XDP_DA3_USB_EXTD_OC_L

23

TP_XDP_PCH_OBSFN_B<0>

6

TP_XDP_PCH_OBSFN_B<1>

6

XDP_DB0_USB_EXTB_OC_EHCI_L

23

XDP_DB1_USB_EXTD_OC_EHCI_L

23

XDP_DB2_AP_PWR_EN

23

XDP_DB3_SDCONN_STATE_CHANGE

23

XDP_PCH_S5_PWRGD XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK2

6

TP_XDPPCH_HOOK3

6

=SMBUS_XDP_SDA

BI

=SMBUS_XDP_SCL

IN

XDP_PCH_TCK

OUT

R2580

1 2

201

NO STUFF

1K1K

R2540

1/16W MF-LF

5% MF

402

1

1K

5%

2

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

18 23

IN

18 23

IN

18

IN

18

IN

18

IN

18

IN

18 23

OUT

18

IN

19

IN

19 23

IN

19 23

OUT

19

OUT

16 23

OUT

8

16

OUT

19

OUT

19 23

OUT

19 23

OUT

8

19

OUT

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

OBSFN_A1

OBSFN_B0 OBSFN_B1

HOOK1

HOOK2 HOOK3

TCK1 TCK0

C2500

0.1uF

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

OBSFN_A1

OBSFN_B0 OBSFN_B1

HOOK1

HOOK2 HOOK3

TCK1 TCK0

C2580

0.1uF

CPU Micro2-XDP

CRITICAL XDP_CONN

J2500

DF40RC-60DP-0.4V

M-ST-SM1

62

2 4 6

10

20

30

40

SDA SCL

50

NC

XDP

10% 16V X5R 402

1

2

60

518S0847

PCH Micro2-XDP

CRITICAL XDP_CONN

J2550

DF40RC-60DP-0.4V

M-ST-SM1

62

2 4 6

10

20

30

40

SDA SCL

XDP

10% 16V X5R 402

1

2

50

NC

60

518S0847

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

61

1 3 5 78 9 1112 1314 1516 1718 19 2122 2324 2526 2728 29 3132 3334 3536 3738 39 4142 4344 4546 4748 49 5152 5354 5556 5758 59

6364

OBSFN_C0OBSFN_A0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3OBSDATA_A3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page TDO TRSTn TDI TMS XDP_PRESENT# XDP

1

C2501

0.1uF

10% 16V

2

X5R 402

CPU_CFG<16> CPU_CFG<17>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_CPU_CLK100M_P

65

XDP_CPU_CLK100M_N

65

XDP_CPURST_L

65

XDP_DBRESET_L

XDP_CPU_TDO XDP_CPU_TRST_L XDP_CPU_TDI XDP_CPU_TMS

IN IN

OUT

IN OUT OUT OUT

9

23 65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

10 23 25 65

10 23 65

R2515 R2516

R2505

PCH SIGNALS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

18 23 38

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

18 23

IN

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

18 23

OUT

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

19 23

OUT

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

16 23

IN

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

19 23

OUT

=PP3V3_S5_XDP

61

1 3 5 78 9 1112 1314 1516 1718 19 2122 2324 2526 2728 29 3132 3334 3536 3738 39 4142 4344 4546 4748 49 5152 5354 5556 5758 59

6364

OBSFN_C0OBSFN_A0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page TDO TRSTn TDI TMS XDP_PRESENT# XDP

1

C2581

0.1uF

10% 16V

2

X5R 402

7

XDP_FC0 XDP_FC1

XDP_DC0_ISOLATE_CPU_MEM_L XDP_DC1_MXM_GOOD

XDP_DC2_DP_AUXCH_ISOL XDP_DC3_SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1>

XDP_DD0_DP_GPU_TBT_SEL XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_EN XDP_DD3_ENET_LOW_PWR

TP_XDP_PCH_HOOK4 TP_XDP_PCH_HOOK5

XDPPCH_PLTRST_L XDP_DBRESET_L

XDP_PCH_TDO TP_XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

XDP_FC1_PCH_GPIO0

23

6

23

6

25

IN

10 23 25 65

OUT

16 23 68

IN

16 23 68

OUT

16 23 68

OUT

0

1K

R2590 R2596 R2592 R2570 R2572

10 23 65

1 2

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

PLACE_NEAR=R1841.1:2.54mm

XDP

ITPXDP_CLK100M_P

1/20W

PLACE_NEAR=R1840.1:2.54mm

XDP

ITPXDP_CLK100M_N

1/20W

XDP

PLACE_NEAR=U1000.D44:2.54mm

CPU_RESET_L

1/20W

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

R2574

XDP_PCH_TDO

16 23 68

XDP_PCH_TDI

16 23 68

XDP_PCH_TMS

16 23 68

XDP_PCH_TCK

16 23 68

0 0

1 2

R2575 R2576

R2510

R2511

R2512 R2513

R2514

MF 2015%

5% MF

5% 201MF

1 2

5% MF1K201

1K series R on PCH Support Page

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

5% 201MF

R2550

R2551

R2552 R2556

51

2 1

51

16 65

IN

16 65

IN

10 25

IN

Non-XDP Signals

1/20W

201

MF5%

201

MF5% 201

2015% MF

MF 2015%

1/20W

AUD_IPHS_SWITCH_EN_PCH

1/20W

TBT_CIO_PLUG_EVENT_ISOL

51

CPU & PCH XDP

Apple Inc.

R

6 3

=PPVCCIO_S0_XDP

7

23

XDP

PLACE_NEAR=J2500.52:2.54mm

1/16W MF-LF

5%

XDP

PLACE_NEAR=U1000.K61:2.54mm

2 1

XDP

2 1

XDP

2 1

XDP

2 1

1/20W

PLACE_NEAR=U1000.H59:2.54mm

1/20W

PLACE_NEAR=U1000.J58:2.54mm

1/20W

PLACE_NEAR=U1000.H63:2.54mm

1/20W

USB_EXTA_OC_L

AP_PWR_EN

USB_EXTB_OC_L

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

JTAG_ISP_TCK

=PP1V05_SUS_PCH_JTAG

7

XDP

PLACE_NEAR=J2550.51:2.54mm

2 1

XDP

2 1

XDP

2 1

XDP

2 1

1/20W

PLACE_NEAR=U1800.U12:2.54mm

1/20W

PLACE_NEAR=U1800.M15:2.54mm

1/20W

PLACE_NEAR=U1800.M17:2.54mm

1/20W

402

MF 2015%

IN

18 36 61

OUT

6

39

IN

26

OUT

16 25

OUT

19 19 23

OUTOUT

19 25

OUT

19 19 23

OUTOUT

MF 2015%

SYNC_DATE=08/04/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

25 OF 109

SHEET

23 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

BOM GROUP

C2602

4.7UF

X5R-CERM1

C2607

4.7UF

X5R-CERM1

1

2

20%

6.3V

402

20%

6.3V

402

CRITICAL

C2620

6.0PF

+/-0.1PF 25V NP0-C0G-CERM 201

1

2

1

2

BYPASS=U2600.5::5mm

BYPASS=U2600.23::5mm

BYPASS=U2600.34::2mm

1

C2603

10% 16V

2

X5R-CERM

0201

BYPASS=U2600.29::2mm

1

C2608

0.1UF

10% 16V

2

X5R-CERM

0201

R2605

100

1 2

5%

1/20W

MF 201

C2611

C2609

24

USB_HUB1_NONREM0

USB_HUB1_NONREM1

USB_HUB1_CFG_SEL0

USB_HUB1_CFG_SEL1

1

R2606

10K

5% 1/20W MF 201

2

1

2

BYPASS=U2600.23::2mm

1

0.1UF0.1UF

10% 16V

2

X5R-CERM

0201

BYPASS=U2600.5::2mm

1

0.1UF

10% 16V

2

X5R-CERM

0201

USB_HUB1_TEST

USB_HUB_RESET_L

USB_HUB1_XTAL1 USB_HUB1_XTAL2

R2607

10K

5% 1/20W MF 201

BYPASS=U2600.15::2mm

1

C2612

0.1UF

10% 16V

2

X5R-CERM

0201

BYPASS=U2600.10::2mm

1

C2610

0.1UF

10% 16V

2

X5R-CERM

0201

510152329

OMIT_TABLE

11

TEST

26

RESET*

33

XTALIN/CLKIN

32

XTALOUT

28

SUSP_IND/LOCAL_PWR/NON_REM0

22

SDA/SMBDATA/NON_REM1

24

SCL/SMBCLK/CFG_SEL0

25

HS_IND/CFG_SEL1

VDD33

SYM VER 1

U2600

USB2513B

CRITICAL

THRM_PAD

PPUSB_HUB1_CRFILT

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB1_PLLFILT

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

14

34

36

CRFILT

PLLFILT

QFN

USBDM_DN1/PRT_DIS_M1 USBDP_DN1/PRT_DIS_P1

USBDM_DN2/PRT_DIS_M2 USBDP_DN2/PRT_DIS_P2

USBDM_DN3/PRT_DIS_M3 USBDP_DN3/PRT_DIS_P3

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2* PRTPWR3/BC_EN3*

37

VOLTAGE=1.8V

IPU IPU IPU IPU

OCS1* OCS2* OSC3*

RBIAS

VBUS_DET

USBDM_UP USBDP_UP

1 2

3 4

6 7

8

NC

9

NC

12

TP_USB_HUB1_PRTPWR1

16

NC_USB_HUB1_PRTPWR2

18

NC_USB_HUB1_PRTPWR3

20

NC_USB_HUB1_PRTPWR4

NC

13 17 19 21

NC_USB_HUB1_OCS4

NC

35

27

30 31

1

C2615

0.1UF

10% 16V

2

X5R-CERM 0201

USB_BT_N USB_BT_P

USB_TPAD_HUB_N USB_TPAD_HUB_P

USB_SMC_N USB_SMC_P

USB_SDCARD_N USB_SDCARD_P

TP_USB_HUB1_OCS1 NC_USB_HUB1_OCS2

NC_USB_HUB1_OCS3

USB_HUB1_RBIAS

USB_HUB1_VBUS_DET

USB_HUB_UP_N USB_HUB_UP_P

1

C2616

1UF

2

BI BI

20%

6.3V X5R 0201

BI BI

36 67

24 67

24 40 67

8

67

8

67

18 67

1

C2617

0.1UF

10% 16V

2

X5R-CERM 0201

BlueTooth

Trackpad/Keyboard

SMC Port

SDCARD(NA to J11)

CRITICAL

1

R2600

12K

1% 1/20W MF 201

2

=PP3V3_S3_USB_HUB

7 8

24

D

CRITICAL

Y2600

2.50X2.00MM-SM

24.000MHZ-50PPM-6PF

CRITICAL

C2619

6.0PF

+/-0.1PF

25V

NP0-C0G-CERM

201

1/20W

10K

HUB_NONREM0_1

1

R2603

10K

5%

5% 1/20W MF

MF

201

2

HUB_NONREM0_0

1

R2604

10K

5%

1/20W MF

MF

201

2

HUB_NONREM1_1

R2601

HUB_NONREM1_0

R2602

C

1 3

1

2

2 4

NC

R2630

1M

1 2

5%

1/20W

MF

201

CRITICAL

NC

HUB_ALLREM

HUB_1NONREM

HUB_2NONREM

HUB_3NONREM

1

C2618

1UF

20%

6.3V

2

X5R 0201

=PP3V3_S3_USB_HUB

1

R2620

10K

5% 1/20W MF 201

2

PART#

338S0983

338S0923

7 8

24

TO PCH XHCI

NON_REM1 NON_REM0 DESCRIPTION

0 0 All ports are removable 0 1 Port 1 is non removable 1 0 Port 1 and 2 are non removable 1 1 Port 1, 2, and 3 are non removable

BOM TABLE

DESCRIPTION

QTY

1

IC,USB2512B,USB 2.0 HUB CNTRL,36-QFN

IC,USB2513B,USB 2.0,HUB CNTRL,3PRT,36QFN

1

USB_SMC_P

24 40 67

USB_SMC_N

24 40 67

TO CONNECT TP/KB TO PCH XHCI NOSTUFF R2611 & R2615, STUFF R2621,R2622,R2616 & R2617

USB_EXTD_XHCI_N

18 67

BI

USB_EXTD_XHCI_P

18 67

BI

BOM OPTIONS

HUB_NONREM1_0,HUB_NONREM0_0

HUB_NONREM1_0,HUB_NONREM0_1

HUB_NONREM1_1,HUB_NONREM0_0

HUB_NONREM1_1,HUB_NONREM0_1

REFERENCE DESIGNATOR(S)

U2600

TPAD_PCH:YES

R2621

0

1 2

5%

1/20W

MF

201

CRITICAL BOM OPTION

CRITICAL

NOSTUFF

1

R2618

10K

5% 1/20W MF 201

2

TPAD_PCH:YES

R2622

0

1 2

5%

1/20W

MF

201

USBHUB2512B

USBHUB2513B

=PP3V3_S3_USB_HUB

NOSTUFF

1

R2619

10K

5% 1/20W MF 201

2

12

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

TABLE_5_HEAD

TABLE_5_ITEM

7 8

24

C

=PP3V3_S3_USB_HUB

7 8

24

TPAD_PCH:YES

1

R2616

10K

B

5% 1/20W MF 201

2

USB XHCI/EHCI2 PORT MUX FOR EXT B

USB_TPAD_HUB_P

24 67

=PP3V3_S3_USBMUX

PCH PORT 9 (EHCI2)

PCH PORT 1 (XHCI)

7

1

18 67

BI

18 67

BI

18 67

BI

18 67

BI

USB_EXTB_EHCI_P USB_EXTB_EHCI_N

USB_EXTB_XHCI_P USB_EXTB_XHCI_N

C2663

0.1UF

X5R-CERM

10% 16V

2

0201

5 4

7 6

8

M+ M-

PI3USB102ZLE D+ D-

9

VCC

U2660

TQFN

CRITICAL

GND

3

TO LIO CONNECTOR

1

Y+

2

Y-

10

SELOE*

USB_EXTB_P USB_EXTB_N

6

39 67

BI BI

6

39 67

LIO External D

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

USB_EXTB_SEL_XHCI

SEL=0 CHOOSE USB EHCI2 PORT SEL=1 CHOOSE USB XHCI PORT

16

IN

TO USB HUB

PCH GPIO60

A

BI

USB_TPAD_HUB_N

24 67

BI

=PP3V3_S3_USB_RESET

7

C2604

0.1UF

X5R-CERM

PLACE_NEAR=U2600.26:2.5MM

10% 16V

0201

1

R2612

10K

5% 1/20W MF 201

2

USB_HUB_RESET_L

1

2

6 3

TPAD_PCH:YES

1

R2617

10K

5% 1/20W MF 201

2

TPAD_PCH:NO

R2611

0

TPAD_PCH:NO

R2615

0

1 2

5%

1/20W

MF

201

24

1 2

5%

1/20W

MF

201

SYNC_MASTER=J13_MLB

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

USB_TPAD_R_P

USB_TPAD_R_N

SYNC_DATE=08/12/2011

USB HUB & MUX

Apple Inc.

48 67

BI

TO TP/KB

48 67

BI

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

26 OF 109

SHEET

24 OF 72

124578

SIZE

B

A

D

8 7 6 5 4 3

12

D

C

B

GreenClk 25MHz Power Powered in S0

SB XTAL Power TBT XTAL Power

=PP3V3_S5_PCHPWRGD

7

25

=PP3V3_S0_SB_PM

7

25

23 40 51 61

IN

56

IN

=PP3V3_S0_SYSCLKGEN

7

=PPVDDIO_S0_SBCLK

7

=PPVDDIO_TBT_CLK

7

C2705

12PF

12

5%

25V

NP0-C0G

NC

201

2 4

NC

C2706

12PF

1 2

5%

25V

NP0-C0G

201

PCH S0 PWRGD

R2750

1K

1/20W

201

ALL_SYS_PWRGD

CPUIMVP_PGOOD

PLACE_NEAR=U1800.P12:7mm

System RTC Power Source & 32kHz / 25MHz Clock Generator

=PPVBAT_G3H_SYSCLK

7

Coin-Cell: VBAT (300-ohm & 10uF RC)

No Coin-Cell: 3.42V G3Hot (no RC)

=PP3V3_S5_SYSCLK

7

Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5

C2724

0.1UF

X5R-CERM

0201

SYSCLK_CLK25M_X2

68

1 3

CRITICAL

Y2705

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

NOTE: 30 PPM crystal required

1

5%

MF

2

5

1

U2750

2

3

SMC_DELAYED_PWRGD

35 40 41

10%

16V

1

2

1

C2750

0.1UF

2

MC74VHC1G08

SC70-HF

4

10% 16V X5R-CERM 0201

C2722

0.1UF

X5R-CERM

R2705

0

1 2

5%

1/20W

MF

201

PM_S0_PGOOD

No Coin-Cell: 3.3V S5

1

10%

16V

2

0201

SYSCLK_CLK25M_X2_R

68

NO STUFF

1

R2706

1M

5% 1/20W MF 201

2

SYSCLK_CLK25M_X1

68

Ground VDDIO of unused CLK outputs for power savings

1

U2760

2

5

MC74VHC1G08

SC70-HF

3

No bypass necessary

1

C2702

1UF

20%

6.3V

2

X5R 0201

NO STUFF

R2763

0

1 2

5%

1/20W

MF

201

=PP3V3_S5_PCHPWRGD

1

C2760

0.1UF

10% 16V

2

X5R-CERM 0201

4

SYS_PWROK_R

R2760

0

1 2

5%

1/20W

MF

201

11

14

7

R2762

3.0K

1 2

5%

1/20W

MF

201

VDDIO_25M_A

6

VDDIO_25M_B VDDIO_25M_C

3

X2

4

X1

25

5

VDD_25M

U2700

SLG3NB148A

TQFN

CRITICAL

GND

7

10

PLACE_NEAR=U1800.M10:5.54mm

NO STUFF

1

R2761

0

5% 1/20W MF 201

2

13

+3.42V

+V3.3A

32KHZ_A

25MHZ_A 25MHZ_B 25MHZ_C

VDD_RTC_OUT

THRM

PAD

16

17

PM_PCH_SYS_PWROK

PM_PCH_PWROK

MAKE_BASE=TRUE

PM_PCH_APWROK

GPIO Glitch Prevention

VBAT and +V3.3A are

internally ORed to

create VDD_RTC_OUT.

+V3.3A should be first available ~3.3V power

to reduce VBAT draw.

12

SYSCLK_CLK32K_RTC

9

SYSCLK_CLK25M_SB

8

NC

15

SYSCLK_CLK25M_TBT =PPVRTC_G3_OUT

1

For SB RTC Power

1

C2710

1UF

20%

6.3V

2

X5R 0201

17 23 40

OUT

17 25

OUT

17

OUT

18 68

IN

18 68

IN

18 68

IN

7

PLACE_NEAR=U1800.G51:5.1mm

LPC_CLK33M_SMC_R

PLACE_NEAR=U1800.E49:5.1mm

LPC_CLK33M_LPCPLUS_R

PLACE_NEAR=U1800.G45:2.54MM:5.1mm

PCH_CLK33M_PCIOUT

16 68

OUT

16 68

OUT

33 68

OUT

R2727

1 2

1/20W

201

DP_AUXIO_EN Inversion

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 35

16 23

IN

DP_AUXCH_ISOL

R2730

CRITICAL

Q2730

SOD-VESM-HF

SSM3K15FV

1

R2731

10K

5% 1/20W MF 201

2

22

5%

MF

R2726

1 2

10K

1 2

5%

1/20W

MF

201

1

G S

NO STUFF

22

5%

1/20W

MF

201

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

R2729

22

1 2

5%

1/20W

MF

201

3

D

2

PCH_CLK33M_PCIIN

DP_AUXIO_EN

C2739

0.1UF

10% 16V

X5R-CERM

0201

Platform Reset Connections

Unbuffered

PLT_RESET_L

18 26

IN

40 68

OUT

6

42 68

OUT

16 68

OUT

Buffered

=PP3V3_S0_RSTBUF

7

25

1

C2771

0.1UF

10% 16V

2

X5R-CERM

0201

=PP3V3_S0_RSTBUF

7

25

2

1

C2780

0.1UF

10% 16V

2

X5R-CERM

0201

63

OUT

1

2

=PP3V3R1V5_S0_PCH_VCCSUSHDA

7

20 22

SPI_DESCRIPTOR_OVERRIDE_L

40

IN

CRITICAL

5

MC74VHC1G08

1

2

U2771

3

SC70-HF

4

PLT_RST_BUF_L

1

R2770

100K

5% 1/20W MF 201

2

Buffered

5

U2780

74LVC1G07

SC70

4

PLT_RST_CPU_BUF_L

NC

1

NC

MAKE_BASE=TRUE

1

R2780

3

100K

5% 1/20W MF 201

2

PCH ME Disable Strap

Q2720

SSM6N37FEAPE

SOT563

D

3

Q2720

SSM6N37FEAPE

R2781

33

1 2

5%

1/20W

MF

201

R2771

0

1 2

5%

1/20W

MF

201

1 2

R2793

1/20W

201

R2783

1 2

R2789

1 2

0

5%

MF

LPCPLUS_RESET_L

MAKE_BASE=TRUE

33

SSD_RESET_L

5%

1/20W

MF

201

PCA9557D_RESET_L

XDP

1K

XDPPCH_PLTRST_L

5%

1/20W

MF

201

AP_RESET_L

Scrub for Layout Optimization

R2772

0

SOT563

1 2

5%

1/20W

MF

R2773

201

0

1 2

MAKE_BASE=TRUE

5%

1/20W

MF

201

R2788

0

1 2

5%

1/20W

MF

201

VTT voltage divider on CPU page

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

2

SG

1

TBT_RESET_L

CPU_RESET_L

SMC_LRESET_L

BKLT_PLT_RST_L

=PP5V_S0_PCH

7

22

=TBT_RESET_L

1

R2721

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

IPD = 9-50k

OUT

10 23

OUT

1

R2720

100K

5% 1/20W MF 201

2

6

42 68

6

37

D

31

23

36

40

35

64

C

B

16 68

OUT

=PP3V3_S3_PCH_GPIO

7

18

CRITICAL

TBT_PWR_EN_PCH

16

IN

LPC_PWRDWN_L

6

17 40 42

A

IN

AUD_IPHS_SWITCH_EN_PCH

19 23

IN

PM_PCH_PWROK

17 25

IN

1

A1

2

B1

5

A2

6

B2

U2752

8

VCC

SOT833

08

GND

4

74LVC2G08GT

1

C2752

0.1UF

10% 16V

2

X5R-CERM 0201

7

Y1

Y2

TBT_PWR_EN

3

AUD_IPHS_SWITCH_EN

19 33

OUT

6

39

OUT

PCH Reset Button

=PP3V3_S0_SB_PM

7

25

XDP_DBRESET_L

XDP

R2796

0

1 2

1/20W

201

MF 5%

1

R2795

10K

5% 1/20W MF 201

2

6 3

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

PM_SYSRST_L

NO STUFF

1

R2797

0

5% 1/16W MF-LF 402

2

SILK_PART=SYS RESET

17 40 10 23 65

BIIN

SYNC_MASTER=J13_MLB

PAGE TITLE

Clock (CK505) and Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

27 OF 109

SHEET

25 OF 72

124578

SYNC_DATE=08/12/2011

SIZE

A

D

8 7 6 5 4 3

12

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

D

C

B

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

=PP3V3_S3_MEMRESET

7

ISOLATE_CPU_MEM_L

23 26

IN

=PP5V_S3_MEMRESET

7

26

NO STUFF

CPUMEM_SLG:NO

1

C2817

0.047UF

10% 16V

2

X7R 402

=MEM_RESET_L

10 26

IN

26

R2815

CPUMEM_SLG:NO

R2890

0

12

ISOLATE_CPU_MEM_L_R

5%

1/20W

MF

201

1

100K

5%

1/20W

MF

201

2

CPUMEM_SLG:NO

Q2815

SSM6N37FEAPE

SOT563

D

6

MEMRESET_ISOL_LS5V_L

31

MAKE_BASE=TRUE

2

S G

1

CPU_MEM_RESET_L

CPUMEM_SLG:NO

R2801

CPUMEM_SLG:NO

Q2800

SSM6N37FEAPE

SOT563

CPUMEM_SLG:NO

R2802

CPUMEM_SLG:NO

Q2800

SSM6N37FEAPE

SOT563

CPUMEM_SLG:NO

Q2815

SSM6N37FEAPE

5

S G

4

100K

5

100K

2

1/20W

SOT563

201

1

5% MF

2

D

SG

1

5% MF

2

D

SG

17 26 36 40 48 61

IN

CPUMEM_SLG:NO

SSM6N37FEAPE

P1V5CPU_EN_L

3

4

CPUMEM_SLG:NO

SSM6N37FEAPE

MEMVTT_EN_L

6

1

R2816

1K

5% 1/20W MF 201

2

D

MEM_RESET_L

3

PM_SLP_S4_L

Q2805

SOT563

2

3

4

Q2810

SOT563

2

3

4

=PP1V5_S3_MEMRESET

1

R2805

2

6

D

SG

1

CPUMEM_SLG:NO

D

Q2805

SSM6N37FEAPE

SOT563

5

S G

1

R2810

2

6

D

SG

1

D

Q2810

SSM6N37FEAPE

SOT563

5

S G

C2816

0.1UF

X5R-CERM

CPUMEM_SLG:NO

10K

5% 1/20W MF 201

P1V5CPU_EN

PM_SLP_S3_L

CPUMEM_SLG:NO

10K

5% 1/20W MF 201

MEMVTT_EN

CPUMEM_SLG:NO

PLT_RESET_L

1

10% 16V

2

0201

OUT

IN

OUT

IN

7

26 60

17 26 40 61

8

26

18 25 26

23 26

17 26 40 61

17 26 36 40 48 61

10 26

18 25 26

26 27 28 29 30

OUT

IN

=PP3V3_S3_MEMRESET

7

26

CPUMEM_SLG:YES

C2800

0.1UF

10%

6.3V X5R 201

PLT_RESET_L

ISOLATE_CPU_MEM_L

PM_SLP_S3_L PM_SLP_S4_L =MEM_RESET_L

1

2

S0_READY

1

9

ISOL*

3

S0_EN

6

S3_EN

7

RST_IN*

10

VDD

U2800

SLG4AP022

TQFN

THRM

GND

PAD

5

11

CPUMEM_SLG:YES

VDDIO_EN

RST_OUT*

=PP1V5_S3_CPU_VCCDDR

7

10 12 15

2

VTT_EN

MEMVTT_EN

4

P1V5CPU_EN

8

MEM_RESET_L

OUT

R2820

R2821

8

26

26 60

26 27 28 29 30

55

=PP3V3_S5_CPU_VCCDDR

7

1

27.4K

1%

1/20W

MF

201

2

P1V5_S0_DIV

1

43.2K

1%

1/20W

MF

201

2

=PP5V_S3_MEMRESET

7

26

SSM6N37FEAPE

=DDRVTT_EN

8

IN

NO STUFF

1V5 S0 "PGOOD" for CPU

1

R2822

10K

5% 1/20W MF 201

2

PM_MEM_PWRGD_L

3

CRITICAL

Q2820

5

DMB53D0UV

SOT-563

4

C2820

1000PF

10% 16V X7R 201

1

2

MEMVTT Clamp

Ensures CKE signals are held low in S3

1

5% MF

2

3

D

SG

4

SSM6N37FEAPE

VTTCLAMP_EN

NO STUFF

C2851

1000PF

R2851

Q2850

SOT563

100K

5

1/20W

201

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CRITICAL

G

2

=PPVTT_S0_VTTCLAMP

7

R2850

VTTCLAMP_L

6

Q2850

SOT563

10% 16V X7R 201

D

2

SG

1

2

PM_MEM_PWRGD

6 D

Q2820

DMB53D0UV

SOT-563

S 1

1

10

5% 1/10W MF-LF

603

2

75mA max load @ 0.75V

60mW max power

10 17 65

OUT

D

C

B

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 0 1

to

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1

A

5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

CPU Memory S3 Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

28 OF 109

SHEET

26 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

PP0V75_S3_MEM_VREFCA_A

27 28 31 66

PP0V75_S3_MEM_VREFDQ_A

27 28 31 66

1

C2900

0.47UF

20% CERM-X5R-1

2

201 4V

MEM_A_ODT<0>

11 27 28 32 66

MEM_A_ODT<1>

11 27 28 32 66

MEM_RESET_L

26 27 28 29 30

240

R2900

1 2

1%

1/20W

MF

201

MEM_A_A<0>

11 27 28 32 66

MEM_A_A<1>

11 27 28 32 66

MEM_A_A<2>

C

B

11 27 28 32 66

MEM_A_A<3>

11 27 28 32 66

MEM_A_A<4>

11 27 28 32 66

MEM_A_A<5>

11 27 28 32 66

MEM_A_A<6>

11 27 28 32 66

MEM_A_A<7>

11 27 28 32 66

MEM_A_A<8>

11 27 28 32 66

MEM_A_A<9>

11 27 28 32 66

MEM_A_A<10>

11 27 28 32 66

MEM_A_A<11>

11 27 28 32 66

MEM_A_A<12>

11 27 28 32 66

MEM_A_A<13>

11 27 28 32 66

MEM_A_A<14>

11 27 28 32 66

MEM_A_A<15>

11 27 28 32 66

MEM_A_BA<0>

11 27 28 32 66

MEM_A_BA<1>

11 27 28 32 66

MEM_A_BA<2>

11 27 28 32 66

MEM_A_CLK_P<0>

11 27 28 32 66

MEM_A_CLK_N<0>

11 27 28 32 66

MEM_A_CKE<0>

11 27 28 32 66

MEM_A_CKE<1>

11 27 28 32 66

MEM_A_CS_L<1>

11 27 28 32 66

MEM_A_CS_L<0>

11 27 28 32 66

MEM_A_RAS_L

11 27 28 32 66

MEM_A_CAS_L

11 27 28 32 66

MEM_A_WE_L

11 27 28 32 66

1

C2901

0.47UF

20% 20% CERM-X5R-1

2

201 4V

G1 F1

N2

H8

MEM_A_ZQ0

H9

MEM_A_ZQ4

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9 F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U2900

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_A

7

27 28 32

VDDQ

OMIT_TABLE

MT41K1G4

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5

N9

NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

NC

512MX8-4GBIT-DDR3-1600

N1

L9

C2902

0.47UF

CERM-X5R-1 201 4V

B3

MEM_A_DQ<7>

C7

MEM_A_DQ<1>

C2

MEM_A_DQ<0>

C8

MEM_A_DQ<3>

E3

MEM_A_DQ<4>

E8

MEM_A_DQ<2>

D2

MEM_A_DQ<5>

E7

MEM_A_DQ<6>

C3

MEM_A_DQS_P<0>

D3

MEM_A_DQS_N<0>

B7

A7

NC

A3

NC

79 80 81 82

1

2

11 66

27 28 31 66

PP0V75_S3_MEM_VREFDQ_A

27 28 31 66

C2910

0.47UF 0.47UF

20% CERM-X5R-1 201 4V

11 27 28 32 66

26 27 28 29 30

240

R2910

1 2

MF

1%

201

11 27 28 32 66

PP0V75_S3_MEM_VREFCA_A

1

2

MEM_A_ODT<0>

MEM_A_ODT<1>

11 27 28 32 66

MEM_RESET_L

1/20W

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_BA<0>

MEM_A_BA<1> MEM_A_BA<2>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CS_L<1> MEM_A_CS_L<0>

MEM_A_RAS_L

11 27 28 32 66

MEM_A_CAS_L

11 27 28 32 66

MEM_A_WE_L

11 27 28 32 66

C2911

20% CERM-X5R-1 201 4V

MEM_A_ZQ1

MEM_A_ZQ5

1

2

G1 F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9

F9

H1 H2

F3 G3 H3

7

27 28 32

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

VREFCA

U2910

FBGA-9P5X11P65-COMBO

ODT0 ODT1

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_A

VDDQ

OMIT_TABLE

MT41K1G4

NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DM/TDQS

NF_TDQS*

VSSQ

N1

N9

L9

B2B8C9D1D9

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

NC

C2912

0.47UF

20% CERM-X5R-1 201 4V

B3

MEM_A_DQ<8>

C7

MEM_A_DQ<14>

C2

MEM_A_DQ<9>

C8

MEM_A_DQ<12>

E3

MEM_A_DQ<10>

E8

MEM_A_DQ<11>

D2

MEM_A_DQ<13>

E7

MEM_A_DQ<15>

C3

MEM_A_DQS_P<1>

D3

MEM_A_DQS_N<1>

B7

A7

NC

A3

NC

79 80 81 82

PP0V75_S3_MEM_VREFCA_A

27 28 31 66

PP0V75_S3_MEM_VREFDQ_A

R2920

27 28 31 66

C2920

0.47UF

20% CERM-X5R-1 201 4V

11 27 28 32 66

26 27 28 29 30

240

1 2

1%MF201

11 27 28 32 66

1

2

MEM_A_ODT<0>

MEM_A_ODT<1>

11 27 28 32 66

MEM_RESET_L

1/20W

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1> MEM_A_BA<2>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<0> MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

1

C2921

0.47UF

20% CERM-X5R-1

2

201 4V

G1 F1

N2

H8

MEM_A_ZQ2

H9

MEM_A_ZQ6 MEM_A_ZQ7

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9 F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VREFDQ

ODT0 ODT1

VREFCA

U2920

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

1

2

11 66

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_A

7

27 28 32

VDD

VDDQ

OMIT_TABLE

MT41K1G4

NF_DQ4 NF_DQ5

N9

NF_DQ6 NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

512MX8-4GBIT-DDR3-1600

N1

L9

1

C2922

0.47UF

20% CERM-X5R-1

2

201 4V

R2930

B3

DQ0 DQ1 DQ2 DQ3

DQS

MEM_A_DQ<19>

C7

MEM_A_DQ<17>

C2

MEM_A_DQ<23>

C8

MEM_A_DQ<20>

E3

MEM_A_DQ<22>

E8

MEM_A_DQ<16>

D2

MEM_A_DQ<18>

E7

MEM_A_DQ<21>

C3

MEM_A_DQS_P<2>

D3

MEM_A_DQS_N<2>

11 66

B7

A7

NC NC

A3

NC

79

NC

80 81 82

PP0V75_S3_MEM_VREFCA_A

27 28 31 66

PP0V75_S3_MEM_VREFDQ_A

27 28 31 66

C2930

0.47UF

20% CERM-X5R-1 201 4V

MEM_A_ODT<0>

11 27 28 32 66

MEM_RESET_L

26 27 28 29 30

240

1 2

1%

MF

1/20W

201

MEM_A_A<0>

11 27 28 32 66

MEM_A_A<1>

11 27 28 32 66

MEM_A_A<2>

11 27 28 32 66

MEM_A_A<3>

11 27 28 32 66

MEM_A_A<4>

11 27 28 32 66

MEM_A_A<5>

11 27 28 32 66

MEM_A_A<6>

11 27 28 32 66

MEM_A_A<7>

11 27 28 32 66

MEM_A_A<8>

11 27 28 32 66

MEM_A_A<9>

11 27 28 32 66

MEM_A_A<10>

11 27 28 32 66

MEM_A_A<11>

11 27 28 32 66

MEM_A_A<12>

11 27 28 32 66

MEM_A_A<13>

11 27 28 32 66

MEM_A_A<14>

11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

MEM_A_BA<0>

11 27 28 32 66

MEM_A_BA<1>

11 27 28 32 66

MEM_A_BA<2>

11 27 28 32 66

MEM_A_CLK_P<0>

11 27 28 32 66

MEM_A_CLK_N<0>

11 27 28 32 66

MEM_A_CKE<0>

11 27 28 32 66

MEM_A_CKE<1>

11 27 28 32 66

MEM_A_CS_L<1>

11 27 28 32 66

MEM_A_CS_L<0>

11 27 28 32 66

MEM_A_RAS_L

11 27 28 32 66

MEM_A_CAS_L

11 27 28 32 66

MEM_A_WE_L

11 27 28 32 66

1

C2931

0.47UF

20% CERM-X5R-1

2

201 4V

MEM_A_ODT<1>

MEM_A_ZQ3

MEM_A_A<15>MEM_A_A<15>

1

2

G1

F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7

G7

G9

F9

H1 H2

F3 G3 H3

=PP1V5_S3_MEM_A

7

27 28 32

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U2930

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

OMIT_TABLE

MT41K1G4

N1

N9

L9

VDDQ

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

NC

C2932

0.47UF

20% CERM-X5R-1 201 4V

B3

MEM_A_DQ<28>

C7

MEM_A_DQ<25>

C2

MEM_A_DQ<27>

C8

MEM_A_DQ<26>

E3

MEM_A_DQ<29>

E8

MEM_A_DQ<24>

D2

MEM_A_DQ<30>

E7

MEM_A_DQ<31>

C3

MEM_A_DQS_P<3>

D3

MEM_A_DQS_N<3>

B7

A7

A3

NC

79 80 81 82

1

2

11 66

D

C

B

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

240

R2901

1 2

MF

201

R2911

1 2

MF

201

A

R2921

R2931

1 2

MF

201

1 2

MF

201

MEM_A_ZQ4

MEM_A_ZQ5

MEM_A_ZQ6

MEM_A_ZQ7

27

SIZE

A

D

SYNC_MASTER=J13_MLB

27

PAGE TITLE

DDR3 DRAM CHANNEL A (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=08/29/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

29 OF 109

SHEET

27 OF 72

124578

1%

1/20W

240

1%

1/20W

240

1%

1/20W

240

1%

1/20W

8 7 6 5 4 3

12

D

PP0V75_S3_MEM_VREFCA_A

27 28 31 66

PP0V75_S3_MEM_VREFDQ_A

27 28 31 66

1

C3000

0.47UF

20%

CERM-X5R-1

201 4V

MEM_A_ODT<0>

11 27 28 32 66

MEM_A_ODT<1>

11 27 28 32 66

MEM_RESET_L

26 27 28 29 30

240

R3000

1 2

1/20W

1%

MF

201

MEM_A_A<0>

C

B

11 27 28 32 66

MEM_A_A<1>

11 27 28 32 66

MEM_A_A<2>

11 27 28 32 66

MEM_A_A<3>

11 27 28 32 66

MEM_A_A<4>

11 27 28 32 66

MEM_A_A<5>

11 27 28 32 66

MEM_A_A<6>

11 27 28 32 66

MEM_A_A<7>

11 27 28 32 66

MEM_A_A<8>

11 27 28 32 66

MEM_A_A<9>

11 27 28 32 66

MEM_A_A<10>

11 27 28 32 66

MEM_A_A<11>

11 27 28 32 66

MEM_A_A<12>

11 27 28 32 66

MEM_A_A<13>

11 27 28 32 66

MEM_A_A<14>

11 27 28 32 66

MEM_A_A<15>

11 27 28 32 66

MEM_A_BA<0>

11 27 28 32 66

MEM_A_BA<1>

11 27 28 32 66

MEM_A_BA<2>

11 27 28 32 66

MEM_A_CLK_P<0>

11 27 28 32 66

MEM_A_CLK_N<0>

11 27 28 32 66

MEM_A_CKE<0>

11 27 28 32 66

MEM_A_CKE<1>

11 27 28 32 66

MEM_A_CS_L<1>

11 27 28 32 66

MEM_A_CS_L<0>

11 27 28 32 66

MEM_A_RAS_L

11 27 28 32 66

MEM_A_CAS_L

11 27 28 32 66

MEM_A_WE_L

11 27 28 32 66

1

C3001

0.47UF

20% 20%

CERM-X5R-1

2

201 4V

G1 F1

N2

H8

MEM_A_ZQ8

H9

MEM_A_ZQ12

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9 F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U3000

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_A

7

27 28 32

VDDQ

OMIT_TABLE

MT41K1G4

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5

N9

NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

NC

512MX8-4GBIT-DDR3-1600

N1

L9

1

C3002

0.47UF

CERM-X5R-1

2

201 201 4V

R3010

B3

MEM_A_DQ<39>

C7

MEM_A_DQ<33>

C2

MEM_A_DQ<34>

C8

MEM_A_DQ<35>

E3

MEM_A_DQ<36>

E8

MEM_A_DQ<37>

D2

MEM_A_DQ<38>

E7

MEM_A_DQ<32>

C3

MEM_A_DQS_P<4>

D3

MEM_A_DQS_N<4>

11 66

B7

A7

NC

A3

NC

79 80 81 82

27 28 31 66

C3010

0.47UF

CERM-X5R-1

4V

26 27 28 29 30

240

1 2

1%

MF

201

11 27 28 32 66

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

1

C3011

0.47UF

20%

CERM-X5R-1

2

201 4V

MEM_A_ODT<0>

11 27 28 32 66

MEM_A_ODT<1>

11 27 28 32 66

MEM_RESET_L

MEM_A_ZQ9

MEM_A_ZQ13

1/20W

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<15> MEM_A_BA<0> MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<0>

11 27 28 32 66

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

11 27 28 32 66

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

1

2

G1 F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9

F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

VREFCA

U3010

FBGA-9P5X11P65-COMBO

ODT0 ODT1

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_A

7

27 28 32

OMIT_TABLE

MT41K1G4

N1

N9

L9

VDDQ

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

NC

VSSQ

B2B8C9D1D9

1

C3012

0.47UF

20%

CERM-X5R-1

2

201 201 4V

R3020

1 2

B3

MEM_A_DQ<41>

C7

MEM_A_DQ<46>

C2

MEM_A_DQ<44>

C8

MEM_A_DQ<45>

E3

MEM_A_DQ<43>

E8

MEM_A_DQ<40>

D2

MEM_A_DQ<47>

E7

MEM_A_DQ<42>

C3

MEM_A_DQS_P<5>

D3

MEM_A_DQS_N<5>

11 66

MF

201

B7

A7

NC

A3

NC

79 80 81 82

PP0V75_S3_MEM_VREFCA_A

27 28 31 66

PP0V75_S3_MEM_VREFDQ_A

27 28 31 66

C3020

0.47UF

20%

CERM-X5R-1

4V

MEM_A_ODT<0>

11 27 28 32 66

MEM_A_ODT<1>

11 27 28 32 66

MEM_RESET_L

26 27 28 29 30

240

1/20W

1%

MEM_A_A<0>

11 27 28 32 66

MEM_A_A<1>

11 27 28 32 66

MEM_A_A<2>

11 27 28 32 66

MEM_A_A<4>

11 27 28 32 66

MEM_A_A<5>

11 27 28 32 66

MEM_A_A<6>

11 27 28 32 66

MEM_A_A<7>

11 27 28 32 66

MEM_A_A<8>

11 27 28 32 66

MEM_A_A<9>

11 27 28 32 66

MEM_A_A<10>

11 27 28 32 66

MEM_A_A<11>

11 27 28 32 66

MEM_A_A<12>

11 27 28 32 66

MEM_A_A<13>

11 27 28 32 66

MEM_A_A<14>

11 27 28 32 66

MEM_A_A<15>

11 27 28 32 66

MEM_A_BA<0>

11 27 28 32 66

MEM_A_BA<1>

11 27 28 32 66

MEM_A_BA<2>

11 27 28 32 66

MEM_A_CLK_P<0>

11 27 28 32 66

MEM_A_CLK_N<0>

11 27 28 32 66

MEM_A_CKE<0>

11 27 28 32 66

MEM_A_CKE<1>

11 27 28 32 66

MEM_A_CS_L<1>

11 27 28 32 66

MEM_A_CS_L<0>

11 27 28 32 66

MEM_A_RAS_L

11 27 28 32 66

MEM_A_CAS_L

11 27 28 32 66

MEM_A_WE_L

11 27 28 32 66

1

2

MEM_A_ZQ10 MEM_A_ZQ14

C3021

0.47UF

CERM-X5R-1

201 4V

PP0V75_S3_MEM_VREFCA_A

27 28 31 66

=PP1V5_S3_MEM_A

7

1

20%

2

G1 F1

N2

H8 H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9 F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VREFDQ

VREFCA

FBGA-9P5X11P65-COMBO

ODT0 ODT1

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

VSS

A1

A8

B1D8F2F8J1J9L1

27 28 32

VDD

U3020

VDDQ

OMIT_TABLE

MT41K1G4

NF_DQ4 NF_DQ5

N9

NF_DQ6 NF_DQ7

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

512MX8-4GBIT-DDR3-1600

N1

L9

1

C3022

0.47UF

20%

CERM-X5R-1

2

201 4V

R3030

B3

MEM_A_DQ<50>

DQS*

DQ0 DQ1 DQ2 DQ3

DQS

C7

MEM_A_DQ<49>

C2

MEM_A_DQ<55>

C8

MEM_A_DQ<51>

E3

MEM_A_DQ<48>

E8

MEM_A_DQ<53>

D2

MEM_A_DQ<54>

E7

MEM_A_DQ<52>

C3

MEM_A_DQS_P<6>

D3

MEM_A_DQS_N<6>

11 66

B7

A7

NC

NC NC

A3

NC

79

NC

80 81 82

27 28 31 66

C3030

0.47UF

CERM-X5R-1

201 4V

11 27 28 32 66

26 27 28 29 30

240

1 2

MF

1%

201

11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66

PP0V75_S3_MEM_VREFDQ_A

1

C3031

0.47UF

20%

CERM-X5R-1

2

201 4V

MEM_A_ODT<0>

MEM_A_ODT<1>

11 27 28 32 66

MEM_RESET_L

MEM_A_ZQ11 MEM_A_ZQ15

1/20W

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3>MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6>

MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<0> MEM_A_CKE<1>

MEM_A_CS_L<1> MEM_A_CS_L<0>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

1

2

G1

F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7

G7

G9

F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U3030

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_A

7

27 28 32

OMIT_TABLE

MT41K1G4

N1

N9

L9

VDDQ

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

NC

C3032

0.47UF

20%

CERM-X5R-1

201 4V

B3

MEM_A_DQ<59>

C7

MEM_A_DQ<57>

C2

MEM_A_DQ<63>

C8

MEM_A_DQ<56>

E3

MEM_A_DQ<58>

E8

MEM_A_DQ<61>

D2

MEM_A_DQ<62>

E7

MEM_A_DQ<60>

C3

MEM_A_DQS_P<7>

D3

MEM_A_DQS_N<7>

B7

A7

NC

A3

NC

79 80 81 82

1

2

11 66

D

C

B

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

240

R3001

201

R3011

201

A

R3021

201

R3031

2011%1/20W

1 2

1%

MF

240

1 2

1%

MF

240

1 2

1%

MF

240

1 2

MF

1/20W

MEM_A_ZQ12

MEM_A_ZQ13

MEM_A_ZQ14

MEM_A_ZQ15

28

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

DDR3 DRAM CHANNEL A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=08/29/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

30 OF 109

SHEET

28 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

PP0V75_S3_MEM_VREFCA_B

29 30 31

PP0V75_S3_MEM_VREFDQ_B

29 30 31

1

C3101

0.47UF

CERM-X5R-1

2

MEM_B_ZQ0

MEM_B_ZQ4

1

20%

2

201 4V

G1 F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9

F9

H1 H2

F3 G3 H3

C3100

0.47UF

20%

CERM-X5R-1

201 4V

MEM_B_ODT<0>

11 29 30 32 66

MEM_B_ODT<1>

11 29 30 32 66

MEM_RESET_L

26 27 28 29 30

240

R3100

1 2

201MF1%

1/20W

MEM_B_A<0>

C

B

11 29 30 32 66

MEM_B_A<1>

11 29 30 32 66

MEM_B_A<2>

11 29 30 32 66

MEM_B_A<3>

11 29 30 32 66

MEM_B_A<4>

11 29 30 32 66

MEM_B_A<5>

11 29 30 32 66

MEM_B_A<6>

11 29 30 32 66

MEM_B_A<7>

11 29 30 32 66

MEM_B_A<8>

11 29 30 32 66

MEM_B_A<9>

11 29 30 32 66

MEM_B_A<10>

11 29 30 32 66

MEM_B_A<11>

11 29 30 32 66

MEM_B_A<12>

11 29 30 32 66

MEM_B_A<13>

11 29 30 32 66

MEM_B_A<14>

11 29 30 32 66

MEM_B_A<15>

11 29 30 32 66

MEM_B_BA<0>

11 29 30 32 66

MEM_B_BA<1>

11 29 30 32 66

MEM_B_BA<2>

11 29 30 32 66

MEM_B_CLK_P<0>

11 29 30 32 66

MEM_B_CLK_N<0>

11 29 30 32 66

MEM_B_CKE<0>

11 29 30 32 66

MEM_B_CKE<1>

11 29 30 32 66

MEM_B_CS_L<1>

11 29 30 32 66

MEM_B_CS_L<0>

11 29 30 32 66

MEM_B_RAS_L

11 29 30 32 66

MEM_B_CAS_L

11 29 30 32 66

MEM_B_WE_L

11 29 30 32 66

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U3100

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

29 30 32

OMIT_TABLE

MT41K1G4

N1

N9

L9

=PP1V5_S3_MEM_B

7

VDDQ

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

NC

VSSQ

B2B8C9D1D9

C3102

0.47UF

20%

CERM-X5R-1

201 4V

B3

MEM_B_DQ<1>

C7

MEM_B_DQ<4>

C2

MEM_B_DQ<2>

C8

MEM_B_DQ<3>

E3

MEM_B_DQ<0>

E8

MEM_B_DQ<5>

D2

MEM_B_DQ<6>

E7

MEM_B_DQ<7>

C3

MEM_B_DQS_P<0>

D3

MEM_B_DQS_N<0>

B7

A7

NC

A3

NC

79 80 81 82

1

2

R3110

11 66

29 30 31

C3110

0.47UF

CERM-X5R-1

240

1 2

MF

1%

201

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B

1

C3111

0.47UF

20%

CERM-X5R-1

2

201

4V

MEM_B_ODT<0>

11 29 30 32 66

MEM_B_ODT<1>

11 29 30 32 66

MEM_RESET_L

26 27 28 29 30

MEM_B_ZQ1

MEM_B_ZQ5

1/20W

MEM_B_A<0>

11 29 30 32 66

MEM_B_A<1>

11 29 30 32 66

MEM_B_A<2>

11 29 30 32 66

MEM_B_A<3>

11 29 30 32 66

MEM_B_A<4>

11 29 30 32 66

MEM_B_A<5>

11 29 30 32 66

MEM_B_A<6>

11 29 30 32 66

MEM_B_A<7>

11 29 30 32 66

MEM_B_A<8>

11 29 30 32 66

MEM_B_A<9>

11 29 30 32 66

MEM_B_A<10>

11 29 30 32 66

MEM_B_A<11>

11 29 30 32 66

MEM_B_A<12>

11 29 30 32 66

MEM_B_A<13>

11 29 30 32 66

MEM_B_A<14>

11 29 30 32 66

MEM_B_A<15>

11 29 30 32 66

MEM_B_BA<0>

11 29 30 32 66

MEM_B_BA<1>

11 29 30 32 66

MEM_B_BA<2>

11 29 30 32 66

MEM_B_CLK_P<0>

11 29 30 32 66

MEM_B_CLK_N<0>

11 29 30 32 66

MEM_B_CKE<0>

11 29 30 32 66

MEM_B_CKE<1>

11 29 30 32 66

MEM_B_CS_L<1>

11 29 30 32 66

MEM_B_CS_L<0>

11 29 30 32 66

MEM_B_RAS_L

11 29 30 32 66

MEM_B_CAS_L

11 29 30 32 66

MEM_B_WE_L

11 29 30 32 66

PP0V75_S3_MEM_VREFCA_B

R3120

29 30 31

C3120

0.47UF

20%

CERM-X5R-1

201 4V

11 29 30 32 66

26 27 28 29 30

240

1 2

1%

MF

201

11 29 30 32 66

PP0V75_S3_MEM_VREFDQ_B

1

C3121

0.47UF

20%

CERM-X5R-1

2

201 4V

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_RESET_L

MEM_B_ZQ2 MEM_B_ZQ6

1/20W

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<14>

MEM_B_A<15> MEM_B_BA<0> MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CS_L<1> MEM_B_CS_L<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

1

2

G1 F1

N2

H8 H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9 F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U3120

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

7

29 30 32

OMIT_TABLE

MT41K1G4

N1

N9

L9

=PP1V5_S3_MEM_B

C3122

VDDQ

DQ0 DQ1 DQ2 DQ3

E3

NF_DQ4

E8

NF_DQ5

D2

NF_DQ6

E7

NF_DQ7

DQS

DQS*

DM/TDQS

A7

NF_TDQS*

NC

VSSQ

B2B8C9D1D9

1

0.47UF

20%

CERM-X5R-1

2

201 201 4V

R3130

B3

MEM_B_DQ<16>

C7

MEM_B_DQ<22>

C2

MEM_B_DQ<21>

C8

MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<23>

C3

MEM_B_DQS_P<2>

D3

MEM_B_DQS_N<2>

11 66

B7

NC

A3

NC

79 80 81 82

=PP1V5_S3_MEM_B

7

29 30 32

1

20%

2

G1 F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9

F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

VREFCA

U3110

FBGA-9P5X11P65-COMBO

ODT0 ODT1

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

OMIT_TABLE

MT41K1G4

N1

N9

L9

VDDQ

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

NC

VSSQ

B2B8C9D1D9

C3112

0.47UF

20%

CERM-X5R-1

201 4V

B3

MEM_B_DQ<14>

C7

MEM_B_DQ<9>

C2

MEM_B_DQ<8>

C8

MEM_B_DQ<12>

E3

MEM_B_DQ<10>

E8

MEM_B_DQ<13>

D2

MEM_B_DQ<11>

E7

MEM_B_DQ<15>

C3

MEM_B_DQS_P<1>

D3

MEM_B_DQS_N<1>

B7

A7

NC

A3

NC

79 80 81 82

1

2

11 66

29 30 31

C3130

0.47UF

CERM-X5R-1

240

1 2

MF

1%

201

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B

1

C3131

0.47UF

20%

CERM-X5R-1

2

4V

MEM_B_ODT<0>

11 29 30 32 66

MEM_B_ODT<1>

11 29 30 32 66

MEM_RESET_L

26 27 28 29 30

1/20W

MEM_B_A<0>

11 29 30 32 66

MEM_B_A<1>

11 29 30 32 66

MEM_B_A<2>

11 29 30 32 66

MEM_B_A<3>

11 29 30 32 66

MEM_B_A<4>

11 29 30 32 66

MEM_B_A<5>

11 29 30 32 66

MEM_B_A<6>

11 29 30 32 66

MEM_B_A<7>

11 29 30 32 66

MEM_B_A<8>

11 29 30 32 66

MEM_B_A<9>

11 29 30 32 66

MEM_B_A<10>

11 29 30 32 66

MEM_B_A<11>

11 29 30 32 66

MEM_B_A<12>

11 29 30 32 66

MEM_B_A<13>

11 29 30 32 66

MEM_B_A<14>

11 29 30 32 66

MEM_B_A<15>

11 29 30 32 66

MEM_B_BA<0>

11 29 30 32 66

MEM_B_BA<1>

11 29 30 32 66

MEM_B_BA<2>

11 29 30 32 66

MEM_B_CLK_P<0>

11 29 30 32 66

MEM_B_CLK_N<0>

11 29 30 32 66

MEM_B_CKE<0>

11 29 30 32 66

MEM_B_CKE<1>

11 29 30 32 66

MEM_B_CS_L<1>

11 29 30 32 66

MEM_B_CS_L<0>

11 29 30 32 66

MEM_B_RAS_L

11 29 30 32 66

MEM_B_CAS_L

11 29 30 32 66

MEM_B_WE_L

11 29 30 32 66

20%

201 4V

MEM_B_ZQ3 MEM_B_ZQ7

1

2

G1

F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7

G7

G9

F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U3130

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

7

29 30 32

OMIT_TABLE

MT41K1G4

N1

N9

L9

=PP1V5_S3_MEM_B

VDDQ

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

NF_DQ4

E8

NF_DQ5

D2

NF_DQ6

E7

NF_DQ7

C3

DQS

D3

DQS*

B7

DM/TDQS

A7

NF_TDQS*

A3

79

NC

80 81 82

VSSQ

B2B8C9D1D9

C3132

0.47UF

20%

CERM-X5R-1

201 4V

MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<24> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<25> MEM_B_DQ<31> MEM_B_DQ<26>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

NCNC

NC NC

1

2

11 66

D

C

B

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

240

R3101

1 2

201

MF

R3111

1 2

201MF1/20W

A

R3121

2011%1/20W

R3131

2011%1/20W

1 2

MF

1 2

MF

MEM_B_ZQ4

MEM_B_ZQ5

MEM_B_ZQ6

MEM_B_ZQ7

29

SIZE

A

D

29

SYNC_MASTER=J13_MLB

PAGE TITLE

DDR3 DRAM CHANNEL B (0-31)

Apple Inc.

29

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

R

6 3

SYNC_DATE=08/29/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

31 OF 109

SHEET

29 OF 72

124578

1%

1/20W

240

1%

240

8 7 6 5 4 3

12

D

PP0V75_S3_MEM_VREFCA_B

29 30 31

PP0V75_S3_MEM_VREFDQ_B

29 30 31

1

C3200

0.47UF

20%

CERM-X5R-1

2

201 4V

MEM_B_ODT<0>

11 29 30 32 66

MEM_B_ODT<1> MEM_B_ODT<0>

11 29 30 32 66 11 29 30 32 66

MEM_RESET_L

26 27 28 29 30

240

R3200

1 2

201

1%

MF

1/20W

MEM_B_A<0>

11 29 30 32 66

MEM_B_A<1>

11 29 30 32 66

MEM_B_A<2>

C

B

11 29 30 32 66

MEM_B_A<3>

11 29 30 32 66 11 66

MEM_B_A<4>

11 29 30 32 66

MEM_B_A<5>

11 29 30 32 66

MEM_B_A<6>

11 29 30 32 66

MEM_B_A<7>

11 29 30 32 66

MEM_B_A<8>

11 29 30 32 66

MEM_B_A<9>

11 29 30 32 66

MEM_B_A<10>

11 29 30 32 66

MEM_B_A<11>

11 29 30 32 66

MEM_B_A<12>

11 29 30 32 66

MEM_B_A<13>

11 29 30 32 66

MEM_B_A<14>

11 29 30 32 66

MEM_B_A<15>

11 29 30 32 66

MEM_B_BA<0>

11 29 30 32 66

MEM_B_BA<1>

11 29 30 32 66

MEM_B_BA<2>

11 29 30 32 66

MEM_B_CLK_P<0>

11 29 30 32 66

MEM_B_CLK_N<0>

11 29 30 32 66

MEM_B_CKE<0>

11 29 30 32 66

MEM_B_CKE<1>

11 29 30 32 66

MEM_B_CS_L<1>

11 29 30 32 66

MEM_B_CS_L<0>

11 29 30 32 66

MEM_B_RAS_L

11 29 30 32 66

MEM_B_CAS_L

11 29 30 32 66

MEM_B_WE_L

11 29 30 32 66

C3201

0.47UF

20% CERM-X5R-1 201 4V

MEM_B_ZQ8

MEM_B_ZQ12

1

2

G1 F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9

F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U3200

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_B

7

29 30 32

VDDQ

OMIT_TABLE

MT41K1G4

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5

N9

NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

NC

512MX8-4GBIT-DDR3-1600

N1

L9

C3202

0.47UF

20% CERM-X5R-1 201 4V

B3

MEM_B_DQ<38>

C7

MEM_B_DQ<33>

C2

MEM_B_DQ<35>

C8

MEM_B_DQ<32>

E3

MEM_B_DQ<37>

E8

MEM_B_DQ<36>

D2

MEM_B_DQ<34>

E7

MEM_B_DQ<39>

C3

MEM_B_DQS_P<4>

D3

MEM_B_DQS_N<4>

B7

A7

NC

A3

NC

79 80 81 82

1

2

R3210

11 66

11 66 11 29 30 32 66

29 30 31

C3210

0.47UF

240

1 2

MF

1%

201

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B

1

0.47UF

20%

CERM-X5R-1

2

201 4V

MEM_B_ODT<0>

11 29 30 32 66

MEM_B_ODT<1>

11 29 30 32 66

MEM_RESET_L

26 27 28 29 30

MEM_B_ZQ13

1/20W

MEM_B_A<0>

11 29 30 32 66

MEM_B_A<1>

11 29 30 32 66

MEM_B_A<2>

11 29 30 32 66

MEM_B_A<3>

11 29 30 32 66

MEM_B_A<4>

11 29 30 32 66

MEM_B_A<5>

11 29 30 32 66

MEM_B_A<6>

11 29 30 32 66

MEM_B_A<7>

11 29 30 32 66

MEM_B_A<8>

11 29 30 32 66

MEM_B_A<9>

11 29 30 32 66

MEM_B_A<10> MEM_B_A<11>

11 29 30 32 66

MEM_B_A<12>

11 29 30 32 66

MEM_B_A<13>

11 29 30 32 66

MEM_B_A<14>

11 29 30 32 66

MEM_B_A<15>

11 29 30 32 66

MEM_B_BA<0>

11 29 30 32 66

MEM_B_BA<1>

11 29 30 32 66

MEM_B_BA<2>

11 29 30 32 66

MEM_B_CLK_P<0>

11 29 30 32 66

MEM_B_CLK_N<0>

11 29 30 32 66

MEM_B_CKE<0>

11 29 30 32 66

MEM_B_CKE<1>

11 29 30 32 66

MEM_B_CS_L<1>

11 29 30 32 66

MEM_B_CS_L<0>

11 29 30 32 66

MEM_B_RAS_L

11 29 30 32 66

MEM_B_CAS_L

11 29 30 32 66

MEM_B_WE_L

11 29 30 32 66

C3211

20% CERM-X5R-1 201 4V

MEM_B_ZQ9

1

2

G1 F1

N2

H8

H9 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9

F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

VREFCA

U3210

FBGA-9P5X11P65-COMBO

ODT0 ODT1

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

512MX8-4GBIT-DDR3-1600

VSS

A1

A8

B1D8F2F8J1J9L1

29 30 32

OMIT_TABLE

MT41K1G4

N1

N9

L9

=PP1V5_S3_MEM_B

7

VDDQ

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

NC

VSSQ

B2B8C9D1D9

C3212

0.47UF

20% CERM-X5R-1 201 4V

B3

MEM_B_DQ<43>

C7

MEM_B_DQ<41>

C2

MEM_B_DQ<42>

C8

MEM_B_DQ<47>

E3

MEM_B_DQ<44>

E8

MEM_B_DQ<45>

D2

MEM_B_DQ<46>

E7

MEM_B_DQ<40>

C3

MEM_B_DQS_P<5>

D3

MEM_B_DQS_N<5>

B7

A7

NC

A3

NC

79 80 81 82

PP0V75_S3_MEM_VREFCA_B

29 30 31

PP0V75_S3_MEM_VREFDQ_B

1

2

R3220

11 66

29 30 31

C3220

0.47UF

20% CERM-X5R-1 201 4V

240

1 2

1%

MF

201

1

2

MEM_B_ODT<0>

11 29 30 32 66

MEM_B_ODT<1>

11 29 30 32 66

MEM_RESET_L

26 27 28 29 30

1/20W

MEM_B_A<0>

11 29 30 32 66

MEM_B_A<1>

11 29 30 32 66

MEM_B_A<2>

11 29 30 32 66

MEM_B_A<3>

11 29 30 32 66

MEM_B_A<4>

11 29 30 32 66

MEM_B_A<5>

11 29 30 32 66

MEM_B_A<6>

11 29 30 32 66

MEM_B_A<7>

11 29 30 32 66

MEM_B_A<8>

11 29 30 32 66

MEM_B_A<9>

11 29 30 32 66

MEM_B_A<10>

11 29 30 32 66

MEM_B_A<11>

11 29 30 32 66

MEM_B_A<12>

11 29 30 32 66

MEM_B_A<13>

11 29 30 32 66

MEM_B_A<14>

11 29 30 32 66

MEM_B_A<15>

11 29 30 32 66

MEM_B_BA<0>

11 29 30 32 66

MEM_B_BA<1>

11 29 30 32 66

MEM_B_BA<2>

11 29 30 32 66

MEM_B_CLK_P<0>

11 29 30 32 66

MEM_B_CLK_N<0>

11 29 30 32 66

MEM_B_CKE<0>

11 29 30 32 66

MEM_B_CKE<1>

11 29 30 32 66

MEM_B_CS_L<1>

11 29 30 32 66

MEM_B_CS_L<0>

11 29 30 32 66

MEM_B_RAS_L

11 29 30 32 66

MEM_B_CAS_L

11 29 30 32 66

MEM_B_WE_L

11 29 30 32 66

1

C3221

0.47UF

20%

CERM-X5R-1

2

201 201 4V

G1 F1

N2

H8

MEM_B_ZQ10

H9

MEM_B_ZQ14

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9 F9

H1 H2

F3 G3 H3

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

ODT0 ODT1

VREFCA

U3220

FBGA-9P5X11P65-COMBO

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

VSS

A1

A8

B1D8F2F8J1J9L1

=PP1V5_S3_MEM_B

7

29 30 32

VDDQ

OMIT_TABLE

MT41K1G4

DQ0 DQ1 DQ2

DQ3 NF_DQ4 NF_DQ5

N9

NF_DQ6 NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

NC

512MX8-4GBIT-DDR3-1600

N1

L9

1

C3222

0.47UF

20%

CERM-X5R-1

2

4V

R3230

1 2

B3

MEM_B_DQ<49>

C7

MEM_B_DQ<53>

C2

MEM_B_DQ<55>

C8

MEM_B_DQ<48>

E3

MEM_B_DQ<50>

E8

MEM_B_DQ<51>

D2

MEM_B_DQ<54>

E7

MEM_B_DQ<52>

C3

MEM_B_DQS_P<6>

D3

MEM_B_DQS_N<6>

11 66

201

B7

A7

NC NC

A3

NC

79 80 81 82

29 30 31

C3230

0.47UF

240

20% CERM-X5R-1 201 4V

26 27 28 29 30

1/20WMF1%

11 29 30 32 66

MEM_RESET_L

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>

MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CS_L<1> MEM_B_CS_L<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B

1

C3231

0.47UF

20%

CERM-X5R-1

2

201 4V

G1

MEM_B_ODT<1>

F1

N2

H8

MEM_B_ZQ11

H9

MEM_B_ZQ15

K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J7 J2 K8 J3

F7 G7

G9 F9

H1 H2

F3 G3 H3

1

2

ODT0 ODT1

RESET*

ZQ0 ZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13

A14

A15 BA0 BA1 BA2

CK CK*

CKE0 CKE1

CS1* CS0*

RAS* CAS* WE*

A1

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

VDD

VREFDQ

VREFCA

U3230

FBGA-9P5X11P65-COMBO

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

A8

B1D8F2F8J1J9L1

N1

L9

=PP1V5_S3_MEM_B

7

29 30 32

VDDQ

OMIT_TABLE

NF_DQ4 NF_DQ5 NF_DQ6 NF_DQ7

DM/TDQS

NF_TDQS*

VSSQ

N9

B2B8C9D1D9

DQS*

DQ0 DQ1 DQ2 DQ3

DQS

NC

C3232

0.47UF

20% CERM-X5R-1 201 4V

B3

MEM_B_DQ<61>

C7

MEM_B_DQ<57>

C2

MEM_B_DQ<58>

C8

MEM_B_DQ<56>

E3

MEM_B_DQ<59>

E8

MEM_B_DQ<60>

D2

MEM_B_DQ<62>

E7

MEM_B_DQ<63>

C3

MEM_B_DQS_P<7>

D3

MEM_B_DQS_N<7>

B7

A7

A3

NC

79 80 81 82

1

2

11 66

D

C

B

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

240

R3201

1 2

201

R3211

1 2

2011%1/20W

A

R3221

R3231

1 2

201

1 2

201

MEM_B_ZQ12

MEM_B_ZQ13

MEM_B_ZQ14

MEM_B_ZQ15

30

SIZE

A

D

30

SYNC_MASTER=J13_MLB

PAGE TITLE

DDR3 DRAM CHANNEL B (32-63)

30

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

Apple Inc.

R

6 3

SYNC_DATE=08/29/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

32 OF 109

SHEET

30 OF 72

124578

MF

1%

1/20W

240

MF

240

1/20W

1%

MF

240

1/20W

1%

MF

8 7 6 5 4 3

=PP3V3_S3_VREFMRGN

7

D

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

C

B

- =PPDDR_S3_MEMVREF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

DDRVREF_DAC - Stuffs Apple margining circuit. VREFDQ:LDO - LDO outputs sent to DQ inputs. VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs. VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs. VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs. VREFCA:LDO - LDO outputs sent to CA inputs. VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

=PPDDR_S3_MEMVREF

7

31

MEMRESET_ISOL_LS5V_L

26 31

PPCPU_MEM_VREFDQ_A

9

OMIT

R3318

SHORT

1 2

CRITICAL

VREFDQ:M1_M3

Q3320

SSM6N15AFE

2

SOT563

S G

1

NONE NONE NONE

402

OMIT

R3319

SHORT

NONE NONE NONE

402

D

6

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

43

IN

43

BI

Addr=0x98(WR)/0x99(RD)

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

Addr=0x30(WR)/0x31(RD)

43

IN

43

BI

25

IN

RST* on ’platform reset’ so that system watchdog will disable margining.

NOTE: Margining will be disabled across all

soft-resets and sleep/wake cycles.

PLACE_NEAR=Q3320.6:2mm

VREFDQ:M1_M3

1

C3320

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=R3321.2:1mm

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

PCA9557D_RESET_L

DDRVREF_DAC

1

C3300

2.2UF

20%

6.3V 2

CERM

402-LF

DDRVREF_DAC

C3302

PLACE_NEAR=Q3320.6:1mm

VREFDQ:M1_M3

1

R3321

1K

1% 1/20W MF 201

2

VREFDQ:M1_M3

1

R3322

1K

1% 1/20W MF 201

2

DDRVREF_DAC

1

C3301

0.1UF

10% 16V

2

X5R-CERM 0201

VDD

6

SCL

7

SDA

9

A0

10

A1

GND

1

0.1UF

10%

6.3V 2

X5R 201

3

A0

4

A1

5

A2

1

SCL

2

SDA

THRM

PAD

17

PP0V75_S3_MEM_VREFDQ_A

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step

8

MSOP

3

U3301

PCA9557

DAC5574

VCC

GND

CRITICAL

DDRVREF_DAC

U3300

VOUTA

VOUTB

VOUTC

VOUTD

CRITICAL

DDRVREF_DAC

16

QFN

(OD)

RESET*

8

27 28 31 66

1

VREFMRGN_SODIMMA_DQ

2

NC

4

VREFMRGN_SODIMMS_CA

5

VREFMRGN_MEMVREG_FBVREF

NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable both at the same time!

6

P0

NC

7

9

NC

10

11

12

13

NC

14

NC

15

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMB_EN VREFMRGN_MEMVREG_EN

P1 P2 P3 P4 P5 P6 P7

DDRVREF_DAC

C3303

0.1UF

X5R-CERM

DDRVREF_DAC

10% 16V

0201

12

DDRVREF_DAC

R3301

100K

5% 1/20W MF 201

DDRVREF_DAC

1

R3307

100K

5% 1/20W MF 201

2

DDRVREF_DAC

1

R3315

100K

5% 1/20W MF 201

2

C3305

0.1UF

X5R-CERM

12

NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.

VREFDQ:LDO_DAC

=PPVTT_S3_DDR_BUF

7

55

10mA max load

V-

B1

V+

V-

B4

B1

V+

B4

B1

V+

B4

B1

V+

V-

B4

DDRVREF_DAC

MAX4253

UCSP

A4

DDRVREF_DAC

U3302

MAX4253

UCSP

C4

DDRVREF_DAC

U3304

MAX4253

UCSP

A4

DDRVREF_DAC

MAX4253

UCSP

C4

U3302

A1

C1

A1

U3304

C1

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_MEMVREG_BUF

1

2

A2

A3

C2

C3

A2

A3

1

10% 16V

0201

C2

2

C3

R3303

200

1 2

1%

1/20W

MF

201

VREFDQ:LDO_DAC

R3304

133

1 2

1%

1/20W

MF

201

VREFCA:LDO_DAC

R3309

200

1 2

1%

1/20W

MF

201

VREFCA:LDO_DAC

R3310

133

1 2

1%

1/20W

MF

201

VREFCA:LDO_DAC

R3305

200

1 2

1%

1/20W

MF

201

VREFCA:LDO_DAC

R3306

133

1 2

1%

1/20W

MF

201

DDRVREF_DAC

R3314

33.2K

1 2

1%

1/20W

MF

201

PLACE_NEAR=U2900.E1:2.54mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3303.2:1mm

PLACE_NEAR=U2900.J8:2.54mm

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3309.2:1mm

PLACE_NEAR=U3100.J8:2.54mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3305.2:1mm

DDRREG_FB

PLACE_NEAR=R7315.2:1mm

29 30 31

PLACE_NEAR=Q3310.3:1mm VREFDQ:LDO_DAC

1

R3360

0

5% 1/20W MF 201

2

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

29 30

PLACE_NEAR=R3309:1mm

NOSTUFF

1

R3361

0

5% 1/20W MF 201

2

27 28 66

D

27 28 31 66

C

55

OUT

B

=PPDDR_S3_MEMVREF

7

31

MEMRESET_ISOL_LS5V_L

26 31

PPCPU_MEM_VREFDQ_B

9

A

MEM A VREF DQ

DAC Channel: PCA9557D Pin: Nominal value Margined target: 1.000V - 2.000V (+/- 500mV) DAC range: VRef current: DAC step size:

CRITICAL

VREFDQ:M1_M3

Q3320

SSM6N15AFE

5

SOT563

S G

4

3

1

2

D

PLACE_NEAR=Q3320.3:2mm

VREFDQ:M1_M3

C3310

0.1UF

10% 16V X5R-CERM 0201

MEM B VREF DQ

A B 1

0.75V (DAC: 0x3A)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced)

7.69mV / step @ output

PLACE_NEAR=R3311.2:1mm

2

PLACE_NEAR=Q3320.3:2mm

VREFDQ:M1_M3

1

R3311

1K

1% 1/20W MF 201

2

PP0V75_S3_MEM_VREFDQ_B

VREFDQ:M1_M3

1

R3312

1K

1% 1/20W MF 201

2

MEM A VREF CA

C 3 4

29 30 31

MEM B VREF CA

C

1.5V (DAC: 0x3A)

0.000V - 3.000V (0x00 - 0x74) +61uA - -61uA (- = sourced)

8.59mV / step @ output

6 3

MEM VREG

D 5

DDRVREF_DAC

1

2

R3313

100K

5% 1/20W MF 201

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

GPU Frame Buffer (1.8V, 70% VRef)

D 6

1.267V (DAC: 0x8B)

1.056V - 1.442V (+/- 180mV)

0.000V - 3.300V (0x00 - 0xFF) +6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

117S0002

118S0012

118S0303

QTY

2

QTY

4

1

DESCRIPTION

RES,MF,1/20W,0.0 OHM,5,0201,SMD

DESCRIPTION

RES,MF,1KOHM,1,1/20W,0201

RES,MF,332OHM,1,1/20W,0201

REFERENCE DES

R3321,R3322,R3311,R3312

SYNC_MASTER=J13_MLB

PAGE TITLE

R3303,R3360

R3309,R3305

R3304

CRITICAL

FSB/DDR3/FRAMEBUF Vref Margining

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

BOM OPTION

VREFDQ:LDO

VREFCA:LDO

BOM OPTION

VREFDQ:M1_DAC

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

33 OF 109

SHEET

31 OF 72

124578

SIZE

A

D

RP3409

C

B

A

8 7 6 5 4 3

=PP1V5_S3_MEM_A

7

27 28 32

1

C3408

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3409

2.2UF

20%

6.3V

2

CERM 402-LF

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

=PP1V5_S3_MEM_B

7

29 30

32

1

C3428

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3429

2.2UF

20%

6.3V

2

CERM 402-LF

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

1

C3400

2

1

C3401

2

1

C3404

2

1

C3405

2

C3402

2.2UF

20%

6.3V CERM 402-LF

1

C3403

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3406

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3407

2.2UF

20%

6.3V

2

CERM 402-LF

2.2UF

20%

6.3V CERM 402-LF

2.2UF

20%

6.3V CERM 402-LF

2.2UF

20%

6.3V CERM 402-LF

2.2UF

20%

6.3V CERM 402-LF

1

C3410

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3411

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3412

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3414

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3415

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3416

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3470

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3471

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3472

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3474

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3475

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3476

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3420

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3421

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3424

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3425

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3422

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3423

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3426

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3427

2.2UF

20%

6.3V

2

CERM 402-LF

=PP1V5_S3_MEM_A

7

27 28 32

7

29 30 32

1

2

1

C3418

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3419

2.2UF

20%

6.3V

2

CERM 402-LF

COLUMN OF THREE CAPS BETWEEN PACKAGES

=PP1V5_S3_MEM_B

1

C3438

2.2UF

20%

6.3V

2

CERM 402-LF

C3439

2.2UF

20%

6.3V CERM 402-LF

COLUMN OF THREE CAPS BETWEEN PACKAGES

6 3

1

C3432

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3433

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3436

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3437

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3430

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3431

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3434

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3435

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3490

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3491

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3492

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3494

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3495

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3496

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3440

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3441

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3442

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3444

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3445

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3446

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3450

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3451

2.2UF

20%

6.3V

2

CERM 402-LF

2 CAPS ALONG PACKAGE EDGE

1

C3454

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3455

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3452

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3453

2.2UF

20%

6.3V

2

CERM 402-LF

2 CAPS ALONG PACKAGE EDGE

1

C3456

2.2UF

20%

6.3V

2

CERM 402-LF

1

C3457

2.2UF

20%

6.3V

2

CERM 402-LF

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

11 27 28 66

11 29 30 66

IN

11 29 30 66

IN

11 29 30 66

IN

11 29 30 66

IN

11 29 30 66

IN

11 29 30 66

IN

11 29 30 66

IN

11 29 30 66

IN

11 29 30 66

C3469

1

0.1UF

10% X5R 201

6.3V

C3479

1

0.1UF

10% X5R 201

6.3V

IN

2

MEM CLOCK TERMINATION

Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM

R3468

30

1 2

MEM_A_CLK_N<0>

11 27 28 66

MEM_A_CLK_P<0>

11 27 28 66

MEM_B_CLK_N<0>

11 29 30 66

MEM_B_CLK_P<0>

11 29 30 66

C3468

3.3PF

5% 25V CERM 201

C3478

3.3PF

5% 25V CERM 201

1

2

1

2

5%

1/20W

MF

201

R3469

30

1 2

5%

1/20W

MF

201

R3478

30

1 2

5%

1/20W

MF

201

R3479

30

1 2

5%

1/20W

MF

201

MEM_A_CLK_TERM_R

VOLTAGE=0V

MEM_B_CLK_TERM_R

VOLTAGE=0V

IN IN IN IN IN IN

IN IN IN

IN

IN IN IN IN IN IN IN IN

IN IN IN IN IN IN

IN IN IN IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

MEM_B_A<3> MEM_B_A<1> MEM_B_CAS_L

MEM_B_A<2> MEM_B_A<6>

MEM_B_CKE<1> MEM_B_ODT<1> MEM_B_A<15> MEM_B_CS_L<1>

MEM_A_CKE<0> MEM_A_WE_L

MEM_A_A<7> MEM_A_BA<0> MEM_A_CS_L<0> MEM_A_ODT<0>

MEM_A_A<12> MEM_A_A<14> MEM_A_A<2>

MEM_A_A<11>

MEM_A_A<10> MEM_A_A<3> MEM_A_A<0> MEM_A_A<4> MEM_A_A<8>

MEM_A_BA<2> MEM_A_BA<1>

MEM_A_A<6>

MEM_A_A<13> MEM_A_A<1> MEM_A_A<5> MEM_A_CAS_L MEM_A_RAS_L MEM_A_A<9>

MEM_A_CKE<1> MEM_A_ODT<1> MEM_A_CS_L<1> MEM_A_A<15>

MEM_B_RAS_L MEM_B_A<8> MEM_B_CKE<0> MEM_B_A<7>

MEM_B_BA<0> MEM_B_A<13> MEM_B_BA<1> MEM_B_ODT<0> MEM_B_A<5> MEM_B_WE_L MEM_B_A<11> MEM_B_BA<2> MEM_B_A<12> MEM_B_A<0> MEM_B_CS_L<0> MEM_B_A<14> MEM_B_A<4> MEM_B_A<10> MEM_B_A<9>

RP3401 RP3402 RP3406 RP3403 RP3402 RP3401

RP3403 RP3407 RP3406

RP3406 RP3402

RP3404 RP3403 RP3404 RP3407 RP3402 RP3403 RP3407

RP3407 RP3404 RP3404 RP3401 RP3401 RP3406

RP3405 RP3405 RP3405 RP3405

RP3413 RP3410 RP3409 RP3411

RP3409 RP3410 RP3408 RP3413 RP3411 RP3413 RP3411

RP3408 RP3408 RP3409 RP3410 RP3414 RP3408 RP3410

RP3414 RP3414 RP3413

RP3414 RP3411

RP3412 RP3412 RP3412 RP3412

=PP0V75_S0_MEM_VTT_A

7

4 5

36

2 7

36

2 7

36

1 8

36

1 8

36

2 7

36

2 7

36

3 6

36

1 8

36

4 5

36

3 6 3 6

36

4 5

36

1 8 2 7

36

4 5

36

3 6

36

1 8

36

4 5

36

2 7

36

4 5

36

3 6

36

1 8

36

3 6

36

1 8

36

2 7

36

3 6

36

4 5

36

=PP0V75_S0_MEM_VTT_B

7

1 8

36

1 8

36

1 8 4 5

36

3 6

36

3 6

36

4 5

36

3 6

36

2 7

36

4 5 3 6 4 5

36

2 7

36

3 6

36

2 7

36

4 5

36

4 5

36

1 8

36

2 7

36

2 7

36

1 8

36

2 7

36

3 6 1 8

36

1 8

36

2 7

36

3 6

36

4 5

36

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W365%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5% 5%

1/32W

5%

1/32W

5%

1/32W 1/32W

5% 5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W365%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W365%

4X0201

1/32W365%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%361/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

SYNC_MASTER=K21_MLB

PAGE TITLE

4X0201 4X0201 4X0201 4X0201 4X0201 4X0201

4X0201 4X0201 4X0201 4X0201

1

C3480

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3482

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3484

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3486

0.47UF

4V

2

CERM-X5R-1 201

1

C3488

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3489

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3481

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3460

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3461

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3463

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3465

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3466

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3477

0.47UF

20% 4V

2

CERM-X5R-1 201

DDR3 DRAM Channel B (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

C3483

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3485

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3487

0.47UF

20%20% 4V

2

CERM-X5R-1 201

1

C3493

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3462

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3464

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3467

0.47UF

20% 4V

2

CERM-X5R-1 201

12

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

34 OF 109

SHEET

32 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

CRITICAL

0.1UF

1 2

X5R-CERM

16V10%

X5R-CERM

16V10%

X5R-CERM

16V10%

X5R-CERM

16V10%

X5R-CERM

16V10%

X5R-CERM

16V10%

X5R-CERM

16V10%

X5R-CERM

16V10%

68

0201

68

0201

68

0201

68

0201

68

0201

68

0201

68

0201

68

0201

35

IN

PCIE_TBT_R2D_P<0> PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<1> PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<2> PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<3> PCIE_TBT_R2D_N<3>

TBT_PCIE_RESET_L

TBT_PWR_ON_POC_RST_L

1

10% 16V

2

0201

1

0

5%

1/20W

MF

201

2

NOSTUFF

1

R3629

0

5% 1/20W MF 201

2

8

OUT

R3630

100K

8

OUT

R3631

100K

R3615

5%

1/20W

MF

201

5%

1/20W

MF

201

OMIT

NONE NONE NONE

1

2

1

2

1

402

2

TP_TBT_MONDC0 TP_TBT_MONDC1

DEBUG: For monitoring current/voltage

TBT_MONOBSP TBT_MONOBSN

DEBUG: For monitoring clock

TP_TBT_THERM_DP

46

Use AA8 GND ball for THERM_DN

TBT_SPI_MOSI

69

TBT_SPI_MISO

69

TBT_SPI_CS_L

69

TBT_SPI_CLK

JTAG_TBT_TDI

19

IN

JTAG_TBT_TMS

19

IN

JTAG_TBT_TCK

19

IN

JTAG_TBT_TDO

19

OUT

TBT_TEST_EN TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

33 68

DP_TBTSNK0_ML_N<3>

33 68

DP_TBTSNK0_ML_P<2>

33 68

DP_TBTSNK0_ML_N<2>

33 68

DP_TBTSNK0_ML_P<1>

33 68

DP_TBTSNK0_ML_N<1>

33 68

DP_TBTSNK0_ML_P<0>

33 68

DP_TBTSNK0_ML_N<0>

33 68

DP_TBTSNK0_AUXCH_P

33 68

DP_TBTSNK0_AUXCH_N

33 68

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_P<3>

33 68

DP_TBTSNK1_ML_N<3>

33 68

DP_TBTSNK1_ML_P<2>

33 68

DP_TBTSNK1_ML_N<2>

33 68

DP_TBTSNK1_ML_P<1>

33 68

DP_TBTSNK1_ML_N<1>

33 68

DP_TBTSNK1_ML_P<0>

33 68

DP_TBTSNK1_ML_N<0>

33 68

DP_TBTSNK1_AUXCH_P

33 68

DP_TBTSNK1_AUXCH_N

33 68

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

63 69

OUT

TBT_A_R2D_C_N<0>

63 69

OUT

TBT_A_D2R_P<0>

63 69

IN

TBT_A_D2R_N<0>

63 69

IN

TBT_A_CONFIG1_BUF

63

OUT

TBT_A_CONFIG2_RC

63

IN

TBT_A_R2D_C_P<1>

63 69

OUT

TBT_A_R2D_C_N<1>

63 69

OUT

TBT_A_D2R_P<1>

63 69

IN

TBT_A_D2R_N<1>

63 69

IN

TBT_A_LSTX

63

OUT

TBT_A_LSRX

63

IN

DP_TBTPA_ML_C_P<1>

63 69

OUT

DP_TBTPA_ML_C_N<1>

63 69

OUT

DP_TBTPA_ML_C_P<3>

63 69

OUT

DP_TBTPA_ML_C_N<3>

63 69

OUT

DP_TBTPA_AUXCH_C_P

63 69

BI

DP_TBTPA_AUXCH_C_N

63 69

BI

DP_TBTPA_HPD

63

IN

TBT_A_HV_EN

33 35 63

OUT

TBT_A_CIO_SEL

63

OUT

TBT_A_DP_PWRDN

33 63

OUT

AB9

PERP_0

AA10

PERN_0

AA12

PERP_1

AB13

PERN_1

AB15 AA16

AA18 AB19

R6

J2

AD23

AC24

W18

W16

Y7

R4

P5

AD3

W4

V1

AB3

AA6

R2

N4

AB5

E14

D13

E16 D15

E18

D17

E20

D19

A6

B5

U6

E6

D5

E8

D7

E10

D9

E12

D11

A4 B3

T5

G24

E24

G22

E22

K1

G4

L24

J24

L22 J22

N2

J6

A16

B17

A18 B19

F3 F1

H1

G2

M3 L2 H3 L4

RECEIVE

PERP_2 PERN_2

PERP_3 PERN_3

PERST_N

PWR_ON_POC_RSTN

MONDC0 MONDC1

MONOBS_P MONOBS_N

THERMDA

EE_DI EE_DO EE_CS_N

EEPROM

EE_CLK

TDI TMS TCK TDO TEST_EN TEST_PWR_GOOD

DPSNK0_3_P DPSNK0_3_N

DPSNK0_2_P DPSNK0_2_N

DPSNK0_1_P DPSNK0_1_N

DPSNK0_0_P DPSNK0_0_N

DPSNK0_AUX_P DPSNK0_AUX_N

DPSNK0_HPD

DPSNK1_3_P DPSNK1_3_N

DPSNK1_2_P DPSNK1_2_N

DPSNK1_1_P DPSNK1_1_N

DPSNK1_0_P DPSNK1_0_N

DPSNK1_AUX_P DPSNK1_AUX_N

DPSNK1_HPD

PA_CIO0_TX_P/DP_SRC_0_P PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_RX_P PA_CIO0_RX_N

PA_CONFIG1/CIO_0_LSEO PA_CONFIG2/CIO_0_LSOE

PA_CIO1_TX_P/DP_SRC_2_P PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_RX_P PA_CIO1_RX_N

PA_LSTX/CIO_1_LSEO PA_LSRX/CIO_1_LSOE

PA_DPSRC_1_P PA_DPSRC_1_N

PA_DPSRC_3_P PA_DPSRC_3_N

PA_AUX_P PA_AUX_N

PA_DPSRC_HPD

GPIO_0/PA_HV_EN/BYP0 GPIO_10/PA_CIO_SEL/BYP1 GPIO_12/PA_DP_PWRDN/BYP2

OMIT_TABLE

U3600

CACTUSRIDGE4C

FCBGA

(SYM 1 OF 2)

JTAG/TEST PORT

SINK PORT 0SINK PORT 1

PORT0PORT1

PETP_0 PETN_0

PETP_1 PETN_1

TRANSMIT

PETP_2 PETN_2

PCIE GEN2

PETP_3 PETN_3

RSENSE

RBIAS

PCIE_RST_0_N PCIE_RST_1_N PCIE_RST_2_N PCIE_RST_3_N

MISC

PCIE RESET

PCIE_CLKREQ_OD_N

EN_LC_PWR

REFCLK_100_IN_P REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

CLOCKS

TMU_CLK_OUT

TMU_CLK_IN

DPSRC_3_P DPSRC_3_N

DPSRC_2_P DPSRC_2_N

DPSRC_1_P DPSRC_1_N

DPSRC_0_P DPSRC_0_N

SOURCE PORT 0

DPSRC_AUX_P

DISPLAYPORT

GPIO_5/CIO_PLUG_EVENT

GPIO_8/EN_CIO_PWR_OD*

PB_CIO2_TX_P/DP_SRC_0_P PB_CIO2_TX_N/DP_SRC_0_N

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DP_SRC_2_P PB_CIO3_TX_N/DP_SRC_2_N

PORT3 PORT2

PORTS

DPSRC_AUX_N

DPSRC_HPD_OD

GPIO_2/GO2SX

(FORCE_PWR)

GPIO_4/WAKE_N_OD

GPIO_6/CIO_SDA_OD GPIO_7/CIO_SCL_OD

GPIO_9/OK2GO2SX_OD*

PB_LSTX/CIO_3_LSEO PB_LSRX/CIO_3_LSOE

GPIO_3

GPIO_14 GPIO_15

PB_CIO2_RX_P PB_CIO2_RX_N

PB_CIO3_RX_P PB_CIO3_RX_N

PB_DPSRC_1_P PB_DPSRC_1_N

PB_DPSRC_3_P PB_DPSRC_3_N

PB_AUX_P PB_AUX_N

PB_DPSRC_HPD

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

AD5

PCIE_TBT_D2R_C_P<0>

68

AD7

PCIE_TBT_D2R_C_N<0>

68

AD9

PCIE_TBT_D2R_C_P<1>

68

AD11

PCIE_TBT_D2R_C_N<1>

68

AD13

PCIE_TBT_D2R_C_P<2>

68

AD15

PCIE_TBT_D2R_C_N<2>

68

AD17

PCIE_TBT_D2R_C_P<3>

68

AD19

PCIE_TBT_D2R_C_N<3>

68

U20

TBT_RSENSE

W20

TBT_RBIAS

U4

NC

Not used in host mode.

N6

TP_TBT_PCIE_RESET0_L

T1

TP_TBT_PCIE_RESET1_L

Y5

TP_TBT_PCIE_RESET2_L

U2

TP_TBT_PCIE_RESET3_L

W6

=TBT_CLKREQ_L

K5

TBT_EN_LC_PWR

PCIE_CLK100M_TBT_P

AB21 AD21

PCIE_CLK100M_TBT_N

AA24

SYSCLK_CLK25M_TBT_R

68

AB23

TP_TBT_XTAL25OUT

AA4

TBT_TMU_CLK_OUT

Y3

TBT_TMU_CLK_IN

A14

TP_DP_TBTSRC_ML_CP<3>

B15

TP_DP_TBTSRC_ML_CN<3>

A12

TP_DP_TBTSRC_ML_CP<2>

B13

TP_DP_TBTSRC_ML_CN<2>

A10

TP_DP_TBTSRC_ML_CP<1>

B11

TP_DP_TBTSRC_ML_CN<1>

A8

TP_DP_TBTSRC_ML_CP<0>

B9

TP_DP_TBTSRC_ML_CN<0>

C2

TP_DP_TBTSRC_AUXCH_CP

D3

TP_DP_TBTSRC_AUXCH_CN

V3

DP_TBTSRC_HPD

Y1

TBT_GO2SX_BIDIR

W2

TBT_PWR_EN

J4

=TBT_WAKE_L

AA2

TBT_CIO_PLUG_EVENT

AB1

=I2C_TBTRTR_SDA

AC2

=I2C_TBTRTR_SCL

P3

(TBT_EN_CIO_PWR_L)

M5

TBT_GPIO_9

T3

TBT_GPIO_14

V5

TBT_DDC_XBAR_EN_L

R24

TBT_B_R2D_C_P<0>

N24

TBT_B_R2D_C_N<0>

R22

TBT_B_D2R_P<0>

N22

TBT_B_D2R_N<0>

P1

TBT_B_CONFIG1_BUF

H5

TBT_B_CONFIG2_RC

W24

TBT_B_R2D_C_P<1>

U24

TBT_B_R2D_C_N<1>

W22

TBT_B_D2R_P<1>

U22

TBT_B_D2R_N<1>

L6

TBT_B_LSTX

G6

TBT_B_LSRX

A20

DP_TBTPB_ML_C_P<1>

B21

DP_TBTPB_ML_C_N<1>

A22

DP_TBTPB_ML_C_P<3>

B23

DP_TBTPB_ML_C_N<3>

D1

DP_TBTPB_AUXCH_C_P

E2

DP_TBTPB_AUXCH_C_N

K3

DP_TBTPB_HPD

M1

TBT_B_HV_EN TBT_B_CIO_SEL TBT_B_DP_PWRDN

C3640

C3641

C3642

C3643

C3644

C3645

C3646

C3647

1

R3655

1K

1% 1/20W MF 201

2

OUT

IN IN

R3697

IN

IN OUT OUT

BI

IN

OUT

33

OUT

OUT OUT

IN

OUT

IN

OUT OUT

IN

OUT

IN

OUT OUT

BI

IN

OUT OUT OUT

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

PCIE_TBT_R2D_C_P<0>

8

68

IN

PCIE_TBT_R2D_C_N<0>

8

68

IN

PCIE_TBT_R2D_C_P<1>

8

68

IN

PCIE_TBT_R2D_C_N<1>

8

68

IN

PCIE_TBT_R2D_C_P<2>

8

68

D

=PP3V3_S4_TBT

7

33 34 35

1

R3610

47K

5%

1/20W

MF

201

2

35

IN

=PP3V3_TBTLC_RTR

1

3.3K

1/20W

1

R3691

3.3K

5%

5% 1/20W

MF

201

2

R3690

(TBT_SPI_MOSI)

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

TBTROM_WP_L

C

TBTROM_HOLD_L

7

33 34 35

1

2

C3690

1UF

5

6

1

3

7

20%

6.3V X5R 0201

D

C

S*

W*

HOLD*

8

VCC

U3690

M95256-RMC6XG

MLP

VSS 4

CRITICAL OMIT_TABLE

THM PAD

9

8

68

8

68

8

68

2

Q

IN

PCIE_TBT_R2D_C_N<2>

IN

PCIE_TBT_R2D_C_P<3>

IN

PCIE_TBT_R2D_C_N<3>

IN

(TBT_SPI_MISO)

R3692

3.3K

1/20W

1

5% MF

201

2

1

R3693

3.3K

5% 1/20W MF 201

2

C3600

C3601

C3602

C3603

C3604

C3605

C3606

C3607

NO STUFF

C3610

X5R-CERM

R3625

SNK0 AC Coupling

DP_TBTSNK0_ML_C_P<0>

8

68

IN

DP_TBTSNK0_ML_C_N<0>

8

68

IN

DP_TBTSNK0_ML_C_P<1>

8

68

IN

DP_TBTSNK0_ML_C_N<1>

8

68

IN

B

8

68

IN

8

68

IN

8

68

IN

8

68

IN

8

68

BI

8

68

BI

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

C3620

C3621

C3622

C3623

C3624

C3625

C3626

C3627

C3628

C3629

0.1UF

1 2

X5R-CERM

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_AUXCH_N

33 68

SNK1 AC Coupling

DP_TBTSNK1_ML_C_P<0>

8

68

IN

DP_TBTSNK1_ML_C_N<0>

8

68

IN

DP_TBTSNK1_ML_C_P<1>

8

68

IN

DP_TBTSNK1_ML_C_N<1>

8

68

IN

DP_TBTSNK1_ML_C_P<2>

8

68

A

IN

8

68

IN

8

68

IN

8

68

IN

8

68

BI

8

68

BI

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

C3630

C3631

C3632

C3633

C3634

C3635

C3636

C3637

C3638

C3639

0.1UF

1 2

X5R-CERM

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_AUXCH_N

33 68

6 3

35

16 68

100K

1/20W

19 33

19 25

41

19

43

33

8

33

8

33

0.1UF

5%

MF

201

69

1 2

PCIE_TBT_D2R_P<0>

16V10%

PCIE_TBT_D2R_N<0>

16V10%

PCIE_TBT_D2R_P<1>

16V10%

PCIE_TBT_D2R_N<1>

16V10%

PCIE_TBT_D2R_P<2>

16V10%

PCIE_TBT_D2R_N<2>

16V10%

PCIE_TBT_D2R_P<3>

16V10%

PCIE_TBT_D2R_N<3>

16V10%

X5R-CERM

0201

=PP3V3_TBTLC_RTR

35

OUT

1

2

NO STUFF

R3699

10K

1/20W

R3632

100K

1/16W MF-LF

5% MF

201

5%

402

1

R3698

10K

5% 1/20W MF 201

2

1

2

1

2

1 2

1

R3696

1K

5% 1/20W MF 201

2

R3695

1/20W

TBT_PWR_REQ_L

TBT_EN_CIO_PWR_L

MAKE_BASE=TRUE

8

68

OUT

8

68

OUT

8

68

OUT

8

68

OUT

8

68

OUT

8

68

OUT

8

68

OUT

8

68

OUT

NOTE: The following pins require testpoints: 0 - GPIO_13 1 - GPIO_1 2 - GPIO_2 3 - GPIO_3 4 - GPIO_5 5 - PCIE_RST_1_N 6 - PCIE_RST_2_N 7 - PCIE_RST_3_N

7

33 34 35

806

SYSCLK_CLK25M_TBT

1%

MF

201

18

OUT

35

OUT

SYNC_MASTER=J13_MLB

PAGE TITLE

=PP3V3_TBTLC_RTR

7

33 34 35

TBT_DDC_XBAR_EN_L

33

TBT_GO2SX_BIDIR

19 33

R3681 for CYA, allows separation of GPIO_2/GPIO_9 if necessary. Stuff one of R3861/2.

TBT_GPIO_9

33

TBT_GPIO_14

33

=PP3V3_S4_TBT

7

33 34 35

TBT_A_DP_PWRDN

33 63

TBT_B_DP_PWRDN

33

TBT_A_HV_EN

33 35 63

TBT_B_HV_EN

33

Thunderbolt Host (1 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

IN

8 - GPIO_15 9 - GPIO_11 10 - GPIO_14 11 - GPIO_0 12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

25 68

R3683

10K

1/20W

R3685

R3688

5%

MF

201

10K

1/20W

201

10K

1/20W

201

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

1

R3680

10K

5% 1/20W MF 201

2

1

R3681

0

5% 1/20W MF 201

2

NO STUFF

1

R3682

10K

5% 1/20W MF 201

2

1

R3686

10K

5%

5% 1/20W

MF

MF 201

2

1

R3687

10K

5%

5% 1/20W

MF

MF 201

2

SYNC_DATE=02/22/2012

051-9276

2.7.0

36 OF 109

33 OF 72

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

=PP1V05_TBTLC_RTR

7

???? mA (Single Port) 250 mA (Dual Port)

D

EDP: 1000 mA

C3700

10UF

6.3V

CERM-X5R

0402-1

C3701

10UF

6.3V

CERM-X5R

0402-1

20%

1

C3710

1.0UF

20%

6.3V

2

X5R 0201-MUR

1

2

1

2

C3730

1.0UF

20%

6.3V X5R 0201-MUR

1

2

C3729

1.0UF

20%

6.3V X5R 0201-MUR

1

C3732

2

1.0UF

20%

6.3V X5R 0201-MUR

1

2

C3712

1.0UF

20%

6.3V X5R 0201-MUR

1

C3713

1.0UF

2

1

C3718

1.0UF

2

20%

6.3V X5R 0201-MUR

20%

6.3V X5R 0201-MUR

C

B

A

1

C3714

1.0UF

2

20%

6.3V X5R 0201-MUR

AA14 AA20

AA22

AB11

AB17

AC10

AC12 AC14

AC16

AC18 AC20

AC22

J10 J12

J14

J16

J8

K17

T15 U14

V7 W8

G10

G12

G14 G16

G18

H19 K19

M19 P19

T19

V15 V19

W12

W14

G8

H9

AD1 K13

K9

L12 L16

L8

M13 M17

M9

N12 N16

N8 P13

P17

P9 R12

R16

R8 T13

T17

T9 U12

U16

U8

V9

A2

A24

AA8

AB7

AC4 AC6

AC8

B1

B7

C10 C12

C14

C16 C18

C20

VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0_DPAUX VCC1P0_DPAUX

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

CRITICAL

OMIT_TABLE

U3600

CACTUSRIDGE4C

FCBGA

(SYM 2 OF 2)

VCCGND

VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0

VCC3P3 VCC3P3 VCC3P3

VCC3P3_CIO VCC3P3_CIO VCC3P3_CIO

VCC3P3_DP VCC3P3_DP VCC3P3_DP VCC3P3_DP

VCC3P3_DPAUX

VCC3P3_POC

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

K11 K15

L10

L14 M11

M15

N10 N14

P11 P15

R10

R14 T11

U10

V11 W10

M7 P7

T7

L18 N18

R18

H11

H13 H15

H17

H7

K7

C22 C24

C4

C6 C8

D21 D23

E4

F11 F13

F15

F17 F19

F21

F23 F5

F7 F9

G20

H21 H23

J18

J20 K21

K23

L20 M21

M23 N20

P21

P23 R20

T21

T23 U18

V13

V17 V21

V23 Y11

Y13

Y15 Y17

Y19

Y21 Y23

Y9

C3740

1.0UF

6.3V

0201-MUR

C3770

1.0UF

6.3V

0201-MUR

C3790

1.0UF

6.3V

0201-MUR

20% X5R

1

2

1

2

=PP3V3_S4_TBT

EDP: 10 mA

1

2

C3741

1.0UF

6.3V

0201-MUR

C3771

1.0UF

6.3V

0201-MUR

1

20%

2

X5R

1

20%

2

X5R

C3742

1.0UF

6.3V

0201-MUR

C3772

1.0UF

6.3V

0201-MUR

7

20% X5R

X5R

33 35

1

2

1

2

C3743

1.0UF

0201-MUR

C3773

1.0UF

0201-MUR

6.3V

1

20%

2

X5R

1

20%

2

X5R

C3744

1.0UF

6.3V

0201-MUR

C3774

1.0UF

6.3V

0201-MUR

1

20%

2

X5R

1

20%

2

X5R

C3745

1.0UF

6.3V

0201-MUR

1

2

1

20%

2

X5R

??? mA (Single-Port) 250 mA (Dual-Port)

C3760

10UF

20%20%

6.3V CERM-X5R 0402-1

EDP: 240 mA

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

=PP1V05_TBTCIO_RTR

???? mA (Single-Port) 2700 mA (Dual-Port) EDP: 3000 mA

1

C3705

10UF

20%

6.3V

2

CERM-X5R 0402-1

=PP3V3_TBTLC_RTR

7

33 35

Thunderbolt Host (2 of 2)

Apple Inc.

R

6 3

12

7

SYNC_DATE=09/01/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

37 OF 109

SHEET

34 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP18V_TBT_REG (18V Boost Output)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP1V05_TBT_FET (1.05V FET Output)

Signal aliases required by this page:

- =TBT_CLKREQ_L

D

- =TBT_RESET_L

BOM options provided by this page: TBTBST:Y - Stuffs 18V boost circuitry.

C

=PP3V3_S0_TBTPWRCTL

7

Q3840

SSM3K15AMFVAPE

TBT_EN_LC_PWR

33

IN

=TBT_RESET_L

25

IN

Platform (PCIe) Reset

TBT_CLKREQ_L

16

OUT

VESM

D

3

Pull-up provided by SB page.

B

=PP3V3_S0_P3V3TBTFET

7 7

TBT_EN_LC_ISOL

1

R3816

36.5K

1%

1/20W

MF

201

2

TBT_EN_LC_RC1V05

=PP1V05_S0_P1V05TBTFET

35

7

A

C3810

1.0UF

X5R-CERM

C3815

1.0UF

X5R-CERM

Supervisor & CLKREQ# Isolation

1

C3800

0.1UF

1

R3840

10% 16V

10K

5%

1

1/20W MF

GS

201

2

X5R-CERM

0201

2

3

6

8

U3800

SLG4AP016V

DLY

MR*

EN OUT

(OD)

GND

5

VDD

TDFN

1

+

-

THRM

PAD

3.3V TBT "LC" Switch

U3810

TPS22924

A2

VIN

TBT_EN_LC_RC3V3

1

1.0UF

10%

6.3V

2

X5R-CERM 02010201

B2

CRITICAL

C2

ON

NO STUFF

C3811

GND

R3811

0

12

5%

1

10%

6.3V

2

1/20W

MF

201

1.05V TBT "LC" Switch

U3815

10%

6.3V

0201

C3816

1.0UF

X5R-CERM

TPS22924

CSP

A2

B2

1

C2

2

1

10%

6.3V

2

0201

VOUT

VIN

CRITICAL

ON

GND

C1

C3816 must be 10%

RC guarantees minimum 5ms to reach 0.5V

=PP1V05_TBTLC_FET

A1

Max Current = 2A (85C)

B1

CRITICAL

SENSE

0.7V

RESET*

IN

9

CSP

VOUT

C1

=PPVIN_SW_TBTBST

7

8-13V Input Changes required for 2S.

63 33

IN

=PP3V3_TBTLC_RTR

1

R3807

100K

5% 1/20W MF 201

2

4

DLY = 60 ms +/- 20%

7

MAKE_BASE=TRUE

=PP3V3_TBTLC_FET

A1

Max Current = 2A (85C)

B1

Part

Type

R(on) @ 1.0V

R3880

470K

1/20W

201

R3881

150K

1/20W

201

Q3805

SSM3K15FV

SOD-VESM-HF

TBT_A_HV_EN

PP1V05_TBTLC

TBT_PCIE_RESET_L

=TBT_CLKREQ_L TBT_CLKREQ_ISOL_L

Part

Type

R(on) @ 2.5V

7

U3815

TPS22924C

Load Switch

20.3 mOhm Typ

28.6 mOhm Max

SI8409DB:

1

5%

MF

2

1

5% MF

2

TBTBST_PWREN_L

1

7

7 6

1

C3880

0.1UF

10% 25V

2

X5R 402

TBTBST_PWREN_DIV_L

3

D

G S

2

35 34 33

33

OUT

33

IN

U3810

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

CRITICAL

Q3880

SI8409DB

4

SGD

1

C3881

2.2UF

20% 10V

2

X5R-CERM

402

C3882

1

R3892

73.2K

1% 1/20W MF 201

2

<R2>

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

35 34 33

2.2UF

X5R-CERM

=PP1V05_S0_P1V05TBTFET

35

7

=PP3V3_TBTLC_RTR

7

Vds(max): -30V Vgs(max): +/-12V Vgs(th): -1.4V Rds(on): 46mOhm @ 4.5V Vgs Id(max): 3.7A @ 70C

BGA

2 3

C3892

2.2UF

20% 10V

X5R-CERM

402

1

20% 10V

2

402

R3820

Q3825

SSM6N37FEAPE

SOT563

2

33

IN

TBT_EN_CIO_PWR_L

PPVIN_SW_TBTBST

7 6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

Voltage not specified here, add property on another page.

1

2

1

C3887

47PF

5% 25V

2

NP0-C0G 201

TBTBST_VC_RC

1

C3893

3300PF

10% 10V

2

X7R 201

=PP3V3_S4_TBT

34 33

7

TBTPOCRST_CT

1

C3831

0.0047UF

10% 25V

2

CERM 402

1

100K

5%

1/20W

MF

201

2

TBT_EN_CIO_PWR

6

D

SG

1

C3890

10UF

X5R-CERM

1

2

TBTBST_EN_UVLO

TBTBST_INTVCC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_VC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_RT

TBTBST_SS

1

C3894

0.33UF

10%

6.3V

2

CERM-X5R 402

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

Q3888

SSM6N37FEAPE

SOT563

2

TBTBST_SHDN_DIV

1

R3887

330K

5% 1/20W MF 201

2

SENSE

U3830

TPS3808

CT

GND

5

0603

Max Vgs: 10V

R3891

200K

1%

1/20W

MF

201

<R1>

1

R3893

10K

1%

1/20W

MF

201

2

1

R3894

41.2K

1%

1/20W

MF

201

2

6

D

S G

1

TBT "POC" Power-up Reset

Intel investigating whether RC is sufficient.

3

1

C3830

0.1UF

10% 16V

2

X5R-CERM

0201

1.05V TBT "CIO" Switch

U3820

TPS22920

A2

B2

VIN

C2

CRITICAL

D2

ON

1

C3820

1.0UF

10%

6.3V

2

X5R-CERM

0201

TBT 15V Boost Regulator

1

20% 25V

2

C3891

10UF

X5R-CERM

1

20% 25V

2

0603

25

EN/UVLO

28

INTVCC

30

VC

33

RT

32

SS

34

SYNC

6.8UH-4.0A

1 2

27

VIN

CRITICAL

L3895

PIMB062D-SM

8

U3890

LT3957

QFN

9

SGND

C3825

330PF

1213141516

1

C3825 value may need tuning

10% 16V

2

X7R 201

7

U3820

TPS22920

Load Switch

8 mOhm Typ

11.5 mOhm Max

1

VDD

QFN

CSP

GND

D1

CRITICAL

THRM

PAD

VOUT

62

RESET*

(IPU)

4

MR*

7

TPS3808G25 Vt = 2.33V +/- 2% Delay = 27.3ms

A1

B1

C1

232437

4

SGND shorted to GND inside package, no XW necessary.

1

R3888

330K

5% 1/20W MF 201

2

3

D

Q3888

SSM6N37FEAPE

SOT563

5

S G

4

Pull-up: R3610

TBT_PWR_ON_POC_RST_L

TBTPOCRST_MR_L

=PP1V05_TBTCIO_FET

Max Current = 4A (85C)

Part

Type

R(on) @ 1.05V

GND

SSM6N37FEAPE

6 3

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

202138

SW

SNS1

SNS2

NC

FBX

17

DIDT=TRUE

6

3

1

2

10 35

36

31

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm

NC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

NO STUFF

1

C3889

2

TBTBST_SNS1

1

TBTBST_VSNS_RC

2

100PF

5% 50V CERM 402

Vout = 1.6V * (1 + Ra / Rb)

SMC_DELAYED_PWRGD

33

OUT

Q3825

SOT563

3

5

D

S G

4

R3889

TBTBST_SNS2

R3890

49.9K

1 2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1% 1/16W MF-LF

402

22PF

5% 50V CERM 402

R3895

C3888

TBTBST_FBX

R3896

=PP3V3_S0_PCH_GPIO

1

R3830

100K

5% 1/20W MF 201

2

TBT_SW_RESET_L

1

0

5%

1/20W

MF

201

2

TBTBST_VSNS

1

133K

1% 1/16W MF-LF

402

2

<Ra>

1

15.8K

1% 1/16W MF-LF

402

2

<Rb>

IN

CRITICAL

A

D3895

POWERDI-123

DFLS230L

K

XW3895

SM

12

PLACE_NEAR=C3895.1:2 mm

1

C3895

10UF

20% 25V

2

X5R-CERM 0603

1

C3896

10UF

20% 25V

2

X5R-CERM

0603

41 40 25

7

19

IN

SYNC_MASTER=J13_MLB

PAGE TITLE

C3897

10UF

X5R-CERM

C389A

20% 25V

0603

X5R-CERM

10UF

25 19 18 17 16

0603

1

2

20% 25V

C389B

10UF

X5R-CERM

1

2

1

20% 25V

2

0603

1

2

TBT Power Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

=PP15V_TBT_REG

Vout = 15.1V Max Current = 1.0A Freq = 300KHz

1

C3898

C3884

10UF

20%

25V

2

X5R-CERM

0603

1

C3885

10UF

20% 25V

2

X5R-CERM 0603

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

38 OF 109

SHEET

35 OF 72

124578

7

1

C3899

0.001UF

10% 50V

2

X7R 402

SIZE

D

C

B

A

D

8 7 6 5 4 3

3V S3 WLAN FET

MOSFET

CHANNEL

RDS(ON)

LOADING

12

DMP2018LFK

P-TYPE

14-20 mOHM @2.5V

0.750 A (EDP)

D

CRITICAL

R4052

0.020

1%

MIN_LINE_WIDTH=1 mm

R4018

0

5%

1/20W

MF

201

C4011

0.01UF

10% 16V

CERM

402

CRITICAL

U4002

SLG4AP016V

SENSE

0.7V

RESET*

IN

THRM

PAD

0.25W MF-LF

805

1 2 3 4

1

2

1

2

1

VDD

TDFN +

-

DLY

GND

9

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_WLAN_R

ISNS_AIRPORT_P ISNS_AIRPORT_N

9

1

2

10

VCC

Y+ Y-

U4010

PI3USB102ZLE

TQFN

CRITICAL

SEL OE*

GND

3

C4053

0.1UF

3

MR*

6

EN

8

OUT

(OD)

5

=PP3V3_S3_WLAN

1

10%

6.3V

2

X5R 201

AIRPORT

CRITICAL

J4001

SSD-K99

F-RT-SM1

1 2 3 4 5 6 7 8 9 10

C

11 12

13 14 15 16 17 18

19 20 21

PCIE_AP_R2D_N

6

68

6

68

PCIE_AP_R2D_P

C4030

PLACEMENT_NOTE=Place close to J4001.

1 2

6.3V

0.1UF

201 X5R10%

0.1UF

PLACEMENT_NOTE=Place close to J4001.

C4031

1 2

6.3V

10% 201X5R

514S0335

BLUETOOTH

BTPWR:S4

R4001

0

PP3V3_S3RS4_BT_F

6

36

B

PLACE_NEAR=J4001.18:1.5mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=3.3V

1

C4032

0.1UF

10%

6.3V

2

X5R 201

A

1 2

5% 1/16W MF-LF

402

BTPWR:S3

R4002

0

1 2

5% 1/16W MF-LF

402

=PP3V3_S4_BT

=PP3V3_S3_BT

7

WIFI_EVENT_L

PCIE_AP_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

PCIE_AP_D2R_P PCIE_AP_D2R_N

PCIE_WAKE_L

USB_BT_CONN_N

6

67

USB_BT_CONN_P

6

67

PP3V3_WLAN_F

6

36 41

OUT

OUT OUT

OUT

R4053

100K

1/20W

IN

201

6

40 41

16 68

6

16 68

6

16 68

6

16 68

6

16 68

6

17

17 26 40 48 61

1

5% MF

2

R4054

232K

1/20W

201

R4055

100K

1/20W

201

1

1% MF

2

1

1% MF

2

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

36 41

1

C4021

0.1UF

10%

6.3V 2

X5R 201

PLACEMENT_NOTE=Place close to Q4050.

1

R4015

15K

1% 1/20W MF 201

2

IN

PM_SLP_S4_L

1 2

DLY = 60 MS +/- 20%

P3V3WLAN_VMON AP_RESET_CONN_L

6

AP_CLKREQ_Q_L

6

PP3V3_WLAN_F

6

1

C4020

10UF

20% 10V

2

X5R 603

PLACEMENT_NOTE=Place close to Q4050.

1% 1/20W MF 201

1/20W

BTPWR:S3

0

BTMUX_SEL

5%

NOSTUFF

MF

201

NOSTUFF

1

R4017

15K

2

NOSTUFFNOSTUFF

1

R4016

15K

2

BTPWR:S4

R4011

2

4

7

6 3

CRITICAL

Q4050

DMP2018LFK

DFN2563-6

4

C4050

0.1UF

1 2

10% 16V

X5R-CERM

0201

OUT OUT

PP3V3_S3RS4_BT_F

1

2

5

USB_BT_WAKE_P

67

M+

4

USB_BT_WAKE_N

67

M-

7

D+ D-

USB_BT_P

6

USB_BT_N

8

SEL OUTPUT

L USB_BT_WAKE H USB_BT

D

S

2 1

45 71

C4010

0.1UF

10%

6.3V X5R 201

G

3

0.033UF

P3V3WLAN_SS

7

36

C4051

10% 16V X5R 402

6

36

24 67

BI

24 67

BI

1

2

1

2

BTPWR:S4

R4050

1 2

R4012

15K

1% 1/20W MF 201

100K

AP_RESET_L

AP_PWR_EN

AP_CLKREQ_L_R

SYNC_MASTER=J13_MLB

PAGE TITLE

X21 WIRELESS CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

5%

1/20W

MF

201

IN

NOSTUFF

1

R4014

15K

1% 1/20W MF 201

2

NOSTUFF

1

R4013

15K

1% 1/20W MF 201

2

25

18 23 61

R4090

0

5%

1/20W

MF

201

1

R4051

10K

5% 1/20W MF 201

2

BTPWR:S4

SSM3K15FV

SOD-VESM-HF

12

AP_CLKREQ_L

=PP3V3_S3_WLAN

PM_WLAN_EN_L

Q4010

1

G S

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

SHEET

124578

IN

=BT_WAKE_L

3

D

2

16

OUT

SYNC_DATE=10/06/2011

2.7.0

40 OF 109

36 OF 72

D

7

36

61

41

C

OUT

B

A

SIZE

D

8 7 6 5 4 3

12

D

CRITICAL

60 61

R4599

0.002

1% 1W MF

0612

12 34

=PP3V3_S0_SSD

ISNS_SSD_P ISNS_SSD_N

=PP3V3_S0_SATAMUX

7

OUT OUT

1

R4505

470K

5% 1/20W MF 201

2

SATAMUX_EN_L

1

R4510

10K

5% 1/20W MF 201

2

45 71

U4510

CBTL02043ABQ

3

A0_P

4

A0_N

7

A1_P

8

A1_N

9

SEL

2

XSD

1610

VDD

VQFN

CRITICAL

VSS

5

11

20

353S3361

21

THRM

PAD

B0_P B0_N

B1_P B1_N

C0_P C0_N

C1_P C1_N

1

2

C4505

0.1UF

10% 10V X5R-CERM 0201

19 18

17 16

15 14

13 12

1

C4514

0.1UF

10% 10V

2

X5R-CERM 0201

PLACE_NEAR=U4510.1:2 mm

PLACE_NEAR=U4510.10:2 mm

PLACE_NEAR=U4510.6:2 mm

PCIE_SSD_R2D_MUX_IN_P

65

PCIE_SSD_R2D_MUX_IN_N

65

SATA_SSD_R2D_MUX_IN_P

67

SATA_SSD_R2D_MUX_IN_N

67

1

C4519

0.01UF

10% 16V

2

X5R-CERM 0201

PCIE_SSD_D2R_MUX_OUT_P

65

PCIE_SSD_D2R_MUX_OUT_N

65

SATA_SSD_D2R_MUX_OUT_P

67

SATA_SSD_D2R_MUX_OUT_N

67

C4518

C4517

C4513

C4512

0.1UF

C4516

C4515

C4511

C4510

1 2

0.01UF

16V

X5R-CERM

16V

X5R-CERM

16V

X5R-CERM

16V

X5R-CERM

1 2

PCIE_SSD_D2R_P<0>

0201

PCIE_SSD_D2R_N<0>

0201

PCIE_SSD_R2D_C_P<0>

0201

PCIE_SSD_R2D_C_N<0>

0201

10%

10% 16V

16V X5R-CERM

16V

X5R-CERM

10%

SATA_HDD_D2R_P

0201

SATA_HDD_D2R_N

0201

SATA_HDD_R2D_C_P

0201

SATA_HDD_R2D_C_N

0201

8

65

OUT

8

65

OUT

8

65

IN

8

65

IN

16 67

OUT

16 67

OUT

16 67

IN

16 67

IN

PLACE_NEAR=J4501.1:3mm

CRITICAL

L4500

PP3V3_S0_SSD_FLT

6

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.150mm VOLTAGE=3.3V

NOSTUFF

1

C4504

2

100UF

20%

6.3V CERM-X5R 1206-1

1

C4503

2

100UF

20%

6.3V CERM-X5R 1206-1

FERR-70-OHM-4A

1 2

1

C4501

0.1UF

10% 10V

2

X5R-CERM 0201

0603

PP3V3_S0_SSD_R

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.150mm VOLTAGE=3.3V

1

C4502

0.1UF

10% 10V

2

X5R-CERM 0201

514S0393

C

B

CRITICAL

J4501

SSD-J5

F-RT-SM

1 2 3 4

GND_VOID=TRUE

5

GND_VOID=TRUE

6 7

GND_VOID=TRUE

8

GND_VOID=TRUE

9 10

GND_VOID=TRUE

11

GND_VOID=TRUE

12 13

GND_VOID=TRUE

14

GND_VOID=TRUE

15 16 17 18

19 20 21 22 23 24 25 26

27 28 29 30 31 32 33 34 35

Per PCIe Spec, only TX side should have AC cap

65

67

6

67

6

67

PCIE_SSD_R2D_P<1>

6

65

PCIE_SSD_R2D_N<1>

6

SATA_SSD_R2D_P

6

SATA_SSD_R2D_N

6

SATA_SSD_D2R_P

SATA_SSD_D2R_N

0.1UF

C4520

X5R-CERM

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

SSD_CLKREQ_L SSD_RESET_L SATA_PCIE_SEL

6

SMC_OOB1_RX_L SMC_OOB1_TX_L

SSD_P3V3S0_EN

6

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

C4521

1 2

0.1UF

X5R-CERM

10% 16V

IN IN

OUT

IN

OUT OUT

1 2

0201

6 8

65

6 8

65

PCIE_SSD_R2D_C_P<1>

0201

16V10%

PCIE_SSD_R2D_C_N<1>

6

16 65

6

16 65

6

16

6

25

6

40

R4520

6

40

41

0

1 2

5%

1/20W

MF

201

IN

=P3V3S0_EN

8

65

8

65

IN

D

C

B

PCIE/SATA GUMSTICK2 CONNECTOR

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

SSD CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

45 OF 109

SHEET

37 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

Right USB Port A

12

D

=PP5V_S3_RTUSB

7

USB_EXTA_OC_L

23

OUT

=USB_PWR_EN

6

39 61

1

C4690

10UF

6.3V

CERM-X5R

0402-2

20%

C4691

0.1UF

10% 16V

2

X5R-CERM 0201

Current limit per port (R4600): 2.18A min / 2.63A max

C

Mojo SMC Debug Mux

=PP3V42_G3H_SMCUSBMUX

7

MOJO:YES

SMC_DEBUGPRT_RX_L

40 41 67

IN

SMC_DEBUGPRT_TX_L

40 41 67

OUT

USB_EXTA_P

18 67

BI

USB_EXTA_N

18 67

BI

B

C4650

0.1UF

X5R-CERM

0201

1

10% 10V

2

5

M+

4

M-

PI3USB102ZLE

7

D+

6

D-

MOJO:YES

8

USB Port Power Switch

CRITICAL

U4600

TPS2561DR

SON

2

IN_0 IN_1

FAULT1* FAULT2*

EN1 EN2

GND

1

THRM

PAD

11

OUT1 OUT2

ILIM

CRITICAL

1

C4696

220UF-35MOHM

20%

6.3V

2

POLY-TANT CASE-B2-SM1

9

VCC

Y+

U4650

CRITICAL

Y-

TQFN

SELOE*

GND

3

SIGNAL_MODEL=MOJO_MUX

1 2

10

USB_EN2

R4601

1/20W

NC

1

0

5%

MF

201

2

3

10

6

4

5

MOJO:YES

1

R4650

10K

5% 1/20W MF 201

2

SMC_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB

9

8

7

NC

USB_ILIM

R4600

23.2K

1/16W MF-LF

IN

CRITICAL

L4605

FERR-120-OHM-3A

1

2

L2

L1

0504

L2

L1

1 2

0603

CRITICAL

L4600

90-OHM DLP0NS

SYM_VER-1

1 2

3

2

3

2

ESD0P2RF-02LS

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

34

CRITICAL

D4621

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4611

TSSLP-2-1

6

VBUS

1

GND

RCLAMP0582N

2

1

2

1

67

67 67

452 3

NC

IO

D4600

SLP1210N6

CRITICAL

2

D4620

ESD0P2RF-02LS

TSSLP-2-1

1

CRITICAL

D4610

ESD0P2RF-02LS

TSSLP-2-1

USB2_EXTA_MUXED_F_N USB2_EXTA_MUXED_F_P

67

USB3_EXTA_RX_F_P USB3_EXTA_RX_F_N

67

USB3_EXTA_TX_F_P USB3_EXTA_TX_F_N

CRITICAL

J4600

USB3.0-J11-J13

F-RT-TH

1

VBUS

2

SSTX+

3

SSTX-

4

GND

5

D-

6

D+

7

GND

8

SXRX+

9

SSRX-

10

GND

11 12 13 14 15 16 17 18

APN: 514-0819

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=5V

1

1%

402

2

40

C4695

10UF

6.3V

CERM-X5R

0402-2

1

20%

2

GND_VOID=TRUE

C4620

0.1UF

18 67

IN

18 67

IN

USB3_EXTA_TX_N

USB3_EXTA_TX_P

1 2

10% X5R

67

6.3V 201

GND_VOID=TRUE

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

0.1UF

1 2

10% X5R

OUT

USB3_EXTA_RX_N

USB3_EXTA_RX_P

67

USB3_EXTA_TX_C_N

67

USB3_EXTA_TX_C_P

6.3V 201

18 67

C4621

C4605

0.01UF

10% 16V

X5R-CERM

0201

GND_VOID=TRUE

CRITICAL

L4610

80OHM-25%-100MA

0504

4

1

GND_VOID=TRUE

CRITICAL

L4620

80OHM-25%-100MA

4

1

D

C

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

External A USB3 Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/06/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

46 OF 109

SHEET

38 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP3V3_S0_AUDIO

6 7

1

C4700

0.1UF

10% 16V

PLACE_NEAR=J4700.5:1.5mm

2

X5R-CERM

0201

SPKRAMP_INR_P

6

50

C

=PP3V3R1V5_S0_AUDIO

PLACE_NEAR=J4700.7:1.5mm

C4720

0.1UF

10% 16V

X5R-CERM

0201

PLACE_NEAR=J4700.9:1.5mm

1

2

C4710

0.1UF

10% 16V

X5R-CERM

0201

6 7

1

2

71

SPKRAMP_INR_N

6

50

71

=PP3V42_G3H_ONEWIRE

6 7

AUD_GPIO_3

6

50

=I2C_MIKEY_SCL

6

43

=I2C_MIKEY_SDA

6

43

AUD_IP_PERIPHERAL_DET

6

18

=I2C_LIO_SCL

6

43

=I2C_LIO_SDA

6

43

HDA_RST_L

6

16 68

HDA_SDIN0

6

16 68

HDA_BIT_CLK

6

16 68

HDA_SYNC

6

16 68

HDA_SDOUT

6

16 68

B

LIO CONNECTOR

998-4617 (HIROSE 3.0mm RCPT)

CRITICAL

J4700

DF40CG3.0-48DS-0.4V

F-ST-SM

49

50

2

1

4

3 5

6

7 8

10

9 11 12 13 14 15 16

19 21 22 23 24 25 26 27 28 29 31 32

35 36 37 38 39 41 42 43 44 45 46 47 48

51 52

6

67

6

67

20

30

AUD_IPHS_SWITCH_EN

40

USB_EXTB_P USB_EXTB_N

GND_VOID=TRUE

USB3_EXTB_RX_RC_N USB3_EXTB_RX_RC_P

GND_VOID=TRUE

USB_CAMERA_P USB_CAMERA_N

GND_VOID=TRUE

USB3_EXTB_TX_C_N USB3_EXTB_TX_C_P

GND_VOID=TRUE

AUD_I2C_INT_L

=USB_PWR_EN

USB_EXTB_OC_L

SMC_BC_ACOK SYS_ONEWIRE

6

24 67

6

18 67

25

18

6

23

6

ESD0P2RF-02LS

38 61

40 41

40

CRITICAL

D4711

TSSLP-2-1

2

1

CRITICAL

2

D4710

ESD0P2RF-02LS

TSSLP-2-1

1

CRITICAL

D4720

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

R4710

0

1 2

201

5%

1/20W MF

NOSTUFF

C4731

GND_VOID=TRUE

1 2

X5R-CERM

0201

10% 16V

0.1UF

NOSTUFF

C4732

GND_VOID=TRUE

10%

X5R-CERM

1 2

16V

0201

0.1UF

GND_VOID=TRUE

R4720

0

1 2

201

5%

1/20W MF

C4721

GND_VOID=TRUE

1 2

X5R-CERM

0201

10% 16V

0.1UF

2

1

D4721

ESD0P2RF-02LS

TSSLP-2-1

1

ON MLB SIDE AS LIO CAN’T FIT CAPS

CRITICAL

2

X5R-CERM 10% 16V

C4722

GND_VOID=TRUE

1 2

0201

0.1UF

USB3_EXTB_RX_N

USB3_EXTB_RX_P

USB3_EXTB_TX_N

USB3_EXTB_TX_P

18 67

D

C

B

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

LIO CONNECTORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

47 OF 109

SHEET

39 OF 72

124578

SYNC_DATE=N/A

SIZE

A

D

8 7 6 5 4 3

12

D

U4900

LM4FSXAH5BB

BGA

(1 OF 2)

OMIT_TABLE

T3CCP1/PJ5/C2T3CCP0/PJ4/C2+

AIN00 AIN01 AIN02 AIN03 AIN04 AIN05 AIN06 AIN07 AIN08 AIN09 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 AIN17 AIN18 AIN19 AIN20 AIN21 AIN22 AIN23

PC5/C1+

SSI0CLK/PA2 SSI0FSS/PA3

SSI0RX/PA4 SSI0TX/PA5

U1RX/B0

U1TX/PB1 T0CCP0/PB6 T0CCP1/PB7

SSI1RX/PF0 SSI1TX/PF1

SSI1CLK/PF2 SSI1FSS/PF3

WT0CCP0/PG4 WT0CCP1/PG5

WT2CCP0/PH0 WT2CCP1/PH1

WT3CCP0/PH4 WT3CCP1/PH5 WT4CCP0/PH6 WT4CCP1/PH7

T1CCP0/PJ0 T1CCP1/PJ1 T2CCP0/PJ2 T2CCP1/PJ3

WT5CCP1/PM3

C0C0+ C1-

PF4 PF5

E2 E1 F2 F1 B3 A3 B4 A4 B5 A5 B6 A6 C1 C2 B1 B2 G2 G1 H1 H2 B7 A7 B8 A8

K2 K1 L2 L1 C5 D5

M2 M3 L4 N1

F11 E11 F4 F3

M9 N9 L10 K10 L9 K9

K7 L7

K3 K4

J3 H4 H3 G4

C9 B9 A9 C8

H10

SMC_ADC0 SMC_ADC1 SMC_ADC2 SMC_ADC3 SMC_ADC4 SMC_ADC5 SMC_ADC6 SMC_ADC7 SMC_ADC8 SMC_ADC9 SMC_ADC10 SMC_ADC11 SMC_ADC12 SMC_ADC13 SMC_ADC14 SMC_ADC15 SMC_ADC16 SMC_ADC17 SMC_ADC18 SMC_ADC19 SMC_ADC20 SMC_ADC21 SMC_ADC22 SMC_ADC23

CPU_PROCHOT_L SMC_VCCIO_CPU_DIV2 SMC_S5_PWRGD_VIN

SPI_DESCRIPTOR_OVERRIDE_L

CPU_CATERR_L CPU_THRMTRIP_3V3

SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L SMC_SYS_LED SMC_GFX_THROTTLE_L

SPI_SMC_MISO SPI_SMC_MOSI SPI_SMC_CLK SPI_SMC_CS_L S5_PWRGD PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L SMC_GFX_OVERTEMP

ALL_SYS_PWRGD SMC_THRMTRIP

PM_PWRBTN_L PM_SYSRST_L MEM_EVENT_L SMC_ADAPTER_EN

SMC_OOB1_RX_L SMC_OOB1_TX_L IR_RX_OUT_RC BDV_BKL_PWM

NC FOR STACK BRD

1.2V FOR ENG PKG

NC FOR STACK BRD

(OD)

NC FOR ENG PKG

SMC_BATLOW_L

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN

OUT

IN IN

OUT OUT OUT OUT

IN OUT OUT

IN OUT OUT OUT

IN

OUT

IN

IN OUT

OUT OUT

IN

IN OUT

OUT

BI

41

10 41 56 65

41

25

10 65

41

61

17

25 35 41

41

38 41 67

8

41

41 68

61

17 23 25

38

41

23 25 51 61

41

17 23

17 25

41

17 41 61

6

37

6

37 41

8

41

41 61

=PP3V3_S5_SMC

1

C4902

1UF

20%

6.3V

2

X5R 0201

1

C4903

0.1UF

10% 10V

2

X5R-CERM 0201

1

C4907

0.1UF

10% 10V

2

X5R-CERM 0201

7

41

L4901

30-OHM-1.7A

1

C4904

0.1UF

10% 10V

2

X5R-CERM 0201

1

C4908

0.1UF

10% 10V

2

X5R-CERM 0201

1

C4905

0.1UF

10% 10V

2

X5R-CERM 0201

1

C4909

0.1UF

10% 10V

2

X5R-CERM 0201

1

C4906

0.1UF

10% 10V

2

X5R-CERM 0201

1

R4902

1M

5% 1/20W MF 201

2

SMC_RESET_L

6

41 42 52

IN

WIFI_EVENT_L

6

36 41

BI

SMC_WAKE_L NC_SMC_HIB_L

SMC_CLK32K

41 68

IN

NC_SMC_XOSC1

SMC_EXTAL

41

SMC_XTAL

41

PP1V2_S5_SMC_VDDC

41

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V

1

C4910

1.0UF

20% 10V

2

X5R-CERM 0201-1

NOSTUFF

1

2

C4911

1.0UF

20% 10V X5R-CERM 0201-1

1 2

0402

G10 C10

B11

(OD)

N13 M12

M10

N10

G12

G13

K12

D7 E6 E8 E9

F10

J7 J9

J10

J1 J6

K13

D6

1

C4912

1.0UF

20% 10V

2

X5R-CERM 0201-1

U4900

LM4FSXAH5BB

(2 OF 2)

RST*

PK4/RTCCLK WAKE* HIB*

XOSC0 XOSC1

OSC0 OSC1

VBAT

OMIT_TABLE

VDD

VDDC

1

C4913

0.1UF

10% 10V

2

X5R-CERM 0201

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V

BGA

SWCLK/TCK SWDIO/TMS

SWO/TDO

VDDA

VREFA+ VREFA-

GNDA

GND

1

C4914

0.1UF

10% 10V

2

X5R-CERM 0201

TDI

A10 A11 B10

A2

NC

D3

D2 D1

45 44

C3

41

E3

A1 C7 D9 E5 F9 H5 H9 J5 J8 J11 K11

SMC_TCK SMC_TMS SMC_TDO SMC_TDI

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

PLACE_NEAR=U4900.D2:1MM PLACE_NEAR=U4900.D1:1MM

1

C4915

0.1UF

10% 10V

2

X5R-CERM 0201

1

C4916

0.1UF

10% 10V

2

X5R-CERM

1

C4901

0.1UF

10% 10V

2

X5R-CERM 0201

6

41 42

6

41 42

6

41 42

6

41 42

41

XW4900

PLACE_NEAR=U4900.A1:4MM

1

C4920

0.01UF

10% 10V

2

X5R 201

1

C4917

0.1UF

10% 10V

2

X5R-CERM 02010201

SM

12

1

C4921

1UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U4900.D2:1MM PLACE_NEAR=U4900.D1:1MM

NC NC

B13

LPC0AD0

A13

LPC0AD1

C12

LPC0AD2

D11

LPC0AD3

H12

LPC0CLK

D12

LPC0FRAME*

C13

LPC0RESET*

H13

LPC0SERIRQ

G11

LPC0CLKRUN*

F13

LPC0PD*

F12

LPC0SCI*

B12

PK5

E10

I2C0SCL

D13

I2C0SDA

M4

I2C1SCL

N2

I2C1SDA

N8

I2C2SCL

M8

I2C2SDA

L8

I2C3SCL

K8

I2C3SDA

N7

I2C4SCL

M7

I2C4SDA

N4

I2C5SCL

N3

I2C5SDA

H11

PM6/FAN0PWM0

L13

PM7/FAN0TACH0

C11

PK6/FAN0PWM1

A12

PK7/FAN0TACH1

G3

PN2/FAN0PWM2

D10

PN3/FAN0TACH2

L11

PN4/FAN0PWM3

N12

PN5/FAN0TACH3

N11

PN6/FAN0PWM4

M11

PN7/FAN0TACH4

J4

PH2/FAN0PWM5

J2

PH3/FAN0TACH5

C4

PECI0RX

C6

PECI0TX

M13

PP0/IRQ116

L12

PP1/IRQ117

M5

PP2/IRQ118

J12

PP3/IRQ119

J13

PP4/IRQ120

L5

PP5/IRQ121

D8

PP6/IRQ122

K6

PP7/IRQ123

D4

PQ0/IRQ124

E4

PQ1/IRQ125

F5

PQ2/IRQ126

N5

PQ3/IRQ127

N6

PQ4/IRQ128

K5

PQ5/IRQ129

M6

PQ6/IRQ130

L6

PQ7/IRQ131

L3

U0RX

M1

U0TX

E13

USB0DM

E12

USB0DP

LPC_AD<0>

6

16 42 68

BI

LPC_AD<1>

6

16 42 68

BI

LPC_AD<2>

6

16 42 68

BI

LPC_AD<3>

6

16 42 68

BI

LPC_CLK33M_SMC

25 68

IN

LPC_FRAME_L

6

16 42 68

IN

SMC_LRESET_L

25

IN

LPC_SERIRQ

6

16 42

BI

PM_CLKRUN_L

6

17 42

OUT

LPC_PWRDWN_L

6

17 25 42

IN

SMC_RUNTIME_SCI_L

19

OUT

SMC_WAKE_SCI_L

19

OUT

SMBUS_SMC_0_S0_SCL

43 70

BI

SMBUS_SMC_0_S0_SDA

43 70

BI

SMBUS_SMC_1_S0_SCL

43 70

BI

SMBUS_SMC_1_S0_SDA

43 70

BI

SMBUS_SMC_2_S3_SCL

43 70

BI

SMBUS_SMC_2_S3_SDA

43 70

BI

SMBUS_SMC_3_SCL

43 70

BI

SMBUS_SMC_3_SDA

43 70

C

B

BI

SMBUS_SMC_4_ASF_SCL

41

BI

SMBUS_SMC_4_ASF_SDA

41

BI

SMBUS_SMC_5_G3_SCL

43 70

BI

SMBUS_SMC_5_G3_SDA

43 70

BI

SMC_FAN_0_CTL

47

OUT

SMC_FAN_0_TACH

47

IN

SMC_FAN_1_CTL

41

OUT

SMC_FAN_1_TACH

41

IN

SMC_MPM5_LED_PWR

41

OUT

SMC_MPM5_LED_CHG

41

OUT

SMC_SYS_KBDLED

48

OUT

SMC_T25_EN_L

41

OUT

SYS_TDM_ONEWIRE

41

BI

SYS_ONEWIRE

6

39

IN

HISIDE_ISENSE_OC

41

IN

SMC_ODD_DETECT

41

OUT

CPU_PECI_R

41

BI

SMC_PECI_L

41

OUT

SMC_BIL_BUTTON_L

41

IN

SMC_DP_HPD_L

41

IN

SMC_PME_S4_WAKE_L

6

41 48

IN

SMC_PME_S4_DARK_L

41

IN

SMC_S4_WAKESRC_EN

41 61

OUT

SMC_LID

6

41 48 51

IN

ENET_ASF_GPIO

41

OUT

SMS_INT_L

41

IN

SMC_BC_ACOK

6

39 41

IN

G3_POWERON_L

41

IN

PM_SLP_S3_L

17 26 61

IN

PM_SLP_S4_L

17 26 36 48 61

IN

PM_SLP_S5_L

17 61

IN

SMC_ONOFF_L

6

41 48

IN

SMC_RX_L

6

41 42

IN

SMC_TX_L

6

41 42

OUT

USB_SMC_N

24 67

USB_SMC_P

24 67

(OD)

NC FOR ENG PKG

(OD)

NC FOR STACK BRD

(OD)

NC FOR ENG PKG

(OD)

D

C

B

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

A

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

6 3

SYNC_MASTER=J30_MLB

PAGE TITLE

SMC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=07/26/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

49 OF 109

SHEET

40 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

SMC Reset "Button", Supervisor & AVREF Supply

=PP3V3_S5_SMC

7

40 41

=PPVIN_S5_SMCVREF

7

Desktops: 5V Mobiles: 3.42V

1

C5020

0.47UF

10%

6.3V 2

CERM-X5R

C5001

0.01UF

10% 10V X5R 201

402

1

2

SMC_TPAD_RST_L

6

48

D

IN

6

40 41 48

IN

1

2

SMC_ONOFF_L SMC_MANUAL_RST_L

OMIT

R5001

0

5% 1/10W MF-LF 603

SILK_PART=SMC_RST

1

V+

U5010

VREF-3.3V-VDET-3.0V

6

MR1*

7

MR2*

4

DELAY

GND

2

(IPU) (IPU)

DFN

SN0903048

CRITICAL

3

VIN

RESET*

REFOUT

THRM

PAD

9

PLACEMENT_NOTE=Place R5001 on BOTTOM side

MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.

5

8

C5025

10UF

X5R-CERM

0402-1

20% 10V

1

R5000

100K

5% 1/20W MF 201

2

SMC_RESET_L PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

1

C5026

0.01UF

10% 10V

2

X5R 201

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

40 44 45

6

40 42 52

OUT

40

Debug Power "Buttons"

SMC_ONOFF_L

603

1

0

5%

2

OMIT

1

R5015

0

PLACE_SIDE=TOP

5% 1/10W MF-LF 603

2

SILK_PART=PWR_BTN

OMIT

R5016

PLACE_SIDE=BOTTOM

C

SILK_PART=PWR_BTN

1/10W MF-LF

6

40 41 48

OUT

SMC Crystal Circuit

SMC USB Clock require these crystal values:5,6,8,10,12,16,18,20,24,25 MHz

R5010

2.49K

SMC_XTAL

40

SMC_EXTAL

40

1 2

1%

1/20W

MF

201

1

2

SMC_XTAL_R

12.000MHZ-30PPM-10PF

C5010

12PF

5% 25V NP0-C0G 201

CRITICAL

Y5010

3.2X2.5MM-SM

1 3

2 4

1

C5011

12PF

5% 25V

2

NP0-C0G 201

Note: ADC10 and ADC11 are shared with comparators on Stack Board.

B

SMC_ADC0

40

SMC_ADC1

40

SMC_ADC2

40

SMC_ADC3

40

SMC_ADC4

40

SMC_ADC5

40

SMC_ADC6

40

SMC_ADC7 SMC_ADC8

40

SMC_ADC9

40

SMC_ADC10

40

SMC_ADC11

40

SMC_ADC12

40

SMC_ADC13

40

SMC_ADC14

40

SMC_ADC15

40

SMC_ADC16

40

SMC_ADC17

40

SMC_ADC18

40

SMC_ADC19

40

SMC_ADC20

40

SMC_ADC21

40

SMC_ADC22

40

SMC_ADC23

40 41

SMC_GFX_OVERTEMP

40

SMC_GFX_THROTTLE_L

40

SMC_FAN_1_CTL

40

SMC_FAN_1_TACH

40

ENET_ASF_GPIO

40

SMC_MPM5_LED_PWR

40

SMC_MPM5_LED_CHG

40

SYS_TDM_ONEWIRE

40

SMC_DP_HPD_L

40

=CHGR_ACOK

44 52

HISIDE_ISENSE_OC

40

SMBUS_SMC_4_ASF_SCL

40

SMBUS_SMC_4_ASF_SDA

40

BDV_BKL_PWM

40

SMC_PME_S4_DARK_L

40 41

MAKE_BASE=TRUE

SMC_T25_EN_L

40

PM_CLK32K_SUSCLK_R

17 68

IN

PLACE_NEAR=U1800.D3:5.1mm

SMC12 SPI Support

Series resistors are no stuffed until the topology of 2 SPI Masters are verified.

R5021

24.9

201

1 2

1%

1/20W

MF

15

5% MF

15

5% MF

201

R5023

15

1 2

5%

1/20W

MF

201

SPI_MLB_MISO

PLACE_NEAR=U6100.2:1MM

SPI_MLB_MOSI

PLACE_NEAR=U6100.5:1MM

SPI_MLB_CLK

PLACE_NEAR=U6100.6:1MM

SPI_MLB_CS_L

PLACE_NEAR=U6100.1:1MM

40 68

IN

SPI_SMC_MISO

SPI_SMC_MOSI

SPI_SMC_CLK

SPI_SMC_CS_L

R5022

1 2

1/20W

R5024

1 2

1/20W

A

=PP3V3_S4_SMC

1

R5082

100K

5% 1/20W MF 201

36

=BT_WAKE_L

IN

2

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

7

41

6

40 48

OUT

6 3

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_VCCSA_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_HDD_ISENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_HS_COMPUTING_ISENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

SMC_1V5S3_ISENSE

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUE

SMC_GFX_VSENSE

MAKE_BASE=TRUE

SMC_CPU_SA_ISENSE

MAKE_BASE=TRUE

SMC_3V3S0_ISENSE

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

NC_SCM_ADC17

MAKE_BASE=TRUE

SMC_GFX_ISENSE

MAKE_BASE=TRUE

NC_SMC_ADC19

MAKE_BASE=TRUE

NC_SMC_ADC20

MAKE_BASE=TRUE

NC_SMC_ADC21

MAKE_BASE=TRUE

NC_SMC_ADC22

MAKE_BASE=TRUE

SMC_ADC23

MAKE_BASE=TRUE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

NC_ENET_ASF_GPIO

MAKE_BASE=TRUE

NC_SMC_MPM5_LED_PWR

MAKE_BASE=TRUE

NC_SMC_MPM5_LED_CHG

MAKE_BASE=TRUE

NC_SYS_TDM_ONEWIRE

MAKE_BASE=TRUE

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

NC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_BDV_BKL_PWM

MAKE_BASE=TRUE

=TBT_WAKE_L

NC_SMC_T25_EN_L

MAKE_BASE=TRUE

R5012

1 2

SMC_CLK32K

5%221/20W

44

45

44

45

45 40

45

44

45

44

40 41

CPU_PROCHOT_L

10 40 56 65

BI

PM_THRMTRIP_L_R

19

OUT

40 41

OUT

CPU_THRMTRIP_3V3

CRITICAL

MMBT3904LP-7

6

1

3

4

Q5058

DFN1006-3

D

Q5059

SSM6N15AFE

SOT563

S G

D

Q5059

SSM6N15AFE

SOT563

S G

3

2

CRITICAL

2

SMC_PROCHOT

CRITICAL

5

SMC_THRMTRIP

1

PM_THRMTRIP_R_L

40

IN

40 41

IN

R5058

3.3K

1 2

5%

1/20W

MF

201

40

IN

From SMC

PM_THRMTRIP_L

SMC_PECI_L

SMC12 PECI Support

CRITICAL

CPU_PECI_R

Q5050

VESM

1

NOSTUFF

1

R5053

1.6K

5% 1/20W MF 201

2

G S

SSM3K15AMFVAPE

R5052

0

1 2

10 19 65

IN

1/20W

201

5% MF

SMC_PECI_L_R

40

OUT

To SMC

=PPVCCIO_S0_SMC

3

D

2

1

R5051

330

5% 1/20W MF 201

2

R5034

43

1 2

1/20W

PLACE_NEAR=R2170.2:5mm

CPU_PECI

5% MF

201

7

41

From/To CPU/PCH

D

65 10

BI

19

C

SMC12 Eng Pkg Support

Eng Package requires 1.2V ON SMC_ADC23 pin.

=PP3V3_S4_SMC

7

41

=PP3V3_S0_SMC

7

PP1V2_S5_SMC_VDDC

40

6

39 40 41

SMC_ADC23

40 41

33

IN

=PPVCCIO_S0_SMC

7

41

40 68

MF 201

42 49 68

OUT

42 49 68

OUT

42 49 68

OUT

42 49 68

OUT

SMC_VCCIO_CPU_DIV2

40

BATLOW# Isolation

=PP3V3_S5_SMCBATLOW

7

1

R5040

100K

5%

1/20W

MF

201

2

SMC_BATLOW_L

40 61 17

IN

CRITICAL

Q5040

SSM3K15AMFVAPE

VESM

D

3

R5041

0

1 2

5% 1/16W MF-LF

402

1

R5099

0

5% 1/20W MF 201

2

SMC_PACKAGE:ENG

1

R5097

100K

1% 1/20W MF 201

2

1

R5096

100K

1% 1/20W MF 201

2

=PP3V3_SUS_SMC

1

GS

PM_BATLOW_L

2

Internal 20K pull-up on PM_BATLOW_L in PCH.

NOSTUFF

7

OUT

SMC_ODD_DETECT

40

SMC_PME_S4_DARK_L

40 41

SMC_OOB1_TX_L

6

37 40

SMC_ONOFF_L

6

40 41 48

G3_POWERON_L

40

SMC_LID

6

40 48 51

SMC_TX_L

6

40 42

SMC_RX_L

6

40 42

SMC_DEBUGPRT_TX_L

38 40 67

SMC_DEBUGPRT_RX_L

38 40 67

SMC_TMS

6

40 42

SMC_TDO

6

40 42

SMC_TDI

6

40 42

SMC_TCK

6

40 42

SMC_BIL_BUTTON_L

40

SMC_BC_ACOK

6

39 40 41

SMC_S5_PWRGD_VIN

40

SMS_INT_L

40

MEM_EVENT_L

40

CPU_THRMTRIP_3V3

40 41

SMC_ROMBOOT

6

42

SMC_ADAPTER_EN

17 40 61

SMC_THRMTRIP

40 41

SMC_DELAYED_PWRGD

25 35 40

SMC_S4_WAKESRC_EN

40 61

WIFI_EVENT_L

6

36 40

Module has 3.3K PU

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

R5066

R5067 R5068

R5070 R5072 R5071 R5073 R5074 R5075 R5076 R5077 R5078 R5079 R5080 R5081 R5087 R5092 R5093

R5014 R5017

1

R5088

1K

5% 1/20W MF 201

2

R5085 R5086

R5091 R5090

R5089

SMC Support

Apple Inc.

R

33K

100K

10K 10K

100K

10K

100K

10K

100K

10K 10K 10K 10K

10K 100K 100K

10K

100K

10K

10K 100K 100K

10K

NO STUFF

1 2 1 2

NO STUFF

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

NO STUFF

1 2 1 2

1 2

NO STUFF

1 2

=PP3V3_S5_SMC

7

40 41

5%

5% MF 201

5%

5% 5% 5%

5% MF 201 5%

5% 201MF

5% 201

5% 201MF

PP3V3_WLAN_F

6

36

5% MF

1/20W

MF

1/20W

1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W

1/20W 1/20W

1/20W

201

MF 201 MF

2015% MF 2015% MF

201 MF 201 MF 201

201

MF5%

201MF5%

2015%

MF

201 MF 2015% MF

2015% MF 2015%

2015% MF

MF 2015% MF

2015%

MF5%

201

MF

201

SYNC_DATE=10/06/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

50 OF 109

SHEET

41 OF 72

SIZE

B

A

D

124578

8 7 6 5 4 3

12

D

=PP3V3_S5_LPCPLUS

6 7

=PP5V_S0_LPCPLUS

6 7

LPC_CLK33M_LPCPLUS

6

25 68

BI

LPC_AD<0>

6

16 40 68

BI

LPC_AD<2>

6

16 40 68

IN

LPC_AD<1>

6

16 40 68

OUT

LPC_AD<3>

6

16 40 68

IN

SPI_ALT_MOSI

6

42

OUT

LPCPLUS_GPIO

6

19

OUT

LPCPLUS_RESET_L

6

25 68

IN

SMC_TDO

6

40 41

OUT

TP_SMC_TRST_L

6

TP_SMC_MD1

6

SMC_TX_L

6

40 41

IN

C

LPC+SPI Connector

LPCPLUS

CRITICAL

J5100

DF40C-30DP-0.4V

M-ST-SM

31

32

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

33

34

SPI_ALT_MISO LPC_FRAME_L

SPIROM_USE_MLB

PM_CLKRUN_L SPI_ALT_CLK

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TMS

6

42

IN

6

16 40 68

BI

6

19 49

BI

6

17 40

OUT

6

42

IN

6

42

IN

6

16 40

BI

6

17 25 40

IN

6

40 41

OUT

6

40 41

OUT

6

40 41 52

OUT

6

41

OUT

6

40 41

OUT

6

40 41

OUT

D

C

998-4235

SPI Bus Series Termination

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK

43

5%

PLACE_NEAR=R5125.2:5mm

1/20W

MF

201

SPI_ALT_CS_L

PLACE_NEAR=J5100.14:5mm PLACE_NEAR=J5100.12:5mm PLACE_NEAR=J5100.9:5mm PLACE_NEAR=J5100.11:5mm

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_MLB_MISO

43

5%

PLACE_NEAR=R5127.2:5mm

1/20W

MF

201

LPCPLUS

1

R5126

43

5% 1/20W MF 201

2

R5121

1 2

1/20W

LPCPLUS

1

2

43

5%

PLACE_NEAR=R5126.2:5mm

MF

201

R5125

43

5% 1/20W MF 201

R5120

1 2

24.9

1%

PLACE_NEAR=U6100.2:5mm

1/20W

MF

201

LPCPLUS

1

R5127

43

5% 1/20W MF 201

2

R5122

1 2

LPCPLUS

1

R5128

24.9

1% 1/20W MF 201

2

SPI_CS0_R_L

16 68

IN

B

16 68

PLACE_NEAR=U1800.W8:5mm

16 68

IN

OUT

SPI_CLK_R

SPI_MOSI_R

SPI_MISO

PLACE_NEAR=U1800.AD12:5mm

PLACE_NEAR=U1800.AB8:5mm

R5112

15

1 2

5%

1/20W

MF

201

R5111

1 2

1/20W

R5110

15

1 2

15

5% MF

201

1/20W

201

SPI_CS0_L

68

5% MF

SPI_CLK

68

SPI_MOSI

68

R5123

1 2

6

42

6

42

6

42

6

42

41 49 68

OUT

41 49 68

OUT

41 49 68

OUT

41 49 68

IN

B

A

SYNC_MASTER=K21_MLB

PAGE TITLE

LPC+SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

51 OF 109

SHEET

42 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH S0 SMBus "0" Connections

=PP3V3_S0_SMBUS_PCH

7

43

1

Cougar-Point

U1800

(MASTER)

SMBUS_PCH_CLK

16 68

D

MAKE_BASE=TRUE

SMBUS_PCH_DATA

16 68

MAKE_BASE=TRUE

R5200

R5201

1K

5%

1/20W1/20W MF

MF

201

2

LED BACKLIGHT

(WRITE: 0x58 READ: 0x59)

=I2C_BKL_1_SCL

=I2C_BKL_1_SDA

U9701

64

SMBUS_SMC_0_S0_SCL

40 70

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

40 70

MAKE_BASE=TRUE

SMC

U4900

(MASTER)

=PP3V3_S0_SMBUS_SMC_0_S0

7

SMC "0" SMBus S0 Connections

1

R5250

4.7K

1/20W

R5251

4.7K

5%

1/20W MF

MF

201

2

Internal DP

(See Table)

=I2C_TCON_SCL

=I2C_TCON_SDA

J9000

=PP3V42_G3H_SMBUS_SMC_BSA

7

SMC

U4900

(MASTER)

SMBUS_SMC_5_G3_SCL

62

40 70

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

40 70

MAKE_BASE=TRUE

VRef DACs

U3300

(Write: 0x98 Read: 0x99)

=I2C_VREFDACS_SCL

31

=I2C_VREFDACS_SDA

=I2C_TBTRTR_SCL

Margin Control

U3301

(Write: 0x30 Read: 0x31)

=I2C_PCA9557D_SCL

31

=I2C_PCA9557D_SDA

C

XDP Connectors

J2600 & J2650

=SMBUS_XDP_SCL

23

=SMBUS_XDP_SDA

23

(MASTER)

=I2C_TBTRTR_SDA

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

TBT

U3600

(Write: 0xXXX Read: 0xXXX)

Mikey

U6800

(Write: 0x72 Read: 0x73)

33

(* = Multiple options)

Internal DP

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y * Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N * DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

6

39

6

39

7

SMC

U4900

(MASTER)

SMBUS_SMC_2_S3_SCL

40 70

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

40 70

MAKE_BASE=TRUE

SMC "2" SMBus S3 Connections

=PP3V3_S3_SMBUS_SMC_A_S3

NOTE: SMC RMT bus remains powered and may be active in S3 state

K21 K78

Samsung LGD Samsung LGD AUO

1

R5270

1/20W

1

R5271

1K

5%

5% 1/20W

MF

201

2

Left I/O Board

(See Table)

=I2C_LIO_SCL

=I2C_LIO_SDA

J4700

6

39

6

39

Battery

Battery Manager - (Write: 0x16 Read: 0x17)

SMC

U4900

(MASTER)

SMBUS_SMC_3_SCL

40 70

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

40 70

MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_MGMT

7

SMC "5" SMBus G3H Connections

1

R5280

2.0K

1/20W

1

R5281

2.0K

5%

1/20W

MF

201

2

SMC "3" SMBus S3 Connections

1

R5290

2.0K

1/20W

R5291

2.0K

5%

5% 1/20W

MF

MF 201

201

2

Battery Charger

ISL6258 - U7000

(Write: 0x12 Read: 0x13)

=SMBUS_CHGR_SCL

=SMBUS_CHGR_SDA

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

Trackpad

(Write: 0x90 Read: 0x91)

=I2C_TPAD_SCL

=I2C_TPAD_SDA

TBT & Inlet Temp

EMC1704: U5400

(Write: 0x98 Read: 0x99)

=I2C_TBT_INLET_THMSNS_SCL

=I2C_TBT_INLET_THMSNS_SDA

Battery

J6955

(See Table)

J5700

52

6

51

6

51

6

48

6

48

D

C

45

B

A

SMLink 1 is slave port to

access PCH

Cougar-Point

U1800

(MASTER)

SML_PCH_0_CLK

16 68

MAKE_BASE=TRUE

SML_PCH_0_DATA

16 68

MAKE_BASE=TRUE

Cougar-Point

U1800

(Write: 0x88 Read: 0x89)

SML_PCH_1_CLK

16 68

SML_PCH_1_DATA

16 68

PCH S0 "SMLink 0" Connections

=PP3V3_S0_SMBUS_PCH

7

43

R5210

8.2K

1/20W

201

PCH S0 "SMLink 1" Connections

Left I/O Board

ALS - (write: 0x72 Read: 0x73) Finstack Temp - (Write: 0x92 Read: 0x93)

B

1

R5211

8.2K

5%

5% 1/20W

MF

MF 201

2

SMC S0 "1" SMBus Connections

=PP3V3_S0_SMBUS_SMC_B_S0

7

1

R5260

4.7K

1/20W

SMBUS_SMC_1_S0_SCL

40 70

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

40 70

MAKE_BASE=TRUE

SMC

U4900

(MASTER)

6 3

R5261

4.7K

5%

1/20W MFMF 201

201

2

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

CPU Temp

EMC1414-A: U5570

(Write: 0x98 Read: 0x99)

46

SYNC_MASTER=J13_MLB

PAGE TITLE

SMBus Connections

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/05/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

52 OF 109

SHEET

43 OF 72

SIZE

A

D

124578

D

C

B

8 7 6 5 4 3

PBUS Voltage Sense Enable & Filter

Q5300

NTUD3169CZ

SOT-963

=PBUSVSENS_EN

61

IN

Enables PBUS VSense divider when in S0.

=PPBUS_S0_VSENSE

7

=CHGR_ACOK

Enables DC-In VSense

NOSTUFF

R5315

R5316

divider when AC present.

1

0

5%

1/20W

MF

201

2

1

0

5%

Enables DC-In VSense

1/20W

divider when SUS present.

MF

201

2

PM_SUS_EN

=PPDCIN_S5_VSENSE

=PPCPUVCORE_S0_VSENSE

7

R5301

100K

1%

1/20W

MF

201

41 52

IN

DCINVSENS_EN

61

IN

R5311

100K

1/20W

=PPVCCSA_S0_VSENSE

7

CPU Vcore Voltage Sense / Filter

2

1

5

4

1

2

PBUSVSENS_EN_L_DIV

2

1

5

4

1

1% MF

201

2

PDCINVSENS_EN_L_DIV

XW5320

SM

1 2

PLACE_NEAR=R7510.2:5 MM

N-CHANNEL

G

P-CHANNEL

Q5310

NTUD3169CZ

N-CHANNEL

G

P-CHANNEL

PLACE_NEAR=R7140.2:5 MM

CPUVSENSE_IN

PLACE_NEAR=U4900.E2:5MM

6

D

S

D

S

PBUSVSENS_EN_L

3

PBUS_S0_VSENSE

DC-In Voltage Sense Enable & Filter

SOT-963

6

D

S

D

S

DCINVSENS_EN_L

3

DCIN_S5_VSENSE

VCCSA Voltage Sense / Filter

XW5340

SM

1 2

1

R5302

100K

1%

1/20W

MF

201

2

PLACE_NEAR=U4900.A3:5MM

R5312

100K

1%

1/20W

MF

201

PLACE_NEAR=U4900.F1:5MM

VCCSAVSENSE_IN

PLACE_NEAR=U4900.F2:5MM

R5320

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_VSENSE

PLACE_NEAR=U4900.E2:5MM

1

C5320

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

Max VOut: 3.3V at 19.77V Input

1

R5303

27.4K

1%

PLACE_NEAR=U4900.A3:5MM

1/20W

MF

RTHEVENIN = 4573 Ohms

201

2

SMC_PBUS_VSENSE

PLACE_NEAR=U4900.A3:5MM

1

R5304

5.49K

1/20W

1

Max VOut: 3.3V at 19.77V Input

2

R5340

4.53K

1 2

1%

1/20W

MF

201

1

C5304

0.22UF

1%

20%

6.3V

2

MF

201

R5313

27.4K

R5314

5.49K

X5R 0201

2

GND_SMC_AVSS

1

1%

1/20W

PLACE_NEAR=U4900.F1:5MM

MF

RTHEVENIN = 4573 Ohms

201

2

PLACE_NEAR=U4900.F1:5MM

1

1%

1/20W

MF

2

201

2

SMC_VCCSA_VSENSE

PLACE_NEAR=U4900.F2:5MM

1

C5350

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

41

OUT

40 41 44 45

SMC_DCIN_VSENSE

C5314

0.22UF

20%

6.3V X5R 0201

GND_SMC_AVSS

40 41 44 45

41

OUT

41

OUT

40 41 44 45

12

=PP3V3_S0_IMVPISNS

7

CPU VCore Load Side Current Sense / Filter

CPUIMVP_ISNS1_P

56 57 71

IN

CPUIMVP_ISNS1_N

57 71

IN

Sense R is R7510 Sense R is 0.75mOhm

EDP: 33A TDP :28.05A

PLACE_NEAR=R7510.3:5MM

R5342

4.42K

1 2

0.1%

1/20W

MF

PLACE_NEAR=R7510.4:5MM

0201

R5343

4.42K

1 2

0.1%

1/20W

MF

0201

CPUIMVP_ISUM_R_P

71

CPUIMVP_ISUM_R_N

71

1

R5344

487K

0.1% 1/20W MF 0201

2

3

2

R5345

487K

1 2

1/20W

8

V+ V-

THRM

4

9

0.1%

SIGNAL_MODEL=EMPTY

MF

0201

CRITICAL

U5340

OPA2333

DFN

1

CPUIMVP_ISUM_IOUT

GFX/IG VCore Load Side Current Sense / Filter

PLACE_NEAR=R7550.3:5MM

57 71

CPUIMVP_ISNS1G_P

IN

57 71

CPUIMVP_ISNS1G_N

IN

PLACE_NEAR=R7550.4:5MM

Sense R is R7550 Sense R is 0.75mOhm

41

EDP: 18A TDP: 15.3A

CPU SA Current Sense / Filter

53 71

VCCSAS0_CS_P

IN

53 71

VCCSAS0_CS_N

IN

Sense R is R7140 Sense R is 1mOhm

EDP: 6A

R5352

4.42K

1 2

0.1%

1/20W

MF

0201

R5353

4.42K

1 2

0.1%

1/20W

MF

0201

=PP3V3_S0_SAISNS

PLACE_NEAR=R7140.3:5MM

R5372

1.82K

1 2

0.1%

1/20W

MF

0201

PLACE_NEAR=R7140.4:5MM

R5373

1.82K

1 2

0.1%

1/20W

MF

0201

71

CPUIMVP_ISUMG_R_P

71

CPUIMVP_ISUMG_R_N

71

1

R5354

715K

0.1% 1/20W MF 0201

2

VCCSAISNS_R_P

71

VCCSAISNS_R_N

1

R5374

1.00M

0.1% 1/20W MF 0201

2

5

6

R5355

715K

1 2

1/20W

CRITICAL

U5340

OPA2333

8

DFN

V+

7

V-

THRM

4

9

SIGNAL_MODEL=EMPTY

0.1% MF

0201

U5370

OPA333DCKG4

5

1

+

SC70-5

V+

V-

3

-

2

R5375

1.00M

1 2

0.1%

1/20W

MF

0201

CRITICAL

PLACE_NEAR=U5340.8:3MM

1

C5340

0.1UF

10%

6.3V

2

X5R 201

CPUIMVP_ISUMG_IOUT

4

ISENSE_SA_IOUT

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U4900.E1:5MM

R5341

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_ISENSE

PLACE_NEAR=U4900.E1:5MM

PLACE_NEAR=U4900.M11:5MM

1

C5341

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

40 41 44 45

Gain:110.181x

Scale: 12.1A / V Max VOut: 2.73V at 39.934A

PLACE_NEAR=U4900.H1:5MM

R5351

4.53K

1 2

1%

1/20W

MF

201

SMC_GFX_ISENSE

PLACE_NEAR=U4900.H1:5MM

PLACE_NEAR=U4900.M13:5MM

1

C5351

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

Gain:161.765x

Scale: 8.24A / V Max VOut: 2.18V at 27.2A

PLACE_NEAR=U5370.5:3MM

1

C5370

0.1UF

10%

6.3V

2

X5R 201

PLACE_NEAR=U4900.C2:5MM

R5371

4.53K

1 2

1/20W

Gain:???

Scale: ???A / V Max VOut: ???V at ???A

SMC_CPU_SA_ISENSE

1% MF

201

PLACE_NEAR=U4900.C2:5MM

1

C5371

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

OUT

40 41 44 45

41

D

41

OUT

C

41

OUT

B

=PPGFXVCORE_S0_VSENSE

7

CPU 1.05V VCCIO Current Sense / Filter

=PP3V3_S0_CPUVCCIOISNS

7

A

PLACE_NEAR=R7640.3:5MM

CPUVCCIOS0_CS_N

58 71

IN

CPUVCCIOS0_CS_P

58 71

IN

PLACE_NEAR=R7640.4:5MM

Sense R is R7640, 2mOhm

EDP: 8.5A TDP :7.225A

GFX/IG Vcore Voltage Sense / Filter

XW5330

SM

1 2

PLACE_NEAR=R7550.2:5 MM

VCCIOISNS_ENG

5

IN-

4

(200V/V)

GFXVSENSE_IN

PLACE_NEAR=U4900.C1:5MM

3

V+

U5360

INA210

SC70

OUT

CRITICAL

GND

REFIN+

2

VCCIOISNS_ENG

1

2

6

1

R5330

4.53K

1 2

1%

1/20W

MF

201

C5360

0.1UF

10%

6.3V X5R 201

CPUVCCIO_IOUT

SMC_GFX_VSENSE

PLACE_NEAR=U4900.C1:5MM

1

C5330

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

VCCIOISNS_ENG

PLACE_NEAR=U4900.A6:5MM

R5361

4.53K

1 2

1%

1/20W

MF

201

Gain: 200x

Scale: 2.5A / V Max VOut: 3.3V at 8.25A

41

OUT

40 41 44 45

SMC_CPUVCCIO_ISENSE

PLACE_NEAR=U4900.A6:5MM

1

C5361

VCCIOISNS_ENG

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

6 3

41

OUT

40 41 44 45

3.3V S0 FET Current Sense / Filter

=PP3V3_S0_3V3S0ISNS

7

PLACE_NEAR=R7831.3:5MM

R5382

1.82K

60 71

ISNS_3V3S0_P

IN

60 71

ISNS_3V3S0_N

IN

Sense R is R7831 Sense R is 1mOhm

EDP: 5A

PLACE_NEAR=R7831.4:5MM

1 2

R5383

1.82K

1 2

0.1%

1/20W

MF

0201

0.1%

1/20W

MF

0201

ISNS_3V3S0_R_N

71

ISNS_3V3S0_R_P

1

R5384

1.00M

0.1% 1/20W MF 0201

2

1

3

+

-

R5385

1.00M

1 2

U5380

OPA333DCKG4

5

SC70-5

V+

V-

2

0.1%

1/20W

MF

0201

CRITICAL

4

ISENSE_3V3S0_IOUT

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5380.5:3MM

1

C5380

0.1UF

10%

6.3V

2

X5R 201

PLACE_NEAR=U4900.B1:5MM

R5381

1 2

4.53K

1%

1/20W

MF

201

SMC_3V3S0_ISENSE

PLACE_NEAR=U4900.B1:5MM

1

C5381

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

Gain:???

Scale: ???A / V Max VOut: ???V at ???A

41

OUT

40 41 44 45

SYNC_MASTER=J13_MLB

PAGE TITLE

SYNC_DATE=09/15/2011

Voltage & Load Side Current Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

53 OF 109

SHEET

44 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

45

ISNS_HS_COMPUTING_N

8

71

IN

ISNS_HS_COMPUTING_P

8

71

IN

D

EDP Current: 15.5 A Max Vdiff: 31 mV

Sense R is R5400, 2mOhm

C

=PP3V3_S0_HS_COMPUTING_ISNS

7

3 V+

U5450

INA214

5

SC70

IN-

4

IN+ REF

(100V/V)

GND

2

=PP3V3_S0_HS_COMPUTING_ISNS

7

45

46 71

BI

46 71

BI

46

BI

46

BI

1

2

6

OUT

1

INLET_THMSNS_D1_P

INLET_THMSNS_D1_N

=TBTTHMSNS_D2_P

=TBTTHMSNS_D2_N

COMPUTING High Side Current Sense / Filter

C5450

0.1UF

10%

6.3V X5R 201

ISNS_HS_COMPUTING_IOUT

GAIN: 100X

SCALE: 5A/ V MAX VOUT: 3.1V at 16.5A

PLACEMENT_NOTEs:

Place close to SMC

Place close to SMC (For R and C)

PLACE_NEAR=U4900.B5:5mm

R5455

4.53K

1 2

1%

1/20W

MF

201

SMC_HS_COMPUTING_ISENSE

PLACE_NEAR=U4900.B5:5mm

1

C5455

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

TBT/Inlet Temp Sensor

R5410

47

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5410.2:5mm PLACE_NEAR=U5410.3:5mm

PLACE_NEAR=U5410.4:5mm PLACE_NEAR=U5410.5:5mm

1 2

PP3V3_S0_HS_COMPUTING_ISNS_R

MIN_LINE_WIDTH=0.5 mm

5%

MIN_NECK_WIDTH=0.20 mm

1/20W

VOLTAGE=3.3V

MF

201

C5411

2200PF

10% 10V

X7R-CERM

0201

SIGNAL_MODEL=EMPTY

C5412

2200PF

X7R-CERM

2

1

2

1

10% 10V

2

0201

4

5

40 41 44 45

1

VDD

U5410

EMC1414-1-AIZL

MSOP

THERM*/ADDR

DP1

CRITICAL

DN1

DP2/DN3

DN2/DP3

ALERT*

SMDATA

GND 6

Write Address: 0x98 Read Address: 0x99

SMCLK

52

41

OUT

Sense R is R7020, 20mOhm

1

C5410

0.1UF

10%

6.3V

2

X5R 201

7

TBT_INLET_THM_L

83

TBT_INLET_ALERT_L

9

=I2C_TBT_INLET_THMSNS_SDA

10

=I2C_TBT_INLET_THMSNS_SCL

DC-IN (AMON) Current Sense Filter

PLACE_NEAR=U4900.B3:5MM

R5431

4.53K

CHGR_AMON

IN

1 2

1%

1/20W

MF 201

DC-In AMON ISL6259 Gain: 20x

Scale: 2.5A / V Max VOut: 1.4V at 8.25A

EDP Current: 3.5A

SMC_DCIN_ISENSE

PLACE_NEAR=U4900.B3:5MM

1

C5431

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

40 41 44 45

41

OUT

Sense R is R7350, 1mOhm

55 71

EDP Current: 12 A Max Vdiff: 24 mV

DDR3 1V5R1V35 Current Sense / Filter

=PP3V3_S3_1V5S3ISNS

7

3 V+

U5460

IN

ISNS_1V5_S3_N

ISNS_1V5_S3_P

5

4

IN-

INA210

SC70

(200V/V)

GND

2

OUT

6

1

REFIN+

1

C5460

0.1UF

10%

6.3V

2

X5R 201

ISNS_1V5S3_IOUT

GAIN: 200X

SCALE: 5A / V MAX VOUT: 2.4V AT 16.5A

PLACEMENT_NOTEs:

Place close to SMC

Place close to SMC (For R and C)

PLACE_NEAR=U4900.B6:5mm

R5465

4.53K

1 2

1%

1/20W

MF

201

SMC_1V5S3_ISENSE

PLACE_NEAR=U4900.B6:5mm

1

C5465

0.22UF

20%

6.3V

2

X5R

0201

GND_SMC_AVSS

40 41 44 45

D

41

OUT

AirPort Current Sense / Filter

=PP3V3_S3_WLANISNS

IN

7

ISNS_AIRPORT_N

ISNS_AIRPORT_P

AIRPORTISNS_ENG

5

IN-

4

3

V+

U5470

INA210

SC70

(200V/V)

GND

2

OUT

AIRPORTISNS_ENG

1

C5470

0.1UF

10%

6.3V

2

X5R 201

6

ISNS_P5VWLAN_IOUT

1

REFIN+

Gain: 200x

Scale: 0.25A / V MAX VOUT: 3V AT 0.825A

PLACEMENT_NOTEs:

Place close to SMC

Place close to SMC (For R and C)

PLACE_NEAR=U4900.B2:5mm

AIRPORTISNS_ENG

R5475

4.53K

1 2

1%

1/20W

1

MF

201

2

SMC_WLAN_ISENSE

AIRPORTISNS_ENG

C5475

0.22UF

20%

PLACE_NEAR=U4900.B2:5mm

6.3V X5R 0201

GND_SMC_AVSS

40 41 44 45

41

OUT

C

R5411

1/20W

1

R5412

10K10K

5%

1/20W MF

MF

201

2

Sense R is R4052, 20mOhm

43

BI

43

BI

EDP Current: 0.750 A Max Vdiff: 15 mV

36 71

HDD Current Sense / Filter

=PP3V3_S0_HDDISNS

7

=PP3V3_S0_HS_OTHER_ISNS

7

3

IN-

V+

U5430

INA213

SC70

CRITICAL

(50V/V)

GND

2

OUT

6

1

REFIN+

=PPVIN_S5_HS_OTHER_ISNS

7

OUT

R5430

0.005

B

7

IN

=PPVIN_S5_HS_OTHER_ISNS_R

CRITICAL

EDP Current: 15.5 A Max Vdiff: 31 mV

ISNS_HS_OTHER_N

71

0612

MF

1W

1%

ISNS_HS_OTHER_P

71

1 2

3 4

5

4

Sense R is R5430, 5mOhm

OTHER High Side Current Sense / Filter

1

C5430

0.1UF

10%

6.3V

2

X5R 201

HS_OTHER_IOUT

GAIN: 50X

SCALE: 5A/ V MAX VOUT: 3.1V at 16.5A

PLACEMENT_NOTEs:

Place close to SMC

Place close to SMC (For R and C)

PLACE_NEAR=U4900.A5:5mm

R5433

4.53K

1 2

1%

1/20W

MF

201

SMC_OTHER_HI_ISENSE

PLACE_NEAR=U4900.A5:5mm

1

C5433

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

40 41 44 45

Sense R is R4599, 3mOhm

ISNS_SSD_N

37 71

IN

ISNS_SSD_P

37 71

IN

41

OUT

EDP Current: 2.36A Max Vdiff: 7.0 mV

LCD Backlight Driver Input Current Sense / Filter

=PP3V3_S0_BKLTISNS

7

HDDISNS_ENG

5

4

LCDBKLTISNS_ENG

Sense R is R0910, 10mOhm

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

PLACE_NEAR=U4900.A4:5MM

R5422

300K

52

CHGR_BMON

IN

From charger

1 2

1%

1/20W

MF

201

A

SMC_BMON_ISENSE

PLACE_NEAR=U4900.A4:5MM

1

C5422

3300PF

10% 10V

2

X7R 201

GND_SMC_AVSS

41

OUT

40 41 44 45

8

71

8

71

EDP Current: 0.67 A Max Vdiff: 6.7 mV

IN

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

5

4

IN-

3

V+

U5480

INA211

SC70

(500V/V)

GND

2

3

V+

U5490

INA211

SC70

(500V/V)

GND

2

OUT

REFIN+

OUT

REFIN+

Charger BMON (Production) Solution ISL6259 Gain: 36x

Scale: 2.78A / V Max VOut: 3.3V at 9.167A

EDP Current: 310A

6 3

HDDISNS_ENG

1

C5480

0.1UF

10%

6.3V

2

X5R 201

6

ISNS_P5VHDD_IOUT

1

GAIN: 500X

SCALE: 0.667A / V MAX VOUT: 3.3V AT 2.2A

LCDBKLTISNS_ENG

1

C5490

0.1UF

10%

6.3V

2

X5R 201

6

ISNS_LCDBKLT_IOUT

1

GAIN: 500X

SCALE: 0.2A / V MAX VOUT: 3.3V AT 0.66A

PLACE_NEAR=U4900.B4:5mm

HDDISNS_ENG

R5485

4.53K

PLACEMENT_NOTEs:

Place close to SMC

Place close to SMC (For R and C)

PLACE_NEAR=U4900.G2:5mm

LCDBKLTISNS_ENG

PLACEMENT_NOTEs:

Place close to SMC (For R and C)

SYNC_MASTER=J13_MLB

PAGE TITLE

1 2

1%

1/20W

MF

201

R5495

4.53K

1 2

1%

1/20W

MF

201

SMC_HDD_ISENSE

HDDISNS_ENG

1

C5485

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

LCDBKLTISNS_ENG

1

C5495

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

High Side Current Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

PLACE_NEAR=U4900.B4:5mm

40 41 44 45

PLACE_NEAR=U4900.G2:5mm

40 41 44 45

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

54 OF 109

SHEET

45 OF 72

124578

41

OUT

41

OUT

SYNC_DATE=09/15/2011

SIZE

B

A

D

8 7 6 5 4 3

12

CPU Proximity Sensor

R5510

47

=PP3V3_S0_CPUTHMSNS

7

D

Detect CPU Die Temperature

Q5510

BC846BLP

DFN1006H4-3

Detect DDR/5V/3.3V Proximity Temperature

Placement note:

Place Q5510 next to DDR/5V/3.3V supply on TOP side

9

71

BI

9

71

BI

3

1

2

CPU_THERMD_P

CPU_THERMD_N

CPUTHMSNS_D2_P

71

CPUTHMSNS_D2_N

71

PLACE_NEAR=U5510.2:5mm PLACE_NEAR=U5510.3:5mm

1 2

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5510.4:5mm PLACE_NEAR=U5510.5:5mm

1/20W

5%

MF

201

C5511

2200PF

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

1

10% 10V

2

X7R-CERM

0201

C5512

2200PF

10% 10V

X7R-CERM

0201

1

C5510

0.1UF

R5511

1

VDD

U5510

EMC1413

DP1

CRITICAL

DN1

DP2/DN3

DN2/DP3

GND

6

DFN

THERM*/ADDR

ALERT*

SMDATA

SMCLK

THRM_PAD

11

Write Address: 0x98 Read Address: 0x99

2

4

5

1

2

10%

6.3V

2

X5R 201

7

CPUTHMSNS_THM_L

83

CPUTHMSNS_ALERT_L

9

=I2C_CPUTHMSNS_SDA

10

=I2C_CPUTHMSNS_SCL

Placement note:

Place U5510 under CPU

1/20W

10K

1

R5512

10K

5%

1/20W MF

MF

201

2

43

BI

43

BI

Use GND pin B1 on U3600 for N leg

PART NUMBER

117S0008

Detect TBT Die Temperature

QTY

1

TP_TBT_THERM_DP

33

BI

DESCRIPTION

RES,MF,1/20W,100K OHM,5,0201,SMD

PLACE_NEAR=U3600.B1:2mm

TBT Die

NO STUFF

R5550

0

TBT_THERMD_P

71

MAKE_BASE=TRUE

1 2

XW5520

To connect Die Sensor, Stuff R5550 & R5551, No stuff R5540 & R5541 To connect Proximity Sensor, Stuff R5540 & R5541, No Stuff R5550,R5551

SM

TBT_THERMD_N

71

REFERENCE DES

1 2

NO STUFF

1 2

CRITICAL

C5361 C5475 C5485 C5495

5%

1/20W

MF

201

R5551

0

5%

1/20W

MF

201

=TBTTHMSNS_D2_P

=TBTTHMSNS_D2_N

BOM OPTION

VCCIOISNS_PROD

AIRPORTISNS_PROD

HDDISNS_PROD

LCDBKLTISNS_PROD

45 46

D

C

Replacing caps with 100K PD on ISENSE SMC inputs

TBT,MLB Bottom & Inlet Proximity Sensors

INLET_THMSNS_D1_P

INLET_THMSNS_D1_N

Q5530

BC846BLP

DFN1006H4-3

3

1

2

B

TBTTHMSNS_D2_R_P

Q5520

BC846BLP

DFN1006H4-3

Q5540

BC846BLP

DFN1006H4-3

3

2

3

2

1

71

TBTTHMSNS_D2_R_N

71

=MLBBOT_THMSNS_D3_N

=MLBBOT_THMSNS_D3_P

45 71

Placement note:

Place Q5530 between near rear vent on bottom side

45 71

R5540

0

1 2

=TBTTHMSNS_D2_P

5%

1/20W

MF

201

R5541

0

=TBTTHMSNS_D2_N

5%

1/20W

MF

201

46

Placement note:

Place Q5540 on MLB bottom side opposite U5400

46

45 46

Placement note:

Place Q5520 close to TBT on TOP side

45 46

B

=TBTTHMSNS_D2_P

45 46

=TBTTHMSNS_D2_N

A

45 46

71

TBT_MLBBOT_THMSNS_P =MLBBOT_THMSNS_D3_P

MAKE_BASE=TRUE

71

TBT_MLBBOT_THMSNS_N

MAKE_BASE=TRUE

=MLBBOT_THMSNS_D3_N

6 3

46

SYNC_MASTER=J13_MLB

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=08/30/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

55 OF 109

SHEET

46 OF 72

SIZE

A

D

124578

8 7 6 5 4 3

12

D

FAN CONNECTOR

C

=PP5V_S0_FAN

6 7

=PP3V3_S0_FAN

7

CRITICAL

J5600

FF14A-4C-R11DL-B-3H

NC

F-RT-SM

5

1

5V DC

2

TACH

3

MOTOR CONTROL

4

GND

6

518S0793

47K

1/20W

201

1

5% MF

2

R5660

R5665

47K

SMC_FAN_0_TACH

40

R5661

100K

5%

1/20W

MF

201

SMC_FAN_0_CTL

B

40

1 2

1/20W

1

GS

2

5% MF

201

FAN_RT_TACH

6

Q5660

SSM3K15FV

SOD-VESM-HF

D

FAN_RT_PWM

6

3

C

B

A

SYNC_MASTER=K21_MLB

PAGE TITLE

Fan

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

56 OF 109

SHEET

47 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP3V3_S4_TPAD

7

48

R5730

1

C5701

0.1UF

10%

1

R5703

10K

1/16W MF-LF

402

USB_TPAD_R_P

24 67

USB_TPAD_R_N

24 67

R5702

10K

1/16W MF-LF

402

C

PM_SLP_S4_L

17 26 36 40 61

IN

5%

2

67

1

5%

2

16V

2

X5R-CERM

0201

USB_TPAD_M_P USB_TPAD_M_N

R5704

1 2

1/20W

201

5

M+

4

M-

7

D+

6

D-

8

0

MF5%

NOSTUFF

C5704

9

VCC

U5700

PI3USB102ZLE

TQFN

CRITICAL

GND

3

USB_TPAD_MUX_SEL

1

0.1UF

10% 16V

2

X5R-CERM

0201

1

Y+

2

Y-

10

SELOE*

SEL=0 Choose pull up/down SEL=1 Choose USB

=PP3V3_S4_TPAD

7

48

=PP5V_S5_TPAD

7

C5710

0.1UF

10% 16V

X5R-CERM

0201

PLACE_NEAR=J5700.10:1.5MM

1 2

1

2

0

MF5%

1/20W

201

PLACE_NEAR=J5700.1:1.5MM

FERR-120-OHM-1.5A

PLACE_NEAR=J5700.10:1.5MM

6 7

PLACE_NEAR=J5700.13:1.5MM

PP3V3_TPAD_CONN

6

VOLTAGE=3.3V

C5700

0.1UF

10%

6.3V X5R 201

L5720

1 2

0402-LF

=PP3V42_G3H_TPAD

1

C5720

0.1UF

10%

6.3V

2

X5R 201

1

2

IPD Flex Connector

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

SMC_PME_S4_WAKE_L

6

40 41

OUT

USB_TPAD_P

6

67

6

67

USB_TPAD_N

BI BI

OUT IN

OUT

=I2C_TPAD_SDA =I2C_TPAD_SCL

SMC_ONOFF_L SMC_LID

SMC_TPAD_RST_L

VOLTAGE=5V

6

43 48

6

43 48

PP5V_TPAD_FILT

MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm

6

40 41 48

6

40 41 48 51

6

41 48

CRITICAL

J5700

FF14A-14C-R11DL-B-3H

F-RT-SM

15

1 2 3 4 5 6 7 8

9 10 11 12 13 14

16

518S0794

PLACE_NEAR=J5700.8:1.5MM

PLACE_NEAR=J5700.9:1.5mm

1

C5732

100PF

5%

25V

2

CERM

C5733

201

100PF

CERM

PLACE_NEAR=J5700.11:1.5MM

PLACE_NEAR=J5700.12:1.5MM

1

5%

25V

2

201

1

C5734

100PF

5%

25V

2

C5735

CERM

201

100PF

25V

CERM

201

PLACE_NEAR=J5700.14:1.5MM

1

5%

2

=I2C_TPAD_SDA

=I2C_TPAD_SCL

SMC_ONOFF_L

SMC_LID

SMC_TPAD_RST_L

1

C5736

100PF

5%

25V

2

CERM

201

6

43 48

6

43 48

6

40 41 48

6

40 41 48 51

6

41 48

D

C

Keyboard Backlight Driver & Detection

=PP5V_S0_KBDLED

7

B

40

To detect Keyboard backlight, SMC will tristate and read SMC_SYS_KBDLED:

If LOW, keyboard backlight present If HIGH, keyboard backlight not present

R5853 always stuffed, R5854 only grounded when KB BL flex connected.

BI

BYPASS=U5750.1:2:2 MM

SMC_SYS_KBDLED

KBDLED_FB

6

C5750

1UF

402-1

1

R5755

4.7

5% 1/16W MF-LF 402

2

1

10%

10V

2

X5R

NC

3

6

5

MIC2292

EN

FB

NC

GND

U5750

CRITICAL

4

A

6 3

CRITICAL

L5750

10UH-0.58A-0.35OHM

1 2

1098AS-SM

2

VIN

MLF

SW

OUT

THRM

PAD

8

9

7

1

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE

KBDLED_ANODE

6

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

1

2

C5755

0.22UF

10%

50V

X5R-CERM 0603-1

1

2

C5756

0.22UF

10%

50V

X5R-CERM 0603-1

Keyboard Backlight Connector

CRITICAL

J5715

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.25 MM

FF14A-4C-R11DL-B-3H

NC

F-RT-SM

5

J5815 pin 1 is grounded

1

on keyboard backlight flex

2 3 4

6

518S0793

SYNC_MASTER=K21_MLB

PAGE TITLE

IPD / KBD Backlight

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

57 OF 109

SHEET

48 OF 72

124578

SIZE

B

A

D

8 7 6 5 4 3

12

D

C

DUAL I/O MODE (MODE 0 & 3) SUPPORTED

=PP3V3_SUS_ROM

7

41 42 68 41 42 68

IN IN

41 42 68

IN

6

19 42

IN

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

High Speed CLK Frequency - 50MHz for fast read dual I/O

1

R6101

3.3K

5% 1/20W MF 201

2

SPI_MLB_CLK

SPI_MLB_CS_L SPI_WP_L SPIROM_USE_MLB

C6100

0.1UF

X5R-CERM

0201

1

10% 16V

2

6

1 3 7

SCK

SST25VF064C

CE* WP*

RST*/HOLD*

VDD

U6100

64MBIT

WSON

OMIT_TABLE

VSS

CRITICAL

SI/SIO0

SO/SOI1

THRM_PAD

984

5

2

SPI_MLB_MOSI

SPI_MLB_MISO

41 42 68

OUT

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

SPI ROM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/13/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

61 OF 109

SHEET

49 OF 72

124578

8 7 6 5 4 3

SPEAKER AMPLIFIERS

APN:353S2888

12

SPEAKER LOWPASS

D

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

=PP5V_S3_AUDIO_AMP

7

6

39 71

6

39 71

6

C

39

IN

SPKRAMP_INR_P

SPKRAMP_INR_N

AUD_GPIO_3

1

R6211

100K

5% 1/20W MF 201

2

CRITICAL

C6211

0.1UF

1 2

10% 16V

X5R-CERM

0201

GAIN

CRITICAL

C6210

0.1UF

1 2

10% 16V

X5R-CERM

0201

R6210

0

1 2

5%

1/20W

MF

201

R6214

1 2

1/20W

201

R_SPKRAMP_SHDN

80 HZ < FC < 132 HZ

6DB

0

5% MF

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_U6210

71

MAX98300_R_P MAX98300_R_N

71

C6207

0.1UF

6.3V

D

1

10%

2

X5R 201

A1

PVDD

U6210

MAX98300

WLP

A3

IN+

CRITICAL

B3

IN-

C2

B2

NC

PGND

A2

OUT+ OUT-

GAINSHDN*

NOSTUFF

R6213

100K

1/20W

B1 C1

C3

R_AMP_GAIN

1

5% MF

201

2

1

R6212

100K

2

5% 1/20W MF 201

CRITICAL

1

C6201

47UF

20%

6.3V

2

POLY-TANT 2012-LLP

SPKRAMP_ROUT_P

MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.30 mm

SPKRAMP_ROUT_N

MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.30 mm

6

51 71

6

51 71

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=K21_MLB

PAGE TITLE

AUDI0: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

62 OF 109

SHEET

50 OF 72

124578

8 7 6 5 4 3

12

MLB to LIO Power Cable Connector

CRITICAL

J6900

WTB-PWR-M82

M-RT-SM

1

2 3

4

D

5 6

518S0508

C6905

0.1UF

603-1

10% 50V X7R

C

S3_S0_LED

D6910

GREEN-3.6MCD

2.0X1.25MM-SM

ALL_SYS_PWRGD

23 25 40 61

IN

B

=PP18V5_DCIN_CONN

6 7

=PP5V_S3_LIO_CONN

NO STUFF

1UF

NO STUFF

CRITICAL

1

10% 35V

2

X5R 603

C6908

1UF

1

10% 35V

2

X5R 603

1

2

CRITICAL

C6907

Debug LEDs

(For development only)

=PP3V3_S3_DBGLEDS

7

S3_S0_LED

R6940

1/20W

DBGLED_S3

DBGLED_S0

S3_S0_LED

A

D6920

GREEN-3.6MCD

2.0X1.25MM-SM

K

DBGLED_S0_D

HALL-SENSOR-MLB-PADS-K99

6 7

MPM5:NO

1

R6912

1

R6910

100K

5% 1/20W MF 201

2

K

A

40.2K

1% 1/20W MF 201

2

CRITICAL

D6912

GDZT2R6.8

GDZ-0201

R6920

4.7

1 2

5%

1/8W

MF-LF

805

R6905

10

1 2

5%

1/8W

MF-LF

805

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

PPDCIN_G3H_OR_PBUS_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

PART NUMBER

118S0560 CRITICAL 117S0008 MPM5:YES

QTY

1 1

CRITICAL

D6905

BAT30CWFILM

SOT-323

1

3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm

2

MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

DESCRIPTION

RES,MF,90.9KOHM,1,1/20W,0201

RES,MF,100KOHM,1,1/20W,0201

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

NC

C6992

4.7UF

X5R-CERM

1

10% 25V

2

0603

C6990

4.7UF

X5R-CERM

0603

1

C6991

4.7UF

10% 25V

2

X5R-CERM

C6997

4.7UF

X5R-CERM

1

C6996

4.7UF

10% 25V

2

X5R-CERM

0603

1

10% 25V

2

0603

C6993

4.7UF

X5R-CERM

1

10% 25V

2

0603

REFERENCE DES

R6912 R6911

6

3

BOOST

VIN

U6990

LT3470A

DFN

8 4

SHDN*

7

NC

1

10% 25V

2

0603

CRITICAL

GND

5

BIAS

THRM

PAD

CRITICAL

BOM OPTION

CRITICAL

P3V42G3H_BOOST

DIDT=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

2

1

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

P3V42G3H_FB

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

SW

FB

9

C6994

0.22UF

10% 10V

CERM

402

1

C6906

0.1UF

10% 16V

2

X5R-CERM 0201

=PP18V5_DCIN_ISOL

7

S3_S0_LED

1

R6941

1K

5%

1/16W MF-LF

MF

402

201

2

CRITICAL

Q6910

SI5419DU

POWERPAK

D

1

G

4

DCIN_ISOL_GATE_R

5A

S

5

MPM5:YES

1

C6912

0.1UF

10% 50V

2

X5R-CERM

0402

DCIN_ISOL_GATE

PPBUS_G3H

6 7

MPM5:NO

R6911

1 2

1/20W

6.8V Zener

0

5%

MF

201

S3_S0_LED

Q6940

SSM3K15FV

3

D

SOD-VESM-HF

1

GS

2

MPM5:YES

1

2

10UH-30%-0.85A-460MOHM

1 2

1

C6995

22PF

5% 50V

2

CERM 402

=PP3V42_G3H_HALL

6 7

SMC_LID_R

6

R6961

0

1 2

5% 1/16W MF-LF

402

CRITICAL

L6995

2520

<Ra>

R6995

348K

1/16W MF-LF

<Rb>

R6996

200K

1/16W MF-LF

SMC_LID

1

1%

402

2

1

1%

402

2

J6955

SM

8

NC

7 6

NC

OMIT_TABLE

518-0369

NO STUFF

1

C6955

0.001UF

10% 50V

2

CERM

402

=PP3V42_G3H_REG

Vout = 3.425V 60MA MAX OUTPUT (Switcher limit)

CRITICAL

1

C6999

10UF

20% 10V

2

X5R-CERM 0402-1

1 2 3 45

6

40 41 48

1

2

NC

CRITICAL

C6998

10UF

20% 10V X5R-CERM 0402-1

D

C

7

B

Vout = 1.25V * (1 + Ra / Rb)

K99-Specific

Battery Connector

PPVBAT_G3H_CONN

1

CRITICAL

J6950

BAT-K99

F-RT-TH

1

POS

2

POS

3

POS

4

SCL

5

SDA

NEG NEG NEG

6 7 8 9

10 11 12 13

A

SYS_DETECT

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

C6951

1UF

10% 16V X5R 402

=SMBUS_BATT_SCL =SMBUS_BATT_SDA SYS_DETECT_L

6

C6950

0.1UF

10% 25V

2

X5R 402

1

1/20W

10K

1

5%

MF

201

2

R6950

518-0369

3

2

6

52

6

43

IN

6

43

BI

CRITICAL NO STUFF

D6950

RCLAMP2402B

SC-75

Right Speaker Connector

CRITICAL

J6903

78171-0002

M-RT-SM

3

50 71

6

IN

6

IN

SPKRAMP_ROUT_P SPKRAMP_ROUT_N

1

2

4

518S0519

6 3

SYNC_MASTER=K21_MLB

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/11/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

69 OF 109

SHEET

51 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

Need to stuff R7092 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!

BOOST

DFN

GND

5

33UF-0.06OHM

CRITICAL

C7040

62UF

POLY

CASE-B

THRM

20% 11V

3

PAD

5.5v "G3Hot" Supply For Erp Lot6 spec

BIAS

9

SW

FB

C7031

POLY-TANT

CASE-D3L

1

2

C7017

2

1

10UF

1

20% 25V

2

CRITICAL

C7041

1

10% 25V

2

X5R 805

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

62UF

20% 11V

POLY

CASE-B

P5V1_BOOST

DIDT=TRUE

1

C7094

0.22UF

10% 10V

2

P5V1_SW

P5V1_FB

CERM

402

1

2

C7095

22PF

5% 50V CERM 201

10UH-30%-0.85A-460MOHM

Vout = 1.25V * (1 + Ra / Rb)

1

2

1

2

1 2 3

1

2

C7035

1UF

10% 25V X5R 603-1

CRITICAL

SI7615DN

PWRPK-1212-8

S

C7014

1UF

10% 25V X5R 603-1

CRITICAL

C7043

Q7055

G

4

62UF

CASE-B

POLY

20% 11V

1

2

D

1

2

C7036

1UF

10% 25V X5R 603-1

1

2

5

C7013

0.1UF

10%

25V X5R 402

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=8.4V

CRITICAL

L7095

1 2

2520

<Ra>

R7095

681K

1%

1/20W

MF

201

<Rb>

R7096

200K

1%

1/20W

MF

201

PLACE_NEAR=Q7030.5:1.5mm

1

C7037

0.001UF

10% 50V

2

X7R 402

CRITICAL

F7040

8AMP-24V

1 2

1206

PLACE_NEAR=L7030.2:1.5mm

1

C7045

1000PF

10% 16V

2

X7R 201

TO/FROM BATTERY

PPVBAT_G3H_CONN

1

C7012

0.01UF

10% 25V

2

X7R 402

MF-LF

1

2

CRITICAL

C7099

10UF

20% 10V X5R 603

CRITICAL

1

C7098

10UF

1

20% 10V

2

X5R 603

2

1

2

TO SYSTEM

=PPBUS_G3H

6

51

This node is powered

Reverse-Current Protection

CRITICAL

Q7080

FROM ADAPTER

=PPDCIN_S5_CHGR

7

D

=PPDCIN_S5_CHGR_ISOL

7

ACIN pin threshold is 3.2V, +/- 50mV

DIVIDER SETS ACIN THRESHOLD AT 12.18V

Input impedance of ~40K meets sparkitecture requirements

=PP3V42_G3H_CHGR

R7000

0

1 2

5%

1/20W

MF

201

MIN_NECK_WIDTH=0.2 mm

1

2

1

2

7

43

IN

43

BI

61

IN

70

1

2

1

C

R7010

66.5K

1% 1/20W MF 201

2

SMC_RESET_L

6

40 41 42

IN

Float CELL for 1S

1

R7011

23.7K

1% 1/20W MF 201

2

R7013

1/20W

100

1

1%

MF

201

2

MIN_LINE_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

R7015

255K

1% 1/20W MF 201

2

CHGR_VCOMP_R

C7015

470PF

10% 16V

X5R-X7R

201

B

R7016

220

1%

1/20W

MF

CHGR_VNEG_R

1

C7016

470PF

10% 16V

2

X5R-X7R 201

201

CRITICAL

D7005

BAT30CWFILM

1

2

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5.1V

CHGR_RST_L =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA CHGR_VFRQ CHGR_CELL

CHGR_ACIN

CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N

C7050

0.47UF

10% 10V X5R 402

SI5419DU SI5419DU

POWERPAK

SOT-323

NO STUFF

R7002

100K

1/20W

201

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

3

1

5%

MF

2

D

G

4

52

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

5A

5

S

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

1

R7081

62K

5% 1/20W MF 201

2

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

PPCHGR_DCIN_D_R

R7001

1 2

12

VHST

13

SMB_RST_N

11

SCL

10

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

1

C7002

1UF

10% 10V

2

X5R 402

4.7

5% 1/16W MF-LF

402

19

VDD

U7000

(AGND)

THRM_PAD

29

PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm

R7080

100K

5%

1/20W

MF

201

PP5V5_DCIN:NO

52

20

VDDP

TQFN

ISL6259HRTZ

20V/V

36V/V

(OD)

PGND

22

XW7000

SM

1 2

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm

1

VOLTAGE=18.5V

2

R7005

1 2

1/10W MF-LF

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

CRITICAL OMIT_TABLE

DCIN

SGATE AGATE

CSIP CSIN

BOOT UGATE PHASE

LGATE

BGATE

AMON

BMON

ACOK

through body diodes: * DCIN through Q7080. * PBUS through Q7085, Charger TOP FETs and Q7055.

PPDCIN_G3H_OR_PBUS

1

C7084

4.7UF

10% 25V

2

X5R-CERM

0603

(CHGR_SGATE)

20

(CHGR_DCIN)

MIN_LINE_WIDTH=0.5 mm

5%

MIN_NECK_WIDTH=0.2 mm

603

C7001

2

CHGR_DCIN

52

26

CHGR_SGATE

1

CHGR_AGATE

28

CHGR_CSI_P

70

27

CHGR_CSI_N

70

25

CHGR_BOOT

24

CHGR_UGATE

23

CHGR_PHASE

21

CHGR_LGATE

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

Inrush Limiter

CRITICAL

Q7085

POWERPAK

5A

5

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

C7020

0.047UF

10% 16V

2

X7R 402

C7022

0.1UF

GATE_NODE=TRUE

S

G

4

(CHGR_AGATE)

1

10% 25V

2

X5R 402

1

2

C7025

0.22UF

10% 10V CERM 402

C7085

0.1UF

1UF

10% 10V X5R X5R 402

470K

2

1% 1/20W MF 201

2

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

OUT OUT OUT

DIDT=TRUE

DIDT=TRUE GATE_NODE=TRUE

45

41 44

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

10% 25V X5R 402

1

2

1

R7085

1

D

R7021

1 2

1/20W

R7022

1 2

1/20W

1

C7021

0.1UF

10% 25V

2

402

PLACE_NEAR=U7000.25:2mm

10

5%

MF

201

10

5%

MF

201

1

6

R7051 R7052

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

CHGR_CSI_R_P

70

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_CSI_R_N

70

2

3 4 5

2.2

1 2

201

1 2

R7086

7

PPCHGR_DCIN_D_R

52

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm

1

332K

1%

1/20W

MF

201

2

CRITICAL

Q7030

RJK03P0DPA

WPAK

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_CSO_R_P

70

5% MF

CHGR_CSO_R_N

70

5%01/20W

(PPVBAT_G3H_CHGR_R)

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

1/20W

(CHGR_BGATE)

1

C7042

2

0.1UF

10%

6.3V X5R 201

C7011

0.01UF

10% 10V X5R 201

1

2

C7000

2

1UF

10% 10V X5R 402-1

C7005

0.22UF

X5R-CERM

0603-1

10% 50V

1

2

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

C7026

1000PF

1

10% 16V

2

X7R 201

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

MF-LF

CRITICAL

123

R7020

0.020

0.5% MF-LF 0612 1W

4

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=18.5V

Max Current = 8A

f = 400 kHz

MIN_NECK_WIDTH=0.1 mm MIN_LINE_WIDTH=0.2 mm

MF

NO STUFF

MIN_NECK_WIDTH=0.2 mm

R7092

MIN_LINE_WIDTH=0.5 mm

0

1 2

1/16W

5%

C7090

402

4.7UF

X5R-CERM

10% 25V

0603

CHGR_DCIN_D

1

2

33UF-0.06OHM

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.4V

R7050

0.01

0.5% 1W MF

0612-3

2 1

4 3

MIN_LINE_WIDTH=0.2 mm

201

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

6

VIN

U7090

LT3470A

8 4

SHDN*

CRITICAL

7

NC

CRITICAL CRITICAL

1

C7030

20% 25V

2

POLY-TANT

CASE-D3L

CRITICAL

L7030

4.7UH-17A

1 2

PIMC104T4R7MN-SM

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.4V

12

PP5V5_DCIN:YES

R7090

0

1 2

5%

402

1/16W

PP5V5_VDDP

R7091

0

1 2

PP5V1_CHGR_VDDP

402

5%

1/16W

PP5V5_CHGR_VDDP

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm VOLTAGE=5.5V

Vout = 5.50V 200MA MAX OUTPUT (Switcher limit)

CHGR_DCIN

7

52

D

C

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

.

SYNC_DATE=10/10/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

70 OF 109

SHEET

52 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PPVIN_S0_VCCSAS0

7

=PP5V_S0_VCCSA

7

1

R7101

2.2

5% 1/16W MF-LF

402

U7100

ISL95870AH

EN

CRITICAL

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

SET0

SET1

VID0

(ENDIAN SWAP)

VID1

XW7100

SM

1 2

PLACE_NEAR=U7100.3:1mm

VCC

GND

2

19

3

PP5V_S0_VCCSAS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

C

CPU_VCCSASENSE

12

IN

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

VCCSAS0_RTN_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

XW7101

PLACE_NEAR=C1763.2:3mm

B

R7151

1.62K

1 2

1%

1/20W

MF

201

R7153

1.62K

1 2

1%

1/20W

MF

201

2

SM

1

C7106

10PF

5% 50V

2

COG 0201

1

2

R7154

3.24K

1% 1/20W MF 201

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7152

3.24K

1% 1/20W MF 201

2

C7103

0.022UF

CERM-X5R

1

C7105

10PF

5% 50V

2

COG 0201

VCCSAS0_SREF

6

1

R7147

20K

1% 1/20W MF 201

2

1

2

R7148

49.9K

1% 1/20W MF 201

2

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

VCCSAS0_SET1_R

6

1

R7149

511K

1% 1/20W MF 201

2

10% 16V

402

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

R7150

56K

1 2

1%

1/20W

MF

201

61

IN

61

OUT

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

C7102

2.2UF

20% 10V

2

X5R-CERM 0402

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

12

IN

12

IN

=PVCCSA_EN

CPU_VCCSASENSE_R

VCCSAS0_VO

VCCSAS0_OCSET

PVCCSA_PGOOD

6

R7103

5%

1/20W

MF

201

CPU_VCCSA_VID<1>

CPU_VCCSA_VID<0>

VCCSAS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=0V

VCCSAS0_RTN VCCSAS0_FSEL

VCCSAS0_SET0

VCCSAS0_SET1

1

0

2

10

7

12

11

14

4

13

8

9

6

5

UTQFN

PVCC

PGND

1

2

20

BOOT

UGATE

PHASE

LGATE

2

CRITICAL

C7101

10UF

20% 10V X5R-CERM 0402-1

1815

17

16

1

VCCSAS0_BOOT_RC

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

VCCSAS0_VBST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

VCCSAS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

VCCSAS0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

VCCSAS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

(VCCSAS0_OCSET)

(VCCSAS0_VO)

R7130

1/16W MF-LF

10% 16V

1

2

R7141

1/20W

CRITICAL

C7120

10UF

10% 16V

X5R-CERM

0805

CRITICAL

1.0UH-7.7A

1 2

1

1K

1%

MF

C7140

201

2

1000PF

1

2

L7100

FDV0630H-SM

5%

25V

NP0-C0G

402

12

CRITICAL

C7119

4 5

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

10UF

X5R-CERM

0805

CRITICAL

Q7100

SIZ710DT

POWERPAK-6X3.7

8

1

C7130

1

0.22UF

0

5%

402

10% 10V

2

CERM 402

2

2 3 7

1

6

PLACE_NEAR=Q7100.2:1.5mm

C7121

0.1UF

10% 16V

X7R-CERM

402

PPVCCSA_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

VCCSAS0_CS_P

44 71

VCCSAS0_CS_N

44 71

1

R7142

1K

1% 1/20W MF 201

2

C7122

1000PF

NP0-C0G

1

5%

25V

2

402

C7123

62UF

20% 11V

POLY

CASE-B

CRITICAL

R7140

0.001

1%

1W MF-1 0612

1 2 3 4

1

2

=PPVCCSA_S0_REG

7

6A Max Output

1

C7141

2

270UF

20% 2V TANT CASE-B2-SM

f = 300 kHz

1

2

CRITICAL

OCP = R7141 x 8.5uA / R7140 OCP = 8.5A

D

C

B

INTEL TABLE:

VID1 VID0 Voltage

0 0 0.9V

1 0 0.8V

0 1 0.725V

1 1 0.675V

A

SYNC_MASTER=J13_MLB

PAGE TITLE

System Agent Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/01/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

71 OF 109

SHEET

53 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

B

7

F=400KHZ

Vout = 5.0V

CRITICAL

1

C7254

62UF

20%

6.3V

2

ELEC

CASE-B2S

=PPVIN_S5_P5VP3V3

CRITICAL

=PP5V_S3_REG

7

54

CRITICAL

1

C7252

150UF

20%

6.3V

2

POLY-TANT

CASE-B2-SM

CRITICAL

1

C7253

150UF

20%

6.3V

2

POLY-TANT CASE-B2-SM

PLACE_NEAR=L7220.1.2:1.5mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

CRITICAL

1

C7242

62UF

20% 11V

2

POLY

CASE-B

PLACE_NEAR=L7220.1:3mm

1

C7250

10UF

20%

10V

2

X5R 603

1

C7271

1000PF

10% 16V

2

X7R 201

P5VS3_VFB1-R

1

R7220

41.2K

1% 1/20W MF 201

2

1

R7221

10K

1% 1/20W MF 201

2

PLACE_NEAR=Q7220.2:1.5mm

1

C7240

62UF

20% 11V

POLY

CASE-B

1.5UH-20%-18A-15MOHM

C7270

1000PF

10% 16V

2

X7R 201

CRITICAL

L7220

1 2

PCMC063T-SM

152S1424

2

XW7220

SM

1

PLACE_NEAR=L7220.1:3mm

2

XW7222

SM

1

C7241

1UF

10% 16V

2

X5R 402

CRITICAL

Q7220

SIZ710DT

POWERPAK-6X3.7

PLACE_NEAR=L7220.2:3mm

2

XW7221

SM

1

237

8

45

P5VS3_CSP1_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

6

R7256

4.22K

1/20W

P5VS3_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

1

C7224

10% 25V

2

X5R 402

C7218

R7247

1.33K

1 2

1

1%

MF

201

2

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

0.1UF

1 2

10% 16V X5R 402

1%

1/20W

MF

201

C7200

R7245

1

1UF

10% 16V

2

X5R 402

0

5% 1/16W MF-LF

402

P5VP3V3_VREG3

54

P5VS3_COMP1_R

C7236

4700PF

54

1

2

1

10% 10V

2

X7R 201

P5VP3V3_VREF2

61

=PP5V_S3_REG

7

54

1

R7200

0

5% 1/20W MF

201

2

P5VP3V3_SKIPSEL

P5VS3_VBST

P5VS3_DRVH

P5VS3_LL

P5VS3_DRVL

P5VS3_CSP1

P5VS3_CSN1

P5VS3_FUNC

P5VS3_VFB1 P5VS3_COMP1

1

R7249

0

5% 1/20W MF 201

2

SKIP_5V3V3:INAUDIBLE

1

R7201

0

5% 1/20W MF

201

2

P5VS3_EN_R

GND_P5VP3V3_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

PLACE_NEAR=U7201.4:2mm

1

R7251

0

5% 1/20W MF 201

2

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

1

32

30

DRVL1

7

CSP1

8

11

MODE

9

VFB1 VFB2

10

4 5

SKIP_5V3V3:AUDIBLE

DIDT=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7236

7.5K

1% 1/20W MF 201

2

OUT

61 61

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

NO STUFF

R7248

0

1 2

1/20WMF201

5%

NO STUFF

1

R7237

20K

1% 1/20W MF 201

2

1

C7237

270PF

10% 16V

2

X7R-CERM

0201

P5VS3_PGOOD

P3V3S5_PGOOD

=P5VS3_EN

IN IN

7

=PP5V_S5_LDO

23

29

VIN

VREG5

CRITICAL

U7201

QFN

TPS51980

THRM_PAD

GND

28

XW7200

SM

1 2

PLACE_NEAR=U7201.28:1mm

22

VREG3

33

54

13

VREF2

EN

VBST2VBST1

DRVH2DRVH1

SW2SW1

DRVL2

CSP2 CSN2CSN1

RF

COMP2COMP1

EN2EN1

PGOOD2PGOOD1

353S2678

=P3V3S5_EN

P5VP3V3_VREG3

P5VP3V3_VREF2

12

26

24

25

27

18

17

3

16 15

21

20

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

C7201

0.22UF

10% 10V

2

CERM

402

=P5V3V3_REG_EN

P3V3S5_RF

P3V3S5_EN_R

PLACE_NEAR=U7201.21:2mm

1

R7252

0

5% 1/20W MF 201

2

IN

P3V3S5_VBST

P3V3S5_DRVH

GATE_NODE=TRUE

P3V3S5_LL

SWITCH_NODE=TRUE

P3V3S5_DRVL

GATE_NODE=TRUE

P3V3S5_CSP2

P3V3S5_CSN2

P3V3S5_VFB2

P3V3S5_COMP2 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7206

249K

1% 1/20W MF 201

2

C7238

4700PF

10% 10V X7R 201

P5VP3V3_VREF2

54

C7203

2.2UF

X5R-CERM

20% 10V

402

61

1

2

1

2

1

R7238

7.5K

1% 1/20W MF 201

2

P3V3S5_COMP2_R

1

C7205

2

DIDT=TRUE

1

R7239

20K

1% 1/20W MF 201

2

C7239

X7R-CERM

10UF

20% 10V

X5R

603

NO STUFF

220PF

10% 25V

201

P3V3S5_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

2

R7264

0

5% 1/16W MF-LF 402

1

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

1

2

C7288

0.1UF

1 2

10% 16V X5R 402

R7246

1.54K

1 2

1%

1/20W

MF

201

C7264

0.1UF0.1UF

1

10% 25V

2

X5R 402

1

R7216

6.65K

1% 1/20W MF 201

2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

6

P3V3S5_CSP2_R

2 3 7

4 5

CRITICAL

C7284

62UF

20% 11V

POLY

CASE-B

CRITICAL

Q7260

SIZ710DT

POWERPAK-6X3.7

8

CRITICAL

1

C7282

2

CASE-B

XW7260

PLACE_NEAR=L7260.1:3mm

62UF

1

20% 11V

2

POLY

2

SM

1

C7281

1UF

10% 16V

2

X5R 402

CRITICAL

L7260

2.5UH-14A

1 2

PCMC063T-SM

XW7261

PLACE_NEAR=L7260.2:3mm

SM

XW7262

2

1

SM

PLACE_NEAR=Q7260.2:1.5mm

1

C7283

1000PF

10% 16V

2

X7R 201

=PP3V3_S5_REG

Vout = 3.3V

6.5A MAX OUTPUT7.2A MAX OUTPUT

F=400KHZ

1

C7290

10UF

20%

10V

2

X5R 603

2

1

PLACE_NEAR=L7260.2:3mm

P3V3S5_VFB2_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7260

23.2K

1% 1/20W MF 201

2

1

R7261

10K

1% 1/20W MF 201

2

CRITICAL

150UF-0.018OHM-1.8A

1

C7292

20%

6.3V

2

TANT

CASE-B2-SM

PLACE_NEAR=L7260.2:1.5mm

1

C7272

1000PF

10% 16V

2

X7R 201

D

7

C

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

5V / 3.3V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

72 OF 109

SHEET

54 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PPVIN_S3_DDRREG

7

CRITICAL

1

C7330

62UF

20% 11V

2

POLY

OUT

XW7360

1 2

PLACE_NEAR=C7361.1:3mm

CRITICAL

PLACE_NEAR=C3101.1:1mm

SM

C7360

CASE-B

402

5%

1 2

8

10UF

20%

6.3V X5R 603

R7325

1

2

0

MF-LF

1/16W

CRITICAL

1

C7361

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=C3101.1:3mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

=PPVIN_S0_DDRREG_LDO

7

=PP5V_S3_DDRREG

7

1

C7300

10UF

20% 10V

2

X5R 603

PLACE_NEAR=U7300.12:1mm

C

=DDRVTT_EN

8

26

IN

=DDRREG_EN

61

IN

DDRREG_1V8_VREF

1V5R1V35_SW

DDRREG_P1V35_L

1V5R1V35_SW

CRITICAL

SSM3K15AMFVAPE

PLACE_NEAR=U7300.8:5mm

Q7319

R7314

150K

1

C7315

0.1UF

10% 16V

2

X5R 402

PLACE_NEAR=U7300.6:1mm

1

1%

1/20W

MF

201

2

3

D

1

R7315

20K

1% 1/20W MF 201

2

PLACE_NEAR=U7300.8:5mm

LVDDR3_HW:NO

1

R7316

100K

1% 1/20W MF 201

2

PLACE_NEAR=U7300.8:5mm

1

2

C7316

0.01UF

10% 16V CERM 402

PLACE_NEAR=U7300.8:1mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

2

PLACE_NEAR=U7300.19:3mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

R7317

200K

1% 1/20W MF 201

VESM

1

G S

2

B

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=0V

VDDQ/VTTREF Enable

31

PLACE_NEAR=U7300.18:3mm

VTT Enable

DDRREG_FB

DDRREG_MODE

DDRREG_TRIP

1

R7318

84.5K

1% 1/20W MF 201

2

1

C7301

10UF

20% 10V

2

X5R 603

PLACE_NEAR=U7300.2:1mm

2

VLDOIN

12 15

V5IN

PGND

U7300

TPS51916

CRITICAL

GND

7

10

17

S3

16

S5

6

VREF

8

REFIN

19

MODE

18

TRIP

VBST DRVH

DRVL

PGOOD

VDDQSNS

VTTSNS

SW

VTT

QFN

VTTREF

THRM

VTT

PADGND

4

21

XW7300

14

13

11

20

9

7

3

1

7

31

5

10mA max load

2

SM

1

PLACE_NEAR=U7300.21:1mm

DDRREG_DRVH

GATE_NODE=TRUE

DDRREG_LL

SWITCH_NODE=TRUE

DDRREG_DRVL

GATE_NODE=TRUE

DDRREG_PGOOD DDRREG_VDDQSNS

=PPVTT_S0_DDR_LDO

DDRREG_VTTSNS

=PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

C7350

0.22UF

10% 10V

CERM

402

DDRREG_VBST

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

1

2

C7360, C7361 close to memory

DDRREG_VBST_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

CRITICAL

1

C7362

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=U7300.9:3mm

CRITICAL

1

C7331

62UF

20% 11V

2

POLY CASE-B

C7325

0.1UF

1 2

10% 25V X5R 402

(DDRREG_LL)

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.17 mm

1

C7332

2

(DDRREG_DRVH)

(DDRREG_DRVL)

1

1UF

10% 25V X5R 603-1

C7333

0.001UF

10% 50V

2

X7R 402

CRITICAL

1

C7334

62UF

20% 11V

2

POLY CASE-B

5

D

CRITICAL

S

1 2 3

D

S

Q7330

IRFHM831PBF

PQFN3.3X3.3

CRITICAL

L7330

0.88UH-20%-19A-2.3MOHM 1 2

MPCG1040LR88-SM

45 71

CRITICAL

Q7335

IRFHM830DPBF

PQFN3.3X3.3

45 71

OUT

PPDDR_S3_REG_R

VOLTAGE=1.5V MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

ISNS_1V5_S3_P

ISNS_1V5_S3_N

CRITICAL

R7350

0.001

0.5W

MF

1206

1%

1 2 3 4

CRITICAL

1

C7340

330UF

20%

2.0V

2

POLY-TANT CASE-B2-SM1

CRITICAL

C7341

POLY-TANT

CASE-B2-SM1

330UF

=PPDDR_S3_REG

1

C7346

0.001UF

10% 50V

2

X7R

1

2

C7345

10UF

20%

402

6.3V X5R 603

2

XW7301

SM

1

PLACE_NEAR=C7340.1:1mm

1

20%

2.0V

2

7

Vout = 1.5V

14.1A max output

(Q7335 limit) f = 400 kHz

G

4

5

G

4

1 2 3

D

C

B

MEM_VDD_SEL_1V5_L

17

IN

PART NUMBER

118S0460

QTY

1

DESCRIPTION

RES,MF,60.4KOHM,1,1/20W,0201

REFERENCE DES

R7316

CRITICAL

BOM OPTION

LVDDR3_HW:YES

If LVDDR3_HW:NO is turned ON, switch R2821 & R7971 back to the original value for 1.5V DDR unless 1V5R1V35_SW is turned ON

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

1.5V DDR3 Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=10/07/2011

2.7.0

73 OF 109

55 OF 72

SIZE

A

D

8 7 6 5 4 3

12

D

C

100KOHM-1%-100MW

B

CRITICAL

R7469

0603

1

R7468

5.76K

1% 1/20W MF 201

2

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

1

2

PLACE_NEAR=Q7510.1:2mm

P5V_S0_CPUIMVP_VDD

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

1

R7466

5.76K

1% 1/20W MF 201

2

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

1

CRITICAL

R7467

100KOHM-1%-100MW

0603

2

PLACE_NEAR=Q7550.1:2mm

=PPVCCIO_S0_CPUIMVP

7

CPUIMVP_VR_ON

61

IN

CPU_VIDSOUT

12 65

IN

CPU_VIDSCLK

12 65

IN

CPU_VIDALERT_L

12 65

IN

NO STUFF

1

R7464

200K

1% 1/20W MF 201

2

1

R7465

10K

1% 1/20W MF 201

2

PLACE_NEAR=U7400.18:2mm

CPU_PROCHOT_L

10 40 41 65

OUT

1

R7462

215K

1% 1/20W MF 201

2

1

R7463

137K

1% 1/20W MF 201

2

R7479

54.9

1/20W

1

R7480

130

1%

1% 1/20W

MF

201

2

PLACE_NEAR=U7400.16:2mm

1

R7460

215K

1% 1/20W MF 201

2

1

R7461

137K

1% 1/20W MF 201

2

GND_CPUIMVP_SGND

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

CPUIMVP_PGOOD

25

OUT

CPUIMVP_AXG_PGOOD

61

OUT

CPUIMVP_NTC CPUIMVP_NTCG

CPUIMVP_SLEW

CPUIMVP_IMAXA CPUIMVP_IMAXB

C7401

2.2UF

X5R-CERM

NO STUFF

1

C7444

47PF

5% 25V

2

NP0-C0G 201

1

20% 10V

2

402

31

NC

39

5

19 10

1

16 18 17

33 34

32

29 30

1

C7440

1000PF

10% 16V

2

X7R 201

1

C7441

1000PF

10% 16V

2

X7R 201

CPU_VCCSENSE_R

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

1

2

R7401

10

1 2

5% 1/16W MF-LF

402

402415

VCC

VDDA

VDDB

U7400

MAX15120

TQFN

DRVPWMA

CRITICAL

GNDSA

3

GNDSB

7

BSTA1

DHA1 LXA1 DLA1

CSPA1

CSPAAVE

CSNA

CSPA2 BSTA2

DHA2 LXA2 DLA2

BSTB

CSPB1

CSNB

PAD

THRM

41

CSPA3 VR_HOT*

POKA POKB

EN

VDIO CLK ALERT*

THERMA THERMB

SR

IMAXA IMAXB

CPU_AXG_SENSE_R

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

NO STUFF

1

NO STUFF

C7442

0.01UF

10% 10V X5R 201

C7443

0.01UF

10% 10V

2

X5R 201

TON

FBA

DHB LXB DLB

FBB

XW7400

2

CPUIMVP_TON

20

CPUIMVP_BOOT1

22

CPUIMVP_UGATE1_R

21

CPUIMVP_PHASE1

23

CPUIMVP_LGATE1

36

CPUIMVP_ISUM_P

35

CPUIMVP_ISUM

37

CPUIMVP_ISUM_N

4

CPUIMVP_FBA

38 28

NC

26

NC

27

NC

25

NC

11

CPUIMVP_BOOT1G

13

CPUIMVP_UGATE1G

12

CPUIMVP_PHASE1G

14

CPUIMVP_LGATE1G

8

CPUIMVP_ISUMG_P

9

CPUIMVP_ISUMG_N

6

CPUIMVP_FBB

SM

12

R7440

10

1 2

5%

1/20W

MF

201

R7441

10

1 2

5%

1/20W

MF

201

1

C7402

2.2UF

20% 10V

2

X5R-CERM 402

PLACE_NEAR=U7400.24:2mm

PLACE_NEAR=U7400.15:2mm

1

C7418

100PF

2

NO STUFF

5% 25V CERM 201

1

2

CPU_AXG_SENSE_N

CPU_VCCSENSE_N

=PP5V_S0_CPUIMVP

1

C7403

2.2UF

20% 10V

2

X5R-CERM 402

OUT

OUT OUT

56

OUT OUT OUT OUT

56

NO STUFF

C7419

100PF

5% 25V CERM 201

R7402

90.9K

1 2

57

1

C7414

2

1% 1/16W MF-LF

402

NO STUFF

100PF

5% 25V CERM 201

R7403

1 2

5%

1/16W

12 65

IN

12 65

IN

7

=PPVIN_S0_CPUIMVP

CPUIMVP_UGATE1

2.2

MF-LF

402

NO STUFF

1

C7415

100PF

5% 25V

2

CERM 201

7

57

OUT

1

C7404

2200PF

10% 10V

2

X7R-CERM 0201

NO STUFF

CPUIMVP_FBA

56

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CPUIMVP_FBB

56

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

57 71

C7409

470PF

OUT

C7452

100PF

1 2

5%

25V

CERM

201

R7412

6.34K

1 2

1%

1/20W

MF

201

R7422

8.25K

1 2

1%

1/20W

MF

201

C7462

100PF

1 2

5%

25V

CERM

201

NO STUFF

C7408

0.039UF

1 2

10% 10V

X5R-CERM

0402

1 2

5%

50V

NP0-C0G

402

57 71

MIN_LINE_WIDTH=0.2 mm

CPUIMVP_ISUM_R

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

1

C7407

0.0022UF

10% 50V

2

CERM 402

1

C7412

1000PF

10% 16V

2

X7R 201

CPUIMVP_FBA_R

C7422

1000PF

CPUIMVP_FBB_R

R7410

1 2

1/20W

201

1

10% 16V

2

X7R 201

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

1

5%

MF

R7413

10

1 2

5%

1/20W

MF

201

R7406

1 2

57 71

OUT

57 71

OUT

R7423

10

1 2

5%

1/20W

MF

201

1/20W

300

CPUIMVP_ISNS1_P

5%

MF

201

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

D

44 57 71

IN

C

B

12 65

IN

12 65

IN

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

CPU IMVP7 & AXG VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/22/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

74 OF 109

SHEET

56 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

CPU=IV Bridge ULV, AXG=GT2

12

D

=PPVIN_S0_CPUIMVP

7

56

CPUIMVP_BOOT1_RC

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

R7511

1/16W MF-LF

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

1

0

5%

402

2

1

C7511

0.22UF

10% 10V

2

CERM 402

56

IN

CPUIMVP_UGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

56

IN

DIDT=TRUE

GATE_NODE=TRUE

IN

PHASE 1

CPUIMVP_BOOT1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

C

376S0984

3

376S0985

CRITICAL

Q7510

IRF6811STRPBF

SQ

D

G

S

NC

1 2 6 7

G

5

1 2 5 64

NC

CRITICAL

D

Q7520

IRF6894MTRPBF

DIRECTFET-MX

S

1

2

CRITICAL

C7513

62UF

20% 11V POLY CASE-B

1

2

CRITICAL

C7514

62UF

20% 11V POLY CASE-B

1

2

CRITICAL

C7515

10UF

20% 25V X5R-CERM 0603

1

2

CRITICAL

C7516

10UF

20% 25V X5R-CERM 0603

0.36UH-20%-30A-1.2MOHM

3 4

THESE TWO CAPS ARE FOR EMC

1

C7517

1UF

10% 16V

2

X5R 402

CRITICAL

L7510

1 2

PIMB104T-SM

152S1323

1

C7518

0.001UF

10% 50V

2

X7R 402

PPVCORE_S0_CPU_PH1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

1

2

C7519

0.001UF

10% 50V X7R 402

CRITICAL

1

C7540

62UF

20% 11V

2

POLY CASE-B

R7513

46.4

1/20W

CRITICAL

R7510

0.00075

1 2 3 4

1

1%

MF

201

2

CRITICAL

1

C7541

62UF

20% 11V

2

POLY CASE-B

1% 1W MF

0612

CPUIMVP_ISNS1_N

44 71

1

R7514

10

1% 1/20W MF 201

2

CRITICAL

1

C7510

62UF

20% 11V

2

POLY CASE-B

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS1_P

NO STUFF

1

C7571

2200PF

10% 10V

2

X7R-CERM 0201

CRITICAL

1

C7520

62UF

20% 11V

2

POLY CASE-B

CPUIMVP_ISUM_N

CPUIMVP_ISUM_P

7

44 56 71

OUT

56 71

IN

56 71

IN

D

C

SIZE

B

A

D

B

=PPVIN_S0_CPUAXG

7

CPUIMVP_UGATE1G_R

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM

AXG PHASE

CPUIMVP_BOOT1G

56

IN

MIN_LINE_WIDTH=0.5 MM

56

DIDT=TRUE

GATE_NODE=TRUE

IN

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1G

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1G

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

A

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1G

56

IN

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT1G_RC

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

1

R7551

10

5% 1/16W MF-LF

402

2

R7555

4.7

1 2

5% 1/16W MF-LF

402

DIDT=TRUE

GATE_NODE=TRUE

C7551

0.22UF

376S1005

CRITICAL

Q7550

CSD58872Q5D

TG

3

1

10% 10V

2

CERM

402

TGR

4

BG

5

SON5X6

VIN

1

VSW

6 7 8

PGND

9

1

C7553

62UF

20% 11V

2

POLY CASE-B

CPUIMVP_VSWG

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE

DIDT=TRUE

CRITICAL

1

C7554

62UF

20% 11V

2

POLY CASE-B

NOSTUFF

1

R7552

2.2

5% 1/10W MF-LF 603

2

CPUIMVP_AXG_SNUB

NOSTUFF

1

C7552

0.001UF

10% 50V

2

CERM 402

CRITICAL

1

C7555

10UF

20% 25V

2

X5R-CERM 0603

DIDT=TRUE

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V

CRITICAL

1

C7556

10UF

20% 25V

2

X5R-CERM 0603

CRITICAL

L7550

0.36UH-20%-30A-1.2MOHM

1 2

PIMB104T-SM

152S1323

6 3

THESE TWO CAPS ARE FOR EMC

1

2

1

1UF

10% 16V X5R 402

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

C7558

2

C7557

PPVCORE_S0_AXG_R

1

C7559

0.001UF

10% 50V X7R 402

0.001UF

10% 50V

2

X7R 402

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N

44 71 44 71

CRITICAL

1

C7560

62UF

20% 11V

2

POLY CASE-B

R7553

46.4

1/20W

201

R7550

0.00075

1 2 3 4

1

1%

MF

2

CRITICAL

1% 1W MF

0612

=PPVCORE_S0_AXG_REG

1

R7554

10

1% 1/20W MF 201

2

CPUIMVP_ISUMG_N

NO STUFF

1

C7574

1000PF

10% 16V

2

X7R 201

CPUIMVP_ISUMG_P

7

SYNC_MASTER=K21_MLB

PAGE TITLE

56 71

IN

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

56 71

IN

CPU IMVP7 & AXG VCore Output

Apple Inc.

R

DRAWING NUMBER

051-9276

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=12/13/2010

2.7.0

75 OF 109

57 OF 72

124578

8 7 6 5 4 3

12

D

CPU VCCIO (1.05V S0) Regulator

=PPVIN_S0_CPUVCCIOS0

7

=PP5V_S0_CPUVCCIOS0

7

CRITICAL

UTQFN

PVCC

PGND

1

C7601

10UF

2

14

BOOT

UGATE

PHASE

LGATE

16

1

R7601

2.2

5%

1/20W

MF

3

EN

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

201

2

13

VCC

U7600

ISL95870

CRITICAL

GND

1

XW7600

SM

1 2

PLACE_NEAR=U7600.1:1mm

C

IN

OUT

2.2UF

1

10% 16V

2

X5R 603

PP5V_S0_CPUVCCIOS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

=CPUVCCIOS0_EN

CPUVCCIOS0_FB

CPUVCCIOS0_SREF

CPUVCCIOS0_VO

CPUVCCIOS0_OCSET

CPUVCCIOS0_PGOOD

CPUVCCIOS0_RTN

CPUVCCIOS0_FSEL

1

R7603

0

5% 1/20W MF 201

2

CPUVCCIOS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=0V

CPU_VCCIOSENSE_P

12 65

1/20W

1

R7644

3.01K

1% 1/20W

1

MF 201

2

<Ra>

1%

MF

201

1%

MF

201

2

1

2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

R7645

2.74K

1% 1/20W MF 201

2

<Rb>

C7604

47PF

NP0-C0G

1

C7605

5%

25V

201

47PF

5% 25V

2

NP0-C0G 201

1

C7603

2

61

C7602

0.047UF

10% 16V X7R 402

CPU_VCCIOSENSE_N

12 65

R7604

3.01K

R7605

2.74K

B

20% 10V X5R 603

12

11

10

15

CPUVCCIOS0_BOOT_RC

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

CPUVCCIOS0_VBST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

CPUVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

(CPUVCCIOS0_OCSET)

(CPUVCCIOS0_VO)

R7630

0

5%

1/10W

MF-LF

603

1 2

1UF

10% 16V

2

X5R 402

2

R7631

0

CPUVCCIOS0_R

5%

1/16W

MF-LF

402

OCP = R7641 x 8.5uA / R7640 OCP = 25.6A Vout = 0.5V * (1 + Ra / Rb)

1

C7630

1

CRITICAL

CSD58872Q5D

TG

3

TGR

4

BG

5

Q7630

SON5X6

CRITICAL

C7620

62UF

20% 11V

POLY

CASE-B

VIN

VSW

PGND

9

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

CRITICAL

1

C7621

2

1

6 7

PPCPUVCCIO_S0_REG

MIN_LINE_WIDTH=0.6 mm

8

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

1

R7641

3.01K

1%

1/20W

MF

201

2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

62UF

20% 11V

2

POLY

CASE-B

0.68UH-22A-2.7MOHM

C7640

1000PF

12

5%

25V

NP0-C0G

402

1

C7622

1000PF

5%

25V

2

NP0-C0G

402

PLACE_NEAR=Q7630.1:1.5mm

L7630

1 2

PIMB104T-SM

CRITICAL

CPUVCCIOS0_CS_P

44 71

CPUVCCIOS0_CS_N

44 71

1

R7642

3.01K

1% 1/20W MF 201

2

CRITICAL

1

C7619

62UF

20% 11V

2

POLY CASE-B

PPCPUVCCIO_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

CRITICAL

R7640

0.001

1% 1W MF

0612

12 34

PLACE_NEAR=L7630.2:1.5mm

C7623

1000PF

NP0-C0G

C

=PPCPUVCCIO_S0_REG

270UF

1

20%

2V

2

TANT

Vout = 1.05V 21A Max Output f = 300 kHz

CRITICAL

C7649

1

5%

25V

2

402

1

2

CRITICAL

C7648

270UF

20% 2V TANT CASE-B2-SM

CASE-B2-SM

7

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

CPU VCCIO (1.05V) Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/01/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

76 OF 109

SHEET

58 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

1.05V SUS LDO

D

=PP3V3_S0_P1V8S0

7

CRITICAL

1

C7724

1000PF

10% 16V

2

X7R 201

=P1V8S0_EN

61

IN

P1V8S0_PGOOD

61

OUT

C

C7720

22UF

X5R-CERM-1

1

20%

6.3V 2

603

5

EN

7

PG

4

SYNCH

SGND

9

10

1

2

VIN

U7720

ISL8014A

QFN

CRITICAL

PGND

11

3

VDD

14

LX

SWITCH_NODE=TRUE

15

LX

DIDT=TRUE

8

VFB

16

NC

6

NC

13

NC

THRM_PAD

12

17

1.8V S0 Regulator

152S1302

L7720

1.0UH-20%-4.5A-24MOHM

PIMB042T-SM

P1V8S0_SW

P1V8S0_FB

1 2

CRITICAL

R7720

113K

1/20W

<Ra>

R7721

90.9K

1/20W

<Rb>

=PP1V8_S0_REG

CRITICAL

1

C7723

47PF

5%

1

1%

MF

201

2

1

1%

MF

201

2

25V

2

NP0-C0G 201

1

2

C7721

22UF

20%

6.3V X5R-CERM-1 603

CRITICAL

C7722

X5R-CERM-1

Vout = 1.794V Max Current = 1.8A Freq = 1 MHz

1

22UF

20%

6.3V 2

603

7

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

CRITICAL

XDP_PCH

U7740

=PP3V3_SUS_P1V05SUSLDO

7

XDP_PCH

C7740

1UF

1

10%

6.3V 2

CERM

402

TPS720105

SON

4

BIAS

6

IN

3

EN

OUT

NC

THRM

PADGND

5

7

=PP1V05_SUS_LDO

Vout = 1.05V

1

Max Current = 0.020A

2

NC

XDP_PCH

1

C7741

2.2UF

10%

6.3V

2

X5R 402

7

Vout = 0.8V * (1 + Ra / Rb)

D

C

SIZE

B

A

D

B

1.5V S0 LDO

CRITICAL

U7770

TPS72015

SON

=PP3V3_S0_P1V5S0

7

=PP1V8_S0_P1V5S0

7

IN

=P1V5S0_EN

61

IN

1

1UF

10%

6.3V

2

CERM

402

C7771

PLACE_NEAR=U7770.6:1mm

C7770

A

PLACE_NEAR=U7770.4:1mm

4

BIAS

6

IN

3

EN

1

1UF

10%

6.3V

2

CERM

402

OUT

NC

THRM

PADGND

5

7

=PP1V5_S0_REG

Vout = 1.5V

1

Max Current = 0.02A

2

NC

1

C7772

2.2UF

10%

6.3V

2

X5R 402

7

=PP3V3_S0_P1V05S0LDO

7

=PP1V8_S0_P1V05S0LDO

7

=1V05_S0_LDO_EN

61

C7782

PLACE_NEAR=U7780.4:1mm

1

1UF

10%

6.3V 2

CERM

402

PLACE_NEAR=U7780.6:1mm

6 3

1.05V S0 LDO

CRITICAL

U7780

TPS720105

4

BIAS

6

IN

3

EN

1

C7780

1UF

10%

6.3V 2

CERM

402

5

SON

OUT

NC

THRM

PADGND

7

=PP1V05_S0_LDO

Vout = 1.05V

1

Max Current = 0.35A

2

NC

1

C7781

2.2UF

10%

6.3V

2

X5R 402

7

SYNC_MASTER=K21_MLB

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

77 OF 109

SHEET

59 OF 72

124578

8 7 6 5 4 3

12

NO STUFF

R7803

0

1 2

5%

D

1

D

1/16W MF-LF

402

PP3V3_S4_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S3_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

RDS(ON)

MOSFET CHANNEL

RDS(ON)

LOADING

CHANNEL

LOADING

CRITICAL

R7804

0

1 2

5% 1/16W MF-LF

402

3.3V S4 FET

CRITICAL

R7811

0

1 2

=PP3V3_S3_FET

5% 1/10W MF-LF

603

3.3V S3 FET

SiA427MOSFET P-TYPE 8V/5V 31 mOhm @1.8V

1.608 A (EDP)

=PP3V3_S4_FET

SiA427 P-TYPE 8V/5V 31 mOhm @1.8V

0.7? A (EDP)

7

=PP3V3_S0_P3V3S0FET

7

3

7

=P3V3S0_EN

37 61

IN

=P5V_3V3_SUS_EN

60 61

IN

=P5V_3V3_SUS_EN

60 61

IN

Q7812

SSM6N37FEAPE

=PP3V3_S5_P3V3SUSFET

7

Q7822

SSM6N37FEAPE

=PP5V_S5_P5VSUSFET

7

Q7822

SSM6N37FEAPE

SOT563

5

SOT563

D

SG

4

6

D

2

SG

1

3

D

5

SG

4

3.3V S4 FET

CRITICAL

Q7800

SIA427DJ

=PP3V3_S4_P3V3S4FET

D

61

IN

7

SSM3K15AMFVAPE

=P3V3S4_EN

Q7809

VESM

1

G S

1

3

D

2

R7802

220K

5% 1/16W MF-LF 402

2

P3V3S4_EN_L

1 2

C7809

0.033UF

R7800

47K

5% 1/16W MF-LF

402

1

10% 16V

2

X5R 402

P3V3S4_SS

3.3V S3 FET

=PP3V3_S3_P3V3S3FET

7

1

6

SOT563

D

2

SG

1

C

=P3V3S3_EN

61

IN

Q7812

SSM6N37FEAPE

R7812

100K

5% 1/20W MF 201

2

P3V3S3_EN_L

1 2

C7811

0.033UF

R7810

47K

5%

1/20W

MF

201

1

10% 16V

2

X5R 402

P3V3S3_SS

4 7

Q7810

SIA427DJ

S

4 7

SC70-6L

S

G

3

C7800

0.01UF

CRITICAL

SC70-6L

G

3

C7810

0.01UF

1 2

10% 16V

CERM

402

10% 10V X5R 201

3.3V S0 FET

1

R7832

10K

5% 1/20W MF 201

2

P3V3S0_EN_L

R7830

1 2

C7831

0.033UF

91K

5%

1/20W

MF

201

1

10% 16V

2

X5R 402

P3V3S0_SS

3.3V_SUS FET

12K

5%

1/20W

MF

201

10% 16V X5R 402

1

2

P3V3SUS_SS

1

R7822

100K

5% 1/20W MF 201

2

P3V3SUS_EN_L

C7821

0.033UF

R7820

1 2

5V_SUS FET

5%

1/20W

MF

201

10% 16V X5R 402

1

2

P5VSUS_SS

1

R7842

220K

5% 1/20W MF 201

2

P5VSUS_EN_L

C7841

0.033UF

R7840

3.3K

1 2

CRITICAL

Q7830

SIA427DJ

S

4 7

3

CRITICAL

Q7820

SIA427DJ

S

4 7

3

CRITICAL

Q7840

SIA413DJ

SC70-6L

S

4 7

3

SC70-6L

G

C7830

0.01UF

1 2

10% 10V X5R 201

SC70-6L

G

C7820

0.01UF

1 2

10% 10V X5R 201

G

C7840

0.01UF

1 2

10% 16V

CERM

402

PP3V3_S0_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 MM

D

1

MIN_NECK_WIDTH=0.20MM

3.3V S0 FET

MOSFET CHANNEL

RDS(ON)

LOADING

1

D

PP3V3_SUS_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

3.3V SUS FET

MOSFET

CHANNEL

RDS(ON)

LOADING

D

1

5V SUS FET

MOSFET CHANNEL

RDS(ON)

LOADING

CRITICAL

R7831

0.001

1%

1W MF-1 0612

1 2 3 4

ISNS_3V3S0_N ISNS_3V3S0_P

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

3.2 A (EDP)

CRITICAL

R7821

0

1 2

1/16W

MF-LF

5%

402

=PP3V3_SUS_FET

SiA427

P-TYPE 8V/5V 26 mOhm @1.8V 100? mA (EDP)

=PP5V_SUS_FET

SiA427 P-TYPE 12V/8V 29 mOhm @4.5V 100? mA (EDP)

=PP3V3_S0_FET

7

44 71

7

D

C

7

1.5V S3/S0 FET

=PP1V5_S3_P1V5S3RS0_FET

=PP5V_S5_P1V5DDRFET

7

C7801

0.1UF

20% 10V

CERM

402

B

26

P1V5CPU_EN

IN

NO STUFF

C7802

4.7UF

6.3V

X5R-CERM

1

10%

2

603

7

1

2

3

VCC

U7801

SLG5AP020

TDFN

ON

CRITICAL

SHDN*

GND

4

1

5

THRM

PAD

9

D

7

G

6

S

8

PG

P1V5S0FET_GATE

R7801

0

1 2

5%

P1V5S0FET_GATE_R

1/16W MF-LF

402

P1V5S3RS0_RAMP_DONE

OUT

1 2 5 6 8

3

G

8

APN 376S0981

CRITICAL

D

Q7801

IRLHS6242TRPBF

PQFN2X2

S

4 7

PP1V5_S3RS0_FET_R

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

CRITICAL

R7850

0

1 2

5%

1/4W

MF-LF

1206

=PP1V5_S3RS0_FET

=PP5V_S3_P5VS0FET

7

=P5VS0_EN

61

IN

Q7802

SSM6N37FEAPE

SOT563

D

5

SG

5.0V S0 FET

1

R7862

220K

5% 1/20W MF 201

2

P5V0S0_EN_L

3

4

C7861

0.033UF

R7860

10K

1 2

5%

1/20W

MF

201

1

10% 16V

2

X5R 402

DMP2018LFK

2 1

P5V0S0_SS

CRITICAL

Q7860

DFN2563-6

S

G

3

C7860

0.01UF

D

1 2

10% 16V

CERM

402

4

PP5V_S0_FET_R

VOLTAGE=5V MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.4 MM

MOSFET

CHANNEL

RDS(ON)

LOADING

CRITICAL

R7841

0

1 2

5% 1/16W MF-LF

402

5.0V S0 FET

DMP2018LFK

P-TYPE

11-16 mOHM @4.5V

1.678 A (EDP)

=PP5V_S0_FET

7

B

1.5V S3/S0 FET

MOSFET CHANNEL RDS(ON) LOADING

A

PQFN2X2 N-TYPE

9.4 mOhm @4.5V 5 A (EDP)

6 3

SYNC_MASTER=K21_MLB

PAGE TITLE

Power FETs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

78 OF 109

SHEET

60 OF 72

124578

SIZE

A

D

C

B

A

40

IN

=PP3V3_S0_VMON

7

61

S0PGOOD_ISL

MAKE_BASE=TRUE

8 7 6 5 4 3

=PP3V42_G3H_PWRCTL

7

61

SMC_PM_G2_EN

=PP3V3_S5_PWRCTL

7

61

Threshold: ??

DLY > 10 ms

S5PGOOD_DLY

1

C7941

220PF

10% 25V

2

X7R-CERM 201

ALL_SYS_PWRGD

23 25 40 51 61

1

R7951

15K

1% 1/20W MF 201

2

1

R7952

7.15K

1% 1/20W MF 201

2

=PP1V5_S3RS0_VMON

7

61

PP1V5_S3RS0

=PP1V05_S0_VMON

7

61

Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

=PP5V_S0_VMON

7

R7960

R7961

6.04K

1/20W

201

15K

201

1% MF

=PP1V5_S3RS0_VMON

7

61

1

S0PGOOD_ISL

R7970

1/20W

2

P5V_DIV_VMON

1

S0PGOOD_ISL

R7971

12.4K

1/20W

2

10K

201

61

1% MF

1

1% MF

2

S5 Rail Enables & PGOOD

Internal pull-ups 100K +/- 20%

10%

6.3V X5R 201

1

2

IN_A

(IPD)

6

IN_B

C7940

0.1UF

1.3V

7

DLY_1C

R7974

0

1 2

5%

1/20W

MF

201

S0 Rail PGOOD (BJT Version)

=PP3V3_S5_VMON

7

R7953

VMON_3V3_DIV VMON_Q2_BASE

1K

1 2

5%

1/20W

MF

201

R7954

1K

1 2

5%

1/20W

MF

201

R7955

1K

1 2

5%

1/20W

MF

201

S0 Rail PGOOD Circuitry

(ISL Version in development)

=PP3V3_S0_VMON

7

61

S0PGOOD_ISL

1

1% MF

201

2

P1V05_DIV_VMON

1

15K

1% MF

201

2

C7960

0.1UF

6.3V

=PP1V05_S0_VMON

7

1

S0PGOOD_ISL

R7972

6.04K

1/20W

2

P1V5_DIV_VMON

S0PGOOD_ISL

R7973

1/20W

1

CRITICAL

343S0497

VDD

U7941

SLG4AP012

TDFN

OUT_A*

(OD,IPU)

OUT_A

DLY

THRM

PAD

(OD,IPU)

OUT_B

(OD,IPU)

9

2:1

GND

+

-

5

CPUVCORE ENABLE

PLACE_NEAR=U7400.1:5mm

1

R7956

150K

1%

1/20W

MF

201

2

S0PGD_C

NC

VMON_Q3_BASE

NC

VMON_Q4_BASE

Worst-Case Thresholds:

Q2: 0.XXXV Q3: 0.640V

3.3V w/Divider: 2.345V Q4: 0.660V

P1V5S0_PGOOD from U7710

1

10%

2

X5R 201

U7960

ISL88042IRTEZ

3

V2MON

5

V3MON

6

2

7

VDD

TDFN

CRITICAL

S0PGOOD_ISL

GND

THRM_PAD

4

4 3

8

5

8

7

2

1

(IPU)

MR*

RST*V4MON

9

353S2310

NC

P5V3V3_REG_EN

MAKE_BASE=TRUE

S5_PWRGD (old name RSMRST_PWRGD)-->SMC SMC-->PM_DSW_PWRGD

CPUIMVP_VR_ON

6

4

Q7950

Q1

Q2

Q3

CRITICAL

ASMCC0179

DFN2015H4-8

Q4

3

353S2809

S0PGD_BJT_GND_R

CPUIMVP_AXG_PGOOD

56

IN

P1V8S0_PGOOD

59

IN

P3V3S5_PGOOD

54

IN

P5VS3_PGOOD

54

IN

CPUVCCIOS0_PGOOD

58

IN

PVCCSA_PGOOD

53

1

8

IN

NC

ALL_SYS_PWRGD_R

R7941

100

1 2

5%

201

1

MF

C7942

0.033UF

10% 16V

2

X5R 402

NO STUFF

1/20W

=P5V3V3_REG_EN

S5_PWRGD

MAKE_BASE=TRUE

56

OUT

SMC_BATLOW_L:100K pull up on SMC page

ALL_SYS_PWRGD

R7957

23 25 40 51 61

Could stuff R7930 to satisfy

PCH power down timing t235

1

100

5%

1/20W

MF

201

2

=PP3V3_S0_PWRCTL

7

NO STUFF

R7968

1 2

R7965

100

1 2

5%

1/20W

R7901

MF

201

1 2

R7963

100

1 2

5%

1/20W

MF

201

S0PGOOD_ISL

R7962

330

1 2

5%

1/20W

MF

201

ALL_SYS_PWRGD

6 3

100

5%

1/20W

MF

201

100

5%

1/20W

MF

201

OUT

40

OUT

61

40 41

17

R7967

10K

1/20W

R7966

100

1 2

5%

1/20W

MF

201

R7964

100

1 2

5%

1/20W

MF

201

54

7

201

=P3V3S5_EN

IN

61

5% MF

P3V3S5_EN

MAKE_BASE=TRUE

OUT

=PP3V3_S5_PWRCTL

7

61

PLACE_NEAR=U7940.1:2.3mm

40 41

IN

3.3V/5.0V Sus ENABLE

=PP3V3_S5_PWRCTL

PLACE_NEAR=U7940.5:2.3mm

SMC_BATLOW_L

PM_SLP_SUS_L

=PP3V3_SUS_PWRCTL

7

1

2

OUT

C7943

0.1UF

NO STUFF

1

R7930

0

5% 1/20W MF 201

2

23 25 40 51 61

10%

6.3V X5R 201

NO STUFF

No stuff C7931, 12ms Min delay time

U7930 Sense input threhold is 3.07V

S4_PGOOD_CT

Deep Sleep (S4AC)

Deep Sleep (S5AC)

Battery Off (G3HotAC)

Battery Off (G3Hot)

C7970

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

1

2

1

3

6

R7917

0

1 2

5%

1/20W

MF

201

61

Run (S0)

Sleep (S3AC)

Sleep (S3)

Deep Sleep (S4)

Deep Sleep (S5)

0.1uF

CERM

74AUP1G3208

A

B

C

7

1

2

NO STUFF

State

1

20% 10V

2

402

U7940

VCC

SMC_ADAPTER_EN

toggle 3Hz

PM_SLP_S5_L:100K pull down on PCH page

5

SOT891

4

Y

GND

2

3.3V SUS Detect

=PP3V3_S5_PWRCTL

PLACE_NEAR=U7930.6:2.3mm

CRITICAL

SENSE

TPS3808G33DBVRG4

4

CT

C7931

1000PF

10% 16V X7R 201

6

VDD

U7930

SOT23-6

GND

2

SUS_PGOOD_MR_L

Mobile System Power State Table

SMC_PM_G2_ENABLE

X 1 0

0 1 0

1

PM_SUS_EN

44

MAKE_BASE=TRUE

RESET*

(90K IPU)

17 40

IN

C7930

0.1UF

6.3V

MR*

PM_SLP_S5_L

10% X5R

201

15

3

1 1 1

1

1 0 0

=P5V_3V3_SUS_EN

1

R7933

2

PM_RSMRST_L

PM_RSMRST_L goes to U1800.C21

SMC_S4_WAKESRC_EN

1 1 1

1 01 0 0 0

6

2

1

NC

5

3

NC

PM_SLP_S3_L

17 26 40 61

IN

OUT

=PP3V3_SUS_PWRCTL

1

100K

5%

1/20W

MF

201

2

OUT

18 23 36

IN

17 40 41

IN

17 26 40 61

IN

PM_SUS_EN

1 1 1

0

0 0

U7970

74LVC1G32

SOT891

4

7 61

SSM3K15FV

60

CHGR VFRQ Generation

17

2N7002DW-X-G

AP_PWR_EN

SMC_ADAPTER_EN

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_S4_L

1 1 1

0 00 00 0 0

PM_SLP_S3_L

1 1 0 1

0 0 0 0 0

1

48

PM_SLP_S4_L

17 26

IN

36 40

0 00 01 011 0 0 0 0 0

MAKE_BASE=TRUE

PLACE_NEAR=U7300.16:6mm

R7911

2

5.1K

5%

1/20W

MF

201

1

DP S4 Power Enable

P5V3V3_S4_EN

MAKE_BASE=TRUE

NOSTUFF

R7915

1 2

0

5% 1/16W MF-LF

402

=TBTAPWRSW_EN

=P3V3S4_EN

63

OUT

60

OUT

PLACE_NEAR=U7300.16:6mm

1

C7910

0.47UF

10%

6.3V

2

CERM-X5R 402

S0 ENABLE

R7978

100

1 2

5%

1/20W

MF

201

=PP3V42_G3H_PWRCTL

R7931

10K

5% 1/20W

MF

1 2

201

CHGR_VFRQ

Q7931

SOD-VESM-HF

3

D

1

G S

7

61

WLAN Enable Generation

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

OUT

2

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

PM_WLAN_EN_L

2

SOT-363

2

G

6

D

S

(AC_EN_L)

1

AC_EN_L

6

D

S

1

NO STUFF

R7929

Q7925

SOT-363

Q7920

2N7002DW-X-G

(PM_SLP_S3_R_L)

R7987

2

33K

5%

1/20W

MF

1

201

PLACE_NEAR=U7100.15:6mm

52

PVCCSA_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7100.15:6mm

1

C7987

0.47UF

10%

6.3V

2

CERM-X5R 402

VFRQ Low: Fix Frequency VFRQ High: Variable Frequency

OUT

1

0

5%

1/20W

MF

201

2

R7981

20K

5% 1/20W MF

1

201

PLACE_NEAR=U7600.3:6mm

CPUVCCIOS0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7600.3:6mm

1

C7981

0.47UF

10%

6.3V

2

CERM-X5R 402

36

3

Q7920

D

2N7002DW-X-G

SOT-363

5

G

S

4

(PM_SLP_S3_L)

PM_SLP_S3_R_L

MAKE_BASE=TRUE

2

R7988

39K

5% 1/20W MF

1

201

PLACE_NEAR=U7770.3:6mm

P1V5S0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7770.3:6mm

1

C7988

0.47UF

10%

6.3V

2

CERM-X5R 402

Q7925

2N7002DW-X-G

SOT-363

NC

SYNC_MASTER=J13_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

12

3.3V,5V S3 ENABLE

R7913

0

1 2

2

R7912

9.1K

5% 1/20W MF 201

1

PLACE_NEAR=Q7812.2:6mm

1

C7912

0.47UF

10%

6.3V

2

CERM-X5R 402

2

1

PLACE_NEAR=U7720.5:6mm

MAKE_BASE=TRUE

PLACE_NEAR=U7720.5:6mm

1

2

NC

3

D

5

G

S

4

NC

Power Control 1/ENABLE

P5VS3_EN

MAKE_BASE=TRUE

5%

1/20W

MF

201

DDRREG_EN

MAKE_BASE=TRUE

R7986

5.1K

5%

1/20W

MF

201

P1V8S0_EN

C7986

0.47UF

10%

6.3V CERM-X5R 402

Unused fet

Apple Inc.

R

P3V3S3_EN

MAKE_BASE=TRUE

=P5VS3_EN

NO STUFF

1

C7913

0.068UF

10% 10V

2

CERM 402

=P3V3S3_EN

=DDRREG_EN =USB_PWR_EN

=P5VS0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=TBT_S0_EN

=P1V8S0_EN

=P1V5S0_EN

=1V05_S0_LDO_EN =CPUVCCIOS0_EN

=PVCCSA_EN

SYNC_DATE=11/18/2011

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

OUT

OUT OUT

OUT

051-9276

2.7.0

79 OF 109

61 OF 72

60

55

6

54

38 39

60

37 60

44

63

59

58

53

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

LCD Connector

Internal DP Connector: 518S0829

CRITICAL

J9000

20525-130E-01

F-RT-SM

R9061

0

=I2C_TCON_SDA

43

BI

=I2C_TCON_SCL

43

IN

C

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

8

IN

=PP3V3_S5_LCD

7

LCD_IG_PWR_EN

R9014

1/20W

1

C9009

1K

0.1UF

5%

10%

6.3V

MF

2

X5R

201

2

3

ON

VIN_1

VIN_2

CRITICAL

U9000

FPF1009

MFET-2X2-8IN

GND

617

VOUT_1

VOUT_2

THRM

PAD

4

5

C9011

0.1UF

DP_INT_HPD

9

OUT

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

C9024

1

C9012

10UF

20%10%

6.3V X5R 201

6.3V

2

X5R 603

9

65

9

65

9

65

9

65

DP_INT_AUX_CH_N

BI

DP_INT_AUX_CH_P

BI

DP_INT_ML_P<0>

IN

DP_INT_ML_N<0>

IN

0.1UF

1 2

10% 16V

X5R-CERM

0201

C9020

0.1UF

1 2

10% 16V

X5R-CERM

0201

B

1 2

R9062

1 2

C9025

0.1UF

1 2

10% 16V

X5R-CERM

0201

C9021

0.1UF

1 2

10% 16V

X5R-CERM

0201

1/20W

5%

MF

201

0

5%

MF

201

I2C_TCON_SDA_R

6

I2C_TCON_SCL_R

(DP_INT_AUX_CH_C_N)

(DP_INT_AUX_CH_C_P)

Pull-ups on panel side,

4.7 kOhm to 3.3V

L9004

FERR-120-OHM-1.5A

1 2

0402-LF

C9015

1000PF

10% 16V X7R 201

PLACE_NEAR=J9000.14:2mm

R9050

1

2

100K

1/20W

6

64

6

64

6

64

6

64

6

64

6

64

R9060

0

1 2

5%

1/20W

MF

201

1

R9070

100K

5% 1/20W MF 201

2

1

R9080

100K

5%

5% 1/20W

MF

201

2

PPVOUT_SW_LCDBKLT

6

64

LED_RETURN_6

OUT

LED_RETURN_5

OUT

LED_RETURN_4

OUT

LED_RETURN_3

OUT

LED_RETURN_2

OUT

LED_RETURN_1

OUT

DP_INT_HPD_CONN

6

PP3V3_SW_LCD

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

6

65

DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P

6

65

6

DP_INT_ML_F_P<0>

65

DP_INT_ML_F_N<0>

6

65

PLACE_NEAR=J9000.24:1mm

R9018

1/20W

1

1M

5%

MF

201

2

PLACE_NEAR=J9000.25:1mm

1

R9017

1M

5%

1/20W

MF

201

2

PLACE_NEAR=J9000.3:2mm

C9017

1000PF

C0G-CERM

1

5%

50V

2

603

31

1

2

NC

3

4

5

NC

6

7

8

LED Backlight I/F

9

10

11

12

NC

13

14

15

16

DisplayPort I/F

17

18

19

20

21

22

23

24

25

26

27

NC

28

NC

29

30

33

34

35

36

37

38

39

40

41

32

C

B

A

SYNC_MASTER=K21_MLB

PAGE TITLE

Internal DisplayPort Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

90 OF 109

SHEET

62 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

3.3V/HV Power MUX

V3P3 must be S4 to support wake from Thunderbolt devices.

=PP3V3_S4_TBTAPWRSW

7

CRITICAL

C9487

100UF

POLY-TANT

CASE-B2-SM

D

7

CRITICAL

1

C9480

2

C9415

4.7UF

X5R-CERM

61

33 35

61

X5R-CERM-1

10% 25V

0603

IN

22UF

20%

6.3V

=PPHV_SW_TBTAPWRSW

18.9V Max

1

20%

6.3V 2

603

1

C9410

2

=TBTAPWRSW_EN

TBT_A_HV_EN

=TBT_S0_EN

0.1UF

1

C9481

0.1UF

10% 16V

2

X5R-CERM 0201

10% 25V X5R 402

1

2

Nominal Min Max IV3P3 1100mA 1030mA 1200mA IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

TBTHV:P15V

R9410

22.6K

1/20W

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

1

2

1% MF

201

19

20

6

7

RSVD

5

EN

11 10

HV_EN

17

S0

V3P3

VHV

CRITICAL

CD3210A0RGP

123

U9410

QFN

GND

V3P3OUT

OUT

RSVD

ISET_V3P3

ISET_S0

ISET_S3

THRM

4

13

PAD

21

18

12

14

C9485

0.1UF

10% 16V

X5R-CERM

0201

1516

8

TBTAPWRSW_ISET_V3P3

TBTAPWRSW_ISET_S0

9

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_S3_R

1

2

12V: See below

1

C9486

2

10UF

20%

6.3V CERM-X5R 0402

TBTAPWRSW_ISET_S0_R

TBTHV:P15V

R9413

22.6K

1/20W

1% MF

201

TBTHV:P15V

1

R9414

22.6K

1% 1/20W MF 201

2

Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.

PP3V3_SW_TBTAPWR

PPHV_SW_TBTAPWR

C9411

0.1UF

10% 25V X5R 402

TBTHV:P15V

1

R9411

22.6K

1% 1/20W MF 201

2

7

63

1

R9412

36.5K

1% 1/20W MF 201

2

PP3V3_SW_TBTAPWR

7

63

33

33 69

OUT

BI BI

IN IN

TBT_A_LSRX

Y = B

DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

1

2

CRITICAL

C9460

0.1UF

20% 10V CERM 402

U9460

74AUP1T97

SOT891

4

Y A

C9430

C9431

C9432

C9433

5

VCC

GND

2

0.1UF

0.22UF

3

1

B

6

C

1 2

63

10% X5R-CERM

20% X5R

7

6.3V 0201

PP3V3_SW_TBTAPWR

33

IN

25

IN

16V 0201

69

8

BI

8

IN

33

OUT

69

33

IN

33

IN

33

OUT

1

C9420

0.1UF

10% 16V

2

X5R-CERM

0201

SIGNAL_MODEL=TBT_MUX TBT_A_CIO_SEL

DP_AUXIO_EN

DP_TBTPA_AUXCH_N DP_TBTPA_AUXCH_P

DP_TBTSNK0_DDC_DATA DP_TBTSNK0_DDC_CLK

TBT_A_CONFIG1_BUF

DP_TBTPA_ML_P<1> DP_TBTPA_ML_N<1>

TBT_A_LSTX TBT_A_LSRX_UNBUF

TBT_A_DP_PWRDN

DP_TBTPA_HPD

C9421

0.1UF

X5R-CERM

0201

10% 16V

R9426

1/20W

25

R9429

HPD

100K

1/20W

1

5%

MF

201

2

24

23

22

1816

19 20

1712

TBT_A_BIAS

VOLTAGE=3.3V

1

C9425

0.1UF

10% 16V

2

X5R-CERM 0201

DP_A_AUXCH_DDC_N DP_A_AUXCH_DDC_P

TBT: RX_1 Bias Sink

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_A_HPD

1

R9428

100K

5% 1/20W MF 201

2

1

R9427

10K

5% 1/20W

2

MF 201

2

1

2

7 8

4

5

11

10

14 13

6

CRITICAL

CBTL05023

BIASIN

AUXIO_EN

AUXAUX+

DDC_DAT DDC_CLK

CA_DETOUT

DP+ DP-

LSTX LSRX

DP_PD

3

VDD

U9420

HVQFN

15

BIASOUT

AUXIOAUXIO+

CA_DET

DPMLO+ DPMLO-

HPDOUT

THMPAD

1

1M

5%

MF

201

2

GND

9

21

C

12

63

D

63 69

63

63 69

63

C

ILIM = 40000 / RISET

For 12V systems:

PART NUMBER

118S0145

Nominal Min Max IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT_A_D2R_P<0>

33 69

OUT

TBT_A_D2R_N<0>

33 69

OUT

DP_TBTPA_ML_C_P<3>

33 69

IN

DP_TBTPA_ML_C_N<3>

33 69

IN

TBT_A_D2R_P<1>

OUT

TBT_A_D2R_N<1>

OUT

B

QTY

2

DESCRIPTION

RES,MF,1/20W,17.8K,1,0201

C9474

0.47UF

C9475

0.47UF

C9476

0.47UF

C9477

0.47UF

GND_VOID=TRUE

(Both C’s)

1 2

20%

CERM-X5R-1

1 2

20%

CERM-X5R-1

C9478

0.22UF

C9479

0.22UF

TBT_A_BIAS

63

GND_VOID=TRUE

(Both C’s)

1 2

20%

CERM-X5R-1

1 2

20%

CERM-X5R-1

DP_A_AUXCH_DDC_P

63 69

DP_A_AUXCH_DDC_N

63 69

1 2

201

4V

201

4V

20% X5R

GND_VOID=TRUE

201

4V

201

4V

6.3V 0201

R9498

2.2K

1/20W

201

REFERENCE DES

R9410,R9413

R9411,R9414

TBT_A_D2R_C_P<0>

69

TBT_A_D2R_C_N<0>

69

DP_TBTPA_ML_P<3> DP_TBTPA_ML_N<3>

69

TBT: Unused

1

R9499

2.2K

5%

5% 1/20W

MF

MF 201

2

GND_VOID=TRUE

TBT_A_D2R_C_P<1>

69

TBT_A_D2R_C_N<1>

C9498

30PF

5%

50V

CERM

402

SIGNAL_MODEL=EMPTY

1

2

CRITICAL

GND_VOID=TRUE

R9494

1

C9499

30PF

5% 50V

2

CERM 402

1/20W

BOM OPTION

TBTHV:P12V

GND_VOID=TRUE

1

R9495

1K

5%

5% 1/20W

MF

2

MF 201

2

SIGNAL_MODEL=EMPTY

D9498

BAR90-02LRH

D9499

BAR90-02LRH

R9478

R9479

470K

CRITICAL

SIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

(Both D’s)

A K

CRITICAL

L9498

650NH-5%-0.430MA-0.52OHM

SIGNAL_MODEL=EMPTY

CRITICAL

L9499

650NH-5%-0.430MA-0.52OHM

SIGNAL_MODEL=EMPTY

201

0603

1 2

TSLP-2-7

12

C9400

0.01UF

10% 50V X7R 402

5% MF

69

TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

69

GND_VOID=TRUE

FERR-120-OHM-3A

1

2

1/20W

201

1/20W

201

L9400

1 2

0603

1

R9401

12

5% 1/20W MF 201

2

TBT Dir

PP3V3RHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

Thunderbolt Connector A

For J9400 TBT SMT pads (3, 5, 17 & 19):

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

CRITICAL

J9400

MDP-J11

F-RT-TH

HOT_PLUG_DETECT CONFIG1 CONFIG2 GND ML_LANE3P ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR

SHIELD PINS

28

514-0818

ML_LANE0P ML_LANE0N

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

RETURN

DP Dir

C9401

0.01UF

1

10% 50V

2

X7R 402

2 4 6

10 12

16 18 20

GND

C9405

0.01UF

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

DP Dir

TBT Dir

(0-18.9V)

1 2

X5R-CERM

0201

TBT_A_R2D_P<0>

69

TBT_A_R2D_N<0>

69

10% 25V

C9470

0.22UF

C9471

0.22UF

GND_VOID=TRUE

(Both C’s)

1 2

20%

6.3V

X5R

0201

6.3V

20% X5R

0201

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

33 69

IN

33 69

IN

TBT: TX_0

C9406

0.01UF

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

1 3 5 713 9 11 814 15 17 19

VOLTAGE=18.9V

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

21222324252627

12

10% 25V

X5R-CERM

0201

TBT_A_R2D_P<1>

69

TBT_A_R2D_N<1>

69

TBT: TX_1

GND_VOID=TRUE

1

R9470

470K

5% 1/20W MF 201

2

GND_VOID=TRUE

1

R9472

470K

5% 1/20W MF 201

2

470k R’s for ESD protection on AC-coupled signals.

C9472

0.22UF

C9473

0.22UF

GND_VOID=TRUE

1

R9471

470K

5% 1/20W MF 201

2

GND_VOID=TRUE

(Both C’s)

1 2

GND_VOID=TRUE

1

R9473

470K

5% 1/20W MF 201

2

20% X5R

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

6.3V

TBT_A_R2D_C_P<1>

0201

TBT_A_R2D_C_N<1>

6.3V 0201

63 69

B

33 69

IN

33 69

IN

TBT_A_HPD

A

63

33

OUT

TBT_A_CONFIG1_RC

TBT_A_CONFIG2_RC

R9452

1/20W

SIZE

A

D

SYNC_MASTER=J13_MLB

0.01UF

X5R-CERM

0201

1

10% 25V

2

C9402

1

R9451

1M

5%

5% 1/20W

MF

201

2

C9494

330PF

1

C9495

10% 16V X7R 201

330PF

10% 16V

2

X7R 201

1

R9441

100K

5% 1/20W MF 201

2

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

PAGE TITLE

Thunderbolt Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=11/18/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

94 OF 109

SHEET

63 OF 72

124578

8 7 6 5 4 3

12

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

1 2 5 6

RDS(ON)

LOADING

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

7

=PP3V3_S0_BKL_VDDIO

CRITICAL

Q9706

FDC638APZ_SBMS001

F9700

3AMP-32V-467

D

=PPBUS_S0_LCDBKLT

7

1 2

8

IN

BOTTOM

603-HF

LCD_BKLT_EN

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

1

R9788

301K

1% 1/20W MF 201

2

LCDBKLT_EN_DIV

1

R9789

147K

1% 1/20W MF 201

2

LCDBKLT_EN_L

Q9707

SSM6N15FEAPE

SOT563

5

3

D

SG

4

LCDBKLT_DISABLE

C9782

0.1UF

Q9707

SSM6N15FEAPE

10% 16V X5R 402

SOT563

SSOT6-HF

4

1

2

3

6

D

C

2

SG

BKLT_PLT_RST_L

25

IN

1

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.65 A (EDP)

8

THERE IS A SENSE RESISTOR BETWEEN

PPBUS_SW_LCDBKLT_PWR AND PPBUS_SW_BKL

ON THE SENSOR PAGE

=PP5V_S0_BKL

7

=PPBUS_SW_BKL

8

PLACE_NEAR=L9701.1:3mm PLACE_NEAR=L9701.1:3mm

64

CRITICAL

1

C9712

10UF

10% 25V X5R 805

1

C9713

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U9701.D1:5mm

PLACE_NEAR=U9701.C4:4mm

C9711

0.1UF

6.3V

10% X5R

201

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

CRITICAL

L9701

15UH-2.8A

1 2

PIMB053T-SM

PLACE_NEAR=U9701.D1:3mm

1

C9710

1UF

603-1

10% 25V X5R

1

C9714

0.01UF

10% 10V

2

X5R 201

1

PPBUS_SW_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.150 MM VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE

PPVOUT_SW_LCDBKLT_FB

VOLTAGE=50V MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM

PLACE_NEAR=L9701.2:3mm

CRITICAL

D9701

SOD-123

A K

RB160M-60G

XW9720

SM

1 2

PLACE_NEAR=C9797.1:5mm

PLACE_NEAR=U9701.A5:3mm

1

C9796

220PF

10% 50V

2

X7R-CERM 402

CRITICAL

1

C9797

10UF

10% 50V

2

X5R 1210-1

PLACE_NEAR=D9701.2:3mm

CRITICAL

1

C9799

10UF

10% 50V

2

X5R 1210-1

PLACE_NEAR=D9701.2:5mm

PPVOUT_SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V

D

6

62

2

C

C4C1D1

VDDIO

BKL_VSYNC_R

R9741

10K

200K

1/20W

201

1 2

5%

1/20W

MF 201

1

R9715

1%

100K

MF

1% 1/20W MF 201

2

PLACE_SIDE=BOTTOM

see spec for others

1

R9755

10K

5% 1/20W MF 201

2

TP_BKL_FAULT

Fpwm=9.62kHz

R9716

90.9K

1/20W

R9753

0

=I2C_BKL_1_SCL

43

IN

43

BI

Addr: 0x58(Wr)/0x59(Rd)

PPBUS_SW_LCDBKLT_PWR

8

64

B

LCD_BKLT_PWM

8

IN

R9757

1 2

1/20W

R9704

1 2

1/20W

201

1 2

5%

1/20W

0

5%

MF

201

MF

201

1 2

R9731

33

5%

1

MF

C9704

2

33PF

5% 25V NP0-C0G 201

BKL_FLTR

BKL_ISET

BKL_FSET

BKL_SCL BKL_SDA=I2C_BKL_1_SDA

BKL_PWM

BKL_EN

I_LED=20.3mA

1

R9714

18.2K

1%

1% 1/20W MF

MF

201

2

GND_BKL_SGND

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

I_LED=369/Riset (EEPROM should set EN_I_RES=1)

D2

VSYNC

C2

FILTER

B3

ISET

B4

FSET

D3

SCLK

D4

SDA

A4

PWM

A3

EN

C3

FAULT

VLDO

U9701

25-BUMP-MICRO

LP8550

CRITICAL

GND_S

GND_L

E4B5A1

XW9710

VIN

B1

SW_0

B2

SW_1

A5

FB

E5

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6

GND_SW

A2

SM

1 2

BKL_ISEN1

D5

BKL_ISEN2

C5

BKL_ISEN3

E3

BKL_ISEN4

E2

BKL_ISEN5

E1

BKL_ISEN6

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

PLACE_NEAR=U9701.E5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.D5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.C5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.E3:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.E2:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.E1:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BOTTOM

BKLT:PROD

R9717

0

1 2

5% 1/16W MF-LF

402

BKLT:PROD

R9718

0

1 2

5% 1/16W MF-LF

402

BKLT:PROD

R9719

0

1 2

5% 1/16W MF-LF

402

BKLT:PROD

R9720

0

1 2

5% 1/16W MF-LF

402

BKLT:PROD

R9721

0

1 2

5% 1/16W MF-LF

402

BKLT:PROD

R9722

0

1 2

5% 1/16W MF-LF

402

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

6

62

OUT

6

62

OUT

B

6

62

OUT

6

62

OUT

6

62

OUT

6

62

OUT

A

PART NUMBER

103S0198

QTY

3

DESCRIPTION

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

6 3

REFERENCE DES

R9717,R9718,R9719

R9720,R9721,R9722

CRITICAL

BOM OPTION

BKLT:ENG

10.2 ohm resistors for current measurement on LED strings.

SYNC_MASTER=J13_MLB

PAGE TITLE

LCD Backlight Driver

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/13/2011

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

97 OF 109

SHEET

64 OF 72

124578

SIZE

A

D

8 7 6 5 4 3

12

CPU Signal Constraints

CPU_45S

CPU_27P4S

SPACING_RULE_SET

CPU_AGTL

D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_8MIL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_ITP

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_COMP CPU_COMP

CPU_COMP

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_VCCSENSE

C

LAYER

ALLOW ROUTE ON LAYER?

*

=27P4_OHM_SE

LAYER

TOP,BOTTOM

LINE-TO-LINE SPACING

=2x_DIELECTRIC

* ?

* *

CPU_VCCSENSE

=STANDARD

AREA_TYPE

**

AREA_TYPE

*

**

AREA_TYPE

*

**

MINIMUM LINE WIDTH

=45_OHM_SE

WEIGHT

?

SPACING_RULE_SET

CPU_8MIL_2ANY

SPACING_RULE_SET

CPU_ITP_2ANY

SPACING_RULE_SET

CPU_COMP_2SELF

CPU_COMP_2OTHER

SPACING_RULE_SET

CPU_VCCSENSE_2SELF

CPU_VCCSENSE_2OTHER

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

CPU_8MIL_2ANY

SPACING_RULE_SET

CPU_ITP_2ANY

SPACING_RULE_SET

CPU_COMP_2SELF

CPU_COMP_2OTHER

SPACING_RULE_SET

CPU_COMP_2SELF

CPU_COMP_2OTHER

SPACING_RULE_SET

CPU_VCCSENSE_2SELF

CPU_VCCSENSE_2OTHER

SPACING_RULE_SET

CPU_VCCSENSE_2SELF

CPU_VCCSENSE_2OTHER

PCI-Express Interface Constraints

LAYER

CLK_PCIE_80D

ALLOW ROUTE ON LAYER?

*

=80_OHM_DIFF

*

=80_OHM_DIFF

PCIE Clock Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_PCIECLK_PCIE

CLK_PCIE

*

CPU PCIE Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE_CPU_TX

PCIE_CPU_RX

B

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

*_CPU_TX

*_CPU_RX

*_CPU_TX

*_TX

*_RX

* *

*

PCH PCIE Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE_PCH_TX PCIE_PCH_TX

PCIE_PCH_RXPCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_TX

A

PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

*_PCH_TX

*_PCH_RX

*_PCH_TX

*_TX

*_RX

*

MINIMUM LINE WIDTH

=80_OHM_DIFF =80_OHM_DIFF

AREA_TYPE

*

SPACING_RULE_SET

CLK_PCIE_2SELF

CLK_PCIE_2OTHER

SPACING_RULE_SET

PCIE_TX2TX

PCIE_RX2RX

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX

PCIE_RX2TX

PCIE_2OTHERHS

PCIE_2OTHER

*

PCIE_2OTHER

AREA_TYPE

*

**

SPACING_RULE_SET

PCIE_TX2TX

PCIE_RX2RX

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX

PCIE_RX2TX

PCIE_2OTHERHS

PCIE_2OTHER

MINIMUM NECK WIDTH

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

CLK_PCIE_2SELF

CLK_PCIE_2OTHER

SPACING_RULE_SET

PCIE_TX2TX

PCIE_RX2RX TOP,BOTTOM?=5x_DIELECTRIC

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX TOP,BOTTOM

PCIE_RX2TX?TOP,BOTTOM

PCIE_2OTHERHS

PCIE_2OTHER

SPACING_RULE_SET

PCIE_TX2TX

PCIE_RX2RX

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX

PCIE_RX2TX

PCIE_2OTHERHS

PCIE_2OTHER

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=45_OHM_SE=45_OHM_SE =45_OHM_SE

=27P4_OHM_SE 0.100 MM=27P4_OHM_SE=27P4_OHM_SE

LAYER

LINE-TO-LINE SPACING

=4x_DIELECTRIC

LAYER

TOP,BOTTOM

LAYER

LINE-TO-LINE SPACING

=6x_DIELECTRIC

=10x_DIELECTRIC

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

LAYER

TOP,BOTTOM

LAYER

LINE-TO-LINE SPACING

=6x_DIELECTRIC

=10x_DIELECTRIC

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

MAXIMUM NECK LENGTH

=80_OHM_DIFF

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF =80_OHM_DIFFPCIE_80D

=80_OHM_DIFF

LAYER

LINE-TO-LINE SPACING

TOP,BOTTOM?=6x_DIELECTRICCLK_PCIE_2SELF

TOP,BOTTOM

LAYER

=10x_DIELECTRICCLK_PCIE_2OTHER

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

LAYER

TOP,BOTTOM

LINE-TO-LINE SPACING

=5x_DIELECTRIC

=7x_DIELECTRIC

TOP,BOTTOM

=6x_DIELECTRIC

TOP,BOTTOM?=5x_DIELECTRIC

LAYER

LINE-TO-LINE SPACING

*

=2.5x_DIELECTRIC

* ?

=2.5x_DIELECTRIC

=4x_DIELECTRIC

=6x_DIELECTRIC

* ?

=6x_DIELECTRIC

*

=4x_DIELECTRIC

* ?

=3x_DIELECTRIC

*

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

DMI_S2N DMI_S2N DMI_N2S DMI_N2S FDI_DATA FDI_DATA PCIE_80D

PM_SYNC PM_MEM_PWRGD

CPU_SM_RCOMP CPU_SM_RCOMP

CPU_CATERR_L

CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L DMI_CLK100M DMI_CLK100M DPLL_REF_CLK120M DPLL_REF_CLK120M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M XDP_TDI

XDP_TCK CPU_45S CPU_ITP XDP_TRST_L XDP_BPM_L XDP_BPM_L_R_CFG (XDP_BPM_L_R_CFG) (XDP_BPM_L_R_CFG) (FSB_CPURST_L)

CPU_VCCSENSE CPU_VCCSENSE CPU_VCCIOSENSE CPU_VCCIOSENSE CPU_AXG_SENSE CPU_AXG_SENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE

CPU_VALSENSE

CPU_SVIDALERT_L CPU_SVIDSCLK

PCIE_CPU_MUX_R2D PCIE_CPU_MUX_R2D

PCIE_CPU_MUX_D2R PCIE_CPU_MUX_D2R

PCIE_CPU_SSD_R2D PCIE_CPU_SSD_R2D

PCIE_CPU_SSD_D2R PCIE_CPU_SSD_D2R

PCIE_CLK100M_SSD PCIE_CLK100M_SSD

DP_INT_ML DP_INT_ML

DP_INT_AUXCH DP_INT_AUXCH

PHYSICAL

PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D

CPU_45S CPU_45S CPU_45S

CPU_45S CPU_45S CPU_ITP CPU_45S

CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S

CLK_PCIE_80D CLK_PCIE CLK_PCIE_80D CLK_PCIE CLK_PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE CPU_45S CPU_ITP CPU_45S CPU_ITPXDP_TDO CPU_45S CPU_ITPXDP_TMS

CPU_45S CPU_ITP CPU_45S CPU_45S CPU_45S CPU_45S CPU_ITP

SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_P2MM CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S

CPU_45S CPU_45S CPU_45S

PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D

CLK_PCIE_80D CLK_PCIE CLK_PCIE_80D CLK_PCIE

DP_80D DP_80D DP_80D DP_80D

DP_80D DP_80D

DP_80D

NET_TYPE

SPACING

PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX CPU_AGTL CPU_AGTL CPU_AGTL

CPU_COMPCPU_PECI CPU_AGTL CPU_AGTL

CPU_ITP

CPU_COMP CPU_COMP CPU_COMPCPU_SM_RCOMP CPU_COMP CPU_COMP CPU_ITP CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CLK_PCIECLK_PCIE_80D CLK_PCIECLK_PCIE_80D

CLK_PCIE CLK_PCIE CLK_PCIECLK_PCIE_80D CLK_PCIE CLK_PCIE

CPU_ITP CPU_ITP CPU_ITP

CPU_ITPCPU_45S

CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSECPU_VALSENSE CPU_VCCSENSE

CPU_COMP CPU_COMP CPU_COMPCPU_SVIDSOUT

PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX

PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_TX PCIE_CPU_TX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX PCIE_CPU_RX

DP_TX DP_TX DP_TX DP_TX

DP_AUX DP_AUX DP_AUXDP_80D DP_AUX

=STANDARD

8 MIL

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

?*

WEIGHT

?*

WEIGHT

?

WEIGHT

?*

WEIGHT

?

WEIGHT

?*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

?

WEIGHT

?*

WEIGHT

?

WEIGHT

?

?*

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

0.100 MM

Note: CPU_8MIL and CPU_ITP can be converted

back to TABLE_SPACING_RULE once rdar://10308147 is resolved

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Note: DisplayPort tables are on Page 103

6 3

DMI_S2N_P<3:0> DMI_S2N_N<3:0> DMI_N2S_P<3:0> DMI_N2S_N<3:0> FDI_DATA_P<7:0> FDI_DATA_N<7:0> FDI_FSYNC<1..0> FDI_LSYNC<1..0> FDI_INT

CPU_PECI PM_SYNC PM_MEM_PWRGD

XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L

EDP_COMP CPU_PEG_COMP CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2> CPU_CFG<11..0> CPU_CATERR_L CPU_VCCIO_SEL CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N DPLL_REF_CLKP DPLL_REF_CLKN ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L<3..0> XDP_BPM_L<7..4> XDP_OBSDATA_B<3..0> CPU_CFG<15..12> XDP_CPURST_L

CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N

CPU_VIDALERT_L CPU_VIDSCLK CPU_VIDSOUT

PCIE_SSD_R2D_C_P<0> PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_MUX_IN_P PCIE_SSD_R2D_MUX_IN_N PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_MUX_OUT_P PCIE_SSD_D2R_MUX_OUT_N

PCIE_SSD_R2D_C_P<1> PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_P<1> PCIE_SSD_R2D_N<1> PCIE_SSD_D2R_P<1> PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_C_P<1> PCIE_SSD_D2R_C_N<1>

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

DP_INT_ML_P<3..0> DP_INT_ML_N<3..0> DP_INT_ML_F_P<3..0> DP_INT_ML_F_N<3..0>

DP_INT_AUX_CH_C_P DP_INT_AUX_CH_C_N DP_INT_AUX_CH_P DP_INT_AUX_CH_N

9

17

9

17

9

17

9

17

9

17

9

17

9

17

9

17

9

17

10 19 41

10 17

10 17 26

10 23 25

10 23

9

10

9

23

10 40

12

10 40 41 56

10 19 23

10 19 41

10 16

8

10

8

10

10 16

16 23

23

10 23

23

9

23

12 56

12 58

12 56

12

9

12 56

8

37

8

37

8

37

8

37

8

37

8

37

6

37

6

37

6 8

37

6 8

37

6

16 37

6

16 37

9

62

9

62

6

62

6

62

6

62

6

62

9

62

9

62

DMI/FDI

PCIe SSD

DP

SYNC_MASTER=CONSTRAINTS

PAGE TITLE

CPU Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

100 OF 109

SHEET

65 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Memory Bus Constraints

MEM_45S

MEM_72D

MEM_80D

LAYER

ALLOW ROUTE ON LAYER?

*

=72_OHM_DIFF

*

=80_OHM_DIFF

*

MINIMUM LINE WIDTH

=45_OHM_SE=45_OHM_SE

=72_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

Spacing Rule Sets

LINE-TO-LINE SPACING

LAYER

*

=2x_DIELECTRIC

*

=3x_DIELECTRIC

* ?

=3x_DIELECTRIC

* ?

=3x_DIELECTRIC

* ?

=6x_DIELECTRIC

* ?

=4x_DIELECTRIC

* ?

=PWR_P2MM

=GND_P2MM

=6x_DIELECTRIC

D

SPACING_RULE_SET

MEM_DATA2SELF

MEM_DQS2OWNDATA

MEM_CMD2CMD

MEM_CMD2CTRL

MEM_CTRL2CTRL

MEM_CLK2CLK

MEM_2OTHERMEM

MEM_2PWR

MEM_2GND

MEM_2OTHER

Memory to Power Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_PWR

MEM_*

* *

AREA_TYPE

SPACING_RULE_SET

*

Memory to GND Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

AREA_TYPE

MEM_*

SPACING_RULE_SET

*GND

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_A_DQS_0

MEM_A_DQS_1

MEM_A_DQS_2

MEM_A_DQS_3

MEM_A_DQS_4

MEM_A_DQS_5

MEM_A_DQS_6

MEM_A_DQS_7

MEM_B_DQS_0

MEM_B_DQS_1

MEM_B_DQS_2

MEM_B_DQS_3

MEM_B_DQS_4

MEM_B_DQS_5

B

MEM_B_DQS_6

MEM_B_DQS_7

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DATA_*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_* MEM_*

AREA_TYPE

MEM_A_DATA_0

MEM_A_DATA_1

MEM_A_DATA_2

MEM_A_DATA_3

MEM_A_DATA_4

MEM_A_DATA_5

MEM_A_DATA_6

MEM_A_DATA_7

MEM_B_DATA_0

MEM_B_DATA_1

MEM_B_DATA_2

MEM_B_DATA_3

MEM_B_DATA_4

MEM_B_DATA_5

MEM_B_DATA_6

MEM_B_DATA_7

AREA_TYPE

=SAME

AREA_TYPE

MEM_CMDMEM_CMD

MEM_CTRL

MEM_CTRLMEM_CTRL

AREA_TYPE

MEM_CLKMEM_CLK

AREA_TYPE

*

SPACING_RULE_SET

MEM_DQS2OWNDATA

SPACING_RULE_SET

MEM_DATA2SELF

SPACING_RULE_SET

MEM_CMD2CMD

MEM_CMD2CTRL

MEM_CTRL2CTRL

SPACING_RULE_SET

MEM_CLK2CLK

SPACING_RULE_SET

MEM_2OTHERMEM

A

WEIGHT

?

?*

MEM_2PWR

DEFAULT

MEM_2GND

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=80_OHM_DIFF

PalPilot Spacing

=2x_DIELECTRIC

=5.7x_DIELECTRIC

=4x_DIELECTRIC

=8.6x_DIELECTRIC

=5.7x_DIELECTRIC

=PWR_P2MM

=GND_P2MM

=8.6x_DIELECTRIC

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_A_DQS_0

MEM_A_DQS_1

MEM_A_DQS_2

MEM_A_DQS_3

MEM_A_DQS_4

MEM_A_DQS_5

MEM_A_DQS_6

MEM_A_DQS_7

MEM_B_DQS_0

MEM_B_DQS_1

MEM_B_DQS_2

MEM_B_DQS_3

MEM_B_DQS_4

MEM_B_DQS_5

MEM_B_DQS_6

MEM_B_DQS_7

MEM_A_DATA_0

MEM_A_DATA_1

MEM_A_DATA_2

MEM_A_DATA_3

MEM_A_DATA_4

MEM_A_DATA_5

MEM_A_DATA_6

MEM_A_DATA_7

MEM_B_DATA_0

MEM_B_DATA_1

MEM_B_DATA_2

MEM_B_DATA_3

MEM_B_DATA_4

MEM_B_DATA_5

MEM_B_DATA_6

MEM_B_DATA_7

MEM_CMD

MEM_CTRL

MEM_CLK

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF

"Real" Spacing

=2x_DIELECTRIC

=3x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

=PWR_P2MM

=GND_P2MM

=6x_DIELECTRIC

AREA_TYPE

*

* *

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK MEM_A_CLK MEM_A_CTRL MEM_A_CTRL MEM_A_CTRL MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_DQ_BYTE0 MEM_45S MEM_A_DQ_BYTE1 MEM_45S MEM_A_DQ_BYTE2 MEM_45S MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_45S MEM_A_DQ_BYTE5 MEM_45S MEM_A_DQ_BYTE6 MEM_45S MEM_A_DQ_BYTE7 MEM_45S MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7

MEM_B_CLK MEM_B_CLK MEM_B_CTRL MEM_B_CTRL MEM_B_CTRL MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_DQ_BYTE0 MEM_45S MEM_B_DQ_BYTE1 MEM_45S MEM_B_DQ_BYTE2 MEM_45S MEM_B_DQ_BYTE3 MEM_45S MEM_B_DQ_BYTE4 MEM_45S MEM_B_DQ_BYTE5 MEM_45S MEM_B_DQ_BYTE6 MEM_45S MEM_B_DQ_BYTE7 MEM_45S MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7

PHYSICAL

MEM_45S MEM_45S MEM_45S

MEM_45S MEM_CMD

MEM_45S

MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D

MEM_45S MEM_45S MEM_45S

MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D

NET_TYPE

SPACING

MEM_CLKMEM_72D MEM_CLKMEM_72D MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMDMEM_45S MEM_CMDMEM_45S MEM_CMDMEM_45S MEM_CMDMEM_45S

MEM_A_DATA_0 MEM_A_DATA_1 MEM_A_DATA_2 MEM_A_DATA_3 MEM_A_DATA_4 MEM_A_DATA_5 MEM_A_DATA_6 MEM_A_DATA_7 MEM_A_DQS_0 MEM_A_DQS_0 MEM_A_DQS_1 MEM_A_DQS_1 MEM_A_DQS_2 MEM_A_DQS_2 MEM_A_DQS_3 MEM_A_DQS_3 MEM_A_DQS_4 MEM_A_DQS_4 MEM_A_DQS_5 MEM_A_DQS_5 MEM_A_DQS_6 MEM_A_DQS_6 MEM_A_DQS_7 MEM_A_DQS_7

MEM_CLKMEM_72D MEM_CLKMEM_72D MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMDMEM_45S MEM_CMDMEM_45S MEM_CMDMEM_45S MEM_CMDMEM_45S MEM_CMDMEM_45S MEM_B_DATA_0 MEM_B_DATA_1 MEM_B_DATA_2 MEM_B_DATA_3 MEM_B_DATA_4 MEM_B_DATA_5 MEM_B_DATA_6 MEM_B_DATA_7 MEM_B_DQS_0 MEM_B_DQS_0 MEM_B_DQS_1 MEM_B_DQS_1 MEM_B_DQS_2 MEM_B_DQS_2 MEM_B_DQS_3 MEM_B_DQS_3 MEM_B_DQS_4 MEM_B_DQS_4 MEM_B_DQS_5 MEM_B_DQS_5 MEM_B_DQS_6 MEM_B_DQS_6 MEM_B_DQS_7 MEM_B_DQS_7

MEM_PWR MEM_PWR MEM_PWR MEM_PWR

MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0> MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0> MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0> MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0> MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

PP1V5_S3RS0 PP1V5_S3 PP0V75_S3_MEM_VREFCA_A PP0V75_S3_MEM_VREFDQ_A

*

**

*

**

*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF =72_OHM_DIFF

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

6 3

8

11 27 28 32

8

11 27 28 32

11 27

11 28

11 27

11 28

8

11 29 30 32

8

11 29 30 32

11 29

11 30

11 29

11 30

6 7

27 28 31

SYNC_MASTER=CONSTRAINTS

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

101 OF 109

SHEET

66 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

SATA Interface Constraints

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF

*

LINE-TO-LINE SPACING

* ?

=4x_DIELECTRIC

*_PCH_TX

*_PCH_RX

*_PCH_TX

SATA_80D =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

SPACING_RULE_SET

SATA_ICOMP

NET_SPACING_TYPE1 NET_SPACING_TYPE2

D

SATA3_PCH_TX

SATA3_PCH_RX

SATA3_PCH_TX

SATA3_PCH_RX

LAYER

SATA3_PCH_TXSATA3_PCH_TX

SATA3_PCH_RXSATA3_PCH_RX

SATA3_PCH_TX *_TX

SATA3_PCH_RX *_TX

SATA3_PCH_TX *_RX

SATA3_PCH_RX

*_RX

SATA3_PCH_TX SATA3_2OTHER

SATA3_PCH_RX

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

C

MINIMUM LINE WIDTH

=80_OHM_DIFF =80_OHM_DIFF

WEIGHT

AREA_TYPE

*

SATA3_TX2OTHERTX

*

SATA3_RX2OTHERRX

*

SPACING_RULE_SET

SATA3_TX2TX

SATA3_RX2RX

SATA3_TX2RX

SATA3_RX2TX

SATA3_2OTHERHS

**

SATA3_2OTHER

**

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

SATA3_TX2TX

SATA3_RX2RX

SATA3_TX2OTHERTX

SATA3_RX2OTHERRX

SATA3_TX2RX

SATA3_RX2TX

SATA3_2OTHERHS =6x_DIELECTRIC

SATA3_2OTHER

SPACING_RULE_SET

SATA3_TX2TX

SATA3_RX2RX

SATA3_TX2OTHERTX

SATA3_RX2OTHERRX

SATA3_TX2RX

SATA3_RX2TX

SATA3_2OTHER

UART Interface Constraints

UART_45S

SPACING_RULE_SET

UART

LAYER

*

ALLOW ROUTE ON LAYER?

LINE-TO-LINE SPACING

=2x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

?*

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

USB 2.0 Interface Constraints

PCH_USB_RBIAS

USB_80D

SPACING_RULE_SET

USB *

LAYER

*

ALLOW ROUTE ON LAYER?

=STANDARD

=80_OHM_DIFF

LINE-TO-LINE SPACING

=2x_DIELECTRIC

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 3.0 Interface Constraints

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_RX

A

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB3_PCH_TXUSB3_PCH_TX

USB3_PCH_RXUSB3_PCH_RX

*_PCH_TX

*_PCH_RX

*_PCH_TX

*_TX

*_RX

AREA_TYPE

*

**

MINIMUM LINE WIDTH

8 MIL

WEIGHT

?

SPACING_RULE_SET

USB3_TX2TX

USB3_RX2RX

USB3_TX2OTHERTX

USB3_RX2OTHERRX

USB3_TX2RX

USB3_RX2TX

USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_TX

USB3_2OTHERUSB3_PCH_RX

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

8 MIL

SPACING_RULE_SET

USB3_TX2TX

USB3_RX2RX?TOP,BOTTOM

USB3_TX2OTHERTX

USB3_RX2OTHERRX

USB3_TX2RX TOP,BOTTOM?=7x_DIELECTRIC

USB3_RX2TX?TOP,BOTTOM

USB3_2OTHERHS

USB3_2OTHER

SPACING_RULE_SET

USB3_TX2TX

USB3_RX2RX

USB3_TX2OTHERTX

USB3_RX2OTHERRX

USB3_TX2RX

USB3_RX2TX

USB3_2OTHERHS

USB3_2OTHER

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=5x_DIELECTRIC

TOP,BOTTOM?=5x_DIELECTRIC

TOP,BOTTOM

=5x_DIELECTRIC

TOP,BOTTOM?=7x_DIELECTRIC

TOP,BOTTOM

=7x_DIELECTRIC

TOP,BOTTOM

TOP,BOTTOM?=5x_DIELECTRIC

LAYER

LINE-TO-LINE SPACING

=2.5x_DIELECTRIC

=4x_DIELECTRIC

* ?

=4x_DIELECTRIC

=6x_DIELECTRIC

* ?

=6x_DIELECTRIC

=4x_DIELECTRICSATA3_2OTHERHS

* ?

*

=3x_DIELECTRIC

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

LAYER

LINE-TO-LINE SPACING

=4x_DIELECTRIC

LINE-TO-LINE SPACING

=5x_DIELECTRIC

LAYER

TOP,BOTTOM

=5x_DIELECTRIC

TOP,BOTTOM

=5x_DIELECTRIC

=7x_DIELECTRIC

TOP,BOTTOM

LAYER

=6x_DIELECTRIC

=5x_DIELECTRIC

LINE-TO-LINE SPACING

* ?

=2.5x_DIELECTRIC

*

=2.5x_DIELECTRIC

*

=4x_DIELECTRIC

*

=4x_DIELECTRIC

*

=6x_DIELECTRIC

*

=6x_DIELECTRIC

* ?

=4x_DIELECTRIC

*

=3x_DIELECTRIC

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

SATA_PCH_MUX_R2D SATA_PCH_MUX_R2D

SATA_MUX_SSD_R2D SATA_MUX_SSD_R2D SATA_PCH_MUX_D2R SATA_PCH_MUX_D2R

SATA_MUX_SSD_D2R SATA_MUX_SSD_D2R PCH_SATA_ICOMP

USB_HUB1_UP USB_HUB1_UP USB_BT USB_BT

USB_TPAD USB_TPAD

USB_TPAD_HUB USB_TPAD_HUB

USB_TPAD_M USB_TPAD_M USB_SDCARD USB_SDCARD USB_SMC USB_SMC

USB_CAMERA USB_CAMERA

USB_EXTA USB_EXTA

USB3_EXTA_RX USB3_EXTA_RX USB3_EXTA_TX USB3_EXTA_TX

USB_EXTB USB_EXTB

USB3_EXTB_RX USB3_EXTB_RX

USB3_EXTB_TX USB3_EXTB_TX

(USB_TPAD_HUB) (USB_TPAD_HUB)

PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_

NET_TYPE

PHYSICAL

SATA_80D

SATA_80D SATA3_PCH_TX SATA_80D SATA_80D SATA3_PCH_RX SATA_80D SATA_80D SATA_80D SATA_80D SATA3_PCH_RX SATA_80D

USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D

USB_80D USB_80D

UART_45S UART USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D

USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D USB_80D

USB_80D USB_80D

PCH_USB_RBIASPCH_USB_RBIAS CLK_PCIE_80D CLK_PCIE CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE_80D CLK_PCIE CLK_PCIE_80D

CPU_45S

SPACING

SATA3_PCH_TX SATA3_PCH_TXSATA_80D SATA3_PCH_TXSATA_80D SATA3_PCH_TXSATA_80D

SATA3_PCH_TX

SATA3_PCH_RX SATA3_PCH_RX SATA3_PCH_RX

SATA3_PCH_RX SATA_ICOMP

USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB

USB USB

USB USB UARTUART_45S

USB USB USB USB USB3_PCH_RX USB3_PCH_RX USB3_PCH_TX USB3_PCH_TX USB3_PCH_RX USB3_PCH_RX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX

USB USB USB USB USB USB USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_RX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX USB3_PCH_TX

USB USB

CLK_PCIE CLK_PCIE

CLK_PCIE CLK_PCIECLK_PCIE_80D CLK_PCIE

=STANDARD

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

?

WEIGHT

?*

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?USB

WEIGHT

?

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=45_OHM_SE=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_ITEM

6 3

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_SSD_R2D_MUX_IN_P SATA_SSD_R2D_MUX_IN_N SATA_SSD_R2D_P SATA_SSD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_SSD_D2R_MUX_OUT_P SATA_SSD_D2R_MUX_OUT_N SATA_SSD_D2R_P SATA_SSD_D2R_N PCH_SATAICOMP

USB_HUB_UP_P USB_HUB_UP_N USB_BT_P USB_BT_N USB_BT_CONN_P USB_BT_CONN_N USB_BT_WAKE_P USB_BT_WAKE_N USB_TPAD_P USB_TPAD_N USB_TPAD_CONN_P USB_TPAD_CONN_N USB_TPAD_HUB_P USB_TPAD_HUB_N USB_TPAD_R_P USB_TPAD_R_N USB_TPAD_M_P USB_TPAD_M_N USB_SDCARD_P USB_SDCARD_N USB_SMC_P USB_SMC_N

USB_CAMERA_P USB_CAMERA_N

USB_EXTA_P USB_EXTA_N SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_EXTA_MUXED_F_P USB2_EXTA_MUXED_F_N USB3_EXTA_RX_P USB3_EXTA_RX_N USB3_EXTA_TX_P USB3_EXTA_TX_N USB3_EXTA_RX_F_P USB3_EXTA_RX_F_N USB3_EXTA_TX_F_P USB3_EXTA_TX_F_N USB3_EXTA_TX_C_P USB3_EXTA_TX_C_N

USB_EXTB_P USB_EXTB_N USB_EXTB_EHCI_P USB_EXTB_EHCI_N USB_EXTB_XHCI_P USB_EXTB_XHCI_N USB3_EXTB_RX_P USB3_EXTB_RX_N USB3_EXTB_RX_RC_P USB3_EXTB_RX_RC_N USB3_EXTB_RX_CONN_P USB3_EXTB_RX_CONN_N USB3_EXTB_TX_P USB3_EXTB_TX_N USB3_EXTB_TX_C_P USB3_EXTB_TX_C_N

USB_EXTD_XHCI_P USB_EXTD_XHCI_N

PCH_USB_RBIAS PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK

16 37

37

6

37

6

37

16 37

37

6

37

6

37

16

18 24

24 36

6

36

6

36

6

48

6

48

24

24 48

48

8

24

8

24

24 40

6

18 39

6

18 39

18 38

38 40 41

38

18 38

38

6

24 39

6

24 39

18 24

18 39

6

39

6

39

18 39

6

39

6

39

18 24

18

16

SATA SSD

USB Hub nets

USB Camera nets

USB EXTA nets (Right USB port)

USB EXTB nets (Left USB port)

Unused USB nets

SYNC_MASTER=CONSTRAINTS

PAGE TITLE

PCH Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

102 OF 109

SHEET

67 OF 72

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

LPC Bus Constraints

LAYER

LPC_45S

CLK_LPC_45S

SPACING_RULE_SET

LAYER

LPC

CLK_LPC

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

D

SMBus Interface Constraints

LAYER

SMB_45S_R_50S

SPACING_RULE_SET

LAYER

HD Audio Interface Constraints

LAYER

HDA_45S

SPACING_RULE_SET

LAYER

HDA ?

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SIO Signal Constraints

LAYER

CLK_SLOW_45S

C

SPACING_RULE_SET

CLK_SLOW

SPI Interface Constraints

SPI_45S

SPACING_RULE_SET

XDP Constraints

PCH_45S

SPACING_RULE_SET

PCH_ITP

DisplayPort

B

DP_80D

SPACING_RULE_SET

DP_2DP

DP_2OTHERHS

DP_2OTHER

DP_AUX

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DP_TX

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

*

=45_OHM_SE =45_OHM_SE

*

LINE-TO-LINE SPACING

=3x_DIELECTRIC

=4x_DIELECTRIC

ALLOW ROUTE ON LAYER?

WEIGHT

?*

?

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SETOP,BOTTOM

=45_OHM_SE

*

LINE-TO-LINE SPACING

*SMB

*

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=45_OHM_SE =45_OHM_SE =45_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=45_OHM_SE =45_OHM_SE =45_OHM_SE

LINE-TO-LINE SPACING

=4x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=45_OHM_SE =45_OHM_SE=45_OHM_SE

*

LINE-TO-LINE SPACING

=4x_DIELECTRIC

ALLOW ROUTE ON LAYER?

*

LINE-TO-LINE SPACING

*

=2:1_SPACING

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

*

* ?

DP_TXDP_TX

*_TX

*_RX

*

=4x_DIELECTRIC

=3x_DIELECTRIC

AREA_TYPE

*

WEIGHT

?

MINIMUM LINE WIDTH

WEIGHT

MINIMUM LINE WIDTH

WEIGHT

?*

MINIMUM LINE WIDTH

=45_OHM_SE

WEIGHT

?SPI *

MINIMUM LINE WIDTH

=45_OHM_SE

WEIGHT

?

MINIMUM LINE WIDTH

=80_OHM_DIFF =80_OHM_DIFF

WEIGHT

?*

? ?

SPACING_RULE_SET

DP_2DP

DP_2OTHERHS

DP_2OTHER

MINIMUM NECK WIDTH

=45_OHM_SE=45_OHM_SE=45_OHM_SE =45_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=45_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=80_OHM_DIFF =80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

DP_2DP

DP_2OTHERHS

DP_2OTHER

DP_AUX

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

WEIGHT

?

? ?

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

=STANDARD=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD LPC_FRAME_L

LPC_CLK33M

SMBUS_PCH_CLK SMBUS_PCH_DATA SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0 HDA_SDOUT

PM_SUS_CLK

SPI_CLK

SPI_MOSI

SPI_MISO SPI_CS0

PCIE_AP_R2D PCIE_AP_R2D

PCIE_AP_D2R

PCIE_CLK100M_AP PCIE_CLK100M_AP

PCIE_TBT_R2D PCIE_TBT_R2D

PCIE_TBT_D2R PCIE_TBT_D2R PCIE_80D

PCIE_CLK100M_TBT PCIE_CLK100M_TBT

XDP_TDI PCH_ITP XDP_TDO

XDP_TCK

PHYSICAL

LPC_45S LPC_45S LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S

SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S

HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S

CLK_SLOW_45S CLK_SLOW SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S

PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D CLK_PCIE_80D CLK_PCIE CLK_PCIE_80D CLK_PCIE

PCIE_80D PCIE_80D PCIE_80D PCIE_80D PCIE_80D

PCIE_80D PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D CLK_PCIE CLK_PCIE_80D CLK_PCIE

PCH_45S

PCH_45S PCH_ITPXDP_TMS

NET_TYPE

SPACING

LPC LPC LPC CLK_LPC CLK_LPC CLK_LPC CLK_LPC CLK_LPC CLK_LPC

SMB SMB SMB SMB SMB SMB

HDA HDA HDA HDA HDA HDA HDA HDA HDA

CLK_SLOWCLK_SLOW_45S

SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI

PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_RX PCIE_PCH_RXPCIE_AP_D2R

PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_TX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX PCIE_PCH_RX CLK_PCIE CLK_PCIECLK_PCIE_80D

PCH_ITPPCH_45S

LPC_AD<3..0> LPC_FRAME_L LPCPLUS_RESET_L LPC_CLK33M_SMC LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS LPC_CLK33M_LPCPLUS_R PCH_CLK33M_PCIIN PCH_CLK33M_PCIOUT

SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDOUT HDA_SDOUT_R

PM_CLK32K_SUSCLK_R SMC_CLK32K SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_SMC_CLK SPI_SMC_MOSI SPI_SMC_MISO SPI_SMC_CS_L SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L

PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N

PCIE_TBT_R2D_P<3..0> PCIE_TBT_R2D_N<3..0> PCIE_TBT_R2D_C_P<3..0> PCIE_TBT_R2D_C_N<3..0> PCIE_TBT_D2R_P<3..0> PCIE_TBT_D2R_N<3..0> PCIE_TBT_D2R_C_P<3..0> PCIE_TBT_D2R_C_N<3..0> PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

PEG_CLK100M_P PEG_CLK100M_N

XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_TCK

6

16 40 42

6

16 40 42

6

25 42

25 40

18 25

6

25 42

18 25

16 25

18 25

16 43

6

16 39

16

6

16 39

16

6

16 39

6

16 39

6

16 39

16 25

17 41

40 41

16 42

42

16 42

42

16 42

42

40 41

41 42 49

6

36

6

36

16 36

6

16 36

6

16 36

6

16 36

6

16 36

33

8

33

8

33

8

33

8

33

16 33

8

16

8

16

16 23

Chipset Net Properties

ELECTRICAL_CONSTRAINT_SET

DP_TBT_ML DP_TBT_ML

DP_TBT_AUXCH DP_TBT_AUXCH

DP_TBT_ML DP_TBT_ML

DP_TBT_AUXCH DP_TBT_AUXCH

PHYSICAL

DP_80D DP_80D DP_80D DP_80D

DP_80D

DP_80D DP_80D DP_80D DP_80D DP_80D DP_AUX DP_80D DP_AUX DP_80D DP_AUX DP_80D DP_AUX

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_XTAL

PHYSICAL

CLK_SLOW_45S

CLK_25M_45S CLK_25M_45S

CLK_25M_45S CLK_25M_45S CLK_25M_45S

NET_TYPE

SPACING

DP_TX DP_TX DP_TX DP_TX DP_AUXDP_80D DP_AUX DP_AUXDP_80D DP_AUX

DP_TX DP_TX DP_TX DP_TX

SPACING

CLK_SLOW

CLK_25M CLK_25M

CLK_25M CLK_25M CLK_25M

12

DP_TBTSNK0_ML_P<3..0> DP_TBTSNK0_ML_N<3..0> DP_TBTSNK0_ML_C_P<3..0> DP_TBTSNK0_ML_C_N<3..0> DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_P<3..0> DP_TBTSNK1_ML_N<3..0> DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT_R

SYSCLK_CLK25M_X1 SYSCLK_CLK25M_X2 SYSCLK_CLK25M_X2_R

16 25

16

25 33

33

25

33

8

33

8

33

8

33

8

33

D

33

8

33

8

33

8

33

8

33

C

B

A

System Clock Signal Constraints

LAYER

CLK_SLOW_45S

CLK_25M_45S

SPACING_RULE_SET

CLK_SLOW

CLK_25M

LAYER

ALLOW ROUTE ON LAYER?

=45_OHM_SE

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

=5x_DIELECTRIC

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=45_OHM_SE =45_OHM_SE =45_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

?

DIFFPAIR PRIMARY GAP

6 3

SIZE

A

D

SYNC_MASTER=CONSTRAINTS

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

PAGE TITLE

PCH Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

103 OF 109

SHEET

68 OF 72

124578

8 7 6 5 4 3

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

LAYER

TBT_SPI_45S

SPACING_RULE_SET

TBT_SPI

D

Thunderbolt/DP Connector Signal Constraints

TBTDP_80D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TBTDP_RX TBTDP_TX TBTDP_RX TBTDP_TX TBTDP_RX TBTDP_TX TBTDP_RX

LAYER

ALLOW ROUTE ON LAYER?

*

LINE-TO-LINE SPACING

*

ALLOW ROUTE ON LAYER?

*

TBTDP_TXTBTDP_TX TBTDP_RXTBTDP_RX TBTDP_RXTBTDP_TX TBTDP_TX

*_TX *_TX *_RX *_RX

* * *

=2x_DIELECTRIC

AREA_TYPE

* * * * * * * * *

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM LINE WIDTH

=80_OHM_DIFF

SPACING_RULE_SET

TBTDP_TX2TX TBTDP_RX2RX TBTDP_TX2RX

TBTDP_TX2RX TBTDP_2OTHERHS TBTDP_2OTHERHS TBTDP_2OTHERHS TBTDP_2OTHERHS

TBTDP_2OTHER TBTDP_2OTHER

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

TBTDP_TX2TX

TBTDP_RX2RX

TBTDP_TX2RX

TBTDP_2OTHERHS

TBTDP_2OTHER

SPACING_RULE_SET

TBTDP_TX2TX

TBTDP_RX2RX

TBTDP_TX2RX

TBTDP_2OTHERHS =6x_DIELECTRIC

TBTDP_2OTHER

C

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

TOP,BOTTOM?=6x_DIELECTRIC

LAYER

*

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=6x_DIELECTRIC

=10x_DIELECTRIC

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

?

? ? ?

WEIGHT

?

? ? ? ?

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

12

Thunderbolt/DP Net Properties

ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

DP_TBTPA_ML1 DP_TBTPA_ML1 DP_TBTPA_ML3 DP_TBTPA_ML3

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TBT_A_D2R1 TBT_A_D2R1 TBT_A_D2R0 TBT_A_D2R0

TBT_A_AUXCH TBT_A_AUXCH

TBT_B_R2D

DP_TBTPB_ML DP_TBTPB_ML

TBT_B_D2R TBTDP_80D

TBT_B_AUXCH TBT_B_AUXCH

NET_TYPE

PHYSICAL

TBTDP_80DTBT_A_R2D TBTDP_80DTBT_A_R2D TBTDP_80D TBTDP_80D

DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D

TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D TBTDP_80D

DP_80D DP_80D DP_AUX DP_80D DP_80D DP_80D DP_AUX DP_80D DP_AUX TBTDP_80D TBTDP_80D

TBTDP_80D TBTDP_80DTBT_B_R2D TBTDP_80D TBTDP_80D

DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D

TBTDP_80D TBTDP_80D

TBTDP_80DTBT_B_D2R

DP_80D DP_80D DP_80D DP_80D DP_80D DP_80D TBTDP_80D TBTDP_80D

SPACING

TBTDP_TX TBTDP_TX TBTDP_TX TBTDP_TX

DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX

TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX

DP_AUX

DP_AUX DP_AUX

TBTDP_RX TBTDP_RX

TBTDP_TX TBTDP_TX TBTDP_TX TBTDP_TX

DP_TX DP_TX DP_TX DP_TX DP_TX DP_TX

TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX

DP_AUX DP_AUX DP_AUX DP_AUX DP_AUX DP_AUX TBTDP_RX TBTDP_RX

TBT_A_R2D_C_P<1..0> TBT_A_R2D_C_N<1..0> TBT_A_R2D_P<1..0> TBT_A_R2D_N<1..0>

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1> DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3> DP_TBTPA_ML_P<3..1:2> DP_TBTPA_ML_N<3..1:2> DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

TBT_A_D2R_C_P<1..0> TBT_A_D2R_C_N<1..0> TBT_A_D2R_P<1> TBT_A_D2R_N<1> TBT_A_D2R_P<0> TBT_A_D2R_N<0>

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

TBT_B_R2D_C_P<1..0> TBT_B_R2D_C_N<1..0> TBT_B_R2D_P<1..0> TBT_B_R2D_N<1..0>

DP_TBTPB_ML_C_P<3..1:2> DP_TBTPB_ML_C_N<3..1:2> DP_TBTPB_ML_P<3..1:2> DP_TBTPB_ML_N<3..1:2> DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

TBT_B_D2R_C_P<1..0> TBT_B_D2R_C_N<1..0> TBT_B_D2R_P<1..0> TBT_B_D2R_N<1..0>

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

33 63

63

33 63

63

33 63

63

8

33

8

33

8

33

8

33

Only used on dual-port hosts.

8

33

8

33

8

33

8

33

D

C

Thunderbolt IC Net Properties

ELECTRICAL_CONSTRAINT_SET

B

TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L

A

6 3

PHYSICAL

DP_80D DP_80D

TBT_SPI_45STBT_SPI_CLK TBT_SPI_45S TBT_SPI_45S TBT_SPI_45S

NET_TYPE

SPACING

DP_TX DP_TX DP_AUXDP_80D DP_AUXDP_80D

TBT_SPI TBT_SPI TBT_SPI TBT_SPI

DP_TBTSRC_ML_C_P<3..0> DP_TBTSRC_ML_C_N<3..0> DP_TBTSRC_AUXCH_C_P DP_TBTSRC_AUXCH_C_N

TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L

Only used on hosts supporting Thunderbolt video-in

33

SYNC_MASTER=CONSTRAINTS

PAGE TITLE

Thunderbolt Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

105 OF 109

SHEET

69 OF 72

124578

SIZE

B

A

D

8 7 6 5 4 3

1:1_DIFFPAIR

LAYER

ALLOW ROUTE ON LAYER?

*

=STANDARD

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD =STANDARD=STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.1 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.1 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

D

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

PHYSICAL

SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S SMB_45S_R_50S

NET_TYPE

SPACING

SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

40 43

12

D

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR SENSE_DIFFPAIR

1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR

C

PHYSICAL

NET_TYPE

SPACING

CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N

CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N

52

C

SIZE

B

A

D

B

A

SYNC_MASTER=CONSTRAINTS

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

106 OF 109

SHEET

70 OF 72

124578

8 7 6 5 4 3

12

D

C

B

SENSE_1TO1_45S

SENSE_1TO1_P2MM

THERM_1TO1_45S

SPKR_DIFFPAIR

SPACING_RULE_SET

SENSE

LAYER

*

ALLOW ROUTE ON LAYER?

=1:1_DIFFPAIR

LINE-TO-LINE SPACING

THERM

AUDIO

SPACING_RULE_SET

*

LAYER

LINE-TO-LINE SPACING

GND *

LINE-TO-LINE SPACING

SPACING_RULE_SET

GND_P2MM 1000

PWR_P2MM 1000

LAYER

*

MINIMUM LINE WIDTH

=2:1_SPACING

=STANDARD

0.20 MM

0.200 MM

0.300 MM

WEIGHT

?

?*

?

WEIGHT

?

WEIGHT

MINIMUM NECK WIDTH

=45_OHM_SE=45_OHM_SE

0.100 MM

=45_OHM_SE=45_OHM_SE =45_OHM_SE

0.100 MM

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

CPU_COMP GND_P2MM

CPU_VCCSENSE GND_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND

SB_POWER

MAXIMUM NECK LENGTH

=45_OHM_SE

=1:1_DIFFPAIR

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

AREA_TYPE

GND *

AREA_TYPE

CLK_PCIE

PCIE*

SATA*

USB* GND_P2MM

LVDS*

CLK_PCIESB_POWER

SATA*

*GND

*

*GND

*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR

GND_P2MM

PWR_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

J11/J13 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR

THERM_1TO1_45SSENSE_DIFFPAIR THERM_1TO1_45S

THERM_1TO1_45SSENSE_DIFFPAIR THERM_1TO1_45S THERM_1TO1_45S THERM_1TO1_45S THERM_1TO1_45S THERM_1TO1_45S

SENSE_1TO1_45S SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_P2MM SENSE_1TO1_P2MM

SENSE_1TO1_P2MM SENSE_1TO1_P2MM SENSE_1TO1_45S SENSE_1TO1_45S

SENSE_1TO1_45S SENSE_1TO1_45S SENSE_1TO1_45S SENSE_1TO1_45S

SENSE_1TO1_P2MM SENSE_1TO1_P2MM

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45S SENSE_1TO1_45S

PHYSICAL

NET_TYPE

SPACING

THERM THERM

THERM THERM THERM THERM THERM THERM

SENSE SENSE

SENSE SENSE SENSE SENSE

SENSE SENSE

INLET_THMSNS_D1_P INLET_THMSNS_D1_N

TBT_THERMD_P TBT_THERMD_N TBT_MLBBOT_THMSNS_P TBT_MLBBOT_THMSNS_N TBTTHMSNS_D2_R_P TBTTHMSNS_D2_R_N

CPU_THERMD_P CPU_THERMD_N

CPUTHMSNS_D2_P CPUTHMSNS_D2_N

CPUVCCIOS0_CS_N CPUVCCIOS0_CS_P

CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N CPUIMVP_ISUM_R_P CPUIMVP_ISUM_R_N

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N CPUIMVP_ISUMG_R_P CPUIMVP_ISUMG_R_N

VCCSAS0_CS_P VCCSAS0_CS_N VCCSAISNS_R_P VCCSAISNS_R_N

ISNS_3V3S0_P ISNS_3V3S0_N ISNS_3V3S0_R_P ISNS_3V3S0_R_N

CPUIMVP_ISUMG_P CPUIMVP_ISUMG_N

CPUIMVP_ISUM_P CPUIMVP_ISUM_N

ISNS_HS_COMPUTING_N ISNS_HS_COMPUTING_P

ISNS_HS_OTHER_N ISNS_HS_OTHER_P

ISNS_1V5_S3_N ISNS_1V5_S3_P

ISNS_AIRPORT_N ISNS_AIRPORT_P

ISNS_SSD_N ISNS_SSD_P

ISNS_LCDBKLT_N ISNS_LCDBKLT_P

45 46

46

9

46

9

46

44 58

44 56 57

44 57

44

44 57

44

44 53

44

44 60

44

56 57

8

45

8

45

45 55

36 45

37 45

8

45

8

45

D

C

B

AUD_DIFF AUD_DIFF

SPKR_OUT SPKR_OUT

1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR 1:1_DIFFPAIR SPKR_DIFFPAIR SPKR_DIFFPAIR

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

SB_POWER SB_POWER

GND

A

6 3

SPKRAMP_INR_P SPKRAMP_INR_N MAX98300_R_P MAX98300_R_N SPKRAMP_ROUT_P SPKRAMP_ROUT_N

PP3V3_S5 PP3V3_S0

GND

6

39 50

6

39 50

50

6

50 51

6

50 51

6 7

SIZE

A

D

SYNC_MASTER=CONSTRAINTS

PAGE TITLE

Project Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

108 OF 109

SHEET

71 OF 72

124578

8 7 6 5 4 3

12

J11/J13 Board-Specific Spacing & Physical Constraints

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

D

DEFAULT

TOP,BOTTOM =50_OHM_SE=50_OHM_SE

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

ALLOW ROUTE ON LAYER?

*

Y

N*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=45_OHM_SE =45_OHM_SE

100 MM 100 MM

=DEFAULT =DEFAULTSTANDARD

=DEFAULT =DEFAULT =DEFAULT=DEFAULT

Single-ended Physical Constraints

ALLOW ROUTE ON LAYER?

27P4_OHM_SE

LAYER

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

27P4_OHM_SE

ALLOW ROUTE ON LAYER?

35_OHM_SE

LAYER

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL935_OHM_SE

35_OHM_SE =STANDARD =STANDARD =STANDARD

C

LAYER

40_OHM_SE

45_OHM_SE

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

LAYER

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ALLOW ROUTE ON LAYER?

ISL4,ISL945_OHM_SE

LAYER

ALLOW ROUTE ON LAYER?

50_OHM_SEYTOP,BOTTOM

B

ALLOW ROUTE ON LAYER?

* N

55_OHM_SE

LAYER

TOP,BOTTOM

Y

N*

Y

N*

Y

N*

Y

N*

Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.182 MM 0.182 MM

0.182 MM

100 MM 100 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.125 MM

0.125 MM 0.125 MM

100 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.170 MM 0.170 MM

0.096 MM 0.096 MM

0.096 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.135 MM 0.135 MM

0.075 MM 0.075 MM

0.080 MM 0.080 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM

100 MM

0.310 MM0.310 MM

0.182 MM

0.182 MM0.182 MM

0.195 MM0.195 MM

0.125 MM

100 MM

0.096 MM

0.099 MM0.099 MM

100 MM100 MM

0.110 MM0.110 MM

100 MM100 MM

0.090 MM

100 MM

BOARD AREAS

NO_TYPE,BGA

MAXIMUM NECK LENGTH

10 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

BOARD UNITS (MIL or MM)

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM 0 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD40_OHM_SE =STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD50_OHM_SE =STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_BOARD_INFO

ALLEGRO VERSION

16.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD45_OHM_SE =STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Spacing Constraints

SPACING_RULE_SET

LAYER

1:1_SPACING

SPACING_RULE_SET

1x_DIELECTRIC

LAYER

TOP,BOTTOM

ISL3,ISL10

ISL4,ISL9

1x_DIELECTRIC

SPACING_RULE_SET

LAYER

DEFAULT

STANDARD =DEFAULT

BGA_P1MM

BGA_P2MM

LINE-TO-LINE SPACING

*

LINE-TO-LINE SPACING

*

LINE-TO-LINE SPACING

*

0.100 MM

0.071 MM

0.053 MM

0.050 MM

0.090 MM

0.1 MM

=DEFAULT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

BGA_P1MM

BGA_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MEM_CLK

CLK_PCIE

CLK_SLOW

AREA_TYPE

BGA**

BGA*

SPACING_RULE_SET

D

C

B

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD=STANDARD

Differential Pair Physical Constraints

LAYER

72_OHM_DIFF

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

72_OHM_DIFF

LAYER

80_OHM_DIFF

A

80_OHM_DIFF

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

ALLOW ROUTE ON LAYER?

* N

ALLOW ROUTE ON LAYER?

80_OHM_DIFF

Y

N*

MINIMUM LINE WIDTH

100 MM

MINIMUM NECK WIDTH

0.165 MM 0.130 MM 0.130 MM0.165 MM

100 MM100 MM

MINIMUM NECK WIDTH

100 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD =STANDARD

6 3

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.150 MM0.150 MM0.109 MM0.109 MM

TABLE_PHYSICAL_RULE_ITEM

0.150 MM0.150 MM0.109 MM0.109 MM

TABLE_PHYSICAL_RULE_ITEM

0.150 MM0.150 MM0.114 MM0.114 MM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.130 MM0.130 MM0.132 MM0.132 MM

TABLE_PHYSICAL_RULE_ITEM

0.115 MM0.115 MM0.081 MM0.081 MM

TABLE_PHYSICAL_RULE_ITEM

0.115 MM0.115 MM0.081 MM0.081 MM

TABLE_PHYSICAL_RULE_ITEM

0.110 MM0.110 MM0.088 MM0.088 MM

TABLE_PHYSICAL_RULE_ITEM

SYNC_MASTER=CONSTRAINTS

PAGE TITLE

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2012

DRAWING NUMBER

051-9276

REVISION

2.7.0

BRANCH

PAGE

109 OF 109

SHEET

72 OF 72

SIZE

A

D

124578