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3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3
B
7
ECNREV
BRANCH
DRAWING NUMBER
REVISION
SIZE
D
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
DRAWING TITLE
THE POSESSOR AGREES TO THE FOLLOWING:
Apple Inc.
SHEET
R
DATE
D
A
C
THE INFORMATION CONTAINED HEREIN IS THE
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
C
3456
D
B
8 7 6 5 4 2 1
12
APPD
CK
DESCRIPTION OF REVISION
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_TABLEOFCONTENTS_ITEM
SCHEM,MLB DVT,K99
07/22/10
Schematic / PCB #’s
1 OF 73
051-8379
4.4.0
1 OF 110
2010-07-22
45
56
K16_MLB
07/07/2010
Fan
44
55
K16_MLB
07/07/2010
Thermal Sensors
43
54
K16_MLB
07/07/2010
Current Sensing
42
53
K16_MLB
07/07/2010
Voltage & Current Sensing
41
52
K16_MLB
07/07/2010
K16/K99 SMus Connections
40
51
K16_MLB
07/07/2010
LPC+SPI Debug Connector
39
50
K16_MLB
07/07/2010
SMC Support
38
49
K16_MLB
07/07/2010
SMC
37
47
N/A
N/A
LIO CONNECTORS
36
46
K16_MLB
07/07/2010
External USB Connectors
35
45
K16_MLB
07/07/2010
SATA CONNECTOR
34
40
K16_MLB
07/07/2010
X21 WIRELESS CONNECTOR
33
39
K16_MLB
07/07/2010
FSB/DDR3 Vref Margining
32
37
K16_MLB
07/07/2010
Memory Active Termination
31
36
K16_MLB
07/07/2010
DDR BYPASSING 2
30
35
K16_MLB
07/07/2010
DDR BYPASSING 1
29
34
K16_MLB
07/07/2010
DDR3 DRAM Channel B (32-63)
28
33
K16_MLB
07/07/2010
DDR3 DRAM Channel B (0-31)
27
32
K16_MLB
07/07/2010
DDR3 DRAM Channel A (32-63)
26
31
K16_MLB
07/07/2010
DDR3 DRAM Channel A (0-31)
25
28
K6_MLB
12/11/2009
SB Misc
24
26
K16_MLB
07/07/2010
MCP Graphics Support
23
25
K16_MLB
07/07/2010
MCP Standard Decoupling
22
24
K16_MLB
07/07/2010
MCP89 GFX Core Rail Gating
21
23
K16_MLB
07/07/2010
MCP89 Memory Rail Gating
20
20
K16_MLB
07/07/2010
MCP Power & Ground
19
19
K16_MLB
07/07/2010
MCP HDA, LPC & MISC
18
18
K16_MLB
07/07/2010
MCP SATA, USB & Ethernet
17
17
K16_MLB
07/07/2010
MCP Graphics
16
16
K16_MLB
07/07/2010
MCP PCIe Interfaces
15
15
K16_MLB
07/07/2010
MCP Memory Interface
14
14
K16_MLB
07/07/2010
MCP CPU Interface
13
13
K16_MLB
07/07/2010
eXtended Debug Port (Micro-XDP)
12
12
K16_MLB
03/24/2010
CPU Decoupling & VID
11
11
K16_MLB
07/07/2010
CPU Power & Ground
10
10
K16_MLB
07/07/2010
CPU FSB
9
9
K6_MLB
12/11/2009
SIGNAL ALIAS
8
8
K6_MLB
12/11/2009
Power Aliases
7
7
K6_MLB
12/11/2009
FUNCTIONAL TEST
6
6
K24_MLB
01/19/2009
Revision History
5
5
K24_MLB
07/20/2009
BOM Configuration
4
4
K6_MLB
12/11/2009
K99 BOM Variants
3
3
K6_MLB
12/11/2009
Power Block Diagram
2
2
K6_MLB
12/11/2009
System Block Diagram
110
Acoustic Cap BOM Config Tables
K16_MLB
07/07/2010
73
109
K99 RULE DEFINITIONS
K16_MLB
07/07/2010
72
108
K16/K99 Specific Constraints
K16_MLB
07/07/2010
71
106
SMC Constraints
K16_MLB
07/07/2010
70
104
Ethernet Constraints
K16_MLB
07/07/2010
69
103
MCP Constraints 2
K16_MLB
07/07/2010
68
102
MCP Constraints 1
K16_MLB
07/07/2010
67
101
Memory Constraints
K16_MLB
07/07/2010
66
100
CPU/FSB Constraints
K16_MLB
07/07/2010
65
99
Additional CPU/GPU Decoupling
K16_MLB
07/07/2010
64
98
LCD Backlight Support
K16_MLB
07/07/2010
63
97
LCD Backlight Driver
K16_MLB
03/31/2010
62
94
DisplayPort Connector
K16_MLB
07/07/2010
61
93
External DisplayPort Support
K16_MLB
07/07/2010
60
90
Internal DisplayPort Connector
K16_MLB
07/07/2010
59
79
Power FETs
K16_MLB
07/07/2010
58
78
Power Sequencing
K16_MLB
07/07/2010
57
77
Misc Power Supplies
K16_MLB
07/07/2010
56
76
CPUVTT (1.05V) Power Supply
K16_MLB
07/07/2010
55
75
MCP VCore Regulator
K6_MLB
12/11/2009
54
74
IMVP6 CPU VCore Regulator
POWER
07/13/2005
53
73
1.5V/1.35V LVDDR3 Supply
K16_MLB
07/07/2010
52
72
5V / 3.3V Power Supply
K16_MLB
07/07/2010
51
70
PBus Supply & Battery Charger
K6_MLB
11/09/2009
50
69
DC-In & Battery Connectors
K84_MLB
11/09/2009
49
66
AUDI0: SPEAKER AMP
AUDIO
02/09/2010
48
61
SPI ROM
K16_MLB
07/07/2010
47
SCHEM,MLB,K99
Contents
(.csa)
Sync
Date
Page
(.csa)
Contents
Date
SyncPage
57
WELLSPRING 1
K16_MLB
07/07/2010
46
1
CRITICAL
PCB
820-2796
PCBF,MLB,K99
SCH
1
CRITICAL051-8379
SCHEM,MLB,K99
1
1
Table of Contents
Page 2
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
1.6 GHZ
XDP CONN
GPIO
MAIN
FSB INTERFACE
PG 36
PG 19
NVIDIA
MCP89U-A01
24.5X24.5MM
0.6MM PITCH
1244P
SPEAKER
J6903
SIL+
SPEAKER
(IPD)
FAN CONN
ADC
U4900
TRACKPAD
PG 37
AUDIO CODEC
LIO FLEX CONN
PG 34
EXT
CAMERA
HDA
PE0[4,5]:X2,X1 GEN2,UP TO 2 LANES
PG 35
PG 25
UP TO 2 PORTS
SATA_A0
J4501
PG 25
PG 19
RTC XTAL
PG 13
J1300
1GB
PG 10
PG 28,29
PG 48
CONN
PG 19
PG 18
PG 19
USB_4
PG 19
HDA
PG 18PG 16
LAN
PG 17
PG 18
PANEL
FLAT
PG 26,27
SUPPORT GEN3,6.0GB/S
PG 19
BOOTROM
SPI
PG 15
PG 14
USB 2.0
J4600
RIGHT
LPC
PG 10
PG 9
J6702
CONN
PG 10
PG 5
LIO BOARD
CONN
J4001
PE1_0
PCIE GEN1
Y2815
MCP
CONN
PWR
SATA
RGB OUT
J9000
EXTERNAL
CONN
DISPLAY
CONN
J9400
PG 62
DISPLAY
EXT USB
U1000
PG 38
CONN
PG 52-57
PG 44
PG 42,43
J5600
PG 45
DP1[1:0]
CONN
CONN
CONN
POWER SUPPLY
LIO
CTRL
J5100
A
B
HDMI OUT
DVI OUT
RGMII
128MX8
MEMORY
U3100,U3200
128MX8
U3300,3400
PG 40
PORT
SERIAL
SMB_BSA SMB_B/0
FAN0
SMS
LID
PM_SLP
SYS_LED
SMB_A
U5920
HALL EFFECT
PG 50
PG 46
PG 50
PG 49
I2C
USB
MIKEY
I2C
J4610
ALS
CONN
CAMERA+
J4702
LEFT
PG 6
EXT USB
PG 11
FILTER
LINE IN
PG 8
FILTER
HEADPHONE
JACK
LINE IN
HEADPHONE/
J6700
SPEAKER
LEFT
AMPS
U6620
SPEAKER
PG 6
CONN
INTERNAL
SSD
PCI-E
CPU/MCP TEMP SENSOR
J6950,U7000
U5515.U5535
SATA
PG 50,51
VOLTAGE/CURRENT SENSOR
PG 47
SMS
CHARGER,BATT CONN
U6610
J6955
S3/S4
DP0[3:0]
PG 60
FCPBGA
SATA 2.0 3GBIT/S
32.768KHZ
X4 DP LINK
25MHZ
BLUETOOTH
Y2810
AIRPORT+
J4700
U6201
AMPS
J5700
USB_2
USB_6
USB_0
USB_5
SMC
LPC+SPI
USB_7
(UP TO 8 DEVICES)
LVDS OUT
TMDS OUT
USB SPK
SPI
U6100
INTEL CPU
MISC
PG 19
DDR3-1066/1333MHZ
DDR3-1066/1333MHZ
64-BIT
MEMORY
64-BIT
FSB
64-BIT
800MHZ
BASE FREQ.=200MHZ
PENRYN
PE1[0,1]:X1,X1 GEN1,UP TO 2 LANES
X2 DP LINK
SMB
1GB
MEMORY
SYNC_MASTER=K6_MLB
SYNC_DATE=12/11/2009
System Block Diagram
2 OF 110
4.4.0
051-8379
2 OF 73
Page 3
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MAX8840
PP1V05_S0_MCP_PLL_REG
MCP89
DELAY
RC
DELAY
RC
DELAY
RC
RC
P1V8S0_EN
MCPCORES0_EN
CPUVTTS0_EN
DDRVTT_EN
16-5
16-6
PM_SLP_S3_L
16-3
16-4
AP_PWR_EN
Q7890
(9 TO 12.6V)
3S2P
PM_SLP_S3_L
U1400
PM_SLP_S4_L
MCP89
11
15
DELAY
RC
11-2
RC
DELAY
11-3
11-1
J6950
PBUSVSENSE_EN
DELAY
PM_WLAN_EN_L
RC
P3V3S0_EN
(S0)
(S0)
16-2
16-1
16-1
04-1
=DDRREG_EN
=DDTVTT_EN
S5
S3
U7300
MCPCORES0_EN
VOUT2
TPS51116
0.75V
VOUT1
02
VIN
EN
VIN
02
1.5V
P5VS3_EN_L
P3V3S3_EN
BKLT_EN
U4900
SMC
P60
P16
ENA
02
(S5)
01
A
ADAPTER
AC
IN
6A FUSE
01
A
ENABLES
PP18V5_DCIN_CONN
VOUT
PPVBAT_G3H_CHGR_REG
Q7085
P3V3S5_EN_L
IMVP_VR_ON_R
25
02
U7500
VOUT
(25A MAX CURRENT)
20
PP1V5_S3_REG
ISL8009B
VIN
VOUT
R7525
P3V3S0_EN
U7720
1.2V
U7710
ISL8009B
U7740
1.8V
TPS62202
U7760
1.5V
EN2
05
VIN
EN1
02
3.3V
(RT)
5V
VREG3
VR_ON
VIN
PP3V3_S5_REG
Q7910
28
V
PP3V3_S0_FET
PP1V8_S0_REG
PP1V5_S0_REG
PP3V3_S0
PP1V5_S0
PP1V05_S0
V2
V1
RST*
U7870
P1V5S0_PGOOD
P5V3V3_PGOOD
MCPCORES0_PGOOD
SLP_S5_L
SLP_S4_L
SLP_S3_L
09
ALL_SYS_PWRGD
05
SMC_ONOFF_L
RSMRST_PWRGD
SLP_S4_L(P94)
SLP_S3_L(P93)
SLP_S5_L(P95)
U4900
PWRGD(P12)
PWR_BUTTON(P90)
RSMRST_IN(P13)
99ms DLY
26
VIN
EN
U6200
VOUT
4.5V AUDIO
PP4V5_AUDIO_ANALOG
24
07
17
Q7940
P5VS0_EN
PP5V_S0_FET
SMC
29
U1000
CPU
U1400
PWRGD
02
CPUVTTS0_EN
02
EN_PSV
VIN
LT3470
ENABLE
U6990
VOUT
3.425V G3HOT
PBUS_G3H_VSENSE
PP1V05_S0
(8A MAX CURRENT)
PP3V42_G3H_REG
03
RN5VD30A-F
SMC PWRGD
U5010
04
RST*
P17(BTN_OUT)
IMVP_VR_ON(P16)
RSMRST_OUT(P15)
PLT_RST*
CPU_RESET#
PWRBTN*
PLTRST*
RESET*
CPUPWRGD(GPIO49)
PWRGOOD
RSMRST*
IMVP_VR_ON_R
PM_PWRBTN_L
SMC_RESET_L
25
PM_RSMRST_L
32
10
FSB_CPURST_L
30
CPU_PWRGD
LPC_RESET_L
31
06-1
13
PP5V_S3_REG
(5.5A MAX
PGOOD1,2
ISL88042
V3
PPBUS_G3H
V
PPDCIN_G3H_OR_PBUS
16
21
Q5315
EN
Q7890,Q7891
DELAY
P1V5S0_EN
P5VS0_EN
DCIN(16.5V)
DDRREG_EN
P5VS3_EN_L
SMC_DCIN_ISENSE
(S0)
F6905
Q7055
PPVBAT_G3H_CHGR_R
R7020
VIN
(S5)
ISL6259
U7000
8A FUSE
F7040
VOUT
Q7080
PBUS_VSENSE
PGOOD
U7600
SMC_CPU_VSENSE
CPUVTTS0_PGOOD
VOUT
CPUVTT
ISL95870
(1.05V)
PPBUS_G3H
CPU VCORE
ISL6261A
U7400
PGOOD
VOUT1
VOUT2
VR_PWRGOOD_DELAY
SMC_CPU_ISENSE
PPVCORE_S0_CPU
(44A MAX CURRENT)
MC34845
VIN
VOUT
U9700
TPS51980
P5V3V3_PGOOD
04
PPVOUT_SW_LCDBKLT
ST1S12G12R
U7201
PPMCPCORE_S0_R
14
PM_SLP_S3_L
SMC_ADAPTER_EN
ISL9563B
1.05V
PP1V2_ENET_REG
TPS74701
S0PGOOD_RST_L
U7750
(13A MAX CURRENT)
CURRENT)
P3V3S3_EN
Q7930
(12A MAX CURRENT)
PP0V75_S0_REG
(1A MAX CURRENT)
PPMCPCORE_S0_REG
MCP_CORE
MCPMEM_GATE
Q2300
MCP_PS_PWRGD
U2850
CPUVTTS0_PGOOD
MCPPLLDO_PGOOD
18
P3V3_S3_WLAN
PM_WLAN_EN_L
Q4050
PP3V3_S3_FET
PPVBAT_G3H_CONN
CHGR_BGATE
PP1V5R1V35_SW_MCP
PP0V9_S5_REG
U7840
SMC_PM_G2_EN
BATTERY CHARGER
PBUS SUPPLY/
CHGR_EN
SMC_BATT_ISENSE
R7050
K99 POWER SYSTEM ARCHITECTURE
Need to update!!!
SYNC_DATE=12/11/2009
SYNC_MASTER=K6_MLB
Power Block Diagram
3 OF 110
4.4.0
051-8379
3 OF 73
Page 4
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
BOM Variants
Sub-BOMs
Bar Code Labels / EEE #’s
4GB
DIE REV
CFG 3CFG 2
1
0
B
A
HYNIX
1
0
SIZE
2GB
DRAM CFG CHART
0 0
1
CFG 0CFG 1
VENDOR
0
SAMSUNG
0 1
1
ELPIDA
1
MICRON
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0L,DDR3:HYNIX_4GB,CAPS:TY
639-1039
PCBA,MLB,HY 4GB,TY CAP,K99
PCBA,MLB,SA 4GB,TY CAP,K99
639-1040
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0M,DDR3:SAMSUNG_4GB,CAPS:TY
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0W,DDR3:MICRON_2GB,CAPS:TY
639-1047
PCBA,MLB,MI 2GB,TY CAP,K99
639-1051
PCBA,MLB,MI 4GB,SS CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DD11,DDR3:MICRON_4GB,CAPS:SS
639-1446
PCBA,MLB,1.6GHZ,EL 2GB,SS CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4Q,DDR3:ELPIDA_2GB,CAPS:SS
K99_CMNPTS,CPU:1.4GHZ,EEE:DF83,DDR3:HYNIX_2GB,CAPS:MU
639-1341
PCBA,MLB,1.4GHZ,HY 2GB,MU CAP,K99
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8N,DDR3:SAMSUNG_2GB,CAPS:TY
PCBA,MLB,1.4GHZ,SA 2GB,TY CAP,K99
639-1357
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DG4M]
EEE:DG4M825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DG4R]
EEE:DG4R825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DG4L]
EEE:DG4L825-7557
CRITICAL
1
LABEL,MLB,K16/K99
[EEE_DG4V]
EEE:DG4V825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DG4T]
EEE:DG4T825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DG4Q]
EEE:DG4Q825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DG4P]
EEE:DG4P825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DG4N]
EEE:DG4N825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DG4K]
EEE:DG4K825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DG4J]
EEE:DG4J825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DG4G]
EEE:DG4G825-7557
CRITICAL
1
LABEL,MLB,K16/K99
EEE:DF8N
[EEE_DF8N]
825-7557
1
CRITICAL
LABEL,MLB,K16/K99
EEE:DF8L
[EEE_DF8L]
825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DF8J]
EEE:DF8J825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DF8G]
EEE:DF8G825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DF8D]
EEE:DF8D825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DF89]
EEE:DF89825-7557
EEE:DF87
LABEL,MLB,K16/K99
CRITICAL
1
[EEE_DF87]
825-7557
EEE:DF86
LABEL,MLB,K16/K99
CRITICAL
1
[EEE_DF86]
825-7557
EEE:DF85CRITICAL
1
LABEL,MLB,K16/K99
[EEE_DF85]
825-7557
EEE:DF84CRITICAL
1
LABEL,MLB,K16/K99
[EEE_DF84]
825-7557
EEE:DF83
[EEE_DF83]
1
CRITICAL
LABEL,MLB,K16/K99
825-7557
CRITICAL
1
EEE:DD15
LABEL,MLB,K16/K99
[EEE_DD15]
825-7557
[EEE_DD13]
1
CRITICAL EEE:DD13
LABEL,MLB,K16/K99
825-7557
1
CRITICAL
[EEE_DD12]
EEE:DD12
LABEL,MLB,K16/K99
825-7557
[EEE_DD10]
1
LABEL,MLB,K16/K99
CRITICAL EEE:DD10825-7557
1
CRITICAL
[EEE_DD0X]
EEE:DD0X
LABEL,MLB,K16/K99
825-7557
LABEL,MLB,K16/K99
1
[EEE_DD0W]
EEE:DD0WCRITICAL825-7557
[EEE_DD0V]
LABEL,MLB,K16/K99
CRITICAL
1
EEE:DD0V825-7557
[EEE_DD0T]
1
EEE:DD0TCRITICAL
LABEL,MLB,K16/K99
825-7557
CRITICAL
1
[EEE_DD0Q]
LABEL,MLB,K16/K99
EEE:DD0Q825-7557
CRITICAL
1
EEE:DD0P
[EEE_DD0P]
LABEL,MLB,K16/K99
825-7557
1
CRITICAL
[EEE_DD0N]
LABEL,MLB,K16/K99
EEE:DD0N825-7557
[EEE_DD0M]
CRITICAL EEE:DD0M
LABEL,MLB,K16/K99
1
825-7557
1
CRITICAL
[EEE_DD0L]
EEE:DD0L
LABEL,MLB,K16/K99
825-7557639-1055
PCBA,MLB,HY 2GB,MU CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DD15,DDR3:HYNIX_2GB,CAPS:MU
PCBA,MLB,HY 4GB,MU CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0R,DDR3:HYNIX_4GB,CAPS:MU
639-1044
639-1054
K99_CMNPTS,CPU:1.6GHZ,EEE:DD14,DDR3:SAMSUNG_2GB,CAPS:MU
PCBA,MLB,SA 2GB,MU CAP,K99
K99 BOM Variants
SYNC_DATE=12/11/2009
SYNC_MASTER=K6_MLB
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DG4H]
EEE:DG4H825-7557
1
LABEL,MLB,K16/K99
CRITICAL
[EEE_DF8K]
EEE:DF8K825-7557
639-1445
PCBA,MLB,1.6GHZ,EL 4GB,TY CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4P,DDR3:ELPIDA_4GB,CAPS:TY
K99_COMMON
CMN PTS,PCBA,MLB,K99
607-6999
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DF88]
EEE:DF88825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DF8C]
EEE:DF8C825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DF8F]
EEE:DF8F825-7557
1
CRITICAL
LABEL,MLB,K16/K99
[EEE_DF8H]
EEE:DF8H825-7557
CRITICAL EEE:DF8M
1
LABEL,MLB,K16/K99
[EEE_DF8M]
825-7557
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8L,DDR3:HYNIX_2GB,CAPS:SS
639-1355
PCBA,MLB,1.4GHZ,HY 2GB,SS CAP,K99
K99 MLB DEVELOPMENT BOM
K99_DEVEL:ENG
085-1121
639-1448
PCBA,MLB,1.6GHZ,EL 4GB,MU CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4T,DDR3:ELPIDA_4GB,CAPS:MU
PCBA,MLB,1.6GHZ,EL 4GB,SS CAP,K99
639-1449
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4V,DDR3:ELPIDA_4GB,CAPS:SS
639-1444
PCBA,MLB,1.6GHZ,EL 2GB,TY CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4N,DDR3:ELPIDA_2GB,CAPS:TY
639-1438
PCBA,MLB,1.6GHZ,EL 2GB,MU CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4G,DDR3:ELPIDA_2GB,CAPS:MU
639-1050
K99_CMNPTS,CPU:1.6GHZ,EEE:DD10,DDR3:MICRON_4GB,CAPS:TY
PCBA,MLB,MI 4GB,TY CAP,K99
639-1049
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Y,DDR3:SAMSUNG_2GB,CAPS:TY
PCBA,MLB,SA 2GB,TY CAP,K99
1
CRITICAL
[EEE_DD11]
EEE:DD11
LABEL,MLB,K16/K99
825-7557
EEE:DF82CRITICAL
[EEE_DF82]
LABEL,MLB,K16/K99
1
825-7557
[EEE_DD14]
EEE:DD14CRITICAL
1
LABEL,MLB,K16/K99
825-7557
LABEL,MLB,K16/K99
[EEE_DD0Y]
EEE:DD0YCRITICAL
1
825-7557
K99_CMNPTS,CPU:1.6GHZ,EEE:DX7,DDR3:HYNIX_2GB,CAPS:SS
639-0651
PCBA,MLB,HY 2GB,SS CAP,K99
PCBA,MLB,HY 4GB,SS CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Q,DDR3:HYNIX_4GB,CAPS:SS
639-1043
PCBA,MLB,1.4GHZ,HY 4GB,TY CAP,K99
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8C,DDR3:HYNIX_4GB,CAPS:TY
639-1348
639-1356
PCBA,MLB,1.4GHZ,HY 4GB,MU CAP,K99
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8M,DDR3:HYNIX_4GB,CAPS:MU
639-1350
PCBA,MLB,1.4GHZ,HY 4GB,SS CAP,K99
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8F,DDR3:HYNIX_4GB,CAPS:SS
639-1045
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0T,DDR3:SAMSUNG_2GB,CAPS:SS
PCBA,MLB,SA 2GB,SS CAP,K99
[EEE_DD0R]
1
CRITICAL EEE:DD0R
LABEL,MLB,K16/K99
825-7557
PCBA,MLB,1.4GHZ,EL 2GB,SS CAP,K99
639-1442
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4L,DDR3:ELPIDA_2GB,CAPS:SS
PCBA,MLB,1.4GHZ,EL 2GB,MU CAP,K99
639-1443
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4M,DDR3:ELPIDA_2GB,CAPS:MU
LABEL,MLB,K16/K99
[EEE_DX7]
1
CRITICAL825-7557
EEE:DX7
K99_CMNPTS
CRITICALCMNPTS
CMN PTS,PCBA,MLB,K99
607-6999
1
DEVEL_BOM
K99 MLB DEVELOPMENT BOM
DEVEL
CRITICAL085-1121
1
K99_CMNPTS,CPU:1.4GHZ,EEE:DF88,DDR3:MICRON_2GB,CAPS:MU
PCBA,MLB,1.4GHZ,MI 2GB,MU CAP,K99
639-1346
PCBA,MLB,1.4GHZ,EL 2GB,TY CAP,K99
639-1447
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4R,DDR3:ELPIDA_2GB,CAPS:TY
PCBA,MLB,1.4GHZ,EL 4GB,TY CAP,K99
639-1440
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4J,DDR3:ELPIDA_4GB,CAPS:TY
PCBA,MLB,1.4GHZ,EL 4GB,MU CAP,K99
639-1439
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4H,DDR3:ELPIDA_4GB,CAPS:MU
PCBA,MLB,1.4GHZ,EL 4GB,SS CAP,K99
639-1441
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4K,DDR3:ELPIDA_4GB,CAPS:SS
K99_CMNPTS,CPU:1.4GHZ,EEE:DF82,DDR3:MICRON_4GB,CAPS:TY
PCBA,MLB,1.4GHZ,MI 4GB,TY CAP,K99
639-1340
PCBA,MLB,1.4GHZ,MI 4GB,MU CAP,K99
639-1345
K99_CMNPTS,CPU:1.4GHZ,EEE:DF87,DDR3:MICRON_4GB,CAPS:MU
K99_CMNPTS,CPU:1.4GHZ,EEE:DF84,DDR3:MICRON_2GB,CAPS:SS
PCBA,MLB,1.4GHZ,MI 2GB,SS CAP,K99
639-1342
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8K,DDR3:SAMSUNG_4GB,CAPS:TY
PCBA,MLB,1.4GHZ,SA 4GB,TY CAP,K99
639-1354
639-1353
PCBA,MLB,1.4GHZ,HY 2GB,TY CAP,K99
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8J,DDR3:HYNIX_2GB,CAPS:TY
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8G,DDR3:SAMSUNG_2GB,CAPS:MU
639-1351
PCBA,MLB,1.4GHZ,SA 2GB,MU CAP,K99
PCBA,MLB,1.4GHZ,SA 2GB,SS CAP,K99
639-1349
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8D,DDR3:SAMSUNG_2GB,CAPS:SS
PCBA,MLB,1.4GHZ,MI 4GB,SS CAP,K99
639-1347
K99_CMNPTS,CPU:1.4GHZ,EEE:DF89,DDR3:MICRON_4GB,CAPS:SS
K99_CMNPTS,CPU:1.4GHZ,EEE:DF85,DDR3:MICRON_2GB,CAPS:TY
PCBA,MLB,1.4GHZ,MI 2GB,TY CAP,K99
639-1343
K99_CMNPTS,CPU:1.4GHZ,EEE:DF86,DDR3:SAMSUNG_4GB,CAPS:SS
639-1344
PCBA,MLB,1.4GHZ,SA 4GB,SS CAP,K99
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8H,DDR3:SAMSUNG_4GB,CAPS:MU
PCBA,MLB,1.4GHZ,SA 4GB,MU CAP,K99
639-1352
639-1052
PCBA,MLB,SA 4GB,SS CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DD12,DDR3:SAMSUNG_4GB,CAPS:SS
PCBA,MLB,MI 2GB,SS CAP,K99
639-1042
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0P,DDR3:MICRON_2GB,CAPS:SS
PCBA,MLB,MI 2GB,MU CAP,K99
639-1053
K99_CMNPTS,CPU:1.6GHZ,EEE:DD13,DDR3:MICRON_2GB,CAPS:MU
639-1041
PCBA,MLB,MI 4GB,MU CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0N,DDR3:MICRON_4GB,CAPS:MU
PCBA,MLB,SA 4GB,MU CAP,K99
639-1046
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0V,DDR3:SAMSUNG_4GB,CAPS:MU
639-1048
PCBA,MLB,HY 2GB,TY CAP,K99
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0X,DDR3:HYNIX_2GB,CAPS:TY
4 OF 110
4.4.0
051-8379
4 OF 73
Page 5
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
BOM Groups
Programmable Parts
Module Parts
Alternate Parts
BOM Configuration
SYNC_MASTER=K24_MLB
SYNC_DATE=07/20/2009
104S0018104S0023
CYNTEC/DALE AS ALTERNATES
ALL
155S0367
TAIYO AS ALTERNATE
ALL
155S0578
ALL
376S0926 376S0610
FAIRCHILD AS ALTERNATE
TAIYO AS ALTERNATE
138S0673138S0671
ALL
107S0139
CYNCTEC AS ALTERNATE
107S0075
ALL
138S0681 138S0638
ALL
TAIYO YUDEN AS ALTERNATE
MAGLAYERS AS ALTERNATE
ALL
152S0516152S0874
IC,SMC,HS8/2117,9X9MM,TLP,HF
338S0563
U4900
CRITICAL
SMC:BLANK
1
DEVEL_BOM,SMC_DEBUG:YES,XDP
K99_DEBUG:ENG
DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO
K99_DEBUG:PVT
BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO
K99_DEBUG:PROD
DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB
DDR3:HYNIX_2GB
DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB
DDR3:HYNIX_4GB
DDR3:ELPIDA_4GB
DRAM_CFG0:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB
BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,MCPPLL_LDO,S3_S0_LED
K99_DEVEL:ENG
HVDDLDO:FIXED
TPS71725DCK AS ALTERNATE FOR U2590
353S2987 353S2988
ALL
335S0610
U6100
CRITICAL
BOOTROM:BLANK
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
1
341T0262 CRITICAL
IC ASSY,EFI UNLOCKED,K99
U6100
1
BOOTROM:UNLOCKED
333S0555
HYNIX,LVDDR3,2GBIT,9X11.1
DRAM_TYPE:HYNIX_4GB
U3400,U3410,U3420,U3430
CRITICAL
4
CRITICAL
U3200,U3210,U3220,U3230
SAMSUNG,LVDDR3,2GBIT,7.5X11.0
4
333S0556
DRAM_TYPE:SAMSUNG_4GB
SAMSUNG,LVDDR3,2GBIT,7.5X11.0
CRITICAL
DRAM_TYPE:SAMSUNG_4GB
U3400,U3410,U3420,U3430
4
333S0556
MICRON,LVDDR3,2GBIT,9X11.5
333S0557 CRITICAL
4
DRAM_TYPE:MICRON_4GB
U3100,U3110,U3120,U3130
333S0566
DRAM_TYPE:ELPIDA_4GB
U3200,U3210,U3220,U3230
CRITICAL
4
ELPIDA,LVDDR3,2GBIT,9X11.5
U3400,U3410,U3420,U3430
333S0566
DRAM_TYPE:ELPIDA_4GB
4
CRITICAL
ELPIDA,LVDDR3,2GBIT,9X11.5
ISL6259_SCREENED:NO
IC,ISL6259,BATCHARGER,4X4MM,QFN28
353S2392
1
U7000
CRITICAL
U7000
ISL6259_SCREENED:YES
353S2929
1
IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28
CRITICAL
U3200,U3210,U3220,U3230
333S0555
4
DRAM_TYPE:HYNIX_4GB
HYNIX,LVDDR3,2GBIT,9X11.1
CRITICAL
333S0557
MICRON,LVDDR3,2GBIT,9X11.5
4
CRITICAL
DRAM_TYPE:MICRON_4GB
U3200,U3210,U3220,U3230
333S0557
DRAM_TYPE:MICRON_4GB
4
CRITICAL
U3300,U3310,U3320,U3330
MICRON,LVDDR3,2GBIT,9X11.5
333S0566
U3100,U3110,U3120,U3130
4
CRITICAL
ELPIDA,LVDDR3,2GBIT,9X11.5
DRAM_TYPE:ELPIDA_4GB
ASSEMBLY,SUBASSY,PCBA HALL EFFECT, K99
J6955
CRITICAL
1
607-6811
U3100,U3110,U3120,U3130
333S0555
DRAM_TYPE:HYNIX_4GB
HYNIX,LVDDR3,2GBIT,9X11.1
4
CRITICAL
ELPIDA,LVDDR3,1GBIT,7.5X10.6
DRAM_TYPE:ELPIDA_2GB
333S0565
U3400,U3410,U3420,U3430
4
CRITICAL
U3300,U3310,U3320,U3330
333S0555
DRAM_TYPE:HYNIX_4GB
CRITICAL
4
HYNIX,LVDDR3,2GBIT,9X11.1
U3300,U3310,U3320,U3330
333S0556
SAMSUNG,LVDDR3,2GBIT,7.5X11.0
DRAM_TYPE:SAMSUNG_4GB
4
CRITICAL
MAGLAYERS AS ALTERNATE
155S0329155S0457
ALL
SAMSUNG,LVDDR3,2GBIT,7.5X11.0
333S0556
U3100,U3110,U3120,U3130
DRAM_TYPE:SAMSUNG_4GB
4
CRITICAL
U3100,U3110,U3120,U3130
333S0552
HYNIX,LVDDR3,1GBIT,7.5X11.0
4
CRITICAL
DRAM_TYPE:HYNIX_2GB
HYNIX,LVDDR3,1GBIT,7.5X11.0
U3200,U3210,U3220,U3230
333S0552 CRITICAL
4
DRAM_TYPE:HYNIX_2GB
333S0552
HYNIX,LVDDR3,1GBIT,7.5X11.0
4
U3300,U3310,U3320,U3330
DRAM_TYPE:HYNIX_2GB
CRITICAL
HYNIX,LVDDR3,1GBIT,7.5X11.0
333S0552
U3400,U3410,U3420,U3430
4
DRAM_TYPE:HYNIX_2GB
CRITICAL
333S0553
U3200,U3210,U3220,U3230
CRITICAL
4
DRAM_TYPE:SAMSUNG_2GB
SAMSUNG,LVDDR3,1GBIT,7.5X11.0
U3300,U3310,U3320,U3330
4
DRAM_TYPE:SAMSUNG_2GB
CRITICAL333S0553
SAMSUNG,LVDDR3,1GBIT,7.5X11.0
333S0554 CRITICAL
U3100,U3110,U3120,U3130
4
MICRON,LVDDR3,1GBIT,8X11.5
DRAM_TYPE:MICRON_2GB
CRITICAL333S0554
MICRON,LVDDR3,1GBIT,8X11.5
4
U3200,U3210,U3220,U3230
DRAM_TYPE:MICRON_2GB
DRAM_TYPE:ELPIDA_2GB
ELPIDA,LVDDR3,1GBIT,7.5X10.6
333S0565
U3200,U3210,U3220,U3230
4
CRITICAL
DRAM_TYPE:ELPIDA_2GB
ELPIDA,LVDDR3,1GBIT,7.5X10.6
333S0565
U3300,U3310,U3320,U3330
4
CRITICAL
DRAM_TYPE:ELPIDA_2GB
ELPIDA,LVDDR3,1GBIT,7.5X10.6
333S0565
4
U3100,U3110,U3120,U3130
CRITICAL
CRITICAL
4
MICRON,LVDDR3,1GBIT,8X11.5
333S0554
U3300,U3310,U3320,U3330
DRAM_TYPE:MICRON_2GB
MICRON,LVDDR3,1GBIT,8X11.5
CRITICAL
4
333S0554
U3400,U3410,U3420,U3430
DRAM_TYPE:MICRON_2GB
337S3820
U1400
CRITICAL
1
MCP89U:A01
IC,MCP89U-A01,24.5MMX24.5MM,1244FCBGA
333S0553
4
DRAM_TYPE:SAMSUNG_2GB
SAMSUNG,LVDDR3,1GBIT,7.5X11.0
CRITICAL
U3100,U3110,U3120,U3130
337S3947
U1000
1
CRITICAL
PDC,SLGFN,PRQ,1,6,10W,R0,3M,BGA
CPU:1.6GHZ
337S3792
U1000
CPU:1.2GHZ
1
CRITICAL
CDC,QKWH,QS,1,2,10W,800,R0,1M,BGA
IC,MCP89U-A02,24.5MMX24.5MM,1244FCBGA
1
U1400
MCP89U:A02
CRITICAL337S3868
PDC,SLGAK,PRQ,1,4,10W,R0,3M,BGA
CPU:1.4GHZ
337S3954 CRITICAL
1
U1000
IC,MCP89U-A03,24.5MMX24.5MM,1244FCBGA
MCP89U:A03
U1400
1
CRITICAL337S3939
333S0553
SAMSUNG,LVDDR3,1GBIT,7.5X11.0
CRITICAL
4
U3400,U3410,U3420,U3430
DRAM_TYPE:SAMSUNG_2GB
MAGLAYERS AS ALTERNATE
152S0586
ALL
152S0847
IC ASSY,EFI,LOCKED,K99
341T0263 CRITICAL
1
BOOTROM:LOCKED
U6100
DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB
DDR3:MICRON_2GB
341T0261
U4900
1
IC ASSY,SMC EXTERNAL,K99
CRITICAL
SMC:PROG
ONSEMI AS ALTERNATE
377S0066377S0107
ALL
DP_ESD,DP_PWR:SMC,VFRQ:SLPS3,HVDDLDO:FIXED,MCPHVDD:P2V5,MCPPLL_R:REG,S0PGOOD_BJT,ISL6259_SCREENED:YES,DPI2C:SMC
K99_MISC
DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:MICRON_4GB
DDR3:MICRON_4GB
DRAM_CFG0:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB
DDR3:SAMSUNG_4GB
DRAM_CFG0:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB
DDR3:SAMSUNG_2GB
LPCPLUS
K99_DEVEL:PVT
K99_PROGPARTS
BOOTROM:UNLOCKED,SMC:PROG
COMMON,ALTERNATE,PROJ:K99,K99_MISC,MCP89U:A03,K99_DEBUG:ENG,K99_PROGPARTS,SPI:41MHZ,LVDDR3:YES,WLAN_PCTL:HW,IPD_5V:S5_INT,IPD_3V3:S5
K99_COMMON
DDR3:ELPIDA_2GB
DRAM_CFG0:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_2GB
CAPS:SS
SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF,SS_CAP_22UF
CAPS:MU
MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF,MU_CAP_22UF
CAPS:TY
TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF,TY_CAP_22UF
333S0557
MICRON,LVDDR3,2GBIT,9X11.5
CRITICAL
DRAM_TYPE:MICRON_4GB
4
U3400,U3410,U3420,U3430
U3300,U3310,U3320,U3330
333S0566
DRAM_TYPE:ELPIDA_4GB
CRITICAL
4
ELPIDA,LVDDR3,2GBIT,9X11.5
5 OF 110
4.4.0
051-8379
5 OF 73
Page 6
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
7/12/2010: Release 4.3.0 (MAJOR)-
- Page 4: Updated BOM options table with correct EEEEs for Elpida configs
- Page 4: Added label table with correct EEEEs for Elpida configs
- Page 5: Updated Elpida 2Gb configs with correct APN 333S0566
- Page 74: Deleted IMVP6_CS_P/N & IMVP6_CS_R_P/N nets from the constraints set as the
(2Gb APN is not ready yet- using 2Gb Micron APN as a placeholder)
- Page 97: Changed min neck width of PPBUS_SW_BKL to 0.25mm
05/19/2010: Release 3.3.0 (Major)-
- Page 76: Replaced Q7630 & Q7635 with APN 376S0895 (RJK03E0) per Dayu
- Page 73: Replaced Q7330 with APN 376S0749 (SIS426) per Dayu
- Page 72: Changed R7220 to 41.2K APN 118S0360 to boost 5V, per Dayu
- Page 72: Replaced Q7220 & Q7225 with APN 376S0895 (RJK03E0) per Dayu
- Page 70: Changed BOM OPTION attribute of U7000 to OMIT_TABLE
- PAGE 19: REMOVED R1955 PULL-UP ON MLB_RAM_CFG1 (INTERNAL PULL-UP)
- PAGE 78: ADDED BYPASS PROPERTIES TO C7895 AND C7896
- PAGE 72: RENAMED =P5VS3_EN_L TO =P5VS3_EN AND =P3V3S5_EN_L TO =P3V3S5_EN
03/05/2010: RELEASE 0.41.0 (MAJOR)-
Revision History
07/07/2010: Release 4.2.0 (MAJOR)-
these would get NOSTUFF’ed
Constraint (TDK)
OMIT_TABLE to NOSTUFF
<rdar://problem/8168390> K99 MLB BOM: Swap 155S0556-> 155S0578, fix 0402
- Page 5: Added DRAM_TYPE:ELPIDA_4GB BOM option to the Module Parts table
- Page 4: Added 12 new BOMs corresponding to Elpida 2GB and 4GB configs
- Page 5: Added DDR3:ELPIDA_4GB BOM group
<rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory
- Page 4: Updated Label table with correct EEEEs for SU9400 configs
- Page 4: Updated SU9400 BOMs with correct EEEEs (Elpida’s still pending)
<rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400
- Moved BOM group table on page 4 to page 5 for space limitations
<rdar://problem/7993210> K99 MLB: Cosmetic updates
<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
- Page 2: Updated CPU block to reflect 1.6GHz
<rdar://problem/7993210> K99 MLB: Cosmetic updates
05/21/2010: Release 3.4.0 (Major)-
- Page 69: Fixed netname =PP3V3_S3_DBGLEDs (= sign was missing)
- Page 4: Activated PROJ:K99 BOMOPTION to select proper APN for U9701
-Page 90: Added Q9090 isolation FET to support LCD panel power-down per
- PAGE 52: CONNECTED SMC 0 SMBUS INTERFACE TO THE TCON-A CHIP IN THE
- PAGE 108: ADDED SMBUS_SMC_0_S0_SCL/SDA_R CONSTRAINTS SET
- PAGE 78: MOVED P3V3S5_EN_L NET FROM PIN 4 TO PIN 3 (NON-INVERTING) AND
- PAGE 4: ADDED DRAM_CFG0:L TO RAM TABLES NOT CALLING OUT DRAM_CFG0:H, AND
- Page 52: Changed R5250 & R5251 with 2K APN 117S0052 to reduce rise time
<rdar://problem/8064296> K99 MLB: Change pull-up values for SMC 0 SMBus for TCON I2C
- Page 5: Added APN 377S0107 as an alternate for APN 377S0066 per GSM/CE
- Page 5: Added APN 155S0457 as an alternate for APN 155S0329 per GSM/CE
- Page 5: Added APN 376S0926 as an alternate for APN 376S0610 per GSM/CE
- Page 5: Added APN 155S0556 as an alternate for APN 155S0367 per GSM/CE
- Page 5: Added APN 138S0671 as an alternate for APN 138S0673 per GSM/CE
- Page 5: Added APN 107S0139 as an alternate for APN 104S0075 per GSM/CE
- Page 5: Added APN 104S0023 as an alternate for APN 104S0018 per GSM/CE
<rdar://problem/8065428> K99 MLB: Add alternates per GSM
parts and Alternate parts tables as space was limited
- Page 5: Deleted revision history and replaced it with BOM module parts, Programmable
<rdar://problem/7993210> K99 MLB: Cosmetic updates
- Page 110: Removed C1200-C1231 from 10uF caps BOM config table
C7360, C7361 and C9480 to these groups
Murata (138S0676) and Taiyo (138S0688). Also assigned C1200-C1231, C4902,
- page 110: Added BOM config table for 22uF caps for three vendors - Samsung (138S0635),
- Page 94: Added OMIT_TABLE BOM option to C9480
- Page 73: Added OMIT_TABLE BOM option to C7360 & C7361
- Page 49: Added OMIT_TABLE BOM option to C4902
vendor BOM group
- Page 4: Added SS_CAP_22uF, MU_CAP_22uF and TY_CAP_22uF BOM options for corresponding
<rdar://problem/8066033> K99 MLB BOM: Change CPU VCORE 0603 bypass caps for acoustics
ELPIDA_2GB BOM option
- Page 4: Added Elpida DRAM to the CFG table
- Page 5: Added Elpida 1Gb APN 333S0565 to the BOM module parts table with DRAM_TYPE:
- Page 4: Added DDR3:ELPIDA_2GB BOM group and set appropriate CFG bits
<rdar://problem/8065431> K99 MLB: Add new Elpida 1Gb memory APN - 333S0565
- Page 5: Added SU9400 1.4GHz APN 337S33954 to the BOM module parts table
- Page 4: Added 18 new EEEs corresponding to new BOMs
- Page 4: Added 18 new 639-XXXX BOMS corresponding to 1.4GHz SU9400 CPU
<rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400
06/06/2010: Release 4.1.0 (MAJOR)-
- Page 77: Added U7760 and surrounding circuits. BOM table need to replace later
- Page 54: Changed R5471 from 4.53K to 15k for higher PMON pin sink capability
<rdar://problem/7871918> K99 MLB: Investigate larger replacement for LCD backlight fuse
<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
- No changes since last release 3.6.0
- Page 50: Added PLACE_NEAR property on R5022 to ensure no stub in fallback case.
<rdar://problem/7794868> K99 MLB: Change to single USB port power switch
***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***
<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR)
- Page 25: Changed BOM table from ISL 353S2986 to MIC5366 353S2988, as Intersil is NOT
<rdar://problem/8027047> K99 MLB BOM: Swap 132s0247 w/132s0257, 138s0621 w/138s0653, 138s0635 w/138s0654
- Page 25,26: Swapped 138s0621 w/138s0653 as per GSM
- Page 31-34,37,49: Swapped 132s0247 w/132s0257 as per GSM
- Page 49,73: Swapped 138s0635 w/138s0654 as per GSM
- Page 75: Changed C7580 to 560pF APN 132S4001 per Intersil FAE
- Page 74: Renamed VSNS nets to VSEN to match page 100 constraints and deleted these
<rdar://problem/7795028> K99 MLB: 5V/3V3 power supply BOM changes per characterization
<rdar://problem/7993210> K99 MLB: Cosmetic updates
convention compliant power net
- Page 4: Replaced label APN 826-4393 with 825-7557
- Page 4: Changed SPI:62Mhz to SPI:41MHZ BOM option
- Proto 1+ OK2FAB Agile Release!!!
- PAGE 19: ADDED 10K R1954 APN 117S0007 PD ON MLB_RAM_CFG0 AS THERE IS NO
6/4/2010: EVT Agile Release 4.0.0 (FAB)*** EVT OK2FAB Agile Release ***
- Upcoming changes (Acoustic, Alternates) will be reflected in 4.1 major release, which
will match Quanta’s deviations for EVT
<rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change
- Page 78: Swapped unused gate to Q7890 and SMC_Adapter_En fet to Q7891.
- This release matches Quanta’s official BOM for EVT build
- Page 4: Deleted 138S0635 from alternate table as it’s been replaced per GSM(see below)
<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR)
05/28/2010: Release 3.6.0 (Major)-
to GND and, U7840.4 output to P3V3S5_EN_L
<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep
<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
it with actual POR APN 138S0673 symbol. Also, deleted it from
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
- PAGE 78: ALIASED =P0V9S5_EN TO CONNECT TO =PP3V3_S5_P0V0S5
- PAGE 78: DELETED Q7891 (PINS 3,4,5) SYMBOL AS P5VS3_EN_L IS ACTIVE HIGH
SIGNAL (SO NO NEED TO INVERT) AND RENAMED IT TO P5VS3_EN. ALSO,
RENAMED IT TO P3V3S5_EN AS IT IS ACTIVE HIGH SIGNAL. LEFT PIN 4
<rdar://problem/8033353> K99 MLB: Change to dual USB port power switch
<rdar://problem/7744955> K99 Proto0 Task: Characterize Voltage/Current/Temperature
<rdar://problem/8033256> K99 MLB: Implement 3V3 S5 bleed resistor to satisfy IPD Cumulus
- Page 77: Fixed BOM table attribute to attach BOM option value to TBL_BOMOPTION
from PP3V3_S3_WLAN**
** Didn’t sync page 40 as K16 needs to sync it first from K99 to remove neck width
** Didn’t sync page 52 as K16 need to sync it first from K99 to remove accelerometer**
***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***
05/26/2010: Release 3.5.0 (Major)-
- Page 49: Changed port P94 from SMC_DP_HPD_L to PM_SLP_S4_L
- Page 49: Changed port P92 from SMC_BS_ALRT_L to SMC_PME_S4_L
- Page 97: Deleted OMIT_TABLE BOM option attribute from C9797 and replaced
-Page 108: Added constraints for new nets on page90, I2C_TCON_SCL/SDA_CONN
-Page 97: Reversed previous change, U9701 back to 353S2896, handled via a
- Page 97: Swapped pins of R9700 to match original orientation before
3/31/2010: Proto 1+ Release 2.1.0 (MAJOR)
- Page 108: Changed Therm, Sense, Audio line-to-line spacing to 1:1 instead of 2:1
<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements
connected R7899 to pin 3 of Q7890; Q7890.5 gate tied to P3V3S5_EN_L; Q7890.4
- Page 54: For IN1C, change R5412 to 118 Ohms, APN : 114S0127
** Didn’t sync pages 79 & 99 as K16 need to sync it first from K99 to fix OMIT_TABLE
- Page 52: Added notes about I2C addresses on panel, may not be 100% accurate yet
***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16***
- Page 78: Added R7899 0ohm 0603 (will change later) pull-up to =PP3V3_S5_REG and
- Page 76: Cleaned-up page, including correcting application of two PLACE_NEAR
properties and changing an OMIT to OMIT_TABLE
<rdar://problem/8036605> K99 MLB BOM: Implement MCP VCORE characterization changes
power sequencing on shutdown
Sensors
- Page 4: Deleted ZS0904 entry from the module parts table as symbol is ready
- PAGE 4: ADDED APN 376S0895 UNDER MODULE PART TABLE FOR Q7220 & Q7225 PER
- PAGE 4: DELETED MODULE TABLE ENTRY FOR ZS0907 AS POR SYMBOL IS READY
- PAGE 78: REPLACED R7813 WITH 0 OHMS APN 117S0002 FOR NOW
POR
353S2986 with 353S2988, making TI its alternate
-Page 4: Removed MIC5366 from alternate BOM table as it is primary now and replaced
<rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout
- Page 9: Replaced ZS0904 with actual symbol for APN 870-1940 and deleted OMIT_TABLE
- Page 74: Changed C7451/C7452 to same APN 131S0287 as C7237/C7239 for BOM consolidation
- Page 46: Changed USB port power switch U4690 back to dual port TPS2052B APN 353S2298
_ Page 53: For IZDM, change U5360 to INA210 (APN : 353S2073)
- Page 4: Deleted APN 353S3047 entry from the alternate table
- Page 25: Replaced APN 353S3048 with 353S2986 in the BOM table for U2590 as primary
***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***
** Didn’t sync page 52 as K16 need to sync it first from K99 to remove accelerometer**
** Didn’t sync page 25 as K16 need to sync it first from K99 to revert to 2.5 LDO**
** Didn’t sync page 40 as K16 needs to sync it first from K99 for above change**
<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements
- Page 24: Changed PPVCORE_SW_MCP_GFX min neck width to 0.12mm for routing
<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V
<rdar://problem/7851979> K16/K99: Set SPI operating frequency to 42Mhz
<rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO
- Page 47: Connected pin 38 to GND
<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V
- Page 4: Added APN 353S2988 (MICREL) as an alternate for 353S2986
- Page 4: Added APN 353S2987 (TI) as an alternate for 353S2986
- Page 25: Reverted U2590 back to the 2.5 LDO APN 353S2988
for HVDDLDO:FIXED
<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
- Page 77: Changed IPD_PWR:S5 to IPD_5V:S5_EXT BOM option
- Page 77: Changed IPD_PWR:S3 to IPD_5V:S3 BOM option
IPD 5V supply. Added BOM option IPD_5V:S5_INT to R7761
<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep
- Page 57: Changed IPD_PWR:S3 to IPD_3V3:S3 BOM option
- Page 78: Removed =USB_TPAD_MUX_EN alias to DDREG_EN as MUX has been removed
- Page 19: Added alias for PM_SLP_S4_L to PM_SLP_S5_L
- Page 49: Changed port P95 from PM_SLP_S4_L to PM_SLP_S5_L
- Page 50: Removed R5095 PU resistor on SMC_PB6
Flex
switcher for IPD 5V supply
- Page 7: Renamed =PP3V3_S3_TPAD to PP3V3_TPAD_CONN and =PP5V_S3_TPAD TO PP5V_TPAD_FILT
- Page 8: Added =PP3V3_SMC_PME alias to PP3V3_S5
<rdar://problem/8009884> K99 MLB: Add new CPU APN for U1000
- Page 4: Added SU9600 CPU APN 337S3947 1.6GHz to the module part table. And, updated
BOM variant table to call out this new APN
<rdar://problem/8011930> K99 MLB: Remove SIL BOM option as SIL is not POR
- Page 4: Removed SIL BOM option from the development BOM
- Page 8: Changed min neck width of PP3V3_S3 to 0.1mm
- Page 40: Deleted line/neck width attributes from =PP3V3_S3_WLAN as duplicates
CONNECTED IT TO PM_SLP_S4_L VIA RC NETWORK - R7813 & C7813
- PAGE 4: ADDED MODULE TABLE ENTRY FOR Z0920 MLB STIFFENER: 806-1176
- Page 7: Renamed PP3V3_S0_DPPWR to PP3V3_SW_DPPWR to match page 94 changes, making it
- Page 49: Changed port PB6 from SMC_PB6 to SMC_DP_HPD_L
<rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state
- Page 57: Renamed pin 10 to PP5V_TPAD_FILT
- Page 57: Renamed pins 5 & 6 to USB_TPAD_CONN_P/N as before
- Page 57: Removed U5750, R5751,R5750 and C5750 USB_IPD Debug Mux as it is not needed
- Page 57: Changed IPD_PWR:S5 to IPD_3V3:S5 BOM option
- Page 50: Changed R5076 to a PU to =PP3V3_SMC_PME. And, renamed SMC_BS_ALERT_L to
SMC_PME_S4_L
- Page 77: Added place near J5700.10:1.5mm to R7761 to avoid long stub
- Page 77: Added R7761 0 ohm bypass option to use internal LDO of 5V/3.3V switcher for
<rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout
- Page 52: Deleted Accelerometer block from the SMBUS page
<rdar://problem/7993210> K99 MLB: Cosmetic updates
- Page 8: Added =PP3V3_S3_DBGLEDS alias to =PP3V3_S3_FET for debug LEDS (like K16)
- Page 57: Changed PP3V3_S5_TPAD_CONN to PP3V3_TPAD_CONN
- Page 4: Deleted SMS:NO BOM option as SMS has been removed
- Page 50: Deleted BOM option SMS:NO from R5093
<rdar://problem/8007333> K99 MLB: Stuff R7872 to enable output connection of ISL power
- Page 78: Added BOM option S0PGOOD_ISL to R7872
03/30/2010: Release 1.5.0 (MAJOR)-
- PAGE 9: ADDED Z0920 (OMIT) APN 998-3068 METAL TAB SYMBOL FOR MDP
- PAGE 39: REMOVED CRITICAL ATTRIBUTE FROM THE BOM TABLE AS IT IS NOT
- PAGE 72: CHANGED R7246 AND R7247 TO 1.69K, 1% APN 118S0134 PER VENDOR
- PAGE 4: UPDATED MICRON 2GB APN 333S0557 IN THE BOM TABLE
- Page 77: Changed R7751 to 2.55K APN 118S0234 & R7752 to 20K APN
- Page 97: Stuff C9799
<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements
- Page 8: Changed min neck width of PP3V3_S3 to 0.1mm
- Page 8: Changed min neck width of PP5V3_S3 to 0.2mm
bottom of the page
<rdar://problem/7993210> K99 MLB: Cosmetic updates
- Page 69: Changed BOM OPTION attribute of C6999 to OMIT_TABLE
- Page 69: Changed BOM OPTION attribute of U6955 to OMIT_TABLE
Dayu
- Page 14: Swapped BCLK_IN_N/P after library symbol refresh
- Page 17: Added CKPLUS_WAIVE properties to VDD_IFPx pins that are legally
- Page 19: Removed PM_SLP_S5_L alias. Other cleanup to make all CRefs
- Page 19: Removed pull-up on MLB_RAM_CFG1 (internal pull-up), changed
pull-down to 470 ohms. Added pull-down on MLB_RAM_CFG0, made
both pull-up and pull-down 10K
- Page 25: Added MCPHVDD LDO, SC-70 version. Added 1uF 0201 input cap and
10K pull-up resistor, BOMOPTIONed same as LDO. L2590 retained
grounded on K16
visible
DRIVEN FROM MCP89 0 SMBUS [R5240-R5243 APN 117S0002] PER
IDEA IS TO PULL THIS NET TO S5 RAIL WHEN SMS IN NOT STUFFED,
- NON-FUNCTIONAL PROTO 1 OK2FAB RELEASE!!!
- PAGE 76: CHANGED R7641 AND R7642 TO 1.78K, 1% APN 118S0144 PER VENDOR
- PAGE 72: ADDED OMIT BOM OPTION TO Q7220 & Q7225 AS SYMBOL IS NOT READY
- Proto 1 Ok2FAB Agile Release!!!
- Page 25: Changed BOM OPTION attribute of C2600 to OMIT_TABLE
- Page 9: Changed BOM OPTION attribute of ZS0904 to OMIT_TABLE
Proto 1
between high & low side FETs, per Dayu
- Page 4: Changed BOM OPTION SPI:25MHz to 62MHz
- Page 52: Changed R5290 & R5291 to 2K APN 118S0174 per RADAR# 7810865
Dayu
- Page 14-20: Changed BOM OPTION attribute of U1400 to OMIT_TABLE
- Page 10-11: Changed BOM OPTION attribute of U1000 to OMIT_TABLE
- Page 4: Deleted DPI2C:SMC BOM OPTION as eDP I2C Bus won’t be routed on
- Page 4: Deleted 376S0895 alternate part entry to avoid mixing of vendors
RADAR 7749046
NEEDED
INTERNAL PD ON GPIO 48
OPTION ATTRIBUTE SMS:YES PER RADAR 7765442
APN 117S0103
with MCPHVDD:P3V3 BOMOPTION
- Page 25: Added voltage divider for HVDD LDO. OMIT_TABLE’d U2590, added
to PM_SLP_S4_L
- Page 49: C4902 changed from 0805 to 0603 to free up some layout space for
MCP VCore regulator
including deleting unused alias for SMC_PB3
BOMOPTION of DP_PWR:S0
- Page 53: Removed PP prefix from non-power nets. Added OMIT_TABLE to
C5310 for vendor control
- Page 59: Sync’ed with K99 (adds R5924, S3 pull-up on SMS_INT_L), plus
lots of cleanup including removing PP prefix from signal net,
are active-high
original net
left indicated as unused. Removed inverter from P5VS3_EN and
Added BYPASS properties to C7895 and C7896. Changed base net
for PM_SLP_S4_DLY_L
- Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned up
page, adding offpages, fixed grid issues, made power nets
convention-compliant and added note about DP_CA_DET pull-up /
FET Vgs reqirements
- Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned up
convention-compliant and added note about DP_CA_DET pull-up /
pins
common-mode chokes and cosmetic changes
report (except for 4 false errors). Other cleanup including
removing some unnecessary net properties
page, adding offpages, fixed grid issues, made power nets
FET Vgs reqirements
- Page 94: Renamed DP_PWR nets to indicate ’SW’ state instead of ’S0’.
3.3V S5 rail. Cleaned up page including fixing grid issues.
reconnected P3V3S5_EN to be non-inverted. R7813 changed from
pull-up to series R (0-ohms). P0V9S5_EN changed to alias to
- Page 4: Updated EEE numbers
between 18 BOMs
added
- Page 72: Changed C7237, C7239 to 100pF, 10% APN 131S0287 per Dayu
- Page 97: Replaced U9701 with new improved E00 version APN 353S2967
- Page 97: Changed R9704 to 33 ohms APN 117S0080 per Kiran
- Page 97: Stuffed C9704 per Kiran
- Page 39: Removed CRITICAL flag from 0-ohm resistor table
tables for fixed (2.5V Intersil) and adjustable (TI) regulators
- Page 49: PB3 changed from SMC_DRAM_S3_PWRDN to SMC_SLPS5_L. P74 changed
from PM_SLP_S4_L to SMC_DP_HPD_L. P75 changed from PM_SLP_S5_L
- Page 50: Added SMS:NO BOMOPTION to SMS_INT_L pull-up. Other cleanup
- Page 50: Added 2 resistors to control DP_PWR and one to connect
DP_EXT_HPD_L to SMC. Updated netname on R5090 and added
- Page 52: Added TCON I2C block and R’s to connect to SMC 0 and MCP 0
buses. Other cosmetic cleanup including grid compliance
correcting BYPASS & PLACE_NEAR properties, correcting offpages,
- Page 76: Value changes to R7641/R7642 and OCP note correction per Dayu
Changed C7288 to match C7218. Removed alias that was serving no
- Page 72: Value changes to C7237/C7239/R7216/R7246/R7247/R7256 per Dayu.
etc
- Page 72: Changed Q7220 & Q7225 to 376S0895 per Dayu’s request. Fixed
netnames on switcher enables, removing _L suffixes since they
purpose and was incorrect since it lacked a MAKE_BASE anyhow
- Page 78: Removed RAM power-down circuit, reconnecting =DDRREG_EN to
- Page 78: Disconnected half of Q7891 from 5V S3 power sequencing, gate
corresponding to this new sub-BOM consisting of common parts
to fix USB short issue
- Page 54: Changed R5418 to 4.53K 0201 APN 118S0384
- Page 72: Changed R7246, R7247 to 1.87K, 1% APN 118S0159 per Dayu
- Page 72: Changed C7236, C7238 to 0.01uF, 10% APN 132S0097 per Dayu
- Page 72: Changed R7216, R7256 to 3.16K, 1% APN 118S0289 per Dayu
- Page 54: Changed R5471 to 4.53K 0402 APN 114S0281
- Page 46: Changed BOM attribute OMIT to OMIT_TABLE for C4690 & C4695
CAPS:SS/MU/TY
deleted OMIT
duplicated on page 72
- Page 4: Replaced K99_SS/MU/TY_CAP BOM option with better nomenclature -
- Page 4: Fixed DRAM CFG table - swapped CFG 1 and 0 columns
- Page 4: Pulled new 607-XXXX APN and added K99_CMNPTS BOM option
- Page 4: Replaced K99_COMMON with K99_CMNPTS in the BOM variant table
- Page 4: Removed K99_ prefix from K99_DDR3_ BOM Group
- Page 4: Deleted 376S0895 APN module parts table entry as it is already
- Page 4: Deleted module table entry for 806-1176 as actual symbol has been
3/26/2010: Release 1.4.0 (MAJOR)-
- Page 4: Added 376S0895 as an alternate for 376S0749 per Dayu
- Page 4: Added 138S0681 as an alternate for 138S0638 per GSM
- Page 4: Added 138S0676 as an alternate for 138S0635 per GSM
- Page 4: Removed alternates that were NA to K99
- Page 72: Deleted OMIT_TABLE attribute from Q7220 & Q7225. Also deleted
the BOM table. Plan is to use 376S0895 as alternate instead
03/25/2010: Release 1.3.0 (MAJOR)-
- Page 61: Changed BOM OPTION attribute of U6100 to OMIT_TABLE
- Page 49: Changed BOM OPTION attribute of U4900 to OMIT_TABLE
- Page 35-36: Changed BOM OPTION attribute of all caps to OMIT_TABLE
- Page 31-34: Changed BOM OPTION attribute of U3100-U3430 to OMIT_TABLE
138S0672 to improve noise immunity & reduce inrush stress, per
- Page 69: Changed R6905 to 10 Ohms APN 101S0089 & C6990 to 2.2uF APN
3/31/2010: Proto 1+ Release 2.2.0 (MAJOR)
***Sync’ed from K16***
03/31/2010 - Proto 1 Agile Release 2.0.0 (FAB)
- Page 93: Added CKPLUS_WAIVE properties to _P nets connecting to FET DRAIN
per radar 7761747
table now to support/clarify different values for K16/K99
radar 7761747
5/12/2010: Proto 1+ Agile Release 3.0.0 (FAB)
syncing with K16
Switch input changed from PM_SLP_S3_L to =DP_PWR_EN. HPD_L
netname changed, offpage added and pull-up changed to DP_PWR.
Other cleanup including removing PLACE_NEARs that should be
handled via constraints, OMIT_TABLEs for caps, CRITICAL flags on
- Page 108: Added net constraints for diffpairs reported by diffpNoPhysNet
INTERNAL DISPLAY. ALSO, PROVIDED 0 OHMS STUFFING OPTIONS TO BE
- PAGE 50: ADDED BOM OPTION ATTRIBUTE SMS:NO TO R5093 PU ON SMS_INT_L.
- PAGE 4: REMOVED SMS_YES BOM OPTION FROM K99_DEVEL:ENG BOM GROUP. INSTEAD,
RESPECTIVELY PER RADAR 7749046
- PAGE 59: ADDED 10K R5924 PU ON SMS_INT_L TO =PP3V3_S3_SMS WITH BOM
- Page 4: Added APNs 353S2987 & 353S2988 as alternates for 353S2986
<rdar://problem/7964678> K99 MLB BOM: Change MCP APN to A03 version
- Page 4: Added MCP89U:A03 BOM table. Changed K99_Common to call out A03
<rdar://problem/7861271> K99 MLB: Set SPI operating frequency to 42MHz
<rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change
- Page 4: Added WLAN_PCTL:HW to K99_Common
<rdar://problem/7953783> K99 IPD power regulator new design
- Page 4: Added IPD_PWR:S5 to K99_Common
- Page 8: Aliased =PPBUS_5V_S5 to PPBUS_G3H signal
<rdar://problem/7825507> K99 MLB BOM: Change label P/N
<rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector
convention compliant power net
- Page 7: Renamed PP3V3_LCDVDD_SW_F to PP3V3_SW_LCD to match page 90, making it
- Page 7: Removed SYS_LED_ANODE_R
- Page 8: Added =PP3V3_S5_TPAD to PP3V3_S5 net
- Page 59: Deleted csa page as SMS is no longer POR
<rdar://problem/7993241> K99 MLB: Cleanup of CheckPlus warnings/errors
- Page 9: Renamed stiffener Z0920 to MT0900, similar to K16
- Page 9: Cleaned-up TP/NC _P/_N errors
nets from constraints table on the same page
attribute as mentioned above**
<rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector
<rdar://problem/7993210> K99 MLB: Cosmetic updates
- Page 13: Changed XDP SMBus nets to =I2C_XDP_* for new aliases on page52
- Page 52: Added XDP to MCP_0 SMBus diagram
<rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state
- Page 46: Corrected Refdes from Q4690 to U4690
<rdar://problem/7993278> K99 MLB: Schematic sync with K16 MLB
- Page 26: Sync’ed with K16, OMIT changed to OMIT_TABLE
- Page 73: Sync’ed with K16, OMITs changed to OMIT_TABLE and cosmetic clean-up
- Page 10: Added Need_TP=True attribute to pin E37 & D40
<rdar://problem/7871167> K99 MLB: Change RC on CPUVCORE PMON output
- Page 54: Changed C5470 from 0.22UF to 68nF 10%. Only one in the library
- Page 23: Changed Q2300 from 376S0868 to 376S0912
- Page 77: Added min line and neck width properties to PP5V_S5_LDO
- Page 78: Aliased =P5V_S5_EN to =P5V3V3_REG_EN
- Page 78: Added R7846 and C7846 0ohm 0.47F (NO STUFF) stuffing options
<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep
- Page 57: Added R5730 & R5731 for power switch on PP3V3_TPAD
- Page 57: Added U5750 USB Mux
- Page 57: Added R5751 (NO STUFF) to bypass U5750 MUX
- Page 78: Added =USB_TPAD_MUX_EN to DDRREG_EN
<rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request
- Page 39: Added Critical attribute to U3920, U3940
- Page 54: Added Critical attribute to Q5401,U5413
5/17/2010: Release 3.1.0 (Major)-
- PAGE 9: REPLACED ZS0907 WITH POR APN 870-1938 AND DELETED OMIT ATTRIBUTE
REMOVED DRAM_CFG1:H AS IT IS NO LONGER NEEDED
- PAGE 78: NO STUFF C7801
NC
CONNECTOR
03/05/2010: RELEASE 0.42.0 (MAJOR)-
- PAGE 72: CHANGED C7237 AND C7239 TO 1000PF, 10% APN 132S0122 PER VENDOR
<rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state
- Page 8: Removed =PP3V3_S5_PWRCTL alias
- Page 9: Tagged POGOS and MT0900 as CRITICAL
- Page 79: Changed OMIT associated with C7980 to OMIT_TABLE
<rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request
- Page 75: Added Critical attribute to R7560
- Page 99: Changed OMIT associated with all caps to OMIT_TABLE
- Page 97: Added Critical attribute to R9700
<rdar://problem/7994057> K99 MLB: Need to add Need_TP=True property to CPU
<rdar://problem/7934374> K99 MLB BOM: Replace 376S0868 with 376S0912
- Page 78: Added BOM Options WLAN_PCTL:HW to Q7891 both halves
- Page 78: Added R7891 0 ohm 5%
- Page 78: Added Bom option WLAN_PCTL:SW to R7891
- Page 77: Added R7760 for switching capability
- Page 57: L5720.2 now connects to PP5V_S5_LDO
<rdar://problem/7953783> K99 IPD power regulator new design
<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
- Page 98: Changed F9800 to 0603 package APN 740S0115
- Page 98: Added Critical attribute toF9800
- Page 77: Removed Critical from C7710, C7715
- Page 46: Replaced Q4690 with single port switch APN 353S1930 (Higher DCR)
- Page 9: Replaced Z0920 with POR stiffener symbol for APN 806-1176 and
<rdar://problem/8006037> K99 MLB: Change RC Filter Values on AMON, and BMON
- Page 54: Changed R5481 to 150K APN 118S0106 and C5487 to 0.0068uF APN 132S0009
- Page 54: Changed R5401 to 300K APN 118S0276 and C5490 to 0.0033uF APN 132S0049
<rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO
- Page 47: Replaced J4700 with new POR connector APN 516S0862
Flex
- Page 4: Deleted APN 353S2988 entry from the alternate table
<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V
- Page 25: Replaced U2590 with 2.85V LDO APN 353S3048 (MICREL)
- Page 4: Replaced APN 353S2987 entry with APN 353S3047 (TI) as an alternate
- Page 25: Replaced APN 353S2986 with 353S3048 in the BOM table too for HVDDLDO:FIXED
<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep
<rdar://problem/8004981> K99 MLB: Connect eDP SMBUS interface to SMC SMBUS 0
- Page 57: Connected a new PME signal SMC_PME_S4_L to pin 2
- Page 4: Added BOM option DPI2C:SMC to stuff R5242 & R5243
5/19/2010: Release 3.2.0 (Major)-
- PAGE 9: REPLACED POGO PIN ZS0906 WITH APN 870-1938 PER PD
- PAGE 19: REPLACED R1957 WITH 10K APN 117S0007 TO BE CONSISTENT
118S0175 to improve noise immunity & reduce inrush stress, per
monitor to ALL_SYS_PWRGD
- PAGE 19: CHANGED R1956 PULL-DOWN TO 470 OHMS (STRONGER PD VS 8.5K PU)
- PAGE 78: CHANGED BASE NET FOR PM_SLP_S4_DLY_L PER WILL
03/05/2010: RELEASE 0.43.0 (MAJOR)-
- PAGE 2: REPLACED THIS PAGE WITH QUANTA’S UPDATED ONE
- PAGE 4: SWITCHED BOM TABLE TO USE SCREENED ISL6259 PART
- PAGE 4: MOVED SMS_YES BOM OPTION FROM K99_MISC TO DEVEL_BOM
- PAGE 9: FIXED MCPCOREISNS SIGNALS ALIASES PER WILL’S CHANGES ON K16
- PAGE 70: NO STUFF Q7080, D7005,Q7055 AND F7040 FOR NON-FUNCTIONAL BOARD
- PAGE 76: CHANGED OCP TEXT NOTE PAR VENDOR
- PAGE 78: ADDED NC SYMBOL TO PIN 5 OF U7896
03/07/2010: PROTO1 NON-FUNCTIONAL AGILE RELEASE 1.0.0 (FAB)-
3/19/2010: RELEASE 1.1.0 (MAJOR)-
ADDED SMS:NO TO K99_MISC [ALSO SEE BELOW CHANGES FOR PAGES 50,59]
ELSE PU TO S3 RAIL (PAGE 59) PER RADAR 7765442
- PAGE 59: REPLACED BOM OPTION SMS_YES WITH SMS:YES
- PAGE 70: STUFF BACK Q7080, D7005,Q7055 AND F7040
to OMIT_TABLEs and performed other cleanup
- Page 12: Fixed invisible pins on CPU bypass caps. Also changed all OMITs
release. Below list depicts all the changes since 3/1 K16 release *
*Please NOTE that some of the below changes were already part of 1.1
***Sync’ed ALL but pages 1-9,28,47,69,70,74,75 and 97 from K16***
- Page 90: After syncing, renamed PP3V3_S5_LCD to PP3V3_S0_LCD
- Page 12: After syncing from K16, deleted C1273 as it NA to K99
- Page 7: Added =I2_TCON_SCL/SDA FCTs under INT DP FUNC_TEST group
- Page 8: Moved PP3V3_S0_LCD & PP3V3_S5_DP_PORT_PWR to S5 rail
- Text sizes have been fixed - safe to sync
03/24/2010: Release 1.2.0 (MAJOR)-
RADAR 7742010
- PAGE 93: ADDED 3300PF APN 132S0241 C9302 CAP ON DP_CA_DET TO GND PER
- PAGE 90: ROUTED NEWLY ADDED =I2C_TCON_SDA/SCL TO PINS 1 & 30 OF J9000
- PAGE 75: REPLACED L7560 WITH 10X10X3MM APN 152S1236 PER RADAR 7769386
- Page 8: Renamed PP3V3_S5_LCD to PP3V3_S0_LCD
syncing from K16
- Page 97: Changed BOM OPTION attribute of C9797 to OMIT_TABLE after
DAYU FOR PART SUPPLY ISSUE
- PAGE 72: CHANGED R7216 AND R7256 TO 4.02K, 1% APN 118S0354 PER VENDOR
BOM table as it is no longer required
- Fixed typo in APN (first column)
<rdar://problem/7825507> K99 MLB BOM: Change label P/N
<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements
<rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory
- Page 90: Changed FL9000, FL9001 from 155S0423 to 155S0559
- Page 9: Deleted CRITICAL attribute from MT0900 and NOSTUFF’ed it
<rdar://problem/8180364> K99 MLB BOM: Remove 806-1176 stiffener
- Page 4: Added IPD_3V3:S5 BOM option under K99_COMMON to select 3.3V S5 power supply
<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep
- Page 4: Changed IPD_PWR:S5 to IPD_5V:S5_INT BOM option to use internal LDO of 5V/3.3V
- Page 110: Removed caps listed above on page 12 from the BOM table as
- Page 94: Changed FL9400-FL9403 from 155S0423 to 155S0559
***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16***
C1219, C1220,C1221,C1222,C1224,C1225,C1228,C1229,C1231 from
C1205,C1206,C1207,C1208,C1209,C1211,C1212,C1213,C1215,C1216,
- Page 12: Changed BOM option attribute of C1200,C1201,C1202,C1203,C1204,
<rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps
alternate parts
- Page 5: Changed 155S0556 to 155S0578 to address the 0603 0402 mismatch
pad with 0603
<rdar://problem/8007524> K99 MLB: Stuff C9799 to provide better phase margin
- Page 69: Renamed PP3V3_S3 going to debug LEDs to =PP3V3_S3_DBGLEDS
<rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps
<rdar://problem/8118512> K99 MLB BOM: Swap 155S0423 -> 155S0559, Supply
<rdar://problem/8175202> K99 MLB: Move MCP Temp Sensor to SMC B SMBUS
- Page 52: Move MCP TEMP I2C connections to SMC B Bus
- Page 52: NOSTUFF’ed R5250 & R5251
- Page 52: Changed MCP TEMP I2C address note to reflect 0XD8/0XD9
- Page 55: Changed R5536 to 15K APN 118S0105 to set ADDR = 0XD8/0XD9.
Updated schematic note too for address
<rdar://problem/8141673> K99 MLB: Change eDP connector J9000 pinout
- Page 90: Changed pine 2 to NC and connected pin 4 to PPVOUT_SW_LCDBKLT
<rdar://problem/8224515> K99 MLB: Remove Q9090 isolation FET
- Page 90: Removed Q9090 FET and directly connected TCON I2C bus J9000
- Page 90: Deleted =I2C_TCON_SCL/SDA_CONN net names and kept
=I2C_TCON_SCL/SDA
<rdar://problem/8224857> K99 MLB: Replace APN 155S0559 with 155S0423
- Page 90: Changed FL9000 and FL9001 back to the original APN 155S0423
(incompatible pad sizes)
- Page 94: Changed FL9400-FL9403back to the original APN 155S0423
<rdar://problem/8224921> K99 MLB: Change R9714 (BKLT_ISET) resistor to
18.2K 1% APN 118S0155
- Page 97: Change R9714 to 18.2K 1% APN 118S0155
<rdar://problem/7993210> K99 MLB: Cosmetic updates
- Page 97: Fixed schematic note - I_LED=369/Riset
7/22/2010: Release 4.4.0 (MAJOR)-
SYNC_DATE=01/19/2009
SYNC_MASTER=K24_MLB
Revision History
6 OF 110
4.4.0
051-8379
6 OF 73
Page 7
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(NEED TO ADD 5 GND TP)
(NEED TO ADD 5 GND TP)
SPEAKER FUNC_TEST
(NEED TO ADD 27 GND TP)
(NEED TO ADD 6 GND TP)
Fan Connectors
(NEED TO ADD 1 GND TP)
(NEED TO ADD 6 GND TP)
AIRPORT / BT
DEBUG VOLTAGE
FSB SIGNALS WITH NOTEST
(NEED 2 TP)
(NEED 2 TP)
(NEED 6 TP)
LIO CONNECTOR
(NEED TO ADD 4 GND TP NEAR J6950 AND 1 FOR SHIELD)
(NEED 4 TP)
(NEED 2 TP)
DC POWER CONN
Functional Test Points
LCP + SPI CONN
(NEED 5 TP)
BATT POWER CONN
SATA HDD
(NEED TO ADD 8 GND TP)
(NEED 6 TP)
(NEED TO ADD 6 GND TP)
HALL EFFECT CONN (PLACEHOLDER)
INT DP FUNC_TEST
(NEED TO ADD 5 GND TP)
IPD_FLEX_CONN
I12
I15
I16
I228
I230
I246
I247
I248
I249
I251
I252
I253
I254
I255
I256
I257
I259
I260
I261
I305
I313
I314
I315
I317
I318
I319
I320
I321
I322
I455
I456
I479
I480
I488
I489
SYNC_MASTER=K6_MLB
FUNCTIONAL TEST
SYNC_DATE=12/11/2009
=PP5V_S3_LIO_CONN
TRUE
TRUE
PP5V_S3
TRUE
=PP3V3_S3_BT
PP5V_TPAD_FILT
TRUE
TRUE
PP3V3_S3
TRUE
FAN_RT_PWM
TRUE
PP5V_S0
FAN_RT_TACH
TRUE
SMC_TPAD_RST_L
TRUE
SMC_PM_G2_EN
TRUE
PM_SLP_S4_L
TRUE
PP0V9_ENET
TRUE
PM_SLP_S3_L
TRUE
PPVOUT_SW_LCDBKLT
TRUE
TRUE
PPBUS_G3H
PP3V3_S5
TRUE
PP3V42_G3H
TRUE
TRUE
PP5V_S0
PP3V3_S0
TRUE
TRUE
PPVCORE_S0_CPU
PPVCORE_S0_MCP
TRUE
PP1V05_S0
TRUE
PP1V5_S0
TRUE
PPBUS_G3H_ISNS
TRUE
PP5V_S3_RTUSB_A_F
TRUE
PP3V3_SW_DPPWR
TRUE
PP3V3_ENET
TRUE
TRUE
PP3V3_S0_HDD_R
PP3V3_WLAN_F
TRUE
PP0V9_S5
TRUE
SMC_TDI
TRUE
LPC_PWRDWN_L
TRUE
TRUE
AUD_I2C_INT_L
LPC_SERIRQ
TRUE
TRUE
SMC_BC_ACOK
TRUE
=PP3V42_G3H_ONEWIRE
TRUE
SMC_LID_R
TRUE
PCIE_AP_D2R_P
SMC_TCK
TRUE
LPCPLUS_GPIO
TRUE
AP_CLKREQ_Q_L
TRUE
AP_RESET_CONN_L
TRUE
PCIE_WAKE_L
TRUE
USB_TPAD_CONN_N
TRUE
TRUE
=I2C_TPAD_SCL
TRUE
PCIE_CLK100M_AP_P
TRUE
USB_BT_P
TRUE
PCIE_AP_D2R_N
TRUE
SMBUS_SMC_BSA_SDA
USB_CAMERA_P
TRUE
SATA_HDD_R2D_N
TRUE
TRUE
SMC_HDD_OOB_TEMP
SATA_HDD_D2R_C_N
TRUE
TRUE
SATA_HDD_D2R_C_P
NO_TEST=TRUE
FSB_ADS_L
NO_TEST=TRUE
FSB_ADSTB_L<1..0>
NO_TEST=TRUE
FSB_D_L<63..0>
NO_TEST=TRUE
FSB_DSTB_L_P<3..0>
FSB_LOCK_L
NO_TEST=TRUE
FSB_HITM_L
NO_TEST=TRUE
NO_TEST=TRUE
FSB_REQ_L<4..0>
TRUE
=PP3V3_S5_LPCPLUS
PM_CLKRUN_L
TRUE
SMC_TMS
TRUE
LPCPLUS_RESET_L
TRUE
SMC_TRST_L
TRUE
LPC_CLK33M_LPCPLUS
TRUE
SPI_ALT_CLK
TRUE
SPI_ALT_CS_L
TRUE
SMC_TX_L
TRUE
SYS_DETECT_L
TRUE
PPVBAT_G3H_CONN
TRUE
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SPKRAMP_INR_N
USB_EXTD_P
TRUE
USB_EXTD_OC_L
TRUE
TRUE
=PP3V3_S0_AUDIO
TRUE
DP_INT_AUX_CH_C_N
NO_TEST=TRUE
FSB_DSTB_L_N<3..0>
FSB_HIT_L
NO_TEST=TRUE
NO_TEST=TRUE
FSB_DINV_L<3..0>
FSB_A_L<35..3>
NO_TEST=TRUE
=I2C_LIO_SCL
TRUE
TRUE
SPIROM_USE_MLB
TRUE
=I2C_MIKEY_SDA
PCIE_AP_R2D_P
TRUE
TRUE
PCIE_CLK100M_AP_N
DP_INT_HPD_CONN
TRUE
TRUE
PCIE_AP_R2D_N
TRUE
HDA_BIT_CLK
TRUE
SPI_ALT_MISO
=USB_PWR_EN
TRUE
=I2C_LIO_SDA
TRUE
TRUE
=I2C_MIKEY_SCL
TRUE
SPKRAMP_INR_P
TRUE
AUD_IP_PERIPHERAL_DET
TRUE
PP3V3_WLAN_F
TRUE
WIFI_EVENT_L
TRUE
USB_BT_N
TRUE
LED_RETURN_1
TRUE
PP3V3_S0_HDD_R
SMC_HDD_TEMP_CTL
TRUE
SATA_HDD_R2D_P
TRUE
TRUE
SYS_ONEWIRE
TRUE
=PP1V8R1V5_S0_AUDIO
TRUE
HDA_SDIN0
SMC_RESET_L
TRUE
TRUE
SMC_NMI
SMC_RX_L
TRUE
TRUE
SMC_MD1
SMC_TDO
TRUE
TRUE
LPC_FRAME_L
TRUE
SPI_ALT_MOSI
LPC_AD<3..0>
TRUE
TRUE
=PP5V_S0_LPCPLUS
AUD_GPIO_3
TRUE
USB_EXTD_N
TRUE
USB_CAMERA_N
TRUE
TRUE
=PP18V5_DCIN_CONN
PP1V05_S0_MCP_PLL_UF
TRUE
PP1V5R1V35_S3
TRUE
PP3V3_SW_LCD
TRUE
PPDCIN_S5_S5
TRUE
TRUE
SPKRAMP_R_N_OUT
TRUE
SPKRAMP_R_P_OUT
PPVOUT_SW_LCDBKLT
TRUE
PP3V3_SW_LCD
TRUE
TRUE
LED_RETURN_5
TRUE
=PP3V42_G3H_HALL
TRUE
=I2C_TCON_SCL
TRUE
LED_RETURN_6
TRUE
=I2C_TCON_SDA
TRUE
HDA_SDOUT
HDA_SYNC
TRUE
TRUE
HDA_RST_L
TRUE
AUD_IPHS_SWITCH_EN
LED_RETURN_4
TRUE
TRUE
LED_RETURN_3
TRUE
LED_RETURN_2
TRUE
DP_INT_AUX_CH_C_P
TRUE
DP_INT_ML_F_P<1>
DP_INT_ML_F_N<1>
TRUE
TRUE
DP_INT_ML_F_P<0>
DP_INT_ML_F_N<0>
TRUE
USB_TPAD_CONN_P
TRUE
PP3V3_TPAD_CONN
TRUE
=PP3V42_G3H_TPAD
TRUE
=I2C_TPAD_SDA
TRUE
SMC_ONOFF_L
TRUE
SMC_LID
TRUE
7 OF 110
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051-8379
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42 59 62
8
42 49
8
57 71
8
7 8
57
8
57 71
8
42
8
42
8
57
8
57 71
8
36
61
8
7
35
7
34 39
8
38 39 40
19 38 40
19 37
19 38 40
9
37 38 39
8
37
49
16 34 67
38 39 40
19 40
34
34
16 34
46 71
41 46
16 34 67
18 34 68
16 34 67
41 70
18 37 68
35 67
35 38
35 67
35 67
10 14 65
10 14 65
10 14 65
10 14 65
10 14 65
10 14 65
10 14 65
8
40
19 38 40
38 39 40
25 40
38 40
25 40 68
40 68
40 68
36 38 39 40
49
49
50
41 70
37 48 71
18 37 68
18 37
8
37
59 71
10 14 65
10 14 65
10 14 65
10 14 65
37 41
19 40 47
37 41
34 67
16 34 67
59
34 67
19 37 68
40 68 36 37 57
37 41
37 41
37 48 71
17 37
7
34 39
34 38 39
18 34 68
59 62
7
35
35 38
35 67
37 38
8
37
19 37 68
38 39 40 50
38 40
36 38 39 40
38 40
38 39 40
19 38 40 68
40 68
19 38 40 68
8
40
37 48
18 37 68
18 37 68
8
49
8
8
71
7
59
8
48 49
48 49
7
42 59
62
7
59
59 62
8
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41 59
59 62
41 59
19 37 68
19 37 68
19 37 68
19 37
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59 62
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59 71
59 71
59 71
59 71
59 71
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46
8
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Page 8
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
11.30 A
LVDDR (1.5V/1.35V) Rails
3.30 A
(MCP VCORE AFTER SENSE RES)
9.40 A
"S0,S0M" RAILS
0.100 A
5.40 A
400mA
300mA
(OR 1.35V)
0 mA
4250 mA
0.064
18 A
LVDDR VRef/VTT (0.75V/0.675V) Rails
1.20 A
23.8 A
.210 A
"G3H" RAILS
"S3" RAILS
"ENET" RAILS
~100mA
1.274 A
"S5" RAILS
105 mA/241 mA
0.290 A
1.07 A + S3 + S0
SYNC_DATE=12/11/2009
SYNC_MASTER=K6_MLB
Power Aliases
=PP5V_S3_AUDIO_AMP
=PP5V_S3_DDRREG
=PP5V_S3_LIO_CONN
=PP5V_S3_MCPDDRFET
=PP5V_S3_P5VS0FET
=PP5V_S3_REG
=PP5V_S3_RTUSB
=PP5V_S3_SYSLED
=PP5V_S3_TPAD
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
PP5V_S3
MAKE_BASE=TRUE
=PP3V3_ENET_MCP_RMGT
MAKE_BASE=TRUE
PP3V3_ENET
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
=PPVCORE_S0_MCPGFXFET
=PPVCORE_S0_MCP
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
PP3V3_S5
MAKE_BASE=TRUE
VOLTAGE=3.3V
=PP3V3_SMC_PME
=PP3V3_S0_LCD
=PP0V9_ENET_P0V9ENETFET
=PP0V9_S5_REG
=PP0V9_S5_MCP_VDD_AUXC
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
VOLTAGE=0.9V
PP0V9_S5
=PP3V3_S5_MCP
=PP3V3_S5_DP_PORT_PWR
=PP3V3_S5_TPAD
=PP3V3_S5_REG
=PP3V3_S0_SMC
=PP3V3_S0_MCP_PLL_UF
=PP3V3_S0_MCP_GPIO
=PP3V3_S0_FAN
=PP1V5_S0_CPU
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP1V5_S0
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
PPDDRVTT_S0
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.4 MM
=PP3V3_S3_TPAD
=PP3V3_S3_WLAN
=PP3V3_S3_1V5S3ISNS
=PP3V3_S3_DBGLEDS
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMS
=PPBUS_G3H_R_OUT
=PP5V_S0_CPU_IMVP
=PP5V_S0_LPCPLUS
MIN_NECK_WIDTH=0.20mm
MIN_LINE_WIDTH=1mm
PPDCIN_S5_S5
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPDCIN_S5_CHGR
=PPVIN_S0_MCPCORE
=PPVIN_S3_DDRREG
=PPBUS_5V_S5
=PPBUS_G3H_R_IN
=PPBUS_S0_LCDBKLT
=PP5VR3V3_S0_DPCADET
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
PP5V_S0
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
=PP3V3_S0_FET
=PPVIN_S5_P5VP3V3
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP1V05_S0
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
=PP1V05_SW_MCP_FSB
=PP3V3_S0_BKLTISNS
=PP3V3_S0_DPCONN
=PP5V_S0_CPUVTTS0
=PP5V_S0_BKL
=PP3V3_S0_P1V5S0
=PP5V_S0_MCPREG
=PP5V_S0_FET
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_MCP_PLL_VLDO
=PP3V3_S0_PWRCTL
=PP3V42_G3H_CHGR
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_PLL_OR
=PP1V8R1V5_S0_AUDIO
=PP1V5_S0_REG
=PP1V5_S0_MCP_PLL_VLDO
=PPVTT_S3_DDR_BUF
PPDDRVREF_S3
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.3 mm
=PPVTT_S0_DDR_LDO
=PPDDRVTT_S0_MEM_A
=PPMCPCORE_S0_REG
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_PLL_UF_R
=PPCPUVTT_S0_REG
=PPVCORE_S0_CPU
PP1V05_S0_MCP_PLL_UF
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
PPVCORE_S0_MCP
VOLTAGE=1.05V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
PPVCORE_S0_CPU
MIN_NECK_WIDTH=0.25 MM
MAKE_BASE=TRUE
VOLTAGE=1.25V
MIN_LINE_WIDTH=0.6 MM
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_HALL
=PP3V3_S5_SMC
=PP3V42_G3H_SMCUSBMUX
=PP3V3_ENET_FET_R
=PP1V5R1V35_S0_MCPDDRFET
=PPDDR_S3_REG
=PP3V42_G3H_REG
=PP3V3_S0_DEBUGROM
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_IMVP
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_AUDIO
=PP3V3_S0_MCPTHMSNS
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_ENET_MCP_PLL_MAC
=PP3V3_S0_MCPCOREISNS
=PP3V3_S5_ROM
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P3V3ENETFET
=PP0V9_ENET_FET
=PP0V9_ENET_MCP_RMGT
MAKE_BASE=TRUE
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP0V9_ENET
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PPLVDDR_S3_MEM_B
=PP3V42_G3H_TPAD
=PP3V42_G3H_SMBUS_SMC_BSA
=PPVIN_S5_SMCVREF
=PP3V42_G3H_ONEWIRE
PP3V42_G3H
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
PP3V3_G3_RTC
=PP3V42_G3H_BMON_ISNS
=PP3V3_S5_LPCPLUS
=PP5V_S0_FAN
=PP3V3_S0_SMBUS_MCP_1
=PP3V3_S5_SMBUS_SMC_MGMT
=PP1V05_S0_CPU
=PP1V05_S0_MCP_M2CLK_DLL
=PP18V5_DCIN_CONN
MIN_NECK_WIDTH=0.25 MM
PPBUS_G3H_ISNS
MAKE_BASE=TRUE
VOLTAGE=8.4V
MIN_LINE_WIDTH=0.6 mm
=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP
MAKE_BASE=TRUE
PPBUS_G3H
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm
VOLTAGE=8.4V
=PP3V3_S0_CSREGISNS
=PP3V3_S0_BKL_VDDIO
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_P0V9ENETFET
=PP3V3_S5_VMON
=PP3V3_S5_P0V9S5
=PP3V3_S5_MCP_GPIO
=PP1V05_S0_MCP_DP0_VDD
=PP1V05_S0_MCP_AVDD_UF
=PP5V_S0_MCPFSBFET
=PPDDRVTT_S0_MEM_B
=PP1V05_S0_XDP
=PP1V05_S0_MCP_PE_DVDD
=PPVCORE_S0_CPU_REG
=PPLVDDR_S3_MEM_A
=PPVIN_S0_DDRREG_LDO
=PP1V5R1V35_S3_MCP_MEM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
PP1V5R1V35_S3
MAKE_BASE=TRUE
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_VREFMRGN
=PP3V3_S3_PDCISENS
=PP3V3_S3_FET
=PPBUS_G3H
=PP3V3_S3_WLANISNS
=PP1V05_S0_MCP_FSB
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PP3V3_S0
=PP3V3_S0_HDDISNS
=PP3V3_S0_HDD
=PP3V3_S0_MCP_HVDD
=PP3V3_S3_BT
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
PP3V3_S3
MAKE_BASE=TRUE
8 OF 110
4.4.0
051-8379
8 OF 73
48
52
7
49
21
58
51
36
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7
18 20 23
7
22
20 23
7
57 71
39
59
58
56
20 23
7
20 23
61
46
51 57
39
23
17 18 19
45
11 12
7
57 71
46
34
42
49
41
43
53
7
40
7
50
54
52
56
43
63
61
7
57
58
51
7
57
20 23
42
61
55
62
56
54
58
43
56
57
50 57
23
56
7
37
56
56
33 52
52
32
54
20 23
56
55
11 12 64
7
7
42
7
42
57
7
49
38 39
36
9
21
52
49
40
41
41
53
44
7
37
44
19 23
23
43
47
58
58
58
58
20 23
7
41
13
20 23
28 29 31
7
46
41
39
7
37
7
19 20 23
43
7
40
45
41
41
10 11 12
15 23
7
49
7
55
53
7
42 49
43
62
25
58
57
56 57
18 19
17 24
23
22
32
13
20 23
53
26 27 30
52
15
7
71
19
33
52
58
50
42
14 20 23
7
57 71
42
35
20 23
7
34
7
Page 9
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
IN
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MDP CONN METAL TAB
EMI IO POGO PINS
UNUSED USB PORTS
USB ALIASES
HEAT SINK MOUNTING BOSSES
FAN BOSS
CHARGER SIGNAL
MCPCOREISNS SIGNAL
SSD BOSS
BSEL<2..0>
FSB MHZ
333
266
200
133
(RSVD)
100
(400)
(166)
1 1 1
0 1 1
0 1 0
1 0 0
1 0 1
1 1 0
0 0 0
0 0 1
CPU ALIASES
MCP89 ALIASES
X16 BOSS
LVDS ALIASES
DISPLAY PORT ALIASES
UNUSED SATA ODD SIGNALS
ETHERNET ALIASES
SATA ALIASES
UNUSED GPU LANES
PCI-E ALIASES
18 69
18 69
18 69
18 69
18 69
18 69
18 69
18
2
1
R0981
1/20W
5%
201
MF
10K
2
1
R0980
10K
1/20W
5%
201
MF
7
37 38 39 50
21
R0911
MF-LF
1/16W
5%
402
0
PLACE_NEAR=U7980.A1:5MM
8
18
2
1
R0982
10K
201
1/20W
5%
MF
2
1
R0984
10K
1/20W
5%
201
MF
2
1
R0983
1/20W
5%
201
10K
MF
2
1
R0985
10K
1/20W
5%
201
MF
1
ZS0905
CRITICAL
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0906
POGO-2.0OD-3.6H-K86-K87
CRITICAL
SM
1
ZS0907
POGO-2.0OD-3.6H-K86-K87
CRITICAL
SM
1
Z0906
STDOFF-4.5OD1.8H-SM
1
Z0915
STDOFF-4.5OD1.9H-SM
1
Z0907
STDOFF-4.5OD1.8H-SM
1
Z0908
STDOFF-4.5OD1.8H-SM
1
Z0909
STDOFF-4.5OD1.8H-SM
1
Z0910
STDOFF-4.5OD1.8H-SM
1
Z0911
STDOFF-4.5OD1.8H-SM
1
Z0912
STDOFF-4.5OD1.8H-SM
1
Z0913
STDOFF-4.5OD1.8H-SM
1
Z0905
STDOFF-4.5OD1.8H-SM
1
Z0914
STDOFF-4.5OD1.9H-SM
1
MT0900
SM-SP
STIFFENER-K16-K99
NOSTUFF
1
ZS0904
SM
POGO-2.0OD-2.95H-K86-K87
CRITICAL
SYNC_DATE=12/11/2009
SYNC_MASTER=K6_MLB
SIGNAL ALIAS
MIN_NECK_WIDTH=0.20MM
GND
VOLTAGE=0V
MIN_LINE_WIDTH=0.50MM
MAKE_BASE=TRUE
ENET_RXD_PD
=PP3V3_ENET_FET_R
ENET_ENERGY_DET
NC_ENET_CLKREQ_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_D2RP<5:4>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_R2DCP<5:4>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2RN<5:4>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_CLKREQ_L
NO_TEST=TRUE
MAKE_BASE=TRUE
DP_AUX_CH_C_P
DP_INT_ML_P<1:0>
MAKE_BASE=TRUE
DP_IG_ML1_N<1:0>
DP_IG_AUX_CH1_P
ENET_RXD<2>
NO_TEST=TRUE
NC_USB_MINIP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_SDCARDN
MAKE_BASE=TRUE
=PP3V3_ENET_FET
MAKE_BASE=TRUE
TP_LVDS_DDC_DATA
TP_DP_INT_MLN<3:2>
MAKE_BASE=TRUE
MCP_MEM_VDD_SEL_1V5
TP_MEM_VDD_SEL_1V5
MAKE_BASE=TRUE
TP_MCP_RGB_DAC_VREF
TP_MEM_A_CLKN<1>
MAKE_BASE=TRUE
TP_MEM_B_CLKP<1>
MAKE_BASE=TRUE
TP_MEM_B_CLKN<1>
MAKE_BASE=TRUE
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
NC_LVDS_IG_B_CLKN
MAKE_BASE=TRUE
NO_TEST=TRUE
SATA_ODD_D2R_N
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_ENET_FET
MCP_RGMII_VREF
ENET_CLK125M_RXCLK
ENET_RXD<3>
ENET_RXD<1>
ENET_RXD<0>
NC_SATA_ODD_D2RN
MAKE_BASE=TRUE
NO_TEST=TRUE
SATA_ODD_R2D_P
NC_SATA_ODD_R2DP
MAKE_BASE=TRUE
NO_TEST=TRUE
SATA_ODD_D2R_P
NC_SATA_ODD_D2RP
MAKE_BASE=TRUE
NO_TEST=TRUE
SATA_ODD_R2D_N
NC_SATA_ODD_R2DN
MAKE_BASE=TRUE
NO_TEST=TRUE
SATA_ODD_R2D_C_P
NC_SATA_ODD_R2DCP
MAKE_BASE=TRUE
NO_TEST=TRUE
SATA_ODD_R2D_C_N
NC_SATA_ODD_R2DCN
MAKE_BASE=TRUE
NO_TEST=TRUE
DP_IG_ML1_P<3:2>
TP_DP_INT_MLP<3:2>
MAKE_BASE=TRUE
DP_IG_ML1_N<3:2>
DP_IG_HPD1
MAKE_BASE=TRUE
DP_INT_HPD
DP_IG_AUX_CH1_N DP_INT_AUX_CH_N
MAKE_BASE=TRUE
DP_INT_AUX_CH_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_INT_ML_N<1:0>
DP_IG_ML1_P<1:0>
DP_CA_DET
DP_AUX_CH_C_N
MAKE_BASE=TRUE
DP_EXT_AUX_CH_C_N
DP_IG_AUX_CH0_N
DP_IG_AUX_CH0_P DP_EXT_AUX_CH_P
MAKE_BASE=TRUE
DP_IG_HPD0
MAKE_BASE=TRUE
DP_EXT_HPD
DP_IG_ML0_P<0..3> DP_EXT_ML_P<0..3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_LVDS_DDC_CLK
MAKE_BASE=TRUE
LCD_BKLT_EN
MAKE_BASE=TRUE
LCD_IG_PWR_EN
MAKE_BASE=TRUE
LCD_BKLT_PWM
=MCP_IFPB_TXD_N<0..3>
=MCP_IFPB_TXD_P<0..3>
NC_LVDS_IG_B_DATAP<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_CLKP
MAKE_BASE=TRUE
NO_TEST=TRUE
=MCP_IFPA_TXD_P<0..3>
NC_LVDS_IG_A_DATAP<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
=MCP_IFPA_TXD_N<0..3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<0..3>
NO_TEST=TRUE
=MCP_IFPA_TXC_P
NC_LVDS_IG_A_CLKP
MAKE_BASE=TRUE
NO_TEST=TRUE
USB_EXTC_N
USB_MINI_N
NO_TEST=TRUE
NC_USB_MININ
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_SDCARDP
MAKE_BASE=TRUE
TP_MEM_B_A<15>
MAKE_BASE=TRUE
MEM_A_A<15>
TP_MEM_A_A<15>
MAKE_BASE=TRUE
MEM_A_CLK_P<1>
TP_MEM_A_CLKP<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
CPU_BSEL<0:2>
=MCP_BSEL<0:2>
SMC_BC_ACOK
MAKE_BASE=TRUE
=MCP_IFPA_TXC_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_EXTCN
NC_LVDS_IG_B_DATAN<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
MEM_A_CLK_N<1>
NC_LVDS_IG_A_CLKN
MAKE_BASE=TRUE
NO_TEST=TRUE
DP_IG_ML0_N<0..3>
ENET_RXCLK_PD
MAKE_BASE=TRUE
ENET_MDIO
MAKE_BASE=TRUE
MCPCORES0_VO
=MCPCOREISNS_N
MAKE_BASE=TRUE
MCPCORES0_ISP_R
=MCPCOREISNS_P
=CHGR_ACOK
USB_EXTC_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_EXTCP
=MCP_IFPAB_DDC_CLK
LCD_IG_BKLT_EN
=PEG_R2D_C_P<5:4>
=PEG_R2D_C_N<5:4>
USB_MINI_P
USB_SDCARD_N
USB_SDCARD_P
=PEG_D2R_P<5:4>
=PEG_D2R_N<5:4>
ENET_CLKREQ_L
PEG_CLKREQ_L
PEG_CLK100M_P
PEG_CLK100M_N
=MCP_IFPAB_DDC_DATA
LCD_IG_PWR_EN
LCD_IG_BKLT_PWM
=MCP_IFPB_TXC_N
=MCP_IFPB_TXC_P
NC_PEG_CLK100MP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_CLK100MN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_R2DCN<5:4>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_RGB_DAC_VREF
NO_TEST=TRUE
MAKE_BASE=TRUE
CPU_PECI_MCP
MEM_B_A<15>
DP_EXT_ML_N<0..3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_EXT_AUX_CH_N
DP_EXT_AUX_CH_C_P
MAKE_BASE=TRUE
DP_EXT_CA_DET
MAKE_BASE=TRUE
ENET_RX_CTRL
9 OF 110
4.4.0
051-8379
9 OF 73
60
59 71
17 67
17 67
58
19
17
15 66
15 66
18 67
67
18 67
67
18 67
18 67
17
17
17 59
17 67 59 71
59 71
59 71
17 67
60
60 61 71
17 67
17 67 60
17 61
17 67 61 71
63
9
17 59
62
17
17
17
17
17
18 68
18 68
15 66
15 66
10 65
14
17
15 66
17 67
54 43
54
43
18 68
17
17
16
16
18 68
18 68
18 68
16
16
16
16
16 67
16 67
17
9
17 59
17
17
17
14
15 66
61 71
60
61 71
61
Page 10
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
BI
BI
BI
BI
OUT
IN
IN
A6*
BR0*
BPM0*
DBR*
DEFER*
DBSY*
A7*
A15*
A14*
REQ2*
A17*
A18*
PREQ*
IERR*
BPRI*
BNR*
A4*
TRST*
LINT1
TEST2
TEST4
A16*
A20M*
A3*
A30*
A31*
A32*
A34*
A35*
A5*
A8*
ADSTB0*
ADSTB1*
BCLK1
BPM2*
BPM3*
FERR*
HIT*
HITM*
IGNNE*
LINT0
RSVD7
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
TEST1
TEST3
TEST5
TEST6
PROCHOT*
REQ0*
REQ1*
REQ3*
REQ4*
SMI*
TCK
TDO
THERMTRIP*
THRMDA
THRMDC
TMS
PRDY*
BPM1*
RS2*
RS1*
RS0*
RESET*
DRDY*
ADS*
A19*
A20*
A21*
A23*
A22*
A24*
A25*
A26*
A27*
A28*
A29*
A33*
STPCLK*
A13*
A12*
A11*
BCLK0
TDI
TRDY*
LOCK*
INIT*
A10*
A9*
(1 OF 8)
XDP/ITP SIGNALS
ADDR GROUP0ADDR GROUP1
THERMAL
H CLK
ICH
CONTROL
D11*
D7*
D6*
D5*
D4*
D3*
D17*
D16*
DINV0*
DSTBP0*
DSTBN0*
D10*
D2*
SLP*
PWRGOOD
PSI*
GTLREF
DSTBP3*
DSTBP2*
DSTBN3*
DSTBN2*
DSTBN1*
DPWR*
DPSLP*
DPRSTP*
DINV3*
DINV2*
D63*
D62*
D61*
D60*
D59*
D58*
D57*
D56*
D55*
D54*
D53*
D52*
D51*
D50*
D49*
D48*
D47*
D46*
D45*
D44*
D43*
D42*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
D31*
D30*
D26*
D25*
D24*
D23*
D22*
D21*
D20*
D13*
D12*
D1*
D0*
COMP3
COMP2
COMP1
COMP0
BSEL2
BSEL1
BSEL0
D27*
D29*
D8*
DINV1*
DSTBP1*
D28*
D14*
D15*
D9*
D19*
D18*
D41*
(2 OF 8)
DATA GRP 3
DATA GRP1
MISC
DATA GRP 0
DATA GRP 2
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PLACE_NEARs:
C1014.1:
R1006.1:
R1005.2:
PLACE_NEARs:
R1020.1:
R1021.1:
R1022.1:
R1023.1:
CPU JTAG Support
2
1
R1000
54.9
1%
201
1/20W
MF
2
1
R1002
68
5%
201
1/20W
MF
2
1
R1005
U1000.AW43:12.7 mm
1%
1K
201
1/20W
MF
2
1
R1006
1%
U1000.AW43:12.7 mm
2K
201
1/20W
MF
2
1
R1023
54.9
1%
U1000.AF2:12.7 mm
201
1/20W
MF
2
1
R1022
27.4
1%
U1000.AE1:12.7 mm
201
1/20W
MF
2
1
R1021
54.9
1%
U1000.AD44:12.7 mm
201
1/20W
MF
2
1
R1020
27.4
1%
U1000.AE43:12.7 mm
201
1/20W
MF
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
14 53 65
14 65
14 65
14 65
13 14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
9
65
9
65
9
65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
7
14 65
14 65
14 65
14 65
14 65
14 65
14 65
7
14 65
7
14 65
7
14 65
13 65
13 65
13 65
13 65
13 65
13 65
10 13 65
14 39 65
44 71
14 39 65
14 65
13 14 65
14 65
14 65
14 65
14 65
10 13 65
10 13 65
10 13 65
10 13 65
44 71
14 65
14 65
14 65
14 65
14 65
14 65
14 65
21
R1010
NO STUFF
5%
0
201
1/20W
MF
2
1
R1011
NO STUFF
1K
5%
201
1/20W
MF
2
1
R1001
54.9
1%
201
1/20W
MF
21
R1090
1%
54.9
201
1/20W
MF
21
R1091
1%
54.9
201
1/20W
MF
21
R1093
1%
54.9
201
1/20W
MF
7
14 65
7
14 65
7
14 65
7
14 65
21
R1094
MF
54.9
1%
201
1/20W
2
1
R1012
NO STUFF
1K
5%
201
1/20W
MF
2
1
C1014
U1000.AE41:12.7 mm
NO STUFF
X5R
10%
0.1UF
201
6.3V
21
R1092
1/20W
1%
54.9
PLACE_NEAR=J1300.52:12.7 mm
201
MF
13 25
14 65
14 65
AV8
L1
AW5
BD34
BB34
B10
AC43
AY10
AE41
C43
D40
E37
AU1
AW7
AV4
F8
E5
F4
J9
AL5
AG5
Y2
V2
H8
K4
H4
K2
G5
W5
P4
U1
R5
R1
D38
AV2
AV10
N1
C5
C9
D8
F10
B40
F2
H2
D4
F38
N5
J1
J7
M2
L5
AY2
BA5
BA7
AY8
J5
C35
A35
AN5
Y4
M4
T2
AB4
AA1
T4
W1
V4
AR1
AP2
AU5
AM2
AL1
AJ1
P2
AR5
AP4
AM4
AH4
AJ5
AF4
AH2
AT2
AK2
C7
AT4
AG1
AK4
AN1
AC1
AB2
AE5
AA5
AD4
AD2
AC5
U1000
NEED_TP=TRUE
NEED_TP=TRUE
OMIT_TABLE
BGA
PENRYN-SFF
CDC-QKWH-QS-1.2-10W-800-R0-1M
D10
E7
BD10
AW43
AY38
AL43
W43
J41
AY40
AK44
U43
K40
C41
B8
G7
BC37
AJ41
R43
P40
K44
L41
E41
AU43
BA35
BB40
BA41
G39
BC39
BC35
AT40
AY36
BB38
BA37
AR41
AW41
AU41
AV40
H44
AT44
AV38
AL41
AN41
AP40
AG43
AK40
AM40
AN43
AM44
H40
AH44
AF44
AG41
AJ43
AF40
AH40
AR43
AP44
T44
Y44
J43
Y40
AA43
AC41
AD40
AB40
AA41
U41
N43
W41
R41
E43
AB44
V44
V40
P44
L43
M44
G41
M40
T40
N41
G43
F40
AF2
AE1
AD44
AE43
B38
C37
A37
U1000
OMIT_TABLE
CDC-QKWH-QS-1.2-10W-800-R0-1M
BGA
PENRYN-SFF
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
CPU FSB
TP_CPU_TEST3
TP_CPU_TEST6
TP_CPU_TEST5
CPU_TEST2
CPU_TEST1
CPU_TEST4
XDP_DBRESET_L
TP_CPU_RSVD_H8
FSB_A_L<31>
FSB_A_L<24>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<18>
XDP_TCK
XDP_TRST_L
XDP_TMS
CPU_THERMD_P
XDP_TRST_L
XDP_BPM_L<3>
FSB_HIT_L
FSB_HITM_L
CPU_TEST4
FSB_LOCK_L
FSB_RS_L<0>
CPU_GTLREF
TP_CPU_RSVD_AL5
XDP_TDI
XDP_TDO
=PP1V05_S0_CPU
CPU_BSEL<0>
CPU_TEST2
CPU_BSEL<1>
FSB_A_L<3>
FSB_REQ_L<0>
FSB_A_L<10>
CPU_COMP<2>
CPU_COMP<3>
FSB_D_L<16>
FSB_DINV_L<0>
FSB_A_L<22>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<14>
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<13>
FSB_A_L<35>
FSB_A_L<30>
FSB_A_L<29>
FSB_A_L<21>
FSB_A_L<20>
FSB_A_L<19>
FSB_A_L<16>
FSB_A_L<15>
FSB_A_L<4>
CPU_SMI_L
CPU_NMI
FSB_A_L<28>
FSB_A_L<11>
FSB_A_L<33>
FSB_A_L<32>
FSB_A_L<27>
FSB_ADSTB_L<0>
FSB_A_L<12>
FSB_A_L<17>
CPU_STPCLK_L
FSB_REQ_L<1>
CPU_IGNNE_L
FSB_ADSTB_L<1>
FSB_A_L<34>
CPU_A20M_L
FSB_REQ_L<2>
FSB_D_L<9>
FSB_D_L<15>
FSB_D_L<14>
FSB_D_L<28>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
FSB_D_L<8>
FSB_D_L<29>
FSB_D_L<27>
CPU_BSEL<2>
CPU_COMP<1>
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_D_L<2>
FSB_D_L<10>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_D_L<17>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<11>
CPU_FERR_L
FSB_D_L<18>
FSB_D_L<19>
CPU_TEST1
TP_CPU_RSVD_AG5
TP_CPU_RSVD_Y2
TP_CPU_RSVD_V2
TP_CPU_RSVD_F4
TP_CPU_RSVD_J9
FSB_BPRI_L
CPU_INIT_L
FSB_CPURST_L
XDP_TCK
XDP_TDO
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
CPU_DPRSTP_L
TP_CPU_PSI_L
FSB_BNR_L
FSB_ADS_L
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
XDP_BPM_L<5>
CPU_PROCHOT_L
PM_THRMTRIP_L
CPU_THERMD_N
XDP_TDI
XDP_BPM_L<4>
XDP_BPM_L<2>
FSB_TRDY_L
FSB_RS_L<2>
FSB_RS_L<1>
CPU_IERR_L
FSB_BREQ0_L
XDP_BPM_L<0>
XDP_BPM_L<1>
CPU_INTR
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_A_L<7>
FSB_A_L<23>
XDP_TMS
CPU_COMP<0>
FSB_CPUSLP_L
CPU_PWRGD
FSB_DPWR_L
CPU_DPSLP_L
10 OF 110
4.4.0
051-8379
10 OF 73
10
10
10
10 13 65
10 13 65
10 13 65
10
33 65
10 13 65
10 13 65
8
11 12
10
65
65
65
10
65
65
Page 11
VCCA
VID
VCC
VCC
VCCP
(3 OF 8)
VSSSENSE
VCCSENSE
VCC VCC
(7 OF 8)
VCCP VCCP
(8 OF 8)
VSS VSS
(6 OF 8)
VSSVSS
(4 OF 8)
VSSVSS
(5 OF 8)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(CPU IO POWER 1.05V)
130 mA
(CPU CORE POWER)
18 A (CULV Design Target)
17.6 A (CULV ICC_Max)
4500 mA (before VCC stable)
2500 mA (after VCC stable)
(CPU INTERNAL PLL POWER 1.5V)
BC13
AY4
BB4
BC5
BB8
BB10
BC7
BD8
BD12
AC37
P38
R37
U37
V38
W37
J37
K38
AF38
AG37
AJ37
AK38
AA37
AB38
L37
N37
D34
B34
BD28
BB26
BD26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
V32
AV26
AY26
AM30
AM28
AP30
AP28
AM26
AP26
AF30
AF28
W33
AH30
AH28
AK30
AK28
AF26
AH26
AK26
Y30
Y28
AB30
J33
AB28
AD30
AD28
Y26
AB26
AD26
P30
P28
T30
T28
K32
V30
V28
P26
T26
V26
K30
K28
M30
M28
K26
L33
M26
D28
D30
F30
F28
H30
H28
D26
F26
H26
M32
B28
B30
B26
BB32
BD32
AT34
AT32
AU33
AV32
AY32
N33
AL33
AM32
AN33
AP32
AR33
AE33
AF32
AG33
AH32
AJ33
F32
AK32
Y32
AA33
AB32
AC33
AD32
P32
R33
T32
U33
G33
H32
U1000
CDC-QKWH-QS-1.2-10W-800-R0-1M
PENRYN-SFF
BGA
OMIT_TABLE
BB14
BD14
AT14
AV14
AY14
AM14
AP14
BB18
BB16
BD18
BD16
BB20
BD20
AT18
AT16
AV18
AV16
AY18
AY16
AT20
AV20
AY20
AM18
AM16
AP18
AP16
AM20
AP20
AF18
AF16
AH18
AH16
AF20
AH20
AK18
AK16
AK20
Y18
Y16
AB18
AB16
AD18
AD16
Y20
AB20
AD20
P18
P16
T18
T16
V18
V16
P20
T20
V20
K18
K16
M18
M16
K20
M20
D16
D18
F18
F16
H18
H16
D20
F20
H20
B16
B18
B20
BB24
BB22
BD24
BD22
AT24
AT22
AV24
AV22
AY24
AY22
AM24
AM22
AP24
AP22
AF24
AF22
AH24
AH22
AK24
AK22
Y24
Y22
AB24
AB22
AD24
AD22
P24
P22
T24
T22
V24
V22
K24
K22
M24
M22
D22
D24
F24
F22
H24
H22
B22
B24
BB30
BB28
BD30
U1000
CDC-QKWH-QS-1.2-10W-800-R0-1M
PENRYN-SFF
BGA
OMIT_TABLE
AJ13
AJ11
AK14
AK12
AF10
AK10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
P14
P12
R13
R11
T14
U13
U11
V14
V12
W13
W11
P10
V10
J13
J11
K14
K12
L13
L11
M14
N13
N11
K10
D12
D14
E13
E11
F14
F12
G13
G11
H14
H12
B12
B14
C13
AL35
AN35
AP36
AE35
AG35
AJ35
AF36
AK36
AA35
AC35
AB36
R35
U35
P36
V36
W35
J35
L35
N35
K36
D32
E35
E33
F34
G35
F36
H36
B32
C33
AL37
AN37
AP38
AE37
A13
A33
AL9
AL7
AN9
AN7
AR9
AR7
AE9
AE7
AG9
AG7
AJ9
AJ7
AA9
AA7
AC9
AC7
R9
R7
U9
U7
W9
W7
L9
L7
N9
N7
AU13
AU11
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AP10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
U1000
CDC-QKWH-QS-1.2-10W-800-R0-1M
PENRYN-SFF
BGA
OMIT_TABLE
A7
A5
A9
A11
A15
A19
A17
A25
A23
A21
A29
A27
A31
A41
A39
BA1
AW1
E1
G1
BA3
BB2
BC3
BD4
AU3
AW3
AL3
AN3
AR3
AE3
AG3
AJ3
AA3
AC3
R3
U3
W3
J3
L3
N3
D2
E3
G3
B4
C3
BA9
BB6
BC9
BD6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
AM8
AM6
AP8
AP6
AF8
AF6
AH8
AH6
AK8
AK6
Y8
Y6
U1000
CDC-QKWH-QS-1.2-10W-800-R0-1M
PENRYN-SFF
BGA
OMIT_TABLE
G27
E31
G31
C27
C29
C31
BA33
BC33
BB36
BD36
T42
AU35
AV34
AW35
AW33
AY34
AT36
AV36
AM34
AP34
AM36
V42
AR35
AF34
AH34
AH36
AK34
Y34
AB34
AD34
Y36
AD36
K42
P34
T34
V34
T36
K34
M34
M36
H34
D36
B36
M42
BA39
BC41
BD40
BD38
AT38
AU39
AU37
AW39
AW37
AL39
F44
AM38
AN39
AR39
AR37
AE39
AG39
AH38
AJ39
Y38
AA39
D44
AC39
AD38
R39
T38
U39
W39
J39
L39
M38
N39
D42
E39
G37
H38
C39
BA43
BB42
AY44
AV44
AT42
AV42
F42
AY42
AM42
AP42
G25
G23
G21
AF42
C21
C23
C25
BA29
BA27
BC29
BC27
BA31
BC31
AU29
AH42
AU27
AW29
AW27
AU31
AW31
AL29
AL27
AN29
AN27
AL31
AK42
AN31
AR29
AR27
AR31
AE29
AE27
AG29
AG27
AJ29
AJ27
Y42
AE31
AG31
AJ31
AA29
AA27
AC29
AC27
AA31
AC31
R29
AB42
R27
U29
U27
R31
U31
W29
W27
W31
J29
J27
AD42
L29
L27
N29
N27
J31
L31
N31
E29
E27
G29
P42
H42
B42
U1000
BGA
CDC-QKWH-QS-1.2-10W-800-R0-1M
PENRYN-SFF
OMIT_TABLE
AB8
AB6
AD8
AD6
P8
P6
T8
T6
V8
V6
U5
K8
K6
M8
M6
D6
E9
F6
G9
H6
B6
BA13
BA11
BB12
BC11
BA15
BC15
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
AM12
AL15
AN15
AR15
AM10
AH12
AE15
AG15
AJ15
AH10
Y12
AD12
AA15
AC15
Y10
AD10
T12
R15
U15
W15
T10
M12
J15
L15
N15
M10
E15
G15
H10
C11
C15
BA19
BA17
BC19
BC17
AU19
AU17
AW19
AW17
AL19
AL17
AN19
AN17
AR19
AR17
AE19
AE17
AG19
AG17
AJ19
AJ17
AA19
AA17
AC19
AC17
R19
R17
U19
U17
W19
W17
J19
J17
L19
L17
N19
N17
E19
E17
G19
G17
C17
C19
BA25
BA23
BA21
BC25
BC23
BC21
AU25
AU23
AU21
AW25
AW23
AW21
AL25
AL23
AL21
AN25
AN23
AN21
AR25
AR23
AR21
AE25
AE23
AE21
AG25
AG23
AG21
AJ25
AJ23
AJ21
AA25
AA23
AA21
AC25
AC23
AC21
R25
R23
R21
U25
U23
U21
W25
W23
W21
J25
J23
J21
L25
L23
L21
N25
N23
N21
E25
E23
E21
U1000
BGA
PENRYN-SFF
CDC-QKWH-QS-1.2-10W-800-R0-1M
OMIT_TABLE
53 65
2
1
R1100
PLACE_NEAR=U1000.BD12:25.4 mm
100
1%
1/20W
MF
201
2
1
R1101
PLACE_NEAR=U1000.BC13:25.4 mm
100
1%
1/20W
MF
201
53 65
12 53 65
12 53 65
12 53 65
12 53 65
12 53 65
12 53 65
12 53 65
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
CPU Power & Ground
CPU_VID<0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V5_S0_CPU
CPU_VID<4>
=PPVCORE_S0_CPU
CPU_VID<3>
CPU_VID<5>
CPU_VID<6>
CPU_VID<2>
CPU_VID<1>
=PPVCORE_S0_CPU
11 OF 110
4.4.0
051-8379
11 OF 73
8
10 11 12
8
10 11 12
8
12
8
11 12 64
8
11 12 64
Page 12
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PLACE ON OPPOSITE SIDE OF CPU
PLACE ON OPPOSITE SIDE OF CPU
CPU VCORE VID CONNECTIONS
VCCA (CPU AVdd) DECOUPLING
LAYOUT NOTE:
PLACE C1281 NEAR PIN B34 OF U1000
PLACE C1291-C1296 CLOSE TO FSB DATA PINS
PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS
PLACE C1290 CLOSE TO CPU
1x 270uF, 12x 2.2uF
VCCP (CPU I/O) DECOUPLING
1x 10uF, 1x 0.01uF
LAYOUT NOTE:
4x 270uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402
CPU VCORE HF AND BULK DECOUPLING
LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU
PLACE ON SAME SIDE AS CPU
LAYOUT NOTE:
LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU
LAYOUT NOTE:
LAYOUT NOTE:
LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU
PLACE ON OPPOSITE SIDE OF CPU
PLACE ON OPPOSITE SIDE OF CPU
LAYOUT NOTE:
LAYOUT NOTE:
2
1
C1210
CRITICAL
OMIT_TABLE
10UF
603
X5R
6.3V
20%
2
1
C1216
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1201
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1202
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1203
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1204
NOSTUFF
X5R
20%
6.3V
603
10UF
CRITICAL
2
1
C1205
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1206
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1207
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1208
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1209
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1229
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1228
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1227
10UF
603
X5R
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1226
20%
6.3V
X5R
603
10UF
CRITICAL
OMIT_TABLE
2
1
C1225
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1224
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1223
CRITICAL
OMIT_TABLE
10UF
603
X5R
6.3V
20%
2
1
C1214
20%
6.3V
X5R
603
10UF
CRITICAL
OMIT_TABLE
2
1
C1222
NOSTUFF
603
20%
6.3V
X5R
10UF
CRITICAL
2
1
C1221
NOSTUFF
CRITICAL
10UF
603
X5R
6.3V
20%
2
1
C1220
NOSTUFF
CRITICAL
10UF
603
X5R
6.3V
20%
2
1
C1231
NOSTUFF
CRITICAL
10UF
603
X5R
6.3V
20%
2
1
C1230
10UF
603
X5R
6.3V
20%
OMIT_TABLE
CRITICAL
2
1
C1249
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1259
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1248
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1258
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1247
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1246
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1257
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1256
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1245
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1244
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1255
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1254
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1243
OMIT_TABLE
CRITICAL
2.2UF
402-LF
CERM
6.3V
20%
2
1
C1253
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1242
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1241
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1252
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1251
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1240
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1250
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1267
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1266
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1265
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1264
CRITICAL
20%
6.3V
CERM
402-LF
2.2UF
OMIT_TABLE
2
1
C1263
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1262
20%
6.3V
CERM
402-LF
2.2UF
CRITICAL
OMIT_TABLE
2
1
C1261
2.2UF
402-LF
CERM
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1260
2.2UF
6.3V
402-LF
CRITICAL
CERM
20%
OMIT_TABLE
2
1
C1291
2.2UF
402-LF
CERM
6.3V
20%
OMIT_TABLE
2
1
C1292
2.2UF
402-LF
CERM
6.3V
20%
OMIT_TABLE
2
1
C1293
2.2UF
402-LF
CERM
6.3V
20%
OMIT_TABLE
2
1
C1294
OMIT_TABLE
2.2UF
402-LF
CERM
6.3V
20%
2
1
C1295
20%
6.3V
CERM
402-LF
2.2UF
OMIT_TABLE
2
1
C1296
OMIT_TABLE
2.2UF
402-LF
CERM
6.3V
20%
2
1
C1283
OMIT_TABLE
20%
6.3V
CERM
402-LF
2.2UF
2
1
C1288
20%
6.3V
CERM
402-LF
2.2UF
OMIT_TABLE
2
1
C1287
OMIT_TABLE
2.2UF
402-LF
CERM
6.3V
20%
2
1
C1286
20%
6.3V
CERM
402-LF
2.2UF
OMIT_TABLE
2
1
C1285
OMIT_TABLE
20%
6.3V
CERM
402-LF
2.2UF
2
1
C1284
OMIT_TABLE
2.2UF
402-LF
CERM
6.3V
20%
2
1
C1270
CRITICAL
270UF
TANT
CASE-B4-SM
20%
2V
2
1
C1272
CRITICAL
270UF
TANT
CASE-B4-SM
20%
2V
2
1
C1271
CASE-B4-SM
CRITICAL
2V
20%
TANT
270UF
2
1
C1290
CRITICAL
270UF
TANT
CASE-B4-SM
20%
2V
11 53 65 65
2
1
C1213
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1212
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1211
NOSTUFF
X5R
10UF
603
6.3V
20%
CRITICAL
2
1
C1219
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1200
NOSTUFF
20%
6.3V
X5R
603
10UF
CRITICAL
2
1
C1215
NOSTUFF
10UF
603
X5R
6.3V
20%
CRITICAL
2
1
C1217
10UF
603
X5R
6.3V
20%
CRITICAL
OMIT_TABLE
2
1
C1218
20%
6.3V
X5R
603
10UF
CRITICAL
OMIT_TABLE
2
1
C1281
10%
10V
X5R
201
0.01UF
2
1
C1280
OMIT_TABLE
20%
6.3V
X5R
603
10uF
SYNC_DATE=03/24/2010
SYNC_MASTER=K16_MLB
CPU Decoupling & VID
CPU_VID<0..6>
MAKE_BASE=TRUE
IMVP6_VID<0..6>
=PP1V05_S0_CPU
=PP1V5_S0_CPU
=PPVCORE_S0_CPU
12 OF 110
4.4.0
051-8379
12 OF 73
8
10 11
8
11
8
11 64
Page 13
IN
BI
BI
BI
BI
OUT
IN
BI
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
NC
IN
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
OBSDATA_B3 OBSDATA_D3
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDI
OBSDATA_A3
SCL
VCC_OBS_AB
OBSDATA_B1
OBSDATA_B0
OBSFN_B1
OBSDATA_A2
OBSFN_B0
PWRGD/HOOK0
HOOK3
SDA
OBSDATA_A0
518S0774
OBSFN_C1
NOTE: This is not the standard XDP pinout.
OBSDATA_B2
OBSDATA_A1
Direction of XDP adapter flex
Please place J1300 within 1" of
board edge with odd-numbered pins
facing edge. Avoid any tall
components between J1300 and edge.
TCK0
HOOK1
HOOK2
OBSDATA_C0
OBSFN_C0
OBSFN_D1
OBSDATA_D1
ITPCLK/HOOK4
VCC_OBS_CD
ITPCLK#/HOOK5
TMS
Use with 920-0782 Adapter Flex to support chipset debug.
TRSTn
TCK1
RESET#/HOOK6
OBSDATA_C3
TDO
OBSDATA_C1
OBSDATA_C2
OBSDATA_D0
OBSDATA_D2
OBSFN_A1
OBSFN_A0
XDP_PRESENT#
DBR#/HOOK7
OBSFN_D0
Micro2-XDP Connector
10 14 65
21
R1399
1K
XDP
1/20W
MF
201
5%
41
41
2
1
R1315
1%
XDP
54.9
201
1/20W
MF
2
1
C1300
XDP
10%
X5R
0.1UF
201
6.3V
2
1
C1301
201
6.3V
0.1UF
XDP
X5R
10%
10 65
10 65
10 65
10 14 65
21
R1303
PLACEMENT_NOTE=Place close to CPU to minimize stub.
5%
1K
XDP
1/20W
MF
201
10 65
10 65
10 65
10 65
14 65
14 65
10 65
10 65
10 65
10 25
19
10 65
19
9
87
60
6
59
5857
5655
5453
5251
50
5
49
4847
4645
4443
4241
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
J1300
F-ST-SM-HF
XDP_CONN
CRITICAL
DF40C-60DS-0.4V
eXtended Debug Port (Micro-XDP)
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
=PP3V3_S0_XDP
JTAG_MCP_TRST_L
JTAG_MCP_TDI
FSB_CLK_ITP_N
XDP_CPURST_L
XDP_DBRESET_L
XDP_TDO
XDP_TDI
XDP_TMS
FSB_CLK_ITP_P
FSB_CPURST_L
TP_XDP_OBSFN_B0
TP_XDP_OBSDATA_B0
XDP_BPM_L<4>
XDP_BPM_L<5>
=PP1V05_S0_XDP
XDP_OBS20
TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B3
JTAG_MCP_TMS
XDP_TRST_L
JTAG_MCP_TDO
TP_XDP_OBSDATA_C0
TP_XDP_OBSDATA_C1
TP_XDP_OBSDATA_C2
TP_XDP_OBSDATA_C3
TP_XDP_OBSDATA_D0
TP_XDP_OBSDATA_D1
TP_XDP_OBSDATA_D2
TP_XDP_OBSDATA_D3
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B1
XDP_TCK
PM_LATRIGGER_L
JTAG_MCP_TCK
XDP_PWRGDCPU_PWRGD
=I2C_XDP_SDA
=I2C_XDP_SCL
13 OF 110
4.4.0
051-8379
13 OF 73
8
19
19
65
8
19
19
Page 14
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BI
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BI
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BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
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IN
BI
OUT
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OUT
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OUT
OUT
OUT
OUT
OUT
OUT
OUT
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IN
BI
BI
OUT
IN
IN
IN
IN
IN
IN
IN
CPU_A8*
CPU_DSTBN0*
CPU_DSTBP1*
CPU_D6*
CPU_D3*
CPU_D5*
CPU_D2*
CPU_D1*
CPU_DSTBP2*
CPU_DSTBN2*
CPU_DBI2*
CPU_D4*
CPU_DBI0*
CPU_DSTBP0*
CPU_DSTBN1*
CPU_DBI1*
CPU_DSTBP3*
CPU_DSTBN3*
CPU_DBI3*
CPU_A4*
CPU_A5*
CPU_A7*
CPU_A6*
CPU_A9*
CPU_A10*
CPU_A11*
CPU_A12*
CPU_A14*
CPU_A15*
CPU_A16*
CPU_A17*
CPU_A18*
CPU_A19*
CPU_A22*
CPU_A25*
CPU_A24*
CPU_A23*
CPU_A26*
CPU_A27*
CPU_A28*
CPU_A29*
CPU_A30*
CPU_A33*
CPU_A32*
CPU_A31*
CPU_A34*
CPU_A35*
CPU_A3*
CPU_ADSTB0*
CPU_ADSTB1*
CPU_REQ1*
CPU_REQ0*
CPU_REQ2*
CPU_REQ3*
CPU_REQ4*
CPU_ADS*
CPU_BNR*
CPU_DBSY*
CPU_BR0*
CPU_HITM*
CPU_HIT*
CPU_DRDY*
CPU_TRDY*
CPU_LOCK*
CPU_PROCHOT*
CPU_THERMTRIP*
CPU_FERR*
CPU_BSEL0
CPU_RS0*
CPU_RS1*
CPU_RS2*
BCLK_VML_COMP_GND
BCLK_VML_COMP_VDD
CPU_PECI
CPU_BSEL2
CPU_BSEL1
CPU_COMP_VCC
CPU_COMP_GND
CPU_D16*
CPU_D0*
CPU_D54*
CPU_D60*
CPU_D61*
CPU_D40*
CPU_D27*
CPU_D26*
CPU_D25*
CPU_D24*
CPU_D22*
CPU_D20*
CPU_D21*
CPU_D7*
CPU_D8*
CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*
CPU_D17*
CPU_D18*
CPU_D19*
CPU_D23*
CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*
CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*
CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*
BCLK_IN_P
BCLK_OUT_ITP_P
CPU_DEFER*
CPU_BPRI*
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
BCLK_OUT_ITP_N
BCLK_OUT_NB_P
BCLK_OUT_NB_N
BCLK_IN_N
CPU_IGNNE*
CPU_A20M*
CPU_INIT*
CPU_INTR
CPU_NMI
CPU_SMI*
CPU_DPRSLPVR
CPU_DPRSTP*
CPU_STPCLK*
CPU_DPSLP*
CPU_DPWR*
CPU_SLP*
CPU_RESET*
CPU_PWRGD
CPU_A21*
CPU_D63*
CPU_D62*
CPU_A20*
CPU_A13*
SYMBOL 1 OF 11
FSB
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Loop-back clock for delay matching.
9
9
9
10 65
10 13 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
7
10 65
10 65
10 65
10 65
10 65
10 65
10 65
13 65
13 65
10 65
10 65
10 65
10 65
10 65
10 65
10 65
10 65
10 13 65
10 65
10 65
10 65
10 65
10 53 65
9
10 39 65
10 39 65
7
10 65
7
10 65
2
1
R1436
49.9
MF
1/20W
201
1%
2
1
R1431
MF
1/20W
201
1%
49.9
2
1
R1430
MF
1/20W
201
49.9
1%
2
1
R1435
MF
1/20W
201
49.9
1%
2
1
R1415
MF
1/20W
201
62
5%
2
1
R1410
MF
1/20W
201
54.9
1%
2
1
R1440
MF
1/20W
201
150
NO STUFF
5%
53 65
7
10 65
7
10 65
10 65
10 65
10 65
10 65
7
10 65
AG32
V35
Y34
AC35
V34
AF34
AD33
AF33
AC34
V36
U37
V38
U39
U40
AA32
V32
AG36
AA35
AG37
Y35
Y33
V33
AD32
AD34
AC33
C37
J37
R34
J38
C38
J36
R35
J39
U32
U33
Y32
AA34
D2
AG35
AF35
B35
L35
U36
F39
L37
H40
P40
D38
A36
D36
B37
M40
A35
C35
E37
B38
C36
A37
E38
C39
E40
D40
L40
E36
D39
J35
H37
F37
M34
L36
H34
H35
J34
L39
M32
M36
M33
L34
M35
L33
F36
H36
R39
R32
L38
P32
P33
P36
P38
P37
P34
R40
U34
R33
R38
P39
P35
R37
R36
U35
J40
H39
M38
H38
F40
F38
M39
M37
AK38
AK37
D35
E35
F35
AG34
AF32
AD35
AF38
Y37
AG33
V39
Y40
Y39
V40
Y36
V37
AG38
AG40
AJ40
AF37
AD36
AD39
U38
AG39
AF40
AF36
AC39
AD40
AC37
AC40
AJ39
AD37
AA33
AJ38
AC38
AD38
AF39
AA38
AA40
AC36
Y38
AA37
AA36
AA39
AK39
AK40
AJ35
AJ34
AK32
AK33
AJ37
AJ36
AJ33
AJ32
U1400
BGA
MCP89U-A01
OMIT_TABLE
SYNC_MASTER=K16_MLB
MCP CPU Interface
SYNC_DATE=07/07/2010
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<11>
FSB_A_L<10>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<5>
FSB_A_L<6>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_A_L<14>
FSB_A_L<18>
FSB_A_L<4>
FSB_DINV_L<1>
FSB_D_L<12>
FSB_A_L<3>
FSB_DINV_L<3>
FSB_CLK_MCP_N
FSB_CLK_MCP_P
FSB_DEFER_L
CPU_A20M_L
FSB_D_L<52>
FSB_CLK_ITP_N
MCP_CPU_COMP_GND
MCP_CPU_COMP_VCC
MCP_BCLK_VML_COMP_GND
FSB_ADSTB_L<0>
FSB_A_L<32>
FSB_ADSTB_L<1>
FSB_A_L<31>
FSB_A_L<30>
FSB_A_L<29>
FSB_REQ_L<1>
FSB_A_L<35>
FSB_REQ_L<0>
FSB_BREQ0_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_DPRSTP_L
FSB_BNR_L
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<41>
=PP1V05_S0_MCP_FSB
=PP1V05_S0_MCP_FSB
FSB_D_L<62>
FSB_D_L<63>
FSB_DPWR_L
CPU_DPSLP_L
CPU_STPCLK_L
PM_DPRSLPVR
CPU_NMI
CPU_INTR
CPU_INIT_L
FSB_D_L<57>
FSB_D_L<55>
FSB_D_L<53>
FSB_D_L<50>
FSB_D_L<47>
FSB_D_L<46>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
FSB_D_L<32>
FSB_D_L<30>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<23>
FSB_D_L<19>
FSB_D_L<18>
FSB_D_L<17>
FSB_D_L<15>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<11>
FSB_D_L<10>
FSB_D_L<9>
FSB_D_L<8>
FSB_D_L<7>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<22>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<60>
FSB_D_L<54>
FSB_D_L<0>
FSB_D_L<16>
=MCP_BSEL<1>
=MCP_BSEL<2>
CPU_PECI_MCP
MCP_BCLK_VML_COMP_VDD
FSB_RS_L<2>
FSB_RS_L<1>
FSB_RS_L<0>
=MCP_BSEL<0>
PM_THRMTRIP_L
CPU_PROCHOT_L
FSB_LOCK_L
FSB_TRDY_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_ADS_L
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_A_L<28>
FSB_A_L<26>
FSB_A_L<19>
FSB_A_L<16>
FSB_A_L<15>
FSB_DSTB_L_N<1>
FSB_D_L<4>
FSB_DSTB_L_N<2>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<5>
FSB_D_L<3>
FSB_D_L<6>
FSB_DSTB_L_P<1>
FSB_DINV_L<0>
FSB_D_L<40>
FSB_D_L<42>
FSB_D_L<49>
FSB_D_L<56>
FSB_D_L<58>
FSB_D_L<59>
FSB_CLK_ITP_P
FSB_CLK_CPU_N
FSB_CLK_CPU_P
FSB_A_L<34>
FSB_BPRI_L
FSB_D_L<51>
FSB_D_L<48>
FSB_D_L<45>
CPU_IGNNE_L
CPU_SMI_L
FSB_CPURST_L
FSB_D_L<37>
FSB_D_L<61>
CPU_FERR_L
FSB_DBSY_L
FSB_A_L<33>
FSB_A_L<24>
FSB_A_L<27>
FSB_A_L<25>
FSB_A_L<23>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<20>
FSB_D_L<31>
FSB_A_L<17>
14 OF 110
4.4.0
051-8379
14 OF 73
65
65
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65
65
8
14 20 23
8
14 20 23
65
Page 15
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BI
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BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
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OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
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BI
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BI
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BI
BI
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BI
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BI
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OUT
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OUT
OUT
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OUT
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OUT
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OUT
OUT
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OUT
OUT
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OUT
OUT
OUT
OUT
OUT
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OUT
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OUT OUT
OUT
OUT
OUT
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OUT
OUT
MCKE0A_0
MCKE0A_1
MCS0A_0*
MCS0A_1*
+VIO_PLL_CPU
+VIO_PLL_CPU
+VIO_PLL_CPU
+VIO_PLL_FSB
+VIO_PLL_FSB
+VIO_PLL_FSB
+VIO_PLL_MEM
+VIO_PLL_MEM
+VIO_M2CLK_DLL
+VIO_M2CLK_DLL
+VIO_M2CLK_DLL
MA0_0
MA0_8
MA0_9
MA0_10
MCAS0*
MBA0_0
MA0_15
MA0_14
MBA0_2
MBA0_1
MWE0*
MRAS0*
MDQS0_0_N
MDQS0_0_P
MDQS0_1_N
MDQS0_1_P
MDQS0_2_N
MDQS0_2_P
+VIO_PLL_MEM
MCLK0A_1_P
MCLK0A_1_N
MODT0A_1
MODT0A_0
MA0_1
MA0_2
MA0_3
MA0_4
MA0_5
MA0_6
MA0_7
MA0_11
MA0_12
MA0_13
MDQS0_3_N
MDQS0_3_P
MDQS0_4_N
MDQS0_5_N
MDQS0_5_P
MDQS0_4_P
MDQS0_7_N
MDQS0_7_P
MDQS0_6_P
MDQM0_5
MDQM0_6
MDQM0_7
MDQ0_60
MDQ0_55
MDQ0_56
MDQ0_52
MDQ0_51
MDQ0_15
MDQ0_48
MDQ0_40
MDQ0_39
MDQM0_2
MDQM0_3
MDQM0_1
MDQM0_0
MDQM0_4
MDQ0_0
MDQ0_1
MDQ0_2
MDQ0_3
MDQ0_4
MDQ0_5
MDQ0_6
MDQ0_10
MDQ0_9
MDQ0_7
MDQ0_8
MDQ0_11
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_16
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_26
MDQ0_25
MDQ0_23
MDQ0_22
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_41
MDQ0_38
MDQ0_37
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_47
MDQ0_50
MDQ0_49
MDQ0_54
MDQ0_53
MDQ0_57
MDQ0_59
MDQ0_58
MDQ0_24
MDQ0_61
MDQ0_62
MDQ0_63
MDQS0_6_N
MCLK0A_0_N
MCLK0A_0_P
MEMORY PARTITION 0
SYMBOL 2 OF 11
MRESET0*
MDQM1_0
MDQM1_1
MDQM1_2
MDQM1_3
MDQM1_4
MDQM1_5
MDQM1_6
MDQM1_7
MDQ1_59
MDQ1_61
MDQ1_60
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MRAS1*
MDQ1_47
MDQ1_43
MDQ1_58
MDQS1_0_N
MDQS1_2_P
MDQS1_3_N
MDQ1_0
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_11
MDQ1_12
MDQ1_13
MDQ1_14
MDQ1_15
MDQ1_16
MDQ1_17
MDQ1_18
MDQ1_19
MDQ1_20
MDQ1_21
MDQ1_22
MDQ1_23
MDQ1_24
MDQ1_25
MDQ1_26
MDQ1_27
MDQ1_28
MDQ1_29
MDQ1_30
MDQ1_31
MDQ1_33
MDQ1_34
MDQ1_35
MDQ1_36
MDQ1_37
MDQ1_38
MDQ1_39
MDQ1_40
MDQ1_41
MDQ1_42
MDQ1_44
MDQ1_45
MDQ1_46
MDQ1_48
MDQ1_49
MDQ1_50
MDQ1_51
MDQ1_52
MDQ1_53
MDQ1_54
MDQ1_55
MDQ1_56
MDQ1_57
MDQ1_62
MDQ1_63
MA1_14
MA1_15
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_2_N
MDQ1_32
MEM_COMP_GND
MEM_COMP_VDD
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
MDQ1_4
MDQ1_5
MDQ1_6
MDQ1_7
MDQ1_8
MDQ1_9
MDQ1_10
MCLK1A_1_P
MCLK1A_1_N
MCLK1A_0_P
MCLK1A_0_N
MCS1A_0*
MCS1A_1*
MODT1A_0
MODT1A_1
MCKE1A_0
MCKE1A_1
MWE1*
MCAS1*
MBA1_1
MBA1_2
MBA1_0
SYMBOL 3 OF 11
MEMORY PARITION 1
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
550 mA
25 mA
25 mA
20 mA 70 mA
27 66
27 66
27 66
27 66
26 66
26 66
26 66
26 66
26 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
9
66
9
66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
26 27 32 66
21 26 27 32 66
21 26 27 32 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
27 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
26 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
28 66
29 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
28 29 32 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
29 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
28 66
29 66
28 66
29 66
29 66
29 66
28 66
28 66
28 66
28 66
9
66
9
66
21 28 29 32 66
21 28 29 32 66
9
66
9
66
28 29 32 66
28 29 32 66
26 27 28 29
2
1
R1520
MF
1/20W
201
1K
5%
2
1
R1511
MF
1/20W
201
40.2
1%
2
1
R1510
MF
1/20W
201
1%
40.2
AJ31
AH30
AH29
AF31
AF30
AF29
AG31
AG30
AG29
AK31
AK30
AJ30
AM18
AR17
AP14
AN17
AR4
AR5
AT6
AU6
AN11
AM11
AT12
AR12
AR29
AP29
AR32
AP32
AV36
AU36
AN35
AN34
AN5
AM9
AR9
AM14
AT29
AN32
AT36
AN37
AV37
AU38
AR35
AN6
AN4
AT4
AU3
AN36
AM7
AN7
AT5
AT3
AU5
AV5
AR6
AN9
AV3
AV4
AM35
AM8
AN8
AP8
AP9
AN12
AT11
AT8
AR8
AT9
AM12
AM34
AP12
AN14
AT14
AR14
AR11
AP11
AM15
AN15
AR27
AT27
AR36
AM30
AN30
AN27
AP27
AN29
AM29
AT30
AT32
AP33
AR33
AR37
AP30
AR30
AM33
AN33
AU35
AV35
AT37
AT38
AT33
AT35
AM36
AM37
AP15
AN18
AM21
AN21
AM20
AN20
AM27
AM26
AM17
AR26
AR18
AP17
AP24
AN24
AR23
AM23
AM24
AN23
AR21
AP20
AN26
AP26
AR15
AR24
AP23
AP18
AP21
AR20
U1400
BGA
MCP89U-A01
OMIT_TABLE
AY18
AM6
AW18
AT17
AW17
AL24
AL23
AN2
AN3
AY5
AY4
AV11
AW11
AV14
AW14
AW27
AY27
AV32
AW32
AY37
AY36
AN38
AN39
AR3
AY6
AV9
AY14
AV27
AU30
AW37
AR38
AW38
AV38
AR40
AM1
AN1
AT1
AU1
AR39
AM3
AM2
AR2
AR1
AW3
AW4
AU8
AV8
AU2
AV2
AM39
AW6
AV6
AY9
AW9
AY11
AY12
AW8
AY8
AU9
AU11
AM38
AU12
AU14
AV15
AU15
AW12
AV12
AY15
AW15
AW26
AY26
AT40
AV29
AW29
AU26
AV26
AU27
AU29
AW30
AV30
AY33
AW33
AU40
AY29
AY30
AU32
AY32
AW35
AY35
AV39
AU39
AV33
AU33
AN40
AM40
AT15
AY17
AV20
AW20
AT20
AU20
AT24
AT26
AV17
AW24
AT18
AV18
AY23
AU23
AV23
AT21
AT23
AU21
AV21
AY21
AU24
AV24
AU17
AY24
AW23
AU18
AW21
AY20
U1400
BGA
MCP89U-A01
OMIT_TABLE
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
MCP Memory Interface
=PP1V5R1V35_S3_MCP_MEM
=PP1V5R1V35_SW_MCP_MEM
MEM_A_DQS_N<6>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<24>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<57>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<47>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<41>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<16>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_DM<4>
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<48>
MEM_A_DQ<15>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<60>
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_BA<0>
MEM_A_CAS_L
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<0>
=PP1V05_S0_MCP_M2CLK_DLL
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_B_BA<0>
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_ODT<1>
MEM_B_ODT<0>
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
MEM_B_DQ<32>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_A<15>
MEM_B_A<14>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<0>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<0>
MEM_B_DQ<58>
MEM_B_DQ<43>
MEM_B_DQ<47>
MEM_B_RAS_L
MEM_B_DQS_P<0>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<59>
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
MEM_RESET_L
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_B_DQ<16>
MEM_A_CLK_N<1>
PP1V05_S0_MCP_PLL_FSBMEM
MEM_A_CLK_P<1>
15 OF 110
4.4.0
051-8379
15 OF 73
8
20 21 23
8
23
66
66
23
Page 16
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
PEC_CLKREQ*/GPIO_51
PE2_REFCLK_P
PE2_REFCLK_N
PEA_CLKREQ*/GPIO_49
PEB_CLKREQ*/GPIO_50
PE0_REFCLK_P
PE0_REFCLK_N
PE1_REFCLK_P
PE1_REFCLK_N
PE_WAKE*
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE1_TX0_P
PE1_TX0_N
PE1_TX1_P
PE1_TX1_N
PEX_RST*
PEX0_TERM_P
PE0_RX4_P
PE0_RX4_N
PE0_RX5_N
PE0_RX5_P
PE1_RX0_P
PE1_RX0_N
PE1_RX1_P
PE1_RX1_N
+3.3V_PLL_HVDD
+VIO_PLL_PE
+VIO_PLL_PE
+VIO_PLL_PE
+VIO_PLL_XREF_XS
+VIO_PLL_XREF_XS
+VIO_PLL_XREF_XS
+VIO_PLL_SATA
+VIO_PLL_SATA
+VIO_PLL_SATA
+VIO_PLL_H
+VIO_PLL_H
PCI EXPRESS
SYMBOL 4 OF 11
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1
PE1 ports are Gen1-only. 2 RCs: x1, x1
+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND
If PE0[3:0] are not used,
+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND
If PE0[4:5] and PE1[0:1] are not used,
2
1
R1610
1/20W
MF
201
2.49K
1%
PLACE_NEAR=U1400.U5:12.7 mm
7
34
34
9
9
9
9
7
34 67
7
34 67 34 67
34 67
25
7
34 67
7
34 67
9
67
9
67
9
9
9
9
9
2
1
R1600
MF
1/20W
201
5%
22K
U6
U5
U4
U1
V1
U7
U3
U2
Y8
Y9
AA2
AA3
Y7
Y6
AA4
AA5
V2
V3
AA7
AA6
Y3
Y2
AA9
AA8
Y4
Y5
V5
V4
AH12
AH11
AH10
AF12
AE11
AE10
AG12
AG11
AG10
AF11
AF10
W10
U1400
MCP89U-A01
BGA
OMIT_TABLE
9
MCP PCIe Interfaces
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
PEG_CLK100M_N
ENET_CLKREQ_L
AP_CLKREQ_L
PEG_CLKREQ_L
=PEG_D2R_N<4>
PCIE_AP_D2R_N
PP1V05_S0_MCP_PLL_PEXSATA
=PEG_D2R_N<5>
TP_PCIE_PE4_R2D_CN
TP_PCIE_PE4_R2D_CP
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
TP_PCIE_PE1_D2RN
PCIE_AP_D2R_P
PP3V3_S0_MCP_PLL_HVDD
=PEG_D2R_P<5>
=PEG_D2R_P<4>
TP_PCIE_PE1_D2RP
TP_PCIE_CLK100M_PE2N
TP_PCIE_CLK100M_PE2P
PCIE_RESET_L
PEG_CLK100M_P
PCIE_CLK100M_AP_P
PCIE_WAKE_L
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
PCIE_CLK100M_AP_N
MCP_PEX0_TERMP
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
16 OF 110
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051-8379
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Page 17
OUT
IN
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IFPA_TXD0_N
IFPA_TXD0_P
DDC_DATA0/GPIO_39
DDC_CLK0/GPIO_38
RGB_DAC_VREF
+3.3V_RGBDAC
IFPA_TXD1_P
IFPA_TXD1_N
DDC_CLK1/GPIO_40
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_N
IFPB_TXD7_P
IFPA_TXC_P
IFPA_TXC_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
DP1_0_P/TMDS0_TX5_P
DP1_0_N/TMDS0_TX5_N
DP1_1_N/TMDS0_TX4_N
DP1_2_N/TMDS0_TX3_N
DP1_1_P/TMDS0_TX4_P
DP0_3_P/TMDS0_TXC_P
DDC_DATA1/GPIO_41
DP1_2_P/TMDS0_TX3_P
DP1_3_N/TMDS0B_TXC_N
DP1_3_P/TMDS0B_TXC_P
DP0_0_N/TMDS0_TX2_N
DP0_0_P/TMDS0_TX2_P
DP0_1_N/TMDS0_TX1_N
DP0_1_P/TMDS0_TX1_P
DP0_2_N/TMDS0_TX0_N
DP0_2_P/TMDS0_TX0_P
DP0_3_N/TMDS0_TXC_N
HPLUG_DET0/GPIO_20
HPLUG_DET1/GPIO_21
HPLUG_DET2/GPIO_22
DDC_DATA2/DP_AUX_CH0_N
DDC_CLK2/DP_AUX_CH0_P
DDC_DATA3/DP_AUX_CH1_N
DDC_CLK3/DP_AUX_CH1_P
LCD_BKL_ON/GPIO_59
LCD_BKL_CTL/GPIO_57
LCD_PANEL_PWR/GPIO_58
IFPAB_VPROBE
IFPAB_RSET
TMDS0_VPROBE
TMDS0_RSET
+3.3V_PLL_DP0
+3.3V_PLL_DP0
+3.3V_PLL_USB
+3.3V_PLL_USB
+VIO_PLL_IFPAB
+VIO_PLL_IFPAB
+VIO_PLL_CORE_LEG
+VIO_PLL_CORE_LEG
+VIO_PLL_SPPLL0
+VIO_PLL_V
+VIO_PLL_SPPLL0
+VIO_PLL_V
+VIO_PLL_NV
+VIO_PLL_NV
+VDD_IFPA
+VDD_IFPB
+VIO_DP0
+VIO_DP0
+VIO_DP0
FLAT PANEL
RGB
SYMBOL 5 OF 11
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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8 7 5 4 2 1
=MCP_IFPB_TXD_P/N<0>
=MCP_IFPAB_DDC_CLK
GPIO Pull-Ups
Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
NOTE: DP_AUX_CH1 also requires pull-downs if used for
dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then
210 mA
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).
NOTE: No Composite/S-Video/Component Video support on MCP89
TMDS/HDMI
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
LVDS_IG_A_CLK_P/N
LVDS
Interface Mode
LVDS_IG_A_DATA_P/N<0>
LVDS_IG_A_DATA_P/N<1>
60 mA
40 mA
160 mA
140 mA
180 mA
30 mA
180 mA
(GMUX_INT)
LVDS_IG_A_DATA_P/N<2>
LVDS_IG_A_DATA_P/N<3>
LVDS_IG_B_CLK_P/N
LVDS_IG_B_DATA_P/N<0>
LVDS_IG_B_DATA_P/N<1>
LVDS_IG_B_DATA_P/N<2>
LVDS_IG_B_DATA_P/N<3>
LVDS_IG_DDC_DATA
LVDS_IG_DDC_CLK
TMDS_IG_TXD_P/N<5>
TMDS_IG_DDC_DATA
TMDS_IG_DDC_CLK
TMDS_IG_TXD_P/N<4>
TMDS_IG_TXD_P/N<2>
TMDS_IG_TXD_P/N<3>
RGB DAC Disable:
Connect +3.3V_RGBDAC pin to GND.
(UNUSED)
(UNUSED)
(UNUSED)
LVDS: Power +VDD_IFPx at 1.8V
=MCP_IFPA_TXD_P/N<3>
=MCP_IFPA_TXD_P/N<2>
=MCP_IFPA_TXD_P/N<1>
=MCP_IFPA_TXD_P/N<0>
TMDS: Power +VDD_IFPx at 3.3V
=MCP_IFPB_TXD_P/N<1>
=MCP_IFPB_TXD_P/N<2>
=MCP_IFPB_TXD_P/N<3>
=MCP_IFPAB_DDC_DATA
=MCP_IFPA_TXC_P/N
=MCP_IFPB_TXC_P/N
MCP Signal
only pull-ups are necessary.
DDC Mode Pull-downs
160 mA
60 mA
20 mA
NOTE: 100K pull-downs required if
HPLUG_DET0/HPLUG_DET1 are not used.
40 mA
17
9
9
9
17 67
9
67
9
67
9
67
9
67
9
67
9
67
9
67
9
67
24 67
24 67
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
59
24 67
24 67
9
9
9
9
9
67
9
67
9
67
9
67
9
17 67
9
17 67
9
17 67
9
9
9
9
9
9
9
9
9
9
7
17 37
17
21
R1782
10K
5%
1/20W
MF 201
21
R1781
10K
5%
1/20W
MF 201
21
R1780
10K
5%
1/20W
MF 201
21
R1711
5%
100K
1/20W
MF 201
21
R1710
5%
100K
1/20W
MF 201
H29
K27
J29
M28
L28
M27
L27
M24
L24
M25
L25
M26
L26
A26
A27
B26
A24
A23
K30
M22
L22
M23
L23
A30
C30
B30
J26
K26
C24
B24
E24
D24
G24
F24
J24
H24
C21
B21
H23
J23
F23
G23
D23
E23
B23
C23
K24
K23
E30
D30
C29
F27
G27
E27
D27
C27
B27
A29
B29
H27
J27
D26
C26
F26
E26
H26
G26
F29
D29 H30
F30
G29
E29 J30
G30
U1400
CKPLUS_WAIVE=PwrTerm2Gnd
CKPLUS_WAIVE=PwrTerm2Gnd
BGA
MCP89U-A01
OMIT_TABLE
21
R1712
5%
100K
1/20W
MF 201
21
R1713
5%
100K
1/20W
MF 201
MCP Graphics
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
DP_IG_AUX_CH1_P
PP3V3_S0_MCP_PLL_DP_USB
DP_IG_AUX_CH1_N
PP1V05_S0_MCP_PLL_CORE
=PP1V05_S0_MCP_PLL_IFP
=MCP_IFPB_TXD_N<2>
=MCP_IFPB_TXD_P<3>
DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N
DP_IG_AUX_CH1_P
MCP_TMDS0_RSET
MCP_TMDS0_VPROBE
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
LCD_IG_PWR_EN
LCD_IG_BKLT_EN
LCD_IG_BKLT_PWM
=MCP_IFPAB_DDC_DATA
=MCP_IFPAB_DDC_CLK
=MCP_IFPB_TXD_N<3>
=MCP_IFPB_TXD_P<2>
=MCP_IFPB_TXD_N<1>
=MCP_IFPB_TXD_P<1>
=MCP_IFPB_TXD_N<0>
=MCP_IFPB_TXD_P<0>
=MCP_IFPB_TXC_P
=MCP_IFPB_TXC_N
=MCP_IFPA_TXD_N<3>
=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<2>
=MCP_IFPA_TXD_P<2>
=MCP_IFPA_TXD_N<1>
=MCP_IFPA_TXD_P<1>
=MCP_IFPA_TXD_N<0>
=MCP_IFPA_TXD_P<0>
=MCP_IFPA_TXC_N
=MCP_IFPA_TXC_P
=PP1V05_S0_MCP_DP0_VDD
DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N
SATARDRVR_A_EN
DP_IG_HPD1
DP_IG_HPD0
DP_IG_ML1_N<0>
DP_IG_ML1_P<0>
DP_IG_ML1_P<1>
DP_IG_ML1_N<1>
DP_IG_ML1_N<2>
DP_IG_ML1_P<2>
DP_IG_ML1_N<3>
DP_IG_ML1_P<3>
DP_IG_ML0_N<0>
DP_IG_ML0_P<0>
DP_IG_ML0_P<1>
TP_MCP_RGB_DAC_VREF
PP3V3_S0_MCP_DAC
DP_IG_ML0_P<3>
DP_IG_ML0_N<3>
DP_IG_ML0_N<2>
DP_IG_ML0_P<2>
DP_IG_ML0_N<1>
=PP3V3R1V8_S0_MCP_IFP_VDD
DP_IG_AUX_CH1_N
AUD_IP_PERIPHERAL_DET
MIKEY_MIC_LOAD_DET
=PP3V3_S0_MCP_GPIO
SATARDRVR_A_EN
AUD_IP_PERIPHERAL_DET
MIKEY_MIC_LOAD_DET
17 OF 110
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051-8379
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9
17 67
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17 67
8
24
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24
24
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17 67
7
17 37
17
8
18 19
17
Page 18
IN
BI
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
USB0_P
USB0_N
SATA_A1_TX_P
SATA_A1_TX_N
SATA_A1_RX_P
SATA_LED*/GPIO_30
SATA_TERMP
USB1_P
USB1_N
USB2_P
USB2_N
USB3_N
USB6_P
USB7_P
USB7_N
USB4_P
USB4_N
USB5_P
USB5_N
USB_OC0*/GPIO_25
USB_OC1*/GPIO_26
USB_RBIAS_GND
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXCTL
RGMII_RXCLK
RGMII_INTR/GPIO_35
+3.3V_PLL_MAC_DUAL
RGMII_COMP_VDD
RGMII_COMP_GND
RGMII_VREF
RGMII_TXD3
RGMII_TXCLK
RGMII_TXCTL
RGMII_MDC
RGMII_MDIO
RGMII_RESET*
RGMII_RXD3
BUF_25MHZ
RGMII_TXD2
RGMII_TXD1
RGMII_TXD0
USB3_P
USB6_N
SATA_A0_TX_P
SATA_A0_TX_N
SATA_A0_RX_N
SATA_A0_RX_P
NC
SATA_A1_RX_N
LAN
SYMBOL 6 OF 11
USB
SATA
BI
BI
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Bluetooth
Internal 19.5K Pull-Downs on all USB pairs
OHCI1/EHCI1
USB JTAG in S3/S4/S5.
Only USB8-11 support nV
Connect RGMII_RXD<0:3> together to 10K pull-down.
Connect RGMII_RXCLK to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_MDIO to 10K pull-down.
Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
20 mA
Internal MAC Disable:
All other pins can be left TP or NC.
AirPort (PCIe Mini-Card)
Camera/External E
External C
External A
EXTERNAL D
SD Card/ExpressCard
OHCI0/EHCI0
Geyser Trackpad/Keyboard
9
9
69
9
69
9
69
9
69
9
69
9
69
9
69
2
1
R1810
MF
1/20W
201
49.9
1%
2
1
R1811
MF
1/20W
201
1%
49.9
7
37 68
7
37 68
46 68 71
46 68 71
9
68
9
68
2
1
R1850
8.2K
MF
1/20W
201
5%
2
1
R1851
201
MF
8.2K
1/20W
5%
7
37 68
7
37 68
9
68
9
68
9
68
9
68
36 68
36 68
2
1
R1860
201
1%
1/20W
887
MF
9
67
9
67
9
67
9
67
35 67
35 67
35 67
35 67
2
1
R1805
MF
1/20W
201
2.49K
1%
9
2
1
R1800
MF
1/20W
201
5%
100K
L19
G12
H14
H20
J20
G20
F20
H21
J21
A20
A21
L21
K21
E20
D20
F21
G21
E21
D21
AG4
AG5
AF2
AF3
AF4
AF5
AF1
AG1
AG2
AG3
B15
D15
J17
F17
F15
C14
G14
G15
C17
H17
C15
A15
D17
G17
H18
E15E17
K15
K14
J18
AK36
H15
AM4
V6
G5
J14
U1400
OMIT_TABLE
BGA
MCP89U-A01
7
34 68
7
34 68
MCP SATA, USB & Ethernet
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
USB_TPAD_P
MCP_USB_RBIAS_GND
USB_BT_N
USB_EXTD_OC_L
ENET_CLK125M_RXCLK
ENET_RXD<0>
ENET_RXD<2>
ENET_ENERGY_DET
ENET_RX_CTRL
MXM_GOOD_L
MCP_MII_COMP_GND
ENET_MDIO
TP_ENET_RESET_L
TP_MCP_CLK25M_BUF0_R
TP_ENET_MDC
TP_ENET_TX_CTRL
TP_ENET_CLK125M_TXCLK
TP_ENET_TXD<2>
TP_ENET_TXD<3>
TP_ENET_TXD<0>
TP_ENET_TXD<1>
USB_EXTD_P
SATA_HDD_D2R_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
USB_EXTD_N
USB_TPAD_N
USB_EXTC_P
USB_MINI_P
USB_MINI_N
USB_EXTA_N
USB_EXTA_P
ENET_RXD<3>
=PP3V3_ENET_MCP_RMGT
MCP_MII_COMP_VDD
PP3V3_ENET_MCP_PLL_MAC
MCP_SATA_TERMP
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
ENET_RXD<1>
=PP3V3_S0_MCP_GPIO
MCP_RGMII_VREF
=PP3V3_S5_MCP_GPIO
USB_EXTA_OC_L
USB_CAMERA_P
USB_CAMERA_N
USB_SDCARD_P
USB_SDCARD_N
USB_BT_P
USB_EXTC_N
18 OF 110
4.4.0
051-8379
18 OF 73
68
7
37
69
8
20 23
69
23
67
8
17 19
8
19
36
Page 19
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
BI
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
BI
OUT
OUT
BI
BI
BI
BI
IN
IN
BI
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
BI
OUT
IN
PKG_TEST2
PKG_TEST
TEST_MODE_EN
SUS_CLK/GPIO_34
XTALOUT_RTC
XTALIN_RTC
XTALIN
XTALOUT
JTAG_TCK
JTAG_TRST*
JTAG_TDO
JTAG_TMS
JTAG_TDI
MGPU_PIO3/GPIO_24
MGPU_PIO1/GPIO_7
MGPU_PIO2/GPIO_23
MGPU_PIO0/GPIO_6
INTRUDER*
MEMVTT_EN/GPIO_45
MCP_MEMVDD_EN/GPIO_44
PWRGD
RTC_RST*
PWRGD_SB
RSTBTN*
PWRBTN*
KBRDRSTIN*/GPIO_56
A20GATE/GPIO_55
SIO_PME*/GPIO_31
EXT_SMI*/GPIO_32
SMB_ALERT*/GPIO_64
SMB_DATA1/MSMB_DATA
SMB_CLK1/MSMB_CLK
SMB_DATA0
SMB_CLK0
THERM_DIODE_N
THERM_DIODE_P
SPKR/GPIO_1
SPI_DO/GPIO_09
SPI_DI/GPIO_08
MCP_VID3/GPIO_16
MCP_VID2/GPIO_15
SLP_RMGT*
SLP_S3*
FANRPM1/GPIO_63/MGPIO_3
FANCTL1/GPIO_62
FANCTL0/GPIO_61
FANRPM0/GPIO_60/MGPIO_2
MISC_VDDEN4/GPIO_19
MEM_VDD_SEL/GPIO_46
MISC_VDDEN3/GPIO_18
MISC_VDDEN2/GPIO_17
MISC_VDDEN1/GPIO_48
MISC_VDDEN0/GPIO_47
LPC_DRQ0*/GPIO_43
LPC_AD1
LPC_AD2
LPC_AD3
LPC_CLKRUN*/GPIO_42
LPC_SERIRQ
LPC_AD0
HDA_PULLDN_COMP
HDA_SYNC
HDA_RESET*
HDA_BITCLK
HDA_SDATA_OUT
HDA_SDATA_IN0
LPC_FRAME*
+VDD_HDA
SLP_S5*
MCP_WAKE_DIS*
MCP_WAKE_REQ*
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
SPI_CLK/GPIO_11
SPI_CS0*/GPIO_10
LPC_RESET*
LPC_CLK0
HDA
LPC
SYMBOL 7 OF 11
MISC
OUT
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Platform-Specific Connections
behavior of Inte’s SLP_S4# signal
NOTE: MCP SLP_S5# signal has the
Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
0 = USER mode (Normal boot mode)
FIXME: AUD_IPHS_SWITCH_EN WAS GPIO_2
internal ~9K
pull-up.
(IPU)
(IPU-S5)
(IPD)
(IPU)
(IPU-S5)
(IPD)
62.5 MHz
42.7 MHz
25.0 MHz
(IPU)
(IPU-S5)
(IPU)
(IPD)
70 mA
(IPD)
(IPU)
(IPU)
(IPU)
1
0
Frequency
24 MHz
14.31818 MHz
0
0
1
1
SPI Frequency Select
1
0
Frequency
BIOS Boot Select
0
LPC_FRAME#
LPC
(IPU)
(IPU)
0
NOTE: MCP89 does not support FWH, only
LPC ROMs. So Apple designs will
HDA_SYNC
I/F
SPI_CLK
BUF_SIO_CLK Frequency
1
SPI
not use LPC for BootROM override.
MCP_SPKR:
(IPD)
(IPU)
(IPU-S5)
(IPD)
For EMI Reduction on HDA interface
1
SPI_DO
31.2 MHz
Connects to SMC for automatic recovery.
HDA Output Caps
NOTE: 42 & 62 MHz use FAST_READ command.
Straps not provided on this page.
1 = SAFE mode (For ROMSIP recovery)
(IPD)
GPIO43 has
70 mA
has the behavior
signal.
NOTE: MCP SLP_S5# pin
of Intel’s SLP_S4#
GPIO Pull-Ups/Downs
7
38 40 68
19 25 68
7
38 40 25 68
1 2
R1961
201
MF
1/20W
5%
10K
21
R1953
201
MF
1/20W
22
5%
7
37 68
21
R1952
201
MF
1/20W
22
5%
21
R1951
MF
1/20W
201
5%
22
21
R1950
201
MF
1/20W
22
5%
7
37 68
7
37 68
7
37 68
2
1
R1900
201
MF
1/20W
1%
49.9
7
37 68
25
25
25
25
38
38
13
25
19 54
19 54
19 54
19 54
44 71
44 71
7
19 38 57
57
7
38 39 57
40 68
19 40 68
40 68
40 68
2
1
R1970
201
MF
1/20W
10K
5%
39
2
1
R1959
10K
5%
1/20W
MF
201
2
1
R1975
1K
1%
1/20W
MF
201
25 68
19 34 57
41 68
41 68
41 68
41 68
2
1
R1930
201
MF
1/20W
5%
10K
2
1
R1931
1/20W
201
MF
5%
100K
13
13
13
13
13
25
38
38
39
2
1
R1920
201
MF
1/20W
49.9K
1%
2
1
R1921
201
MF
1/20W
49.9K
1%
2
1
C1951
201
25V
NPO
10PF
5%
2
1
C1950
201
25V
NPO
5%
10PF
2
1
C1953
201
25V
NPO
5%
10PF
2
1
C1952
201
25V
NPO
5%
10PF
7
38 40
21
21 57
21
R1960
201
MF
1/20W
22
5%
21
R1910
201MF
1/20W
22
5%
21
R1912
201MF
1/20W
5%
22
21
R1911
201MF
1/20W
22
5%
21
R1913
201MF
1/20W
5%
22
7
38 40 68
7
38 40 68
7
38 40 68
7
38 40 68
38
7
37
7
19 40 47
19 22
7
19 37
19 38
19
19
38 39 57
9
19 39
21
R1996
10K
5%
1/20W
MF 201
21
R1980
201MF
1/20W
10K
5%
21
R1987
201MF
1/20W
5%
100K
21
R1990
10K
5%
1/20W
MF 201
21
R1991
201MF
1/20W
10K
5%
21
R1989
201MF
1/20W
5%
10K
21
R1981
201MF
1/20W
10K
5%
21
R1992
201MF
1/20W
100K
5%
21
R1993
201MF
1/20W
5%
100K
21
R1994
201MF
1/20W
5%
100K
21
R1995
201MF
1/20W
100K
5%
21
R1986
201MF
1/20W
100K
5%
7
19 40
7
38 40 19 25 68
21
R1965
201
MF
1/20W
33
5%
2
1
R1966
5%
MF
201
1/20W
10K
NO STUFF
21
R1983
5% 201MF
1/20W
10K
21
R1998
201MF
1/20W
5%
20K
21
R1999
201MF
1/20W
5%
100K
C18
B14
B18
A14
C2
D1
A6
H9
E1
E14
B9
H10
G8
C6
C8
B6
C5
D9
B8
A8
C9
D14
D18
F12
F18
E9
H12
C20
B20
J12
G11
F11
E11
F14
A11
G9
F9
E6
D5
C11
D11
E18
A9
D6
E5
E4
E3
B11
H5
F5
F3
F2
F1 F4
H4
H3
H2
H1
D3
E12
B12
C12
D12
A12
G18
A4
B3
C3
C4A5
B4
G7
E8
F8
D8
J11
F6
U1400
OMIT_TABLE
MCP89U-A01
BGA
2
1
R1956
470
201
MF
1/20W
5%
DRAM_CFG1:L
2
1
R1957
201
MF
1/20W
5%
DRAM_CFG0:H
10K
2
1
R1978
201
MF
1/20W
10K
5%
DRAM_CFG2:H
2
1
R1979
5%
10K
1/20W
MF
201
DRAM_CFG2:L
2
1
R1976
5%
10K
1/20W
MF
201
DRAM_CFG3:H
2
1
R1977
5%
10K
1/20W
MF
201
DRAM_CFG3:L
2
1
R1958
5%
1/20W
MF
201
10K
DRAM_CFG0:L
38
7
19 38 57
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
MCP HDA, LPC & MISC
ENET_LOW_PWR
SDCARD_RESET
MEM_EVENT_L
LPCPLUS_GPIO
MCP_CPU_VTT_EN_L
AUD_IPHS_SWITCH_EN
GFXVCORE_PWR_EN
SMC_IG_THROTTLE_L
=PP3V3_S5_MCP_GPIO
=PP3V3_S0_MCP_GPIO
=PP3V3_S3_MCP_GPIO
SPI_MISO
AP_PWR_EN
MCP_VID<0>
MCP_VID<1>
MCP_CLK25M_XTALOUT
JTAG_MCP_TCK
JTAG_MCP_TDO
SM_INTRUDER_L
MCP_MEM_VDD_EN
HDA_SYNC_R
MLB_RAM_CFG2
MEM_EVENT_L
SDCARD_RESET
ENET_LOW_PWR
SPI_MOSI_R
MCP_THMDIODE_P
AP_PWR_EN
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
LPC_RESET_L
MLB_RAM_CFG3
MLB_RAM_CFG2
MLB_RAM_CFG1
MLB_RAM_CFG0
PM_CLK32K_SUSCLK_R
MLB_RAM_CFG1
MCP_VID<2>
MCP_VID<3>
HDA_SYNC_R
HDA_BIT_CLK_R
HDA_SDOUT_R
LPC_FRAME_L
PP3V3_G3_RTC
=PP3V3R1V5_S0_MCP_HDA
LPC_AD<3>
HDA_RST_R_L
LPC_AD<0>
HDA_SYNC
=PP3V3_S0_MCP_GPIO
HDA_BIT_CLK
HDA_RST_L
HDA_SDOUT
LPC_AD<2>
LPC_AD<1>
LPC_FRAME_R_L
MCP_SPKR
PM_RSMRST_L
LPC_CLK33M_SMC_R
SPI_CS0_R_L
SPI_CLK_R
MCP_WAKE_REQ_L
PM_BATLOW_L
HDA_SDIN0
HDA_SDOUT_R
HDA_BIT_CLK_R
HDA_RST_R_L
MCP_HDA_PULLDN_COMP
LPC_AD_R<0>
LPC_SERIRQ
PM_CLKRUN_L
LPC_AD_R<3>
LPC_AD_R<2>
LPC_AD_R<1>
MCP_CPU_VTT_EN_L
MLB_RAM_CFG0
MCP_VID<2>
MCP_VID<3>
MCP_THMDIODE_N
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
PM_LATRIGGER_L
SMC_WAKE_SCI_L
AUD_I2C_INT_L
SMC_RUNTIME_SCI_L
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
RTC_RST_L
MCP_PS_PWRGD
MCP_MEM_VTT_EN
SMC_IG_THROTTLE_L
GFXVCORE_PWR_EN
AUD_IPHS_SWITCH_EN
SPIROM_USE_MLB
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L
MCP_CLK25M_XTALIN
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
LPCPLUS_GPIO
SMC_ADAPTER_EN
MLB_RAM_CFG3
MCP_MEM_VDD_SEL_1V5
MCP_VID<1>
SPI_MISO
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
MCP_VID<0>
=PP3V3_S3_MCP_GPIO
MCP_TEST_MODE_EN
LPC_RESET_L
LPC_PWRDWN_L
PM_SLP_S5_L
MAKE_BASE=TRUE
PM_SLP_S4_L
SPIROM_USE_MLB
19 OF 110
4.4.0
051-8379
19 OF 73
19
19
19 38
7
19 40
19
7
19 37
19 22
19 39
8
18
8
17 18 19
8
19
19 40 68
19 34 57
19 54
19 54
19 68
19
19
19
19
19
19
19 54
19 54
19 68
19 68
19 68
8
20 23
8
23
19 68
8
17 18 19
19 68
19 68
19 68 68
19
19
19
8
19
7
19 40 47
Page 20
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VDD_MEM
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+3.3V_HVDD
+3.3V
+VTT_CPU2
+3.3V
+3.3V
+VDD_DUAL_AUXC
+VDD_DUAL_AUXC
+3.3V_VBAT
+3.3V_DUAL_USB
+3.3V_DUAL_USB
+3.3V_DUAL
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+3.3V_DUAL_RMGT
+3.3V_DUAL_RMGT
+VDD_DUAL_RMGT
+VDD_DUAL_RMGT
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
SYMBOL 8 OF 11
POWER I
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREB
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREA_SENSE
GND_COREA_SENSE
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_DVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
GND_COREB_SENSE
+VDD_COREB_SENSE
POWER II
SYMBOL 9 OF 11
GND GND
SYMBOL 10 OF 11
GND
GND GND
GND
SYMBOL 11 OF 11
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.
400 MA
PE1[1:0])
2000 mA 4300 mA
200 mA
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
30 mA
250 mA
150 mA
?? uA (G3)
5 mA (S0)
200 mA
40 mA
240 mA
140 mA
300 mA
regulators.
8450 mA (0.85V)
be used for remote sensing unless
15350 mA (0.85V)
(PE0[5:0]
COREA/COREB are powered by separate
(PE0[5:0], PE1[1:0])
1000 MA
100 mA
300 mA
Instead connect regulator sense point
as close to COREB FET as possible.
NOTE: VDD_COREx_SENSE signals should NOT
N30
T30
L31
AA30
E32
K31
N29
W30
W29
Y29
Y30
V29
AA29
U29
V30
R29
P29
U30
L30
T29
L32
P30
R30
L29
M30
M29
A32
D33
C33
AB29
AB30
D32
A33
G32
E33
H32
F32
J33
B32
G33
B33
J32
H33
F33
M31
C32
AC32
AD31
AC31
AB31
AD30
AC30
AD29
AC29
AK13
AJ26
AL30
AK5
AL29
AL27
AL26
AL21
AL20
AL18
AL17
AL15
AL14
AL12
AK15
AL11
AJ14
AJ13
AJ6
AK7
AJ15
AJ16
AJ25
AJ8
AJ7
AJ17
AJ1
AK1
AJ18
AK10
AJ20
AJ3
AJ29
AJ5
AJ11
AK28
AK21
AK9
AJ28
AK25
AK2
AK6
AK11
AJ9
AK24
AK18
AK29
AJ24
AJ4
AK27
AK8
AK22
AK14
AJ21
AJ22
AK3
AJ2
AK23
AJ23
AK17
AJ12
AJ10
AJ27
AK20
AK26
AK4
AK12
AJ19
AK16
AK19
L17
K17
K18
L18
A18
V9
K20
L20
B17
A17
J15
K29
H11
V10
U1400
BGA
MCP89U-A01
OMIT_TABLE
AC6
AD5
AC5
AC4
AC3
AD4
AD3
AD2
AC2
AC1
AD1
AG7
AF9
AG6
AG9
AF8
AF7
AG8
AF6
AD11
AD7
AC10
AC7
AD9
AC9
AC8
AD6
AE12
AD12
AC12
AC11
AD10
AD8
AA11
Y12
Y11
W12
W11
V12
AB10
U12
AB12
AB11
AA12
AA10
J9
M12
M11
AB23
M14
M13
L14
L13
M2
AB20
AB19
AB18
AB17
AB22
Y22
Y21
Y20
Y19
Y18
Y23
Y17
AB21
V22
V21
V20
V18
V19
V17
V23
K4
M7
L6
J5
L1
L2
J6
K11
J3
L3
L4
M5
L7
J7
J1
J2
L5
L11
M4
J4
M3
L9
K5
K2
K8
M1
K7
K10
L12
M6
L10
M10
M8
L8
M9
U9
R3
R5
N4
R8
V11
U11
P9
T12
T11
W24
V24
U24
AD22
AD21
AD20
AD19
AD18
R12
AD17
N12
AA24
Y24
AD23
R11
P7
P12
P11
AC24
N11
AB24
R6
P6
R7
AD24
P5
R10
N8
R4
P2
N2
R1
P10
N10
N5
R9
P1
R2
P8
P4
P3
N7
J8
U8
U1400
BGA
MCP89U-A01
OMIT_TABLE
AP36
AL22
K34
AC18
E22
B34
B19
B22
G10
AW19
AB4
AU34
AE31
AN16
AA22
AC21
AN25
AH31
AT31
U31
AL31
AB2
H31
D10
AU10
W4
AY38
AU25
AM32
B10
E10
G13
T37
H13
AW7
E7
T33
AW13
AU22
AP25
AU19
D4
AN28
T36
AT7
AU7
AW5
AU37
V31
AH37
T4
B39
T2
N33
AL25
AY3
AE33
Y31
AA31
AA23
AU13
K13
AB36
W33
AP10
K37
AN19
AV1
AE37
B13
AH7
AW2
Y10
W19
L15
B7
AE4
G31
K39
D16
G37
B2
D7
AW16
W20
AT2
N34
AT10
AB5
AT16
W18
AE5
AC20
AW34
AE36
G36
H28
D28
AV40
B28
AH34
E28
AA20
AE8
AL2
AL19
AU31
AP31
AN13
AP22
AC23
W37
W39
W36
G4
D22
U23
AW31
AT25
AA18
AE39
AT34
A38
AP19
AH2
B5
AT13
AT19
W8
AA19
AU4
B31
H25
U21
P31
G34
C40
AL34
U1400
BGA
MCP89U-A01
OMIT_TABLE
AM5
V8
V7
H7
H6
AK35
AK34
W2
U17
AP7
AL13
E13
K33
T10
AA17
N31
T31
AL39
W31
T7
U18
AP34
AL10
AP2
W7
W5
AE7
M21
M20
M19
M18
M17
M15
M16
T8
AE30
D31
AN22
T34
AW22
K22
L16
E19
AU28
AW28
AE29
N37
N36
N39
AB8
AN10
AW39
AL5
AH39
AB39
G39
W17
AW10
AL33
AH5
AC17
AH36
AB7
AH4
T39
D13
AL7
AE2
AB37
B36
D37
E39
C1
AL4
AW36
G22
U20
AB34
AU16
AL37
AN31
AC19
T5
E2
G2
K19
H8
H22
AC22
W23
Y1
D19
K36
E25
D34
W21
AP5
AT39
AE34
AL28
E34
K12
U19
W34
U10
B25
AB33
AP39
AW25
R31
G28
AH8
A3
H19
W22
AP37
AA1
AL8
AT22
AH33
H16
AT28
AP28
U22
AP13
G16
E31
K25
G25
AP4
AL16
D25
K28
K16
AA21
G19
AL36
AP16
E16
B16
U1400
MCP89U-A01
BGA
OMIT_TABLE
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
MCP Power & Ground
=PP0V9_ENET_MCP_RMGT
=PPVCORE_SW_MCP_GFX
=PP1V05_S0_MCP_PE_DVDD
PP1V05_S0_MCP_PE_AVDD
PP1V05_S0_MCP_SATA_AVDD
=PP1V05_S0_MCP_SATA_DVDD
TP_MCP_VDDCOREB_SENSEN
TP_MCP_VDDCOREB_SENSEP
=PP1V05_S0_MCP_FSB
=PP3V3_S0_MCP_HVDD
=PP3V3_S0_MCP
=PP0V9_S5_MCP_VDD_AUXC
PP3V3_G3_RTC
=PP3V3_S5_MCP
=PP3V3_ENET_MCP_RMGT
TP_MCP_VDDCOREA_SENSEN
TP_MCP_VDDCOREA_SENSEP
=PPVCORE_S0_MCP
=PP1V5R1V35_SW_MCP_MEM
=PP1V05_SW_MCP_FSB
20 OF 110
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051-8379
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8
23
22 24
8
23
23 23
8
23
8
14 23
8
23
8
23
8
23
8
19 23
8
23
8
18 23
8
23
15 21 23
8
23
Page 21
NC
NC
OUT
OUT
IN
BI
BI
BI
BI
D
G S
IN
VCC
D
DONE
G
GND
THRM
S
EN
CNFG
PAD
D
G
G
D
S
S
D
G
G
D
S
S
NC
K1
G
S
SENSE
D
KELVIN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NO STUBS on CKE signals!
DIMM CKE Clamps
Q2355/Q2356 chosen for low output capacitance.
CKE must be held low to keep memory in self-refresh.
Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.
Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.
Clamps enable before MCP89 MEMVDD rail switched off.
<R1>
Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)
Gated Rail Savings: 120mW
NV Requirements:
NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.
- Min Ramp-Up Time: 20 uS (10% to 90%)
- FET Ron <= 3.8 mOhms
4250 mA
(OR 1.35V)
Q2300
Type
Part
N-Channel
STMFS4854N
- Max Ramp-Up Time: 65 uS (ENABLE to 90%)
Loading
(G driven to VCC)
C2300 helps reduce input rail
droop during Q2300 turn-on.
Rds(on)
10 mOhm @3.2V
4.3 A (EDP)
43
43
2
1
R2305
MF
560K
1%
1/20W
201
19 57
2
1
C2305
0.1UF
402
CERM
10V
20%
2
1
C2300
CRITICAL
PLACE_NEAR=Q2300.9:2 mm
1206-1
CERM-X5R
6.3V
20%
100UF
15 28 29 32 66
15 28 29 32 66
15 26 27 32 66
15 26 27 32 66
2
1
3
Q2350
SOD-VESM-HF
SSM3K15FV
19
2
1
R2350
5%
10K
MF
1/20W
201
1
9
6
4
7
2
8
5
3
U2305
CRITICAL
TDFN
SLG5AP031
1
4
2
5
6
3
Q2355
SOT-963
CRITICAL
NTUD3170NZXXG
1
4
2
5
6
3
Q2356
SOT-963
CRITICAL
NTUD3170NZXXG
7 321
6
5
4
9
Q2300
DFN
CRITICAL
STMFS4855NS
MCP89 Memory Rail Gating
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
PP1V5R1V35_SW_MCP
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm
MCPMEM_GATE
MCPDDRFET_KELVIN
MCPDDRFET_SENSE
=PP1V5R1V35_S0_MCPDDRFET
MCP_MEM_VDD_EN
=PP1V5R1V35_SW_MCP_MEM
MCPMEM_CNFG
TP_MCPMEM_DONE
=PP5V_S3_MCPDDRFET
MCP_MEM_VTT_EN
=PP5V_S3_MCPDDRFET
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEMVTT_EN_L
23 OF 110
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051-8379
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8
15 20 23
8
21
8
21
Page 22
OUT
OUT
S
D
G
IN
CNFG
EN
S
THRM
GND
G
DONE
D
VCC
PAD
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
<C1>
Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)
(G driven to VCC)
- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)
Q2400
15.35 A (EDP)
NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.
droop during Q2400 turn-on.
C2400 helps reduce input rail
N-Channel
Si4838BDY
3.2 mOhm @2.5V
- Min Ramp-Up Time: 100 uS (10% to 90%)
- FET Ron <= 2.5 mOhms
Gated Rail Savings: 860mW
NV Requirements:
Type
Part
Loading
Rds(on)
21
XW2401
PLACE_NEAR=C2400.2:1 mm
SM
21
XW2400
SM
PLACE_NEAR=C2400.1:1 mm
54 71
54 71
321
4
8765
Q2400
SO-8
SI4838BDY
CRITICAL
19
2
1
C2405
20%
10V
CERM
402
0.1UF
2
1
C2400
100UF
PLACE_NEAR=Q2400.5:2 mm
CRITICAL
1206-1
CERM-X5R
6.3V
20%
2
1
C2406
10%
CERM
820PF
402
50V
1
9
6
4
7
2
8
5
3
U2405
SLG5AP033
TDFN
CRITICAL
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
MCP89 GFX Core Rail Gating
=PPVCORE_SW_MCP_GFX
MCPCORES0_VSEN_N
MCPCORES0_VSEN_P
MCPGFX_GATE
MCPGFX_CNFG
GFXVCORE_PWR_EN
TP_MCPGFX_DONE
=PP5V_S0_MCPFSBFET
=PPVCORE_S0_MCPGFXFET
MIN_NECK_WIDTH=0.12 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE
PPVCORE_SW_MCP_GFX
24 OF 110
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051-8379
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20 24
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Page 23
NC
VOUT
EN
VIN
GND
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MCP 3.3V DP & USB PLL Power
<Ra>
<Rb>
210 mA
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
260 mA
MCP CPU FSB (VTT) Power
MCP 3.3V PLL Power
50 mA
140 mA
800 mA
300 mA
555 mA
160 mA
325 mA
70 mA
240 mA
300 mA
5 mA (S0)
70 mA
30 mA
550 mA
100 mA200 mA
150 mA
200 mA
2000 mA
4300 mA (1.5V)
MCP 1.05V CPU/FSB/MEM PLL Power
MCP 1.05V PCIe/SATA PLL Power
MCP Memory Power
MCP 1.05V PCIE Digital Power
MCP 3.3V AUX/USB Power
MCP 3.3V I/O Power
MCP 3.3V MAC/SMU Power
MCP 0.9V AUX Core Power
250 mA
? uA (G3)
MCP 1.05V Memory DLL Power
MCP 1.05V Core/Misc PLL Power
MCP 0.9V MAC/SMU Power
MCP 1.05V SATA Digital Power
MCP S0 FSB (VTT) Power
MCP 3.3V/1.5V HDA Power
MCP 2.0V-3.3V RTC Power
MCP 1.05V PCIe Analog Power
500 mA
MCP 1.05V SATA Analog Power
8450 mA (0.85V)
MCP 3.3V MAC PLL POWER
20 mA 20 mA
MCP 3.3V PCIe/SATA I/O PLL Power
MCP Non-GFX Core Power
Vout = 0.8V * (Ra + Rb) / Rb, Rb ~ 320kOhms
2
1
C2590
20%
4.7UF
603
6.3V
CERM
2
1
C2503
20%
X5R
0.22UF
6.3V
201
2
1
C2502
20%
X5R
0201
6.3V
1.0UF
2
1
C2507
X5R
6.3V
201
10%
0.1UF
2
1
C2506
X5R
0.1UF
6.3V
201
10%
2
1
C2505
X5R
0.1UF
6.3V
201
10%
2
1
C2504
X5R
0.1UF
6.3V
201
10%
2
1
C2508
X5R
0.1UF
6.3V
201
10%
2
1
C2532
20%
X5R
6.3V
1.0UF
0201
2
1
C2531
20%
X5R
0201
1.0UF
6.3V
2
1
C2530
20%
4.7UF
402
X5R-1
4V
2
1
C2536
20%
4.7UF
402
X5R-1
4V
2
1
C2519
X5R
6.3V
201
0.1UF
10%
2
1
C2518
X5R
201
6.3V
10%
0.1UF
2
1
C2517
X5R
6.3V
201
10%
0.1UF
2
1
C2516
X5R
10%
6.3V
201
0.1UF
2
1
C2515
X5R
0.1UF
6.3V
201
10%
2
1
C2514
X5R
6.3V
201
10%
0.1UF
2
1
C2513
X5R
0.1UF
6.3V
201
10%
2
1
C2512
X5R
0.1UF
6.3V
201
10%
2
1
C2511
X5R
0.1UF
6.3V
201
10%
2
1
C2510
20%
4.7UF
402
X5R-1
4V
21
L2560
0603
30-OHM-5A
21
L2567
30-OHM-5A
0603
2
1
C2500
20%
X5R
OMIT_TABLE
10UF
603-1
6.3V
2
1
C2501
20%
4.7UF
402
X5R-1
4V
2
1
C2527
X5R
6.3V
201
0.1UF
10%
2
1
C2526
X5R
6.3V
201
0.1UF
10%
2
1
C2591
20%
402
10V
CERM
0.1UF
2
1
C2537
X5R
6.3V
201
0.1UF
10%
2
1
C2533
X5R
0.1UF
10%
201
6.3V
2
1
C2534
X5R
10%
0.1UF
201
6.3V
2
1
C2529
X5R
0.1UF
10%
6.3V
201
2
1
C2528
20%
4.7UF
402
X5R-1
4V
2
1
C2549
X5R
0.1UF
10%
6.3V
201
2
1
C2548
20%
4.7UF
603
6.3V
CERM
2
1
C2535
X5R
6.3V
201
0.1UF
10%
2
1
C2554
20%
402
10V
CERM
0.1uF
2
1
C2553
20%
4.7uF
603
6.3V
CERM
2
1
C2551
20%
402
0.1uF
CERM
10V
2
1
C2550
20%
4.7uF
603
6.3V
CERM
2
1
C2543
20%
4.7uF
603
6.3V
CERM
2
1
C2544
20%
402
0.1uF
CERM
10V
2
1
C2545
20%
402
0.1uF
CERM
10V
2
1
C2546
20%
402
CERM
10V
0.1uF
2
1
C2547
20%
402
10V
0.1uF
CERM
2
1
C2520
20%
X5R
603-1
OMIT_TABLE
10UF
6.3V
2
1
C2521
20%
4.7UF
402
X5R-1
4V
2
1
C2522
20%
X5R
6.3V
0201
1.0UF
2
1
C2523
20%
X5R
6.3V
0201
1.0UF
2
1
C2525
20%
X5R
6.3V
0201
1.0UF
2
1
C2524
20%
4.7UF
402
X5R-1
4V
2
1
C2560
20%
X5R
OMIT_TABLE
10UF
6.3V
603-1
2
1
C2561
20%
4.7UF
402
X5R-1
4V
2
1
C2562
20%
X5R
1.0UF
0201
6.3V
2
1
C2563
20%
X5R
6.3V
0201
1.0UF
2
1
C2564
X5R
0.1UF
10%
201
6.3V
2
1
C2567
20%
X5R
OMIT_TABLE
10UF
603-1
6.3V
2
1
C2568
20%
4.7UF
402
X5R-1
4V
2
1
C2569
X5R
10%
201
6.3V
0.1UF
2
1
C2565
X5R
0.1UF
10%
201
6.3V
2
1
C2566
X5R
0.1UF
6.3V
201
10%
2
1
C2540
20%
4.7UF
402
X5R-1
4V
2
1
C2595
20%
4.7UF
PLACE_NEAR=R2595.1:50 mil
CERM
6.3V
603
2
1
C2596
20%
402
0.1UF
CERM
10V
2
1
C2597
20%
402
10V
CERM
0.1uF
21
R2595
MF
0.33
5%
1/16W
0402
2
1
C2542
20%
402
CERM
0.1uF
10V
2
1
C2541
20%
4.7UF
CERM
603
6.3V
2
1
C2572
X5R
6.3V
201
0.1UF
10%
2
1
C2571
X5R
0.1UF
6.3V
201
10%
2
1
C2570
20%
4.7UF
402
X5R-1
4V
PLACE_NEAR=R2570.1:50 mil
21
R2570
MF
1/16W
0402
0.33
5%
2
1
C2573
X5R
0.1UF
6.3V
201
10%
2
1
C2578
X5R
0.1UF
6.3V
201
10%
2
1
C2577
X5R
6.3V
201
0.1UF
10%
2
1
C2576
X5R
201
0.1UF
6.3V
10%
2
1
C2575
20%
4.7UF
402
X5R-1
4V
2
1
C2583
X5R
0.1UF
6.3V
201
10%
2
1
C2582
X5R
6.3V
201
0.1UF
10%
2
1
C2581
X5R
6.3V
201
10%
0.1UF
2
1
C2580
20%
4.7UF
402
X5R-1
4V
2
1
C2579
X5R
0.1UF
6.3V
201
10%
2
1
C2584
X5R
0.1UF
6.3V
201
10%
2
1
C2552
20%
4.7UF
603
6.3V
CERM
21
L2570
CRITICAL
0603
220-OHM-2.2A
21
L2580
220-OHM-2.2A
0603
CRITICAL
21
L2575
220-OHM-2.2A
0603
CRITICAL
21
L2595
220-OHM-2.2A
CRITICAL
0603
21
L2590
CRITICAL
FERR-240-OHM-200MA
0402
MCPHVDD:P3V3
2
1
C2556
20%
402
0.1UF
CERM
10V
2
1
C2555
20%
4.7UF
603
CERM
6.3V
21
L2555
0402
FERR-240-OHM-200MA
CRITICAL
2
1
C2559
20%
4.7UF
402
X5R-1
4V
2
1
C2538
20%
4.7UF
402
X5R-1
4V
51
2
3
U2590
SC70
CRITICAL
OMIT_TABLE
MIC5365-2.5V
2
1
R2590
10K
201
5%
1/20W
MF
MCPHVDD:P2V5
2
1
C2592
20%
X5R
MCPHVDD:P2V5
1.0UF
0201
6.3V
2
1
R2591
201
1%
665K
1/20W
MF
HVDDLDO:ADJ
2
1
R2592
HVDDLDO:ADJ
201
1%
316K
1/20W
MF
SYNC_DATE=07/07/2010
MCP Standard Decoupling
SYNC_MASTER=K16_MLB
353S2979
IC,LDO,TPS717,ADJ,150MA,3%,SC70,HF
1 CRITICAL
HVDDLDO:ADJ
U2590
353S2988
IC,MIC5366,LDO REG,2.5V,150MA,SC70
1 CRITICALU2590
HVDDLDO:FIXED
=PPVCORE_S0_MCP
=PP1V5R1V35_SW_MCP_MEM
=PP0V9_S5_MCP_VDD_AUXC
=PP1V05_S0_MCP_PE_DVDD
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_CORE
=PP3V3_S0_MCP_HVDD
=PP1V05_S0_MCP_PLL_UF
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
PP3V3_ENET_MCP_PLL_MAC
=PP3V3_ENET_MCP_PLL_MAC
=PP1V05_S0_MCP_AVDD_UF
PP3V3_G3_RTC
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S5_MCP
=PP1V05_S0_MCP_FSB
=PP1V05_S0_MCP_SATA_DVDD
=PP3V3_ENET_MCP_RMGT
=PP1V05_S0_MCP_M2CLK_DLL
PP1V05_S0_MCP_PLL_FSBMEM
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V05_S0_MCP_PLL_PEXSATA
=PP3V3_S0_MCP
=PP0V9_ENET_MCP_RMGT
GND_MCP_PLL_FSB
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V
MIN_LINE_WIDTH=0.25 MM
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 MM
GND_MCP_PLL_DP_USB
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V05_S0_MCP_SATA_AVDD
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
PP1V05_S0_MCP_PE_AVDD
=PP1V05_SW_MCP_FSB
=PP3V3_S0_MCP_PLL_UF
P2V8HVDD_EN
PP3V3_S0_MCP_PLL_HVDD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
P2V8HVDD_FB
PP3V3_S0_MCP_PLL_DP_USB
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
25 OF 110
4.4.0
051-8379
23 OF 73
4
8
20
15 20 21
8
20
8
20 17
8
20
8
18
8
8
8
19 20
8
19
8
20
8
14 20
8
20
8
18 20
8
15
15
16
8
20
8
20
20
20
8
20
8
16
17
Page 24
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
15350 mA (0.85V)
MCP GFX Core Power
140 mA
MCP 3.3V RGBDAC Power
If RGBDAC is used, requires ferrite (155S0382)
If RGBDAC is not used, tie to GND.
plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.
160 mA
MCP 1.05V DisplayPort Power
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
2
1
C2650
X5R
6.3V
201
10%
0.1UF
NO STUFF
2
1
R2655
MF
1/20W
201
1K
1%
NO STUFF
2
1
C2655
X5R
6.3V
201
10%
0.1UF
NO STUFF
2
1
C2640
20%
4.7UF
402
X5R-1
4V
2
1
R2670
1/20W
0
5%
201
MF
2
1
C2600
20%
X5R
OMIT_TABLE
6.3V
10UF
603-1
2
1
C2601
20%
4.7UF
402
X5R-1
4V
2
1
C2602
20%
X5R
6.3V
0201
1.0UF
2
1
C2603
20%
X5R
1.0UF
6.3V
0201
2
1
C2604
20%
X5R
201
6.3V
0.22UF
2
1
C2605
20%
X5R
201
0.22UF
6.3V
2
1
C2606
X5R
6.3V
201
10%
0.1UF
2
1
C2607
X5R
0.1UF
6.3V
201
10%
2
1
C2608
X5R
6.3V
201
10%
0.1UF
2
1
C2609
X5R
6.3V
201
10%
0.1UF
2
1
C2610
X5R
6.3V
201
10%
0.1UF
2
1
C2611
X5R
6.3V
201
10%
0.1UF
2
1
C2612
X5R
6.3V
201
10%
0.1UF
2
1
C2641
X5R
6.3V
201
0.1UF
10%
2
1
R2650
MF
201
1%
1K
1/20W
SYNC_DATE=07/07/2010
MCP Graphics Support
SYNC_MASTER=K16_MLB
=PP1V05_S0_MCP_PLL_IFP
=PP3V3R1V8_S0_MCP_IFP_VDD
=PP1V05_S0_MCP_DP0_VDD
MCP_IFPAB_RSET
MCP_TMDS0_VPROBE
MCP_TMDS0_RSET
MCP_IFPAB_VPROBE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
GND_MCP_DAC_P3V3
MAKE_BASE=TRUE
PP3V3_S0_MCP_DAC
=PPVCORE_SW_MCP_GFX
26 OF 110
4.4.0
051-8379
24 OF 73
17
17
8
17
17 67
17 67
17 67
17 67
17
20 22
Page 25
IN
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
IN
NC
NC
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
B
Y
A
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
System Reset Circuit
PCIE Reset (Unbuffered)
LPC Reset (Unbuffered)
Platform Reset Connections
10K pull-up to 3.3V S0 inside MCP
MCP 25MHz Crystal
RTC Crystal
MCP S0 PWRGD & CPU_VLD
10 13 19
21
C2810
25V
NP0-C0G
201
12PF
5%
21
C2811
25V
NP0-C0G
201
12PF
5%
21
R2810
MF
1/20W
201
0
5%
2
1
R2811
10.0M
0201
1/20W
MF
5%
NO STUFF
19 68
21
R2896
MF
1/20W
201
0
5%
XDP
21
R2883
MF
1/20W
201
PLACEMENT_NOTE=Place close to U1400
5%
33
21
R2881
MF
1/20W
201
PLACEMENT_NOTE=Place close to U1400
33
5%
2
1
R2897
OMIT
SILK_PART=SYS RST
5%
0
PLACEMENT_NOTE=Place R2897 on BOTTOM
MF-LF
1/16W
402
7
40
38
19
19
16
21
R2826
MF
1/20W
201
5%
33
PLACEMENT_NOTE=Place close to U1400
21
R2825
MF
1/20W
201
PLACEMENT_NOTE=Place close to U1400
5%
33
19 68
21
C2815
25V
NP0-C0G
201
12PF
5%
21
C2816
25V
NP0-C0G
201
12PF
5%
31
42
Y2815
25.0000M
CRITICAL
SM-3.2X2.5MM
21
R2815
MF
1/20W
201
0
5%
2
1
R2816
MF
1/20W
201
1M
5%
NO STUFF
19
19
38 68
21
R2829
MF
1/20W
201
22
5%
PLACEMENT_NOTE=Place close to U1400
19 68
21
R2899
MF
1/20W
201
33
5%
2
1
C2899
6.3V
0201
1.0UF
20%
X5R
NO STUFF
38
7
40 68
38 68
41
Y2810
CRITICAL
7X1.5X1.4-SM
32.768K
21
R2891
MF
1/20W
201
0
5%
33
21
R2893
MF
1/20W
201
0
5%
63
34
21
R2894
MF
1/20W
201
0
5%
53
38 49 57
2
1
C2850
10%
201
X5R
6.3V
0.1UF
19
5
4
1
2
3
U2850
74LVC1G08GW
SOT353
SYNC_MASTER=K6_MLB
SYNC_DATE=12/11/2009
SB Misc
=PP3V3_S5_MCPPWRGD
MCP_PS_PWRGD
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT_R
RTC_CLK32K_XTALOUT
MCP_CLK25M_XTALOUT
MCP_CLK25M_XTALOUT_R
PM_SYSRST_DEBOUNCE_L
LPCPLUS_RESET_L
LPC_RESET_L
PM_CLK32K_SUSCLK
PM_CLK32K_SUSCLK_R
XDP_DBRESET_L
SMC_LRESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
VR_PWRGOOD_DELAY
ALL_SYS_PWRGD
MCP_CLK25M_XTALIN
PCA9557D_RESET_L
BKLT_PLT_RST_L
PCIE_RESET_L
MAKE_BASE=TRUE
AP_RESET_L
PM_SYSRST_L
28 OF 110
4.4.0
051-8379
25 OF 73
8
Page 26
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NC
NC
NC
NC NC
NC
NC
NC
NC
NCNC
NC
A14/A15 FOR 2G/4G MONO ONLY
CS1 IS FOR 2G DDP RANK CONTROL
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3100
OMIT_TABLE
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
MEM_A_ZQ0
FBGA
2
1
C3102
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3101
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3100
20%
0.47UF
201
CERM-X5R-1
4V
21
R3100
201
240
1%MF1/20W
2
1
C3112
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3111
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3110
20%
0.47UF
201
CERM-X5R-1
4V
21
R3110
201
1/20W
240
MF
1%
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3110
FBGA
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
OMIT_TABLE
2
1
C3122
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3121
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3120
20%
0.47UF
201
CERM-X5R-1
4V
21
R3120
201
1/20W
240
MF
1%
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3120
FBGA
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
OMIT_TABLE
2
1
C3132
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3131
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3130
20%
0.47UF
201
CERM-X5R-1
4V
21
R3130
201
240
1/20WMF1%
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3130
FBGA
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
OMIT_TABLE
DDR3 DRAM Channel A (0-31)
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
MEM_A_CKE<1>
MEM_A_A<14>
MEM_A_ZQ0
MEM_A_ODT<1>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_BA<0>
MEM_A_CKE<0>
MEM_A_BA<2>
MEM_RESET_L
MEM_A_A<8>
MEM_A_A<4>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<0>
PPVREF_S3_MEM_VREFDQ
PPVREF_S3_MEM_VREFCA
MEM_A_DM<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<2>
MEM_A_DQ<4>
MEM_A_DQ<0>
MEM_A_DQ<3>
MEM_A_DQ<7>
MEM_A_DQ<1>
MEM_A_A<3>
MEM_A_A<5>
MEM_A_CLK_P<0>
MEM_A_BA<1>
=PPLVDDR_S3_MEM_A
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MEM_A_ODT<0>
MEM_A_CLK_N<0>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<11>
MEM_A_WE_L
PPVREF_S3_MEM_VREFDQ
MEM_A_ODT<0>
MEM_RESET_L
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ
MEM_A_DQ<8>
MEM_A_A<4>
MEM_A_ODT<1>
MEM_A_CAS_L
MEM_A_A<11>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_WE_L
MEM_A_RAS_L
=PPLVDDR_S3_MEM_A
MEM_A_BA<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_ZQ3
MEM_A_DQ<25>
MEM_A_DQ<28>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<29>
MEM_A_DQS_N<3>
MEM_A_DM<3>
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<7>
MEM_A_A<4>
MEM_A_A<8>
MEM_RESET_L
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_BA<0>
MEM_A_A<9>
MEM_A_ODT<1>
MEM_A_ZQ3
MEM_A_A<11>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_CLK_N<0>
MEM_A_ODT<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_RAS_L
=PPLVDDR_S3_MEM_A
MEM_A_BA<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_ZQ2
MEM_A_DQ<17>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<16>
MEM_A_DQ<18>
MEM_A_DQ<21>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
PPVREF_S3_MEM_VREFCA
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<7>
MEM_A_A<6>
MEM_RESET_L
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_BA<0>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_ZQ2
MEM_A_A<14>
MEM_A_CKE<1>
MEM_A_A<11>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_CLK_N<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CAS_L
=PPLVDDR_S3_MEM_A
MEM_A_BA<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_ZQ1
MEM_A_DQ<12>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<13>
MEM_A_DQ<15>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DM<1>
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<8>
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_BA<0>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_CKE<1>
MEM_A_ZQ1
MEM_A_RAS_L
MEM_A_ODT<1>
MEM_A_CLK_N<0>
MEM_A_A<14>
MEM_A_A<8>
MEM_A_A<10>
MEM_A_DQ<14>
MEM_A_DQ<9>
MEM_A_DM<2>
MEM_A_A<6>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_A<14>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_CKE<1>
MEM_A_DQS_P<3>
MEM_A_DQ<24>
31 OF 110
4.4.0
051-8379
26 OF 73
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66
15 26 27 32 66
15 26 27 28 29
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
26 27 28 29 33
26 27 28 29 33
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 26 27 32 66
15 26 27 32 66
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15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
26 27 28 29 33
15 26 27 32 66
15 26 27 28 29
26 27 28 29 33
26 27 28 29 33
15 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29 33
26 27 28 29 33
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 28 29
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27
32 66
26
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29 33
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 28 29
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
26
15 26
27 32 66
15 21 26
27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27
32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66 15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 21 26 27 32 66
26
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 66
15 66
15 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26
27 32
66
15 66
15 66
15 21 26
27 32 66
15 66
15 66
Page 27
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NC
NC
NC
CS1 IS FOR 2G DDP RANK CONTROL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A14/A15 FOR 2G/4G MONO ONLY
NC
NC
NC
NC NC
NC
NC
2
1
C3232
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3220
4V
CERM-X5R-1
201
0.47UF
20%
21
R3230
1%MF1/20W
240
201
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3230
OMIT_TABLE
MT41J128M8HX-187E
128MX8-SDRAM-1066MHZ
FBGA
21
R3220
1%MF1/20W
240
201
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3220
OMIT_TABLE
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
FBGA
2
1
C3212
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3211
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3210
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3202
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3201
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3200
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3231
4V
CERM-X5R-1
201
0.47UF
20%
21
R3210
1%MF1/20W
240
201
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3210
OMIT_TABLE
128MX8-SDRAM-1066MHZ
FBGA
MT41J128M8HX-187E
21
R3200
1%MF1/20W
240
201
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3200
OMIT_TABLE
MT41J128M8HX-187E
128MX8-SDRAM-1066MHZ
FBGA
2
1
C3230
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3222
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3221
4V
CERM-X5R-1
201
0.47UF
20%
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
DDR3 DRAM Channel A (32-63)
MEM_A_A<11>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_CLK_N<0>
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_BA<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_ZQ9
MEM_A_DQ<46>
MEM_A_DQ<41>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<40>
MEM_A_DQ<47>
MEM_A_DQ<42>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DM<5>
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<8>
MEM_RESET_L
MEM_A_CKE<0>
MEM_A_BA<0>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_ODT<1>
MEM_A_ZQ9
MEM_A_A<14>
MEM_A_CKE<1>
MEM_A_BA<2>
MEM_A_A<11>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_CLK_N<0>
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_RAS_L
=PPLVDDR_S3_MEM_A
MEM_A_BA<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_ZQ8
MEM_A_DQ<33>
MEM_A_DQ<39>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<32>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DM<4>
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<8>
MEM_RESET_L
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_BA<0>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_ODT<1>
MEM_A_ZQ8
MEM_A_A<14>
MEM_A_CKE<1>
MEM_A_A<11>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_CLK_N<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_BA<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_ZQ10
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<55>
MEM_A_DQ<48>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<52>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DM<6>
PPVREF_S3_MEM_VREFDQ
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<8>
MEM_RESET_L
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_BA<0>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_ODT<1>
MEM_A_ZQ10
MEM_A_A<14>
MEM_A_CKE<1>
MEM_A_A<11>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_CLK_N<0>
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_RAS_L
=PPLVDDR_S3_MEM_A
MEM_A_BA<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_ZQ11
MEM_A_DQ<57>
MEM_A_DQ<59>
MEM_A_DQ<56>
MEM_A_DQ<63>
MEM_A_DQ<58>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<60>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DM<7>
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<8>
MEM_RESET_L
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_BA<0>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_ODT<1>
MEM_A_ZQ11
MEM_A_A<14>
MEM_A_CKE<1>
PPVREF_S3_MEM_VREFDQ
MEM_A_ODT<0>
PPVREF_S3_MEM_VREFCA
=PPLVDDR_S3_MEM_A
=PPLVDDR_S3_MEM_A
PPVREF_S3_MEM_VREFDQ
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFCA
32 OF 110
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051-8379
27 OF 73
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15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 28 29
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
27
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
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15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29
33
26 27 28 29
33
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 28 29
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27
32 66
27
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29 33
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 28 29
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
27
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26
27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 28 29
15 26 27 32 66
15 21 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32 66
15 26 27 32
66
27
15 26 27
32 66
15 21 26 27
32 66
26 27 28 29 33
15 26 27 32 66
26 27 28 29 33
8
26 27 30
26 27 28 29 33
26 27 28 29 33
26 27 28 29 33
Page 28
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NC
NC
NC NC
NC
NC
CS1 IS FOR 2G DDP RANK CONTROL
A14/A15 FOR 2G/4G MONO ONLY
NC
NC
NC NC
NCNC
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3300
MT41J128M8HX-187E
128MX8-SDRAM-1066MHZ
MEM_B_ZQ0
FBGA
OMIT_TABLE
2
1
C3302
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3301
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3300
4V
CERM-X5R-1
201
0.47UF
20%
21
R3300
1/20WMF1%
240
201
2
1
C3312
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3311
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3310
4V
CERM-X5R-1
201
0.47UF
20%
21
R3310
1%MF1/20W
240
201
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3310
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
FBGA
OMIT_TABLE
2
1
C3322
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3321
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3320
4V
CERM-X5R-1
201
0.47UF
20%
21
R3320
1%MF1/20W
240
201
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3320
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
FBGA
OMIT_TABLE
2
1
C3332
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3331
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3330
4V
CERM-X5R-1
201
0.47UF
20%
21
R3330
1%MF1/20W
240
201
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3330
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
FBGA
OMIT_TABLE
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
DDR3 DRAM Channel B (0-31)
PPVREF_S3_MEM_VREFDQ
PPVREF_S3_MEM_VREFCA
MEM_B_A<14>
MEM_B_ZQ0
MEM_B_ODT<1>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_BA<0>
MEM_B_CKE<0>
MEM_B_BA<2>
MEM_RESET_L
MEM_B_A<8>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<0>
MEM_B_DM<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<4>
MEM_B_A<5>
MEM_B_CLK_P<0>
MEM_B_BA<1>
=PPLVDDR_S3_MEM_B
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CLK_N<0>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_CKE<1>
MEM_B_A<14>
MEM_B_ZQ1
MEM_B_ODT<1>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_BA<0>
MEM_B_CKE<0>
MEM_B_BA<2>
MEM_RESET_L
MEM_B_A<8>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<2>
MEM_B_A<0>
PPVREF_S3_MEM_VREFCA
MEM_B_DM<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQ<15>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<8>
MEM_B_DQ<14>
MEM_B_DQ<9>
MEM_B_ZQ1
MEM_B_A<5>
MEM_B_CLK_P<0>
MEM_B_BA<1>
=PPLVDDR_S3_MEM_B
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_CLK_N<0>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_CKE<1>
MEM_B_A<14>
MEM_B_ZQ2
MEM_B_ODT<1>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_BA<0>
MEM_B_CKE<0>
MEM_RESET_L
MEM_B_A<8>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<0>
PPVREF_S3_MEM_VREFDQ
PPVREF_S3_MEM_VREFCA
MEM_B_DM<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DQ<23>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<16>
MEM_B_DQ<22>
MEM_B_ZQ2
MEM_B_A<3>
MEM_B_A<5>
MEM_B_CLK_P<0>
MEM_B_BA<1>
=PPLVDDR_S3_MEM_B
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_CLK_N<0>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_CKE<1>
MEM_B_A<14>
MEM_B_ZQ3
MEM_B_ODT<1>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_BA<0>
MEM_B_CKE<0>
MEM_B_BA<2>
MEM_RESET_L
MEM_B_A<8>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<1>
MEM_B_A<2>
PPVREF_S3_MEM_VREFDQ
PPVREF_S3_MEM_VREFCA
MEM_B_DM<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DQ<26>
MEM_B_DQ<31>
MEM_B_DQ<25>
MEM_B_DQ<27>
MEM_B_DQ<24>
MEM_B_DQ<28>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_ZQ3
MEM_B_A<3>
MEM_B_A<5>
MEM_B_CLK_P<0>
MEM_B_BA<1>
=PPLVDDR_S3_MEM_B
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_CLK_N<0>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_A<0>
MEM_B_CKE<1>
MEM_B_ODT<0>
MEM_B_A<3>
MEM_B_DQ<3>
MEM_B_A<1>
MEM_B_DQ<7>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_A<3>
MEM_B_DQ<12>
MEM_B_BA<2>
PPVREF_S3_MEM_VREFDQ
MEM_B_DQ<11>
33 OF 110
4.4.0
051-8379
28 OF 73
26 27 28 29 33
26 27 28 29 33
15 28 29 32 66
28
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28 29 32
66
15 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
28
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
26 27 28 29 33
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
8
28 29 31
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29
32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
28
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
26 27 28 29 33
26 27 28 29 33
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
8
28 29 31
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28
29 32 66
15 28
29 32
66
28
15 28 29
32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
26 27 28 29 33
26 27 28 29 33
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
8
28 29 31
15 28
29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28
29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 28 29 32 66 15 66
15 28 29 32 66
15 66
15 66
15 66
15 28 29 32 66 15 66
15 28 29 32 66
26 27 28 29 33
15 66
Page 29
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
A11
A13
A12/BC*
CK*
ODT
CS*
NC
VSS
VSSQ
WE*
CAS*
RAS*
VDDQ
VDD
BA1
CK
A5
A3
ZQ
DQ1
DQ0
DQ3
DQ2
DQ4
DQ5
DQ6
DQ7
DQS
DQS*
DM/TDQS
TDQS*
VREFCA
VREFDQ
A0
A2
A1
A7
A6
A4
A8
RESET*
NC
BA2
CKE
BA0
A9
A10/AP
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NC
NC
CS1 IS FOR 2G DDP RANK CONTROL
NC
NC
NC
NC
NC
A14/A15 FOR 2G/4G MONO ONLY
NC
NC
NC NC
NC
2
1
C3432
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3420
20%
0.47UF
201
CERM-X5R-1
4V
21
R3430
201
240
1/20WMF1%
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3430
OMIT_TABLE
MT41J128M8HX-187E
128MX8-SDRAM-1066MHZ
FBGA
21
R3420
201
240
1/20WMF1%
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3420
OMIT_TABLE
MT41J128M8HX-187E
128MX8-SDRAM-1066MHZ
FBGA
2
1
C3412
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3411
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3410
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3402
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3401
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3400
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3431
20%
0.47UF
201
CERM-X5R-1
4V
21
R3410
201
240
1/20WMF1%
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3410
OMIT_TABLE
FBGA
MT41J128M8HX-187E
128MX8-SDRAM-1066MHZ
21
R3400
201
240
1/20WMF1%
H8
H3
D9
D1
C9
B8
B2
L9
L1
J9
J1
F8
F2
D8
B1
N9
N1
A8
A1
E1
J8
E9
E2
C1
B9
M9
M1
K9
K1
G8
G2
D7
A9
A2
A7
N2
F3
G1
H9
F1
H1
F9
N7
J7
A3
D3
C3
E7
D2
E8
E3
C8
C2
C7
B3
B7
H2
G9
G7
F7
G3
J3
K8
J2
M3
N8
M2
M8
L2
L8
K2
L3
N3
K7
M7
H7
L7
K3
U3400
OMIT_TABLE
MT41J128M8HX-187E
FBGA
128MX8-SDRAM-1066MHZ
2
1
C3430
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3422
20%
0.47UF
201
CERM-X5R-1
4V
2
1
C3421
20%
0.47UF
201
CERM-X5R-1
4V
DDR3 DRAM Channel B (32-63)
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
MEM_B_A<11>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_CLK_N<0>
MEM_B_ODT<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_RAS_L
=PPLVDDR_S3_MEM_B
MEM_B_BA<1>
MEM_B_CLK_P<0>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_ZQ8
MEM_B_DQ<33>
MEM_B_DQ<38>
MEM_B_DQ<32>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<39>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DM<4>
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<8>
MEM_RESET_L
MEM_B_BA<2>
MEM_B_CKE<0>
MEM_B_BA<0>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_ODT<1>
MEM_B_ZQ8
MEM_B_A<14>
MEM_B_CKE<1>
PPVREF_S3_MEM_VREFDQ
MEM_B_CAS_L
MEM_B_CLK_P<0>
MEM_B_A<11>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_CLK_N<0>
MEM_B_ODT<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_RAS_L
=PPLVDDR_S3_MEM_B
MEM_B_BA<1>
MEM_B_CLK_P<0>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_ZQ11
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DM<7>
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_RESET_L
MEM_B_BA<2>
MEM_B_CKE<0>
MEM_B_BA<0>
MEM_B_A<10>
MEM_B_ODT<1>
MEM_B_ZQ11
MEM_B_A<14>
MEM_B_CKE<1>
MEM_B_A<11>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_CLK_N<0>
MEM_B_ODT<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_WE_L
MEM_B_RAS_L
=PPLVDDR_S3_MEM_B
MEM_B_BA<1>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_ZQ10
MEM_B_DQ<53>
MEM_B_DQ<48>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<54>
MEM_B_DQ<52>
MEM_B_DM<6>
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<8>
MEM_RESET_L
MEM_B_BA<2>
MEM_B_CKE<0>
MEM_B_BA<0>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_ZQ10
MEM_B_A<14>
MEM_B_CKE<1>
MEM_B_A<11>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_CLK_N<0>
MEM_B_ODT<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CAS_L
=PPLVDDR_S3_MEM_B
MEM_B_BA<1>
MEM_B_CLK_P<0>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_ZQ9
MEM_B_DQ<41>
MEM_B_DQ<43>
MEM_B_DQ<47>
MEM_B_DQ<42>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<40>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DM<5>
PPVREF_S3_MEM_VREFCA
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<8>
MEM_RESET_L
MEM_B_BA<2>
MEM_B_CKE<0>
MEM_B_BA<0>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_ODT<1>
MEM_B_ZQ9
MEM_B_A<14>
MEM_B_CKE<1>
MEM_B_RAS_L
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQ<55>
MEM_B_DQ<49>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_DQ<61>
34 OF 110
4.4.0
051-8379
29 OF 73
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
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15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29
33
26 27 28 29
33
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
29
15 28 29 32 66
15 21 28 29 32 66
26 27 28 29 33
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
8
28 29 31
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29 33
26 27 28 29 33
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32
66
29
15 28 29
32 66
15 21 28 29
32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29 33
26 27 28 29 33
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
29
15 28 29 32 66
15 21 28
29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29
32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
8
28 29 31
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
15 66
26 27 28 29 33
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 26 27 28 29
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
29
15 28 29 32 66
15 21 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 28 29 32 66
15 66
15 66
15 66
15 66
15 28 29 32 66
15 28 29 32 66
15 66
Page 30
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
2 CAPS ALONG PACKAGE EDGE 2 CAPS ALONG PACKAGE EDGE
2
1
C3540
CERM
402-LF
2.2UF
6.3V
20%
OMIT_TABLE
2
1
C3541
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3542
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3550
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3551
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3530
402-LF
20%
2.2UF
6.3V
CERM
OMIT_TABLE
2
1
C3531
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3554
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3555
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3544
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3545
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3546
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3534
CERM
20%
2.2UF
6.3V
402-LF
OMIT_TABLE
2
1
C3535
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3520
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3521
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3510
CERM
20%
6.3V
402-LF
2.2UF
OMIT_TABLE
2
1
C3511
CERM
20%
2.2UF
6.3V
402-LF
OMIT_TABLE
2
1
C3512
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3500
CERM
20%
6.3V
402-LF
2.2UF
OMIT_TABLE
2
1
C3501
2.2UF
CERM
402-LF
20%
6.3V
OMIT_TABLE
2
1
C3524
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3525
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3514
CERM
20%
402-LF
6.3V
2.2UF
OMIT_TABLE
2
1
C3515
20%
CERM
402-LF
6.3V
2.2UF
OMIT_TABLE
2
1
C3516
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3504
CERM
402-LF
20%
6.3V
2.2UF
OMIT_TABLE
2
1
C3505
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
DDR BYPASSING 1
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
=PPLVDDR_S3_MEM_A =PPLVDDR_S3_MEM_A
35 OF 110
4.4.0
051-8379
30 OF 73
8
26 27 30
8
26 27 30
Page 31
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
2 CAPS ALONG PACKAGE EDGE
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
2 CAPS ALONG PACKAGE EDGE
2
1
C3640
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3641
402-LF
20%
6.3V
2.2UF
CERM
OMIT_TABLE
2
1
C3642
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3650
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3651
2.2UF
CERM
402-LF
20%
6.3V
OMIT_TABLE
2
1
C3630
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3631
CERM
402-LF
20%
6.3V
2.2UF
OMIT_TABLE
2
1
C3654
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3655
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3644
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3645
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3646
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3634
CERM
20%
2.2UF
6.3V
402-LF
OMIT_TABLE
2
1
C3635
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3620
CERM
20%
2.2UF
6.3V
402-LF
OMIT_TABLE
2
1
C3621
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3610
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3611
6.3V
402-LF
CERM
20%
2.2UF
OMIT_TABLE
2
1
C3612
CERM
402-LF
20%
6.3V
2.2UF
OMIT_TABLE
C3600
402-LF
CERM
6.3V
20%
2.2UF
OMIT_TABLE
2
1
C3601
CERM
402-LF
2.2UF
20%
6.3V
OMIT_TABLE
2
1
C3624
20%
402-LF
CERM
6.3V
2.2UF
OMIT_TABLE
2
1
C3625
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3614
2.2UF
20%
CERM
402-LF
6.3V
OMIT_TABLE
2
1
C3615
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3616
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3604
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
2
1
C3605
CERM
402-LF
20%
2.2UF
6.3V
OMIT_TABLE
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
DDR BYPASSING 2
=PPLVDDR_S3_MEM_B =PPLVDDR_S3_MEM_B
36 OF 110
4.4.0
051-8379
31 OF 73
8
28 29 31
8
28 29 31
Page 32
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
MEM CLOCK TERMINATION
Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM
15 26 27 66
15 26 27 66
81
RP3702
4X0201
36
1/32W
5%
72
RP3702
36
4X0201
5%
1/32W
54
RP3706
4X0201
1/32W
5%
36
63
RP3702
4X0201
5%
1/32W
36
54
RP3702
4X0201
36
5%
1/32W
81
RP3704
5%
1/32W
36
4X0201
63
RP3707
36
5%
1/32W
4X0201
72
RP3703
4X0201
1/32W
5%
36
63
RP3704
4X0201
5%
1/32W
36
54
RP3703
5%
1/32W
4X0201
36
63
RP3703
4X0201
5%
1/32W
36
81
RP3703
4X0201
1/32W
5%
36
54
RP3704
4X0201
1/32W
5%
36
21
R3790
1/20W
5%
36
201
72
RP3706
36
5%
1/32W
4X0201
81
RP3706
5%
36
4X0201
1/32W
54
RP3701
1/32W
5%
4X0201
36
72
RP3701
4X0201
36
5%
1/32W
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 21 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
21
R3700
5%
1/20W
MF
30
201
21
R3701
5%
30
MF
1/20W
201
2
1
C3700
0.1UF
MEM_A_CLK_TERM_R
10%
X5R
6.3V
201
2
1
C3702
6.3V
X5R
0.1UF
10%
201
21
R3704
30
MF
1/20W
5%
201
21
R3705
30
5%
MF
1/20W
201
81
RP3701
5%
1/32W
36
4X0201
63
RP3701
5%
1/32W
36
4X0201
72
RP3707
5%
1/32W
36
4X0201
72
RP3704
4X0201
5%
1/32W
36
63
RP3706
4X0201
5%
1/32W
36
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
15 26 27 66
63
RP3715
1/32W
5%
36
4X0201
54
RP3715
5%
36
4X0201
1/32W
72
RP3715
1/32W
5%
36
4X0201
81
RP3711
1/32W
5%
36
4X0201
81
RP3709
1/32W
5%
36
4X0201
81
RP3715
1/32W
36
5%
4X0201
63
RP3710
4X0201
1/32W
36
5%
63
RP3709
4X0201
1/32W
5%
36
72
RP3711
1/32W
5%
36
4X0201
72
RP3709
4X0201
5%
1/32W
36
81
RP3708
5%
1/32W
36
4X0201
72
RP3708
5%
1/32W
36
4X0201
63
RP3711
5%361/32W
4X0201
54
RP3709
4X0201
36
5%
1/32W
63
RP3708
5%361/32W
4X0201
54
RP3713
5%361/32W
4X0201
54
RP3710
5%361/32W
4X0201
72
RP3710
5%
1/32W
36
4X0201
81
RP3710
5%
1/32W
36
4X0201
54
RP3708
1/32W
36
4X0201
5%
63
RP3713
5%
1/32W
36
4X0201
72
RP3714
1/32W
5%
4X0201
36
81
RP3714
1/32W
5%
4X0201
36
54
RP3714
1/32W
5%
36
4X0201
63
RP3714
1/32W
5%
36
4X0201
72
RP3713
1/32W
5%
36
4X0201
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 21 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 28 29 66
15 21 28 29 66
15 28 29 66
15 28 29 66
2
1
C3704
CERM
25V
5%
3.3PF
201
2
1
C3706
3.3PF
5%
25V
CERM
201
2
1
C3710
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3713
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3712
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3715
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3714
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3717
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3716
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3718
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3720
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3722
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3724
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3727
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3726
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3729
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3728
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3730
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3733
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C3732
4V
CERM-X5R-1
201
0.47UF
20%
81
RP3707
5%
36
4X0201
1/32W
15 26 27 66
21
R3791
5%
36
1/20W
201
21
R3793
5%
36
1/20W
201
21
R3792
1/20W
36
5%
201
81
RP3713
36
1/32W
5%
4X0201
15 21 26 27 66
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
Memory Active Termination
MEM_A_CLK_N<0>
MEM_A_A<3>
MEM_A_BA<0>
MEM_B_CLK_P<0>
=PPDDRVTT_S0_MEM_B
=PPDDRVTT_S0_MEM_A
MEM_A_BA<1>
MEM_A_A<0>
MEM_A_CKE<1>
MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_A<2>
MEM_A_A<11>
MEM_A_A<5>
MEM_A_A<6>
VOLTAGE=0V
MEM_B_CLK_TERM_R
VOLTAGE=0V
MEM_A_A<9>
MEM_A_CS_L<0>
MEM_A_CKE<0>
MEM_A_A<1>
MEM_A_A<4>
MEM_A_A<10>
MEM_A_A<13>
MEM_B_CLK_N<0>
MEM_B_CKE<0>
MEM_A_CLK_P<0>
MEM_A_WE_L
MEM_A_BA<2>
MEM_B_A<8>
MEM_B_CAS_L
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_CS_L<1>
MEM_A_A<7>
MEM_A_A<14>
MEM_A_A<8>
MEM_A_A<12>
MEM_B_A<0>
MEM_B_A<4>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<9>
MEM_B_WE_L
MEM_B_A<14>
MEM_B_A<1>
MEM_B_BA<0>
MEM_B_ODT<1>
MEM_B_CKE<1>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_BA<1>
MEM_B_A<13>
MEM_B_A<3>
MEM_B_A<12>
MEM_B_A<2>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_A<7>
MEM_B_RAS_L
MEM_B_BA<2>
MEM_B_ODT<0>
37 OF 110
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15 26 27 66
15 28 29 66
8
8
15 28 29 66
15 26 27 66
Page 33
OUT
OUT
V-
V+
V-
V+
V-
V+
V-
V+
IN
NC
NC
NC
RESET*
A0
A1
A2
SCL
SDA
P0
P1
P2
P5
P6
P7
P3
P4
THRM
VCC
GND
PAD
NC
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTA
SCL
SDA
A0
A1
GND
IN
BI
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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SIZE
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
(OD)
RST* on ’platform reset’ so that system
NOTE: Must not enable more than two SO-DIMM margining
buffers at once or VRef source may be overloaded.
VREFMRGN:YES - Stuffs VREF Margining
BOM options provided by this page:
Addr=0x30(WR)/0x31(RD)
Addr=0x98(WR)/0x99(RD)
VREFMRGN:NO - Bypasses VREF Margining
+750uA - -528uA (- = sourced) +33uA - -33uA (- = sourced)
D
1.5V (DAC: 0x3A)
0.000V - 1.501V (0x00 - 0x74)
1.998V - 1.002V (+/- 498mV)
8.59mV / step @ output
MEM VREG
5
D
DAC Channel:
PCA9557D Pin:
DAC range:
Nominal value
DAC step size:
VRef current:
Margined target:
1
A
0.000V - 1.501V (0x00 - 0x74)
C
3
- =PP3V3_S3_VREFMRGN
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
Circuitry.
Circuitry.
- =PPVTT_S3_DDR_BUF
Page Notes
Power aliases required by this page:
Signal aliases required by this page:
10mA max load
7
CPU GTLREF (FSB)
0.7V (DAC: 0x8B)
0.200V - 1.050V (+/- 500mV)
0.000V - 1.191V (0x00 - 0x5C)
9.24mV / step @ output
0.75V (DAC: 0x3A)
0.300V - 1.200V (+/- 450mV)
+3.4mA - -3.4mA (- = sourced)
7.69mV / step @ output
both at the same time!
(RSVD for FBVREF)
a DAC output, cannot enable
NOTE: MEMVREG and FRAMEBUF share
MEM VREF DQ MEM VREF CA
Required zero ohm resistors when no VREF margining circuit stuffed
soft-resets and sleep/wake cycles.
NOTE: Margining will be disabled across all
watchdog will disable margining.
52
2
1
C3910
201
10%
X5R
6.3V
0.1UF
VREFMRGN:YES
21
R3942
22.6K
1%
PLACE_NEAR=R7320.2:1mm
VREFMRGN:YES
MF
1/20W
201
2
1
R3940
VREFMRGN:YES
100K
201
1/20W
MF
5%
2
1
R3945
201
1/20W
MF
VREFMRGN:YES
5%
100K
10 65
21
R3944
1%
PLACE_NEAR=R1005.2:1mm
267
VREFMRGN:YES
MF
1/20W
201
B4
B1
C4
C1
C2
C3
U3920
VREFMRGN:YES
UCSP
MAX4253
CRITICAL
B4
B1
A4
A1
A2
A3
U3920
UCSP
MAX4253
VREFMRGN:YES
CRITICAL
B4
B1
A4
A1
A2
A3
U3940
VREFMRGN:YES
MAX4253
UCSP
CRITICAL
B4
B1
C4
C1
C2
C3
U3940
VREFMRGN:YES
MAX4253
UCSP
CRITICAL
21
R3900
NONE
OMIT
SHORT
402
NONE
NONE
21
R3910
OMIT
NONE
SHORT
NONE
402
NONE
25
21
R3921
PLACE_NEAR=U3230.E1.1:2.54MM
201
1/20W
MF
VREFMRGN:YES
1%
200
21
R3922
PLACE_NEAR=R3921.2:1MM
201
1/20W
MF
VREFMRGN:YES
133
1%
21
R3923
PLACE_NEAR=U3230.J8:2.54MM
VREFMRGN:YES
1/20W
MF
1%
200
201
21
R3924
PLACE_NEAR=R3923.2:1MM
201
1/20W
MF
1%
133
VREFMRGN:YES
2
1
R3925
100K
201
1/20W
MF
VREFMRGN:YES
5%
2 1
R3920
MF
100K
1/20W
5%
201
VREFMRGN:YES
16
17
2
1
15
14
13
12
11
10
9
7
6
8
5
4
3
U3910
QFN
PCA9557
VREFMRGN:YES
CRITICAL
41
41
5
4
2
1
8
7
6
3
10
9
U3900
CRITICAL
MSOP
DAC5574
VREFMRGN:YES
41
41
2
1
C3901
10%
201
X5R
6.3V
VREFMRGN:YES
0.1UF
2
1
C3900
VREFMRGN:YES
2.2UF
CERM
402-LF
20%
6.3V
2
1
C3940
10%
201
X5R
6.3V
VREFMRGN:YES
0.1UF
2
1
C3920
0.1UF
VREFMRGN:YES
6.3V
X5R
201
10%
RES,MF,1/20W,0.0 OHM,5,0201,SMD
117S0002
2
VREFMRGN:NOR3921,R3923
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
FSB/DDR3 Vref Margining
=PP3V3_S3_VREFMRGN
MIN_NECK_WIDTH=0.15 MM
PPVREF_S3_MEM_VREFCA
MIN_LINE_WIDTH=0.3 mm
VOLTAGE=0.75V
=PPVTT_S3_DDR_BUF
VREFMRGN_CA_BUF
=I2C_VREFDACS_SCL
VREFMRGN_CA_DRAM
VREFMRGN_DQ_DRAM
PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
VREFMRGN_DQ_DRAM_EN
VREFMRGN_DQ_BUF
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
VREFMRGN_CPUGTLREF_BUF
DDRREG_FB
CPU_GTLREF
MIN_LINE_WIDTH=0.3 mm
PPVREF_S3_MEM_VREFDQ
VOLTAGE=0.75V
MIN_NECK_WIDTH=0.2 mm
=I2C_VREFDACS_SDA
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PP3V3_S3_VREFMRGN_CTRL
MIN_LINE_WIDTH=0.3 mm
VREFMRGN_MEMVREG_BUF
VREFMRGN_MEMVREG_FBVREF
VREFMRGN_MEMVREG_EN
PCA9557D_RESET_L
VREFMRGN_CPUGTLREF_EN
VREFMRGN_CA_DRAM_EN
39 OF 110
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051-8379
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8
26 27 28 29
8
52
26 27 28 29
Page 34
OUT
IN
IN
IN
IN
IN
BI
BI
OUT
OUT
OUT
OUT
S
G
D
RESET*
OUT
EN
MR*
GND
THRM
IN
VDD
SENSE
+
-
PAD
(OD)
0.7V
DLY
OUT
IN
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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8 7 5 4 2 1
DLY = 60 MS +/- 20%
514S0335
CHANNEL
0.750 A (EDP)
P-TYPE
3V S3 WLAN FET
TPCP8102
20-30 MOHM @2.5V
MOSFET
LOADING
RDS(ON)
AIRPORT
BLUETOOTH
7
16
57
21
C4030
0.1UF
X5R201
PLACEMENT_NOTE=Place close to J4001.
10%
6.3V
16 67
16 67
21
C4031
0.1UF
PLACEMENT_NOTE=Place close to J4001.
6.3V
10% 201X5R
7
16 67
7
16 67
2
1
C4021
6.3V
10%
201
X5R
0.1UF
PLACEMENT_NOTE=Place close to Q4050.
7
18 68
7
18 68
2
1
C4020
10V
20%
805
X5R
10UF
PLACEMENT_NOTE=Place close to Q4050.
7
16 67
7
16 67
43
21
R4052
1%
CRITICAL
0.25W
0.020
805
MF-LF
42 71
42 71
321
4
8765
Q4050
CRITICAL
23V1K-SM
TPCP8102
1
9
2
4
8
3
7
5
6
U4002
TDFN
SLG4AP016V
CRITICAL
2
1
C4053
201
6.3V
10%
X5R
0.1UF
16
25
19 57
2
1
R4053
5%
201
MF
100K
1/20W
2
1
R4055
1/20W
1%
201
MF
100K
2
1
R4054
1/20W
1%
201
MF
232K
2
1
C4032
PLACE_NEAR=J4001.27:1.5mm
0.1UF
X5R
201
10%
6.3V
9
8
7
6
5
4
3
2
18
17
16
15
14
13
12
11
10
1
21
20
19
J4001
SSD-K99
CRITICAL
F-RT-SM1
7
38 39
21
C4050
10%
16V
402
X5R
0.1UF
2
1
C4051
16V
10%
402
0.033UF
X5R
21
R4050
1/20W
5%
201
MF
100K
2
1
R4051
5%
1/20W
201
MF
10K
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
X21 WIRELESS CONNECTOR
=PP3V3_S3_WLAN
PCIE_AP_D2R_N
WIFI_EVENT_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
PP3V3_WLAN_R
ISNS_AIRPORT_N
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
=PP3V3_S3_BT
PCIE_AP_D2R_P
PCIE_WAKE_L
AP_RESET_CONN_L
PCIE_AP_R2D_P
PCIE_AP_R2D_C_P
ISNS_AIRPORT_P
PM_WLAN_EN_L
P3V3WLAN_SS
AP_CLKREQ_L
AP_RESET_L
P3V3WLAN_VMON
AP_PWR_EN
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=1 mm
PP3V3_WLAN_F
=PP3V3_S3_WLAN
AP_CLKREQ_Q_L
USB_BT_N
USB_BT_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_N
40 OF 110
4.4.0
051-8379
34 OF 73
7 8
7
7
67
7
39
8
34
7
7
67
Page 35
OUT
OUT
NC
NC
OUT
OUT
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SATA SSD
4 3
2 1
R4599
0612
MF
1W
0.003
1%
CRITICAL
42 71
42 71
9
8
7
6
5
4
3
2
18
17
16
15
14
13
12
11
10
1
21
20
19
J4501
CRITICAL
SSD-K99
F-RT-SM1
21
R4510
201
5%
MF
0
1/20W
21
R4511
201
0
1/20W
MF
5%
2
1
C4501
0.1UF
20%
CERM
10V
PLACE_NEAR=J4501.1:1.5mm
402
18 67
18 67
18 67
18 67
21
C4516
X5R10V10% 201
0.01UF
PLACE_NEAR=J4501.3:1.5MM
21
C4510
PLACE_NEAR=J4501.8:1.5MM
10V 20110% X5R
0.01UF
21
C4511
PLACE_NEAR=J4501.7:1.5MM
20110V10% X5R
0.01UF
21
C4515
PLACE_NEAR=J4501.4:1.5MM
10V10% 201X5R
0.01UF
SYNC_DATE=07/07/2010
SATA CONNECTOR
SYNC_MASTER=K16_MLB
ISNS_HDD_N
ISNS_HDD_P
=PP3V3_S0_HDD
TP_SSD_RSRVD
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
SMC_HDD_OOB_TEMP
SMC_HDD_TEMP_CTL_CONN
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_R2D_N
SMC_HDD_TEMP_CTL
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SMC_HDD_OOB_TEMP_CONN
SATA_HDD_R2D_P
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
VOLTAGE=5V
PP3V3_S0_HDD_R
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38
7
67
7
67
7
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7
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67
Page 36
OUT1
GND
TPAD
OUT2
OC1*
IN
EN1
EN2
OC2*
BI
BI
SYM_VER-1
IN
OUT
IN
OUT
VCC
GND
SELOE*
D+
D-
Y+
Y-
M+
M-
IOIONC
GND
VBUS
NC
IN
VBUS
D-
D+
GND
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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SIZE
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PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Right USB Port
SEL=1 Choose USB
SEL=0 Choose SMC
(USB_EXTA_MUXED_N)
(USB_EXTA_MUXED_P)
514-0740
D4600.5
D4600.4
USB/SMC Debug Mux
Port Power Switch
9
6
7
5
8
2
1
4
3
U4690
MSOP
CRITICAL
TPS2052B
21
L4605
CRITICAL
0603
FERR-220-OHM-2.5A
PLACE_NEAR=J4600.1:3 mm
2
1
C4695
OMIT_TABLE
10UF
603
6.3V
X5R
20%
2
1
C4691
20%
CERM
10V
402
0.1UF
18 68
18 68
2
1
C4650
0.1UF
SMC_DEBUG:YES
10%
6.3V
X5R
201
2
1
R4650
10K
5%
201
1/20W
MF
4 3
21
L4600
DLP11S
90-OHM-100MA
CRITICAL
PLACE_NEAR=D4600.3:2 mm
PLACE_NEAR=D4600.2:2 mm
7
38 39 40
7
38 39 40
38
21
R4651
5%
SMC_DEBUG:NO
0
201
1/20W
MF
21
R4652
MF
1/20W
201
SMC_DEBUG:NO
0
5%
2
1
C4605
0.01uF
CERM
402
20%
16V
18
2
1
C4690
OMIT_TABLE
6.3V
20%
603
X5R
10UF
1
2
9
10
8
5
4
3
7
6
U4650
SMC_DEBUG:YES
TQFN
PI3USB102ZLE
CRITICAL
SIGNAL_MODEL=USB_MUX
6
4 5
1
D4600
RCLAMP0502N
PLACE_NEAR=J4600.2:2 mm
CRITICAL
SLP1210N6
PLACE_NEAR=J4600.3:2 mm
7
37 57
2
1
C4696
6.3V
POLY-TANT
20%
100UF
CASE-B2-SM
CRITICAL
1
6
5
4
3
2
J4600
CRITICAL
F-RT-TH
USB-RIGHT-K99
SYNC_MASTER=K16_MLB
External USB Connectors
SYNC_DATE=07/07/2010
=PP5V_S3_RTUSB
=USB_PWR_EN
USB_EXTA_OC_L
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
PP5V_S3_RTUSB_A_ILIM
USB_EXTA_MUXED_N
=PP3V42_G3H_SMCUSBMUX
MIN_LINE_WIDTH=0.5 mm
PP5V_S3_RTUSB_A_F
VOLTAGE=5V
MIN_NECK_WIDTH=0.375 mm
USB_LT1_P
USB_LT1_N
USB_EXTA_N
USB_EXTA_P
USB_EXTA_MUXED_P
USB_DEBUGPRT_EN_L
SMC_RX_L
SMC_TX_L
46 OF 110
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68 71
8
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71
68 71
Page 37
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
516S0862
LIO CONNECTOR
2
1
C4720
10%
0.1UF
6.3V
X5R
PLACE_NEAR=J4700.32:1.5mm
201
2
1
C4710
10%
0.1UF
201
X5R
6.3V
PLACE_NEAR=J4700.30:1.5mm
2
1
C4700
10%
0.1UF
201
X5R
6.3V
PLACE_NEAR=J4700.20:1.5mm
9
8
7
6
5
4
38
37
36
35
34
33
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J4700
AXK736327G
F-ST-SM
SYNC_MASTER=N/A
SYNC_DATE=N/A
LIO CONNECTORS
=PP1V8R1V5_S0_AUDIO
=PP3V42_G3H_ONEWIRE
SYS_ONEWIRE
SMC_BC_ACOK
=USB_PWR_EN
USB_EXTD_OC_L
=PP3V3_S0_AUDIO
USB_CAMERA_N
USB_CAMERA_P
USB_EXTD_N
USB_EXTD_P
AUD_GPIO_3
=I2C_LIO_SDA
HDA_SYNC
HDA_RST_L
HDA_SDIN0
HDA_BIT_CLK
SPKRAMP_INR_N
SPKRAMP_INR_P
AUD_IPHS_SWITCH_EN
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
=I2C_LIO_SCL
=I2C_MIKEY_SDA
=I2C_MIKEY_SCL
HDA_SDOUT
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7 8
7 8
7
38
7 9
38 39
7
36 57
7
18
7 8
7
18 68
7
18 68
7
18 68
7
18 68
7
48
7
41
7
19 68
7
19 68
7
19 68
7
19 68
7
48 71
7
48 71
7
19
7
17
7
19
7
41
7
41
7
41
7
19 68
Page 38
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
BI
IN
IN
OUT
BI
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
OUT
IN
IN
BI
BI
OUT
IN
OUT
OUT
NC
OUT
OUT
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
OUT
OUT
P13
P14
P15
P16 P66
P10
P11
P12
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P60
P61
P62
P63
P64
P65
P67
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P84
P85
P86
P90
P91
P92
P93
P94
P95
P96
P97
P35
P83
P82
(1 OF 3)
PA5
PA4
PA0
PA1
PA2
PA3
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE0
PE1
PE2
PE3
PE4
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
(2 OF 3)
RES*
NMI
VSS
VCLVCC
NC
MD2
MD1
ETRST
AVSS
AVREF
AVCC
EXTAL
XTAL
(3 OF 3)
IN
NC
IN
OUT
IN
BI
OUT
BI
BI
BI
BI
IN
IN
IN
OUT
BI
IN
IN
IN
BI
BI
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER
SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(DEBUG_SW_2)
(DEBUG_SW_1)
If SMS interrupt is not used, pull up to SMC rail.
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
H8S2117-R:
(EXCARD_OC_L)
(EXCARD_CP)
(OC)
(OC)
(OC)
(OC)
(OC)
(SMC_PECI_VREF)
(SMC_PECI)
(SMC_PECI_VSTP)
(OC)
(OC)
(EXCARD_PWR_EN)
(OC)
(OC)
2
1
C4902
20%
22UF
603
6.3V
OMIT_TABLE
X5R-CERM-1
7
19 40
7
39 40 50
7
39 46
2
1
C4907
BYPASS=U4900.E1:D2:5 mm
4V
CERM-X5R-1
201
0.47UF
20%
2
1
C4903
10V
0.1UF
CERM
20%
402
2
1
C4920
10V
402
20%
BYPASS=U4900.M12:L9:5 mm
CERM
0.1UF
21
R4999
MF
1/20W
5%
4.7
PLACE_NEAR=C4920.1:2 mm
201
2
1
C4904
0.1UF
10V
20%
CERM
402
2 1
XW4900
SM
19
53
2
1
C4905
10V
0.1UF
CERM
20%
402
19
57
25 49 57
39
2
1
C4906
CERM
10V
402
0.1UF
20%
43
42
39
39
43
42
43
39
39 46
7 9
37 39
7
36 38 39 40
7
36 38 39 40
7
57
41
2
1
R4909
MF
5%
10K
1/20W
201
7
40
7
40
2
1
R4901
MF
1/20W
5%
10K
201
2
1
R4902
MF
1/20W
10K
5%
201
2
1
R4903
1/20W
MF
5%
0
NO STUFF
201
2
1
R4998
MF
1/20W
5%
10K
201
36
7
37
19
39
19
45
39
39
39
39
39
39
45
39
39
39
39
39
39 42
39
7
39 40
39
7
39 40
7
39 40
7
39 40
7
39 46 49
41
41
41
41
41
41
39
39
39
7
36 38 39 40
7
36 38 39 40
39
39
7
19 40
19
25
7
40
19
7
19 40
39
39
19 39 57
39
39
39
F1
F4
G4
H4
G1
H2
G3
J4
C6
B5
A6
D5
C7
B6
A7
L12
N13
M13
N12
N11
L10
M11
N10
H12
J11
J10
K13
J12
K11
K12
L13
E4
F3
G2
C3
C1
B2
C2
A1
B4
A5
D4
D6
D7
D8
A8
B7
C8
D9
A9
E10
F13
E12
E13
F11
D12
E11
D13
D10
C12
C13
D11
B13
A12
A13
B12
U4900
LGA-HF
H8S2117
OMIT_TABLE
C4
B3
A4
J2
F2
E2
L6
M7
N6
K6
K7
K8
N7
M8
M4
L4
N4
M5
L5
M6
N5
K5
K4
J1
K2
J3
K1
L7
K9
N8
M9
L8
K10
N9
M10
J13
H11
G12
G10
H13
F12
G13
G11
A11
C11
B10
C10
A10
B9
C9
B8
L2
K3
L1
N2
M2
M3
N1
N3
U4900
LGA-HF
OMIT_TABLE
H8S2117
A3
C5
B11
F10
L3
D2
E1
H10
M1
B1
D3
E3
H1
D1
A2
H3
L9
L11
M12
U4900
LGA-HF
H8S2117
OMIT_TABLE
39
7
19 57
7
35
7
35
7
34 39
39
7
19 40 68
7
19 40 68
7
19 40 68
7
19 40 68
7
19 40 68
25
25 68
39
41
7
19 39 57
19
25 68
41
41
39
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
SMC
LPC_PWRDWN_L
SMC_RSTGATE_L
SMC_P10
LPC_AD<0>
SMC_LRESET_L
SMC_HDD_TEMP_CTL
SMB_0_S0_DATA
PM_SLP_S5_L
SMC_PME_S4_L
SMC_BC_ACOK
SMC_ONOFF_L
PM_SLP_S3_L
SMC_TDO
SMB_BSA_DATA
=SMC_SMS_INT
SMC_LID
SMC_TMS
PM_CLK32K_SUSCLK
SMC_TDI
SMC_G3H_POWERON_L
WIFI_EVENT_L
USB_DEBUGPRT_EN_L
SMC_CASE_OPEN
SMC_SLPS5_L
SMC_ODD_DETECT
SMC_RUNTIME_SCI_L
SMC_DP_HPD_L
PM_SLP_S4_L
SMC_PA1
PM_SYSRST_L
SYS_ONEWIRE
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
SMC_ADC14
SMC_ADC15
SMC_SYS_LED
SMC_MCP_SAFE_MODE
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH3
MIN_NECK_WIDTH=0.10 MM
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 MM
SMC_XTAL
SMC_TRST_L
SMC_MD1
SMC_KBC_MDE
SMC_NMI
SMC_VCL
GND_SMC_AVSS
SMC_EXTAL
SMC_RESET_L
PM_CLKRUN_L
SMB_MGMT_CLK
SMC_RX_L
SMC_TX_L
SMC_NB_MISC_ISENSE
SMC_BATT_ISENSE
SMC_PBUS_VSENSE
SMC_DCIN_ISENSE
SMC_GPU_VSENSE
SMC_GPU_ISENSE
SMC_CPU_VSENSE
SMC_CPU_ISENSE
SMC_BIL_BUTTON_L
SMC_ADAPTER_EN
SMC_PM_G2_EN
SMC_RX_L
SMC_SYS_KBDLED
SMC_GFX_THROTTLE_L
SMB_MGMT_DATA
LPC_SERIRQ
LPC_CLK33M_SMC
LPC_FRAME_L
LPC_AD<3>
LPC_AD<2>
LPC_AD<1>
SMC_BMON_MUX_SEL
SMC_P24
SMC_P20
PM_PWRBTN_L
SMC_PROCHOT_3_3_L
IMVP_VR_ON
PM_RSMRST_L
RSMRST_PWRGD
SMC_TCK
SMC_HDD_OOB_TEMP
SMS_ONOFF_L
SMC_PA0
PM_BATLOW_L
SMB_A_S3_CLK
SMB_0_S0_CLK
SMC_GFX_OVERTEMP_L
SMC_PB4
SMC_WAKE_SCI_L
SMC_TX_L
MEM_EVENT_L
ALL_SYS_PWRGD
=PP3V3_S5_SMC
PP3V3_S5_AVREF_SMC
49 OF 110
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E5
39
39
39
39
39
39 42 43
39
43
39
39
39
39
8
39
39
Page 39
D
S G
IN
OUT
BI
IN
D
S G
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
E
Q2
C
BD
Q1
GS
OUT
G
D
S
OUT
IN
REFOUT
MR1*
THRM
GND
RESET*
DELAY
MR2*
VIN
V+
SN0903048
PAD
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SMC Pull-downs
System (Sleep) LED Circuit
Debug Power "Buttons"
SMC Pull-ups
NOTE: Internal pull-ups are to VIN, not V+.
PLACEMENT_NOTEs:
Used on mobiles to support SMC reset via keyboard.
(IPU)
(IPU)
SMC Reset "Button", Supervisor & AVREF Supply
Desktops: 5V
Mobiles: 3.42V
SMC Crystal Circuit
MR1* and MR2* must both be low to cause manual reset.
SMC FSB to 3.3V Level Shifting
TO SMC
TO CPU
SMC Aliases
Unused Pins
4
5
3
Q5059
SOT563
SSM6N37FEAPE
21
R5070
10K
1/20W
MF 2015%
21
R5071
5%
100K
1/20W
MF 201
21
R5073
10K
MF 2015%
1/20W
21
R5074
MF5%
100K
1/20W
201
21
R5076
201
100K
5%
1/20W
MF
21
R5077
10K
1/20W
5% MF 201
21
R5078
10K
MF
1/20W
5% 201
21
R5079
10K
MF
1/20W
5% 201
21
R5080
10K
MF
1/20W
5% 201
21
R5085
201
10K
MF
1/20W
5%
21
R5086
1/20W
10K
201MF5%
21
R5088
10K
5%
1/20W
MF 201
21
R5090
DP_PWR:S0
5% 201
100K
1/20W
MF
38
10 14 65
21
R5062
5%
3.3K
201
1/20W
MF
10 14 65
38
1
2
6
Q5059
SOT563
SSM6N37FEAPE
21
R5091
100K
5%
1/20W
201MF
21
R5092
100K
5%
1/20W
201MF
21
R5089
NO STUFF
5%
10K
201MF
1/20W
21
R5081
10K
MF
1/20W
5% 201
21
R5010
5%
201
MF
1/20W
0
2
1
Y5010
5X3.2-SM
20.00MHZ
CRITICAL
21
C5011
5%
15PF
201
NPO
25V
21
C5010
5%
15PF
NPO
25V
201
21
R5087
MF
1/20W
5%
470K
201
21
R5093
5% 201
1/20W
MF
10K
38
38
38
38
38 19
38
38
38
38
38 42
38
38
38
38
21
R5096
1/20W
201
5%
0
MF
38 19
38
38
38
38
21
R5094
10K
5%
1/20W
MF 201
38
38
38
2
1
R5032
SIL
1.47K
1%
1/16W
MF-LF
402
2
1
R5031
SIL
523
1%
1/16W
MF-LF
402
2
1
R5030
SIL
40.2
1%
1/16W
MF-LF
402
1 2463
5
Q5030
SIL
DMB54D0UV
SOT-563
49
4
3
5
Q5060
DMB53D0UV
SOT-563
2
1
R5061
201
MF
1/20W
5%
100K
1
2
6
Q5060
SOT-563
DMB53D0UV
2
1
R5060
201
MF
1/20W
5%
10K
38
19
3
1
9
5
8
7
6
2
4
U5010
VREF-3.3V-VDET-3.0V
DFN
7
46
7
38 39 46
2
1
R5000
5%
1K
1/20W
201
MF
2
1
C5026
10%
201
X5R
10V
0.01UF
2
1
C5025
6.3V
20%
603
X5R
10uF
OMIT_TABLE
2
1
C5001
201
10V
0.01UF
10%
X5R
7
38 40 50
2
1
C5020
0.47UF
6.3V
10%
402
CERM-X5R
38 39
38
2
1
R5015
Place R5015 on BOTTOM side
SILK_PART=PWR_BTN
OMIT
0
5%
1/10W
MF-LF
603
2
1
R5014
Place R5014 on TOP side
SILK_PART=PWR_BTN
OMIT
0
5%
1/10W
MF-LF
603
2
1
R5001
PLACEMENT_NOTE=Place R5001 on BOTTOM side
SILK_PART=SMC_RST
OMIT
5%
0
1/10W
603
MF-LF
38
38
38
38
21
R5040
5%
10K
1/20W
MF 201
38 39
21
R5020
DP_PWR:S0
MF
1/20W
201
0
5%
7
19 38 57
61
21
R5021
DP_PWR:SMC
MF
1/20W
201
0
5%
38
21
R5022
5%
0
201
1/20W
MF
DP_PWR:SMC
PLACE_NEAR=Q9441.2:5 mm
38 39 61
12
R5098
100K
5%
1/20W
MF 201
7
38 39 46
SMC Support
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
SMC_GFX_OVERTEMP_L
SMC_SLPS5_L
SMC_ADC15
SMS_X_AXIS
SMC_DP_HPD_L
PM_SLP_S3_L
DP_EXT_HPD_L
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ADC14
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
SMC_NB_MISC_ISENSE
SMC_ANALOG_ID
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
=SMC_SMS_INT
MAKE_BASE=TRUE
SMC_G3H_POWERON_L
MCP_SPKR
SMC_LCDBKLT_ISENSE
MAKE_BASE=TRUE
SMC_WLAN_ISENSE
MAKE_BASE=TRUE
SMC_HDD_ISENSE
MAKE_BASE=TRUE
SMC_CSREG_ISENSE
MAKE_BASE=TRUE
SMC_LCDBKLT_VSENSE
MAKE_BASE=TRUE
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE
SMC_1V5S3_ISENSE
MAKE_BASE=TRUE
TP_SMC_ANALOG_ID
MAKE_BASE=TRUE
TP_SMC_GPU_ISENSE
MAKE_BASE=TRUE
SMC_MCP_VSENSE
MAKE_BASE=TRUE
SMC_GFX_THROTTLE_L
MCP_WAKE_REQ_L
SMS_INT_L
MAKE_BASE=TRUE
SMC_MCP_SAFE_MODE
SMC_PH3
SMC_P24
SMC_P10
SMC_P20
SMC_RSTGATE_L
SMC_FAN_3_CTL
SMC_FAN_2_CTL
MAKE_BASE=TRUE
TP_SMC_PH3
MAKE_BASE=TRUE
TP_SMC_P24
TP_SMC_P20
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_P10
NO_TEST=TRUE
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
SMC_FAN_3_TACH
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMC_FAN_3_CTL
NO_TEST=TRUE
NC_SMC_FAN_2_TACH
MAKE_BASE=TRUE
SMC_FAN_2_TACH
TP_SMC_FAN_1_TACH
MAKE_BASE=TRUE
SMC_FAN_1_TACH
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SMC_FAN_2_CTL
SMC_FAN_1_CTL
SMC_SYS_KBDLED
SMS_ONOFF_L
TP_SMC_FAN_1_CTL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_SYS_KBDLED
MAKE_BASE=TRUE
TP_SMS_ONOFF_L
SMC_THRMTRIP
SMC_PROCHOT
CPU_PROCHOT_BUF
CPU_PROCHOT_L_R
CPU_PROCHOT_L
PM_THRMTRIP_L
SMC_PROCHOT_3_3_L
=PP3V3_S0_SMC
SMC_EXTAL
SMC_TPAD_RST_L
SMC_ONOFF_L
=PP3V3_S5_SMC
=PPVIN_S5_SMCVREF
VOLTAGE=0V
MIN_LINE_WIDTH=0.4 mm
GND_SMC_AVSS
MIN_NECK_WIDTH=0.1 mm
SMC_ONOFF_L
PP3V3_S5_AVREF_SMC
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm
SMC_MANUAL_RST_L
SMC_RESET_L
SYS_LED_ANODE
SMC_SYS_LED
SYS_LED_ILIM
=PP5V_S3_SYSLED
SYS_LED_L_VDIV
SYS_LED_L
SMC_PA0
SMS_INT_L
=DP_PWR_EN
MAKE_BASE=TRUE
DP_PWR_EN
SMC_XTAL_R
SMC_XTAL
SMC_PA1
SMC_BC_ACOK
SMC_G3H_POWERON_L
SMC_DP_HPD_L
SMC_PB4
=PP3V3_S5_SMC
SMC_LID
SMC_BIL_BUTTON_L
SMC_CASE_OPEN
SMC_ADAPTER_EN
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
SMC_ONOFF_L
SMC_TX_L
SMC_RX_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_ODD_DETECT
SMC_TCK
PP3V3_WLAN_F
WIFI_EVENT_L
=PP3V3_SMC_PME
SMC_PME_S4_L
50 OF 110
4.4.0
051-8379
39 OF 73
38
42
42
42
43
43
43
42
42
8
38
8
38 39
8
38 42 43
38
8
38
39
38
38
7 9
37 38
38 39
38 39
38
8
38 39
7
38 46 49
38
38
19 38 57
7
38 39 46
7
36 38 40
7
36 38 40
7
38 40
7
38 40
7
38 40
38
7
38 40
7
34
7
34 38
8
38 46
Page 40
OUT
IN
E0/NC0
SCL
SDA
E2
E1
WC*
VCC
VSS
IN
BI
NC
BI
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUT
IN
IN
BI
BI
BI
OUT
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
LPC+SPI Connector
516S0573
SPI Bus Series Termination
Read: 0xAD/0xAF
Write: 0xAC/0xAE
EFI Debug ROM
2
1
R5126
47
5%
LPCPLUS
201
1/20W
MF
47 68
21
R5122
47
5%
201
1/20W
MF
21
R5112
15
5%
201
1/20W
MF
19 68
2
1
R5127
47
LPCPLUS
5%
201
1/20W
MF
2
1
R5128
0
5%
LPCPLUS
201
1/20W
MF
7
4
8
5
6
3
2
U5101
M24M01-R
CRITICAL
SO8N
EFI_DEBUG
2
1
R5101
EFI_DEBUG
5%
0
1/20W
MF
201
2
1
R5104
NO STUFF
0
5%
1/20W
MF
201
2
1
R5102
NO STUFF
5%
0
1/20W
MF
201
2
1
R5103
EFI_DEBUG
0
5%
1/20W
MF
201
2
1
C5101
402
0.1UF
CERM
10V
20%
EFI_DEBUG
41
41
9
8
7
6
5
4
34
33
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J5100
55909-0374
M-ST-SM
CRITICAL
LPCPLUS
7
19 38 68
7
38 39
7
38 39
7
38
7
25
7
36 38 39
7
38
47 68
21
R5110
5%
15
201
1/20W
MF
19 68
47 68
21
R5111
5%
15
201
1/20W
MF
19 68
7
25 68
7
19 38 68
7
19 38 68
7
19 38 68
7
19 47
7
19 38
7
19 38
7
38 39
7
38 39 50
7
38
7
38 39
7
36 38 39
7
19
7
19 38
7
19 38 68
47 68
21
R5123
5%
15
201
1/20W
MF
19 68
21
R5120
47
5%
201
1/20W
MF
2
1
R5125
47
5%
LPCPLUS
201
1/20W
MF
21
R5121
47
5%
201
1/20W
MF
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
LPC+SPI Debug Connector
SPI_CS0_R_L
SPI_MLB_MISO
=PP3V3_S0_DEBUGROM
DEBUGROM_E1
DEBUGROM_E2
SPI_MOSI
SPI_MISO
SPI_CLK_R
=I2C_DEBUGROM_SDA
=I2C_DEBUGROM_SCL
SPI_MOSI_R
SPI_MLB_MOSI
SPI_MLB_CLK
SPI_CLK
SPI_MLB_CS_L
SPI_CS0_L
SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS_GPIO
SMC_RX_L
SMC_NMI
SMC_RESET_L
SMC_TCK
SMC_TDI
LPC_PWRDWN_L
LPC_SERIRQ
SPI_ALT_CS_L
SPI_ALT_CLK
SPIROM_USE_MLB
LPC_AD<3>
LPC_AD<2>
LPC_CLK33M_LPCPLUS
=PP5V_S0_LPCPLUS
=PP3V3_S5_LPCPLUS
SPI_ALT_MISO
SPI_ALT_MOSI
LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
SMC_TMS
PM_CLKRUN_L
SMC_TDO
LPCPLUS_RESET_L
SMC_TRST_L
SMC_MD1
SMC_TX_L
51 OF 110
4.4.0
051-8379
40 OF 73
1
8
68
68
68
7
40 68
7
40 68
7
40 68
7
40 68
7
40 68
7
40 68
7 8
7 8
7
40 68
7
40 68
Page 41
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
U1400
(MASTER)
Internal DP
(MASTER)
U4900
SMC "Management" SMBus Connections
(* = Multiple options)
Samsung LGD Samsung LGD AUO
Battery Manager - (Write: 0x16 Read: 0x17)
Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *
Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *
J9000
K16 K99
MCP89 SMBus 1 is slave port to
(Write: 0xE0 Read: 0xE1)
access internal thermal diodes.
Another slave port is available
at 0x10/0x11, probably not used.
U1400
MCP89
MCP89 SMBus "1" Connections
U4900
SMC
(MASTER)
Left I/O Board
ALS - N/A (Feature Removed)
Finstack Temp - (Write: 0x98 Read: 0x99)
U4900
SMC
(MASTER)
CPU Temp
EMC1413: U5515
J4700
(See Table)
Left I/O Board
Internal DP
(Write: 0x58 Read: 0x59)
Margin Control
(See Table)
J1300
Vref DACs
U3900
EFI Debug Serial
(Write: 0x30 Read: 0x31)
U3910
U5101
(Write: 0xAC/0xAE
Read: 0xAD/0xAF)
(Write: 0x72 Read: 0x73)
Mikey
J4700 (LIO Connector)
SMC
(MASTER)
SMC
Battery
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
(See Table)
J6950
(Write: 0x12 Read: 0x13)
ISL6259 - U7000
J5700
U4900
The bus formerly known as "Battery B"
Battery
(MASTER)
U4900
SMC
Trackpad
SMC "Battery A" SMBus Connections
Battery Charger
(Write: 0x90 Read: 0x91)
(MASTER)
(Write: 0x98 Read: 0x99)
MCP89 SMBus "0" Connections
SMC "0" SMBus Connections
U9701
LP8545 (Bklt)
MCP89
NOTE: SMC RMT bus remains powered and may be active in S3 state
EMC1413: U5535
XDP Connector
DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N
SMC "A" SMBus Connections
SMC "B" SMBus Connections
(Write: 0x98 Read: 0x99)
MCP Temp
(Write: 0xD8 Read: 0xD9)
2
1
R5280
1%
2.61K
1/20W
MF
201
2
1
R5281
1%
2.61K
1/20W
MF
201
2
1
R5261
201
1/20W
MF
4.7K
5%
2
1
R5260
4.7K
5%
201
1/20W
MF
2
1
R5271
201
1/20W
1K
5%
MF
2
1
R5270
1K
5%
1/20W
MF
201
2
1
R5251
NO STUFF
1/20W
5%
MF
2.0K
201
2
1
R5250
NO STUFF
5%
1/20W
MF
2.0K
201
2
1
R5231
5%
2.0K
NO STUFF
1/20W
MF
201
2
1
R5230
NO STUFF
5%
2.0K
1/20W
MF
201
2
1
R5200
5%
1K
201
1/20W
MF
2
1
R5201
1K
5%
201
1/20W
MF
2
1
R5236
5%
0
1/20W
MF
201
2
1
R5235
5%
0
1/20W
MF
201
2
1
R5291
2.0K
201
5%
1/20W
MF
2
1
R5290
MF
5%
201
1/20W
2.0K
2
1
R5243
0
5%
201
1/20W
MF
DPI2C:SMC
2
1
R5242
0
5%
201
1/20W
MF
DPI2C:SMC
12
R5241
DPI2C:MCP
0
1/20W
MF
5%
201
12
R5240
DPI2C:MCP
201
1/20W
0
MF
5%
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
K16/K99 SMus Connections
=I2C_MCPTHMSNS_SCL
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SCL
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL
=I2C_MIKEY_SCL
MAKE_BASE=TRUE
SMBUS_MCP_0_CLK
=I2C_MCPTHMSNS_SDA
=PP3V3_S0_SMBUS_SMC_0_S0
=I2C_TPAD_SDA
=SMBUS_BATT_SDA
SMB_BSA_DATA
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
=SMBUS_CHGR_SDA
=PP3V42_G3H_SMBUS_SMC_BSA
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SCL
SMB_MGMT_DATA
=SMBUS_CHGR_SCL
=SMBUS_BATT_SCL
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
SMB_BSA_CLK
=I2C_TCON_SDA
=I2C_TCON_SCL
SMB_0_S0_CLK
SMB_0_S0_DATA
=I2C_BKL_1_SDA
SMB_MGMT_CLK
=I2C_TPAD_SCL
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
=I2C_MIKEY_SDA
=I2C_PCA9557D_SCL
=I2C_DEBUGROM_SCL
=I2C_DEBUGROM_SDA
=I2C_VREFDACS_SDA
=I2C_VREFDACS_SCL
=I2C_XDP_SCL
=I2C_XDP_SDA
MAKE_BASE=TRUE
I2C_TCON_SCL
=I2C_PCA9557D_SDA
=PP3V3_S0_SMBUS_MCP_0
=I2C_BKL_1_SCL
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_1
MAKE_BASE=TRUE
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
=I2C_LIO_SCL
=I2C_LIO_SDA
SMB_A_S3_CLK
SMB_A_S3_DATA
=I2C_CPUTHMSNS_SDA
=I2C_CPUTHMSNS_SCLSMB_B_S0_CLK
SMB_B_S0_DATA
MAKE_BASE=TRUE
I2C_TCON_SDA
=PP3V3_S5_SMBUS_SMC_MGMT
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
52 OF 110
4.4.0
051-8379
41 OF 73
44
70
70
19 68
70
7
37
19 68
44
8
7
46
49
38
7
70
50
8
70
38
50
49
7
70
38
7
59
7
59
38
38 62
38
7
46
70
7
37
33
40
40
33
33
13
13
71
33
8
62
8
8 8
19 68
19 68
70
7
37
7
37
38
38
44
44 38
38
71
8
70
70
Page 42
OUT
IN
OUT
S
S
D
N-CHANNEL
G
D
G
P-CHANNEL
OUT
OUT
OUT
OUT
V+
REFIN+
IN-
OUT
GND
V+
REFIN+
IN-
OUT
GND
V+
REFIN+
IN-
OUT
GND
V+
REFIN+
IN-
OUT
GND
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(CLIPS AT 6.6A)
(CLIPS AT 0.825A)
DDR3 1V5R1V35 Current Sense / Filter
Max Vdiff: 24.0 mV
PLACEMENT_NOTEs:
Gain: 200x
Place RC close to SMC
Place RC close to SMC
(For R and C)
(For R and C)
Max Vdiff: 14.6 mV
WF: Verify SSD current!
EDP Current: ??? A
Max Vdiff: ??? mV
WF: Verify LCD backlight current!
PLACEMENT_NOTEs:
(200V/V)
CPU Voltage Sense / Filter
(For R and C)
PLACEMENT_NOTEs:
GAIN: 500X
SCALE: 0.667A / V
MAX VOUT: 3.54V
MAX VOUT: 3V
Scale: 0.25A / V
EDP Current: 1.2 A?
(500V/V)
PLACEMENT_NOTEs:
(500V/V)
MAX VOUT: 3.33V
SCALE: 0.2A / V
GAIN: 500X
LCD Backlight Driver Input Current Sense / Filter
(CLIPS AT 0.66A)
(CLIPS AT 2.2A)
DIVIDER: 1/22
Place RC close to SMC
RTHEVENIN = 4573 Ohms
divider when high.
Enables PBUS VSense
EDP Current: 0.727 A?
WF: Verify Airport current!
PBUS Voltage Sense Enable & Filter
MCP Voltage Sense / Filter
HDD Current Sense / Filter
(500V/V)
GAIN: 200X
SCALE: 0.4A / V
MAX VOUT: 3.5V
(For R and C)
AirPort Current Sense / Filter
WF: Verify SO-DIMM current!
Max Vdiff: 13.0 mV
EDP Current: 7 A
39
2
1
C5359
0.22UF
X5R
6.3V
20%
201
21
R5359
MF
201
1%
4.53K
1/20W
57
2
1
R5316
MF
1/20W
201
1%
100K
2
1
R5315
MF
1/20W
201
1%
100K
38
2
1
C5315
0.22UF
201
20%
6.3V
X5R
2
1
R5317
27.4K
1%
201
1/20W
MF
2
1
R5318
5.49K
1%
201
1/20W
MF
4
1
5
2
3
6
Q5315
NTUD3169CZ
SOT-963
39
39
39
39
21
R5365
4.53K
1%
Place close to SMC
1/20W
MF
201
2
1
C5365
20%
6.3V
0.22UF
Place close to SMC
X5R
201
2
1
C5360
0.1UF
10%
X5R
6.3V
201
3
1
6
4
5
2
U5360
INA210
SC70
2
1
C5375
Place close to SMC
0.22UF
X5R
20%
6.3V
201
2
1
C5385
Place close to SMC
6.3V
20%
X5R
201
0.22UF
3
1
6
4
5
2
U5370
SC70
INA210
3
1
6
4
5
2
U5380
SC70
INA211
2
1
C5395
Place close to SMC
0.22UF
X5R
20%
6.3V
201
3
1
6
4
5
2
U5390
SC70
INA211
2
1
C5370
6.3V
X5R
0.1UF
10%
201
2
1
C5380
0.1UF
201
6.3V
10%
X5R
2
1
C5390
10%
0.1UF
X5R
6.3V
201
21
R5375
4.53K
201
MF
1/20W
1%
Place close to SMC
21
R5385
4.53K
1%
Place close to SMC
1/20W
MF
201
21
R5395
201
MF
1/20W
1%
4.53K
52 71
52 71
34 71
34 71
35 71
35 71
62 71
62 71
21
XW5310
SM
PLACE_NEAR=D9701.2:5 MM
2
1
R5319
1%
1/20W
201
1M
MF
2
1
R5320
MF
1/20W
1%
201
47K
21
R5321
PLACE_NEAR=U4900:5 MM
1/20W
1%
MF
201
226K
2
1
C5310
OMIT_TABLE
PLACE_NEAR=U4900:5 MM
0402
20%
6.3V
X5R
2.2UF
38 39
21
XW5359
SM
PLACE_NEAR=R7525.2:5 MM
38
21
R5309
201
1/20W
1%
MF
4.53K
2
1
C5309
6.3V
201
20%
X5R
0.22UF
21
XW5309
PLACE_NEAR=L7400.2:5 MM
SM
SYNC_MASTER=K16_MLB
Voltage & Current Sensing
SYNC_DATE=07/07/2010
MCPVSENSE_IN
PBUS_G3H_VSENSE
PBUSVSENS_EN_L_DIV
=PBUSVSENS_EN
PBUSVSENS_EN_L
PPBUS_G3H
GND_SMC_AVSS
SMC_PBUS_VSENSE
LCDBKLT_VSEN
LCDBKLT_VSEN_DIV
SMC_ADC15
PPVOUT_SW_LCDBKLT
=PP3V3_S0_BKLTISNS
ISNS_LCDBKLT_N
=PP3V3_S0_HDDISNS
ISNS_P5VHDD_IOUT
ISNS_HDD_N
GND_SMC_AVSS
SMC_WLAN_ISENSE
GND_SMC_AVSS
ISNS_P5VWLAN_IOUT
=PP3V3_S3_WLANISNS
ISNS_1V5S3_IOUT
GND_SMC_AVSS
GND_SMC_AVSS
SMC_1V5S3_ISENSE
CPUVSENSE_IN
GND_SMC_AVSS
GND_SMC_AVSS
PPVCORE_S0_MCP
PPVCORE_S0_CPU
SMC_CPU_VSENSE
SMC_MCP_VSENSE
ISNS_1V5_S3_N
ISNS_1V5_S3_P
ISNS_AIRPORT_N
ISNS_AIRPORT_P
ISNS_LCDBKLT_P
SMC_HDD_ISENSE
ISNS_HDD_P
ISNS_LCDBKLT_IOUT
SMC_LCDBKLT_ISENSE
=PP3V3_S3_1V5S3ISNS
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49
38 39 42 43
7
59 62
8
8
38 39 42 43
38 39 42 43
8
38 39 42 43
38 39 42 43
38 39 42 43
38 39 42 43
7 8
7 8
8
Page 43
V+
REFIN+
IN-
OUT
GND
OUT
OUT
IN
OUT
IN
OUT
VER 1
VCC
A
1
0
B1
GND
B0
SEL
IN
IN
IN
IN
OUT
IN
OUT
IN-
IN+ REF
V+
GND
IN
IN
OUT
IN
IN
OUT
IN-
IN+ REF
V+
GND
+IN
-IN
V+
V-
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(200V/V)
R5431:
MAX VOUT: 3.352V
MCP VCore Current Sense Filter
SCALE: 2.5A / V
MAX VOUT: 3.00V
Charger/Load side
Battery side
NOTE: Monitoring current from
battery to PBUS (battery
From charger
Sense R: R7050
Value: 10 mOhm
Max Vdiff: 80mV
PLACEMENT_NOTEs:
(100V/V)
(Sense R "output")
Max Vdiff = 24.8mV
Gain: 100x
Scale: 10A / V
R7593 at the same time!
(For R and C)
(For R and C)
Max VOut: 2.88V
Sense R is R7525, 1mOhm
(Sense R "input")
MAX VOUT: 2.38V
MCP MEM VDD Current Sense / Filter
Sense R: R7020
Value: 20 mOhm
ISL6259 Gain: 20x
MAX VOUT: 1.24V
discharge) across R7050
(100V/V)
NOTE: Do not stuff R5415 and
(For R’s and C)
PLACEMENT_NOTEs:
(For R and C)
PLACEMENT_NOTEs:
PLACEMENT_NOTEs:
DCIN (AMON) Current Sense, RMUX & Filter
(For Rs and C)
CPU VCore Load Side Current Sense / Filter
For production, stuff BMON:PROD
For engineering, stuff BMON:ENG
INA213 Gain: 50x
Chipset Regulators High-Side Current Sense / Filter
ISL6259 Gain: 36x
Battery (BMON) Current Sense, MUX & Filter
PLACEMENT_NOTEs:
(For R and C)
SCALE: 1A / V
From charger
GAIN: 100X
(CLIPS AT 3.3A)
Gain: 36x
Scale: 2.778A / V
GAIN: 200X
PLACEMENT_NOTEs:
VERIFY ALL RESISTOR AND GAINS
2
1
C5417
201
0.1UF
6.3V
10%
X5R
3
1
6
4
5
2
U5402
SC70
INA210
39
2
1
C5436
20%
0.22UF
Place close to SMC
6.3V
402
X5R
38
2
1
C5418
6.3V
BMON:ENG
0.1UF
201
X5R
10%
50
21
R5431
PLACE_NEAR=U5413:2 mm
5%
BMON:PROD
201
1/20W
0
MF
2
1
R5423
1/20W
5%
BMON:ENG
100K
MF
201
2
1
C5459
10%
6.3V
BMON:ENG
0.1UF
X5R
201
38
53
2
1
R5480
NOSTUFF
Place close to SMC
402
MF-LF
1/16W
1%
17.4K
21
R5471
MF-LF
15.0K
1%
1/16W
402
Place close to SMC
38
2
1
C5487
10%
0.0068UF
CERM
25V
402
Place close to SMC
5
6
2
1
3 4
U5413
CRITICAL
NC7SB3157P6XG
SC70
BMON:ENG
38
50 70
50 70
432
1
R5492
CRITICAL
0612
0.002
1%
MF
1W
50
2
1
R5482
MF-LF
1%
NOSTUFF
Place close to SMC
402
1/16W
133K
39
21
R5416
MF
4.53K
1%
201
1/20W
Place close to SMC
2
1
C5472
6.3V
X5R
0.22UF
Place close to SMC
20%
201
54
21
R5415
5%
0
1/20W
MF
201
2
1
C5420
0.1UF
6.3V
X5R
10%
201
3
1
6
4
5
2
U5420
SC70
INA214
9
9
2
1
R5411
201
1/20W
5%
0
MF
39
2
1
C5435
Place close to SMC
402
6.3V
20%
X5R
0.22UF
2
1
C5400
201
X5R
6.3V
10%
0.1UF
2
1
R5410
201
1/20W
5%
0
MF
21
21
2
1
C5434
0.1UF
6.3V
X5R
10%
NOSTUFF
201
21
R5417
1/16W
1%
402
MF-LF
4.53K
Place close to SMC
2
3
1
Q5401
CRITICAL
2SA2154MFV-YAE
SOD
2
1
R5412
118
1/16W
1%
402
MF-LF
21
R5418
201
1%
4.53K
Place close to SMC
1/20W
MF
3
1
6
4
5
2
U5403
INA214
SC70
BMON:ENG
PLACEMENT_NOTE=Place near sense resistor
5
2
1
4
3
U5400
SC70-5
OPA330
2
1
C5470
402
0.068UF
10%
10V
CERM
21
R5481
201
150K
1%
1/20W
MF
21
R5401
300K
201
1%
1/20W
MF
2
1
C5490
402
0.0033UF
10%
50V
CERM
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
Current Sensing
GND_SMC_AVSS
CSREG_IOUT
BMON_INA_OUT
SMC_BMON_MUX_SEL
=PP3V42_G3H_BMON_ISNS
GND_SMC_AVSS
SMC_BATT_ISENSE
BMON_AMUX_OUT
CHGR_AMON
GND_SMC_AVSS
SMC_DCIN_ISENSE
MCPDDRFET_KELVIN
MCPDDR_SENSE_B
SMC_CPU_ISENSE
SMC_CSREG_ISENSE
ISNS_CSREG_N
=PP3V3_S0_CSREGISNS
GND_SMC_AVSS
IMVP6_PMON
MCPDDRFET_SENSE
=PP3V3_S0_MCPDDRISNS
MCPDDR_SENSE_C
CHGR_CSO_R_N
=PPBUS_G3H_R_OUT
ISNS_CSREG_P
SMC_MCP_DDR_ISENSE
GND_SMC_AVSS
MCPCORE_IOUT
=MCPCOREISNS_N
=MCPCOREISNS_P
GND_SMC_AVSS
SMC_MCP_CORE_ISENSE
CHGR_CSO_R_P
MCPDDR_SENSE_E
MCPDDR_SENSE_AMP
=PPBUS_G3H_R_IN
CHGR_BMON
=PP3V3_S0_MCPCOREISNS
MCPCORES0_IMON
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38 39 42 43
38 39 42 43
71
8
38 39 42 43
8
8
71
38 39 42 43
38 39 42 43
8
8
Page 44
BI
BI
BI
BI
BI
BI
THRM_PAD
DN2/DP3
DP2/DN3
VDD
SMDATA
SMCLK
GND
DN1
DP1
THERM*/ADDR
ALERT*
THRM_PAD
DN2/DP3
DP2/DN3
VDD
SMDATA
SMCLK
GND
DN1
DP1
THERM*/ADDR
ALERT*
BI
BI
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Addr: 0xD8(Wr)/0xD9(Rd)
MCP Thermal Diode
Local sensor for MCP Proximity
MCP T-Diode Thermal Sensor
FIXME: OFFGRID
CPU T-Diode Thermal Sensor
Addr: 0x98(Wr)/0x99(Rd)
Local sensor for CPU Proximity
CPU Thermal Diode
DRAM/SSD Temperature
2
1
C5515
10%
0.1UF
201
X5R
6.3V
41
41
2
1
C5535
10%
6.3V
X5R
201
0.1UF
2
3
1
Q5501
PLACEMENT_NOTE=Place Q5501 near DRAMs below MCP
CRITICAL
SOT732-3
BC846BMXXH
21
R5515
47
5%
201
1/20W
MF
21
R5535
5%
47
201
MF
1/20W
2
1
C5522
201
2.2NF
X5R
10V
10%
19 71
19 71
2
1
C5521
201
X5R
10V
2.2NF
10%
10 71
10 71
U5535
PLACEMENT_NOTE=Place U5535 near MCP
CRITICAL
DFN
EMC1413
1
11
7
9
10
6
4
2
5
3 8
U5515
EMC1413
PLACEMENT_NOTE=Place U5515 near CPU
CRITICAL
DFN
2
1
R5517
10K
5%
201
1/20W
MF
2
1
R5516
10K
1%
201
1/20W
MF
2
1
R5536
201
15K
MF
1/20W
1%
2
1
R5537
10K
5%
201
1/20W
MF
2
1
C5520
201
10%
2.2NF
10V
X5R
41
41
2
3
1
Q5535
PLACEMENT_NOTE=Place Q5535 near J9000
CRITICAL
SOT732-3
BC846BMXXH
2
1
C5523
2.2NF
10%
10V
X5R
201
Thermal Sensors
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
=I2C_MCPTHMSNS_SCL
=I2C_MCPTHMSNS_SDA
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
CPU_THERMD_N
CPUTHMSNS_THERM_L
CPUTHMSNS_ALERT_L
DRAMTHMSNS_D2_P
=PP3V3_S0_CPUTHMSNS
DRAMTHMSNS_D2_N
CPU_THERMD_P
PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MCPTHMSNS_ALERT_L
MCPTHMSNS_THERM_L
MCP_THMDIODE_P
MLBR_THMDIODE_P
MLBR_THMDIODE_N
PP3V3_S0_MCPTHMSNS_R
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
=PP3V3_S0_MCPTHMSNS
MCP_THMDIODE_N
55 OF 110
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051-8379
44 OF 73
8
71
71
71
8
Page 45
D
GS
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NC
FAN CONNECTOR
518S0793
GND
MOTOR CONTROL
TACH
5V DC
NC
21
R5665
47K
201
MF
1/20W
5%
2
1
R5660
201
47K
1/20W
5%
MF
2
1
R5661
100K
MF
1/20W
5%
201
2
1
3
Q5660
SOD-VESM-HF
SSM3K15FV
4
3
2
1
6
5
J5600
FF14A-4C-R11DL-B-3H
F-RT-SM
CRITICAL
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
Fan
=PP3V3_S0_FAN
SMC_FAN_0_TACH
SMC_FAN_0_CTL
FAN_RT_TACH
FAN_RT_PWM
=PP5V_S0_FAN
56 OF 110
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38
38
7
7
8
Page 46
BI
BI
OUT
IN
OUT
SYM_VER-1
BI
BI
BI
BI
BI
BI
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
518S0794
IPD Flex Connector
2
1
C5710
PLACE_NEAR=J5700.10:1.5MM
0.1uF
20%
CERM
10V
402
2
1
C5720
0.1UF
X5R
6.3V
201
10%
PLACE_NEAR=J5700.13:1.5MM
7
41 46
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J5700
FF14A-14C-R11DL-B-3H
F-RT-SM
CRITICAL
2
1
C5700
0.1UF
201
10%
X5R
6.3V
PLACE_NEAR=J5700.1:1.5MM
7
41 46
7
38 39 46
7
38 39 46 49
7
39 46
2
1
C5732
X7R-CERM
PLACE_NEAR=J5700.8:1.5MM
201
100PF
10%
25V
2
1
C5733
PLACE_NEAR=J5700.9:1.5mm
201
100PF
25V
X7R-CERM
10%
2
1
C5734
PLACE_NEAR=J5700.11:1.5MM
201
X7R-CERM
100PF
25V
10%
2
1
C5735
10%
PLACE_NEAR=J5700.12:1.5MM
201
X7R-CERM
25V
100PF
2
1
C5736
PLACE_NEAR=J5700.14:1.5MM
201
100PF
25V
X7R-CERM
10%
4 3
21
L5710
DLP0NS
90-OHM
18 68 71
18 68 71
7
46 71
7
46 71
21
L5720
0402-LF
PLACE_NEAR=J5700.10:1.5MM
FERR-120-OHM-1.5A
21
R5730
0
5%
MF-LF1/16W
402
IPD_3V3:S5
21
R5731
MF-LF
402
1/16W05%
IPD_3V3:S3
7
46 71
7
46 71
38 39
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
WELLSPRING 1
=I2C_TPAD_SCL
USB_TPAD_CONN_P
SMC_LID
PP5V_S5_LDO
USB_TPAD_N
=I2C_TPAD_SDA
=PP3V3_S5_TPAD
=PP3V42_G3H_TPAD
USB_TPAD_P
USB_TPAD_CONN_N
=I2C_TPAD_SDA
SMC_LID
SMC_ONOFF_L
SMC_TPAD_RST_L
=I2C_TPAD_SCL
USB_TPAD_CONN_P
=PP3V3_S3_TPAD
SMC_TPAD_RST_L
PP5V_TPAD_FILT
VOLTAGE=5V
MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm
USB_TPAD_CONN_N
SMC_ONOFF_L
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm
PP3V3_TPAD_CONN
VOLTAGE=3.3V
SMC_PME_S4_L
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8
7 8
7
41 46
7
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7
38 39 46
7
39 46
7
41 46
8
7
7
Page 47
OUT
IN
IN IN
IN
GND
VCC
WP*/ACC
CE*
SI/SIO0
HOLD*
SCLK
SO/SIO1
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Frequency
0
0
1
1
SPI_MOSI
SPI_CLK
0
1
0
1
MCP89 SPI Frequency Select
62.5 MHz
41.7 MHz
25.0 MHz
31.2 MHz
NOTE: 42 & 62 MHz use FAST_READ command.
ROM will ignore SPI cycles.
NOTE: If HOLD* is asserted
2
1
C6100
0.1UF
10%
201
X5R
6.3V
2
1
R6101
3.3K
5%
201
1/20W
MF
40 68
40 68
40 68 40 68
7
19 40
3
8
2
5
6
7
4
1
U6100
32MBIT
MX25L3205DM2I-12G
SOP
CRITICAL
OMIT_TABLE
2
1
R6151
5%
10K
SPI:41MHZ&SPI:62MHZ
201
1/20W
MF
2
1
R6153
5%
10K
SPI:25MHZ&SPI:31MHZ
201
1/20W
MF
2
1
R6152
10K
5%
SPI:25MHZ&SPI:41MHZ
201
1/20W
MF
2
1
R6150
10K
5%
SPI:31MHZ&SPI:62MHZ
201
1/20W
MF
SPI ROM
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
=PP3V3_S5_ROM
SPI_MLB_MOSI
SPI_MLB_CLK
SPI_WP_L
SPI_MLB_MISO
SPI_MLB_CS_L
SPIROM_USE_MLB
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Page 48
IN
IN
IN
IN-
IN+
OUT+
OUT-
GAIN
SHDN*
PVDD
NC
PGND
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
APN:353S2888
80 HZ < FC < 132 HZ
GAIN
SPEAKER LOWPASS
SPEAKER AMPLIFIERS
6DB
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM
21
C6610
0.1UF
CRITICAL
6.3V
10%
201
X5R
7
37 71
2
1
C6607
0.1UF
201
6.3V
10%
X5R
2
1
C6601
CRITICAL
6.3V
20%
2012-LLP
POLY-TANT
47UF
21
R6610
1/20W
5%
201
MF
0
7
37
7
37 71
C2
A1
A2
B1
C1
A3
B3
C3
U6610
MAX98300
WLP
2
1
R6612
NOSTUFF
1/20W
5%
201
MF
100K
21
C6611
CRITICAL
0.1UF
X5R
201
10%
6.3V
2
1
R6611
1/20W
5%
201
MF
100K
2
1
R6613
MF
100K
5%
NOSTUFF
1/20W
201
21
R6614
402
MF-LF
1/16W
0
5%
SYNC_MASTER=AUDIO
SYNC_DATE=02/09/2010
AUDI0: SPEAKER AMP
R_SPKRAMP_SHDN
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
PP5V_S3_U6610
MAX98300_R_N
=PP5V_S3_AUDIO_AMP
SPKRAMP_INR_N
R_AMP_GAIN
SPKRAMP_INR_P
AUD_GPIO_3
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_R_N_OUT
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_R_P_OUT
MAX98300_R_P
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7
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7
49
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NC
SW
BOOST
VIN
BIAS
SHDN*
GND
NC
FB
PAD
THRM
NC
NC
IN
IN
NC
NC
G
D
S
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
NEG
POS
POS
NEG
NEG
SYS_DETECT
SDA
SCL
POS
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER
SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
518-0369
3.425V "G3Hot" Supply
518S0508
Vout = 1.25V * (1 + Ra / Rb)
<Rb>
<Ra>
60MA MAX OUTPUT
Vout = 3.425V
APN:518S0519
HALL EFFECT PADS
SPKR
SIL ON MLB FOR DEVELOPMENT ONLY
S3 AND S0 INDICATOR LEDS FOR DEVELOPMENT ONLY
BATTERY CONNECTOR
Supply needs to guarantee 3.31V delivered to SMC VRef generator
MLB TO LIO POWER CABLE CONNECTOR
998-3029
(Switcher limit)
2
1
C6905
50V
0.01UF
603
20%
CERM
2
1
C6999
6.3V
603-1
X5R
20%
10UF
CRITICAL
OMIT_TABLE
2
1
C6994
X5R
201
6.3V
20%
0.22UF
2
1
R6995
1/20W
348K
201
MF
1%
2
1
C6995
201
22PF
5%
CERM
50V
2
1
R6996
201
MF
1/20W
1%
200K
2
1
C6990
10%
25V
2.2UF
X5R-CERM
603
21
R6905
MF-LF
1/8W
10
5%
805
2
1
C6950
0.1UF
X5R
25V
402
10%
2
1
3
D6950
RCLAMP2402B
SC-75
CRITICAL
NOSTUFF
2
1
R6950
5%
10K
201
1/20W
MF
2
1
C6955
10%
402
CERM
50V
0.001UF
NOSTUFF
21
R6961
5%
0
MF
201
1/20W
6
9
48
5
1
3
2
U6990
DFN
CRITICAL
LT3470A
21
L6995
33UH-20%-0.39A-0.435OHM
CRITICAL
DP418C-SM
6
5
4
3
2
1
J6900
M-RT-SM
WTB-PWR-M82
2
1
C6906
0.01UF
X5R
201
10%
10V
2
1
C6951
X5R
10%
16V
1UF
402
7
48
7
48
3
2
1
D6905
SOT-323
BAT30CWFILM
CRITICAL
8
7
6
5 4
3
2
1
J6955
SM
HALL-SENSOR-MLB-PADS-K99
OMIT_TABLE
2
1
4
3
J6903
78171-0002
M-RT-SM
CRITICAL
K
A
D6920
2.0X1.25MM-SM
S3_S0_LED
GREEN-3.6MCD
K
A
D6910
2.0X1.25MM-SM
GREEN-3.6MCD
S3_S0_LED
4
5
3
Q6940
SOT-363
2N7002DW-X-G
S3_S0_LED
2
1
R6941
402
5%
1/16W
MF-LF
S3_S0_LED
1K
2
1
R6940
1K
5%
1/16W
MF-LF
S3_S0_LED
402
K
A
D6900
SIL
2.0X1.25MM-SM
GREEN-3.6MCD
9
8
7
6
5
4
3
2
1
13
12
11
10
J6950
F-RT-TH
CRITICAL
BAT-K99
SYNC_DATE=11/09/2009
SYNC_MASTER=K84_MLB
DC-In & Battery Connectors
DIDT=TRUE
P3V42G3H_BOOST
=PP3V42_G3H_REG
=PP3V3_S3_DBGLEDS
PPBUS_G3H
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.5 mm
P3V42G3H_SW
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
ITS_ALIVE
CORE_VOLTAGES_ON_R
SYS_LED_ANODE
ALL_SYS_PWRGD
SMC_LID_R
=PP3V42_G3H_HALL
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SMC_LID
=PP5V_S3_LIO_CONN
P3V42G3H_FB
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=18.5V
PPDCIN_G3H_OR_PBUS_R
PPDCIN_G3H_OR_PBUS
=PP18V5_DCIN_CONN
MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V
MIN_NECK_WIDTH=0.20mm
CORE_VOLTAGES_ON
PPVBAT_G3H_CONN
=SMBUS_BATT_SDA
SYS_DETECT_L
=SMBUS_BATT_SCL
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39
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7
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50
7 8
7
50
41
7
41
Page 50
OUT
OUT
IN
BI
OUT
AMON
BMON
ACOK
LGATE
PHASE
BOOT
SGATE
AGATE
CSIP
CSIN
DCIN
VNEG
CSOP
CSON
THRM_PAD
PGND
VDDP
VDD
BGATE
UGATE
ICOMP
VCOMP
ACIN
SDA
VFRQ
CELL
VHST
SCL
SMB_RST_N
IN
S
G
D
G
D
S
IN
G
D
S
G
D
S
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
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SHEET
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
FROM ADAPTER
(CHGR_DCIN)
TO/FROM BATTERY
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE
Reverse-Current Protection
(CHGR_AGATE)
ACIN pin threshold is 3.2V, +/- 50mV
Input impedance of ~40K meets
DIVIDER SETS ACIN THRESHOLD AT 12.18V
(PPVBAT_G3H_CHGR_R)
Q7055.
30mA max load
sparkitecture requirements
(CHGR_CSO_N)
(AGND)
353S2392
(PPVBAT_G3H_CHGR_R)
This node is powered
through body diodes:
* DCIN through Q7080.
Charger TOP FETs and
* PBUS through Q7085,
(CHGR_BGATE)
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
20V/V
(GND)
Float CELL for 1S
(OD)
36V/V
(CHGR_CSO_P)
f = 400 kHz
Inrush Limiter
Max Current = 8A
TO SYSTEM
(CHGR_SGATE)
2
1
R7011
MF
1%
10.5K
1/20W
201
2
1
C7042
10%
X5R
6.3V
0.1UF
201
2
1
C7016
201
X5R-X7R
16V
470PF
10%
2
1
R7016
MF
201
3.01K
1%
1/20W
2
1
C7015
201
X5R-X7R
16V
10%
470PF
2
1
R7015
201
1/20W
MF
5%
220K
2
1
C7002
10V
402
1UF
X5R
10%
2
1
C7000
X5R
402-1
1UF
10%
10V
21
R7001
4.7
5%
402
MF-LF
1/16W
2
1
R7010
201
MF
1/20W
1%
30.1K
21
XW7000
PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm
SM
2
1
C7001
X5R
10%
10V
402
1UF
2
1
C7021
10%
402
X5R
25V
0.1UF
2
1
C7022
X5R
0.1UF
25V
402
10%
2
1
C7020
0.047UF
16V
X7R
10%
402
2
1
C7025
0.22UF
10V
CERM
10%
PLACE_NEAR=U7000.25:2mm
402
321
4
5
Q7035
LFPAK-HF
RJK0305DPB
CRITICAL
21
R7022
MF
1/20W
201
5%
10
21
R7021
MF
201
1/20W
5%
10
2
1
C7030
20%
POLY-TANT
25V
CRITICAL
CASE-D3L
33UF-0.06OHM
2
1
C7031
20%
25V
POLY-TANT
33UF-0.06OHM
CRITICAL
CASE-D3L
F7040
1206-1
7AMP-24V
CRITICAL
21
R7051
201
MF
1/20W
5%
2.2
21
R7052
0
5%
201
MF
1/20W
2
1
R7086
201
MF
1/20W
332K
1%
2
1
R7081
1/20W
62K
201
MF
5%
2
1
C7005
0.22UF
20%
603
X5R
25V
43
43
41
41
2
1
C7011
10%
0.01UF
201
X5R
10V
2
1
C7050
0.47UF
10V
10%
X5R
402
2
1
C7026
10%
1000PF
201
16V
X7R
9
43
21
R7050
0.01
0.5%
1W
MF
0612-3
432
1
R7020
0.020
0.5%
MF-LF
0612
1W
CRITICAL
2
1
C7037
X7R
402
10%
0.001UF
50V
PLACE_NEAR=Q7030.5:1.5mm
2
1
C7045
1000PF
PLACE_NEAR=L7030.2:1.5mm
201
16V
X7R
10%
8
12
4
20
19
7
24
29
13
26
10
11
23
22
21
5
2
18
17
28
27
6
25
15
16
9
1
14
3
U7000
ISL6259HRTZ
TQFN
CRITICAL
OMIT_TABLE
2
1
R7002
MF
1/20W
100K
5%
NO STUFF
201
57
321
4
5
Q7055
PWRPK-1212-8
CRITICAL
SI7615DN
2
1
R7013
201
MF
1/20W
100
1%
3
2
1
D7005
CRITICAL
BAT30CWFILM
SOT-323
2
1
C7085
25V
10%
0.1UF
402
X5R
2
1
R7080
201
MF
1/20W
100K
5%
2
1
R7085
1/20W
1%
MF
201
470K
321
4
5
Q7030
RJK0332DPB-01
LFPAK-SM
CRITICAL
2
1
C7041
CASE-B2
11V
ELEC
CRITICAL
20%
62UF
21
R7005
5%
201
MF
1/20W
20
2
1
C7035
X5R
25V
10%
1UF
603-1
2
1
C7036
X5R
603-1
1UF
10%
25V
21
L7030
4.7UH-9.5A
IHLP4040DZ-SM
CRITICAL
21
R7000
201
MF
1/20W
0
5%
7
38 39 40
5A
5
4
1
Q7080
SI5419DU
CRITICAL
POWERPAK
5A
5
4
1
Q7085
SI5419DU
CRITICAL
POWERPAK
2
1
C7043
CASE-B2
62UF
20%
11V
CRITICAL
ELEC
2
1
C7040
20%
CASE-B2
ELEC
62UF
11V
CRITICAL
2
1
C7014
10%
1UF
603-1
25V
X5R
2
1
C7013
25V
X5R
402
10%
0.1UF
2
1
C7012
10V
X5R
0.01UF
10%
201
2
1
C7017
X5R
10UF
25V
805
10%
PBus Supply & Battery Charger
SYNC_MASTER=K6_MLB
SYNC_DATE=11/09/2009
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=5.1V
PP5V1_CHGR_VDDP
MIN_NECK_WIDTH=0.2 mm
PP5V1_CHGR_VDD
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=5.1V
CHGR_RST_L
=PP3V42_G3H_CHGR
=PPBUS_G3H
CHGR_SGATE_DIV
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm
CHGR_CSI_P
CHGR_CSO_P
DIDT=TRUE
CHGR_BOOT
GND_CHGR_AGND
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=0V
VOLTAGE=8.4V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V
PPDCIN_G3H_CHGR
MIN_NECK_WIDTH=0.4 mm
CHGR_CSI_R_N
CHGR_ACIN
CHGR_ICOMP
CHGR_CSO_N
CHGR_VNEG
CHGR_VCOMP
CHGR_VCOMP_R
=CHGR_ACOK
CHGR_CELL
=SMBUS_CHGR_SCL
CHGR_LGATE
GATE_NODE=TRUE
DIDT=TRUE
CHGR_AMON
CHGR_CSI_R_P
CHGR_VNEG_R
SMC_RESET_L
CHGR_BMON
GND_CHGR_AGND
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_DCIN_D_R
CHGR_CSO_R_N
CHGR_CSO_R_P
CHGR_UGATE
GATE_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=8.4V
MIN_NECK_WIDTH=0.4 mm
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
CHGR_PHASE
DIDT=TRUE
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm
CHGR_AGATE_DIV
MIN_NECK_WIDTH=0.25 mm
PPDCIN_G3H_OR_PBUS
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
PPDCIN_G3H_INRUSH
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V
PPVBAT_G3H_CHGR_R
VOLTAGE=8.4V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 mm
CHGR_BGATE
CHGR_AGATE
=PPDCIN_S5_CHGR
CHGR_SGATE
CHGR_DCIN
CHGR_CSI_N
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70
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70
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Page 51
OUT
IN IN
EN
EN2EN1
DRVL2
SKIPSEL1
SKIPSEL2
DRVL1
V5SW
VBST2VBST1
VREG5
VREF2
VIN
THRM_PAD
SW2SW1
RF
PGOOD2PGOOD1
GND
DRVH2DRVH1
CSP2
CSN2CSN1
COMP2COMP1
VREG3
VFB1 VFB2
OCSEL
MODE
CSP1
OUT
IN
GND/S2
VSW/S1/D2
GHS/G1
GLS/G2
VIN/D1
G
D
S
G
D
S
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
F=400KHZ
Vout = 3.3V
5.3A MAX OUTPUT
353S2678
F=400KHZ
Vout = 5.0V
5.6A MAX OUTPUT
2
1
C7200
1UF
10%
X5R
16V
402
21
L7260
CRITICAL
PCMC063T-SM
2.5UH-14A
2
1
C7241
1UF
X5R
10%
16V
402
2
1
C7264
402
0.1UF
10%
25V
X5R
2
1
C7290
OMIT
10UF
6.3V
603
20%
X5R
2
1
C7224
10%
25V
X5R
402
0.1UF
2
1
C7252
150UF
POLY-TANT
6.3V
20%
CRITICAL
CASE-B2-SM
2
1
C7250
X5R
10UF
805
20%
10V
2
1
C7281
402
16V
1UF
10%
X5R
21
L7220
PCMC063T-SM
2.5UH-14A
CRITICAL
2
1
C7203
OMIT_TABLE
10%
402
CERM
6.3V
1UF
2
1
C7205
OMIT_TABLE
6.3V
10UF
X5R
20%
603
2
1
R7206
1/20W
MF
1%
201
249K
57
2
1
XW7261
SM
PLACE_NEAR=L7260.2:3mm
2
1
C7201
10V
10%
402
CERM
0.22UF
2
1
R7260
1%
201
1/20W
MF
23.2K
2
1
R7261
1%
10K
201
1/20W
MF
2
1
R7220
1/20W
1%
41.2K
MF
201
2
1
R7221
1%
10K
201
MF
1/20W
2
1
C7240
11V
ELEC
CASE-B2
62UF
20%
CRITICAL
21
XW7200
SM
PLACE_NEAR=U7201.28:1mm
2
1
R7216
1%
1/20W
MF
201
3.16K
21
R7246
1/20W
MF
1%
1.87K
201
2
1
XW7260
PLACE_NEAR=L7260.1:3mm
SM
21
C7218
16V
10%
X5R
402
0.1UF
21
R7247
1/20W
MF
1%
1.87K
201
2
1
R7256
MF
1/20W
3.16K
1%
201
2
1
XW7220
SM
PLACE_NEAR=L7220.1:3mm
2
1
XW7221
SM
PLACE_NEAR=L7220.2:3mm
2
1
R7236
1%
6.04K
MF
201
1/20W
2
1
R7237
201
20K
1/20W
MF
1%
NO STUFF
2
1
XW7262
SM
PLACE_NEAR=L7260.2:3mm
2
1
XW7222
SM
PLACE_NEAR=L7220.1:3mm
2
1
C7292
CASE-B2-SM
TANT
6.3V
20%
150UF-0.018OHM-1.8A
CRITICAL
2
1
R7239
MF
1/20W
201
NO STUFF
1%
20K
2
1
C7239
10%
100PF
X7R-CERM
25V
201
2
1
R7238
1%
MF
201
6.04K
1/20W
2
1
C7238
X5R
10%
201
0.01UF
10V
57 57
21
R7248
5%0201MF1/20W
NO STUFF
2
1
R7249
0
201
1/20W
MF
5%
2
1
C7272
X7R
10%
16V
201
1000PF
PLACE_NEAR=L7260.2:1.5mm
2
1
C7283
16V
PLACE_NEAR=Q7260.2:1.5mm
X7R
10%
1000PF
201
2
1
C7270
PLACE_NEAR=Q7220.5.2:1.5mm
1000PF
201
10%
X7R
16V
2
1
C7271
10%
X7R
16V
201
1000PF
PLACE_NEAR=L7220.1.2:1.5mm
29
22
13
23
16
9
26
31
2
33
25
32
19
6
3
20
5
14
11
28
21
4
12
27
30
24
1
18
7
17
8
15
10
U7201
QFN
CRITICAL
TPS51980
2
1
C7282
ELEC
CRITICAL
CASE-B2
11V
20%
62UF
2
1
R7245
0
5%
MF-LF
402
1/16W
2
1
R7251
PLACE_NEAR=U7201.4:2mm
402
MF-LF
1/16W
0
5%
2
1
R7252
5%
0
1/16W
MF-LF
402
PLACE_NEAR=U7201.21:2mm
57
57
8
7
3
2
5
4
6
1
Q7260
CRITICAL
SIZ700DT
POWERPAIR-6X3.7
2
1
C7236
10%
X5R
10V
0.01UF
201
2
1
C7237
10%
100PF
X7R-CERM
25V
201
21
C7288
402
X5R
10%
16V
0.1UF
1
2
R7264
402
1/16W
5%
0
MF-LF
3 2 1
4
5
Q7225
RJK03E0DNS
HWSON-8
CRITICAL
3 2 1
4
5
Q7220
HWSON-8
CRITICAL
RJK03E0DNS
SYNC_MASTER=K16_MLB
5V / 3.3V Power Supply
SYNC_DATE=07/07/2010
P5VS3_VFB1
=PP5V_S3_REG
P5VS3_VFB1-R
DIDT=TRUE
SWITCH_NODE=TRUE
P5VS3_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
=PPVIN_S5_P5VP3V3
P3V3S5_CSN2
P3V3S5_COMP2
P5VS3_EN_R
P5VS3_COMP1
P5VS3_CSN1
P5VS3_DRVH
GATE_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
P5VS3_VBST_R
MIN_LINE_WIDTH=0.6 mm
P5VP3V3_VREF2P5VP3V3_VREF2
P5VS3_PGOOD
P5VS3_CSP1
P5VS3_VBST
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
P5VP3V3_VREG3
P3V3S5_PGOOD
P3V3S5_VBST_R
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
=PP5V_S3_REG
=PP3V3_S5_REG
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
P3V3S5_LL
MIN_LINE_WIDTH=0.6 mm
P5VP3V3_VREF2
P3V3S5_VFB2_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
P3V3S5_VBST
=P5V3V3_REG_EN
P3V3S5_RF
P5VS3_FUNC
P3V3S5_COMP2_R
=P3V3S5_EN
=P5VS3_EN
P5VS3_COMP1_R
P5VP3V3_VREG3
DIDT=TRUE
GATE_NODE=TRUE
P3V3S5_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
P3V3S5_CSP2_R
P5VS3_CSP1_R
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
P5VS3_DRVL
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
P3V3S5_CSP2
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
P3V3S5_DRVL
DIDT=TRUE
P5VP3V3_VREG5
P3V3S5_EN_R
P3V3S5_VFB2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
GND_P5VP3V3_SGND
051-8379
4.4.0
72 OF 110
51 OF 73
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51
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Page 52
MODE
VDDQSNS
COMP
NC0
NC1
VTTSNS
VTT
VTTREF
PGOOD
S3
S5
VTTGND
THRM_PAD
GND
CS_GND
PGND
CS
LL
DRVL
DRVH
VDDQSET
VBST
VLDOINV5FILT
V5IN
SYM (2 OF 2)
IN
IN
OUT
NC
NC
G
D
S
OUT
OUT
G
D
S
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
(DDRREG_DRVL)
(DDRREG_LL)
(DDRREG_VBST)
f = 400 kHz
13A Max Output
Vout = 1.501V / 1.352V
Vout = 0.75V * (1 + Ra / Rb)
(DDRREG_DRVH)
(DDRREG_CSGND)
VDDQ PGOOD
VDDQ/VTTREF Enable
VTT Enable
Vout = VTTREF
Vout = VDDQSNS/2
10mA max load
(DDRREG_VDDQSNS)
(DDRREG_FB)
(GND_DDRREG_SGND)
<Ra>
<Rb>
Use LVDDR3:YES for fixed 1.35V operation or LVDDR3:NO for fixed 1.5V operation.
21
C7325
402
0.1UF
16V
10%
X5R
2
1
R7320
MF
1/20W
1%
15K
201
2
1
R7321
LVDDR3:YES
201
MF
1/20W
18.7K
1%
2
1
C7332
10%
1UF
16V
402
X5R
2
5
1
24
23
8
9
22
15
14
25
11
10
13
18
12
7
4
20
3
19
21
17
16
6
U7300
QFN
CRITICAL
TPS51116
21
R7305
4.7
1/16W
MF-LF
5%
402
2
1
C7361
6.3V
X5R-CERM-1
603
22UF
20%
OMIT_TABLE
2
1
C7360
6.3V
X5R-CERM-1
603
22UF
20%
OMIT_TABLE
21
XW7360
SM
PLACE_NEAR=C7360.1:1 mm
21
XW7335
SM
PLACE_NEAR=Q7335.1:1 mm
2
1
C7350
33000PF
201
X5R
10%
6.3V
57
2
1
C7300
4.7UF
10V
X5R
10%
805
57
2
1
R7310
201
1/20W
MF
1%
12K
21
L7330
IHLP2525CZ-SM
0.82UH-20%-13A-0.0067OHM
CRITICAL
2
1
XW7345
SM
PLACE_NEAR=L7330.2:1 MM
2
1
C7355
10UF
X5R
6.3V
603
20%
OMIT_TABLE
2
1
C7341
CASE-B2-SM
330UF
TANT
2.5V
CRITICAL
20%
2
1
C7340
CASE-B2-SM
CRITICAL
330UF
TANT
2.5V
20%
2
1
C7345
10UF
X5R
OMIT_TABLE
6.3V
603
20%
2
1
C7333
201
16V
1000PF
10%
X7R
PLACE_NEAR=Q7330.1:1.5mm
2
1
C7305
10%
402-1
X5R
10V
1UF
21
XW7300
PLACE_NEAR=U7300.3:1 mm
PLACE_NEAR=U7300.25:1 mm
SM
321
4
5
Q7335
CRITICAL
PWRPK-12128
SIS426DN
2
1
C7320
10%
X7R
16V
201
1000PF
LVDDR3:YES
2
1
R7380
100K
5%
201
MF
1/20W
42 71
42 71
2
1
C7331
CRITICAL
62UF
11V
ELEC
CASE-B2
20%
2
1
C7330
CASE-B2
62UF
11V
ELEC
CRITICAL
20%
2
1
C7346
PLACE_NEAR=R7350.1:1.5MM
16V
10%
X7R
201
1000PF
321
4
5
Q7330
SIS426DN
PWRPK-12128
CRITICAL
341
2
R7350
1%
1/4W
MF-LF
1206
CRITICAL
0.002
LVDDR3:NO
R73211114S0331
RES,15K,1%,1/16W,MF-LF,0402
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
1.5V/1.35V LVDDR3 Supply
DDRREG_FB
=PPVIN_S0_DDRREG_LDO
PPDDR_S3_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
ISNS_1V5_S3_P
=DDRREG_EN
=DDRVTT_EN
DDRREG_VTTSNS
DDRREG_VBST
DIDT=TRUE
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DDRREG_CS
DDRREG_CSGND
MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm
=PP5V_S3_DDRREG
VOLTAGE=5V
PP5V_S3_DDRREG_V5FILT
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DDRREG_LL
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.17 mm
DIDT=TRUE
GATE_NODE=TRUE
DDRREG_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
=PPVIN_S3_DDRREG
DDRREG_VDDQSNS
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.2 mm
=PPDDR_S3_REG
ISNS_1V5_S3_N
=PPVTT_S3_DDR_BUF
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.17 mm
DDRREG_DRVL
MIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V
MIN_NECK_WIDTH=0.17 mm
GND_DDRREG_SGND
DDRREG_PGOOD
=PP3V3_S3_PDCISENS
=PPVTT_S0_DDR_LDO
73 OF 110
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051-8379
52 OF 73
33
8
8
8
8
8
33
8
8
Page 53
S
G
D
D
G
S
NC
NC
NCNC
OUT
NC
OUT
IN
NC
V5FILT
OSRSEL
ISLEW
VID6
DROOP
TRIPSEL
VR_TT*
THERM
GNDSNS
VREF
VID0
VID1
VID2
VID3
VID4
VID5
CSP
CSN
LL
VR_ON
GND
PGND
DPRSLPVR
DRVL
PGOOD
DRVH
VBST
PWRMON
DPRSTP*
CLK_EN*
VSNS
V5IN
TONSEL
IN
IN
IN
IN
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MIN_LINE_WIDTH
MIN_NECK_WIDTH
MIN_NECK_WIDTH
MAX CURRENT = 18A
MIN_LINE_WIDTH
IMVP6 CPU VCORE REGULATOR
PWM FREQ. = 400KHZ
(CPUIMVP_LL)
OCP = 21.5MV / R7480 + 3.1A
18A @ 1V = 1.62V
VPMON = 90 X R7480 X VO X IO
LOAD LINE = R7480 X 6 / (500U X R7414)
21
L7400
PCMC104T-SM
CRITICAL
0.36UH-30A-1.05MOHM
2
1
C7453
X5R
10%
1UF
16V
402
2
1
C7458
CRITICAL
11V
62UF
20%
ELEC
CASE-B2
2
1
C7459
62UF
20%
11V
CRITICAL
ELEC
CASE-B2
2
1
C7457
1UF
402
16V
10%
X5R
3
4 6
5
2
1
Q7400
S1
IRF6710
CRITICAL
43
5
7621
Q7451
DIRECTFET-MX
IRF6795
CRITICAL
4 3
2 1
R7480
MF-1
1%
0612
1W
CRITICAL
0.001
2
1
C7454
PLACE_NEAR=Q7400.1:1.5mm
X7R
10%
16V
201
1000PF
2
1
C7455
PLACE_NEAR=R7480.1:1.5MM
16V
10%
X7R
1000PF
201
21
R7491
0
MF
5%
201
1/20W
21
R7492
201
0
5%
MF
1/20W
2
1
C7414
1UF
10%
16V
X5R-X7R
603-2
21
R7451
201
1/20W
MF5%
470
21
R7452
470
5% MF
1/20W
201
2
1
C7451
201
10%
X7R-CERM
25V
100PF
2
1
R7415
0
5%
MF-LF
1/16W
402
25
43
38
2
1
C7452
201
10%
X7R-CERM
25V
100PF
2
1
C7412
X5R-CERM
4.7UF
603
10%
6.3V
2
1
C7413
603
CERM1
6.3V
20%
2.2UF
6
1
8
25
10
11
12
13
14
15
16
18
21
31
27
28
7
26
22
33
29
19
30
5
2
20
17
32
9
23
4
3
24
U7400
QFN
TPS51982RHB
CRITICAL
2
1
C7415
5%
100PF
25V
CERM
201
11 12 65
11 12 65
2
1
R7414
MF
201
1/20W
1%
3.01K
2
1
R7411
5%
0
MF
1/20W
201
2
1
R7410
MF
1/20W
5%
0
201
11 12 65
11 12 65
11 12 65
11 12 65
11 12 65
21
XW7400
SM
2
1
R7426
150K
5%
MF
1/20W
201
2
1
R7425
1%
1/20W
124K
MF
201
2
1
R7421
NO STUFF
5%
201
1/20W
MF
10K
2
1
R7420
5%
MF
0
1/20W
201
2
1
C7456
11V
62UF
20%
CASE-B2
ELEC
CRITICAL
I787
2
1
R7422
201
2.0K
1/20W
MF
5%
21
R7453
1/20W1%MF
201
499
14 65
2
1
C7450
NO STUFF
100PF
5%
50V
402
CERM
2
1
C7460
10V
CERM
10%
402
0.22UF
IMVP6 CPU VCore Regulator
SYNC_MASTER=POWER
SYNC_DATE=07/13/2005
0.20 MM0.25 MM
PP1V7_S0_IMVP6_VREF
IMVP6_CS_R_N
IMVP6_VSEN_P
IMVP6_VSEN_N
IMVP6_CS_R_P
IMVP6_CS_P
VR_PWRGOOD_DELAY
CPU_VID<2>
=PPVCORE_S0_CPU_REG
=PPVIN_S5_CPU_IMVP
IMVP6_TONSEL
=PP3V3_S0_IMVP
CPU_VID<5>
PM_DPRSLPVR
GATE_NODE=TRUE
IMVP6_DRVL
DIDT=TRUE
IMVP6_ISLEW
IMVP6_THERM
IMVP6_DROOP
DIDT=TRUE
IMVP6_VBST
DIDT=TRUE
IMVP6_DRVH
GATE_NODE=TRUE
IMVP6_VBST_RC
DIDT=TRUE
IMVP6_PMON
IMVP6_DPRSLPVR
CPU_VID<0>
CPU_VID<1>
IMVP_VR_ON
CPU_VCCSENSE_P
1.5 MM
0.20 MM
IMVP6_VBST_RC
1.5 MM
0.20 MM
IMVP6_DRVH
1.5 MM
0.20 MM
IMVP6_LL
0.20 MM
PP5V_S0_IMVP6_V5FILT
0.25 MM
0.25 MM 0.20 MM
IMVP6_VBST
1.5 MM
0.20 MM
IMVP6_DRVL
CPU_VCCSENSE_N
0.25 MM 0.20 MM
IMVP6_THERM
GND_IMVP6_SGND
0.20 MM0.50 MM
CPU_VID<4>
CPU_VID<6>
CPU_VID<3>
=PP5V_S0_CPU_IMVP
PP5V_S0_IMVP6_V5FILT
VOLTAGE=5V
DIDT=TRUE
SWITCH_NODE=TRUE
IMVP6_LL
PPVCORE_S0_CPU_REG_R
VOLTAGE=1.25V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.7V
PP1V7_S0_IMVP6_VREF
CPU_DPRSTP_L
VOLTAGE=0V
GND_IMVP6_SGND
IMVP6_OSRSEL
IMVP6_TRIPSEL
IMVP6_CS_N
0.20 MM0.25 MM
IMVP6_ISLEW
0.25 MM 0.20 MM
IMVP6_DROOP
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Page 54
IN
IN
IN
OUT
OUT
IN
IN
NC
IN
IN
NC
ISP
OCSET
ISN
ICOMP
LGATE
COMP
VDIFF
AF_EN
IMON
VID3
VID2
VDD
BOOT
FB
FDE
PGND
PGOOD PHASE
PVCC
RTN
THRM_PAD
VID0
VID1
VO
VSEN
VSS
VW
UGATE
VIN
RBIAS
SOFT
VR_ON
G
D
S
G
D
S
G
D
S
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(MCPCORES0_FB)
(MCPCORES0_COMP)
(MCPCORES0_VO)
(MCPCORES0_ISN)
(MCPCORES0_ICOMP)
Vimon = 31 * Io * R7525 * (1 + R7575/R7573)
(MCPCORES0_UGATE)
OCP = R7569 X 10UA / ( R7525 X (1 + R7575 / R7573) )
0100 0.8750V
0011 0.8875V
0010 0.9000V
1101 0.9625V
1110 0.9500V
0000 0.9250V
0101 0.8625V
0110 0.8500V
0111 0.8375V
1000 0.8250V
1001 0.8125V
1010 0.8000V
1011 0.7875V
(MCPCORES0_VW)
VID<3:0> VOLTAGE
K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27
0001 0.9125V
1111 0.9375V
1100 0.9750V
(MCPCORES0_VDIFF)
(MCPCORES0_VSEN)
(MCPCORES0_RTN)
f = 300 kHz
(Q7560 Limit)
MAX CURRENT: 15A
(MCPCORES0_PHASE)
19
19
21
R7568
201
1/20W
MF
20
1%
21
R7566
201
1/20W
MF
1%
20
2
1
C7570
1000PF
16V
10%
X7R
201
2
1
R7563
201
1/20W
MF
1%
100
2
1
C7576
0.1UF
402
16V
X7R-CERM
10%
2
1
R7572
201
1%
1/20W
MF
147K
57
57
2
1
R7561
201
1K
1/20W
MF
5%
21
XW7561
PLACE_NEAR=U7500.33:1mm
SM
2
1
R7575
201
MF
1/20W
1%
22.1K
2
1
R7573
201
1/20W
1%
MF
10K
21
R7569
201
1/20W
MF
1%
9.76K
1
2
R7565
MF-LF
603
0
5%
1/10W
2
1
C7564
603
5%
10V
0.22UF
CERM-X7R
2
1
C7550
16V
402
X5R
1UF
10%
21
R7560
CRITICAL
1/10W
5%
603
MF-LF
2.2
2
1
C7562
X5R
402
16V
10%
1UF
21
R7578
201
1/20W
MF
1%
200
21
R7579
MF
201
3.01K
1/20W
1%
21
R7577
201
1%
1/20W
MF
150K
21
C7580
402
CERM
560PF
10%
50V
21
C7581
100PF
CERM
402
50V
5%
2
1
R7571
1%
100
1/20W
MF
201
21
C7582
4700PF
CERM
402
10%
100V
2
1
C7579
402
10%
50V
X7R
0.001UF
2
1
R7576
201
MF
1%
6.98K
1/20W
2
1
C7566
10UF
4V
603
20%
X5R
2
1
C7568
20%
270UF
2V
CASE-B4-SM
CRITICAL
TANT
2
1
C7565
270UF
CRITICAL
CASE-B4-SM
TANT
2V
20%
2
1
C7567
603
4V
10UF
X5R
20%
2
1
C7561
X5R
10%
1UF
16V
402
2
1
C7563
201
16V
1000PF
PLACE_NEAR=Q7560.5:1.5mm
X7R
10%
21
R7500
MF-LF
1%
1/16W
402
100
2
1
C7573
201
NP0-C0G
25V
5%
47PF
2
1
C7575
201
NP0-C0G
25V
5%
47PF
43
21
R7525
0.001
1%
1W
0612
MF-1
CRITICAL
21
L7560
CRITICAL
0.47UH-20%-0.0021OHM-26A
PCMB103T-SM
2
1
C7540
CRITICAL
CASE-B2
11V
ELEC
62UF
20%
43
2
1
C7541
CASE-B2
11V
ELEC
62UF
20%
CRITICAL
22 71
22 71
21
R7593
0
5% MF
1/20W
201
NOSTUFF
21
R7590
0
5% MF
1/20W
201
21
R7591
5%
0
MF
1/20W
201
2
1
C7578
10%
X7R
16V
201
1000PF
2
1
C7577
10%
16V
X7R
201
1000PF
21
R7592
MF
1/20W
5%
201
0
21
R7594
0
MF
1/20W
5%
201
19
19
4
15
8
29
12
14
27
26
25
24
7
16
18
33
2
9
1
22
1931
20
3
21
13
11
28
10
32
6
5
17
30
U7500
CRITICAL
ISL9563B
QFN
321
4
5
Q7560
SIS426DN
PWRPK-12128
CRITICAL
321
4
5
Q7565
SIS426DN
PWRPK-12128
CRITICAL
2
1
C7569
201
16V
1000PF
X7R
10%
PLACE_NEAR=R7525.1:1.5MM
321
4
5
Q7566
PWRPK-12128
SIS426DN
CRITICAL
SYNC_DATE=12/11/2009
SYNC_MASTER=K6_MLB
MCP VCore Regulator
MIN_NECK_WIDTH=0.2 MM
PP5V_S0_MCPREG_VDD
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
MCPCORES0_LGATE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
GATE_NODE=TRUE
MCPCORES0_IMON_R
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
MCPCORES0_PHASE
DIDT=TRUE
SWITCH_NODE=TRUE
MCPCORES0_UGATE
MIN_LINE_WIDTH=0.5 MM
GATE_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
PPMCPCORE_S0_R
MCPCORES0_VO
MCPCORES0_RTN
MCPCORES0_FDE
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
GND_MCPCORES0_AGND
MCP_VID2_REG
MCP_VID0_REG
MCPCORES0_PGOOD
=PPMCPCORE_S0_REG
MCPCORES0_VW
=MCPCORES0_EN
MCP_VID<0>
MCPCORES0_VSEN_P
MCP_VID<2>
MCP_VID<1>
MCPCORES0_IMON
MCPCORES0_VSEN_N
MCPCORES0_VDIF_C
=PPMCPCORE_S0_REG
MCP_VID<3>
MIN_LINE_WIDTH=0.25 MM
DIDT=TRUE
MCPCORES0_BOOT_R
MIN_NECK_WIDTH=0.2 MM
=PP5V_S0_MCPREG
=PPVIN_S0_MCPCORE
MCPCORES0_ISN
MCPCORES0_OCSET
MCPCORES0_ICOMP
MCPCORES0_ISP
MCPCORES0_ISP_R
MCPCORES0_RBIAS
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MCPCORES0_BOOT
MCPCORES0_VSEN
MCPCORES0_SOFT
MCP_VID3_REG
MCP_VID1_REG
MCPCORES0_VDIFF
MCPCORES0_FB
MCPCORES0_COMP_C
MCPCORES0_COMP
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IN
BOOT
UGATE
LGATE
PHASE
RTN
FSEL
PGOOD
OCSET
VO
SREF
VCC
PVCC
GND
PGND
EN
FB
OUT
G
D
S
G
D
S
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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8 7 5 4 2 1
(CPUVTTS0_OCSET)
Place XW7610, XW7611
<Rb>
<Ra>
(CPUVTTS0_VO)
remote sensing.
at desired location for
f = 300 kHz
Vout = 1.05V
11.5A Max Output
Vout = 0.5V * (1 + Ra / Rb)
OCP = R7641 x 8.5uA / R7640
57
34
12
R7640
CRITICAL
0.001
MF-1
0612
1W
1%
2
1
C7630
402
1UF
X5R
10%
16V
2
1
C7620
20%
11V
ELEC
62UF
CASE-B2
CRITICAL
2
1
C7621
CASE-B2
62UF
ELEC
11V
20%
CRITICAL
2
1
C7622
PLACE_NEAR=Q7630.1:1.5mm
X7R
10%
1000PF
16V
201
2
1
C7647
OMIT_TABLE
X5R
6.3V
10UF
603
20%
2
1
C7601
10UF
20%
X5R
10V
603
2
1
R7601
1/10W
5%
MF-LF
603
2.2
21
XW7600
SM
2
1
C7603
X7R
10%
16V
0.047UF
402
2
1
R7641
1.78K
1%
1/20W
MF
201
2 1
C7640
25V
5%
402
1000PF
NP0-C0G
2
1
R7642
201
MF
1/20W
1%
1.78K
1
2
R7644
201
MF
1/20W
1%
3.01K
2
1
R7645
2.74K
1%
1/20W
MF
201
8
13
11
4
2
14
10
9
16
7
15
1
5
6
3
12
U7600
ISL95870
UTQFN
CRITICAL
21
L7630
CRITICAL
0.82UH-20%-13A-0.0067OHM
IHLP2525CZ-SM
2
1
C7602
X5R
603
2.2UF
16V
10%
2
1
R7603
201
MF
1/20W
5%
0
57
2
1
C7605
201
16V
1000PF
10%
X7R
2
1
C7604
201
10%
X7R
16V
1000PF
2
1
R7604
3.01K
1%
1/20W
MF
201
2
1
R7605
201
2.74K
1/20W
MF
1%
2
1
C7648
CRITICAL
270UF
CASE-B4-SM
TANT
2V
20%
2
1
C7649
CRITICAL
270UF
CASE-B4-SM
TANT
2V
20%
2
1
C7623
1000PF
201
16V
X7R
10%
PLACE_NEAR=L7630.2:1.5mm
21
XW7611
SM
21
XW7610
SM
321
4
5
Q7630
CRITICAL
RJK03E0DNS
HWSON-8
321
4
5
Q7635
HWSON-8
RJK03E0DNS
CRITICAL
CPUVTT (1.05V) Power Supply
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
CPUVTTS0_CS_P
CPUVTTS0_OCSET
=PPCPUVTT_S0_REG
CPUVTTS0_LL
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
PPCPUVTT_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
CPUVTTS0_CS_N
CPUVTTS0_VO
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
DIDT=TRUE
CPUVTTS0_VBST
=PPVIN_S0_CPUVTTS0
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
CPUVTTS0_DRVH
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
CPUVTTS0_DRVL
=PPCPUVTT_S0_REG
CPU_VTTSENSE_P
CPU_VTTSENSE_N
CPUVTTS0_FB
CPUVTTS0_PGOOD
=PP5V_S0_CPUVTTS0
CPUVTTS0_RTN
CPUVTTS0_FSEL
=CPUVTTS0_EN
CPUVTTS0_AGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
CPUVTTS0_SREF
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
PP5V_S0_CPUVTTS0_VCC
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IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GND
THRM_PAD
SS
IN0
IN1
THRML_PAD
EN FB
BIAS
OUT0
OUT1
GND
PG
OUT
OUT
IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GND
THRM_PAD
OUT
GND
EN
OUT
IN
NC
NC
IN
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.
MAX CURRENT = 1.5A
<Rb>
<Ra>
<Ra>
Vout = 1.05V
Vout = 0.8V * (1 + Ra / Rb)
<Ra>
<Rb>
TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.
f = 1.6MHZ
f = 1.6MHZ
Vout = 1.508V
TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.
MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER.
BOMOPTIONs:
<Rb>
1.5V S0 Regulator
Max Current = 0.5A
1.05V S0 MCP PLL LDO
MAX CURRENT = 0.016A
Vout = 0.8V * (1 + Ra / Rb)
MAX CURRENT = 1.5A
Vout = 0.902V
Vout = 0.8V * (1 + Ra / Rb)
Vout = 5.0V
MCP 0.9V S5 (AUXC) Switcher
5.0V S5 IPD LDO
2
1
C7750
PLACE_NEAR=U7750.1:1.5mm
CRITICAL
22UF
CERM
6.3V
805
20%
2
1
R7751
1/20W
2.55K
1%
MF
201
2
1
R7752
MF
1/20W
1%
20K
201
2
1
C7751
201
25V
NP0-C0G
47PF
5%
21
L7750
CRITICAL
2.2UH-3.25A
IHLP1616BZ-SM
57
1
6
9
4 5
3
8
7
2
U7750
DFN
CRITICAL
ISL8009B
2
1
C7743
201
10V
X5R
2.2NF
10%
MCPPLL_LDO
11
7 3
10
9
2
1
6
85
4
U7740
CRITICAL
TPS74701
SON
MCPPLL_LDO
2
1
R7747
201
MF
MCPPLL_LDO
4.42K
1%
1/20W
2
1
C7741
1UF
6.3V
402
CERM
10%
MCPPLL_LDO
2
1
R7743
MCPPLL_R:LDO
100
402
MF-LF
5%
1/16W
2
1
C7740
MCPPLL_LDO
1UF
402
CERM
6.3V
10%
2
1
R7746
201
MF
1/20W
MCPPLL_LDO
1%
1.37K
2
1
C7742
20%
4V
X5R
402
MCPPLL_LDO
4.7UF
21
R7744
1/16W
0
402
5%
MCPPLL_R:LDO
MF-LF
21
R7745
MCPPLL_R:REG
402
5%
MF-LF
1/16W
0
21
R7748
201
MF
1/20W
5%
0
MCPPLL_LDO
57
57
57
1
6
9
4 5
3
8
7
2
U7710
CRITICAL
ISL8009B
DFN
2
1
C7710
805
6.3V
CERM
20%
22UF
PLACE_NEAR=U7710.1:1.5mm
2
1
R7712
201
113K
1%
1/20W
MF
2
1
C7711
5%
47PF
201
25V
NP0-C0G
2
1
R7711
1%
100K
MF
201
1/20W
2
1
C7715
805
CERM
6.3V
20%
22UF
21
L7710
IHLP1616BZ-SM
CRITICAL
2.2UH-3.25A
57
2
1
R7750
402
1/16W
MCPPLL_R:LDO
5%
MF-LF
0
2
1
C7755
20%
22UF
CRITICAL
CERM
6.3V
805
2
1
C7712
PLACE_NEAR=U7710.1:1.5mm
X7R
201
16V
10%
1000PF
2
1
C7716
201
X7R
10%
1000PF
16V
PLACE_NEAR=L7710.2:1.5mm
2
1
C7752
PLACE_NEAR=U7750.1:1.5mm
1000PF
X7R
16V
10%
201
2
1
C7756
1000PF
16V
10%
X7R
PLACE_NEAR=L7750.2:1.5mm
201
51
2
3
U7760
SOT23-5
MIC5235-2.5V
OMIT_TABLE
2
1
C7761
IPD_5V:S5_EXT
X5R
402
16V
10%
1UF
2
1
C7760
402
X5R-CERM
IPD_5V:S5_EXT
2.2UF
20%
10V
57
21
R7760
IPD_5V:S3
1/16W
0
MF-LF
5%
402
21
R7761
5%
MF-LF
1/16W
0
PLACE_NEAR=J5700.10:1.5mm
IPD_5V:S5_INT
402
IPD_5V:S5_EXT
IC,LDO,MIC5235,5V,1%,150MA,SOT23-5
U7760
353S3034 1
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
Misc Power Supplies
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=5V
PP5V_S5_LDO
P5VP3V3_VREG5
=PP3V3_S5_P0V9S5
P0V9S5_PGOOD
=PP3V3_S0_P1V5S0
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
PP3V3_S0_MCP_PLL_LDO_BIAS
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
PP1V5_S0_MCPPLLLDO
=PP5V_S3_TPAD
P5V_S5_EN
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_REG
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
P1V5S0_EN
=PP1V5_S0_MCP_PLL_VLDO
=PP1V5_S0_REG
=PP0V9_S5_REG
=P0V9S5_EN
P1V5S0_PGOOD
P1V5S0_FB
MCPPLLLDO_SS
=PP1V05_S0_MCP_PLL_UF_R
=PP1V05_S0_MCP_PLL_OR
MCPPLLLDO_PGOOD
MCPPLLLDO_PGOOD_R
MCPPLLLDO_FB
=PP3V3_S0_MCP_PLL_VLDO
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
P1V5S0_SW
DIDT=TRUE
MIN_LINE_WIDTH=0.4 mm
P0V9S5_FB
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
DIDT=TRUE
P0V9S5_SW
SWITCH_NODE=TRUE
=PPBUS_5V_S5
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OUT
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
D
SG
D
S G
D
SG
OUT
NC
IN
OUT
D
G S
OUT
VDD
OUT_A*
OUT_A
THRM
GND
IN_A
DLY_1C
IN_B
OUT_B
DLY
(OD,IPU)
(OD,IPU)
(OD,IPU)
(IPD)
1.3V
PAD
2:1
-
+
OUT
IN
OUT
IN
OUT
IN
THRM_PAD
GND
V3MON
V4MON
RST*
MR*
VDD
VDDA
V2MON
Q3
Q2
Q4
Q1
NC
NC
IN
OUT
OUT
IN
OUT
OUT
D
SG
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
NOTE: "AC" term valid only when Q7891 is stuffed
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
3.3V w/Divider: 2.345V
Internal pull-ups 100K +/- 20%
S5 Rail Enables & PGOOD
Pull-up is with power FET.
DLY > 10 ms
Threshold: ??
353S2809
S0 Rail PGOOD (ISL Version)
S0 Rail PGOOD Circuitry
Q4: 0.660V
S0 Rail PGOOD (BJT Version)
V4MON: 0.610V
V3MON: 0.610V
U7750 EN tied to VIN
Q2: 0.XXXV
Worst-Case Thresholds:
Q3: 0.640V
Power Control Signals
353S2718
(IPU)
V2MON: 3.000V
VDD: 2.9140V
Worst-Case Thresholds:
ISL6259 Frequency Select
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
1
1
0
1
Run (S0)
State
SMC_PM_G2_ENABLE
0
0
0
1
0
0
11
PM_SLP_S4_L PM_SLP_S3_L
the same time as MEMVDD rail (Q2300).
VTT rail must ramp up in about
VTT Rail Enable
S0 Rail Enables
Need to re-characterize for power sequencing!
ENET Rail Enables
S3 Rail Enables
Need to re-characterize for power sequencing!
51
25 38 49
12
R7813
1/20W
0
201
5%
MF
2
1
C7813
NO STUFF
10V
0.068UF
10%
CERM
402
21
R7812
0
MF
201
1/20W
5%
2
1
C7812
NO STUFF
0.47UF
10V
X5R
402
10%
51
7
36 37
2 1
R7859
201
1/20W
MF
5%
100
58
1
2
R7884
5.1K
5%
1/20W
201
MF
2
1
C7884
0.47UF
10%
402
X5R
10V
58
56
7
19 38 39 57
19 38 39
19 34
4
5
3
Q7890
SSM6N37FEAPE
SOT563
1
2
6
Q7891
SOT563
SSM6N37FEAPE
WLAN_PCTL:HW
1
2
6
Q7890
SSM6N37FEAPE
SOT563
34
2
1
C7870
402
CERM
10V
20%
0.1uF
S0PGOOD_ISL
2
1
R7871
S0PGOOD_ISL
20.0K
1/16W
1%
MF-LF
402
2
1
R7870
10K
1/16W
402
1%
MF-LF
S0PGOOD_ISL
56
52
21
R7864
VFRQ:SLPS4
5%
0
201
MF
1/20W
21
R7863
MF
5%
0
201
VFRQ:SLPS3
1/20W
2
1
3
Q7860
VFRQ:SLPS4&VFRQ:SLPS3
SSM3K15FV
SOD-VESM-HF
2
1
R7861
MF
10K
201
1/20W
VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH
5%
2
1
R7860
5%
VFRQ:LOW
201
10K
1/20W
MF
50
1
9
8
4
3
6
2
5
7
U7840
SLG4AP012
TDFN
CRITICAL
2
1
C7841
220PF
25V
201
10%
X7R-CERM
2
1
C7840
6.3V
X5R
201
0.1UF
10%
38 56
51
2
1
C7801
10%
NO STUFF
33000PF
6.3V
X5R
201
7
38
51
19 21
7
2
6
5
3
9
8
1
4
U7870
S0PGOOD_ISL
TDFN
CRITICAL
ISL88042IRTJJZ
3
2
8
4
6
1
7
5
Q7820
DFN2015H4-8
ASMCC0179
S0PGOOD_BJT
CRITICAL
2
1
R7821
S0PGOOD_BJT
201
15K
1/20W
MF
1%
2
1
R7822
S0PGOOD_BJT
1%
MF
1/20W
201
7.15K
21
R7823
201
5%
1/20W
MF
1K
S0PGOOD_BJT
21
R7824
S0PGOOD_BJT
201
1K
1/20W
MF
5%
21
R7825
1/20W
S0PGOOD_BJT
201
MF
5%
1K
2
1
R7827
S0PGOOD_BJT
100
201
1/20W
MF
5%
21
R7828
S0PGOOD_BJT
201
1/20W
MF
5%
10
21
R7872
S0PGOOD_ISL
10
5%
1/20W
MF
201
2
1
R7826
201
MF
1/20W
1%
S0PGOOD_BJT
150K
19
58
58
51
58
21
R7840
201
0
5%
MF
1/20W
21
R7842
1/20W
MF
5%
201
0
21
R7841
1/20W
MF
5%
201
0
21
R7845
201
1/20W
MF
0
5%
21
R7843
0
201
5%
MF
1/20W
21
R7844
0
201
5%
MF
1/20W
56
4
5
3
Q7891
SOT563
SSM6N37FEAPE
WLAN_PCTL:HW
7
19 38 57
52
2
1
R7891
WLAN_PCTL:SW
5%
1/16W
0
402
MF-LF
21
R7811
1/20W
5.1K
MF
5%
201
2
1
C7846
NO STUFF
0.47UF
10%
10V
X5R
402
56
2
1
R7846
5%
0
MF-LF
402
1/16W
57
2
1
R7899
603
NO STUFF
MF-LF
1/10W
0
5%
2
1
C7810
402
0.47UF
10V
X5R
10%
57
42
2
1
R7810
100K
5%
MF
1/20W
201
1
2
R7882
201
15K
MF
1/20W
5%
1
2
R7881
201
MF
1/20W
5%
33K
1
2
R7880
22K
201
MF
5%
1/20W
2
1
C7882
10V
X5R
402
10%
0.47UF
2
1
C7881
402
10%
X5R
10V
0.47UF
2
1
C7880
10V
X5R
10%
402
0.47UF
55
7
19 38 39 57
2
1
R7879
201
1/20W
MF
5%
100K
54
2
1
R7820
10K
5%
MF
1/20W
201
54
55
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
Power Sequencing
S0PGOOD_BJT
S0PGOOD_BJT_L
VMON_3V3_DIV
PP1V5_S0
PP1V05_S0
DDRREG_EN
MAKE_BASE=TRUE
P0V9S5_PGOOD
CPUVTTS0_EN
MAKE_BASE=TRUE
=DDRREG_EN
=P3V3S3_EN
S5PGOOD_DLY
MAKE_BASE=TRUE
MCP_MEM_VDD_EN
PM_SLP_S3_R_L
MAKE_BASE=TRUE
=CPUVTTS0_EN
=P3V3S0_EN
MAKE_BASE=TRUE
P3V3S0_EN
=PBUSVSENS_EN
MCPCORES0_EN
MAKE_BASE=TRUE
PP3V3_S0
=DDRVTT_EN
P3V3S3_EN
MAKE_BASE=TRUE
=P5VS3_EN
PM_SLP_RMGT_L
MAKE_BASE=TRUE
=P3V3ENET_EN
=P0V9ENET_EN
=P1V5S0_EN
PM_SLP_S3_L
P1V5S0_EN
MAKE_BASE=TRUE
=PP3V42_G3H_CHGR
CHGR_VFRQ
CHGR_VFRQ_GATE
PM_SLP_S4_L
PP5V_S0
PP3V3_S0
=PP3V3_S5_VMON
VMON_Q4_BASE
VMON_EMITTER
=PP3V3_S0_PWRCTL
PP3V3_S0_VMON
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VMON_Q3_BASE
PP1V5_S0
PP1V05_S0
S0PGOOD_RST_L
CPUVTTS0_PGOOD
MCPPLLLDO_PGOOD
MCPCORES0_PGOOD
P1V5S0_PGOOD
PM_SLP_S3_L
ALL_SYS_PWRGD
MAKE_BASE=TRUE
=MCPCORES0_EN
VMON_Q2_BASE
MAKE_BASE=TRUE
P5VS3_EN
=P0V9S5_EN
PP3V3_S5
PM_SLP_S4_L
=USB_PWR_EN
P3V3S5_PGOOD
P5VS3_PGOOD
MAKE_BASE=TRUE
P3V3S5_EN
P3V3S5_EN_L
AC_OR_S0_L
PM_WLAN_EN_L
AP_PWR_EN
SMC_ADAPTER_EN
PM_SLP_S3_L
SMC_PM_G2_EN
MAKE_BASE=TRUE
=P5V3V3_REG_EN
P5V_S5_EN
RSMRST_PWRGD
MAKE_BASE=TRUE
=P3V3S5_EN
=PP3V42_G3H_PWRCTL
=PP3V3_S5_P0V9S5
P3V3_BLEED
=PP3V3_S5_REG
P3V3S5_EN_L
=P5VS0_EN
78 OF 110
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7 8
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7
19 38 57
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7 8
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8
8
7 8
57 71
7 8
57
7
19 38 39 57
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8
8
56
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Page 58
GND
VOUT
ON
VIN
D
S
G
D
SG
D
SG
IN
S
G
D
IN
IN
D
G S
D
G S
D
G S
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
3.3V S3 FET
3.3V ENET Switch
0.9V ENET FET
3.294 A (EDP)
Loading
FDC638P
2.0 A @85C
2.0 A @85C
65 mOhm @2.5V
65 mOhm @2.5V
FDC638P
P-Channel
Part
0.100 A (EDP)
3.3V S0 FET
7.2 A @85C
ID(max)
Loading
ID(max)
14 mOhm @4.5V
TPCP8102
Type
Loading
Rds(on)
Type
ID(max)
Part
Type
R(on)
I(max)
Loading
50 mOhm Max
0.4 A (EDP)
2 A
Load Switch
TPS22924C
18 mOhm Typ
U7980
Q7940
Rds(on)
Q7910
Q7930
MOSFET
P-Channel
5V S0 FET
Rds(on)
Type
MOSFET
P-Channel
1.274 A (EDP)
N-Channel
SI2312BDS
3.25 A @85C
0.140 A (EDP)
MOSFET
Rds(on)
Loading
ID(max)
Type
37 mOhm @2.5V
Q7990
4
3
6
5
2
1
Q7910
FDC638P_G
SM
CRITICAL
B1
A1
B2
A2
C2
C1
U7980
TPS22924
CRITICAL
CSP
2
1
C7980
OMIT_TABLE
10%
6.3V
CERM
402
1UF
2
1
C7991
X5R
10V
10%
0.01UF
201
2
1
3
Q7990
CRITICAL
SI2312BDS
SOT23
2
1
C7990
10%
X5R
6.3V
0.1UF
201
1
2
6
Q7991
SSM6N37FEAPE
SOT563
21
R7990
5%
100K
MF
1/20W
201
21
R7991
201
1/20W
MF
10K
1%
2
1
R7992
69.8K
1%
MF
1/20W
201
4
5
3
Q7991
SSM6N37FEAPE
SOT563
2
1
C7911
0.033UF
16V
X5R
402
10%
57
321
4
8765
Q7930
TPCP8102
23V1K-SM
CRITICAL
4
3
6
5
2
1
Q7940
CRITICAL
FDC638P_G
SM
21
R7910
47K
201
MF
1/20W
5%
2
1
R7912
201
MF
1/20W
5%
10K
21
C7930
0.01UF
10%
X5R
201
10V
2
1
C7931
10%
16V
X5R
402
0.033UF
21
R7930
201
MF
1/20W
47K
5%
2
1
R7932
100K
201
MF
1/20W
5%
57
57
2
1
3
Q7903
SSM3K15FV
SOD-VESM-HF
2
1
3
Q7905
SOD-VESM-HF
SSM3K15FV
21
C7940
10%
16V
CERM
402
0.01UF
2
1
C7941
10%
16V
X5R
402
0.033UF
21
C7910
201
10V
X5R
10%
0.01UF
21
R7940
MF
1/20W
201
47K
5%
2
1
R7942
MF
1/20W
201
5%
47K
2
1
3
Q7945
SOD-VESM-HF
SSM3K15FV
57
57
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
Power FETs
P0V9ENET_SS
P0V9ENET_EN_L
P0V9ENET_EN_L_RC
=PP0V9_ENET_P0V9ENETFET
=P0V9ENET_EN
=PP3V3_S5_P0V9ENETFET
=PP0V9_ENET_FET
=PP3V3_S3_FET
P5VS0_EN_L
=P3V3S3_EN
=P3V3S0_EN
=P5VS0_EN
P3V3S3_EN_L
=PP3V3_S0_FET
=PP3V3_S5_P3V3S0FET
P3V3S0_EN_L
P5VS0_SS
=PP5V_S3_P5VS0FET
=PP5V_S0_FET
P3V3S3_SS
P3V3S0_SS
=PP3V3_ENET_FET
=P3V3ENET_EN
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_P3V3S3FET
79 OF 110
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051-8379
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Page 59
GND
THRM
ON
VIN_1
VIN_2
VOUT_1
VOUT_2
PAD
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
BI
BI
BI
IN
SYM_VER-2
SYM_VER-2
NC
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DisplayPort I/F
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP
(DP_INT_AUX_CH_C_N)
LED Backlight I/F
Internal DP Connector: 518S0787
LCD Connector
Pull-ups on panel side,
4.7 kOhm to 3.3V
(DP_INT_AUX_CH_C_P)
2
1
C9012
10UF
603
X5R
6.3V
20%
OMIT_TABLE
2
1
C9011
10%
6.3V
X5R
201
0.1UF
2
1
R9014
1K
5%
1/20W
MF
201
2
1
C9009
0.1UF
201
X5R
6.3V
10%
5
4
3
2
7
1
6
U9000
MFET-2X2
FPF1009
CRITICAL
2
1
C9017
5%
50V
C0G-CERM
603
1000PF
PLACEMENT_NOTE=PLACE CLOSE TO J9000
2
1
C9015
10%
16V
X7R
201
1000PF
21
C9024
0.1uF
402
X5R
16V
10%
21
C9025
10%
16V
X5R
402
0.1uF
21
C9020
10%
16V
X5R
402
0.1uF
21
C9021
0.1uF
402
X5R
16V
10%
21
C9022
0.1uF
402
X5R
16V
10%
21
C9023
10%
16V
X5R
402
0.1uF
9
8
7
6
5
41
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J9000
F-RT-SM
CRITICAL
CABLINE-CA
2
1
R9050
100K
5%
1/20W
MF
201
21
R9060
201
5%
MF
1/20W
0
2
1
R9080
100K
5%
1/20W
MF
201
2
1
R9070
100K
MF
201
1/20W
5%
9
7
62
7
62
7
62
7
62
7
62
7
62
9
71
9
71
9
71
9
71
9
17
9
71
9
71
7
41
7
41
4
32
1
FL9000
CRITICAL
TCM1210-4SM
12-OHM-100MA
4
32
1
FL9001
TCM1210-4SM
12-OHM-100MA
CRITICAL
21
L9004
0402-LF
FERR-120-OHM-1.5A
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
Internal DisplayPort Connector
DP_INT_AUX_CH_C_P
DP_INT_AUX_CH_C_N
DP_INT_ML_F_N<1>
DP_INT_HPD
DP_INT_ML_C_P<1>
DP_INT_ML_C_N<0>
DP_INT_ML_F_N<0>
DP_INT_ML_P<0>
=I2C_TCON_SCL
=I2C_TCON_SDA
PP3V3_SW_LCD_UF
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
DP_INT_ML_F_P<1>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<0>
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
PP3V3_SW_LCD
DP_INT_HPD_CONN
LED_RETURN_4
LED_RETURN_3
LED_RETURN_5
=PP3V3_S0_LCD
DP_INT_AUX_CH_N
DP_INT_AUX_CH_P
DP_INT_ML_N<0>
DP_INT_ML_P<1>
DP_INT_ML_N<1>
LCD_IG_PWR_EN
LED_RETURN_2
DP_INT_ML_F_P<0>
LED_RETURN_1
LED_RETURN_6
PPVOUT_SW_LCDBKLT
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42 62
Page 60
IN
D
SG
D
S G
D
SG
D
S G
BI
BIBI
BI
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: Pulled up to 5V on DP connector page.
(DP_CA_DET_RC)
FET spec’ed for 1.5V Vgs operaiton.
21
C9300
X5R
10%
0.1UF
6.3V
201
21
C9301
201
6.3V
X5R
10%
0.1UF
9
4
5
3
Q9302
SIGNAL_MODEL=DP_AUXCH_FET
SOT563
SSM6N37FEAPE
1
2
6
Q9302
SIGNAL_MODEL=DP_AUXCH_FET
SSM6N37FEAPE
SOT563
4
5
3
Q9300
SSM6N37FEAPE
SOT563
SIGNAL_MODEL=DP_AUXCH_FET
CKPLUS_WAIVE=PdifPr_badTerm
1
2
6
Q9300
SIGNAL_MODEL=DP_AUXCH_FET
CKPLUS_WAIVE=PdifPr_badTerm
SOT563
SSM6N37FEAPE
9
9 9
9
2
1
C9302
201
3300PF
10%
10V
X7R
21
R9302
MF
1/20W
5%
201
22
External DisplayPort Support
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
DP_EXT_AUX_CH_N
DP_CA_DET
DP_AUX_CH_C_P
DP_EXT_DDC_DATA
DP_CA_DET_RC
DP_AUX_CH_C_N
DP_EXT_DDC_CLK
DP_EXT_AUX_CH_P
93 OF 110
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Page 61
BI
IONCNC
IONCIO
IO
NC
GND
GND
DP_PWR
AUX_CHP
GND
RETURN
ML_LANE3P
GND
ML_LANE3N
GND
ML_LANE1P
ML_LANE2N
ML_LANE2P
ML_LANE1N
GND
CONFIG1
HOT_PLUG_DETECT
ML_LANE0P
ML_LANE0N
AUX_CHN
CONFIG2
SHIELD PINS
OUT
SYM_VER-2
IN
SYM_VER-2
SYM_VER-2
SYM_VER-2
IN
IO
NC NC
IO
GND
OUT
IO
NC NC
IO
GND
IN
IN
IN
IN
IN
IN
G
D
S
G
D
S
OUT
G
D
S
G
D
S
BI
IN
IN
OC*
OUT
EN
GND
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(CA) has 100k
pull-up to DP_PWR.
to 100K (DPv1.1a).
greater than or equal
down HPD input with
DP Source must pull
Port Power Switch
Cable Adapter
DP to DVI/HDMI
NOTE: Q9440 must have Drain to Gate
leakage of < 500 nA and gate to
Source resistance of > 5 MOhm.
9
71
2
1
C9400
10%
201
X5R
10V
0.01UF
2
1
C9480
20%
6.3V
603
22UF
X5R-CERM-1
OMIT_TABLE
1 2 4 5
3
D9410
DP_ESD
RCLAMP0524P
CRITICAL
SLP2510P8
2
1
C9487
CRITICAL
100UF
6.3V
POLY-TANT
CASE-B2-SM
20%
19
10
12
15
17
9
11
3
5
22 21
2
14 13
8 7
1
20
6
4
16
18
J9400
F-RT-TH
MINIDSPLYPRT-K99
CRITICAL
39
4
3 2
1
FL9403
CRITICAL
12-OHM-100MA
TCM1210-4SM
9
71
4
32
1
FL9400
CRITICAL
12-OHM-100MA
TCM1210-4SM
4
32
1
FL9401
12-OHM-100MA
CRITICAL
TCM1210-4SM
4
32
1
FL9402
CRITICAL
TCM1210-4SM
12-OHM-100MA
9
71
2
1
R9421
5%
201
MF
1/20W
100K
12
3
D9411
DP_ESD
SLP2510P8
RCLAMP0524P
CRITICAL
21
C9415
0.1UF
6.3V
10% 201X5R
21
C9414
X5R 201
0.1UF
6.3V
10%
9
21
C9411
201X5R
0.1UF
6.3V
10%
21
C9410
X5R 201
0.1UF
6.3V
10%
2
1
R9420
5%
100K
201
MF
1/20W
52
6
4
3
1
D9400
RCLAMP0504F
SC70-6-1
DP_ESD
CRITICAL
54
3
D9411
DP_ESD
SLP2510P8
CRITICAL
RCLAMP0524P
2
1
R9425
201
1/20W
MF
1M
5%
21
C9417
X5R
0.1UF
6.3V
10% 201
21
C9416
201X5R
6.3V
10%
0.1UF
21
C9413
201X5R
0.1UF
6.3V
10%
21
C9412
201X5R
0.1UF
6.3V
10%
9
71
9
71
9
71
9
71
21
L9400
0603
FERR-120-OHM-3A
9
71
9
71
4
5
3
Q9440
2N7002DW-X-G
SOT-363
1
2
6
Q9440
2N7002DW-X-G
SOT-363
2
1
R9443
201
1/20W
MF
100K
5%
2
1
R9442
1/20W
MF
100K
201
5%
9
1
2
6
Q9441
2N7002DW-X-G
SOT-363
4
5
3
Q9441
2N7002DW-X-G
SOT-363
2
1
R9422
5%
MF
1/20W
201
1M
2
1
R9445
5%
1/20W
MF
201
10K
2
1
R9444
5%
10K
201
1/20W
MF
2
1
R9423
201
1/20W
MF
100K
5%
9
71
39
2
1
C9481
0.1UF
201
10%
X5R
6.3V
2
1
C9486
OMIT_TABLE
603
X5R
10UF
20%
6.3V
1
3
5
2
4
U9480
TPS2051B
CRITICAL
SOT23
2
1
C9485
10%
0.1UF
X5R
201
6.3V
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
DisplayPort Connector
DP_EXT_ML_F_N<3>
DP_EXT_AUX_CH_C_P
PP3V3_SW_DPPWR
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
DP_CA_DET_Q
DP_EXT_ML_F_P<2>
DP_EXT_ML_F_N<1>
DP_EXT_ML_F_P<3>
HDMI_CEC
=PP3V3_S5_DP_PORT_PWR
=DP_PWR_EN
DP_HPD_Q
DP_EXT_HPD_L
PP3V3_SW_DPILIM
PP3V3_SW_DPILIM
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
=PP3V3_S0_DPCONN
=PP3V3_S0_DPCONN
TP_DPPWR_OC_L
DP_EXT_ML_P<1>
DP_EXT_ML_N<1>
DP_EXT_HPD
DP_EXT_ML_P<3>
DP_EXT_ML_N<3>
DP_EXT_ML_N<0>
DP_EXT_ML_P<0>
DP_EXT_ML_N<2>
DP_EXT_ML_P<2>
DP_CA_DET_Q_L
=PP5VR3V3_S0_DPCADET
DP_EXT_CA_DET
DP_EXT_AUX_CH_C_N
DP_EXT_ML_C_N<3>
DP_EXT_ML_C_P<3>
DP_EXT_ML_F_P<0>
DP_EXT_ML_F_N<0>
DP_EXT_ML_C_N<0>
DP_EXT_ML_F_P<1>
DP_EXT_ML_C_N<1>
DP_EXT_ML_C_P<1>
DP_EXT_ML_F_N<2>
DP_EXT_ML_C_N<2>
DP_EXT_ML_C_P<2>
DP_EXT_ML_C_P<0>
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61
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61
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61
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71
71
71
71
71
71
71
71
71
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Page 62
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
OUT1
FSET
GD
FILTER
ISET
PWM
EN
FAULT
THRM
GND_L
GND_SW
OUT6
VIN
VDDIO VLDO
FB
SW
OUT2
OUT4
OUT5
VSYNC
OUT3SCLK
SDA
GND_S
PAD
IN
IN
BI
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NO STUFF R9740, C9740, C9741, R9754
FOR LP8543:
I_LED=23.2mA
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
10.2 ohm resistors for current
Addr: 0x58(Wr)/0x59(Rd)
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
measurement on LED strings.
STUFF R9741
Fpwm=9.62kHz
see spec for others
(EEPROM should set EN_I_RES=1)
I_LED=369/Riset
2
1
R9755
MF
1/20W
5%
201
10K
21
R9741
201
1/20W
5%
MF
10K
2
1
C9799
1210-1
50V
X5R
10%
10UF
2
1
C9797
X5R
1210-1
50V
10%
10UF
21
L9701
22UH-2.5A
CRITICAL
IHLP2525CZ-SM
3 4
1 2
R9700
0.01
1W
MF
0612
0.5%
CRITICAL
42 71
42 71
21
R9757
201
MF
5%
0
1/20W
2
1
C9712
25V
10%
X5R
805
10UF
PLACE_NEAR=L9701.1:3mm
CRITICAL
2
1
C9713
PLACE_NEAR=L9701.1:3mm
X5R
402
25V
10%
0.1UF
2
1
C9796
50V
402
10%
X7R-CERM
220PF
PLACE_NEAR=U9701.21:3mm
21
D9701
SOD-123
RB160M-60G
CRITICAL
21
R9722
0
BKLT:PROD
MF-LF
1/16W
5%
402
21
R9721
0
5%
BKLT:PROD
1/16W
MF-LF
402
21
R9720
402
MF-LF
1/16W
BKLT:PROD
0
5%
7
59
7
59
21
R9753
201
5%
1/20W
MF
0
7
59
7
59
7
59
7
59
21
R9718
5%
0
1/16W
MF-LF
402
BKLT:PROD
21
R9719
0
1/16W
MF-LF
BKLT:PROD
402
5%
21
R9717
5%
0
BKLT:PROD
1/16W
MF-LF
402
2
1
R9715
1/20W
100K
201
MF
1%
21
R9731
201
1%
1/20W
MF
200K
2
1
C9723
0.1UF
10%
NO STUFF
402
X5R
25V
2
1
C9710
PLACE_NEAR=U9701.22:5mm
10%
25V
1UF
603-1
X5R
2
1
C9711
PLACE_NEAR=U9701.8:4mm
0.1UF
201
6.3V
X5R
10%
21
XW9710
SM
19
22
23
8
25
24
11
10
2
18
17
16
14
13
12
3
1
9
15
6
5
20
21
7
4
U9701
OMIT_TABLE
CRITICAL
LLP
LP8545SQX
2
1
C9714
0.01UF
PLACE_NEAR=U9701.22:3mm
0201
X7R
10%
10V
2
1
R9703
201
MF
1/20W
5%
0
NO STUFF
2
1
R9702
201
5%
MF
1/20W
0
9
21
R9704
33
201
MF
1/20W
5%
2
1
C9704
NP0-C0G
25V
33PF
5%
201
2
1
R9714
201
18.2K
MF
1/20W
1%
21
R9701
201
MF
0
5%
1/20W
41
41
2
1
R9716
1%
90.9K
201
1/20W
MF
SYNC_DATE=03/31/2010
SYNC_MASTER=K16_MLB
LCD Backlight Driver
R9717,R9718,R9719
BKLT:ENG3
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
103S0198
3
R9720,R9721,R9722
BKLT:ENG
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
103S0198
IC,LP8545,LED BKLT CTRLR,PRODUCTIO,LLP24
353S2896 1 CRITICALU9701 PROJ:K16
IC,LP8545,LED BKLT CTRLR,LLP24,K99 VER
U9701 CRITICAL1 PROJ:K99353S2967
TP_BKL_FAULT
BKL_EN
MIN_LINE_WIDTH=0.4 MM
GND_BKL_SGND
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
BKL_FSET
BKL_VSYNC_R
BKL_ISEN6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKL_ISET
VOLTAGE=24V
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
PPBUS_SW_LCDBKLT_PWR_SW
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
PPVIN_SW_BKL_R
MIN_LINE_WIDTH=0.4 MM
PP5V_S0_BKL_VLDO
VOLTAGE=5V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.5mm
PPBUS_SW_BKL
MIN_NECK_WIDTH=0.25mm
=PP3V3_S0_BKL_VDDIO
BKL_FLTR
BKL_ISEN5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKL_SDA
LCD_BKLT_PWM
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_4
LED_RETURN_2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_6
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
LED_RETURN_5
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
LED_RETURN_1
=I2C_BKL_1_SCL
=I2C_BKL_1_SDA
=PP5V_S0_BKL
PPBUS_SW_LCDBKLT_PWR
BKL_PWM
PPBUS_SW_LCDBKLT_PWR
ISNS_LCDBKLT_P
BKL_ISEN1
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN2
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN4
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN3
ISNS_LCDBKLT_N
BKL_SCL
MIN_LINE_WIDTH=0.5 MM
VOLTAGE=24V
PPVOUT_SW_LCDBKLT
MIN_NECK_WIDTH=0.2 MM
97 OF 110
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051-8379
62 OF 73
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62 63
62 63
7
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Page 63
IN
D
SG
D
SG
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
P-TYPE
FDC638APZ
PPBUS S0 LCDBkLT FET
LOADING
RDS(ON)
MOSFET
43 mOhm @4.5V
0.4 A (EDP)
.
CHANNEL
2
1
R9808
201
MF
1/20W
1%
301K
2
1
R9809
147K
201
1%
MF
1/20W
2
1
C9802
0.1UF
10%
16V
X5R
402
4
3
6521
Q9806
CRITICAL
FDC638APZ_SBMS001
SSOT6-HF
25
1
2
6
Q9807
SSM6N37FEAPE
SOT563
4
5
3
Q9807
SSM6N37FEAPE
SOT563
2
1
R9810
10K
201
1/20W
5%
MF
21
F9800
CRITICAL
2AMP-32V
0603
9
LCD Backlight Support
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
=PPBUS_S0_LCDBKLT
LCDBKLT_EN_DIV
LCDBKLT_DISABLE
BKLT_PLT_RST_L
LCD_BKLT_EN
VOLTAGE=8.4V
PPBUS_SW_LCDBKLT_PWR
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm
LCDBKLT_EN_L
VOLTAGE=8.4V
MIN_NECK_WIDTH=0.25 mm
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
98 OF 110
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051-8379
63 OF 73
8
62
Page 64
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
40x 1uF 0402
ADDITIONAL CPU VCORE HF DECOUPLING
LAYOUT NOTE:
LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU
PLACE ON OPPOSITE SIDE OF CPU
PLACE ON OPPOSITE SIDE OF CPU
LAYOUT NOTE:
LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU
C9909
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9908
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9907
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9906
OMIT_TABLE
402-LF
CRITICAL
6.3V
2.2UF
20%
CERM
C9905
OMIT_TABLE
2.2UF
6.3V
20%
402-LF
CERM
CRITICAL
C9904
2.2UF
OMIT_TABLE
6.3V
20%
402-LF
CERM
CRITICAL
C9903
CRITICAL
2.2UF
OMIT_TABLE
6.3V
20%
402-LF
CERM
C9902
OMIT_TABLE
CRITICAL
2.2UF
6.3V
20%
402-LF
CERM
C9901
OMIT_TABLE
2.2UF
CRITICAL
6.3V
20%
402-LF
CERM
C9900
OMIT_TABLE
2.2UF
6.3V
20%
402-LF
CERM
CRITICAL
C9919
OMIT_TABLE
2.2UF
6.3V
20%
402-LF
CERM
CRITICAL
C9918
OMIT_TABLE
CRITICAL
CERM
6.3V
2.2UF
20%
402-LF
C9917
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9916
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9915
402-LF
OMIT_TABLE
6.3V
2.2UF
20%
CERM
CRITICAL
C9914
CRITICAL
2.2UF
OMIT_TABLE
6.3V
20%
402-LF
CERM
C9913
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9912
OMIT_TABLE
CERM
CRITICAL
6.3V
2.2UF
20%
402-LF
C9911
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9910
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9929
OMIT_TABLE
CRITICAL
6.3V
2.2UF
20%
402-LF
CERM
C9928
2.2UF
402-LF
OMIT_TABLE
6.3V
20%
CERM
CRITICAL
C9927
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9926
OMIT_TABLE
2.2UF
6.3V
20%
402-LF
CERM
CRITICAL
C9925
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9924
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9923
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9922
OMIT_TABLE
2.2UF
6.3V
20%
402-LF
CERM
CRITICAL
C9921
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9920
OMIT_TABLE
CERM
402-LF
6.3V
2.2UF
20%
CRITICAL
C9939
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9938
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9937
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9936
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9935
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9934
OMIT_TABLE
CRITICAL
6.3V
2.2UF
20%
402-LF
CERM
C9933
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9932
OMIT_TABLE
CRITICAL
6.3V
2.2UF
20%
402-LF
CERM
C9931
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
C9930
OMIT_TABLE
6.3V
2.2UF
20%
402-LF
CERM
CRITICAL
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
Additional CPU/GPU Decoupling
=PPVCORE_S0_CPU
99 OF 110
4.4.0
051-8379
64 OF 73
8
11 12
Page 65
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
Signals within each 4x group should be matched within 5 ps of strobe.
FSB 4X signals / groups shown in signal table on right.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
SR DG recommends at least 25 mils, >50 mils preferred
Some signals require 27.4-ohm single-ended impedance.
Most CPU signals with impedance requirements are 55-ohm single-ended.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
ELECTRICAL_CONSTRAINT_SET
CPU / FSB Net Properties
FSB 2X signals / groups shown in signal table on right.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
FSB Clock Constraints
CPU Signal Constraints
MCP FSB COMP Signal Constraints
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1
FSB (Front-Side Bus) Constraints
PHYSICAL
FSB 4X Signal Groups
SPACING
NET_TYPE
Signals
FSB 2X
FSB 1X Signals
FSB 1X signals shown in signal table on right.
(See above)
(FSB_CPURST_L)
(CPU_VCCSENSE)
(CPU_VCCSENSE)
=4x_DIELECTRIC
FSB_DATA
?
TOP,BOTTOM
=STANDARD=STANDARD*
FSB_55S
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
*
=1:1_DIFFPAIR =1:1_DIFFPAIR
FSB_DSTB_55S
=55_OHM_SE
=55_OHM_SE =55_OHM_SE =55_OHM_SE
=4x_DIELECTRICCLK_FSB
?
TOP,BOTTOM
8 MIL
CPU_8MIL
?
*
?
CPU_COMP
*
25 MIL
CPU_AGTL
?
*
=STANDARD
25 MIL
CPU_GTLREF
*
?
=3x_DIELECTRIC
?
CLK_FSB
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
*
CLK_FSB_100D
8 MIL
*
?
MCP_FSB_COMP
CPU_ITP
*
?
=2:1_SPACING
MCP_50S
=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE
* =STANDARD=STANDARD
?
FSB_ADDR
*
=STANDARD
=2x_DIELECTRIC
*
FSB_DATA
?
*
FSB_DSTB
?
=3x_DIELECTRIC =5x_DIELECTRIC
?
FSB_DSTB
TOP,BOTTOM
=3x_DIELECTRIC
?
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
?
TOP,BOTTOM
FSB_1X
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
CPU/FSB Constraints
25 MIL
?
CPU_VCCSENSE
*
CPU_AGTL
?
=2x_DIELECTRIC
TOP,BOTTOM
=27P4_OHM_SE
=27P4_OHM_SE
*
=27P4_OHM_SE =27P4_OHM_SE
7 MIL7 MIL
CPU_27P4S
* =STANDARD =STANDARD
CPU_55S
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
*
FSB_1X
=STANDARD
?
TOP,BOTTOM
?
FSB_ADSTB
=4x_DIELECTRIC
FSB_ADSTB
?
*
=2x_DIELECTRIC
CPU_55S
CPU_AGTL
CPU_STPCLK_L
CPU_ASYNC
CPU_55S
PM_THRMTRIP_L
CPU_8MIL
PM_THRMTRIP_L
FSB_CLK_ITP
CLK_FSB
FSB_CLK_ITP_P
CLK_FSB_100D
CPU_55S
XDP_TRST_L
CPU_ITP
XDP_TRST_L
MCP_FSB_COMP
MCP_50S
MCP_CPU_COMP_VCC
MCP_CPU_COMP
MCP_50S
MCP_BCLK_VML_COMP_VDD
MCP_CPU_COMP MCP_FSB_COMP
CPU_VCCSENSE
IMVP6_VSEN_N
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
IMVP6_VSEN_P
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_N
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_P
CPU_55S
IMVP6_VID<6..0>
CPU_8MIL
CPU_55S
CPU_VID<6..0>
CPU_8MIL
CPU_55S
XDP_BPM_L5
CPU_ITP
XDP_BPM_L<5>
CPU_55S
XDP_CPURST_L
CPU_ITP
CPU_55S
XDP_BPM_L
XDP_BPM_L<4..0>
CPU_ITP
CPU_55SXDP_TCK CPU_ITP
XDP_TCK
CPU_55S
XDP_TDO
XDP_TDO CPU_ITP
CPU_55SXDP_TMS CPU_ITP
XDP_TMS
CPU_55S
PM_DPRSLPVR
CPU_AGTL
PM_DPRSLPVR
FSB_CLK_MCP
CLK_FSB
CLK_FSB_100D
FSB_CLK_MCP_N
FSB_CLK_CPU
FSB_CLK_CPU_N
CLK_FSB
CLK_FSB_100D
CLK_FSB_100D
FSB_CLK_ITP
CLK_FSB
FSB_CLK_ITP_N
FSB_1X
FSB_HIT_L
FSB_1X
FSB_55S
FSB_HITM_L
FSB_1XFSB_1X
FSB_55S
CPU_55S
CPU_SMI_L
CPU_ASYNC
CPU_AGTL
CPU_55S
CPU_PWRGD
CPU_AGTL
CPU_PWRGD
CPU_55S
CPU_PROCHOT_L
CPU_PROCHOT_L
CPU_AGTL
CPU_55S
CPU_FERR_L
CPU_FERR_L
CPU_8MIL
CPU_55S
CPU_BSEL<2..0>
CPU_AGTLCPU_BSEL
CPU_55S
CPU_AGTL
CPU_A20M_L
CPU_ASYNC
FSB_TRDY_L
FSB_1X FSB_1X
FSB_55S
FSB_1X
FSB_CPURST_L
FSB_CPURST_L
FSB_55S
FSB_LOCK_L
FSB_1XFSB_1X
FSB_55S
FSB_1X
FSB_DRDY_L
FSB_1X
FSB_55S
FSB_BNR_L
FSB_1XFSB_1X
FSB_55S
FSB_ADDR_GROUP1
FSB_ADDR
FSB_A_L<35..17>
FSB_55S
FSB_DSTB0
FSB_DSTB
FSB_DSTB_L_N<0>
FSB_DSTB_55S
FSB_D_L<31..16>
FSB_DATA
FSB_DATA_GROUP1
FSB_55S
FSB_DINV_L<1>
FSB_DATA
FSB_DATA_GROUP1
FSB_55S
FSB_D_L<63..48>
FSB_DATA
FSB_DATA_GROUP3
FSB_55S
FSB_DATA_GROUP3
FSB_DINV_L<3>
FSB_DATA
FSB_55S
FSB_DSTB_L_P<3>
FSB_DSTB
FSB_DSTB3
FSB_DSTB_55S
FSB_DSTB
FSB_DSTB3
FSB_DSTB_L_N<3>
FSB_DSTB_55S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_A_L<16..3>
FSB_55S
FSB_ADDR_GROUP0
FSB_REQ_L<4..0>
FSB_ADDR
FSB_55S
FSB_ADSTB
FSB_ADSTB_L<1>
FSB_ADSTB1
FSB_55S
FSB_ADS_L
FSB_1X FSB_1X
FSB_55S
FSB_BREQ0_L
FSB_BREQ0_L
FSB_1X
FSB_55S
FSB_ADSTB
FSB_ADSTB_L<0>
FSB_ADSTB0
FSB_55S
CPU_55S
CPU_AGTL
FSB_CPUSLP_L
FSB_CPUSLP_L
FSB_DSTB0
FSB_DSTB_L_P<0>
FSB_DSTBFSB_DSTB_55S
FSB_DINV_L<2>
FSB_DATA
FSB_DATA_GROUP2
FSB_55S
FSB_DSTB
FSB_DSTB_L_P<1>
FSB_DSTB1
FSB_DSTB_55S
FSB_DATA_GROUP0
FSB_DINV_L<0>
FSB_DATA
FSB_55S
FSB_DATA_GROUP0
FSB_D_L<15..0>
FSB_DATA
FSB_55S
FSB_DSTB
FSB_DSTB2
FSB_DSTB_L_N<2>
FSB_DSTB_55S
FSB_DSTB_L_P<2>
FSB_DSTB
FSB_DSTB2
FSB_DSTB_55S
FSB_DATA
FSB_D_L<47..32>
FSB_DATA_GROUP2
FSB_55S
FSB_DSTB1
FSB_DSTB
FSB_DSTB_L_N<1>
FSB_DSTB_55S
FSB_BPRI_L
FSB_1XFSB_1X
FSB_55S
FSB_1X
FSB_DBSY_L
FSB_1X
FSB_55S
FSB_1X
FSB_DEFER_L
FSB_1X
FSB_55S
FSB_1X
FSB_RS_L<2..0>
FSB_1X
FSB_55S
CPU_GTLREF
CPU_50S
CPU_GTLREF CPU_GTLREF
MCP_50S
MCP_CPU_COMP_GND
MCP_CPU_COMP MCP_FSB_COMP
CPU_55S
CPU_AGTL
IMVP_DPRSLPVR
FSB_CLK_CPU
FSB_CLK_CPU_P
CLK_FSB
CLK_FSB_100D
CPU_55S
CPU_AGTL
FSB_DPWR_L
CPU_ASYNC
CPU_55S
CPU_AGTL
CPU_DPRSTP_L
CPU_DPRSTP_L
CPU_55S
CPU_AGTL
CPU_DPSLP_L
CPU_FROM_SB
MCP_BCLK_VML_COMP_GND
MCP_50S
MCP_CPU_COMP MCP_FSB_COMP
CPU_55S
CPU_IERR_L
CPU_IERR_L
CLK_FSB_100D
FSB_CLK_MCP
CLK_FSB
FSB_CLK_MCP_P
CPU_55S CPU_ITPXDP_TDI
XDP_TDI
CPU_27P4S
CPU_COMP CPU_COMP
CPU_COMP<0>
CPU_50S
CPU_COMP
CPU_COMP<1>
CPU_COMP
CPU_COMP
CPU_COMP<2>
CPU_27P4S
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP<3>
CPU_COMP
CPU_55S
CPU_NMI
CPU_ASYNC_R
CPU_AGTL
CPU_55S
CPU_INTR
CPU_ASYNC_R
CPU_AGTL
CPU_55S
CPU_INIT_L
CPU_INIT_L
CPU_AGTL
CPU_55S
CPU_AGTL
CPU_IGNNE_L
CPU_ASYNC
100 OF 110
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051-8379
65 OF 73
10 14
10 14 39
13 14
10 13
14
14
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53
11 53
11 53
12
11 12 53
10 13
13
10 13
10 13
10 13
10 13
14 53
14
10 14
13 14
7
10 14
7
10 14
10 14
10 13 14
10 14 39
10 14
9
10
10 14
10 14
10 13 14
7
10 14
10 14
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
10 14
7
10 14
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
7
10 14
10 14
10 14
10 14
10 14
10 33
14
10 14
10 14
10 14 53
10 14
14
10
14
10 13
10
10
10
10
10 14
10 14
10 14
10 14
Page 66
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
PHYSICAL
Memory Bus Constraints
NV DG says 2x inner, 4x outer
NV DG says 2x inner, 4x outer
NV DG says 2x inner, 4x outer
NV DG says 2x inner, 4x outer
NV DG says 2x inner, 4x outer
NV DG says 4x inner, 5x outer
NV DG says 2x inner, 4x outer
NV DG says 3x inner, 4x outer
Memory Bus Spacing Group Assignments
Need to support MEM_*-style wildcards!
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2
MCP MEM COMP Signal Constraints
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps
CMD/CTRL signals should be matched within 150 ps.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
DQ signals should be matched within 5 ps of associated DQS pair.
DDR3:
All memory signals maximum length is 1.030 ps.
No DQS to clock matching requirement.
=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE
MEM_50S
=STANDARD* =STANDARD
=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE
MEM_55S
=STANDARD* =STANDARD
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF =70_OHM_DIFF
* =70_OHM_DIFF =70_OHM_DIFF
MEM_70D
MCP_MEM_COMP
* =STANDARD =STANDARD
=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE
=2x_DIELECTRIC
MCP_MEM_COMP
*
?
MEM_DQS2MEM
*
MEM_CLKMEM_DQS
MEM_DQS
MEM_DQS2MEM
*
MEM_CTRL
*
MEM_DQS2MEM
MEM_DQS MEM_CMD
*
MEM_DQS2MEM
MEM_DQS MEM_DQS
MEM_DQS
MEM_DQS2MEM
*
MEM_DATA
*
MEM_DQS
MEM_CTRL2MEM
MEM_CTRL
*
MEM_CLK
MEM_CTRL2MEM
MEM_CTRL
*
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
*
MEM_CTRL2MEM
MEM_DATAMEM_CTRL
MEM_CTRL2MEM
*
MEM_CMD
MEM_CTRL
*
MEM_CLK
MEM_CLK2MEM
MEM_DQS
MEM_CLK2MEM
MEM_CLK
*
MEM_DATA
*
MEM_CLK2MEM
MEM_CLKMEM_CLK
*
MEM_CLK2MEM
MEM_CTRL
MEM_CLK
*
MEM_CLK
MEM_CLK2MEM
MEM_CMD
MEM_2OTHER
**
MEM_DATA
**
MEM_DQS
MEM_2OTHER
* *
MEM_CMD
MEM_2OTHER
* *
MEM_CLK
MEM_2OTHER
**
MEM_CTRL
MEM_2OTHER
*
MEM_DATA2DATA
MEM_DATAMEM_DATA
MEM_DQS
*
MEM_DATA
MEM_DATA2MEM
MEM_CMD
*
MEM_DATA
MEM_DATA2MEM
MEM_CTRL
MEM_DATA2MEM
*
MEM_DATA
MEM_CLK
MEM_DATA
MEM_DATA2MEM
*
MEM_DQS
*
MEM_CMD
MEM_CMD2MEM
MEM_DATA
MEM_CMD2MEM
MEM_CMD
*
MEM_CMD2CMD
MEM_CMDMEM_CMD
*
MEM_CLK
MEM_CMD2MEM
*
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CMD
*
?
*
MEM_2OTHER
25 MIL
=1.5:1_SPACING
?
*
MEM_DATA2DATA
*
MEM_DQS2MEM
=3:1_SPACING
?
?
*
=3:1_SPACINGMEM_DATA2MEM
=3:1_SPACING
?
*
MEM_CMD2MEM
?
*
MEM_CMD2CMD
=1.5:1_SPACING
=4:1_SPACING
?
*
MEM_CLK2MEM
?
*
=2:1_SPACING
MEM_CTRL2CTRL
=2.5:1_SPACING
?
*
MEM_CTRL2MEM
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
Memory Constraints
MEM_55SMEM_A_DQ_BYTE7
MEM_DATA
MEM_A_DQ<63..56>
MEM_50S
MEM_A_CKE
MEM_CTRL
MEM_A_CKE<3..0>
MEM_50S
MEM_B_CKE
MEM_CTRL
MEM_B_CKE<3..0>
MEM_50S
MEM_A_CNTL
MEM_A_CS_L<3..0>
MEM_CTRL
MEM_50S
MEM_A_CMD
MEM_CMD
MEM_A_BA<2..0>
MEM_50S
MEM_A_CMD
MEM_CMD
MEM_A_RAS_L
MEM_55SMEM_A_DQ_BYTE2
MEM_DATA
MEM_A_DQ<23..16>
MEM_55SMEM_A_DQ_BYTE6
MEM_A_DQ<55..48>
MEM_DATA
MEM_55SMEM_A_DQ_BYTE3
MEM_A_DQ<31..24>
MEM_DATA
MEM_55SMEM_A_DQ_BYTE4
MEM_DATA
MEM_A_DM<4>
MEM_55SMEM_A_DQ_BYTE6
MEM_A_DM<6>
MEM_DATA
MEM_A_DQS4
MEM_DQS
MEM_A_DQS_N<4>
MEM_70D
MEM_A_DQS6
MEM_DQS
MEM_A_DQS_N<6>
MEM_70D
MEM_A_DQS7
MEM_70D MEM_DQS
MEM_A_DQS_P<7>
MEM_B_CLK
MEM_70D
MEM_B_CLK_N<5..0>
MEM_CLK
MEM_50S
MEM_B_CNTL
MEM_CTRL
MEM_B_CS_L<3..0>
MEM_70D MEM_DQS
MEM_A_DQS_P<5>
MEM_A_DQS5
MEM_A_DQS3
MEM_70D MEM_DQS
MEM_A_DQS_P<3>
MEM_55SMEM_A_DQ_BYTE0
MEM_A_DM<0>
MEM_DATA
MEM_50S
MEM_A_CNTL
MEM_A_ODT<3..0>
MEM_CTRL
MEM_50S
MEM_A_CMD
MEM_A_A<15..0>
MEM_CMD
MEM_50S
MEM_A_CMD
MEM_CMD
MEM_A_CAS_L
MEM_50S
MEM_A_CMD
MEM_A_WE_L
MEM_CMD
MEM_55SMEM_A_DQ_BYTE0
MEM_A_DQ<7..0>
MEM_DATA
MEM_55SMEM_A_DQ_BYTE5
MEM_DATA
MEM_A_DQ<47..40>
MEM_55SMEM_A_DQ_BYTE1
MEM_A_DM<1>
MEM_DATA
MEM_55SMEM_A_DQ_BYTE2
MEM_DATA
MEM_A_DM<2>
MEM_55SMEM_A_DQ_BYTE4
MEM_DATA
MEM_A_DQ<39..32>
MEM_55SMEM_A_DQ_BYTE1
MEM_DATA
MEM_A_DQ<15..8>
MEM_DQSMEM_70D
MEM_B_DQS0
MEM_B_DQS_P<0>
MEM_DQS
MEM_B_DQS_N<0>
MEM_B_DQS0
MEM_70D
MEM_A_DQS7
MEM_A_DQS_N<7>
MEM_DQSMEM_70D
MEM_B_CLK
MEM_70D
MEM_B_CLK_P<5..0>
MEM_CLK
MEM_70D MEM_CLK
MEM_A_CLK
MEM_A_CLK_P<5..0>
MEM_70D MEM_CLK
MEM_A_CLK
MEM_A_CLK_N<5..0>
MEM_55SMEM_A_DQ_BYTE3
MEM_A_DM<3>
MEM_DATA
MEM_55SMEM_A_DQ_BYTE5
MEM_DATA
MEM_A_DM<5>
MEM_A_DQS0
MEM_70D MEM_DQS
MEM_A_DQS_N<0>
MEM_A_DQS1
MEM_70D MEM_DQS
MEM_A_DQS_N<1>
MEM_DQS
MEM_A_DQS1
MEM_A_DQS_P<1>
MEM_70D
MEM_70D MEM_DQS
MEM_A_DQS_P<2>
MEM_A_DQS2
MEM_A_DQS2
MEM_DQS
MEM_A_DQS_N<2>
MEM_70D
MEM_70D MEM_DQS
MEM_A_DQS_P<4>
MEM_A_DQS4
MEM_70D MEM_DQS
MEM_A_DQS_N<3>
MEM_A_DQS3
MEM_70D MEM_DQS
MEM_A_DQS_N<5>
MEM_A_DQS5
MEM_A_DQS6
MEM_DQS
MEM_A_DQS_P<6>
MEM_70D
MEM_55S
MEM_DATA
MEM_B_DQ<47..40>
MEM_B_DQ_BYTE5
MEM_55S
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ_BYTE4
MEM_55S
MEM_DATA
MEM_B_DQ<15..8>
MEM_B_DQ_BYTE1
MEM_55S
MEM_DATA
MEM_B_DQ<23..16>
MEM_B_DQ_BYTE2
MEM_50S MEM_CMD
MEM_B_WE_L
MEM_B_CMD
MEM_55S
MEM_DATA
MEM_B_DQ<31..24>
MEM_B_DQ_BYTE3
MEM_55S
MEM_DATA
MEM_B_DQ<63..56>
MEM_B_DQ_BYTE7
MEM_55S
MEM_DATA
MEM_B_DQ<55..48>
MEM_B_DQ_BYTE6
MEM_55S
MEM_DATA
MEM_B_DQ<7..0>
MEM_B_DQ_BYTE0
MEM_55S
MEM_DATA
MEM_B_DM<0>
MEM_B_DQ_BYTE0
MEM_50S MEM_CMD
MEM_B_BA<2..0>
MEM_B_CMD
MEM_DQSMEM_70D
MEM_B_DQS_N<6>
MEM_B_DQS6
MEM_DQSMEM_70D
MEM_B_DQS_P<7>
MEM_B_DQS7
MEM_55S
MEM_DATA
MEM_B_DM<7>
MEM_B_DQ_BYTE7
MEM_DQSMEM_70D
MEM_B_DQS_P<6>
MEM_B_DQS6
MEM_DQSMEM_70D
MEM_B_DQS_P<5>
MEM_B_DQS5
MEM_DQS
MEM_B_DQS_N<4>
MEM_70D
MEM_B_DQS4
MEM_DQSMEM_70D
MEM_B_DQS_N<5>
MEM_B_DQS5
MEM_DQSMEM_70D
MEM_B_DQS_N<3>
MEM_B_DQS3
MEM_DQSMEM_70D
MEM_B_DQS_P<4>
MEM_B_DQS4
MEM_DQSMEM_70D
MEM_B_DQS_N<2>
MEM_B_DQS2
MEM_DQSMEM_70D
MEM_B_DQS_P<2>
MEM_B_DQS2
MEM_DQSMEM_70D
MEM_B_DQS_P<1>
MEM_B_DQS1
MEM_DQSMEM_70D
MEM_B_DQS_N<1>
MEM_B_DQS1
MEM_DQSMEM_70D
MEM_B_DQS_P<3>
MEM_B_DQS3
MEM_55S
MEM_DATA
MEM_B_DM<6>
MEM_B_DQ_BYTE6
MEM_55S
MEM_DATA
MEM_B_DM<5>
MEM_B_DQ_BYTE5
MEM_55S
MEM_DATA
MEM_B_DM<3>
MEM_B_DQ_BYTE3
MEM_DQSMEM_70D
MEM_B_DQS_N<7>
MEM_B_DQS7
MEM_55S
MEM_DATA
MEM_B_DM<4>
MEM_B_DQ_BYTE4
MEM_55S
MEM_DATA
MEM_B_DM<2>
MEM_B_DQ_BYTE2
MEM_55S
MEM_DATA
MEM_B_DM<1>
MEM_B_DQ_BYTE1
MEM_50S
MEM_CTRL
MEM_B_CNTL
MEM_B_ODT<3..0>
MCP_MEM_COMP_VDD
MCP_MEM_COMPMCP_MEM_COMP MCP_MEM_COMP
MCP_MEM_COMP_GND
MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP
MEM_50S MEM_CMD
MEM_B_CAS_L
MEM_B_CMD
MEM_50S MEM_CMD
MEM_B_RAS_L
MEM_B_CMD
MEM_50S
MEM_B_A<15..0>
MEM_CMD
MEM_B_CMD
MEM_55SMEM_A_DQ_BYTE7
MEM_A_DM<7>
MEM_DATA
MEM_A_DQS0
MEM_A_DQS_P<0>
MEM_70D MEM_DQS
101 OF 110
4.4.0
051-8379
66 OF 73
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Page 67
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6
Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3.
Max trace length: LVDS 10 inches, DP 8.5 inches.
DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
SATA intra-pair matching should be 1 ps.
NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.
LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2
SATA Interface Constraints
R/G/B signals should be matched as close as possible and < 10 inches.
CRT signal single-ended impedence varies by location:
- 50-ohm from first to second termination resistor.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.
NEED PCIe Gen1/Gen2 notes!
Digital Video Signal Constraints
- 37.5-ohm from MCP to first termination resistor.
- 75-ohm from output of three-pole filter to connector (if possible).
Analog Video Signal Constraints
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3
ELECTRICAL_CONSTRAINT_SET
MCP89 Net Properties
NET_TYPENET_TYPE
SPACING
PHYSICAL
PCI-Express
PCIE_90D
=90_OHM_DIFF =90_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF*
=90_OHM_DIFF
=90_OHM_DIFF
PCIE
?
TOP,BOTTOM
=4X_DIELECTRIC
20 MIL
CLK_PCIE
?
*
8 MIL
MCP_PEX_COMP
?
*
PCIE
=3X_DIELECTRIC
?
*
=100_OHM_DIFF
=100_OHM_DIFF
CLK_PCIE_100D =100_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF
*
=100_OHM_DIFF
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
MCP Constraints 1
CRT_2CRT
*
CRTCRT
CRT_50S
=50_OHM_SE
=STANDARD* =STANDARD
=50_OHM_SE=50_OHM_SE =50_OHM_SE
CRT
*
?
20 MIL
TOP,BOTTOM
=4x_DIELECTRIC
?
DISPLAYPORT
?
LVDS
=4x_DIELECTRIC
TOP,BOTTOM
CRT_2CRT
?
*
15 MIL
?
*
CRT_2CLK
50 MIL
MCP_DAC_COMP
*
?
=2x_DIELECTRIC
CRT_SYNC
?
*
=4x_DIELECTRIC
*
?
CRT_2SWITCHER
250 MIL
?
*
LVDS
=3x_DIELECTRIC
=100_OHM_DIFF
LVDS_100D
*
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SATA
?
TOP,BOTTOM
=4x_DIELECTRIC
*
?
SATA_TERMP 8 MIL
?
SATA
*
=3x_DIELECTRIC
*
SATA_90D
=90_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF
=3x_DIELECTRIC
*
?
DISPLAYPORT
*
Y
20 MIL 20 MIL
=STANDARD
=STANDARD =STANDARD
MCP_DV_COMP
DP_90D
=90_OHM_DIFF=90_OHM_DIFF
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF
=90_OHM_DIFF*
DP_90D
DP_IG_ML0_P<3..0>
DISPLAYPORT
DP_EXT_ML
DP_90D
DISPLAYPORT
DP_IG_AUX_CH0_P
DP_EXT_AUX_CH
DP_IG_AUX_CH0_N
DISPLAYPORT
DP_90D
DP_EXT_AUX_CH
MCP_DV_COMP
MCP_TMDS0_RSET
MCP_TMDS0_RSET
DP_INT_ML
DP_90D
DP_IG_ML1_P<1..0>
DISPLAYPORT
DP_INT_ML
DISPLAYPORT
DP_90D
DP_IG_ML1_N<1..0>
DP_IG_ML0_N<3..0>
DP_90D
DISPLAYPORT
DP_EXT_ML
LVDS_100D
LVDS_IG_A_CLK
LVDS_IG_A_CLK_P
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS_IG_A_DATA_P<2..0>
LVDS
LVDS
LVDS_IG_A_DATA_P<3>
LVDS_100D
LVDS_IG_A_DATA3
LVDS_100D
LVDS_IG_A_DATA_N<3>
LVDS
LVDS_IG_A_DATA3
MCP_TMDS0_VPROBE
MCP_TMDS0_VPROBE
LVDS_IG_A_CLK_N
LVDS
LVDS_100D
LVDS_IG_A_CLK
LVDS_IG_B_CLK_P
LVDS
LVDS_IG_B_CLK
LVDS_100D
LVDS_IG_B_CLK_N
LVDS
LVDS_100D
LVDS_IG_B_CLK
PCIEPCIE_90D
PCIE_ENET_D2R_N
PCIEPCIE_90D
PCIE_ENET_D2R_C_P
PCIEPCIE_90D
PCIE_ENET_D2R_C_N
PCIEPCIE_90D
PCIE_FW_R2D_P
PCIE_FW_R2D
PCIE_FW_R2D_C_P
PCIEPCIE_90D
PCIEPCIE_90D
PCIE_FW_R2D_C_N
PCIE_FW_D2R
PCIE_FW_D2R_P
PCIEPCIE_90D
PCIE_FW_D2R_N
PCIEPCIE_90D
PCIE_FW_D2R_C_N
PCIEPCIE_90D
CLK_PCIE
PEG_CLK100M_P
CLK_PCIE_100D
MCP_PE0_REFCLK
PEG_CLK100M_N
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_AP_N
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_ENET_P
CLK_PCIE_100D
MCP_PE2_REFCLK
CLK_PCIE
PCIE_CLK100M_ENET_N
CLK_PCIE_100D
CRT_IG_R_C_PR
CRT
CRT_50SCRT_RED
CRT_50S
CRT_IG_G_Y_Y
CRT
CRT_GREEN
CRT_50S
CRT
CRT_IG_B_COMP_PB
CRT_BLUE
PCIE_CLK100M_FW_N
CLK_PCIE_100D
CLK_PCIE
PCIE_FW_D2R_C_P
PCIEPCIE_90D
PCIE_90D PCIE
PEG_D2R_N<15..0>
PEG_D2R_C_N<15..0>
PCIEPCIE_90D
PCIE_AP_R2D_C_P
PCIE_AP_R2D
PCIE_90D PCIE
MCP_SATA_TERMP
SATA_TERMP
MCP_SATA_TERMP
SATA
SATA_ODD_D2R_C_P
SATA_90D
SATA_ODD_D2R_C_N
SATASATA_90D
SATA
SATA_ODD_D2R_N
SATA_90D
SATA_ODD_D2R_P
SATASATA_ODD_D2R SATA_90D
SATA
SATA_ODD_R2D_N
SATA_90D
SATA
SATA_ODD_R2D_C_N
SATA_90D
SATA
SATA_ODD_R2D_P
SATA_90D
SATA_ODD_R2D_C_P
SATASATA_ODD_R2D SATA_90D
SATA
SATA_HDD_D2R_C_N
SATA_90D
SATA
SATA_HDD_D2R_C_P
SATA_90D
SATA
SATA_HDD_D2R_P
SATA_HDD_D2R SATA_90D
SATA
SATA_HDD_D2R_N
SATA_90D
SATA
SATA_HDD_R2D_N
SATA_90D
SATA_HDD_R2D_P
SATASATA_90D
SATA
SATA_HDD_R2D_C_N
SATA_90D
SATA_HDD_R2D_C_P
SATASATA_HDD_R2D SATA_90D
MCP_IFPAB_VPROBE
MCP_IFPAB_VPROBE
LVDS
LVDS_100D
LVDS_IG_B_DATA3
LVDS_IG_B_DATA_N<3>
LVDS
LVDS_100D
LVDS_IG_B_DATA3
LVDS_IG_B_DATA_P<3>
LVDS
LVDS_100D
LVDS_IG_B_DATA
LVDS_IG_B_DATA_P<2..0>
LVDS_100D
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA
LVDS
DP_INT_AUX_CH
DP_IG_AUX_CH1_N
DP_90D
DISPLAYPORT
PCIEPCIE_90D
PCIE_ENET_R2D_N
PCIEPCIE_90D
PCIE_ENET_D2R_P
PCIE_ENET_D2R
PCIEPCIE_90D
PCIE_ENET_R2D_P
PCIEPCIE_90D
PCIE_ENET_R2D_C_N
PEG_D2R_C_P<15..0>
PCIEPCIE_90D
PEG_R2D_C_P<15..0>
PCIE_90D PCIE
PEG_R2D
PEG_D2R_P<15..0>
PCIE_90D PCIE
PEG_D2R
PCIE_AP_R2D_N
PCIEPCIE_90D
PCIE_90D PCIE
PEG_R2D_C_N<15..0>
PCIEPCIE_90D
PCIE_AP_R2D_P
MCP_IFPAB_RSET
MCP_IFPAB_RSET
MCP_DV_COMP
LVDS_100D
LVDS_IG_B_DATA
LVDS
LVDS_IG_B_DATA_N<2..0>
MCP_PEX_COMP
MCP_PEX0_TERMP
MCP_PEX_CLK_COMP
CLK_PCIE
PCIE_CLK100M_FW_P
CLK_PCIE_100D
MCP_PE3_REFCLK
PCIEPCIE_90D
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D
PCIE_FW_R2D_N
PCIEPCIE_90D
PCIE_CLK100M_AP_P
CLK_PCIE
CLK_PCIE_100D
MCP_PE1_REFCLK
PCIEPCIE_90D
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_D2R
PCIEPCIE_90D
PCIE_AP_R2D_C_N
PCIEPCIE_90D
PEG_R2D_N<15..0>
PCIE_90D PCIE
PCIE_90D PCIE
PEG_R2D_P<15..0>
CRT_50S
CRT_IG_VSYNC
CRT_SYNCCRT_SYNC
MCP_TV_DAC_VREF
MCP_DAC_COMPMCP_DAC_VREF
CRT_IG_HSYNC
CRT_SYNC
CRT_50S
CRT_SYNC
MCP_TV_DAC_RSET
MCP_DAC_COMPMCP_DAC_RSET
DP_INT_AUX_CH
DP_IG_AUX_CH1_P
DP_90D
DISPLAYPORT
102 OF 110
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16 34
16 34
18
9
18
9
18
9
9
18
9
9
18
7
35
7
35
18 35
18 35
7
35
7
35
18 35
18 35
17 24
9
17
7
34
7
34
17 24
16
7
16 34
7
16 34
7
16 34
16 34
9
17
Page 68
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MCP89 Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SMBus Interface Constraints
USB 2.0 Interface Constraints
SPI Interface Constraints
HD Audio Interface Constraints
LPC Bus Constraints
PHYSICAL
SPACING
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.7
(SMBUS_SMC_MGMT_SCL)
(SMBUS_SMC_MGMT_SDA)
SIO Signal Constraints
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.12
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.11
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.9
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.10
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.8
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF=90_OHM_DIFF*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=STANDARD*
LPC_55S
=55_OHM_SE =55_OHM_SE =55_OHM_SE
=STANDARD
=55_OHM_SE
=STANDARD =STANDARD
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
CLK_LPC_55S
*
=1.5x_DIELECTRIC
*
?
LPC
=2x_DIELECTRIC
?
*
CLK_LPC
*
?
USB
=2x_DIELECTRIC
=55_OHM_SE
* =STANDARD =STANDARD
SMB_55S
=55_OHM_SE =55_OHM_SE =55_OHM_SE
=2x_DIELECTRIC
?
*
SMB
* =STANDARD=STANDARD
HDA_55S
=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE
?
*
8 MIL
MCP_HDA_COMP
=2x_DIELECTRIC
HDA
*
?
=STANDARD =STANDARD
CLK_SLOW_55S
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
*
=1.5x_DIELECTRIC
*
CLK_SLOW
?
=STANDARD=STANDARD*
=55_OHM_SE =55_OHM_SE =55_OHM_SE
SPI_55S
=55_OHM_SE
=1.5x_DIELECTRIC
*
SPI
?
8 MIL
=STANDARD
=STANDARD =STANDARD
8 MIL
=STANDARD
*
MCP_USB_RBIAS
USB
?
TOP,BOTTOM
=4x_DIELECTRIC
MCP Constraints 2
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
SPI
SPI_55S
SPI_ALT_CLK
SPI_55S
SPI
SPI_ALT_MISO
SPI_55S
SPI
SPI_ALT_MOSI
SPI
SPI_55S
SPI_ALT_CS_L
SPI_55S
SPI
SPI_MLB_CS_L
SPI
SPI_55S
SPI_MLB_MOSI
SPI_55S
SPI
SPI_MLB_CLK
SPI_CS0_L
SPI_55S
SPI
SPI
SPI_55S
SPI_MOSI
SPI_CLK
SPI
SPI_55S
HDA_55S
HDA
HDA_RST_R_L
HDA_RST_L
HDA_55S
HDA
HDA_RST_L
SPI_55S
SPI
SPI_MOSI
SPI_MOSI_R
SPI
SPI_55SSPI_CS0
SPI_CS0_R_L
HDA_SDIN_CODEC
HDA_55S
HDA
HDA_55S
HDA_SDOUT
HDA
HDA_SDOUT
HDA
HDA_SDOUT_R
HDA_55S
PM_CLK32K_SUSCLK_R
CLK_SLOWCLK_SLOW_55S
MCP_SUS_CLK
USB
USB_EXTC_N
USB_90D
USB
USB_90D
USB_SDCARD_N
USB_90D
USB
USB_EXTC
USB_EXTC_P
USB
USB_90D
USB_T57_P
USB_T57
USB_CAMERA_N
USB_90D
USB
USB_BT_P
USB_BT
USB
USB_90D
USB_TPAD
USB_TPAD_P
USB_90D
USB
USB_TPAD_N
USB_90D
USB
USB_IR
USB_90D
USB
USB_IR_P
USB_IR_N
USB
USB_90D
USB_EXTB_P
USB_EXTB
USB
USB_90D
USB_EXTB_N
USB
USB_90D
USB_90D
USB
USB_T57_N
USB_90D
USB
USB_WM_N
HDA_55S
HDA
HDA_BIT_CLK
HDA_BIT_CLK
HDA_55S
HDA
HDA_SYNC_R
HDA_SDIN0
HDA_55S
HDA
HDA_SDIN0
USB_CAMERA_P
USB
USB_CAMERA
USB_90D
USB_BT_N
USB
USB_90D
USB_90D
USB_EXTD_N
USB
USB_EXTD
USB_90D
USB_EXTD_P
USB
USB_90D
USB
USB_MINI_N
USB_EXTA_MUXED_N
USB
USB_90D
USB_MINI_P
USB_MINI
USB_90D
USB
USB_EXTA_MUXED_P
USB_90D
USB
USB_90D
USB_EXTA_N
USB
USB_EXTA_P
USB_90D
USB
USB_EXTA
LPC_CLK33M_LPCPLUS
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_SMC
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_SMC_R
CLK_LPC_55S
CLK_LPC
MCP_LPC_CLK0
LPC_55S
LPC_RESET_L
LPC
LPC_RESET_L
LPC_55S
LPC
LPC_FRAME_L
LPC_FRAME_L
LPC
LPC_55S
LPC_AD<3..0>
LPC_AD
SPI_MISO
SPI_55S
SPI_MISO
SPI
PM_CLK32K_SUSCLK
CLK_SLOW_55S CLK_SLOW
MCP_HDA_PULLDN_COMP
MCP_HDA_PULLDN_COMP
MCP_HDA_COMP
HDA_55S
HDA
HDA_BIT_CLK_R
HDA_55S
HDA_SYNC
HDA
HDA_SYNC
SMB_55S
SMB
SMBUS_MCP_1_DATA
SMB_55S
SMB
SMBUS_MCP_1_CLK
SMB_55S
SMBUS_MCP_0_DATA
SMB
SMBUS_MCP_0_DATA
SMB_55S
SMBUS_MCP_0_CLK
SMBUS_MCP_0_CLK
SMB
MCP_USB_RBIAS MCP_USB_RBIAS
MCP_USB_RBIAS_GND
USB_90D
USB
USB_SDCARD_P
USB_SDCARD
USB
USB_90D
USB_WM
USB_WM_P
SPI_55SSPI_CLK
SPI_CLK_R
SPI
SPI
SPI_55S
SPI_MLB_MISO
103 OF 110
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7
19 37
19 40
19 40
7
19 37
19
19 25
9
18
9
18
9
18
7
18 37
7
18 34
18 46 71
18 46 71
7
19 37
19
7
19 37
7
18 37
7
18 34
7
18 37
7
18 37
9
18
36 71
9
18
36 71
18 36
18 36
7
25 40
25 38
19 25
19 25
7
19 38 40
7
19 38 40
19 40
25 38
19
19
7
19 37
19 41
19 41
19 41
19 41
18
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18
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Page 69
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SD Card Interface Constraints
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
BCM5764M/BCM57765 co-layout.
ELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
NET_TYPE
SPACING
NOTE: SD_D<7..5> are different to support
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
SPACING
RGMII Net Properties
SPACING
MCP RGMII (Ethernet) Constraints
SD Card Net Properties
PHYSICAL
Ethernet Net Properties
88E1116R (Ethernet PHY) Constraints
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
=STANDARD
MCP_MII_COMP
*
7.5 MIL
=STANDARD=STANDARD
7.5 MIL
=STANDARD
=55_OHM_SE
=55_OHM_SE
* =STANDARD=STANDARD
ENET_MII_55S
=55_OHM_SE =55_OHM_SE
?
=3:1_SPACINGMCP_BUF0_CLK
*
ENET_MII
*
?
12 MIL
=100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
*
=100_OHM_DIFF
ENET_MDI_100D
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
Ethernet Constraints
25 MIL
ENET_MDI
*
?
SD_55S
=55_OHM_SE=55_OHM_SE =55_OHM_SE
=STANDARD=STANDARD
=55_OHM_SE
*
SD_INTERFACE
=3X_DIELECTRIC
?
*
ENET_RESET_L
ENET_MIIENET_MII_55S
ENET_MII
ENET_MDIO
ENET_MDIO
ENET_MII_55S
ENET_RXCLK
ENET_CLK125M_RXCLK_R
ENET_MIIENET_MII_55S
ENET_MIIENET_MII_55S
ENET_RXD_STRAP
ENET_RXD<3..1>
ENET_MII_55S ENET_MIIENET_RXD
ENET_RX_CTRL
ENET_MII
ENET_RXD_R<3..0>
ENET_MII_55S
ENET_CLK125M_RXCLK
ENET_MII_55S ENET_MII
ENET_MIIENET_TXD
ENET_TXD<0>
ENET_MII_55S
ENET_MII_55S
ENET_TXD<3..1>
ENET_MIIENET_TXD
ENET_INTR_L
ENET_MII_55S
ENET_INTR_L
ENET_MII
RTL8211_CLK25M_CKXTAL1
MCP_BUF0_CLKENET_MII_55S
MCP_BUF0_CLK
MCP_CLK25M_BUF0
MCP_CLK25M_BUF0_R
ENET_MII_55S
MCP_MII_COMP_VDD
MCP_MII_COMP MCP_MII_COMP
MCP_MII_COMP_GND
MCP_MII_COMP MCP_MII_COMP
ENET_MII
ENET_MDC
ENET_MDC ENET_MII_55S
ENET_MII
ENET_PWRDWN_L
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII_55S
ENET_CLK125M_TXCLK
ENET_MII
ENET_TXCLK
ENET_TX_CTRL
ENET_MII_55S ENET_MIIENET_TXD
ENET_MDI
ENET_MDI_100D
ENET_MDI_N<3..0>
ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI
ENET_MDI_100D
SD_55S
SD_INTERFACE
SDCONN_DATA<4..0>
SD_INTERFACE
SD_DATA
SD_55S
SD_D<4..0>
SD_55S
SD_INTERFACE
BCM57765_CR_DATA<4>
SD_D<7..5>
SD_DATA_R
SD_INTERFACE
SD_55S
SD_INTERFACE
SD_55S
SDCONN_DATA<7..5>
BCM57765_CR_DATA<7..5>
SD_INTERFACE
SD_55S
SD_CLK SD_55S
SD_INTERFACE
SD_CLK
SD_55S
SD_INTERFACE
SDCONN_CLK
SD_55S
SD_INTERFACE
SD_CLK_R
SD_55S
SD_INTERFACE
SDCONN_CMD
SD_INTERFACE
SD_55SSD_CMD
SD_CMD
BCM57765_CR_CMD
SD_INTERFACE
SD_55S
ENET_RXD_STRAP
ENET_MII
ENET_RXD<0>
ENET_MII_55S
104 OF 110
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TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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SIZE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
SPACING
SMC SMBus Net Properties
SPACING
PHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SMC Constraints
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
=STANDARD =STANDARD
0.1 MM 0.1 MM
*
=STANDARD=STANDARD
1TO1_DIFFPAIR
SMB_55S
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SCL
SMB
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SDA
SMB
SMB_55S
SMBUS_SMC_MGMT_SCL
SMB
SMB_55S
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SCL
SMB
SMB_55S
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SDA
SMB
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SCL
SMB_55S
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SDA
SMB
SMB_55S
SMBUS_SMC_B_S0_SDA
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMBUS_SMC_B_S0_SCL
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMBUS_SMC_A_S3_SDA
SMB_55S
SMBUS_SMC_A_S3_SDA
SMB
CHGR_CSI
1TO1_DIFFPAIR
CHGR_CSI_P
1TO1_DIFFPAIR
CHGR_CSI_N
CHGR_CSI_R_P
1TO1_DIFFPAIR
CHGR_CSO_R_N
1TO1_DIFFPAIR
CHGR_CSO_N
1TO1_DIFFPAIR
CHGR_CSO_P
1TO1_DIFFPAIR
CHGR_CSO
CHGR_CSI_R_N
1TO1_DIFFPAIR
CHGR_CSO_R_P
1TO1_DIFFPAIR
106 OF 110
4.4.0
051-8379
70 OF 73
41
41
41
41
7
41
7
41
41
41
41
41
50
50
50
43 50
50
50
50
43 50
Page 71
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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DRAWING NUMBER
SIZE
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SHEET
PAGE TITLE
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2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
SD CARD READER LAYOUT RELAXATIONS
MCP Fanout Constraint Relaxations
Graphics Net Properties
(DP_EXT_ML)
(DP_EXT_AUX_CH)
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
SPACING
ELECTRICAL_CONSTRAINT_SET
Audio Net Properties
PHYSICAL
NET_TYPE
SPACING
Power Net Properties
ELECTRICAL_CONSTRAINT_SET
(USB_EXTA)
(USB_EXTA)
PHYSICAL
Misc Net Properties
(USB_TPAD)
(USB_EXTA)
SPACING
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
SPACING
NET_TYPE
(USB_TPAD)
(USB_TPAD)
(USB_TPAD)
(USB_EXTA)
=1:1_DIFFPAIR
*
=55_OHM_SE
SENSE_1TO1_55S
=55_OHM_SE=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
PWR_P2MM
MEM_POWER
*
MEM_CLK
SB_POWER PWR_P2MM
SATA
*
SB_POWER PWR_P2MM
USB
*
GND
*
GND_P2MMENET_MDI
PWR_P2MM
MEM_POWER
*
MEM_CTRL
MEM_CLK
GND_P2MM
*
GND
MEM_CMD
GND_P2MM
*
GND
MEM_CTRL GND_P2MM
*
GND
MEM_DATA GND_P2MM
*
GND
*
1000
0.20 MM
PWR_P2MM
1000
0.20 MM
*
GND_P2MM
MEM_POWER
?
*
=STANDARD
GND
?
=STANDARD
*
PCIE
*
GND
GND_P2MM
GND_P2MM
USB
*
GND
SB_POWER PWR_P2MMCLK_PCIE
*
GND_P2MM
GND
*
LVDS
GND_P2MMCLK_PCIE
*
GND
GND_P2MM
SATA
*
GND
MEM_DQS
GND_P2MM
*
GND
GND_P2MM
CPU_GTLREF
*
GND
GND_P2MMCPU_COMP
*
GND
GND_P2MM
*
GND
CLK_FSB
PWR_P2MM
MEM_POWER
*
MEM_CMD
PWR_P2MM
MEM_POWER
*
MEM_DATA
PWR_P2MM
MEM_POWER
*
MEM_DQS
CPU_VCCSENSE
*
GND
GND_P2MM
=1:1_DIFFPAIR
=1:1_DIFFPAIR
*
DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
*
THERM_1TO1_55S
=1:1_DIFFPAIR
=55_OHM_SE =55_OHM_SE=55_OHM_SE
?
25 MILS
*
ENETCONN
=1:1_SPACING
*
SENSE
?
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
K16/K99 Specific Constraints
=1:1_SPACING
?
*
AUDIO
=1:1_SPACING
?
*
THERM
0.1 MM
500 MIL
TOP
MCP_MII_COMP
0.25 MM
*
250 MIL
MCP_DV_COMP
0.1 MMTOP
MCP_USB_RBIAS
500 MIL
MCP_MEM_COMP
0.1 MM
500 MIL
TOP
MCP_DV_COMP
TOP
500 MIL
0.1 MM
*
0.09 MM
5.8 MM
MEM_40S
=STANDARD
SD_55S
*
USB_90D
USB
USB_TPAD_N
MCPTHMSNS_D2
MLBR_THMDIODE_P
THERM_1TO1_55S
THERM
THERM
CPU_THERMD_P
THERM_1TO1_55S
CPU_THERMD
DRAMTHMSNS_D2_P
THERM_1TO1_55S
THERM
CPUTHMSNS_D2
DRAMTHMSNS_D2_N
THERM_1TO1_55S
THERM
USB_TPAD_CONN_P
USB_90D
USB
USB_EXTA_MUXED_N
USB
USB_90D
USB_LT1_N
USB
USB_90D
USB_90D
USB_LT1_P
USB
USB
USB_EXTA_MUXED_P
USB_90D
USB_90D
USB
USB_TPAD_P
USB_TPAD_CONN_N
USB_90D
USB
THERM
CPU_THERMD_N
THERM_1TO1_55S
MLBR_THMDIODE_N
THERM_1TO1_55S
THERM
MCP_THMDIODE_P
THERM
THERM_1TO1_55S
MCP_THMDIODE
THERM
MCP_THMDIODE_N
THERM_1TO1_55S
CPUVTTS0_CS_P
SENSE
SENSE_1TO1_55SSENSE_DIFFPAIR
CPUVTTS0_CS_N
SENSE
SENSE_1TO1_55S
IMVP6_CS_R_N
SENSE
SENSE_1TO1_55S
IMVP6_CS_P
SENSE
SENSE_1TO1_55SSENSE_DIFFPAIR
ISNS_1V5_S3_P
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
ISNS_1V5_S3_N
SENSE
SENSE_1TO1_55S
ISNS_CSREG_P
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
ISNS_AIRPORT_P
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE
ISNS_AIRPORT_N
SENSE_1TO1_55S
SENSE
ISNS_CSREG_N
SENSE_1TO1_55S
SENSE
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
ISNS_HDD_P
ISNS_LCDBKLT_N
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
ISNS_HDD_N
ISNS_LCDBKLT_P
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
CPU_VTTSENSE_P
SENSE_1TO1_55S
SENSE
CPU_VTTSENSE_N
SENSE
SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
MCPCORES0_VSEN_P
SENSE
SENSE
SENSE_1TO1_55S
MCPCORES0_VSEN_N
PP3V3_S5
SB_POWER
PP3V3_S0
SB_POWER
PP1V5_S0
SB_POWER
SPKRAMP_INR
SPKRAMP_INR_P
DIFFPAIR
AUDIO
MAX98300_R
MAX98300_R_P
AUDIO
DIFFPAIR
MAX98300_R_N
AUDIO
DIFFPAIR
I2C_SMC_SMS_SDA_R
SMBUS_SMC_MGMT_SDA
SMB
SMB_55S
SMB_55S
SMB
I2C_SMC_SMS_SCL_R
SMBUS_SMC_MGMT_SCL
DP_INT_ML_N<1..0>
DISPLAYPORT
DP_90D
DISPLAYPORT
DP_90D
DP_INT_ML_F_P<1..0>
DISPLAYPORT
DP_90D
DP_INT_ML_F_N<1..0>
DISPLAYPORT
DP_INT_AUX_CH_C_P
DP_90D
DP_INT_AUX_CH_N
DISPLAYPORT
DP_90D
DP_INT_AUX_CH_P
DISPLAYPORT
DP_90D
DISPLAYPORT
DP_EXT_ML_P<3..0>
DP_90D
DP_EXT_ML_N<3..0>
DISPLAYPORT
DP_90D
DISPLAYPORT
DP_EXT_ML_C_P<3..0>
DP_90D
DP_EXT_ML_C_N<3..0>
DISPLAYPORT
DP_90D
DP_90D
DISPLAYPORT
DP_EXT_ML_F_P<3..0>
DP_90D
DISPLAYPORT
DP_EXT_ML_F_N<3..0>
DP_EXT_AUX_CH_C_P
DP_90D
DISPLAYPORT
DP_90D
DP_EXT_AUX_CH_C_N
DISPLAYPORT
I2C_TCON_SCL
SMB
SMB_55S
I2C_TCON_SDA
SMB_55S
SMB
I2C_TCON_SDA_CONN
SMB
SMB_55S
I2C_TCON_SCL_CONN
SMB_55S
SMB
DP_INT_ML_P<1..0>
DISPLAYPORT
DP_90D
DP_INT_ML_C_P<1..0>
DISPLAYPORT
DP_90D
DP_90D
DISPLAYPORT
DP_INT_ML_C_N<1..0>
SPKRAMP_INR_N
DIFFPAIR
AUDIO
DP_90D
DISPLAYPORT
DP_INT_AUX_CH_C_N
IMVP6_CS_N
SENSE
SENSE_1TO1_55S
IMVP6_CS_R_P
SENSE
SENSE_1TO1_55SSENSE_DIFFPAIR
MEM_POWER
PP1V5R1V35_S3
GND
GND
108 OF 110
4.4.0
051-8379
71 OF 73
18 46 68
44
10 44
44
44
7
46
36 68
36
36
36 68
18 46 68
7
46
10 44
44
19 44
19 44
55
55
53
53
42 52
42 52
43
34 42
34 42
43
35 42
42 62
35 42
42 62
55
55
22 54
22 54
7 8
57
7 8
57
7 8
57
7
37 48
48
48
9
59
7
59
7
59
7
59
9
59
9
59
9
61
9
61
61
61
61
61
9
61
9
61
41
41
9
59
59
59
7
37 48
7
59
53
53
7 8
Page 72
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
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SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_BOARD_INFO
VERSION
ALLEGRO
(MIL or MM)
BOARD UNITS
BOARD LAYERS
BOARD AREAS
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
K99 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
0.350 MM
5X_DIELECTRIC
?
*
*
1.5X_DIELECTRIC
0.105 MM
?
2X_DIELECTRIC
0.140 MM
?
*
0.210 MM
3X_DIELECTRIC
?
*
0.280 MM
*
4X_DIELECTRIC
?
ISL4,ISL9
0.250 MM0.250 MM
27P4_OHM_SE
Y
TOP,BOTTOM
0.110 MM
50_OHM_SE
Y
0.110 MM
Y
50_OHM_SE
ISL3,ISL4,ISL9,ISL10
0.090 MM 0.090 MM
55_OHM_SE =STANDARD=STANDARD=STANDARD
=STANDARDY =STANDARD*
40_OHM_SE
0.140 MM
ISL3,ISL4,ISL9,ISL10
Y
0.140 MM
=STANDARD50_OHM_SE
=STANDARD* Y
=STANDARD=STANDARD
=STANDARD
0.3 MM
BGA_P3MM
*
?
0.2 MM
*
BGA_P2MM
?
0.1 MM
?
*
BGA_P1MM
0.130 MM0.130 MM
0.155 MM0.155 MM
ISL4,ISL9
70_OHM_DIFF
Y
55_OHM_SE
ISL3,ISL4,ISL9,ISL10
Y
0.076 MM0.076 MM
ISL4,ISL9
80_OHM_DIFF
0.160 MM0.160 MM
0.125 MM0.125 MM
Y
0.130 MM0.130 MM
0.135 MM0.135 MM
ISL3,ISL10
Y
70_OHM_DIFF
TOP,BOTTOM
Y
55_OHM_SE
0.090 MM 0.090 MM
0.170 MM
40_OHM_SE
0.170 MM
Y
TOP,BOTTOM
15.5.1
NO_TYPE,BGA
MM
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
0.250 MM
27P4_OHM_SE
0.250 MM
Y
ISL3,ISL10
TOP,BOTTOM
0.130 MM0.130 MM
0.175 MM0.175 MM
70_OHM_DIFF
Y
70_OHM_DIFF
=STANDARD
=STANDARD
Y
*
=STANDARD
=STANDARD=STANDARD
=STANDARD =STANDARD
Y
=STANDARD
*
1:1_DIFFPAIR
0.1 MM 0.1 MM
0.200 MM
0.085 MM
Y
100_OHM_DIFF
0.085 MM
0.200 MM
ISL4,ISL9
0.105 MM
Y
90_OHM_DIFF
0.105 MM
0.210 MM 0.210 MM
ISL4,ISL9
0.089 MM
Y
90_OHM_DIFF
0.089 MM
0.210 MM 0.210 MM
ISL3,ISL10
=STANDARD
=STANDARD=STANDARD
=STANDARD
*
Y
=STANDARD
90_OHM_DIFF
0.140 MM
0.140 MM0.140 MM
0.140 MM
75_OHM_DIFF
ISL4,ISL9
Y
0.105 MM0.105 MM
95_OHM_DIFF
ISL4,ISL9
0.210 MM0.210 MM
Y
0.115 MM
95_OHM_DIFF
0.210 MM0.210 MM
0.115 MM
Y
TOP,BOTTOM
=STANDARD
95_OHM_DIFF
=STANDARD
Y
*
=STANDARD =STANDARD
=STANDARD
95_OHM_DIFF
ISL3,ISL10
0.210 MM0.210 MM
0.089 MM
Y
0.089 MM
100_OHM_DIFF
=STANDARD =STANDARD
=STANDARD=STANDARD
=STANDARD
*
Y
TOP,BOTTOM
Y
0.115 MM 0.115 MM
0.210 MM 0.210 MM
90_OHM_DIFF
0.160 MM0.160 MM
0.109 MM0.109 MM
ISL3,ISL10
Y
80_OHM_DIFF
80_OHM_DIFF
0.160 MM0.160 MM
0.140 MM0.140 MM
TOP,BOTTOM
Y
80_OHM_DIFF
=STANDARD
*
Y
=STANDARD
=STANDARD =STANDARD
=STANDARD
*
=DEFAULT
=DEFAULT
=DEFAULT
Y
12.7 MM
=DEFAULT
STANDARD
*
DEFAULT
0.076 MM
30 MM
0 MM 0 MM
Y
0.100 MM
75_OHM_DIFF
=STANDARD
=STANDARD
=STANDARDY
*
=STANDARD =STANDARD
75_OHM_DIFF
0.160 MM0.160 MM
0.160 MM0.160 MM
TOP,BOTTOM
Y
0.300 MM
100_OHM_DIFF
Y
0.075 MM 0.075 MM
0.300 MM
ISL3,ISL10
0.091 MM
Y
100_OHM_DIFF
TOP,BOTTOM
0.091 MM
0.200 MM 0.200 MM
Y
75_OHM_DIFF
0.120 MM
0.140 MM0.140 MM
0.120 MM
ISL3,ISL10
=STANDARD=STANDARD =STANDARD
=STANDARDY =STANDARD*
27P4_OHM_SE
=STANDARD=STANDARD
*
=STANDARD
Y =STANDARD=STANDARD
40_OHM_SE
?
*
=STANDARDPP1V5_MEM
0.25 MM
2.5:1_SPACING
*
?
=STANDARD
GND
*
?
0.2 MM
1000
GND_P2MM
*
1000
PWR_P2MM
*
0.2 MM
?
=STANDARDNB_STATIC
*
1:1_SPACING
*
?
0.1 MM
1.5:1_SPACING
?
*
0.15 MM
0.18 MM
*
?
1.8:1_SPACING
0.2 MM
*
?
2:1_SPACING
2.28:1_SPACING
?
*
0.228 MM
0.3 MM
3:1_SPACING
*
?
4:1_SPACING
*
0.4 MM
?
STANDARD
*
=DEFAULT
?
DEFAULT
0.1 MM
?
*
SYNC_DATE=07/07/2010
SYNC_MASTER=K16_MLB
K99 RULE DEFINITIONS
109 OF 110
4.4.0
051-8379
72 OF 73
Page 73
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICALDESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICALDESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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REVISION
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SHEET
PAGE TITLE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTIONQTYPART NUMBER CRITICAL
TAIYO YUDEN
MURATA
TAIYO YUDEN
TAIYO YUDEN
MURATA
TAIYO YUDEN
MURATA
SAMSUNG
SAMSUNG
SAMSUNG
SAMSUNG
22UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS
10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS
2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS
MURATA
1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS
3
CAP, 22UF, 6.3V, 20%, 0603
C1223,C1226,C1227
CRITICAL
SS_CAP_22UF
138S0635
4
C1210,C1214,C1217,C1218
CAP, 22UF, 6.3V, 20%, 0603
138S0635
SS_CAP_22UF
CRITICAL
5
CAP, 22UF, 6.3V, 20%, 0603
C1230,C4902,C7360,C7361,C9480
SS_CAP_22UF
CRITICAL
138S0635
C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999
CRITICAL
138S0626
CAP, 10UF, 6.3V, 20%, 0603
8
SS_CAP_10UF
10
138S0634
TY_CAP_2_2UF
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
Acoustic Cap BOM Config Tables
SYNC_MASTER=K16_MLB
SYNC_DATE=07/07/2010
8
138S0626
CAP, 10UF, 6.3V, 20%, 0603
CRITICAL
C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647
SS_CAP_10UF
CAP, 10UF, 6.3V, 20%, 0603
138S0626
1
C1280
CRITICAL
SS_CAP_10UF
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
CAP, 2.2UF, 6.3V, 20%, 0402
SS_CAP_2_2UF
CRITICAL
138S0632
10
C7203,C7980
2
138S0628
MU_CAP_1UF
CRITICAL
CAP, 1UF, 6.3V, 10%, 0402
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310
9
MU_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647
CRITICAL
8
CAP, 10UF, 6.3V, 20%, 0603
138S0625
MU_CAP_10UF
C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999
8
TY_CAP_10UF
138S0627
CAP, 10UF, 6.3V, 20%, 0603
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
10
138S0634
TY_CAP_2_2UF
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
CRITICAL
5
C1230,C4902,C7360,C7361,C9480
CAP, 22UF, 6.3V, 20%, 0603
CRITICAL
TY_CAP_22UF
138S0688
3
CAP, 22UF, 6.3V, 20%, 0603
C1223,C1226,C1227
TY_CAP_22UF
138S0688
CRITICAL
4
CAP, 22UF, 6.3V, 20%, 0603
C1210,C1214,C1217,C1218
CRITICAL
TY_CAP_22UF
138S0688
5
C1230,C4902,C7360,C7361,C9480
CAP, 22UF, 6.3V, 20%, 0603
138S0676
MU_CAP_22UF
CRITICAL
3
C1223,C1226,C1227
CAP, 22UF, 6.3V, 20%, 0603
138S0676
MU_CAP_22UF
CRITICAL
4
C1210,C1214,C1217,C1218
CAP, 22UF, 6.3V, 20%, 0603
CRITICAL
138S0676
MU_CAP_22UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
CRITICAL10SS_CAP_2_2UF
2
C7203,C7980
CRITICAL
SS_CAP_1UF
CAP, 1UF, 6.3V, 10%, 0402
138S0629
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
SS_CAP_2_2UF
10
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
138S0632
CRITICAL
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
SS_CAP_2_2UF
10
CAP, 2.2UF, 6.3V, 20%, 0402
138S0632
10
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
CAP, 2.2UF, 6.3V, 20%, 0402
SS_CAP_2_2UF
138S0632
CRITICAL
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
SS_CAP_2_2UF
CAP, 2.2UF, 6.3V, 20%, 0402
12
138S0632
CRITICAL
138S0632
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310
9
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
SS_CAP_2_2UF
SS_CAP_2_2UF
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
CRITICAL
10
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
CAP, 2.2UF, 6.3V, 20%, 0402
138S0632
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
CRITICAL
SS_CAP_2_2UF
10
CRITICAL
C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999
MU_CAP_10UF
CAP, 10UF, 6.3V, 20%, 0603
8
138S0625
1
C1280
CRITICAL
MU_CAP_10UF
138S0625
CAP, 10UF, 6.3V, 20%, 0603
C1280
1
CAP, 10UF, 6.3V, 20%, 0603
TY_CAP_10UF
138S0627
CRITICAL
CRITICAL
C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647
8
138S0627
CAP, 10UF, 6.3V, 20%, 0603
TY_CAP_10UF
CRITICAL
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
CAP, 2.2UF, 6.3V, 20%, 0402
10
138S0632
SS_CAP_2_2UF
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
8
138S0632
SS_CAP_2_2UF
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
10
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
CAP, 2.2UF, 6.3V, 20%, 0402
138S0632
SS_CAP_2_2UF
CRITICAL
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
SS_CAP_2_2UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
10
CRITICAL
138S0633
10
CRITICAL
MU_CAP_2_2UF
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
CAP, 2.2UF, 6.3V, 20%, 0402
138S0633
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
MU_CAP_2_2UF
10
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
MU_CAP_2_2UF
138S0633
8
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
CRITICAL
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
MU_CAP_2_2UF
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
10
MU_CAP_2_2UF
138S0633
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
10
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
MU_CAP_2_2UF
138S0633
12
CRITICAL
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
10
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
138S0633
MU_CAP_2_2UF
MU_CAP_2_2UF
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
CRITICAL
10
CAP, 2.2UF, 6.3V, 20%, 0402
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
MU_CAP_2_2UF
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
CRITICAL
10
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
8
SS_CAP_2_2UF
138S0632
CRITICAL
10
138S0633
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
MU_CAP_2_2UF
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
MU_CAP_2_2UF
CRITICAL
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
8
CAP, 2.2UF, 6.3V, 20%, 0402
138S0633
CRITICAL
10
CAP, 2.2UF, 6.3V, 20%, 0402
138S0633
MU_CAP_2_2UF
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
MU_CAP_2_2UF
10
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
138S0633
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
TY_CAP_2_2UF
9
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
10
TY_CAP_2_2UF
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
CRITICAL
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
8
138S0634
TY_CAP_2_2UF
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
138S0634
10
TY_CAP_2_2UF
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
138S0634
12
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
TY_CAP_2_2UF
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
138S0634
10
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
CRITICAL
TY_CAP_2_2UF
138S0634
10
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
CRITICAL
CAP, 2.2UF, 6.3V, 20%, 0402
TY_CAP_2_2UF
CAP, 2.2UF, 6.3V, 20%, 0402
10
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
CRITICAL
TY_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
TY_CAP_2_2UF
138S0634
8
CAP, 2.2UF, 6.3V, 20%, 0402
138S0634
CRITICAL
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
TY_CAP_2_2UF
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
10
CAP, 2.2UF, 6.3V, 20%, 0402
CRITICAL
TY_CAP_2_2UF
138S0634
CRITICAL
10
CAP, 2.2UF, 6.3V, 20%, 0402
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
TY_CAP_2_2UF
138S0634
C7203,C7980
2
138S0630
CAP, 1UF, 6.3V, 10%, 0402
TY_CAP_1UF
CRITICAL
110 OF 110
4.4.0
051-8379
73 OF 73
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