Page 1
SCHEM,EVT,MLB,K21
www.laptopblue.vn
04/18/11
DATE
2011-04-18
(.csa)
TABLE_TABLEOFCONTENTS_HEAD
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10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
42
43
44
45
1
1 MASTER
2 K6_MLB
3
4 MASTER
5
6 (K99_MLB)
7
8
9
Table of Contents
2
System Block Diagram
3
Power Block Diagram
4
Revision History
5
BOM Configuration
7
Functional Test / No Test
8
Power Aliases
9
Signal Aliases
10
CPU DMI/PEG/FDI/RSVD
11
CPU CLOCK/MISC/JTAG
12
CPU DDR3 INTERFACES
13
CPU POWER
14
CPU GROUNDS
16
CPU DECOUPLING-I
17
CPU DECOUPLING-II
18
PCH SATA/PCIE/CLK/LPC/SPI
19
PCH DMI/FDI/GRAPHICS
20
PCH PCI/FLASHCACHE/USB
21
PCH MISC
22
PCH POWER
23
PCH GROUNDS
24
PCH DECOUPLING
25
CPU & PCH XDP
26
USB HUBS
27
Clock (CK505) and Chipset Support
28
CPU Memory S3 Support
29
DDR3 DRAM CHANNEL A (0-31)
30
DDR3 DRAM CHANNEL A (32-63)
31
DDR3 DRAM CHANNEL B (0-31)
32
DDR3 DRAM CHANNEL B (32-63)
33
FSB/DDR3/FRAMEBUF Vref Margining
34
DDR3 DRAM Channel B (32-63)
35
SecureDigital Card Reader
36
T29 Host (1 of 2)
37
T29 Host (2 of 2)
38
T29 Power Support
40
X21 WIRELESS CONNECTOR
45
SATA CONNECTOR
46
External USB Connectors
47
Left I/O (LIO) Connector
49
SMC41
50
SMC Support
51
LPC+SPI Debug Connector
52
SMBus Connections
53
Voltage & Load Side Current Sensing
Contents
K17_REF
K91_MLB
K91_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K21_MLB
K21_MLB
K21_MLB
K21_MLB
K21_MLB
K78_MLB
K78_MLB
K21_MLB
K21_MLB
K78_MLB
K21_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
(MASTER)
K78_MLB
K78_MLB
K78_MLB
K21_MLB
K78_MLB
K21_MLB
K21_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
Date
SyncPage
MASTER
12/11/2009
19/01/2011
MASTER
05/28/2009
(02/16/2010)
05/15/2010
05/15/2010
01/10/2011
01/10/2011
01/10/2011
01/10/2011
01/10/2011
02/08/2011
01/10/2011
12/13/2010
12/13/2010
12/13/2010
12/13/2010
12/13/2010
01/10/2011
01/10/2011
12/13/2010
12/13/2010
11/29/2010
12/13/2010
12/07/2010
12/07/2010
12/07/2010
12/07/2010
01/10/2011
12/16/2010
(MASTER)
01/10/2011
01/10/2011
01/10/2011
12/13/2010
01/10/2011
12/13/2010
11/09/2010
01/10/2011
01/10/2011
01/10/2011
01/10/2011
01/10/2011
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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Page
(.csa)
54
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
High Side Current Sensing
55
Thermal Sensors
56
Fan
57
IPD / KBD Backlight
61
SPI ROM
62
AUDI0: SPEAKER AMP
69
DC-In & Battery Connectors
70
PBus Supply & Battery Charger
71
System Agent Supply
72
5V / 3.3V Power Supply
73
1.5V DDR3 Supply
74
CPU IMVP7 & AXG VCore Regulator
75
CPU IMVP7 & AXG VCore Output
76
CPU VCCIO (1.05V) Power Supply
77
Misc Power Supplies
78
Power FETs
79
Power Control 1/ENABLE
90
Internal DisplayPort Connector
93
DisplayPort/T29 A MUXing
94
DisplayPort/T29 A Connector
97
LCD Backlight Driver
100
CPU Constraints
101
Memory Constraints
102
PCH Constraints 1
103
PCH Constraints 2
104
Ethernet/FW Constraints
105
T29 Constraints
106
SMC Constraints
108
Project Specific Constraints
109
PCB Rule Definitions
Contents
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
JACK_K90I
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K78_MLB
K21_MLB
K78_MLB
K78_MLB
K21_CONSTRAINTS
K21_CONSTRAINTS
K21_CONSTRAINTS
K21_CONSTRAINTS
K21_CONSTRAINTS
K21_CONSTRAINTS
K21_CONSTRAINTS
K21_CONSTRAINTS
K21_CONSTRAINTS
Sync
Date
01/16/2011
01/16/2011
01/10/2011
01/10/2011
01/10/2011
01/10/2011
08/20/2010
12/03/2010
01/16/2011
01/16/2011
01/10/2011
01/10/2011
12/07/2010
01/10/2011
01/16/2011
01/10/2011
01/10/2011
02/10/2011
12/13/2010
12/07/2010
01/16/2011
04/06/2011
04/06/2011
04/06/2011
04/06/2011
04/06/2011
04/06/2011
04/06/2011
04/06/2011
04/06/2011
D
C
B
DRAWING TITLE
SCHEM,MOCKUP,MLB,K21
QTY
1
1
DESCRIPTION
SCHEM,MLB,K21
PCBF,MLB,K21
8 7 6 5 4 2 1
REFERENCE DES
SCH
PCB
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
PRODUCT SAFETY REQUIREMENTS:
PCB,UL RECOGNIZED, MIN. 130-C TEMP RATING AND V-O FLAME RATING PER UL 796 & UL 94
PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE
NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP RATING AND V-O FLAME RATING
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Apple Inc.
R
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
051-8870
3.13.0
1 OF 109
1 OF 75
SIZE
A
D
Page 2
www.laptopblue.vn
345678
2 1
1G/2GB
J2500
CPU
XDP CONN
PG 23
D
J9000
INTERNAL
DISPLAY
CONN
PG 63
JTAG
PG 10
PCIE
PG 9
U2900,U3030
U1000
INTEL CPU
EDP
PG 9
SANDYBRIDGE SFF
1.6 GHZ
FDI
PG 9
DMI
PG 9
MEMORY
PG 11
DDR3-1066/1333MHZ
A
DDR3-1066/1333MHZ
B
64-Bit
64-Bit
MEMORY
PG 27,38
U3100,3230
MEMORY
PG 29,30
1G/2GB
U7000
CHARGER
PG 52
D
POWER CIRCUITRY
PG 52-60
TEMP SENSOR
PG 47
U2700
SYSTEM
CLOCK
PG 25
J4501
SSD
C
CONN
PG 38
RTC
PG 16
CLOCK
BUFFER
PG16
SATA
PG 16
FDI
PG 17
DMI
PG 17
U1800
EDP OUT
HDMI OUT
U3600
T29 ROUTER
J9400
DISPLAY PORT+
T29
CONN
PG 65
1
U9390
MUX
PG 64
0
B
PG 34,35
PCIE
DP
J4610
PCH
XDP CONN
PG 23
X21
CONN
PG 37
PCIE
USB
J4001
WIRELESS
RGB OUT
DVI OUT
TMDS OUT
LVDS OUT
DP OUT
PG 17
JTAG
PG 16
PCIE
INTEL PCH
COUGAR POINT
PCI
PG 18PG 16
SMB
PG 16
GPIO
PG 15
SPI
PG 16
MISC
PG 19
LPC
PG 16
PWR
CTRL
PG 17
USB
PG 18
HDA
U6100
BOOTROM
PG 50
U4900
J5100
LPC+SPI
CONN
PG 43
U2600
USB
HUB-1
3
4
5 1
6
7 2
8 0
9
10
1112
13
PG 16
U2650
PG 24
USB
HUB-2
PG 24
U3500
SD CARD
CONTROLLER
PG 33
J5700
IPD FLEX
CONN
PG 49
J4600
RIGHT
EXT USB
CONN
PG 39
J3500
SERIAL
PORT
PM_SLP
S3/S4
SDCARD
CONN
PG 33
SMB_BSA SMB_B/0
SMC
PG 41
ADC
FAN0
LID
SMB_A
VOLTAGE/CURRENT SENSOR
PG 46
J5600
FAN CONN
PG 48
C
B
U6210
SPEAKER
J4700
HDA
LEFT I/O CONN
PG 40
U6201
AUDIO CODEC
PG 7
U6620
J6702
AMP
PG 9
LEFT
SPEAKER
CONN
A
LINE INSPEAKER
FILTER
PG 11
J6700
HEADPHONE/
LINE IN
JACK
PG 10
PG 10
CAM
HEADPHONE
FILTER
PG 8
USBUSB
EXT
J4702
CAMERA+ALS
CONN
LIO BOARD
J6955
HALL
EFFECT
PG 51
J4610
EXT USB
LEFT
CONN
PG 5PG 6
SPK
I2C
AMP
PG 51
8 7 5 4 2 1
J6903
RIGHT
SPEAKER
CONN
PG 52
SIZE
A
D
SYNC_MASTER=K6_MLB
PAGE TITLE
System Block Diagram
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/11/2009
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
2 OF 109
SHEET
2 OF 75
36
Page 3
PPDCIN_G3H_OR_PBUS
R6905
PPVIN_G3H_P3V42G3H
www.laptopblue.vn
D6905
2
R6920
ENABLE
3.425V G3HOT
LT3470A
U6990
(PAGE 52)
PP3V42_G3H_REG
345678
3
SMC POWER
SN0903048
U5010
(PAGE 42)
SMC_RESET_L
2 1
4
R7640
A
CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD
A
PPVTT_S0_DDR_LDO
16-1
DDRREG_PGOOD
PPVCCSA_S0_REG
15
10-4
PP5V_S0_VMON
PP1V5_S3RS0_VMON
PP1V05_S0_VMON
P1V8S0_PGOOD
PP1V8_S0_REG
1V05_S0_LDO_EN
PP3V3_T29_FET
PPCPUVCCIO_S0_REG
SMC_CPU_FSB_ISENSE
22-1
R5320
SMC_CPU_VSENSE
V
PPVCORE_S0_CPU_REG
R5330
SMC_GFX_VSENSE
V
PPVCORE_S0_AXG_REG
25-1
26-1
R7350
PPDDR_S3_REG
P1V5CPU_EN
23-1
PP3V3_S0_VMON
V2MON
ISL88042IRTEZ
V3MON
V4MON
(PAGE 62)
18
TPS720105
EN
U7780
(PAGE 60)
U7770
TPS72015
(PAGE 60)
PP1V5S0_EN
A
VDD
U7960
EN
R7140
6
U7801
PP1V05_S0_LDO.
36
TPS22924
U3816/U3815
(PAGE 36)
25
26
16
PP1V5_S3RS0_FET
23
CPUIMVP_AXG_PGOOD
P1V8S0_PGOOD
P5VS3_PGOOD
P3V3S5_PGOOD
CPUVCCIOS0_PGOOD
PVCCSA_PGOOD
ALL_SYS_PWRGD
R7962
4
19
PP1V5_S0_REG
22
D
T29_PWR_EN
PP1V05_T29_FET
27
U2850
25
S5_PWRGD
SMC_ONOFF_L
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
9
5
PAGE TITLE
COUGAR-POINT
(PCH)
U1800
PM_PCH_PWRGD
(PAGE 17~21)
CPU
U1000
UNCOREPWRGOOD
(PAGE 9~15)
SMC
PWRGD(P12)
RSMRST_IN(P13)
PWR_BUTTON(P90)
SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)
U4900
(PAGE 41)
SYS_RERST#
PROCPWRGD
DRAMPWROK
SM_DRAMPWROK
RESET*
RSMRST_OUT(P15)
99ms DLY
IMVP_VR_ON(P16)
SYSRST(PA2)
P17(BTN_OUT)
PWRBTN#
RSMRST#
DPWROK
PLTRST#
P15
RES*
PM_PWRBTN_L
PM_SYSRST_L
PM_RSMRST_L
PM_DSW_PWRGD
PLT_RERST_L
CPU_PWRGD
PM_MEM_PWRGD
30
PM_DSW_PWRGD
PM_RSMRST_L
CPUIMVP_VR_ON
PM_SYSRST_L
PM_PWRBTN_L
SMC_RESET_L
Power Block Diagram
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
29
28
10
12
26
6-1
4
SYNC_DATE=19/01/2011
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
3 OF 109
SHEET
3.13.0
3 OF 75
SIZE
C
B
A
D
EN
VCC
EN
VR_ON
PP3V3_S0
VIN
1.05V
ISL95870
U7600
(PAGE 59)
VIN
CPU VCORE
MAX15092GTL
U7400
(PAGE 57)
1.5V
S5
S3
0.75V
TPS51916
U7300
(PAGE 56)
VCC
ISL95870A
EN
(PAGE 54)
VID1
16
ISL8014A
EN
(PAGE 60)
TPS22924
EN
(PAGE 36)
VOUT
PGOOD
VOUT
VOUT
PGOOD
PGOODG
VIN
VLDOIN
VOUT1
VOUT2
PGOOD
U7100
VOUT
PGOOD
PP1V05_SUS_LDO
U7720
U3810
CPUVCCIOS0_PGOOD
PVCCSA_PGOOD
PP5V_S0_FET
J6900
F6905
D
AC
ADAPTER
DCIN(14.5V)
IN
6A FUSE
SMC_DCIN_ISENSE
4
J6950
PPVBATT_G3H_CONN
2S3P
(6 TO 8.4V)
1
R7020
A
SMC_RESET_L
VIN
BATTERY CHARGER
Q7055
CHGR_BGATE
U7000
ISL6259HRTZ
PBUS SUPPLY/
(PAGE 53)
PPVBAT_G3H_CHGR_R
VOUT
PPVBAT_G3H
R7050
SMC_BATT_ISENSE
A
1
F7040
PPBUS_G3H
R5400
A
K78/K21 POWER SYSTEM ARCHITECTURE
C
B
A
SMC
U4900
(PAGE 41)
COUGAR-POINT
(PCH)
U1800
(PAGE 17~21)
1V05_S0_LDO_EN
CPUVCCIOS0_EN
RC
DELAY
PVCCSA_EN
RC
DELAY
P1V5S0_EN
RC
DELAY
P1V8S0_EN
RC
DELAY
P60
SLP_S5#(E4)
SLP_SUS#
SLP_S4#(H4)
SLP_S3#(F4)
6
SMC_PM_G2_EN
PM_SLP_SUS_L
PM_SLP_S3_R_L
21
21
22
19
17
RC
DELAY
PM_SLP_S5_L
U7940
RC
DELAY
RC
DELAY
PM_SLP_S4_L
PM_SLP_S3_L
R7978
P5VS0_EN
P3V3S0_EN
PBUSVSENS_EN
P3V3S5_EN
PG 17
P5V_3V3_SUS_EN
P3V3S3_EN
DDRREG_EN
P5VS3_EN
PG 17
PG 17
PG62
14-1
14-1
14-1
PG62
PG62
PG62
7
11
10-1
PG61
13
15
13-2
13
14
F9700
LCD_BKLT_EN
BKLT_PLT_RST_L
&&
PPBUS_SW_LCDBKLT_PWR
Q5300
PBUSVSENS_EN
T29_A_HV_EN
T29BST_EN_UVLO
Q9706
Q3880
EN
13-1
VIN
LP8550
U9701
(PAGE 66)
PPVIN_S5_P5VP3V3
P5VS3_EN
P3V3S5_EN
7
VOUT
VIN
LT3957
U3890
EN/UVLO
(PAGE 36)
EN1
EN2
PPVOUT_SW_LCDBKLT
SMC_PBUS_VSENSE
PP15V_T29_REG
VOUT
VIN
5V
(L/H)
3.3V
(R/H)
TPS51980
U7201
(PAGE 55)
PGOOD
P5VS3_PGOOD
P3V3S5_PGOOD
VOUT1
VOUT2
PP5V_S3_REG
PP3V3_S5_REG
14-1
9
PP3V3_S5
P5V_3V3_SUS_EN
P5V_3V3_SUS_EN
P3V3S0_EN
14
22
Q7820
Q7810
P3V3S3_EN
Q7840
Q7830
15
PP5V_S0_CPUVCCIOS0.
CPUVCCIOS0_EN
21
CPUIMVP_VR_ON
DDRREG_EN
DDRVTT_EN
PP5V_S0_VCCSA
PVCCSA_EN
CPU_VCCSA_VID<1>
14
8
10-3
PP3V3_SUS_FET
PP3V3_S3_FET
PP5V_SUS_FET
24
Q7860
P5VS0_EN
TPS720105
U7740
(PAGE 60)
14-1
10-2
P1V8_S0_EN
17
T29_PWR_EN
8 7 5 4 2 1
Page 4
www.laptopblue.vn
345678
2 1
BOM Variants
BOM NUMBER
D
C
085-2684
607-8041
639-2553
639-2554
639-2558
639-2549
639-2555
639-2557
639-2548
639-2550
639-2551
639-2552
639-2556
639-2559
BOM NAME
K21i MLB DEVELOPMENT BOM
CMN PTS,PCBA,MLB,K21
PCBA,MLB,1.8GHZ,HY 2GB,K21
PCBA,MLB,1.7GHZ,SA 4GB,K21
PCBA,MLB,1.8GHZ,EL 4GB,K21
PCBA,MLB,1.7GHZ,EL 4GB,K21
PCBA,MLB,1.8GHZ,HY 4GB,K21
PCBA,MLB,1.8GHZ,SA 4GB,K21
PCBA,MLB,1.7GHZ,HY 2GB,K21
PCBA,MLB,1.8GHZ,MI 2GB,K21
PCBA,MLB,1.7GHZ,HY 4GB,K21
PCBA,MLB,1.7GHZ,SA 2GB,K21
PCBA,MLB,1.8GHZ,SA 2GB,K21
PCBA,MLB,1.7GHZ,MI 2GB,K21
BOM OPTIONS
K21_DEVEL:ENG
K21_COMMON
K21_CMNPTS,EEEE:DP1F,CPU:1.8GHZ,DDR3:HYNIX_2GB
K21_CMNPTS,EEEE:DP1G,CPU:1.7GHZ,DDR3:SAMSUNG_4GB
K21_CMNPTS,EEEE:DP1H,CPU:1.8GHZ,DDR3:ELPIDA_4GB
K21_CMNPTS,EEEE:DP1J,CPU:1.7GHZ,DDR3:ELPIDA_4GB
K21_CMNPTS,EEEE:DP1K,CPU:1.8GHZ,DDR3:HYNIX_4GB
K21_CMNPTS,EEEE:DP1L,CPU:1.8GHZ,DDR3:SAMSUNG_4GB
K21_CMNPTS,EEEE:DP1M,CPU:1.7GHZ,DDR3:HYNIX_2GB
K21_CMNPTS,EEEE:DP1N,CPU:1.8GHZ,DDR3:MICRON_2GB
K21_CMNPTS,EEEE:DP1P,CPU:1.7GHZ,DDR3:HYNIX_4GB
K21_CMNPTS,EEEE:DP1Q,CPU:1.7GHZ,DDR3:SAMSUNG_2GB
K21_CMNPTS,EEEE:DP1R,CPU:1.8GHZ,DDR3:SAMSUNG_2GB
K21_CMNPTS,EEEE:DP1T,CPU:1.7GHZ,DDR3:MICRON_2GB
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Labels / EEEE #’s
PART NUMBER
825-7563
825-7563
825-7563
825-7563
825-7563 CRITICAL
825-7563
825-7563
825-7563
825-7563 CRITICAL
825-7563 CRITICAL
825-7563
825-7563
QTY
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
LABEL,LIO,K99
REFERENCE DES
[EEEE_DP1F]
[EEEE_DP1G]
[EEEE_DP1H]
[EEEE_DP1J]
[EEEE_DP1K]
[EEEE_DP1L]
[EEEE_DP1M]
[EEEE_DP1N]
[EEEE_DP1P]
[EEEE_DP1Q]
[EEEE_DP1R]
[EEEE_DP1T]
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
EEEE:DP1F
EEEE:DP1G
EEEE:DP1H
EEEE:DP1J
EEEE:DP1K
EEEE:DP1L
EEEE:DP1M
EEEE:DP1N
EEEE:DP1P
EEEE:DP1Q
EEEE:DP1R
EEEE:DP1T
D
C
SIZE
B
A
D
B
A
SYNC_MASTER=MASTER
PAGE TITLE
Revision History
Sub BOM
PART NUMBER
QTY
1
1
DESCRIPTION
K21 MLB DEVELOPMENT
CMN PTS,PCBA,MLB,K21
8 7 5 4 2 1
REFERENCE DES
DEVEL
CMNPTS
CRITICAL
CRITICAL085-2684
CRITICAL607-8041
BOM OPTION
DEVEL_BOM
K21_CMNPTS
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
36
Apple Inc.
R
SYNC_DATE=MASTER
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
4 OF 109
SHEET
4 OF 75
Page 5
K21 BOM GROUPS
BOM GROUP
K21_COMMON
K21_MISC
K21_PROGPARTS
K21_DEVEL:ENG
K21_DEVEL:PVT
K21_DEBUG:ENG
D
K21_DEBUG:PVT
K21_DEBUG:PROD
DDR3:HYNIX_2GB
DDR3:HYNIX_4GB
DDR3:SAMSUNG_2GB
DDR3:SAMSUNG_4GB
DDR3:MICRON_2GB
DDR3:ELPIDA_4GB
Programmable Parts
PART NUMBER
C
341T0352 CRITICAL
337S3997
338S0895
341T0348
335S0809
341T0349
Alternate Parts
PART NUMBER
376S0855
376S0977
376S0972
377S0107
138S0676
371S0679 371S0652
138S0679
B
138S0671
337S4092
337S4093
353S3312
376S0790 376S0928
128S0333
152S1462
104S0035
152S1085
514-0744 998-3941
376S0874
138S0684
338S0721
152S1493
A
www.laptopblue.vn
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
ALTERNATE FOR
PART NUMBER
376S0613
376S0859
376S0612
377S0066
138S0691
138S0678
138S0673
337S4100
337S4101
353S3055
128S0294
152S1295
104S0011
152S1307
376S0895
138S0648138S0703
138S0660
338S0923
152S1300
QTY
1
1
1
1
1
1
1
1
1
DESCRIPTION
IC,EEPROM,SERIAL,SPI,1Kx8,1.8V,MLP8,LF
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
IC,SMC,RENESAS,H8S/2117RP,9MM,TLP,HF
64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix
64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx
IC,EFI ROM,K21 K78
BOM OPTION
BOM OPTIONS
ALTERNATE,COMMON,K21_MISC,K21_DEBUG:ENG,K21_PROGPARTS,USBHUB_2513B,T29BST:Y,EDP,PCH:B3
CPUMEM_S0,HUB1_2NONREM,HUB2_2NONREM,T29:YES,SDRVI2C:MCU,SDRV_PD,KB_BL
BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG
BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD
IC,T29-ROM,K21
IC,T29-MCU,K21
IC,SMC,K21
REF DES
COMMENTS:
Diodes alt to Toshiba
ALL
ALL
Diodes alt to Toshiba
Rohm alt to Toshiba
ALL
ALL
ONsemi alt to Semtech
ALL
Murata alt to Samsung
ALL
NXP alt to NXP
ALL
Murata/Samsung to Taiyo
ALL
Taiyo alt to Murata
ALL
EARLY 1.5GHZ CPU SAMPLES
EARLY 1.4GHZ CPU SAMPLES
ALL
NXP alt to Pericom
ALL
ALL
TI alt to Fairchild
ALL
Sanyo alt for Sanyo/Frederick
ALL
Toko alt for NEC inductor
Panasonic alt to Cyntec
ALL
Toko alt for Cyntec
ALL
ALL
Old J9400 alt to New J9400
ALL
FDMC0202S alt to RJK03E0DNS
Murata alt to Taiyo Yuden
ALL
Murata alt to Taiyo Yuden
ALL
SMSC USX2061 alt to USB2513B
ALL
ALL
Coilcraft alt to Murata
BOOTROM_PROG,SMC_PROG,T29ROM:PROG,T29MCU:PROG
LPCPLUS,XDP_CONN,XDP_PCH
DEVEL_BOM,SMC_DEBUG_YES,XDP
DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT
DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB
DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB
DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB
DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB
DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB
DRAM_CFG0:H,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB
REFERENCE DES
U3690
U3690
U9330
U9330
U4900
U4900
U6100
U6100
U6100
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL
CRITICAL335S0550
CRITICAL
CRITICAL341T0353
CRITICAL
CRITICAL
CRITICAL
CRITICAL335S0803
CRITICAL
BOM OPTION
T29ROM:BLANK
T29ROM:PROG
T29MCU:BLANK
T29MCU:PROG
SMC_BLANK
SMC_PROG
BOOTROM_BLANK
BOOTROM_BLANK
BOOTROM_PROG
8 7 5 4 2 1
Module Parts
PART NUMBER
337S4121
337S4119
337S4101
337S4100
337S4099
337S4098
337S4080
337S4091
338S0976
333S0585
333S0585
333S0585
333S0585
333S0586
333S0586
333S0586
333S0586
333S0587
333S0587
333S0587
333S0587
333S0588
333S0588
333S0588
333S0588
333S0590
333S0590
333S0590
333S0590
333S0589
333S0589
333S0589
333S0589
353s2929
QTY
PD Module Parts
806-2333
806-2356
806-2347
806-2376
806-2377
DRAM CFG CHART
VENDOR
HYNIX
SAMSUNG
MICRON
ELPIDA
SIZE
2GB
4GB
DESCRIPTION
1
SNB,QAYS,QS,J1,1.8,17W,2+2,1.20,4M,BGA
SNB,QAYM,QS,J1,1.7,17W,2+2,1.20,3M,BGA
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
SNB,QAM1,QS,J1,1.6,17W,2+2,1.1,4M,BGA
SNB,QAM2,QS,J1,1.5,17W,2+2,1.1,4M,BGA
SNB,QAM3,QS,J1,1.4,17W,2+2,1.05,3M,BGA
SNB,QALV,QS,J1,1.3,17W,2+2,1.05,3M,BGA
COUGAR POINT,SLHAG,PRQ,BD82QS67
COUGAR POINT,B3,SLJ4K,PRQ,BD82QS67
IC,T29 Eagle Ridge,192 FCBGA,8x9MM
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX
IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,T-DIE,HYNIX
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX
IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,B-DIE,HYNIX
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG
IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,G-DIE,SAMSUNG
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG
IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,D-DIE,SAMSUNG
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON
IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,V68A-D,MICRON
IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA
IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,C-DIE,ELPIDA
IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA
IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28
K21, T29 Fence
K21, T29 Can
K21, T29 Filter Can
K78, mDP Can
K78, mDP Spring
CFG 0CFG 1
0 0
1
0
1
CFG 2
0
1
1
0
1
DIE REV
A
B
345678
REFERENCE DES
U1000
U1000
U1000
U1000
U1000
U1000
U1800
U1800
U3600
U2900,U2910,U2920,U2930
U3000,U3010,U3020,U3030
U3100,U3110,U3120,U3130
U3200,U3210,U3220,U3230
U2900,U2910,U2920,U2930
U3000,U3010,U3020,U3030
U3100,U3110,U3120,U3130
U3200,U3210,U3220,U3230
U2900,U2910,U2920,U2930
U3000,U3010,U3020,U3030
U3100,U3110,U3120,U3130
U3200,U3210,U3220,U3230
U2900,U2910,U2920,U2930
U3000,U3010,U3020,U3030
U3100,U3110,U3120,U3130
U3200,U3210,U3220,U3230
U2900,U2910,U2920,U2930
U3000,U3010,U3020,U3030
U3100,U3110,U3120,U3130
U3200,U3210,U3220,U3230
U2900,U2910,U2920,U2930
U3000,U3010,U3020,U3030
U3100,U3110,U3120,U3130
U3200,U3210,U3220,U3230
U7000
T29FENCE
T29CAN
T29FILTERCAN
MDPCAN
MDPSPRING
CFG 3
0
1
36
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
DRAM_TYPE:HYNIX_2GB
DRAM_TYPE:HYNIX_2GB
DRAM_TYPE:HYNIX_2GB
DRAM_TYPE:HYNIX_2GB
DRAM_TYPE:HYNIX_4GB
DRAM_TYPE:HYNIX_4GB
DRAM_TYPE:HYNIX_4GB
DRAM_TYPE:HYNIX_4GB
DRAM_TYPE:SAMSUNG_2GB
DRAM_TYPE:SAMSUNG_2GB
DRAM_TYPE:SAMSUNG_2GB
DRAM_TYPE:SAMSUNG_2GB
DRAM_TYPE:SAMSUNG_4GB
DRAM_TYPE:SAMSUNG_4GB
DRAM_TYPE:SAMSUNG_4GB
DRAM_TYPE:SAMSUNG_4GB
DRAM_TYPE:MICRON_2GB
DRAM_TYPE:MICRON_2GB
DRAM_TYPE:MICRON_2GB
DRAM_TYPE:MICRON_2GB
DRAM_TYPE:ELPIDA_4GB
DRAM_TYPE:ELPIDA_4GB
DRAM_TYPE:ELPIDA_4GB
DRAM_TYPE:ELPIDA_4GB
2 1
CPU:1.8GHZ
CPU:1.7GHZ
CPU:1.6GHZ
CPU:1.5GHZ
CPU:1.4GHZ
CPU:1.3GHZ
PCH:B2
PCH:B3
T29:YES
NOSTUFF
NOSTUFF
SYNC_MASTER=K17_REF
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
BOM Configuration
Apple Inc.
R
SYNC_DATE=05/28/2009
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
5 OF 109
SHEET
5 OF 75
SIZE
D
C
B
A
D
Page 6
www.laptopblue.vn
345678
2 1
Functional Test Points
J4001: AirPort / BT Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
D
C
B
A
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
J4501: SATA SSD Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
J4800: SD Card Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
J5100: LPC+SPI Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_WLAN_F
WIFI_EVENT_L
PCIE_AP_R2D_N
PCIE_AP_R2D_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
USB_BT_P
USB_BT_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_WAKE_L
AP_RESET_CONN_L
AP_CLKREQ_Q_L
=PP3V3_S3_BT
(Need to add 8 GND TPs)
PP3V3_S0_HDD_R
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_R2D_N
SATA_HDD_R2D_P
SMC_HDD_OOB_TEMP_CONN
SMC_HDD_TEMP_CTL_CONN
(Need to add 6 GND TPs)
J4700: LIO Connector
=PP3V42_G3H_ONEWIRE
=PP3V3_S0_AUDIO
=PP3V3R1V5_S0_AUDIO
SYS_ONEWIRE
SMC_BC_ACOK
=USB_PWR_EN
SMC_LID
=I2C_LIO_SDA
=I2C_LIO_SCL
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
AUD_IPHS_SWITCH_EN
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
AUD_GPIO_3
SPKRAMP_INR_N
SPKRAMP_INR_P
USB_EXTD_N
USB_EXTD_P
USB_CAMERA_N
USB_CAMERA_P
HDA_SDOUT
HDA_BIT_CLK
HDA_SDIN0
USB_EXTD_OC_L
HDA_RST_L
HDA_SYNC
(Need to add 5 GND TPs)
PP3V3_SW_SD_PWR
SD_CLK
SD_CMD
SD_D<7..0>
SD_CD_L
SD_WP
(Need to add 2 GND TPs)
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_AD<3..0>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
LPC_CLK33M_LPCPLUS
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
(Need to add 6 GND TPs)
(Need 5 TPs)
37
41 37
70 37
70 37
70 37 16
70 37 16
69 37 24
69 37 24
70 37 16
70 37 16
37 17
37
37
37
7
(Need 5 TPs)
38
69 38
69 38
69 38
69 38
38
38
40
7
(Need 2 TPs)
40
7
40
7
41 40
42 41 40
62 40 39
49 42 41 40
6
44 40
44 40
44 40
44 40
40 19
40 18
40 18
51 40
74 51 40
74 51 40
69 40 24
69 40 24
69 40 18
69 40 18
70 40 16
70 40 16
70 40 16
40 24
70 40 16
70 40 16
33
33
33
33
33
33
43
7
43
7
70 43 41 16
43
43
70 43 41 16
43 41 17
43 42 41
43 25
43 42 41
43 41
43 41
43 42 41 39
70 43 25
50 43 19
43
43
43 41 16
43 41 17
43 42 41
43 42 41
53 43 42 41
43 41
43 42 41 39
43 19
I628
I629
I630
I631
I632
I633
I634
I636
I635
I638
I637
I639
I641
I640
I643
I642
I644
I646
I645
I648
I647
I649
I650
I651
I653
I652
I654
I655
I657
I656
I624
I623
J5600: Fan Connector
FUNC_TEST
TRUE
TRUE
TRUE
J5700: IPD Flex Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
J6900: DC-In Connector
FUNC_TEST
TRUE
TRUE
J6903: Speaker Connector
FUNC_TEST
TRUE
TRUE
J6950: Battery Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
J9000: Internal DP Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
=PP5V_S0_FAN
FAN_RT_TACH
FAN_RT_PWM
(Need to add 1 GND TP)
PP3V3_TPAD_CONN
PP5V_TPAD_FILT
=PP3V42_G3H_TPAD
USB_TPAD_CONN_P
USB_TPAD_CONN_N
=I2C_TPAD_SDA
=I2C_TPAD_SCL
SMC_ONOFF_L
SMC_LID
SMC_TPAD_RST_L
SMC_PME_S4_WAKE_L
(Need to add 5 GND TPs)
=PP18V5_DCIN_CONN
=PP5V_S3_LIO_CONN
(Need to add 5 GND TPs)
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
(Need to add 3 GND TPs)
PPVBAT_G3H_CONN
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SYS_DETECT_L
(Need to add 4 GND TPs near
J6950 and 1 for shield)
PPVOUT_SW_LCDBKLT
PP3V3_SW_LCD
I2C_TCON_SDA_R
I2C_TCON_SCL_R
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
DP_INT_HPD_CONN
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P
DP_INT_ML_F_P<0>
DP_INT_ML_F_N<0>
DP_INT_ML_F_P<1>
DP_INT_ML_F_N<1>
(Need to add 5 GND TPs)
Misc Voltages & Control Signals
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PPBUS_G3H
PPVIN_SW_T29BST
PPBUS_S5_HS_COMPUTING_ISNS
PPDCIN_G3H
PP3V42_G3H
PPVRTC_G3H
PP5V_S5
PP5V_SUS
PP3V3_S5
PP3V3_SUS
PP3V3_S3
PP1V8_S0
PP3V3_S0
PP1V5_S3
PP1V5_S3RS0
PP1V5_S0
PP1V05_S0
PPVTTDDR_S3
PP0V75_S0_DDRVTT
PPVCCSA_S0_CPU
PP1V05_SUS
PP15V_T29
PP3V3_T29
PP1V05_T29
PP1V05_S0_PCH_VCCADPLL
PPVCORE_S0_CPU
PPVCORE_S0_AXG
PP1V5_S3_CPU_VCCDQ
PP1V05_S0_CPU_VCCPQE
PP1V8_S0_CPU_VCCPLL_R
(Need to add 27 GND TPs)
48
7
48
48
49
49
49
7
74 49
74 49
49 44
49 44
49 42 41
49 42 41 40
6
49 42
49 42 41
(Need 6 TPs)
52
7
52
7
74 52 51
74 52 51
(Need 4 TPs)
53 52
52 44
52 44
52
(Need 2 TPs)
66 63
(Need 2 TPs)
63
63
63
66 63
66 63
66 63 18
66 63
66 63
66 63
63
70 63
70 63
70 63
70 63
70 63
70 63
52
7
36
7
7
7
7
7
7
7
74
7
7
7
7
74
7
68
7
68
7
7
7
7
7
7
7
7
7
36
7
7
7
7
7
7
7
16
16
16
18
I627
I626
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
16
16
16
16
16
8 7 5 4 2 1
J5715: KB BKLT CONNECTOR
FUNC_TEST
TRUE
TRUE
NO_TEST Nets
NO_TEST
TP_CRT_IG_BLUE
17
TP_CRT_IG_GREEN
17
TP_CRT_IG_RED
17
TP_CRT_IG_DDC_CLK
17
TP_CRT_IG_DDC_DATA
17
TP_CRT_IG_HSYNC
17
TP_CRT_IG_VSYNC
17
TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA
TP_PCH_LVDS_VBG
TP_PCI_PME_L
TP_PCI_CLK33M_OUT3
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
I593
I592
I595
I594
I596
I597
I598
I599
I600
I601
I602
TP_SDVO_TVCLKINN
17
TP_SDVO_TVCLKINP
17
TP_SDVO_STALLN
17
TP_SDVO_STALLP
17
TP_SDVO_INTN
17
TP_SDVO_INTP
17
TP_XDP_PCH_OBSFN_A<0..1>
23
TP_XDP_PCH_OBSFN_B<0..1>
23
TP_XDPPCH_HOOK2
23
TP_XDPPCH_HOOK3
23
TP_XDP_PCH_OBSFN_D<0..1>
23
TP_XDP_PCH_HOOK4
23
TP_XDP_PCH_HOOK5
23
TP_PCH_GPIO64_CLKOUTFLEX0
16
TP_PCH_GPIO65_CLKOUTFLEX1
16
TP_PCH_GPIO66_CLKOUTFLEX2
16
TP_PCH_GPIO67_CLKOUTFLEX3
16
KBDLED_FB
KBDLED_ANODE
(Need to add 2 GND TP)
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
XDP_PCH_AP_PWR_EN
TRUE
XDP_PCH_USB_HUB_SOFT_RST_L
TRUE
XDP_PCH_SDCONN_STATE_RST_L
TRUE
XDP_PCH_ENET_PWR_EN
TRUE
XDP_PCH_SDCONN_DET_L
TRUE
XDP_PCH_S5_PWRGD
TRUE
XDP_PCH_PWRBTN_L
TRUE
XDP_PCH_ISOLATE_CPU_MEM_L
TRUE
XDP_FW_CLKREQ_L
TRUE
XDP_AP_CLKREQ_L
TRUE
XDP_PCH_AUD_IPHS_SWITCH_EN
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
NC_LVDS_IG_CTRL_CLK
NC_LVDS_IG_CTRL_DATA
NC_PCH_LVDS_VBG
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
36
49
49
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
23
23
23
23
23
23
23
23
23
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
NC_SDVO_STALLN
NC_SDVO_STALLP
NC_SDVO_INTN
NC_SDVO_INTP
NC_TP_XDP_PCH_OBSFN_A<0..1>
NC_TP_XDP_PCH_OBSFN_B<0..1>
NC_TP_XDPPCH_HOOK2
NC_TP_XDPPCH_HOOK3
NC_TP_XDP_PCH_OBSFN_D<0..1>
NC_TP_XDP_PCH_HOOK4
NC_TP_XDP_PCH_HOOK5
NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3
NC_EDP_TXP<0..3>
MAKE_BASE=TRUE
NC_EDP_TXN<0..3>
MAKE_BASE=TRUE
NC_EDP_AUXP
MAKE_BASE=TRUE
NC_EDP_AUXN
MAKE_BASE=TRUE
NC_CPU_THERMDA
MAKE_BASE=TRUE
NC_CPU_THERMDC
MAKE_BASE=TRUE
NC_CPU_RSVD<30..45>
MAKE_BASE=TRUE
NC_CPU_RSVD<8..27>
MAKE_BASE=TRUE
NC_PEG_R2D_CP<15..4>
MAKE_BASE=TRUE
NC_PEG_R2D_CN<15..4>
MAKE_BASE=TRUE
NC_PEG_D2RP<15..4>
MAKE_BASE=TRUE
NC_PEG_D2RN<15..4>
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N
16
TP_PCIE_CLK100M_PE5P
16
TP_PCIE_CLK100M_PE6N
16
TP_PCIE_CLK100M_PE6P
16
TP_PCIE_CLK100M_PE7N
16
TP_PCIE_CLK100M_PE7P
16
TP_PSOC_P1_3
TP_SATA_B_D2RN
16
TP_SATA_B_D2RP
16
TP_SATA_B_R2D_CN
16
TP_SATA_B_R2D_CP
16
TP_SATA_D_D2RN
16
TP_SATA_D_D2RP
16
TP_SATA_D_R2D_CN
16
TP_SATA_D_R2D_CP
16
TP_SATA_E_D2RN
16
TP_SATA_E_D2RP
16
TP_SATA_E_R2D_CN
16
TP_SATA_E_R2D_CP
16
TP_SATA_F_D2RN
16
TP_SATA_F_D2RP
16
TP_SATA_F_R2D_CN
16
TP_SATA_F_R2D_CP
16
TP_PCH_TP18
TP_PCH_TP17
TP_PCH_TP16
TP_PCH_TP15
TP_PCH_TP14
TP_PCH_TP13
TP_PCH_TP12
TP_PCH_TP10
TP_PCH_TP9
TP_PCH_TP8
TP_PCH_TP7
TP_PCH_TP6
TP_PCH_TP5
TP_PCH_TP4
TP_PCH_TP3
TP_PCH_TP2
TP_PCH_TP1
PCH_VSS_NCTF<1>
TRUE
I566
I567
I568
I570
I571
I569
PCH_VSS_NCTF<2>
TRUE
PCH_VSS_NCTF<5>
TRUE
PCH_VSS_NCTF<9>
TRUE
PCH_VSS_NCTF<11>
TRUE
PCH_VSS_NCTF<12>
TRUE
TP_LVDS_IG_B_CLKN
8
TP_LVDS_IG_B_CLKP
8
TP_LVDS_IG_BKL_PWM
SYNC_MASTER=(K99_MLB)
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SMC_BS_ALRT_L
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
70
70
70
70
70
70
TRUE
MAKE_BASE=TRUE
TP_EDP_TX_P<0..3>
TP_EDP_TX_N<0..3>
TP_EDP_AUX_P
TP_EDP_AUX_N
TP_CPU_THERMDA
TP_CPU_THERMDC
TP_CPU_RSVD<30..45>
TP_CPU_RSVD<8..27>
=PEG_R2D_C_P<15..4>
=PEG_R2D_C_N<15..4>
=PEG_D2R_P<15..4>
=PEG_D2R_N<15..4>
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_B_D2RN
NC_SATA_B_D2RP
NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
NC_PCH_TP18
NC_PCH_TP17
NC_PCH_TP16
NC_PCH_TP15
NC_PCH_TP14
NC_PCH_TP13
NC_PCH_TP12
NC_PCH_TP10
NC_PCH_TP9
NC_PCH_TP8
NC_PCH_TP7
NC_PCH_TP6
NC_PCH_TP5
NC_PCH_TP4
NC_PCH_TP3
NC_PCH_TP2
NC_PCH_TP1
PCH_VSS_NCTF<15>
TRUE
I500
I499
I501
I502
I503
I504
I505
I506
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM
NC_SMC_BS_ALRT_L
SYNC_DATE=(02/16/2010)
Functional Test / No Test
Apple Inc.
R
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
7 OF 109
SHEET
9
9
9
9
9
9
3.13.0
6 OF 75
D
C
B
70
70
70
6
70
6
70
70
70
70
A
SIZE
D
Page 7
www.laptopblue.vn
=PPBUS_G3H
53
PPVIN_SW_T29BST
36
6
VOLTAGE=12.8V
=PPVIN_S5_HS_COMPUTING_ISNS
46
D
=PP18V5_DCIN_CONN
52
6
=PP3V42_G3H_REG
52
C
=PPVRTC_G3_OUT
25
=PP5V_S5_LDO
55
=PP5V_SUS_FET
61
B
=PP5V_S3_REG
55
=PP5V_S0_FET
61
A
"G3Hot" (Always-Present) Rails
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPBUS_S0_LCDBKLT
=PPBUS_S0_VSENSE
=PPVIN_SW_T29BST
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_P5VP3V3
PPBUS_S5_HS_COMPUTING_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_VCCSAS0
=PPVIN_S0_CPUAXG
PPDCIN_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPDCIN_S5_CHGR
=PPDCIN_S5_VSENSE
PP3V42_G3H
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_CHGR
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
=PP3V42_G3H_ONEWIRE
PPVRTC_G3H
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE
=PPVRTC_G3_PCH
5V Rails
PP5V_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S5_P1V5DDRFET
=PP5V_S5_P5VSUSFET
=PP5V_S5_TPAD
PP5V_SUS
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP5V_SUS_PCH
PP5V_S3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_AUDIO_AMP
=PP5V_S3_DDRREG
=PP5V_S3_MEMRESET
=PP5V_S3_P5VS0FET
=PP5V_S3_RTUSB
=PP5V_S3_LIO_CONN
PP5V_S0
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN
=PP5V_S0_LPCPLUS
=PP5V_S0_VCCSA
=PP5V_S0_PCH
=PP5V_S0_VMON
=PP5V_S0_KBDLED
52
6
66
45
36
8
46
55
6
56
59
54
58
6
53
45
6
43
6
53
62
44
39
49
6
42
25
40
6
6
6
61
61
49
6
22
51
56
26
61
39
52
6
66
57
59
48
6
43
6
54
22
62
49
58 57
42 41
20 17 16
=PP3V3_S5_REG
55
=PP3V3_SUS_FET
61
=PP3V3_S3_FET
61
=PP3V3_S0_FET
61
3.3V Rails
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP3V3_S5
=PP3V3_S5_XDP
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S5_LCD
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_SMCBATLOW
=PP3V3_S5_ROM
=PP3V3_S5_USB_RESET
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_PWRCTL
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S5_P3V3SUSFET
=PP3V3_S5_TPAD
=PP3V3_S4_DPAPWRSW
=PP3V3_S4_SMC
PP3V3_SUS
=PP3V3_SUS_PCH_VCCSUS_USB
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_GPIO
=PP3V3_SUS_PCH
=PP3V3_SUS_PWRCTL
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_SMC
PP3V3_S3
=PP3V3_S3_BT
=PP3V3_S3_CARDREADER
=PP3V3_S3_MEMRESET
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_WLANISNS
=PP3V3_S3_BMON_ISNS
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_1V5S3ISNS
=PP3V3_S3_DBGLEDS
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
=PP3V3_S0_CPUVCCIOISNS
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_HS_COMPUTING_ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_CPU_VCCIO_SEL
=PP3V3_S0_DP_DDC
=PP3V3_S0_FAN
=PP3V3_S0_P3V3T29FET
=PP3V3_S0_P1V8S0
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_STRAPS
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMC
=PP3V3_S0_HDD
=PP3V3_S0_HDDISNS
=PP3V3_S0_VMON
=PP3V3_S0_P1V5S0
=PP3V3_S0_T29PWRCTL
=PP3V3_S0_DPSDRVA
=PP3V3_S0_P1V05S0LDO
=PP3V3_S0_IMVPISNS
=PP3V3_S0_XDP
=PP3V3_S0_T29I2C
=PP3V3_S0_BKLTISNS
=PP3V3_S0_SYSCLKGEN
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
74
6
23
61
61
26
63
19 17
25
42
50
24
22 20
25
62
62
22 20
61
49
65
42
6
22 20
22 20
20
22
62
60
42
6
37
6
33
26
44
44
24
8
24
31
37
46
46
19 18
46
52
74
6
45
40
6
66
46
47
12
8
48
36
60
22 19 16
18
22
22 20
22 20
22 20
22 20
22
19 17 16
62
25
25
44
44
44
42
38
46
62
60
36
64
60
45
23
44
46
25
19 18 17 16
=PP1V8_S0_REG
60
2A max supply
=PPDDR_S3_REG
56
=PP1V5_S3RS0_FET
61
=PP1V5_S0_REG
60
=PPVTT_S3_DDR_BUF
56 31
=PPVTT_S0_DDR_LDO
56
=PPVCCSA_S0_REG
54
=PP1V05_SUS_LDO
60
=PPCPUVCCIO_S0_REG
59
? mA
8 7 5 4 2 1
1.8V/1.5V/1.2V/1.05V Rails
PP1V8_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_S0_CPU_VCCPLL
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_P1V05S0LDO
=PP1V8R1V5_S0_PCH_VCCVRM
=PPVDDIO_S0_SBCLK
=PP1V8_S0_P1V5S0
PP1V5_S3
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_P1V5S3RS0_FET
=PPVIN_S0_DDRREG_LDO
PP1V5_S3RS0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_CPU_VCCDDR
=PP1V5_S3RS0_VMON
PP1V5_S0
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP3V3R1V5_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA
PPVTTDDR_S3
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
PP0V75_S0_DDRVTT
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
PPVCCSA_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCCSA_S0_CPU
PP1V05_SUS
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_SUS_PCH_JTAG
PP1V05_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_CPU_VCCIO
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_VMON
=PP1V05_S0_PCH_VCCIO_CLK
=PPVCCIO_S0_CPUIMVP
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
=PPVCCIO_S0_XDP
=PPVCCIO_S0_SMC
=PP1V05_S0_P1V05T29FET
345678
6
14
22 20 18
60
20
25
60
68
6
26
32 28 27
32 30 29
61
56
68
6
26 15 12 10
62
6
40
6
22 20 16
6
6
32
32
26
15 12
6
14 12
15 12
6
14 12
23
6
20
14 12 10
9
22 16
22 20
17
22 20 16
22 20
22 20
22 20
62
22 20
57
22 20 16
22 20
22 20
20
22 20
20
20
23
41
36
=PP15V_T29_REG
36
8
=PP3V3_T29_FET
36
=PP1V05_T29_FET
36
=PP1V05_S0_LDO
60
=PPVCORE_S0_CPU_REG
58
=PPVCORE_S0_AXG_REG
58
=PP1V5_S3_CPU_VCCDQ
=PP1V05_S0_CPU_VCCPQE
=PP1V8_S0_CPU_VCCPLL_R
36
2 1
T29 Rails (off when no cable)
PP15V_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE
=PPHV_SW_DPAPWRSW
PP3V3_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PPVDDIO_T29_CLK
=PP3V3_T29_RTR
=PP3V3_T29_PCH_GPIO
PP1V05_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_T29_RTR
1V05 S0 LDO
PP1V05_S0_PCH_VCCADPLL
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCADPLL
Chipset "VCore" Rails
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU
=PPCPUVCORE_S0_VSENSE
PPVCORE_S0_AXG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU_VCCAXG
=PPGFXVCORE_S0_VSENSE
PP1V5_S3_CPU_VCCDQ
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
PP1V05_S0_CPU_VCCPQE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP1V8_S0_CPU_VCCPLL_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
SYNC_MASTER=K91_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Power Aliases
Apple Inc.
R
6
65
6
25
6
35
6
20
SYNC_DATE=05/15/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
8 OF 109
SHEET
7 OF 75
D
36 35 34
19 16
36
6
14 12
9
45
6
9
45
6
6
6
C
15 12
B
A
SIZE
D
Page 8
www.laptopblue.vn
345678
2 1
=PEG_R2D_C_P<3..0>
CPU signals
MEMVTT_EN
Plated Board Slot
SL0900
TH-NSP
1
SL-2.3X3.9-2.9X4.5
D
STDOFF-4.5OD1.8H-SM
C
DisplayPort Pogo
CPU Heat Sink Mounting Bosses
Z0913
STDOFF-4.5OD1.8H-SM
STDOFF-4.5OD1.8H-SM
Fan Boss
Z0905
1
Z0911
1
1
4x 860-1327
X21 Boss
STDOFF-4.5OD1.9H-SM
1
Z0914
860-1327860-1327
EMI I/O Pogo Pins
CRITICAL
ZS0905
POGO-2.0OD-3.6H-K86-K87
SM
1
870-1938
Z0910
STDOFF-4.5OD1.8H-SM
1
Z0912
STDOFF-4.5OD1.8H-SM
1
USB/SD Card Pogo
POGO-2.0OD-3.6H-K86-K87
SSD Boss
Z0915
STDOFF-4.5OD1.9H-SM
1
860-1327
CRITICAL
ZS0906
SM
1
870-1938
DP_EXTA_ML_C_P<3..0>
70 64
MAKE_BASE=TRUE
DP_EXTA_ML_C_N<3..0>
70 64
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_P
70 64
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_N
70 64
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_N
16
PCIE_EXCARD_D2R_P
16
PCIE_EXCARD_R2D_C_N
16
PCIE_EXCARD_R2D_C_P
16
PCIE_CLK100M_EXCARD_N
70 16
PCIE_CLK100M_EXCARD_P
70 16
PEG_CLK100M_P
70 16
PEG_CLK100M_N
70 16
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68
11
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
16
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>
MEM_A_A<15>
MEM_B_A<15>
MAKE_BASE=TRUE
69
69
69
69
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DPLL_REF_CLK_N
DPLL_REF_CLK_P
DisplayPort PCB Stiffener
(Provides PCB support for small finger above J9400)
NO STUFF
MT0900
STIFFENER-K16-K99
SM-SP
1
806-1176
B
Digital Ground
GND
VOLTAGE=0V
MIN_NECK_WIDTH=0.075MM
MIN_LINE_WIDTH=0.6MM
=PPVIN_SW_T29BST
36
7
T29_A_BIAS
65 64
C0960
0.01UF
1
10%
10V
2
X5R
201
T29BST:N
R0960
0
1 2
5%
1/8W
MF-LF
805
T29_A_BIAS_R
65
8
=PP15V_T29_REG
T29_A_BIAS caps
SIGNAL_MODEL=EMPTY
T29 Can Slots
SIGNAL_MODEL=EMPTY
SL0901
TH-NSP
1
SL-1.1X0.4-1.4X0.7
SL0903
TH-NSP TH-NSP
1
SL0905
TH-NSP
A
1
SL-1.1X0.45-1.4X0.75 SL-1.1X0.45-1.4X0.75
SL0902
TH-NSP
1
SL-1.1X0.4-1.4X0.7
SL0904
1
SL-1.1X0.45-1.4X0.75SL-1.1X0.45-1.4X0.75
SL0906
TH-NSP
1
65
8
T29_A_BIAS_R
65
8
T29_A_BIAS_R
65
8
T29_A_BIAS_R
SIGNAL_MODEL=EMPTY
R0933
1 2
SIGNAL_MODEL=EMPTY
R0934
1 2
1/20W
1 2
=DDRVTT_EN
TP_DP_IG_B_MLP<3..0>
TP_DP_IG_B_MLN<3..0>
DP_IG_B_AUX_P
DP_IG_B_AUX_N
NC_PCIE_EXCARD_D2RN
NC_PCIE_EXCARD_D2RP
NC_PCIE_EXCARD_R2D_CN
NC_PCIE_EXCARD_R2D_CP
NC_PCIE_CLK100M_EXCARDN
NC_PCIE_CLK100M_EXCARDP
NC_PEG_CLK100MP
NC_PEG_CLK100MN
TP_MEM_A_CLKP<1>
TP_MEM_A_CLKN<1>
NC_MEM_A_CKE<1>
NC_MEM_A_CS_L<1>
NC_MEM_A_ODT<1>
TP_MEM_B_CLKP<1>
TP_MEM_B_CLKN<1>
NC_MEM_B_CKE<1>
NC_MEM_B_CS_L<1>
NC_MEM_B_ODT<1>
TP_MEM_A_A<15>
TP_MEM_B_A<15>
DPLL_REF_CLKN
DPLL_REF_CLKP
7
R0931
51
1 2
T29_A_BIAS_R2DP0
5%
1
1/20W
201
R0932
51
5%
1/20W
MF
201
51
5%
1/20W
MF
201
51
5%
MF
201
MF
C0901
0.01UF
10%
SIGNAL_MODEL=EMPTY
10V
2
X5R
201
T29_A_BIAS_R2DN0
1
C0902
0.01UF
10%
10V
SIGNAL_MODEL=EMPTY
2
X5R
201
T29_A_BIAS_R2DP1
1
C0903
0.01UF
10%
SIGNAL_MODEL=EMPTY
10V
2
X5R
201
T29_A_BIAS_R2DN1
1
C0904
0.01UF
10%
SIGNAL_MODEL=EMPTY
10V
2
X5R
201
56 26 26
17
17
17
17
TP_DP_IG_C_CTRL_CLK
17
TP_DP_IG_C_CTRL_DATA
17
TP_DP_IG_D_CTRL_CLK
17
TP_DP_IG_D_CTRL_DATA
17
DP_EXTA_DDC_CLK
64
MAKE_BASE=TRUE
DP_EXTA_DDC_DATA
64
MAKE_BASE=TRUE
DP_EXTA_HPD
64
MAKE_BASE=TRUE
67 10
67 10
PPBUS_SW_LCDBKLT_PWR
66
MAKE_BASE=TRUE
74 46
74 46
ISNS_LCDBKLT_P
OUT
ISNS_LCDBKLT_N
OUT
NC_USB_HUB1_OCS4
MAKE_BASE=TRUE
NC_USB_HUB2_OCS4
MAKE_BASE=TRUE
R0908
100K
1/20W
1
5%
MF
201
2
8 7
8 7
CRITICAL
R0910
0.01
0.5%
1W MF
0612-1
1 2
3 4
=PP3V3_S0_DP_DDC
R0920
2.2K 2.2K
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=PP3V3_S0_DP_DDC
DP_IG_B_DDC_CLK
DP_IG_B_DDC_DATA
DP_IG_B_HPD
T29_A_BIAS caps
SIGNAL_MODEL=EMPTY
R0926
51
T29_A_BIAS_R
65
8
36
T29_A_BIAS_R
65
8
64
64
64
64
64
1 2
1/20W
SIGNAL_MODEL=EMPTY
R0927
1 2
1/20W
C0962
0.01UF
10%
10V
X5R
201
DP_A_BIAS_N_2
24
5%
MF
201
51
5%
MF
201
DP_A_BIAS caps
1
2
1
C0905
0.01UF
10%
10V
2
X5R
201
T29 Aliases
Unused USB ports
=PP3V3_S3_USB_HUB
7
NO STUFF
R0917
69 64
T29_A_RSVD_N
T29_A_RSVD_P
R0918
201
1/20W
201
1/20W
9
9
9
9
1
R0921
5%
1/20W
R0924
1/20W
MF
201
2
DP_IG_C_CTRL_CLK
DP_IG_C_CTRL_DATA
DP_IG_D_CTRL_CLK
DP_IG_D_CTRL_DATA
1
R0925
2.2K
5%
1/20W
MF
201
2
PPBUS_SW_BKL
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPBUS_SW_BKL
201
=USB_HUB1_OCS4
=USB_HUB2_OCS4
T29_A_BIAS_D2RP1
1
C0906
0.01UF
10%
SIGNAL_MODEL=EMPTY
10V
2
X5R
201
T29_A_BIAS_D2RN1
1
C0907
0.01UF
10%
10V
SIGNAL_=EMPTY
2
X5R
201
DP_A_BIAS_P_0DP_A_BIAS_P_2
64 64
C0964
0.01UF
DP_A_BIAS_N_0
64
SIGNAL_MODEL=EMPTYSIGNAL_MODEL=EMPTY
R0915
0
1 2
5%
0
1 2
MF
5%
MF
=PEG_R2D_C_N<3..0>
=PEG_D2R_P<3..0>
=PEG_D2R_N<3..0>
5%
MF
2.2K
10K
1/20W
1
2
1/20W
10%
10V
X5R
201
201
5%
MF
201
5%
MF
R0922
2.2K
1
2
1
2
1
2
1
2
1/20W
201
17
17
17
C0908
0.01UF
10%
10V
X5R
201
1
2
1
5%
MF
2
65
65
R0916
10K
5%
1/20W
MF
201
USB_T29A_N
USB_T29A_P
R0923
2.2K
1/20W
66
24
24
5%
MF
201
NO STUFF
8 7 5 4 2 1
36
PEG_R2D_C_P<3..0>
67
PEG_R2D_C_N<3..0>
67
PEG_D2R_P<3..0>
67
PEG_D2R_N<3..0>
67
TP_DP_IG_C_HPD
17
1
2
TP_DP_IG_C_MLP<3..0>
17
TP_DP_IG_C_MLN<3..0>
17
TP_DP_IG_C_AUXP
17 72 34
TP_DP_IG_C_AUXN
17
TP_DP_IG_D_HPD
17
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
T29 DP Ports
MAKE_BASE=TRUE
LVDS Aliases
TP_LVDS_IG_B_CLKP
6
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKN
6
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAP<0..3>
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<0..3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
LCD_BKLT_PWM
MAKE_BASE=TRUE
LCD_IG_PWR_EN
MAKE_BASE=TRUE
LCD_BKLT_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
SATA Aliases
Unused SATA ODD Signals
69 16
69 16
69 16
69 16
SATA_ODD_R2D_C_P
IN
SATA_ODD_R2D_C_N
IN
SATA_ODD_D2R_P
OUT
SATA_ODD_D2R_N
OUT
Unused PGOOD signal
TP_P1V5S3RS0_RAMP_DONE
MAKE_BASE=TRUE
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
23 19
19
19
69 24
69 24 69 64
IN
IN
OUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
JTAG_ISP_TCK
JTAG_ISP_TDI
JTAG_ISP_TDO
SYNC_MASTER=K91_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
JTAG_T29_TCK_R
PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_T29SNK0_HPD
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
DP_IG_D_HPD
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<0..3>
LVDS_IG_B_DATA_N<0..3>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_BKL_PWM
LVDS_IG_PANEL_PWR
LVDS_IG_BKL_ON
NC_SATA_ODD_R2DCP
MAKE_BASE=TRUE
NC_SATA_ODD_R2DCN
MAKE_BASE=TRUE
NC_SATA_ODD_D2RP
MAKE_BASE=TRUE
NC_SATA_ODD_D2RN
MAKE_BASE=TRUE
P1V5S3RS0_RAMP_DONE
DDRREG_PGOOD
T29 JTAG
JTAG_T29_TDI
JTAG_T29_TDO
Signal Aliases
Apple Inc.
R
R0990
0
1 2
5%
1/20W
MF
201
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
JTAG_T29_TCK
1
R0909
100K
5%
1/20W
MF
201
2
69
69
69
69
69
69
17 66
17 63
17 66
61
IN
56
IN
OUT
OUT
IN
SYNC_DATE=05/15/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
9 OF 109
SHEET
8 OF 75
70 34
70 34
70 34
70 34
34
72 34
72 34
D
72 34
C
B
34
34
34
A
SIZE
D
Page 9
www.laptopblue.vn
345678
2 1
67 17
67 17
67 17
67 17
D
C
=PP1V05_S0_CPU_VCCIO
14
9 7
10 12
R1030
24.9
1 2
1%
1/20W
MF
201
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
67 17
PLACE_NEAR=U1000.AF3:12.7MM
B
Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation.
NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are
shared with other interfaces.
NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor
(refer to latest Processor EDS for DC specifications).
If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.
DMI_S2N_N<0>
IN
DMI_S2N_N<1>
IN
DMI_S2N_N<2>
IN
DMI_S2N_N<3>
IN
DMI_S2N_P<0>
IN
DMI_S2N_P<1>
IN
DMI_S2N_P<2>
IN
DMI_S2N_P<3>
IN
DMI_N2S_N<0>
OUT
DMI_N2S_N<1>
OUT
DMI_N2S_N<2>
OUT
DMI_N2S_N<3>
OUT
DMI_N2S_P<0>
OUT
DMI_N2S_P<1>
OUT
DMI_N2S_P<2>
OUT
DMI_N2S_P<3>
OUT
FDI_DATA_N<0>
OUT
FDI_DATA_N<1>
OUT
FDI_DATA_N<2>
OUT
FDI_DATA_N<3>
OUT
FDI_DATA_N<4>
OUT
FDI_DATA_N<5>
OUT
FDI_DATA_N<6>
OUT
FDI_DATA_N<7>
OUT
FDI_DATA_P<0>
OUT
FDI_DATA_P<1>
OUT
FDI_DATA_P<2>
OUT
FDI_DATA_P<3>
OUT
FDI_DATA_P<4>
OUT
FDI_DATA_P<5>
OUT
FDI_DATA_P<6>
OUT
FDI_DATA_P<7>
OUT
FDI_FSYNC<0>
IN
FDI_FSYNC<1>
IN
FDI_INT
IN
FDI_LSYNC<0>
IN
FDI_LSYNC<1>
IN
EDP_COMP
67
EDP_HPD_L
9
DP_INT_AUX_CH_N
70 63
DP_INT_AUX_CH_P
70 63
DP_INT_ML_N<0>
70 63
DP_INT_ML_N<1>
70 63
TP_EDP_TX_N<2>
6
TP_EDP_TX_N<3>
6
DP_INT_ML_P<0>
70 63
DP_INT_ML_P<1>
70 63
TP_EDP_TX_P<2>
6
TP_EDP_TX_P<3>
6
M2
DMI_RX_0*
P6
DMI_RX_1*
P1
DMI_RX_2*
P10
DMI_RX_3*
N3
DMI_RX_0
P7
DMI_RX_1
P3
DMI_RX_2
P11
DMI_RX_3
K1
DMI_TX_0*
M8
DMI_TX_1*
N4
DMI_TX_2*
R2
DMI_TX_3*
K3
DMI_TX_0
M7
DMI_TX_1
P4
DMI_TX_2
T3
DMI_TX_3
U7
FDI0_TX_0*
W11
FDI0_TX_1*
W1
FDI0_TX_2*
AA6
FDI0_TX_3*
W6
FDI1_TX_0*
V4
FDI1_TX_1*
Y2
FDI1_TX_2*
AC9
FDI1_TX_3*
U6
FDI0_TX_0
W10
FDI0_TX_1
W3
FDI0_TX_2
AA7
FDI0_TX_3
W7
FDI1_TX_0
T4
FDI1_TX_1
AA3
FDI1_TX_2
AC8
FDI1_TX_3
AA11
FDI0_FSYNC
AC12
FDI1_FSYNC
U11
FDI_INT
AA10
FDI0_LSYNC
AG8
FDI1_LSYNC
AD2
EDP_ICOMPO
AF3
EDP_COMPIO
FIXME: Pin should be EDP_HPD*
AG11
EDP_HPD
AG4
EDP_AUX*
AF4
EDP_AUX
AC3
EDP_TX_0*
AC4
EDP_TX_1*
AE11
EDP_TX_2*
AE7
EDP_TX_3*
AC1
EDP_TX_0
AA4
EDP_TX_1
AE10
EDP_TX_2
AE6
EDP_TX_3
OMIT_TABLE
CRITICAL
U1000
SANDY-BRIDGE
MOBILE-2C-35W
BGA
(1 OF 9)
DMI
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
PCI EXPRESS BASED INTERFACE SIGNALS
EMBEDDED DISPLAY PORT
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
CPU_PEG_COMP
67
PLACE_NEAR=U1000.G3:12.7MM
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>
=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>
R1010
24.9
1 2
1%
1/20W
MF
201
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
=PP1V05_S0_CPU_VCCIO
8
8
8
8
6
6
6
6
6
6
6
6
6
6
6
6
8
8
8
8
6
6
6
6
6
6
6
6
6
6
6
6
doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.
8
8
8
8
6
6
6
6
6
6
6
6
6
6
6
6
8
8
8
8
6
6
6
6
6
6
6
6
6
6
6
6
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_VCCAXG
NOSTUFF
R1064
49.9
NOSTUFF
R1065
49.9
NOTE: Intel validation sense lines per
NOSTUFF
1
1
R1070
49.9
1%
1%
1/20W
1/20W
MF
MF
201
201
2
2
PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
NOSTUFF
1
1
R1071
49.9
1%
1%
1/20W
1/20W
MF
MF
201
201
2
2
PLACE_NEAR=U1000.K45:50.8MM
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.K43:50.8MM
PLACE_SIDE=BOTTOM
9 7
7
NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.
14 12 10
14 12
67 23
67 23
67 23
67 23
67 23
67 23
67 23
67 23
15 12
7
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
67 23
67 23
67 23
67 23
67 23
67 23
67 23
23
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
IN
IN
IN
IN
23
IN
67
IN
IN
IN
9
IN
23
IN
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>
TP_CPU_VCC_DIE_SENSE
CPU_THERMD_P
74 47
OUT
CPU_THERMD_N
47 74
OUT
NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.
This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core
to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.
68 31 30 29 28 27
PP0V75_S3_MEM_VREFDQ_A
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
H43
K43
H45
K45
F48
H48
K48
BA19
NC
AV19
NC
AT21
NC
BB21
NC
BB19
NC
AY21
NC
BA22
NC
AY22
NC
AU19
NC
AU21
NC
BD21
NC
BD22
NC
BD25
NC
BD26
NC
BG22
NC
BE22
NC
BG26
NC
BE26
NC
BF23
NC
BE24
NC
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_DIE_SENSE
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
OMIT_TABLE
CRITICAL
U1000
NOSTUFF
R1021
0
1 2
5%
1/20W
MF
201
BGA
(5 OF 9)
RESERVED
SANDY-BRIDGE
MOBILE-2C-35W
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
NOSTUFF
1
R1020
1K
1%
1/20W
MF
201
2
BE7
RSVD_28
BG7
RSVD_29
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38
RSVD_39
RSVD_40
RSVD_41
RSVD_42
RSVD_43
RSVD_44
RSVD_45
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
N42
L42
L45
L47
M13
M14
U14
W14
P13
AT49
K24
AH2
AG13
AM14
AM15
N50
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CPU_MEM_VREFDQ_A
CPU_MEM_VREFDQ_A
TP_CPU_DC_TEST_A4
CPU_DC_TEST_C4_D3
TP_CPU_DC_TEST_D1
TP_CPU_DC_TEST_A58
CPU_DC_TEST_C59_A59
CPU_DC_TEST_C61_A61
TP_CPU_DC_TEST_D61
TP_CPU_DC_TEST_BD61
CPU_DC_TEST_BE59_BE61
CPU_DC_TEST_BG59_BG61
TP_CPU_DC_TEST_BG58
TP_CPU_DC_TEST_BG4
CPU_DC_TEST_C4_BE3_BG3
CPU_DC_TEST_C4_BE1_BG1
TP_CPU_DC_TEST_BD1
9
9
D
C
B
CPU_CFG<16>
23
CPU_CFG<7>
23
9
67
CPU_CFG<6>
67 23
9
CPU_CFG<5>
67 23
9
CPU_CFG<4>
67 23
9
CPU_CFG<2>
67 23
9
R1042
EDP
1
1
R1044
1K
5%
1/16W
1/16W
MF-LF
MF-LF
402
2
1
R1045
1K
1K
5%
5%
1/16W
MF-LF
402
402
2
2
NOSTUFF
A
NOSTUFFNOSTUFF
R1046
NOSTUFF
1
1
R1047
1K
1K
5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
402
2
2
FOR SANDYBRIDGE PROCESSOR
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
8 7 5 4 2 1
9
CPU_CFG<3>
67 23
9
CPU_CFG<1>
23
9
67
CPU_CFG<0>
67 23
9
NOSTUFF
R1040
These can be Placed close to J2500 and Only for debug access
1
1K
5%
1/16W
MF-LF
402
2
NOSTUFF NOSTUFF
1
R1041
R1043
1K
5%
1/16W
MF-LF
402
2
1K
5% 5%
1/16W
MF-LF
402
=PP1V05_S0_CPU_VCCIO
14 12 10
9 7
NOSTUFF
1
2
R1049
1
1K
1/16W
MF-LF
402
2
DP_INT_HPD
63
Q1031
SSM3K15FV
SOD-VESM-HF
1
G S
PLACE_NEAR=U1000.AG11:12.7MM
1
R1031
1K
5%
1/20W
MF
201
2
EDP_HPD_L
3
D
2
9
SIZE
A
D
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
10 OF 109
SHEET
9 OF 75
36
Page 10
www.laptopblue.vn
345678
2 1
D
=PP1V05_S0_CPU_VCCIO
14 12 10
9 7
NOSTUFF NOSTUFF
1
R1100
1
R1101
62
5%
1/20W
MF
201
2
C
R1103
56
67 57 42
=PP1V5_S3_CPU_VCCDDR
26 15 12
7
67 26 17
IN
=PP1V05_S0_CPU_VCCIO
14 12 10
9 7
B
CPU_RESET_L
25 23
IN
CPU_PROCHOT_L
BI
PM_MEM_PWRGD
R1120
200
1/20W
1
1%
MF
201
2
R1126
1/20W
1
75
1%
MF
201
2
1 2
5%
1/20W
MF
201
R1121
1 2
R1125
1 2
130
1/20W
201
43.2
1/20W
201
CPU_PROCHOT_R_L
1%
MF
1%
MF
67 41 19
67 19
67 17
67 23 19
18
OUT
67
OUT
BI
OUT
IN
IN
26
OUT
PM_MEM_PWRGD_R
1K
5%
1/20W
MF
201
2
CPU_PROC_SEL_L
CPU_CATERR_L
CPU_PECI
PM_THRMTRIP_L
PM_SYNC
CPU_PWRGD
PLT_RESET_LS1V1_L
=MEM_RESET_L
1
1
R1113
R1112
25.5140
1%
1%
1/20W
1/20W
MF
MF
201
201
2
2
NOSTUFF
1
R1104
51
5%
1/20W
MF
201
2
CPU_SM_RCOMP<0>
67
CPU_SM_RCOMP<1>
67
CPU_SM_RCOMP<2>
67
1
R1114
200
1%
1/20W
MF
201
2
1
R1115
4.99K
1%
1/20W
MF
201
2
NOSTUFF
1
R1102
1K
5%
1/20W
MF
201
2
1
R1111
10K
5%
1/20W
MF
201
2
C57
NC
F49
C49
A48
C45
D45
C48
B46
BE45
D44
AT30
BF44
BE43
BG43
PROC_DETECT*
PROC_SELECT*
CATERR*
PECI
PROCHOT*
THERMTRIP*
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET*
SM_DRAMRST*
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
OMIT_TABLE
CRITICAL
U1000
SANDY-BRIDGE
MOBILE-2C-35W
BGA
(2 OF 9)
THERMAL
PWR MGMT
DDR3 MISC
DPLL_REF_CLK
DPLL_REF_CLK*
BCLK_ITP
CLOCKS
BCLK_ITP*
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
JTAG & BPM
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
BCLK
BCLK*
PRDY*
PREQ*
TRST*
DBR*
BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*
TCK
TMS
TDI
TDO
J3
H2
AG3
AG1
N59
N58
N53
N55
L56
L55
J58
M60
L59
K58
G58
E55
E59
G55
G59
H60
J59
J61
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
DPLL_REF_CLKP
DPLL_REF_CLKN
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TDO
XDP_DBRESET_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
67 16
IN
67 16
IN
67
8
IN
67
8
IN
67 16
IN
67 16
IN
67 23
OUT
67 23
IN
67 23
IN
67 23
IN
67 23
IN
67 23
IN
67 23
OUT
67 25 23
OUT
67 23
BI
67 23
BI
67 23
BI
67 23
BI
67 23
BI
67 23
BI
67 23
BI
67 23
BI
D
C
B
A
8 7 5 4 2 1
36
PAGE TITLE
CPU CLOCK/MISC/JTAG
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
11 OF 109
SHEET
10 OF 75
SIZE
A
D
Page 11
www.laptopblue.vn
345678
2 1
OMIT_TABLE
CRITICAL
MEM_A_DQ<0>
68 27
BI
MEM_A_DQ<1>
68 27
BI
MEM_A_DQ<2>
68 27
BI
MEM_A_DQ<3>
68 27
BI
MEM_A_DQ<4>
68 27
D
C
B
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 27
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 28
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
BI
MEM_A_DQ<5>
BI
MEM_A_DQ<6>
BI
MEM_A_DQ<7>
BI
MEM_A_DQ<8>
BI
MEM_A_DQ<9>
BI
MEM_A_DQ<10>
BI
MEM_A_DQ<11>
BI
MEM_A_DQ<12>
BI
MEM_A_DQ<13>
BI
MEM_A_DQ<14>
BI
MEM_A_DQ<15>
BI
MEM_A_DQ<16>
BI
MEM_A_DQ<17>
BI
MEM_A_DQ<18>
BI
MEM_A_DQ<19>
BI
MEM_A_DQ<20>
BI
MEM_A_DQ<21>
BI
MEM_A_DQ<22>
BI
MEM_A_DQ<23>
BI
MEM_A_DQ<24>
BI
MEM_A_DQ<25>
BI
MEM_A_DQ<26>
BI
MEM_A_DQ<27>
BI
MEM_A_DQ<28>
BI
MEM_A_DQ<29>
BI
MEM_A_DQ<30>
BI
MEM_A_DQ<31>
BI
MEM_A_DQ<32>
BI
MEM_A_DQ<33>
BI
MEM_A_DQ<34>
BI
MEM_A_DQ<35>
BI
MEM_A_DQ<36>
BI
MEM_A_DQ<37>
BI
MEM_A_DQ<38>
BI
MEM_A_DQ<39>
BI
MEM_A_DQ<40>
BI
MEM_A_DQ<41>
BI
MEM_A_DQ<42>
BI
MEM_A_DQ<43>
BI
MEM_A_DQ<44>
BI
MEM_A_DQ<45>
BI
MEM_A_DQ<46>
BI
MEM_A_DQ<47>
BI
MEM_A_DQ<48>
BI
MEM_A_DQ<49>
BI
MEM_A_DQ<50>
BI
MEM_A_DQ<51>
BI
MEM_A_DQ<52>
BI
MEM_A_DQ<53>
BI
MEM_A_DQ<54>
BI
MEM_A_DQ<55>
BI
MEM_A_DQ<56>
BI
MEM_A_DQ<57>
BI
MEM_A_DQ<58>
BI
MEM_A_DQ<59>
BI
MEM_A_DQ<60>
BI
MEM_A_DQ<61>
BI
MEM_A_DQ<62>
BI
MEM_A_DQ<63>
BI
MEM_A_BA<0>
OUT
MEM_A_BA<1>
OUT
MEM_A_BA<2>
OUT
MEM_A_CAS_L
OUT
MEM_A_RAS_L
OUT
MEM_A_WE_L
OUT
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
BD37
BF36
BA28
BE39
BD39
AT41
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS*
SA_RAS*
SA_WE*
U1000
BGA
(3 OF 9)
SANDY-BRIDGE
MOBILE-2C-35W
MEMORY CHANNEL A
SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*
SA_CK_0
SA_CK_0*
SA_CKE_0
SA_CK_1
SA_CK_1*
SA_CKE_1
SA_CS_0*
SA_CS_1*
SA_ODT_0
SA_ODT_1
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
AU36
AV36
AY26
AT40
AU40
BB26
BB40
BC41
AY40
BA41
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_B_DQ<0>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
68 32 28 27
68 32 28 27
68 32 28 27
68
8
68
8
68
8
68 32 28 27
68
8
68 32 28 27
68
8
68 27
BI
68 27
BI
68 27
BI
68 27
BI
68 28
BI
68 28
BI
68 28
BI
68 28
BI
68 27
BI
68 27
BI
68 27
BI
68 27
BI
68 28
BI
68 28
BI
68 28
BI
68 28
BI
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68 32 28 27
68
8
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 29
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 30
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
BI
MEM_B_DQ<1>
BI
MEM_B_DQ<2>
BI
MEM_B_DQ<3>
BI
MEM_B_DQ<4>
BI
MEM_B_DQ<5>
BI
MEM_B_DQ<6>
BI
MEM_B_DQ<7>
BI
MEM_B_DQ<8>
BI
MEM_B_DQ<9>
BI
MEM_B_DQ<10>
BI
MEM_B_DQ<11>
BI
MEM_B_DQ<12>
BI
MEM_B_DQ<13>
BI
MEM_B_DQ<14>
BI
MEM_B_DQ<15>
BI
MEM_B_DQ<16>
BI
MEM_B_DQ<17>
BI
MEM_B_DQ<18>
BI
MEM_B_DQ<19>
BI
MEM_B_DQ<20>
BI
MEM_B_DQ<21>
BI
MEM_B_DQ<22>
BI
MEM_B_DQ<23>
BI
MEM_B_DQ<24>
BI
MEM_B_DQ<25>
BI
MEM_B_DQ<26>
BI
MEM_B_DQ<27>
BI
MEM_B_DQ<28>
BI
MEM_B_DQ<29>
BI
MEM_B_DQ<30>
BI
MEM_B_DQ<31>
BI
MEM_B_DQ<32>
BI
MEM_B_DQ<33>
BI
MEM_B_DQ<34>
BI
MEM_B_DQ<35>
BI
MEM_B_DQ<36>
BI
MEM_B_DQ<37>
BI
MEM_B_DQ<38>
BI
MEM_B_DQ<39>
BI
MEM_B_DQ<40>
BI
MEM_B_DQ<41>
BI
MEM_B_DQ<42>
BI
MEM_B_DQ<43>
BI
MEM_B_DQ<44>
BI
MEM_B_DQ<45>
BI
MEM_B_DQ<46>
BI
MEM_B_DQ<47>
BI
MEM_B_DQ<48>
BI
MEM_B_DQ<49>
BI
MEM_B_DQ<50>
BI
MEM_B_DQ<51>
BI
MEM_B_DQ<52>
BI
MEM_B_DQ<53>
BI
MEM_B_DQ<54>
BI
MEM_B_DQ<55>
BI
MEM_B_DQ<56>
BI
MEM_B_DQ<57>
BI
MEM_B_DQ<58>
BI
MEM_B_DQ<59>
BI
MEM_B_DQ<60>
BI
MEM_B_DQ<61>
BI
MEM_B_DQ<62>
BI
MEM_B_DQ<63>
BI
MEM_B_BA<0>
OUT
MEM_B_BA<1>
OUT
MEM_B_BA<2>
OUT
MEM_B_CAS_L
OUT
MEM_B_RAS_L
OUT
MEM_B_WE_L
OUT
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
BG39
BD42
AT22
AV43
BF40
BD45
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
SB_CAS*
SB_RAS*
SB_WE*
OMIT_TABLE
CRITICAL
U1000
BGA
(4 OF 9)
SB_CK_0
SB_CK_0*
SB_CKE_0
SB_CK_1
SB_CK_1*
SB_CKE_1
SB_CS_0*
SANDY-BRIDGE
MOBILE-2C-35W
SB_CS_1*
SB_ODT_0
SB_ODT_1
SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
SB_DQS_0
MEMORY CHANNEL B
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
BA34
AY34
AR22
BA36
BB36
BF27
BE41
BE47
AT43
BG47
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<0>
MEM_B_CLK_P<1>MEM_A_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CKE<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
68 32 30 29
68 32 30 29
68 32 30 29
68
8
68
8
68
8
68 32 30 29
68
8
68 32 30 29
68
8
68 29
BI
68 29
BI
68 29
BI
68 29
BI
68 30
BI
68 30
BI
68 30
BI
68 30
BI
68 29
BI
68 29
BI
68 29
BI
68 29
BI
68 30
BI
68 30
BI
68 30
BI
68 30
BI
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29
68
8
D
C
B
A
PAGE TITLE
CPU DDR3 INTERFACES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 5 4 2 1
36
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
12 OF 109
SHEET
11 OF 75
SIZE
A
D
Page 12
www.laptopblue.vn
345678
2 1
=PPVCORE_S0_CPU_VCCAXG
15 12
NOSTUFF
1
R1370
100
1%
1/20W
MF
201
2
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
15 12
1
1%
MF
2
9 7
=PPVCCSA_S0_CPU
7
AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61
F45
G45
BB3
BC1
BC4
L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20
VAXG_1
VAXG_2
VAXG_3
VAXG_4
VAXG_5
VAXG_6
VAXG_7
VAXG_8
VAXG_9
VAXG_10
VAXG_11
VAXG_12
VAXG_13
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_18
VAXG_19
VAXG_20
VAXG_21
VAXG_22
VAXG_23
VAXG_24
VAXG_25
VAXG_26
VAXG_27
VAXG_28
VAXG_29
VAXG_30
VAXG_31
VAXG_32
VAXG_33
VAXG_34
VAXG_35
VAXG_36
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43
VAXG_44
VAXG_45
VAXG_46
VAXG_47
VAXG_48
VAXG_49
VAXG_50
VAXG_51
VAXG_52
VAXG_53
VAXG_54
VAXG_55
VAXG_56
VAXG_SENSE
VSSAXG_SENSE
VCCPLL_1
VCCPLL_2
VCCPLL_3
VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14
VCCSA_15
VCCSA_16
=PPVCORE_S0_CPU
14 12
9 7
A26
VCC_1
A29
D
C
B
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
A
OMIT_TABLE
CRITICAL
U1000
BGA
(6 OF 9)
SANDY-BRIDGE
MOBILE-2C-35W
PEG AND DDR
CORE SUPLLY
RAIL
LINES
SENSE SVID QUIET
VSS_SENSE_VCCIO
VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29
VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49
VCCIO_50
VCCIO_51
VCCIO_SEL
VCCPQE_1
VCCPQE_2
VIDALERT*
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
=PP1V05_S0_CPU_VCCIO
(NOT controlled by VCCIO_SEL)
Fixed at 1.05V
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
W16
W17
For Future Compatibility
BC22
CPU_VCCIO_SEL
AM25
=PP1V05_S0_CPU_VCCPQE
AN22
A44
B43
C44
F43
G43
AN16
AN17
CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
=PP3V3_S0_CPU_VCCIO_SEL
1
R1320
10K
5%
1/20W
MF
201
2
14
7
7
1
R1302
130
1%
PLACE_NEAR=U1000.C44:2.54mm
1/20W
MF
201
2
PLACE_NEAR=U1000.F43:50.8mm
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
PLACE_NEAR=U1000.G43:50.8mm
R1310
43
1 2
201
1/20W
R1311
1 2
1/20W
201
R1312
1 2
1/20W
201
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
=PP1V05_S0_CPU_VCCIO
PLACE_NEAR=R1310.2:2.54mm
1
R1300
75
1%
1/20W
MF
201
2
5% MF
MF05%
MF05%
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
=PP1V05_S0_CPU_VCCIO
100
1/20W
100
1/20W
NOSTUFF
1
1
R1362
100
1%
1%
1/20W
MF
MF
201
201
2
2
NOSTUFF
1
1
R1363
100
1%
1%
PLACE_SIDE=BOTTOM
1/20W
MF
MF
201
201
2
2
NOSTUFF
R1360
NOSTUFF
R1361
14 12 10
9 7
IN
OUT
BI
=PPVCORE_S0_CPU
PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=BOTTOM
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
67 57
OUT
67 57
OUT
67 59
OUT
67 59
OUT
PLACE_NEAR=U1000.AN17:50.8mm
15 12
67 57
67 57
67 57
67 57
67 57
14 12
9 7
14 12 10
9 7
PLACE_NEAR=U1000.G45:50.8mm
=PPVCORE_S0_CPU_VCCAXG
9 7
PLACE_NEAR=U1000.F45:50.8mm
PLACE_SIDE=BOTTOM
CPU_AXG_SENSE_P
OUT
CPU_AXG_SENSE_N
OUT
=PP1V8_S0_CPU_VCCPLL_R
14
7
NOSTUFF
R1371
PLACE_SIDE=BOTTOM
100
1/20W
201
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
8 7 5 4 2 1
36
OMIT_TABLE
CRITICAL
U1000
BGA
(7 OF 9)
SANDY-BRIDGE
MOBILE-2C-35W
GRPHICS
DDR3-1.5V RAILS
(IPU)
RAIL
QUIET
VSS_SENSE_VDDQ
LINE
SENSE
(IPU)
LINE
SENSE
1.8V
RAIL
SA RAIL
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VCCDQ_1
VCCDQ_2
VDDQ_SENSE
VCCSA_SENSE
VCCSA_VID_0
VCCSA_VID_1
SM_VREF
=PP1V5_S3_CPU_VCCDDR
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
AM28
AN26
BC43
BA43
U10
D48
D49
AY43
R1314
1/20W
=PP1V5_S3_CPU_VCCDQ
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_VCCSASENSE
CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>
CPU_DDR_VREF
VOLTAGE=0.75V
1
1
R1313
10K
10K
5%
5%
1/20W
MF
MF
201
201
2
2
PLACE_NEAR=U1000.BC43:50.8mm
PLACE_NEAR=U1000.BA43:50.8mm
=PP1V5_S3_CPU_VCCDDR
26 15 12 10
7
PLACE_NEAR=U1000.U10:50.8mm
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
26 15 12 10
=PP1V5_S3_CPU_VCCDDR
7
SM_VREF_EXT
R1330
PLACE_NEAR=U1000.AY43:2.54mm
SM_VREF_EXT
R1331
PLACE_NEAR=U1000.AY43:2.54mm
SYNC_MASTER=K78_MLB
PAGE TITLE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
=PPVCCSA_S0_CPU
15 12
7
1
R1380
100
1%
1/20W
MF
201
2
15
7
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
54
OUT
12
1
100
5%
1/20W
MF
201
2
1
100
5%
1/20W
MF
201
2
R1381
100
1/20W
1
1%
MF
201
2
1
2
SM_VREF_EXT
C1330
0.1UF
10%
16V
X5R-CERM
0201
PLACE_NEAR=U1000.AY43:2.54mm
CPU POWER
1
R1382
100
1%
1/20W
MF
201
2
CPU_DDR_VREF
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
13 OF 109
SHEET
12 OF 75
OUT
D
C
54
B
12
A
SIZE
D
Page 13
www.laptopblue.vn
OMIT_TABLE
OMIT_TABLE
CRITICAL
BG13
VSS
BG17
VSS
BG21
VSS
BG24
VSS
BG28
VSS
D
C
B
BG37
BG41
BG45
BG49
BG53
VSS
VSS
VSS
VSS
VSS
C29
VSS
C35
VSS
C40
VSS
D4
VSS
D6
VSS
D10
VSS
D14
VSS
D18
VSS
D22
VSS
D26
VSS
D29
VSS
D35
VSS
D40
VSS
D43
VSS
D46
VSS
D50
VSS
D54
VSS
D58
VSS
E3
VSS
E25
VSS
E29
VSS
E35
VSS
E40
VSS
F13
VSS
F15
VSS
F19
VSS
F29
VSS
F35
VSS
F40
VSS
F55
VSS
G6
VSS
G48
VSS
G51
VSS
G61
VSS
H4
VSS
H10
VSS
H14
VSS
H17
VSS
H21
VSS
H53
VSS
H58
VSS
J1
VSS
J49
VSS
J55
VSS
K8
VSS
K11
VSS
K21
VSS
K51
VSS
L16
VSS
L20
VSS
L22
VSS
L26
VSS
L30
VSS
L34
VSS
L38
VSS
L43
VSS
L48
VSS
L61
VSS
M4
VSS
M6
VSS
U1000
BGA
(9 OF 9)
VSS
SANDY-BRIDGE
MOBILE-2C-35W
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M11
M15
M58
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P9
P14
P16
P18
P21
P58
P59
R4
R17
R20
R46
T1
T47
T50
T51
T52
T53
T55
T56
U8
U13
V20
V61
W8
W13
W15
W18
W21
W46
Y4
Y47
Y58
Y59
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
A
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AD17
AD20
AD61
AE13
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
A9
VSS
A13
VSS
A17
VSS
A21
VSS
A25
VSS
A28
VSS
A33
VSS
A37
VSS
A40
VSS
A45
VSS
A49
VSS
A53
VSS
AA1
VSS
AA8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC6
VSS
VSS
VSS
VSS
AD4
VSS
VSS
VSS
VSS
AE8
VSS
VSS
AF1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH4
VSS
VSS
AJ7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM4
VSS
VSS
VSS
VSS
VSS
VSS
8 7 5 4 2 1
CRITICAL
U1000
BGA
(8 OF 9)
VSS
SANDY-BRIDGE
MOBILE-2C-35W
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM34
AM38
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP7
AP10
AP51
AP55
AR7
AR13
AR17
AR21
AR41
AR48
AR61
AT4
AT14
AT19
AT36
AT45
AT52
AT58
AU1
AU7
AU11
AU28
AU32
AU51
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW7
AW13
AW43
AW61
AY4
AY9
AY14
AY19
AY30
AY36
AY41
AY45
AY49
AY55
AY58
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC5
BC13
BC57
BD8
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BE5
BG9
345678
36
2 1
PAGE TITLE
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CPU GROUNDS
Apple Inc.
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
14 OF 109
SHEET
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SIZE
D
C
B
A
D
Page 14
All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide
www.laptopblue.vn
345678
2 1
CPU VCORE DECOUPLING
Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF
=PPVCORE_S0_CPU
12
9 7
D
C
CRITICAL
1
C1600
2.2UF
20%
4V
2
X5R
402
PLACEMENT_NOTE (C1655-C1666):
Place close to U1000 on top side.
CRITICAL
1
C1655
22UF
20%
4V
2
X5R
402
PLACEMENT_NOTE (C1667-C1679):
CRITICAL
1
C1601
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1656
22UF
20%
4V
2
X5R
402
CRITICAL
1
C1602
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1657
22UF
20%
4V
2
X5R
402
CRITICAL
1
2
C1603
2.2UF
20%
4V
X5R
402
CRITICAL
1
C1604
2.2UF
20%
4V
2
X5R
402
CRITICAL CRITICAL
1
C1658
22UF
20%
4V
2
X5R
402
CRITICAL
1
C1605
2.2UF
20%
4V
2
X5R
402
1
C1659
22UF
20%
4V
2
X5R
402
CRITICAL
1
C1606
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
2
CRITICAL CRITICAL
1
2
C1660
22UF
20%
4V
X5R
402
C1607
2.2UF
20%
4V
X5R
402
CRITICAL
1
C1661
22UF
20%
4V
2
X5R
402
Processor Load Line : -2.9 mOhms
1
C1608
2.2UF
20%
4V
2
X5R
402
1
2
CRITICAL
C1662
22UF
20%
4V
X5R
402
CRITICAL
1
C1609
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1663
22UF
20%
4V
2
X5R
402
CRITICAL
1
C1610
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1664
22UF
20%
4V
2
X5R
402
CRITICAL
1
C1611
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
2
CRITICAL
1
C1665
22UF
20%
4V
2
X5R
402
C1612
2.2UF
20%
4V
X5R
402
CRITICAL
1
2
CRITICAL
1
C1666
22UF
20%
4V
2
X5R
402
C1613
2.2UF
20%
4V
X5R
402
CRITICAL
1
C1614
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1615
2.2UF
20%
4V
2
X5R
402
D
C
PLACEMENT_NOTE (C1640-C1645):
1
C1680
270UF
20%
2V
2
TANT
CASE-B2-SM
1
C1681
270UF
20%
2V
2
TANT TANT
CASE-B2-SM
1
C1682
270UF
20%
2V
2
CASE-B2-SM
1
C1683
270UF
20%
2V
2
TANT
CASE-B2-SM
1
C1679
270UF
20%
2V
2
TANT
CASE-B2-SM
CPU VCCIO/VCCPQ DECOUPLING
Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF
PLACEMENT_NOTE (C1684-C167F):
Place on bottom side of U1000Place on bottom side of U100.
Place on bottom side of U1000
=PP1V05_S0_CPU_VCCIO
12 10
9 7
B
A
8 7 5 4 2 1
Place on bottom side of U1000
1
C1684
1UF
10%
10V
2
X5R
402
1
C1697
1UF
10%
10V
2
X5R
402
PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
1
C161E
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167D
270UF
20%
2V
2
TANT
CASE-B2-SM
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1601
0.010
1 2
1%
1/4W
MF
0603
1
C1685
1UF
10%
10V
2
X5R
402
1
C1698
1UF
10%
10V
2
X5R
402
1
C161F
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167E
270UF
20%
2V
2
TANT
CASE-B2-SM
1
C1686
2
1
C1699
2
1
C162A
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167G
270UF
20%
2V
2
TANT
CASE-B2-SM
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
=PP1V05_S0_CPU_VCCPQE
1
C167F
1UF
10%
Note:The smallest 10mOhm available in the library are 0805s
10V
2
X5R
402
1
2
1
C169A
1UF
10%
10V
2
X5R
402
1
C162B
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167H
270UF
20%
2V
2
TANT
CASE-B2-SM
12
7
C1687
1UF
10%
10V
X5R
402
1
C1688
1UF
10%
10V
2
X5R
402
1
C169B
1UF
10%
10V
2
X5R
402
1
C162C
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1689
1UF
10%
10V
2
X5R
402
1
C169C
1UF
10%
10V
2
X5R
402
1
C162D
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1690
1UF
10%
10V
2
X5R
402
1
C169D
1UF
10%
10V
2
X5R
402
1
C162E
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1691
1UF
10%
10V
2
X5R
402
1
C169E
1UF
10%
10V
2
X5R
402
1
C167A
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1692
2
1
C169F
2
1
C167B
10UF
20%
6.3V
2
CERM-X5R
0402-1
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
C1693
2
1
C161A
2
1
C167C
10UF
20%
6.3V
2
CERM-X5R
0402-1
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
C1694
1UF
10%
10V
2
X5R
402
1
C161B
1UF
10%
10V
2
X5R
402
1
C1695
1UF
10%
10V
2
X5R
402
1
C161C
1UF
10%
10V
2
X5R
402
1
C1696
1UF
10%
10V
2
X5R
402
1
C161D
1UF
10%
10V
2
X5R
402
=PP1V8_S0_CPU_VCCPLL
7
36
CPU VCCPLL DECOUPLING
Intel recommendation (section 6.4): 2x 1uF, 1x 330uF
PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA
PLACEMENT_NOTE (C1646-C1671):
Place near U1000 on top side
R1600
0
1 2
5%
1/16W
MF-LF
402
PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA
CPU VCCPLL Low pass filter
=PP1V8_S0_CPU_VCCPLL_R
1
C160X
1UF
10%
10V
2
X5R
402
SYNC_MASTER=K78_MLB
PAGE TITLE
1
C160Y
1UF
10%
10V
2
X5R
402
PLACE_NEAR=U1000.BC2:5mm
1
C160Z
270UF
20%
2V
2
TANT
CASE-B2-SM
CPU DECOUPLING-I
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/08/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
16 OF 109
SHEET
14 OF 75
12
7
B
A
SIZE
D
Page 15
www.laptopblue.vn
345678
2 1
VAXG DECOUPLING
Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)
=PPVCORE_S0_CPU_VCCAXG
12
9 7
D
C
PLACEMENT_NOTE (C1700-C1710):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
Place on bottom side of U1000
CRITICAL
1
C1700
1UF 1UF
10%
10V
2
X5R
402
PLACEMENT_NOTE (C1711-C1716):
1
2
CRITICAL
1
C1711
10UF
20%
6.3V
2
CERM-X5R
0402-1
PLACEMENT_NOTE (C1717-C1722):
1
2
CRITICAL
1
C1717
22UF
20%
6.3V
2
X5R-CERM1
0603
PLACEMENT_NOTE (C1723-C1724):
1
C1723
270UF
20%
2V
2
TANT
CASE-B2-SM
1
2
CRITICAL
C1701
10%
10V
X5R
402
CRITICAL
C1712
10UF
20%
6.3V
CERM-X5R
0402-1
CRITICAL
C1718
22UF
20%
6.3V
X5R-CERM1
0603
1
C1724
270UF
20%
2V
2
TANT
CASE-B2-SM
1
2
1
2
C1713
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
CRITICAL
C1702
1UF
10%
10V
X5R
402
CRITICAL
CRITICAL
C1719
22UF
20%
6.3V
X5R-CERM1
0603
1
C1725
270UF
20%
2V
2
TANT
CASE-B2-SM
1
2
1
C1703
2
C1714
10UF
20%
6.3V
CERM-X5R
0402-1
1
C1720
2
CRITICAL
1UF
10%
10V
X5R
402
CRITICAL
CRITICAL
22UF
20%
6.3V
X5R-CERM1
0603
1
2
1
2
C1715
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
C1704
1UF
10%
10V
X5R
402
CRITICAL
CRITICAL
CRITICAL
C1721
22UF
20%
6.3V
X5R-CERM1
0603
Graphics Load Line : -3.9 mOhms
1
2
1
C1705
1UF
10%
10V
2
X5R
402
CRITICAL
C1716
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
CRITICAL
CRITICAL
C1722
22UF
20%
6.3V
X5R-CERM1
0603
1
2
CRITICAL
C1706
1UF
10%
10V
X5R
402
1
2
CRITICAL
C1707
1UF
10%
10V
X5R
402
1
2
CRITICAL
C1708
1UF
10%
10V
X5R
402
1
2
CRITICAL
C1709
1UF
10%
10V
X5R
402
1
2
CRITICAL
C1710
1UF
10%
10V
X5R
402
D
C
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF
=PP1V5_S3_CPU_VCCDDR
26 12 10
7
B
A
8 7 5 4 2 1
PLACEMENT_NOTE (C1738-C1747):
Place on bottom side of U1000
Place on bottom side of U1000
Place on bottom side of U1000
Place on bottom side of U100.
1
C1738
1UF
10%
10V
2
X5R
402
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom sidePlace close to U1000 on bottom side
Place close to U1000 on bottom sidePlace close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
1
C1748
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1756
270UF
20%
2V
2
TANT
CASE-B2-SM
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1702
1 2
0.010
1
C1739
1UF
10%
10V
2
X5R
402
1
C1749
10UF
20%
6.3V
2
CERM-X5R
0402-1 0402-1
=PP1V5_S3_CPU_VCCDQ
1%
1/4W
MF
0603
1
C1740
1UF
10%
10V
2
X5R
402
1
C1750
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1757
1UF
10%
10V
2
X5R
402
CPU VCCSA DECOUPLING
1
C1741
1UF
10%
10V
2
X5R
402
1
C1751
10UF
20%
6.3V
2
CERM-X5R
12
7
1
C1742
1UF
10%
10V 10V
2
X5R
402
1
C1752
10UF
20%
6.3V
2
CERM-X5R
0402-1 0402-1
1
C1743
1UF
10%
2
X5R X5R
402
1
C1753
10UF
20%
6.3V
2
CERM-X5R
1
2
1
C1744
2
C1754
10UF
20%
6.3V
CERM-X5R
0402-1
1
1UF
10%
10V
402
C1745
1UF
10% 10%
10V
2
X5R
402
1
C1755
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
2
C1746
1UF
10V
X5R
402
1
C1747
1UF
10%
10V
2
X5R
402
12
7
=PPVCCSA_S0_CPU
Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf
PLACEMENT_NOTE (C1758-C1762):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
Place on bottom side of U1000
1
C1758
1UF
10%
10V
2
X5R
402
1
C1763
10UF
20%
6.3V
2
CERM-X5R
0402-1 0402-1
1
C1768
270UF
20%
2V
2
TANT
CASE-B2-SM
1
2
1
2
C1759
1UF
10%
10V
X5R
402
C1764
10UF
20%
6.3V
CERM-X5R
1
2
1
2
C1765
10UF
20%
6.3V
CERM-X5R
0402-1
C1760
1UF
10%
10V
X5R
402
1
C1761
1UF
10%
10V
2
X5R
402
1
C1766
10UF
20%
6.3V
2
CERM-X5R
0402-1 0402-1
SYNC_MASTER=K78_MLB
PAGE TITLE
1
2
1
2
C1762
1UF
10%
10V
X5R
402
C1767
10UF
20%
6.3V
CERM-X5R
CPU DECOUPLING-II
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
17 OF 109
SHEET
15 OF 75
SIZE
B
A
D
36
Page 16
SYSCLK_CLK32K_RTC
IN
PCH_SRTCRST_L
RTC_RESET_L
D
PCH_INTRUDER_L
PCH_INTVRMEN_L
HDA_BIT_CLK_R
HDA_SYNC_R
PCH_SPKR
HDA_RST_R_L
HDA_SDIN0
IN
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
HDA_SDOUT_R
JTAG_T29_TMS
IN
ENET_MEDIA_SENSE
IN
XDP_PCH_TCK
IN
XDP_PCH_TMS
IN
XDP_PCH_TDI
C
IN
XDP_PCH_TDO
OUT
SPI_CLK_R
OUT
SPI_CS0_R_L
OUT
TP_SPI_CS1_L
SPI_MOSI_R
OUT
SPI_MISO
IN
ENET_MEDIA_SENSE
1
R1899
10K
5%
1/20W
MF
201
2
B
=PPVRTC_G3_PCH
1
1
R1802
20K
1/20W
201
1
201
5%
MF
2
NOSTUFF
R1880
1 2
1/20W
1
R1801
1M
5%
1/20W
MF
201
2
C1802
1.0UF
0201-MUR
0
5%
MF
201
20%
6.3V
X5R
R1800
330K
1/20W
A
HDA_SDOUT_R
Pullup needed for SPI_DESCRIPTOR_OVERRIDE_L? PD needed for BCM_MEDIA_SENSE?
PLACE_NEAR=R1813.1:2.54mm
R1803
5%
MF
2
2
1
1
2
2
SPI_DESCRIPTOR_OVERRIDE_L
8 7 5 4 2 1
A19
RTCX1
C19
RTCX2
NC
A23
SRTCRST*
F19
RTCRST*
K22
INTRUDER*
C21
INTVRMEN
H35
HDA_BCLK
H37
HDA_SYNC
N1
SPKR
F35
HDA_RST*
D36
HDA_SDIN0
B36
HDA_SDIN1
C35
HDA_SDIN2
A35
HDA_SDIN3
K37
HDA_SDO
K35
HDA_DOCK_EN*/GPIO33
M35
HDA_DOCK_RST*/GPIO13
M17
JTAG_TCK
M15
JTAG_TMS
U12
JTAG_TDI
M12
JTAG_TDO
AD12
SPI_CLK
AB8
SPI_CS0*
AB6
SPI_CS1*
W8
SPI_MOSI
Y2
SPI_MISO
=PP3V3_T29_PCH_GPIO
=PP3V3_S0_PCH_STRAPS
R1851
10K
1/20W
201
20K
5%
1/20W
MF
201
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
C1803
1.0UF
20%
6.3V
X5R
0201-MUR
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME*
LDRQ1*/GPIO23
LPC
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED*
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA3COMPI
SATA3RCOMP0
SATA3RBIAS
1
R1844
10K
5%
1/20W
MF
201
2
LDRQ0*
SERIRQ
5%
MF
1
R1846
2
U1800
COUGAR-POINT
MOBILE-SFF
FCBGA
(1 OF 10)
OMIT_TABLE
RTC
IHDA
JTAG
SPI
1
R1845
10K
5%
1/20W
MF
201
2
=PP3V3_S0_PCH_STRAPS
=PP3V3_SUS_GPIO
R1847
10K
1/20W
201
NOSTUFF
R1849
5%
MF
10K
1/20W
201
1
R1850
2
1
5%
MF
2
1
R1848
10K
5%
1/20W
MF
201
2
OUT
=PP3V3R1V5_S0_PCH_VCCSUSHDA
NOSTUFF
1
R1866
10K
5%
1/20W
MF
201
2
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S0_PCH
A37
A39
C39
C37
K40
H40
F37
Y4
AN3
AN1
AU3
AU1
AN6
AN8
AR3
AR1
AD4
AD2
AL3
AL1
AD8
AD6
AG3
AG1
AE3
AE1
AH8
AH6
AC3
AC1
AJ3
AJ1
AB10
AB12
W10
M2
R1
AF12
AF10
AH4
1
10K
5%
1/20W
MF
201
2
NOSTUFF
R1833
10K
1/20W
201
1
10K
5%
1/20W
MF
201
2
HDA_SYNC_R
HDA_SDOUT_R
5%
MF
LPC_R_AD<0>
LPC_R_AD<1>
LPC_R_AD<2>
LPC_R_AD<3>
LPC_FRAME_R_L
TP_LPC_DREQ0_L
T29_PWR_EN_PCH
LPC_SERIRQ
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
TP_SATA_B_D2RN
TP_SATA_B_D2RP
TP_SATA_B_R2D_CN
TP_SATA_B_R2D_CP
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
PCH_SATAICOMP
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
PCH_SATALED_L
DP_AUXCH_ISOL
SATARDRVR_EN
PCH_SATA3COMP
PCH_SATA3RBIAS
1
4.7K
5%
1/20W
MF
201
R1834
R1842
2
10K
5%
1/20W
MF
201
1
2
R1878
1
2
PCIECLKRQ0_L_GPIO73
PCIECLKRQ5_L_GPIO44
PEG_B_CLKRQ_L_GPIO56
PLACE_NEAR=U1800.AF12:2.54mm
1
R1877
10K
1/20W
SATARDRVR_EN
4.7K
5%
1/20W
MF
201
2
DP_AUXCH_ISOL
www.laptopblue.vn
37.4
1/20W
5%
1/20W
MF
201
33
5%
1/20W
MF
201
33
5%
1/20W
MF
201
201
0
PLACE_NEAR=U1800.AB10:2.54mm
1
1%
MF
2
NOSTUFF
R1841
0
1 2
5%
1/20W
MF
201
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDOUT
NC_PCIE_1_D2RN
NC_PCIE_1_D2RP
NC_PCIE_1_R2D_CN
NC_PCIE_1_R2D_CP
PCIE_AP_D2R_N
IN
PCIE_AP_D2R_P
IN
PCIE_AP_R2D_C_N
OUT
PCIE_AP_R2D_C_P
OUT
NC_PCIE_3_D2RN
NC_PCIE_3_D2RP
NC_PCIE_3_R2D_CN
NC_PCIE_3_R2D_CP
PCIE_EXCARD_D2R_N
IN
PCIE_EXCARD_D2R_P
IN
PCIE_EXCARD_R2D_C_N
OUT
PCIE_EXCARD_R2D_C_P
OUT
NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP
NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP
NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP
TP_PCIE_CLK100M_PE0N
TP_PCIE_CLK100M_PE0P
PCIECLKRQ0_L_GPIO73
PCIE_CLK100M_AP_N
OUT
PCIE_CLK100M_AP_P
OUT
AP_CLKREQ_L
IN
TP_PCIE_CLK100M_PE2N
TP_PCIE_CLK100M_PE2P
PCIECLKRQ2_L_GPIO20
PCIE_CLK100M_EXCARD_N
OUT
PCIE_CLK100M_EXCARD_P
OUT
EXCARD_CLKREQ_L
IN
PCIE_CLK100M_T29_N
OUT
PCIE_CLK100M_T29_P
OUT
T29_CLKREQ_L
IN
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
PCIECLKRQ5_L_GPIO44
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
PEG_B_CLKRQ_L_GPIO56
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
WOL_EN
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P
PCH_GPIO46
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
ITPCPU_CLK100M_N
OUT
OUT
OUT
OUT
IN
R1860
1 2
33
5%
1/20W
R1861
1 2
33
5%
1/20W
R1862
1 2
33
1/20W
5%
R1863
1 2
33
5%
1/20W
R1864
1 2
33
1/20W
5%
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
LPC_AD<0>
MF
201
LPC_AD<1>
MF
201
LPC_AD<2>
201
MF
LPC_AD<3>
MF
201
LPC_FRAME_L
201
MF
(IPU)
BI
BI
BI
BI
BI
R1830
1
R1820
10K
5%
1/20W
MF
201
2
BI
=PP1V05_S0_PCH
1
R1831
49.9
1%
1/20W
MF
201
2
1
R1832
750
PLACE_NEAR=U1800.AH4:2.54mm
1%
1/20W
MF
201
2
R1876
10K
1/20W
201
1
5%
MF
2
HDA_BIT_CLK_R
HDA_SYNC_R
PLACE_NEAR=U1800.F35:1.27mm
HDA_RST_R_L
HDA_SDOUT_R
JTAG_T29_TMS
PCH_SPKR
AP_CLKREQ_L
PCH_SATALED_L
EXCARD_CLKREQ_L
T29_CLKREQ_L
PEG_CLKREQ_L
PCIECLKRQ2_L_GPIO20
NOSTUFF
R1840
33
5%
MF
33
5%
MF
1 2
PLACE_NEAR=U1800.H37:1.27mm
R1811
1 2
PLACE_NEAR=U1800.K37:1.27mm
R1813
1 2
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P ITPCPU_CLK100M_P
PLACE_NEAR=U1800.H35:1.27mm
R1810
1 2
1/20W
201
R1812
1 2
1/20W
201
201
1
5%
MF
2
=PP3V3_SUS_GPIO
SML_PCH_0_ALERT_L
SML_PCH_1_ALERT_L
SMC_SCI_L
BJ33
PERN1
BL33
PERP1
BB30
PETN1
AY30
PETP1
BJ35
PERN2
BL35
PERP2
BB33
PETN2
AY33
PETP2
BH36
PERN3
BK36
PERP3
BF33
PETN3
BD33
PETP3
BJ37
PERN4
BL37
PERP4
BD35
PETN4
BF35
PETP4
BJ39
PERN5
BL39
PERP5
AY35
PETN5
BB35
PETP5
BH40
PERN6
BK40
PERP6
BD37
PETN6
BF37
PETP6
BJ41
PERN7
BL41
PERP7
AY37
PETN7
BB37
PETP7
BJ43
PERN8
BL43
PERP8
AY40
PETN8
BB40
PETP8
AD48
CLKOUT_PCIE0N
AD50
CLKOUT_PCIE0P
M4
PCIECLKRQ0*/GPIO73
AE49
CLKOUT_PCIE1N
AE51
CLKOUT_PCIE1P
U8
PCIECLKRQ1*/GPIO18
AD40
CLKOUT_PCIE2N
AD42
CLKOUT_PCIE2P
T4
PCIECLKRQ2*/GPIO20
AA49
CLKOUT_PCIE3N
AA51
CLKOUT_PCIE3P
B8
PCIECLKRQ3*/GPIO25
Y48
CLKOUT_PCIE4N
Y50
CLKOUT_PCIE4P
M19
PCIECLKRQ4*/GPIO26
AB40
CLKOUT_PCIE5N
AB42
CLKOUT_PCIE5P
K8
PCIECLKRQ5*/GPIO44
AF40
CLKOUT_PEG_B_N
AF42
CLKOUT_PEG_B_P
C4
PEG_B_CLKRQ*/GPIO56
AB44
CLKOUT_PCIE6N
AB46
CLKOUT_PCIE6P
J3
PCIECLKRQ6*/GPIO45
W44
CLKOUT_PCIE7N
W46
CLKOUT_PCIE7P
H4
PCIECLKRQ7*/GPIO46
AR12
CLKOUT_ITPXDP_N
AR10
CLKOUT_ITPXDP_P
345678
U1800
COUGAR-POINT
MOBILE-SFF
FCBGA
(2 OF 10)
OMIT_TABLE
PCI-E*
SMBALERT*/GPIO11
SML0ALERT*/GPIO60
SMBUS
SML1ALERT*/PCHHOT*/GPIO74
LINK
CNTRL
PEG_A_CLKRQ*/GPIO47
CLK
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
FLEX CLOCK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_DATA1
CL_RST1*
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
2 1
=PP1V05_S0_PCH_VCCDIFFCLK
SMBCLK
SMBDATA
SML0CLK
CL_CLK1
H12
F17
F10
H22
K12
A9
C9
D12
C11
L3
J1
M8
R8
AF44
AF46
BB24
AY24
AN10
AN12
BD17
BF17
BB26
AY26
M24
K24
AK8
AK6
J49
E51
W49
W51
AC49
H50
D48
G49
J51
NC
PCH_GPIO11
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_ALERT_L
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_ALERT_L
SML_PCH_1_CLK
SML_PCH_1_DATA
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
PEG_CLKREQ_L
PEG_CLK100M_N
PEG_CLK100M_P
DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
DOES THIS NEED LENGTH MATCH???
SYSCLK_CLK25M_SB_R
PCH_XCLK_RCOMP
TP_PCH_GPIO64_CLKOUTFLEX0
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO67_CLKOUTFLEX3
PLACE THIS RESISTOR NEAR THE PCH PIN
R1885
1 2
604
1/20W
1%201 MF
1.5V -> 1.1V
PLACE_NEAR=U1800.W49:2.54mm
OUT
BI
OUT
BI
OUT
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
PLACE_NEAR=U1800.W49:5.1mm
1
R1870
10K
5%
1/20W
MF
201
2
SYSCLK_CLK25M_SB
1
R1886
1K
1%
1/20W
MF
201
2
PLACE_NEAR=R1885.1:2.54mm
R1890
90.9
1/20W
201
1
R1871
10K
5%
1/20W
MF
201
2
IN
1
1%
MF
2
D
C
B
1
R1853
10K
5%
1/20W1/20W
MF
SYNC_MASTER=K21_MLB
201
PAGE TITLE
2
PCH SATA/PCIE/CLK/LPC/SPI
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
18 OF 109
SHEET
16 OF 75
SIZE
A
D
NOSTUFF
R1888
0
1 2
5%
1/20W
MF
201
1
R1854
10K
5%
1/20W
MF
201
2
PCH_GPIO11
1
R1855
10K
5%
MF
201
2
36
Page 17
R1905
D
C
B
10K
1/20W
201
www.laptopblue.vn
=PP3V3_SUS_GPIO
1
5%
MF
2
1
R1920
750
1%
1/20W
MF
201
2
=PP1V05_S0_PCH_VCCIO_PCIE
1
R1900
49.9
1%
1/20W
MF
PLACE_NEAR=U1800.BF19:12.7mm
201
2
PLACE_NEAR=U1800.BK20:2.54mm
DMI_N2S_N<0>
IN
DMI_N2S_N<1>
IN
DMI_N2S_N<2>
IN
DMI_N2S_N<3>
IN
DMI_N2S_P<0>
IN
DMI_N2S_P<1>
IN
DMI_N2S_P<2>
IN
DMI_N2S_P<3>
IN
DMI_S2N_N<0>
OUT
DMI_S2N_N<1>
OUT
DMI_S2N_N<2>
OUT
DMI_S2N_N<3>
OUT
DMI_S2N_P<0>
OUT
DMI_S2N_P<1>
OUT
DMI_S2N_P<2>
OUT
DMI_S2N_P<3>
OUT
PCH_DMI2RBIAS
PCH_DMI_COMP
PM_SYSRST_L
IN
PM_PCH_SYS_PWROK
IN
PM_PCH_PWROK
IN
PM_MEM_PWRGD
OUT
PM_DSW_PWRGD
IN
PM_PCH_APWROK
IN
PM_RSMRST_L
IN
PCH_SUSWARN_L
OUT
PM_PWRBTN_L
IN
SMC_ADAPTER_EN
IN
PM_BATLOW_L
IN
PCH_RI_L
BL21
DMI0RXN
BL23
DMI1RXN
BJ19
DMI2RXN
BL17
DMI3RXN
BJ21
DMI0RXP
BJ23
DMI1RXP
BL19
DMI2RXP
BJ17
DMI3RXP
BD22
DMI0TXN
BB22
DMI1TXN
BB19
DMI2TXN
BB17
DMI3TXN
BF22
DMI0TXP
AY22
DMI1TXP
AY19
DMI2TXP
AY17
DMI3TXP
BK20
DMI2RBIAS
BF19
DMI_ZCOMP
BD19
DMI_IRCOMP
L1 D8
SYS_RESET*
M10
SYS_PWROK
M22
PWROK
B12
DRAMPWROK
A21
DPWROK
G3
APWROK
B20
RSMRST*
C13
SUSWARN*/SUSPWRDNACK/GPIO30
K19
PWRBTN*
H19
ACPRESENT/GPIO31
H10
BATLOW*/GPIO72
F12
RI*
1
R1909
100K
5%
1/20W
MF
201
2
U1800
COUGAR-POINT
MOBILE-SFF
FCBGA
(3 OF 10)
DMI
MANAGEMENT
SYSTEM POWER
DF_TVS:DMI & FDI Term Voltage
Set to Vss when Low
Set to Vcc when High
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
OMIT_TABLE
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
WAKE*
CLKRUN*/GPIO32
SUS_STAT*/GPIO61
SUSCLK/GPIO62
SLP_S5*/GPIO63
SLP_S4*
SLP_S3*
SLP_A*
PMSYNCH
SLP_LAN*/GPIO29
DSWVRMEN
SLP_SUS*
SUSACK*
BL13
BJ15
BD12
BJ11
AY15
AY12
BJ9
BF10
BJ13
BL15
BF12
BL11
BB15
BB12
BL9
BD10
BB10
BH12
BK8
BK12
BH8
T2
G6
D3
F6
K10
D4
C7
BB8
A7
F22
A15
F15
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
FDI_INT
FDI_FSYNC<0>
FDI_FSYNC<1>
FDI_LSYNC<0>
FDI_LSYNC<1>
=T29_WAKE_L
PCIE_WAKE_L
MAKE_BASE=TRUE
PM_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L
PM_SYNC
GPIO29_SLP_LAN_L
PCH_DSWVRMEN
PM_SLP_SUS_L
PCH_SUSACK_L
LVDS_IG_BKL_ON
OUT
LVDS_IG_PANEL_PWR
OUT
LVDS_IG_BKL_PWM
OUT
1
R1955
100K
5%
1/20W
MF
201
2
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
=PPVRTC_G3_PCH
1
R1915
390K
5%
1/20W
MF
201
2
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
PCH_DAC_IREF
IN
1
R1951
1K
5%
1/20W
PLACE_NEAR=U1800.R51:2.54mm
MF
201
2
M44
M42
L49
L51
NC
K46
NC
R42
NC
M40
NC
AH42
NC
AH40
NC
AG51
NC
AG49
NC
AK44
NC
AK46
NC
AR46
NC
AN49
NC
AN44
NC
AK40
NC
AR44
NC
AN51
NC
AN46
NC
AK42
NC
AH46
NC
AH44
NC
AM50
NC
AL49
NC
AJ51
NC
AH50
NC
AM48
NC
AL51
NC
AJ49
NC
AH48
NC
M46
R46
U46
R49
N49
M50
N51
R51
T48
345678
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK*
LVDSA_CLK
LVDSA_DATA_0*
LVDSA_DATA_1*
LVDSA_DATA_2*
LVDSA_DATA_3*
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK*
LVDSB_CLK
LVDSB_DATA_0*
LVDSB_DATA_1*
LVDSB_DATA_2*
LVDSB_DATA_3*
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
U1800
COUGAR-POINT
MOBILE-SFF
FCBGA
(4 OF 10)
OMIT_TABLE
LVDS
CRT
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DIGITAL DISPLAY INTERFACE
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
2 1
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AU40
AU42
AR51
AR49
AT50
AT48
W42
R44
AW51
AW49
AY42
AY48
AY50
AY44
AY46
BB44
BB46
BA49
BA51
T50
U44
AU51
AU49
BE46
BC49
BC51
BD48
BD50
BF46
BF45
BE49
BE51
M48
U42
AU46
AU44
BK44
BG51
BG49
BF42
BD42
BJ47
BL47
BL45
BJ45
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
TP_SDVO_STALLN
TP_SDVO_STALLP
TP_SDVO_INTN
TP_SDVO_INTP
DP_IG_B_DDC_CLK
DP_IG_B_DDC_DATA
DP_IG_B_AUX_N
DP_IG_B_AUX_P
DP_IG_B_HPD
TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_C_AUXN
TP_DP_IG_C_AUXP
TP_DP_IG_C_HPD
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD
TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>
D
C
B
R1986
0
PCH_SUSWARN_L
5%
1/20W
MF
201
12
=PP3V3_SUS_GPIO
=PP3V3_S5_PCH
=PP3V3_SUS_GPIO
NOSTUFF
R1925
1K
1/20W
201
1
1
R1985
1%
MF
1K
1%
1/20W
MF
2
2
201
R1984
10K
1/20W
201
1
R1982
5%
MF
10K
5%
1/20W
MF
201
2
A
8 7 5 4 2 1
1
2
PCH_SUSACK_L
R1983
10K
1/20W
201
1
5%
MF
2
GPIO29_SLP_LAN_L
PM_BATLOW_L
PM_PWRBTN_L
PCIE_WAKE_L
PCH_SUSWARN_L
=PP3V3_S0_PCH_STRAPS
R1991
8.2K
5%
1/20W
MF
201
1
2
PM_CLKRUN_L
SIZE
A
D
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
36
PCH DMI/FDI/GRAPHICS
Apple Inc.
R
.
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
19 OF 109
SHEET
17 OF 75
Page 18
www.laptopblue.vn
345678
2 1
DF_TVS
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
BE3
BE1
AU8
BJ7
BA3
BH3
AU6
AW3
AW1
AY6
AY2
AY4
BC3
BC1
BG1
BG3
BE6
BH4
BF7
BJ4
BJ5
BK6
AY8
BC7
BL5
BB6
BD2
BD4
BA1
BF6
F24
H24
C25
A25
C27
A27
H28
F28
M26
K26
D28
B28
H26
F26
D32
B32
M28
K28
C29
A29
C31
A31
H33
F33
H30
F30
M33
K33
C33
A33
C17
A17
A13
D16
A11
B16
C23
H15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PCH_DF_TVS
USB_HUB1_UP_N
USB_HUB1_UP_P
NC_USB_1N
NC_USB_1P
NC_USB_2N
NC_USB_2P
NC_USB_3N
NC_USB_3P
NC_USB_4N
NC_USB_4P
NC_USB_5N
NC_USB_5P
NC_USB_6N
NC_USB_6P
NC_USB_7N
NC_USB_7P
USB_HUB2_UP_N
USB_HUB2_UP_P
USB_CAMERA_N
USB_CAMERA_P
NC_USB_10N
NC_USB_10P
NC_USB_11N
NC_USB_11P
NC_USB_12N
NC_USB_12P
NC_USB_13N
NC_USB_13P
R2081
2.2K
1/20W
R2080
1K
1 2
5%
1/20W
MF
201
PCH_USB_RBIAS
68
=PP1V8_S0_PCH_VCC_DFTERM
1
5%
MF
201
2
CPU_PROC_SEL_L
24 68
BI
USB HUB 1
24 68
BI
Unused
Unused
Unused
Unused
Unused
Unused
Unused
BI
USB HUB 2
BI
BI
Camera
BI
Unused
Unused
Unused
Unused
R2060
1
R2070
22.6
1%
1/20W
MF
PLACE_NEAR=U1800.C33:2.54mm
201
2
10K
1/20W
201
D
C
B
=PP3V3_S3_PCH_GPIO
=PP3V3_SUS_GPIO
1
10K
201
R2065
10K
5%
201
1
R2067
MF
10K
2
5%
1/20W
MF
201
2
R2069
1/20W
1
R2064
1
10K
5%
5%
1/20W
MF
201
MF
2
2
1
R2061
10K
5%
1/20W
MF
201
2
NOSTUFF
1
R2062
5%
MF
1/20W
2
10K
1/20W
201
1
R2068
10K
5%
1/20W
MF
201
2
1
5%
MF
2
PCH_GPIO59_OC0_L
USB_HUB_SOFT_RESET_L
SDCONN_STATE_RST_L
ENET_PWR_EN
PCH_GPIO43_OC4_L
SDCONN_STATE_CHANGE
PCH_GPIO10_OC6_L
PCH_GPIO14_OC7_L
SYNC_MASTER=K21_MLB
PAGE TITLE
PUs TO S0 INSTEAD?
PCH PCI/FLASHCACHE/USB
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
19
7
19 17 16
7
NOTE: PULLUP IS REQUIRED
ON AP_PWR_EN IF ISOLATION RESISTOR
R2090 IS UNSTUFFED
R2090
0
12
AP_PWR_EN
5%
1/20W
MF
201
23
23
23
23
23
23
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
SHEET
SYNC_DATE=12/13/2010
3.13.0
20 OF 109
18 OF 75
SIZE
A
D
36
BH24
BK24
BH20
BK16
BH16
AN42
AN40
AR40
AR42
D20
M30
AM4
AT4
AT2
AD10
B24
D24
AD44
AD46
BJ48
BL7
W40
K30
BH49
BB42
BJ25
BJ27
BJ31
BJ29
BL25
BL27
BL31
BL29
BF26
BB28
BF28
BF30
BD26
AY28
BD28
BD30
D49
C48
C47
C45
G46
K44
F46
F42
H42
D44
A47
C41
F45
F40
G51
E49
H48
J43
G45
E3
H2
F7
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP41
TP42
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA*
PIRQB*
PIRQC*
PIRQD*
REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54
GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
PME*
PLTRST*
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
NC
NC
NC
NC
D
FIXME: NEED INTEL APPROVAL OF NC ON TPS
TP_PM_TEST_RST_L
C
=PP3V3_S0_PCH_GPIO
7
R2010
R2011
R2012
R2013
R2016
R2017
R2018
R2030
B
R2031
R2015
PCH_PCI_GNT3_L
18
PCH_PCI_GNT2_L
18
PCH_PCI_GNT1_L
18
NOSTUFF
A
R2052
1/20W
10K
201
10K
10K
10K
10K
10K
10K
10K
10K
10K
201 MF5%
10K
201
NOSTUFF
1
R2053
5%
MF
10K
1/20W
2
201
5%
MF
NOSTUFF
1
2
12
12
12
12
12
12
12
12
12
39
12
5%
NOSTUFF
R2054
10K
1/20W
63
201
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
6
1/20W
5%
MF
MF201 5%
MF201 5%
MF201 5%
MF201 5%
MF201 5%
MF201 5%
MF201 5%
MF201 5%
IN
IN
MF
1
2
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
JTAG_GMUX_TMS
T29_A_HV_EN_L
PCI_REQ3_L
PCH_PCI_GNT1_L
18
PCH_PCI_GNT2_L
18
PCH_PCI_GNT3_L
18
PCI_INTE_L
AUD_IP_PERIPHERAL_DET
39
6
IN
T29_MCU_INT_L
AUD_I2C_INT_L
TP_PCI_PME_L
6
PLT_RESET_L
26 25
OUT
LPC_CLK33M_SMC_R
69 25
OUT
LPC_CLK33M_LPCPLUS_R
25
OUT
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
6
PCH_CLK33M_PCIOUT
25
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
U1800
COUGAR-POINT
MOBILE-SFF
FCBGA
(5 OF 10)
OMIT_TABLE
RSVD
TP
PCI
USB
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
RSVD_BE3
RSVD_BE1
RSVD_AU8
RSVD_BJ7
RSVD_BA3
RSVD_BH3
RSVD_AU6
RSVD_AW3
RSVD_AW1
RSVD_AY6
RSVD_AY2
RSVD_AY4
RSVD_BC3
RSVD_BC1
RSVD_BG1
RSVD_BG3
RSVD_BE6
RSVD_BH4
RSVD_BF7
RSVD_BJ4
RSVD_BJ5
RSVD_BK6
RSVD_AY8
RSVD_BL5
RSVD_BB6
RSVD_BD2
RSVD_BD4
RSVD_BA1
RSVD_BF6
USBRBIAS*
USBRBIAS
8 7 5 4 2 1
Page 19
www.laptopblue.vn
345678
2 1
D
C
B
JTAG_ISP_TCK
ODD_PWR_EN_L
GMUX_INT
=PP3V3_SUS_GPIO
NOSTUFF
R2195
=PP3V3_S5_PCH
R2191
10K
1/20W
=PP3V3_T29_PCH_GPIO
=PP3V3_S0_PCH_STRAPS
201
5%
MF
10K
1/20W
1
2
201
1
=PP3V3_S0_PCH
R2150
10K
5%
1/20W
MF
201
NOSTUFF
SMC_IG_THROTTLE_L
IN
FW_PME_L
IN
GMUX_INT
=PP3V3_S0_PCH
1
R2190
100K
5%
1/20W
MF
201
BI
R2112
1/20W
201
R2193
100K
5%
MF
1/20W
201
1
2
1
5%
MF
2
1
R2111
20K
5%
1/20W
MF
201
2
R2192
10K
1/20W
201
1
5%
MF
2
1
5%
MF
2
1
R2113
10K10K
5%
1/20W
MF
201
2
1
R2194
10K
5%
1/20W
MF
201
2
SPIROM_USE_MLB
ISOLATE_CPU_MEM_L
(NC-ed per Intel chklist)
PCH_GPIO12
PCH_GPIO24
2
(PU necessary?)
(PU necessary?)
(PUs necessary?)
IN
SMC_RUNTIME_SCI_L
IN
NC_GPIO8
PCH_GPIO12
PCH_GPIO15
AUD_IPHS_SWITCH_EN_PCH
OUT
LPCPLUS_GPIO
ODD_PWR_EN_L
OUT
PCH_GPIO24
SMC_SCI_L
IN
ISOLATE_CPU_MEM_L
OUT
T29_SW_RESET_L
PCH_GPIO35
PCH_GPIO36_SATA2GP
JTAG_ISP_TCK
OUT
JTAG_ISP_TDO
IN
JTAG_ISP_TDI
FW_PWR_EN
ENET_LOW_PWR
SPIROM_USE_MLB
BI
MLB_RAM_CFG3
MLB_RAM_CFG2
MLB_RAM_CFG1
MLB_RAM_CFG0
(IPU)
(IPU)
SMC_SCI_L
R2160
10K
1/20W
201
5%
MF
1
R2184
2
10K
201
5%
MF
1
2
R2185
10K
1/20W1/20W
201
1
5%
MF
2
R2186
10K
1/20W
201
1
5%
MF
2
AUD_IPHS_SWITCH_EN_PCH
IN
JTAG_ISP_TDO
FW_PME_L
FW_PWR_EN
SMC_IG_THROTTLE_L
BMBUSY*/GPIO0
B40
TACH1/GPIO1
C43
TACH2/GPIO6
A45
TACH3/GPIO7
H17
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
K6
GPIO15
AA3
SATA4GP/GPIO16
B44
TACH0/GPIO17
W3
SCLOCK/GPIO22
K15
GPIO24/MEM_LED
C15
GPIO27
G1
GPIO28
R3
STP_PCI*/GPIO34
W12
GPIO35
W6
SATA2GP/GPIO36
M6
SATA3GP/GPIO37
N3
SLOAD/GPIO38
U10
SDATAOUT0/GPIO39
U1
SDATAOUT1/GPIO48
AA1
SATA5GP/GPIO49
K17
GPIO57
K42
TACH4/GPIO68
A43
TACH5/GPIO69
D40
TACH6/GPIO70
A41
TACH7/GPIO71
=PP3V3_S3_PCH_GPIO
T29_PWR_EN_PCH
IN
PM_PCH_PWROK
R2152
0
12
AUD_IPHS_SWITCH_EN_PCH_R
5%
1/20W
MF
201
PM_PCH_PWROK
U1800
COUGAR-POINT
MOBILE-SFF
FCBGA
(6 OF 10)
OMIT_TABLE
GPIO
5
A
U2150
6
B
MISC
NCTF
8
08
4
CPU
VSS_NCTF_A4
VSS_NCTF_A48
VSS_NCTF_A49
VSS_NCTF_A5
VSS_NCTF_A51
VSS_NCTF_BH1
VSS_NCTF_BH51
VSS_NCTF_BJ1
VSS_NCTF_BJ3
VSS_NCTF_BJ49
VSS_NCTF_BJ51
VSS_NCTF_BL1
VSS_NCTF_BL3
VSS_NCTF_BL4
VSS_NCTF_BL48
VSS_NCTF_BL49
VSS_NCTF_BL51
VSS_NCTF_C3
VSS_NCTF_C49
VSS_NCTF_C51
VSS_NCTF_D1
VSS_NCTF_D51
VSS_NCTF_E1
74LVC2G08GT
SOT833
3
Y
1
2
PROCPWRGD
THRMTRIP*
INIT3_3V*
A
U2150
B
A20GATE
PECI
RCIN*
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
74LVC2G08GT
8
08
4
SOT833
7
Y
U3W1
AU12
U6
AU10
BC9
R6C5
AK10
AH12
AK12
AH10
U40
A4
A48
A49
A5
A51
BH1
BH51
BJ1
BJ3
BJ49
BJ51
BL1
BL3
BL4
BL48
BL49
BL51
C3
C49
C51
D1
D51
E1
PCH_A20GATE
PCH_PECI CPU_PECI
PCH_RCIN_L
PCH_PROCPWRGD
PM_THRMTRIP_L_R
PCH_INIT3V3_L
ALL RSVD TPs NC-ed per INTEL approval
1
2
2
R2170
43
1 2
1/20W
5%
C2152
0.1UF
10%
16V
X5R-CERM
0201
T29_PWR_EN
AUD_IPHS_SWITCH_EN
MF
201
OUT
1
R2155
10K
5%
1/20W
MF
201
2
R2140
0
1 2
201MF1/20W
5%
This has internal pull up and should not pulled low.
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
CPU_PWRGD
=PP3V3_T29_PCH_GPIO
OUT
R2156
OUT
390
1/20W
1 2
201
5%
PM_THRMTRIP_L
MF
=PP3V3_S0_PCH_STRAPS
1
R2196
10K
5%
1/20W
MF
201
2
1
R2199
10K
5%
1/20W
MF
201
2
NOSTUFF
1
R2198
10K
5%
1/20W
MF
201
2
IN
PCH_INIT3V3_L
NOSTUFF
R2197
10K
5%
1/20W
MF
201
1
R2110
10K
5%
1/20W
MF
201
2
NOSTUFF
R2130
1/20W
1
2
T29_SW_RESET_L
SMC_RUNTIME_SCI_L
PCH_GPIO36_SATA2GP
1
1K
5%
MF
201
2
JTAG_ISP_TDI
ENET_LOW_PWR
D
C
B
WOL_EN
R2114
1/20W
201
1
5%
MF
2
=PP3V3_SUS_GPIO
R2115
10K10K
1/20W
201
1
5%
MF
2
PCH_GPIO46
=PP3V3_S0_PCH_STRAPS
A
DRAM_CFG0:H
R2175
10K
1/20W
201
DRAM_CFG1:H
R2174
1
5%
MF
2
10K
1/20W
201
DRAM_CFG2:H
1
5%
MF
2
R2173
10K
1/20W
201
1
5%
MF
2
DRAM_CFG3:H
R2172
10K
1/20W
201
1
5%
MF
2
MLB_RAM_CFG3
MLB_RAM_CFG2
MLB_RAM_CFG1
MLB_RAM_CFG0
MLB_RAM_CFG3
MLB_RAM_CFG2
MLB_RAM_CFG1
MLB_RAM_CFG0
DRAM_CFG3:L
R2162
8 7 5 4 2 1
GPIO[68:71] have 15K-45K internal PUs
1
R2163
1K
5%
1/20W
MF
201
2
1/20W
1
1K
5%
MF
201
2
SIZE
A
D
SYNC_MASTER=K21_MLB
DRAM_CFG1:LDRAM_CFG2:L
R2164
1/20W
1
1K
5%
MF
201
2
DRAM_CFG0:L
1
R2165
1K
5%
1/20W
MF
201
2
PAGE TITLE
PCH MISC
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
21 OF 109
SHEET
19 OF 75
36
Page 20
www.laptopblue.vn
345678
2 1
D
C
B
PLACE_NEAR=U1800.R15:2.54mm
VCCACLK pin left as NC per DG
=PP3V3_S5_PCH_VCCDSW
7
22
TP_PPVOUT_PCH_DCPSUSBYP
PP3V3_S0_PCH_VCC3_3_CLK_F
22
=PP1V05_S0_PCH_VCCIO_CLK
7
20 22
AL24 left as NC per DG
=PP1V05_S0_PCH_VCCASW
7
20 22
PPVOUT_G3_PCH_DCPRTC
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=3.3V
1
C2210
0.1UF
10%
16V
2
X5R-CERM
0201
MIN_LINE_WIDTH=0.2 mm
PLACE_NEAR=U1800.U17:2.54mm
1
C2222
0.1UF
10%
16V
2
X5R-CERM
0201
PCH output, for decoupling only
=PP1V8R1V5_S0_PCH_VCCVRM
7
20
PP1V05_S0_PCH_VCCADPLLA
20
PP1V05_S0_PCH_VCCADPLLB
20
=PP1V05_S0_PCH_VCCIO_CLK
7
20 22
=PP1V05_S0_PCH_VCCDIFFCLK
7
16 22
55mA Max, 5mA Idle
=PP1V05_S0_PCH_VCCSSC
7
22
PPVOUT_S0_PCH_DCPSST
MIN_NECK_WIDTH=0.2 mm
7
22
=PPVRTC_G3_PCH
7
VCCAPLLDMI2 pin left as NC per DG
VOLTAGE=3.3V
=PP1V05_S0_PCH_V_PROC_IO
1
C2231
1UF
10%
6.3V
2
CERM
402
1
C2232
0.1UF
10%
16V
2
X5R-CERM
0201
PLACE_NEAR=U1800.N16:2.54mm
PLACE_NEAR=U1800.N16:2.54mm
PLACE_NEAR=U1800.N16:2.54mm
1
C2233
0.1UF
10%
16V
2
X5R-CERM
0201
AC51
NC
R12
R10
V37
V39
AW31
NC
AP27
V13
NC
AR33
NC
AU33
NC
AB27
AB29
AB31
AC27
AC29
AC31
AE27
AE29
AE31
U21
V21
V23
V25
Y21
Y23
Y25
Y27
Y29
Y31
R15
U15
AC39
BF40
BD40
AJ17
AC37
AE37
AE39
AC35
U17
AM17
N16
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3_V37
VCC3_3_V39
VCCAPLLDMI2
VCCIO_AP27
DCPSUS_V13
DCPSUS_AR33
DCPSUS_AU33
VCCASW_AB27
VCCASW_AB29
VCCASW_AB31
VCCASW_AC27
VCCASW_AC29
VCCASW_AC31
VCCASW_AE27
VCCASW_AE29
VCCASW_AE31
VCCASW_U21
VCCASW_V21
VCCASW_V23
VCCASW_V25
VCCASW_Y21
VCCASW_Y23
VCCASW_Y25
VCCASW_Y27
VCCASW_Y29
VCCASW_Y31
DCPRTC_R15
DCPRTC_U15
VCCVRM_AC39
VCCADPLLA
VCCADPLLB
VCCIO_AJ17
VCCDIFFCLKN_AC37
VCCDIFFCLKN_AE37
VCCDIFFCLKN_AE39
VCCSSC
DCPSST
V_PROC_IO
VCCRTC
COUGAR-POINT
U1800
MOBILE-SFF
FCBGA
(8 OF 10)
OMIT_TABLE
CLOCK/MISC
RTC CPU
VCCIO_R23
VCCIO_R25
VCCIO_U23
VCCIO_U25
VCCSUS3_3_R27
VCCSUS3_3_R29
VCCSUS3_3_U27
VCCSUS3_3_U29
USB
VCCSUS3_3_N27
VCCIO_N18
V5REF_SUS
DCPSUS_AU31
VCCSUS3_3_AM27
V5REF
VCCSUS3_3_R33
VCCSUS3_3_R35
VCCSUS3_3_U33
VCCSUS3_3_U35
VCC3_3_AB19
VCC3_3_AC19
PCI/GPIO/LPC
VCC3_3_R40
VCC3_3_AF6
VCCIO_AA13
VCCIO_AG13
VCCIO_AG15
VCCIO_AF15
SATA
VCCAPLLSATA
VCCVRM_AE19
VCCVRM_AF17
VCCIO_AB15
VCCIO_AC13
VCCIO_AC15
VCCASW_U19
VCCASW_R19
VCCASW_V19
FUSE
VCCSUSHDA
HDA
R23
R25
U23
U25
R27
R29
U27
U29
N27
N18
M37
AU31
AM27
N36
R33
R35
U33
U35
AB19
AC19
R40
AF6
AA13
AG13
AG15
AF15
AM2
AE19
AF17
AB15
AC13
AC15
U19
R19
V19
V31
7
=PP1V05_S0_PCH_VCCIO_USB
=PP3V3_SUS_PCH_VCCSUS_USB
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP5V_SUS_PCH_V5REFSUS
NC-ed per DG
NC
=PP3V3_SUS_PCH_VCCSUS
=PP5V_S0_PCH_V5REF
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_SATA
=PP1V05_S0_PCH_VCCIO_SATA
VCCAPLLSATA pin left as NC per DG
NC
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP3V3R1V5_S0_PCH_VCCSUSHDA
10 mA Max, 1mA Idle
=PP1V05_S0_PCH_VCCADPLL
22
7
R2260
0
1 2
5%
1/16W
MF-LF
402
7
22
7
22
7
7
22
7
22
7
22
7
16 20 22
20
7
16 20 22
7
20 22
7
=PP1V05_S0_PCH_VCC_CORE
7
22
1.44 A Max, 474mA Idle
22
7
=PP1V05_S0_PCH_VCCIO_PLLPCIE
7
TP_1V05_S0_PCH_VCCAPLLEXP
=PP1V05_S0_PCH_VCCIO
7
22
=PP3V3_S0_PCH_VCC3_3_PCI
7
22
=PP1V8R1V5_S0_PCH_VCCVRM
7
20
VCCAFDIPLL pin left as NC per DG
=PP1V05_S0_PCH_VCCIO_PLLFDI
7
=PP1V05_S0_PCH_VCCDMI_FDI
16 22 17 16
PCH VCCADPLLA Filter
(PCH DPLLA PWR)
PP1V05_S0_PCH_VCCADPLLA
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2260
0.1UF
10%
16V
2
X5R-CERM
0201
1
C2261
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U1800.BF40:2.54MM
7
20
68 mA
AB21
AB23
AC21
AC23
AE21
AE23
AF21
AF23
AG21
AG23
AG25
AG27
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AK29
AK31
AK33
AM33
AM35
AM21
AP19
AR15
AT13
AR23
AR25
AR27
AR29
AU23
AU25
AU27
AU29
AU35
AW34
BK28
AU19
AW18
AP13
NC
AP15
NC
AK21
AU15
AW16
VCCCORE_AB21
VCCCORE_AB23
VCCCORE_AC21
VCCCORE_AC23
VCCCORE_AE21
VCCCORE_AE23
VCCCORE_AF21
VCCCORE_AF23
VCCCORE_AG21
VCCCORE_AG23
VCCCORE_AG25
VCCCORE_AG27
VCCCORE_AJ21
VCCCORE_AJ23
VCCCORE_AJ25
VCCCORE_AJ27
VCCCORE_AJ29
VCCCORE_AJ31
VCCCORE_AK29
VCCCORE_AK31
VCCCORE_AK33
VCCCORE_AM33
VCCCORE_AM35
VCCIO_AM21
VCCAPLLEXP
VCCIO_AR15
VCCIO_AT13
VCCIO_AR23
VCCIO_AR25
VCCIO_AR27
VCCIO_AR29
VCCIO_AU23
VCCIO_AU25
VCCIO_AU27
VCCIO_AU29
VCCIO_AU35
VCCIO_AW34
VCC3_3_BK28
VCCVRM_AU19
VCCVRM_AW18
VCCAFDIPLL_AP13
VCCAFDIPLL_AP15
VCCIO_AK21
VCCDMI_AU15
VCCDMI_AW16
U1800
COUGAR-POINT
MOBILE-SFF
FCBGA
(7 OF 10)
OMIT_TABLE
LVDS
VCCTX_LVDS_AF37
VCCTX_LVDS_AG37
VCCTX_LVDS_AG39
VCC CORE
VCCTX_LVDS_AJ37
HVCMOS
DMI
VCCDFTERM_AJ13
VCCDFTERM_AJ15
VCCDFTERM_AK15
VCCDFTERM_AL13
NAND/SPI
VCCIO
FDI
VCCADAC
CRT
VSSADAC
VCCALVDS_AF33
VCCALVDS_AG33
VSSALVDS_AC33
VSSALVDS_AE33
VCC3_3_T39
VCC3_3_U37
VCCVRM_AU21
VCCVRM_AW21
VCCDMI_AM23
VCCCLKDMI
VCCSPI
U51
V50
AF33
AG33
AC33
AE33
AF37
AG37
AG39
AJ37
T39
U37
AU21
AW21
AM23
AP39
AJ13
AJ15
AK15
AL13
Y19
PP3V3_S0_PCH_VCCA_DAC_F
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V05_S0_PCH_VCC_DMI
PP1V05_S0_PCH_VCCCLKDMI_F
=PP1V8_S0_PCH_VCC_DFTERM
=PP3V3_S5_PCH_VCC_SPI
22
D
7
22
7
20
7
22
22
7
18 22
7
22
C
B
PCH VCCADPLLB Filter
10%
16V
X5R-CERM
0201
(PCH DPLLB PWR)
PP1V05_S0_PCH_VCCADPLLB
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2266
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U1800.BF40:2.54MM
69 mA
20
SIZE
A
D
PAGE TITLE
PCH POWER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
22 OF 109
SHEET
20 OF 75
36
R2265
0
1 2
5%
1/16W
MF-LF
402
1
C2265
0.1UF
2
A
8 7 5 4 2 1
Page 21
www.laptopblue.vn
345678
2 1
BB50
BC11
G7
AA7
AA9
AA11
AA39
AA41
D
C
B
A
AA43
AA45
AB2
AB4
AB17
AB25
AB33
AB35
AB37
AB48
AB50
AC7
AC9
AC11
AC17
AC25
AC41
AC43
AC45
AE7
AE9
AE11
AE13
AE15
AE17
AE25
AE35
AE41
AE43
AE45
AF2
AF4
AF8
AF19
AF25
AF27
AF29
AF31
AF35
AF48
AF50
AG7
AG9
AG11
AG17
AG19
AG29
AG31
AG35
AG41
AG43
AG45
AH2
AJ7
AJ9
AJ11
AJ19
AJ33
AJ35
AJ39
AJ41
AJ43
AJ45
AK2
AK4
AK17
AK19
AK23
AK25
AK27
AK35
AK37
AK48
AK50
BA11
BA13
BA16
BA18
BA21
BA23
BA25
BA27
BA29
BA9 BB2
VSS_G7
VSS_AA7
VSS_AA9
VSS_AA11
VSS_AA39
VSS_AA41
VSS_AA43
VSS_AA45
VSS_AB2
VSS_AB4
VSS_AB17
VSS_AB25
VSS_AB33
VSS_AB35
VSS_AB37
VSS_AB48
VSS_AB50
VSS_AC7
VSS_AC9
VSS_AC11
VSS_AC17
VSS_AC25
VSS_AC41
VSS_AC43
VSS_AC45
VSS_AE7
VSS_AE9
VSS_AE11
VSS_AE13
VSS_AE15
VSS_AE17
VSS_AE25
VSS_AE35
VSS_AE41
VSS_AE43
VSS_AE45
VSS_AF2
VSS_AF4
VSS_AF8
VSS_AF19
VSS_AF25
VSS_AF27
VSS_AF29
VSS_AF31
VSS_AF35
VSS_AF48
VSS_AF50
VSS_AG7
VSS_AG9
VSS_AG11
VSS_AG17
VSS_AG19
VSS_AG29
VSS_AG31
VSS_AG35
VSS_AG41
VSS_AG43
VSS_AG45
VSS_AH2
VSS_AJ7
VSS_AJ9
VSS_AJ11
VSS_AJ19
VSS_AJ33
VSS_AJ35
VSS_AJ39
VSS_AJ41
VSS_AJ43
VSS_AJ45
VSS_AK2
VSS_AK4
VSS_AK17
VSS_AK19
VSS_AK23
VSS_AK25
VSS_AK27
VSS_AK35
VSS_AK37
VSS_AK48
VSS_AK50
VSS_BA11
VSS_BA13
VSS_BA16
VSS_BA18
VSS_BA21
VSS_BA23
VSS_BA25
VSS_BA27
VSS_BA29
VSS_BA9
U1800
FCBGA
(9 OF 10)
VSS
MOBILE-SFF
COUGAR-POINT
OMIT_TABLE
VSS_AL7
VSS_AL9
VSS_AL11
VSS_AL39
VSS_AL41
VSS_AL43
VSS_AL45
VSS_AM15
VSS_AM19
VSS_AM25
VSS_AM29
VSS_AM31
VSS_AM37
VSS_AP2
VSS_AP4
VSS_AP7
VSS_AP9
VSS_AP11
VSS_AP17
VSS_AP21
VSS_AP23
VSS_AP25
VSS_AP29
VSS_AP31
VSS_AP33
VSS_AP35
VSS_AP37
VSS_AP41
VSS_AP43
VSS_AP45
VSS_AP48
VSS_AP50
VSS_AR6
VSS_AR8
VSS_AR17
VSS_AR19
VSS_AR21
VSS_AR31
VSS_AR35
VSS_AR37
VSS_AT7
VSS_AT9
VSS_AT11
VSS_AT39
VSS_AT41
VSS_AT43
VSS_AT45
VSS_AU17
VSS_AU37
VSS_AV2
VSS_AV4
VSS_AV48
VSS_AV50
VSS_AW7
VSS_AW9
VSS_AW11
VSS_AW13
VSS_AW23
VSS_AW25
VSS_AW27
VSS_AW29
VSS_AW36
VSS_AW39
VSS_AW41
VSS_AW43
VSS_AW45
VSS_AY10
VSS_B6
VSS_B10
VSS_B14
VSS_B18
VSS_B22
VSS_B26
VSS_B30
VSS_B34
VSS_B38
VSS_B42
VSS_B46
VSS_BA7
VSS_BB48
VSS_BA31
VSS_BA34
VSS_BA36
VSS_BA39
VSS_BA41
VSS_BA43
VSS_BA45
VSS_BB4
VSS_BB2
AL7
AL9
AL11
AL39
AL41
AL43
AL45
AM15
AM19
AM25
AM29
AM31
AM37
AP2
AP4
AP7
AP9
AP11
AP17
AP21
AP23
AP25
AP29
AP31
AP33
AP35
AP37
AP41
AP43
AP45
AP48
AP50
AR6
AR8
AR17
AR19
AR21
AR31
AR35
AR37
AT7
AT9
AT11
AT39
AT41
AT43
AT45
AU17
AU37
AV2
AV4
AV48
AV50
AW7
AW9
AW11
AW13
AW23
AW25
AW27
AW29
AW36
AW39
AW41
AW43
AW45
AY10
B6
B10
B14
B18
B22
B26
B30
B34
B38
B42
B46
BA7
BB48
BA31
BA34
BA36
BA39
BA41
BA43
BA45
BB4
BC13
BC16
BC18
BC21
BC23
BC25
BC27
BC29
BC31
BC34
BC36
BC39
BC41
BC43
BC45
BD15
BD24
BE7
BE9
BE11
BE13
BE16
BE18
BE21
BE23
BE25
BE27
BE29
BE31
BE34
BE36
BE39
BE41
BE43
BE45
BF2
BF4
BF15
BF24
BF48
BF50
BH6
BH10
BH14
BH18
BH22
BH26
BH28
BH30
BH32
BH34
BH38
BH42
BH44
BH46
BH48
BK10
BK14
BK18
BK22
BK26
BK30
BK32
BK34
BK38
BK42
BK46
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
F48
F50
G11
G13
G16
G18
G21
G23
G25
G27
G29
G31
D6
F2
F4
G9
VSS_BB50
VSS_BC11
VSS_BC13
VSS_BC16
VSS_BC18
VSS_BC21
VSS_BC23
VSS_BC25
VSS_BC27
VSS_BC29
VSS_BC31
VSS_BC34
VSS_BC36
VSS_BC39
VSS_BC41
VSS_BC43
VSS_BC45
VSS_BD15
VSS_BD24
VSS_BE7
VSS_BE9
VSS_BE11
VSS_BE13
VSS_BE16
VSS_BE18
VSS_BE21
VSS_BE23
VSS_BE25
VSS_BE27
VSS_BE29
VSS_BE31
VSS_BE34
VSS_BE36
VSS_BE39
VSS_BE41
VSS_BE43
VSS_BE45
VSS_BF2
VSS_BF4
VSS_BF15
VSS_BF24
VSS_BF48
VSS_BF50
VSS_BH6
VSS_BH10
VSS_BH14
VSS_BH18
VSS_BH22
VSS_BH26
VSS_BH28
VSS_BH30
VSS_BH32
VSS_BH34
VSS_BH38
VSS_BH42
VSS_BH44
VSS_BH46
VSS_BH48
VSS_BK10
VSS_BK14
VSS_BK18
VSS_BK22
VSS_BK26
VSS_BK30
VSS_BK32
VSS_BK34
VSS_BK38
VSS_BK42
VSS_BK46
VSS_D6
VSS_D10
VSS_D14
VSS_D18
VSS_D22
VSS_D26
VSS_D30
VSS_D34
VSS_D38
VSS_D42
VSS_D46
VSS_F2
VSS_F4
VSS_F48
VSS_F50
VSS_G9
VSS_G11
VSS_G13
VSS_G16
VSS_G18
VSS_G21
VSS_G23
VSS_G25
VSS_G27
VSS_G29
VSS_G31
U1800
FCBGA
(10 OF 10)
VSS
MOBILE-SFF
COUGAR-POINT
OMIT_TABLE
8 7 5 4 2 1
VSS_G34
VSS_G36
VSS_G39
VSS_G41
VSS_G43
VSS_J7
VSS_J9
VSS_J11
VSS_J13
VSS_J16
VSS_J18
VSS_J21
VSS_J23
VSS_J25
VSS_J27
VSS_J29
VSS_J31
VSS_J34
VSS_J36
VSS_J39
VSS_J41
VSS_J45
VSS_K2
VSS_K4
VSS_K48
VSS_K50
VSS_L7
VSS_L9
VSS_L11
VSS_L13
VSS_L16
VSS_L18
VSS_L21
VSS_L23
VSS_L25
VSS_L27
VSS_L29
VSS_L31
VSS_L34
VSS_L36
VSS_L39
VSS_L41
VSS_L43
VSS_L45
VSS_N7
VSS_N9
VSS_N11
VSS_N13
VSS_N21
VSS_N23
VSS_N25
VSS_N29
VSS_N31
VSS_N34
VSS_N39
VSS_N41
VSS_N43
VSS_N45
VSS_P2
VSS_P4
VSS_P48
VSS_P50
VSS_R17
VSS_R21
VSS_R31
VSS_R37
VSS_T7
VSS_T9
VSS_T11
VSS_T13
VSS_T41
VSS_T43
VSS_T45
VSS_U31
VSS_U49
VSS_V2
VSS_V4
VSS_V7
VSS_V9
VSS_V11
VSS_V15
VSS_V17
VSS_V27
VSS_V29
VSS_V33
VSS_V35
VSS_V41
VSS_V43
VSS_V45
VSS_V48
VSS_Y15
VSS_Y17
VSS_Y33
VSS_Y35
VSS_Y37
36
G34
G36
G39
G41
G43
J7
J9
J11
J13
J16
J18
J21
J23
J25
J27
J29
J31
J34
J36
J39
J41
J45
K2
K4
K48
K50
L7
L9
L11
L13
L16
L18
L21
L23
L25
L27
L29
L31
L34
L36
L39
L41
L43
L45
N7
N9
N11
N13
N21
N23
N25
N29
N31
N34
N39
N41
N43
N45
P2
P4
P48
P50
R17
R21
R31
R37
T7
T9
T11
T13
T41
T43
T45
U31
U49
V2
V4
V7
V9
V11
V15
V17
V27
V29
V33
V35
V41
V43
V45
V48
Y15
Y17
Y33
Y35
Y37
SYNC_MASTER=K78_MLB
PAGE TITLE
PCH GROUNDS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
23 OF 109
SHEET
21 OF 75
SIZE
D
C
B
A
D
Page 22
www.laptopblue.vn
345678
2 1
16
7
D
=PP3V3_S0_PCH_VCCADAC
7
C
B
=PP1V05_S0_PCH
PLACE_NEAR=U1800.N36:2.54mm
L2406
10UH-0.12A-0.36OHM
1 2
0603
R2450
0
1 2
5%
1/20W
MF
201
C2450
10UF
CERM-X5R
PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm
=PP3V3_S0_PCH
19 16
7
=PP5V_S0_PCH
7
1 mA
=PP3V3_SUS_PCH
7
=PP5V_SUS_PCH
7
1 mA S0-S5
PLACE_NEAR=U1800.M37:2.54mm
R2415
PP1V05_S0_PCH_VCCCLKDMI_R
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
PLACE_NEAR=U1800.AP39:2.54mm
1
C2451
0.1UF
201
20%
10V
402
5%
MF
201
10
5%
MF
X5R-CERM
12
NC
1
2
12
1
2
10%
16V
0201
NC
20%
6.3V
2
0402
R2405
1/20W
C2439
1UF
R2404
C2438
0.1UF
100
10%
10V
X5R
402
1/20W
CERM
1 2
1
C2455
0.01UF
2
X5R-CERM
PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)
1
5
D2400
NC
BAT54DW-X-G
SOT-363
6
PP5V_S0_PCH_V5REF
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)
4
2
D2400
NC
BAT54DW-X-G
SOT-363
3
PP5V_SUS_PCH_V5REFSUS
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_SUS_PCH_V5REFSUS
1
5%
1/20W
MF
201
PP3V3_S0_PCH_VCCA_DAC_F
1
10%
16V
2
0201
PP1V05_S0_PCH_VCCCLKDMI_F
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
1
C2411
10UF
20%
6.3V
2
CERM-X5R
0402-1
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
NEED PWR CONSTRAINT
<1 MA
=PP5V_S0_PCH_V5REF
NEED PWR CONSTRAINT
20
<1 MA S0-S5
PCH VCCSUS3_3 BYPASS
(PCH SUSPEND USB 3.3V PWR)
=PP3V3_SUS_PCH_VCCSUS_USB
20
20
20
=PP3V3_S0_PCH_VCC3_3_CLK
7
20
7
1
2
PLACE_NEAR=U1800.R27:2.54mm
=PP1V05_S0_PCH_V_PROC_IO
20
7
PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm
PCH VCCIO BYPASS
=PP1V05_S0_PCH_VCC_DMI
20
7
PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)
PLACE_NEAR=U1800.AM23:2.54mm
R2451
1
1 2
PP3V3_S0_PCH_VCC3_3_CLK_R
5%
1/16W
MF-LF
402
C2484
0.1UF
10%
16V
X5R-CERM
0201
PLACE_NEAR=U1800.U27:2.54mm
C2416
4.7UF
1
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
=PP1V05_S0_PCH_VCCIO
20
7
1
C2413
0.1UF
10%
16V
2
X5R-CERM
0201
20%
6.3V
X5R
402
C2419
1UF
20%
6.3V
X5R
0201
1
C2429
1UF
20%
6.3V
2
X5R
0201
1
1
C2417
0.1UF
10%
16V
2
2
X5R-CERM
0201
10UH-0.12A-0.36OHM
1
C2414
1UF
20%
6.3V
2
X5R
0201
1
C2430
0.1UF
10%
16V
2
X5R-CERM
0201
L2451
1 2
0603
C2453
CERM-X5R
PLACE_NEAR=U1800.V37:2.54mm
1
C2407
1UF
20%
6.3V
2
X5R
0201
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
20
PLACE_NEAR=U1800.R12:2.54mm
PP3V3_S0_PCH_VCC3_3_CLK_F
20
10UF
20%
6.3V
0402-1
=PP1V8_S0_PCH_VCC_DFTERM
20 18
7
PLACE_NEAR=U1800.AJ15:2.54mm
PCH VCCSUSHDA BYPASS
(PCH HD Audio 3.3V/1.5V PWR)
=PP3V3R1V5_S0_PCH_VCCSUSHDA
20 16
7
PLACE_NEAR=U1800.V31:2.54mm
=PP3V3_S5_PCH_VCC_SPI
20
7
PLACE_NEAR=U1800.Y19:2.54mm
=PP3V3_S5_PCH_VCCDSW
7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
1
C2463
1UF
20%
6.3V
2
X5R
0201
C2401
10UF
6.3V
CERM-X5R
0402
PLACE_NEAR=U1800.V37:2.54mm
1
20%
2
C2499
0.1UF
X5R-CERM
0201
1
C2454
1UF
20%
6.3V
2
X5R
0201
10%
16V
1
2
1
C2441
0.1UF
10%
16V
2
X5R-CERM
0201
1
C2442
1UF
20%
6.3V
2
X5R
0201
1
2
C2440
0.1UF
10%
16V
X5R-CERM
0201
PLACE_NEAR=U1800.AC35:2.54mm
PLACE_NEAR=U1800.AJ17:2.54mm
=PP1V05_S0_PCH_VCCIO_SATA
20 16
7
PLACE_NEAR=U1800.AG13:2.54mm
=PP1V05_S0_PCH_VCCSSC
20
7
=PP1V05_S0_PCH_VCCDIFFCLK
20 16
7
PLACE_NEAR=U1800.AE37:2.54mm
PCH VCCIO BYPASS
(PCH USB 1.05V PWR)
=PP1V05_S0_PCH_VCCIO_USB
20
7
PLACE_NEAR=U1800.U23:2.54mm
=PP1V05_S0_PCH_VCC_CORE
20
7
1
C2481
1UF
20%
6.3V
2
X5R
0201
=PP1V05_S0_PCH_VCCIO_CLK
20
7
1
C2444
1UF
20%
6.3V
2
X5R
0201
1
2
1
C2482
1UF
20%
6.3V
2
X5R
0201
PLACE_NEAR=U1800.AC21:2.54mm
PLACE_NEAR=U1800.AF23:2.54mm
PLACE_NEAR=U1800.AJ25:2.54mm
PLACE_NEAR=U1800.AK33:2.54mm
1
C2452
1UF
20%
6.3V
2
X5R
0201
C2475
1UF
20%
6.3V
X5R
0201
1
C2434
1UF
20%
6.3V
2
X5R
0201
PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)
1
C2483
1UF
20%
6.3V
2
X5R
0201
1
C2469
1UF
20%
6.3V
2
X5R
0201
PLACE_NEAR=U1800.AC13:2.54mm
=PP3V3_SUS_PCH_VCCSUS_GPIO
20
7
PLACE_NEAR=U1800.U33:2.54mm
1
C2446
1UF
20%
6.3V
2
X5R
0201
1
C2460
10UF
20%
6.3V
2
CERM-X5R
0402
1
C2476
1UF
20%
6.3V
2
X5R
0201
D
C
B
=PP3V3_S0_PCH_VCC3_3_PCI
20
7
1
C2421
0.1UF
10%
16V
2
X5R-CERM
PLACE_NEAR=U1800.BK28:2.54mm
0201
A
=PP3V3_S0_PCH_VCC3_3_HVCMOS
20
7
1
C2424
0.1UF
10%
16V
2
X5R-CERM
PLACE_NEAR=U1800.T39:2.54mm
0201
8 7 5 4 2 1
=PP3V3_S0_PCH_VCC3_3_SATA
20
7
PLACE_NEAR=U1800.AF6:2.54mm
=PP3V3_S0_PCH_VCC3_3_GPIO
20
7
PLACE_NEAR=U1800.AC19:2.54mm
1
C2486
0.1UF
10%
16V
2
X5R-CERM
0201
1
C2423
0.1UF
10%
16V
2
X5R-CERM
0201
1
2
C2485
0.1UF
10%
16V
X5R-CERM
0201
PLACE_NEAR=U1800.R40:2.54mm
=PP1V05_S0_PCH_VCCASW
20
7
1
C2426
1UF
20%
6.3V
2
X5R
0201
1
C2456
1UF
20%
6.3V
2
X5R
0201
1
C2496
1UF
20%
6.3V
2
X5R
0201
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
C2428
22UF
6.3V
X5R-CERM1
0603
SIZE
A
D
C2420
22UF
6.3V
X5R-CERM1
0603
1
20%
2
1
20%
2
SYNC_MASTER=K78_MLB
PAGE TITLE
PCH DECOUPLING
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
24 OF 109
SHEET
22 OF 75
36
Page 23
www.laptopblue.vn
PROCESSOR MICRO2-XDP CONNECTOR
NOTE: This is not the standard XDP pinout
Use with 920-0782 Adapter Flex to support chipset debug
=PP3V3_S0_XDP
D
1K
201
1K
201
MF
MF
5%
MF-LF
5%
MF-LF
5%
MF-LF
5%
MF-LF
1 2
5%
MF-LF
1 2
5%
MF-LF
5%
MF-LF
5%
MF-LF
0
1 2
0
1 2
0
1 2
0
1 2
0
0
0
1 2
0
1 2
1/20W
R2502
1 2
5%
1/20W
1 2
5%
5%
5%
R2564
R2565
R2566
R2567
R2560
R2561
R2562
R2563
XDP
R2500
1 2
XDP
R2501
1 2
XDP_BPM_L<4>
IN
XDP_BPM_L<5>
IN
XDP_BPM_L<6>
IN
XDP_BPM_L<7>
IN
CPU_CFG<12>
IN
CPU_CFG<13>
IN
CPU_CFG<14>
IN
CPU_CFG<15>
IN
PLACE_NEAR=U1000.B46:1MM
C
PLACE_NEAR=U1000.B50:2.54MM
CPU_PWRGD
IN
PLACE_NEAR=U4900.D10:2.54MM
OUT
CPU_CFG<0>
OUT
PM_PCH_SYS_PWROK
OUT
PM_PWRBTN_L
XDP
0
MF
201
XDP
R2504
MF-LF
XDP_CPU:BPM
1/16W
402
XDP_CPU:BPM
1/16W
402
XDP_CPU:BPM
1/16W
402
XDP_CPU:BPM
1/16W
402
XDP_CPU:CFG
1/16W
402
XDP_CPU:CFG
1/16W
402
XDP_CPU:CFG
1/16W
402
XDP_CPU:CFG
1/16W
402
1/20W
910
1/16W
402
XDP_CPU_PREQ_L
BI
XDP_CPU_PRDY_L
IN
XDP_BPM_L<0>
IN
XDP_BPM_L<1>
IN
XDP_BPM_L<2>
IN
XDP_BPM_L<3>
IN
CPU_CFG<10>
IN
CPU_CFG<11>
IN
XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>
XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
XDP_CPU_CFG<0>
XDP_VR_READY
=SMBUS_XDP_SDA
BI
=SMBUS_XDP_SCL
IN
XDP_CPU_TCK
OUT
=PPVCCIO_S0_XDP
NOSTUFF
1
R2540
1K
5%
1/16W
MF-LF
402
2
OBSFN_A0
OBSFN_A1 OBSFN_C1
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSFN_B0
OBSFN_B1
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
XDP
1
C2500
0.1UF
10%
16V
2
X5R
402
Even pins should be facing edge of the board
PCH MICRO2-XDP CONNECTOR
NOTE: This is not the standard XDP pinout
Use with 920-0782 Adapter Flex to support chipset debug
=PP3V3_S5_XDP
B
PLACE_NEAR=U1800.H4:2.54MM
PCH_GPIO59_OC0_L
IN
PLACE_NEAR=U1800.A17:2.54MM
USB_HUB_SOFT_RESET_L
IN
PLACE_NEAR=U1800.A13:2.54MM
SDCONN_STATE_RST_L
IN
PLACE_NEAR=U1800.D16:2.54MM
ENET_PWR_EN
IN
PLACE_NEAR=U1800.B16:2.54MM
SDCONN_STATE_CHANGE
IN
PLACE_NEAR=J2550.39:2.54MM
ALL_SYS_PWRGD
IN
PLACE_NEAR=U4900.D10:2.54MM
PM_PWRBTN_L
OUT
A
XDP
5%
5%
5%
5%
5%
5%
MF-LF
5%
MF
MF
MF
MF
MF
MF
R2582
0
1 2
XDP
R2580
0
1 2
XDP
R2586
0
1 2
XDP
R2587
0
1 2
XDP
R2581
0
1 2
XDP
R2584
1K
1 2
XDP
R2585
0
1 2
201
201
201
201
201
402
201
1/20W
1/20W
1/20W
1/20W
1/20W
1/16W
1/20W
TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>
XDP_PCH_GPIO59_OC0_L
XDP_PCH_USB_HUB_SOFT_RST_L
XDP_PCH_SDCONN_STATE_RST_L
XDP_PCH_ENET_PWR_EN
TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>
PCH_GPIO43_OC4_L
IN
XDP_PCH_SDCONN_DET_L
PCH_GPIO10_OC6_L
IN
PCH_GPIO14_OC7_L
IN
XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
=SMBUS_XDP_SDA
BI
=SMBUS_XDP_SCL
IN
XDP_PCH_TCK
OUT
Even pins should be facing edge of the board
OBSFN_A0
OBSFN_A1
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSFN_B0
OBSFN_B1
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
C2580
TCK1
TCK0
0.1UF
SDA
SCL
XDP
1
10%
16V
2
X5R
402
8 7 5 4 2 1
XDP_CONN
CRITICAL
J2500
DF40RC-60DP-0.4V
M-ST-SM
62
61
1
2
3
4
5
6
78
10
9
1112
1314
1516
1718
19
20
2122
2324
2526
2728
29
30
3132
3334
3536
3738
39
40
4142
4344
4546
4748
49
50
5152
5354
NC
5556
5758
59
60
6364
998-2516
XDP_CONN
CRITICAL
J2550
DF40RC-60DP-0.4V
M-ST-SM
62
61
1
2
3
4
5
6
78
10
9
1112
1314
1516
1718
19
20
2122
2324
2526
2728
29
30
3132
3334
3536
3738
39
40
4142
4344
4546
4748
49
50
5152
5354
NC
5556
5758
59
60
6364
998-2516
OBSFN_C0
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
1
C2501
0.1UF
10%
16V
2
X5R
402
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
1
C2581
0.1UF
10%
16V
2
X5R
402
PCH_GPIO15
SMC_IG_THROTTLE_L
XDP_PCH_ISOLATE_CPU_MEM_L
PCH_GPIO35
DP_AUXCH_ISOL
SATARDRVR_EN
TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>
PCH_GPIO36_SATA2GP
JTAG_ISP_TCK
XDP_PCH_AUD_IPHS_SWITCH_EN
ENET_LOW_PWR
TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5
XDPPCH_PLTRST_L
XDP_DBRESET_L
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS
CPU_CFG<16>
CPU_CFG<17>
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
XDP_CPURST_L
XDP_DBRESET_L
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
5%
MF
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
XDP
R2515
0
1 2
5%
MF
201
XDP
R2516
0
1 2
5%
MF
201
XDP
R2505
1K
1 2
5%
MF
201
XDP
R2578
0
1 2
1/20W
201
XDP
R2579
0
1 2
5%
MF
1K series R on PCH Support P. 28
345678
PLACE_NEAR=R1841.1:2.54MM
1/20W
ITPXDP_CLK100M_P
PLACE_NEAR=R1840.1:2.54MM
1/20W
ITPXDP_CLK100M_N
PLACE_NEAR=R1125.1:2.54MM
1/20W
CPU_RESET_L
PLACE_NEAR=U1800.G1:2.54MM
ISOLATE_CPU_MEM_L
PLACE_NEAR=U1800.AA3:2.54MM
1/20W
AUD_IPHS_SWITCH_EN_PCH
201
36
PLACE_NEAR=J2500.52:2.54MM
XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
PLACE_NEAR=U1000.J58:2.54MM
IN
IN
IN
PLACE_NEAR=J2550.52:2.54MM.
XDP_PCH_TDO
XDP_PCH_TDI
XDP_PCH_TMS
XDP_PCH_TCK
IN
IN
2 1
DESIGN NOTE:
ODT AVAILABLE ON JTAG
PLACEMENT NOTE:
PLACE TDO TERM NEAR
SNB XDP CONN
PLACEMENT NOTE:
PLACE TDO TERM NEAR
PCH XDP CONN
SYNC_MASTER=K21_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
R2510
R2513
R2550
XDP
1/16W
MF-LF
XDP
1/20W
1
51
5%
402
2
1
51
5%
MF
201
2
XDP
1
51
5%
1/16W
MF-LF
402
2
PLACE_NEAR=U1000.M60
PLACE_NEAR=U1000.L56:2.54MM
R
PLACE_NEAR=U1000.L55:2.54MM
XDP
1
R2511
R2514
R2551
PLACE_NEAR=U1800.U12:2.54MM
PLACE_NEAR=U1800.M17:2.54MM
51
5%
1/16W
MF-LF
402
2
XDP
1
51
5%
1/20W
MF
201
2
XDP
1
51
5%
1/20W
MF
201
2
R2512
PLACEMENT NOTE:
PLACE TCK/TDI/TMS/TRST*
TERM NEAR CPU
R2552
R2556
PLACEMENT NOTE:
PLACE TCK/TDI/TMS/TRST*
TERM NEAR PCH
CPU & PCH XDP
Apple Inc.
=PPVCCIO_S0_XDP
XDP
1
51
5%
1/16W
MF-LF
402
2
=PP1V05_SUS_PCH_JTAG
XDP
1
51
5%
1/20W
PLACE_NEAR=U1800.M15:2.54MM
MF
201
2
XDP
1
51
5%
1/20W
MF
201
2
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
25 OF 109
SHEET
23 OF 75
3.13.0
SIZE
D
C
B
A
D
Page 24
www.laptopblue.vn
345678
BOM GROUP
=PP3V3_S3_USB_HUB
24 8 7
D
CRITICAL
Y2600
24.000M-150PPM-6PF
CRITICAL
C2619
18PF
5%
25V
NP0-C0G
HUB1_NONREM1_1
R2601
HUB1_NONREM1_0
R2602
C
24 8 7
HUB1_NONREM0_1
1
1
R2603
10K
10K
5%
5%
1/20W
1/20W
MF
MF
201
201
2
2
HUB1_NONREM0_0
1
1
R2604
10K
10K
5%
5%
1/20W
1/20W
MF
MF
201
201
2
2
=PP3V3_S3_USB_HUB
201
1 2
2X1.6X0.65-SM
1
R2630
1M
1 2
2
5%
1/20W
MF
201
CRITICAL
BYPASS=U2650.5::5mm
1
C2652
4.7UF
20%
6.3V
2
X5R-CERM1
402
B
CRITICAL
Y2650
24.000M-150PPM-6PF
1 2
2X1.6X0.65-SM
1
R2680
1M
1 2
2
5%
1/20W
MF
201
CRITICAL
HUB2_NONREM1_1
R2651
10K
1/20W
HUB2_NONREM1_0
R2652
10K
1/20W
CRITICAL
C2669
18PF
5%
25V
NP0-C0G
HUB2_NONREM0_1
1
1
R2653
10K
5%
5%
1/20W
MF
MF
201
201
2
2
HUB2_NONREM0_0
1
1
R2654
10K
5%
5%
1/20W
MF
MF
201
201
2
2
201
A
BYPASS=U2600.5::5mm
1
C2602
4.7UF
20%
6.3V
2
X5R-CERM1
402
BYPASS=U2600.23::5mm
1
C2607
4.7UF
20%
6.3V
2
X5R-CERM1
402
CRITICAL
1
C2620
18PF
5%
25V
2
NP0-C0G
201
BYPASS=U2650.23::2mm
1
C2653
0.1UF
10%
16V
2
X5R-CERM
0201
BYPASS=U2650.23::5mm
1
C2657
4.7UF
20%
6.3V
2
X5R-CERM1
402
CRITICAL
1
C2670
18PF
5%
25V
2
NP0-C0G
201
BYPASS=U2600.34::2mm
1
C2603
0.1UF
10%
16V
2
X5R-CERM
0201
BYPASS=U2600.29::2mm
1
C2608
0.1UF
10%
16V
2
X5R-CERM
0201
R2605
100
1 2
5%
1/20W
MF
201
1
R2606
10K
5%
1/20W
MF
201 201
2
1
C2661
0.1UF
10%
16V
2
X5R-CERM
0201
1
C2658
0.1UF
10%
16V
2
X5R-CERM
0201
R2655
100
1 2
5%
1/20W
MF
201
1
R2656
10K
5%
1/20W
MF
201
2
BYPASS=U2600.23::2mm
1
C2611
0.1UF
X5R-CERM
C2612
10%
16V
2
0201
X5R-CERM
BYPASS=U2600.5::2mm
1
C2609
0.1UF
X5R-CERM
C2610
10%
16V
2
0201
X5R-CERM
USB_HUB1_TEST
USB_HUB_RESET_L
24
USB_HUB1_XTAL1
USB_HUB1_XTAL2
USB_HUB1_NONREM0
USB_HUB1_NONREM1
USB_HUB1_CFG_SEL0
USB_HUB1_CFG_SEL1
1
R2607
10K
5%
1/20W
MF
2
BYPASS=U2650.34::2mm
C2662
0.1UF
X5R-CERM
1
10%
16V
2
0201
BYPASS=U2650.15::2mm
BYPASS=U2650.10::2mm
BYPASS=U2650.29::2mm
1
C2659
0.1UF
X5R-CERM
C2660
10%
16V
2
0201
X5R-CERM
USB_HUB2_TEST
USB_HUB_RESET_L
24
USB_HUB2_XTAL1
USB_HUB2_XTAL2
USB_HUB2_NONREM0
USB_HUB2_NONREM1
USB_HUB2_CFG_SEL0
USB_HUB2_CFG_SEL1
1
R2657
10K
5%
1/20W
MF
201
2
BYPASS=U2600.15::2mm
1
0.1UF
10%
16V
2
0201
BYPASS=U2600.10::2mm
1
0.1UF
10%
16V
2
0201
11
26
33
32
28
22
24
25
BYPASS=U2650.5::2mm
1
0.1UF
10%
16V
2
0201
11
26
33
32
28
22
24
25
1015232936
5
VDD33
OMIT_TABLE
SYM VER 1
U2600
USB2513B
TEST
RESET*
XTALIN/CLKIN
XTALOUT
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
THRM_PAD
1015232936
5
VDD33
OMIT_TABLE
SYM VER 1
U2650
USB2513B
TEST
RESET*
XTALIN/CLKIN
XTALOUT
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
THRM_PAD
PPUSB_HUB1_CRFILT
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
PPUSB_HUB1_PLLFILT
14
34
CRFILT
PLLFILT
QFN
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
37
PPUSB_HUB2_CRFILT
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
PPUSB_HUB2_PLLFILT
14
34
CRFILT
PLLFILT
QFN
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
37
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
OCS1*
IPU
OCS2*
IPU
OSC3*
IPU
IPU
RBIAS
VBUS_DET
USBDM_UP
USBDP_UP
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
OCS1*
IPU
OCS2*
IPU
OSC3*
IPU
IPU
RBIAS
VBUS_DET
USBDM_UP
USBDP_UP
1
2
3
4
6
7
8
NC
NC
9
NC
NC
12
16
18
20
NC
13
17
19
21
NC
35
27
30
31
1
2
3
4
6
7
8
NC
NC
9
NC
NC
12
16
18
20
NC
13
17
19
21
NC
35
27
30
31
1
C2615
0.1UF
10%
16V
2
X5R-CERM
0201
USB_T29A_N
USB_T29A_P
USB_SDCARD_N
USB_SDCARD_P
USB_EXTD_N
USB_EXTD_P
TP_USB_HUB1_PRTPWR1
NC_USB_HUB1_PRTPWR2
NC_USB_HUB1_PRTPWR3
NC_USB_HUB1_PRTPWR4
TP_USB_HUB1_OCS1
NC_USB_HUB1_OCS2
USB_EXTD_OC_L
=USB_HUB1_OCS4
USB_HUB1_RBIAS
USB_HUB1_VBUS_DET
USB_HUB1_UP_N
USB_HUB1_UP_P
1
C2665
0.1UF
10%
16V
2
X5R-CERM
0201
USB_BT_N
USB_BT_P
USB_TPAD_HUB_N
USB_TPAD_HUB_P
USB_EXTA_N
USB_EXTA_P
TP_USB_HUB2_PRTPWR1
NC_USB_HUB2_PRTPWR2
NC_USB_HUB2_PRTPWR3
NC_USB_HUB2_PRTPWR4
TP_USB_HUB2_OCS1
NC_USB_HUB2_OCS2
USB_EXTA_OC_L
=USB_HUB2_OCS4
USB_HUB2_RBIAS
USB_HUB2_VBUS_DET
USB_HUB2_UP_N
USB_HUB2_UP_P
1
2
BI
BI
BI
BI
BI
BI
1
2
C2616
1UF
20%
6.3V
X5R
0201
BI
BI
C2666
1UF
20%
6.3V
X5R
0201
BI
BI
69 8
69 8
69 33
69 33
69 40 6
69 40 6
IN
IN
69 18
69 18
BI
BI
49
BI
49
BI
BI
BI
IN
IN
69 18
69 18
1
C2617
0.1UF
10%
16V
2
X5R-CERM
0201 0201
T29
SDCARD(NA to K78)
LIO External D
40 6
8
CRITICAL
1
R2600
12K
1%
1/20W
MF
201
2
1
C2667
0.1UF
10%
16V
2
X5R-CERM
0201
69 37 6
BlueTooth
69 37 6
Trackpad/Keyboard
69 39
Right USB A
69 39
39
8
CRITICAL
1
R2650
12K
1%
1/20W
MF
201
2
8 7 5 4 2 1
HUB1_ALLREM
HUB1_1NONREM
HUB1_2NONREM
HUB1_3NONREM
HUB2_ALLREM
HUB2_1NONREM
HUB2_2NONREM
HUB2_3NONREM
1
C2618
1UF
20%
6.3V
2
X5R
=PP3V3_S3_USB_HUB
1
R2620
10K
5%
1/20W
MF
201
2
1
C2668
1UF
20%
6.3V
2
X5R
0201
=PP3V3_S3_USB_HUB
1
R2670
10K
5%
1/20W
MF
201
2
NON_REM1 NON_REM0 DESCRIPTION
0 0 All ports are removable
0 1 Port 1 is non removable
1 0 Port 1 and 2 are non removable
1 1 Port 1, 2, and 3 are non removable
BOM TABLE
PART#
338S0720
338S0824
338S0923
24 8 7
=PP3V3_S3_USB_RESET
7
=PP3V3_S5_USB_RESET
7
1
R2642
100K
5%
1/20W
MF
201
2
23 18
24 8 7
USB_HUB_SOFT_RESET_L
IN
DESCRIPTION
QTY
SMSC USB2514
2
2
SMSC USB2514B
SMSC USX2513B
2
1 2
NOSTUFF
1
C2641
100PF
5%
25V
2
CERM
201
P3V3S3_EN_RC
1
C2640
0.47UF
10%
6.3V
2
CERM-X5R
402
R2640
20K
5%
1/20W
MF
201
36
2 1
BOM OPTIONS
HUB1_NONREM1_0,HUB1_NONREM0_0
HUB1_NONREM1_0,HUB1_NONREM0_1
HUB1_NONREM1_1,HUB1_NONREM0_0
HUB1_NONREM1_1,HUB1_NONREM0_1
HUB2_NONREM1_0,HUB2_NONREM0_0
HUB2_NONREM1_0,HUB2_NONREM0_1
HUB2_NONREM1_1,HUB2_NONREM0_0
HUB2_NONREM1_1,HUB2_NONREM0_1
REFERENCE DESIGNATOR(S)
U2600,U2650
U2600,U2650
U2600,U2650
USB_HUB_RESET
6
D
Q2640
2
2N7002DW-X-G
G
S
SOT-363
1
R2690
0
1 2
USB_HUB_SOFT_RESET_L_R
5%
1/20W
MF
201
SYNC_MASTER=K21_MLB
PAGE TITLE
5
USB HUBS
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
R
G
1
2
3
D
S
4
BAT54XV2T1
R2641
10K
5%
1/20W
MF
201
D2600
CRITICAL
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
USBHUB_2514
USBHUB_2514B
USBHUB_2513B
USB_HUB_RESET_L
Q2640
2N7002DW-X-G
SOT-363
SOD-523
12
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
26 OF 109
SHEET
3.13.0
24 OF 75
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
C
B
A
SIZE
D
.
Page 25
www.laptopblue.vn
345678
2 1
D
C
GreenClk 25MHz Power
Powered in S0
SB XTAL Power
T29 XTAL Power
=PP3V3_S0_SYSCLKGEN
7
=PPVDDIO_S0_SBCLK
7
=PPVDDIO_T29_CLK
7
C2705
12PF
12
5%
25V
NP0-C0G
NC
201
NC
C2706
12PF
1 2
5%
25V
NP0-C0G
201
System RTC Power Source & 32kHz / 25MHz Clock Generator
=PPVBAT_G3_SYSCLK
7
Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
=PP3V3_S5_SYSCLK
7
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
C2724
0.1UF
X5R-CERM
SYSCLK_CLK25M_X2
1 3
CRITICAL
2 4
Y2705
25.000MHZ-12PF-20PPM
SM-3.2X2.5MM
NOTE: 30 PPM crystal required
No Coin-Cell: 3.3V S5
C2722
0.1UF
X5R-CERM
R2705
0
1 2
5%
1/20W
MF
201
1
10%
16V16V
2
0201
Ground VDDIO of unused CLK
outputs for power savings
SYSCLK_CLK25M_X2_R
NO STUFF
1
R2706
1M
5%
1/20W
MF
201
2
SYSCLK_CLK25M_X1
1
10%
2
0201
No bypass necessary
1
C2702
1UF
10%
10V
2
X5R
402-1
11
VDDIO_25M_A
6
VDDIO_25M_B
14
VDDIO_25M_C
3
X2
4
X1
5
VDD_25M
SLG3NB148V
CRITICAL
2
+V3.3A
U2700
TQFN
VDD_RTC_OUT
GND
7
10
16
32KHZ_A
25MHZ_A
25MHZ_B
25MHZ_C
THRM
PAD
17
13
+3.42V
VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
12
9
8
15
1
NC
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_T29
=PPVRTC_G3_OUT
For SB RTC Power
1
C2710
1UF
10%
10V
2
X5R
402-1
Platform Reset Connections
Unbuffered
R2781
33
PLT_RESET_L
26 18
IN
MAKE_BASE=TRUE
70 16
OUT
70 16
OUT
70 34
OUT
7
=PP3V3_S0_RSTBUF
7
2
NC
1
C2780
0.1UF
10%
16V
2
X5R-CERM
0201
1
NC
5
U2780
74LVC1G07
SC70
4
3
Buffered
PLT_RST_BUF_L
MAKE_BASE=TRUE
1
R2780
100K
5%
1/20W
MF
201
2
1 2
5%
1/20W
MF
201
R2771
0
1 2
5%
1/20W
MF
201
R2782
0
1 2
5%
1/20W
MF
201
R2783
1 2
R2788
1 2
R2789
1 2
R2793
1 2
LPC_RESET_L
LPCPLUS_RESET_L
MAKE_BASE=TRUE
33
SMC_LRESET_L
5%
1/20W
MF
201
SDCARD_PLT_RST_L
0
AP_RESET_L
5%
1/20W
MF
201
PCA9557D_RESET_L
XDP
1K
XDPPCH_PLTRST_L
5%
1/20W
MF
201
=T29_RESET_L
Series R is R3803
0
BKLT_PLT_RST_L
5%
1/20W
MF
201
CPU_RESET_L
VTT voltage divider on CPU page
70
OUT
43
6
OUT
41
OUT
D
33
OUT
37
OUT
31
OUT
23
OUT
36
OUT
66
OUT
C
23 10
OUT
NO STUFF
C2760
0.1UF
10%
16V
X5R-CERM
0201
SYS_PWROK_R
R2763
0
1 2
5%
1/20W
MF
201
R2760
0
1 2
5%
1/20W
MF
201
25
7
R2762
3.0K
1 2
5%
1/20W
MF
201
PLACE_NEAR=U1800.M10:5.54mm
NO STUFF
1
R2761
0
5%
1/20W
MF
201
2
PM_PCH_SYS_PWROK
PM_PCH_PWROK
MAKE_BASE=TRUE
PM_PCH_APWROK
PCH Reset Button
=PP3V3_S0_SB_PM
25
7
1
R2795
10K
23 17
OUT
XDP_DBRESET_L
19 17
OUT
17
OUT
XDP
R2796
1 2
1/16W
402
MF-LF
5%
1/16W
MF-LF
402
2
0
5%
PM_SYSRST_L
NO STUFF
1
R2797
0
5%
1/16W
MF-LF
402
2
SILK_PART=SYS RESET
41 17 67 23 10
BIIN
B
PCH S0 PWRGD
=PP3V3_S5_PCHPWRGD
25
7
=PP3V3_S0_SB_PM
25
7
1
C2750
0.1UF
10%
16V
2
X5R-CERM
0201
5
MC74VHC1G08
1
2
U2750
SC70-HF
4
PM_S0_PGOOD
3
1
2
62 52 41 23
1
R2750
1K
5%
1/20W
MF
201
2
ALL_SYS_PWRGD
IN
CPUIMVP_PGOOD
57
IN
B
SMC_DELAYED_PWRGD
41 36
U2760
5
MC74VHC1G08
SC70-HF
3
=PP3V3_S5_PCHPWRGD
1
2
4
CLOCK (CK505)
UNUSED clock terminations for FCIM MODE
PCH_CLK14P3M_REFCLK
69 16
PCIE_CLK100M_PCH_N
69 16
PCIE_CLK100M_PCH_P
69 16
PCH_CLK100M_SATA_N
69 16
PCH_CLK100M_SATA_P
69 16
PCH_CLK96M_DOT_N
A
69 16
69 16
PCH_CLK96M_DOT_P
1
R2757
10K
2
PLACE_NEAR=U1800.G51:5.1mm
LPC_CLK33M_SMC_R
70 18
IN
1
1
1
1
1
R2751
R2752
R2753
10K
5%
1/20W
MF
201
10K
5%
5%
1/20W
1/20W
MF
MF
201
201
2
2
10K5%10K
5%
1/20W
MF
201
2
R2754
1/20W
MF
201
2
R2755
10K
5%
1/20W
MF
201 201
2
1
R2756
10K
2
5%
1/20W
MF
18
18
IN
IN
PLACE_NEAR=U1800.G45:2.54MM:5.1mm
PCH_CLK33M_PCIOUT
PLACE_NEAR=U1800.E49:5.1mm
LPC_CLK33M_LPCPLUS_R
8 7 5 4 2 1
R2727
22
1 2
5%
1/20W
MF
201
R2726
22
1 2
5%
1/20W
MF
201
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
R2729
22
1 2
5%
1/20W
MF
201
36
PCH_CLK33M_PCIIN
SIZE
A
D
70 41
OUT
70 43
6
OUT
69 16
OUT
SYNC_MASTER=K78_MLB
PAGE TITLE
Clock (CK505) and Chipset Support
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
SHEET
SYNC_DATE=11/29/2010
3.13.0
27 OF 109
25 OF 75
Page 26
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
D
C
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
=PP3V3_S3_MEMRESET
7
CPUMEM_S0
CPUMEM_S0
Q2800
SSM6N37FEAPE
CPUMEM_S0
R2890
0
ISOLATE_CPU_MEM_L
19 23
IN
=PP5V_S3_MEMRESET
7
26
CPUMEM_S0
R2815
100K
1/20W
201
12
ISOLATE_CPU_MEM_L_R
5%
1/20W
MF
201
1
5%
MF
2
CPUMEM_S0
Q2815
SSM6N37FEAPE
SOT563
D
6
2
S G
1
CPUMEM_S0
CPUMEM_S0
Q2800
SSM6N37FEAPE
B
1
C2817
0.047UF
10%
16V
2
X7R
402
10
IN
=MEM_RESET_L
MEMRESET_ISOL_LS5V_L
CPU_MEM_RESET_L
MAKE_BASE=TRUE
SSM6N37FEAPE
CPUMEM_S3
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN
S0
0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to
2 0 0 1 1 1 1 0 1
3 0 0 0 1 X 1 0 0
S3
4 0 0 1 1 X 1 0 1
A
5 0 1 1 1 0 (*) 1 1 1
to
6 0 1 1 1 1 1 1 1
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
S0
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
8 7 5 4 2 1
R2801
100K
5%
1/20W
MF
201
SOT563
5
R2802
100K
5%
1/20W
MF
201
SOT563
2
CPUMEM_S0
Q2815
5
SOT563
S G
4
R2817
0
1 2
5%
1/20W
MF
201
17 41 49 62
IN
1
SSM6N37FEAPE
2
P1V5CPU_EN_L
3
D
SG
4
1
SSM6N37FEAPE
2
MEMVTT_EN_L
6
D
SG
1
CPUMEM_S0
1
R2816
20K
2
D
3
PM_SLP_S4_L
CPUMEM_S0
Q2805
SOT563
CPUMEM_S0
Q2810
SOT563
5%
1/20W
MF
201
MEM_RESET_L
www.laptopblue.vn
CPUMEM_S0
1
R2805
10K
5%
1/20W
MF
201
2
P1V5CPU_EN
6
D
2
SG
1
D
Q2805
SSM6N37FEAPE
SOT563
5
S G
CPUMEM_S0
1
2
6
D
SG
1
D
Q2810
SSM6N37FEAPE
SOT563
5
S G
NOSTUFF
C2816
0.1UF
X5R-CERM
CPUMEM_S0
PM_SLP_S3_L
R2810
10K
5%
1/20W
MF
201
MEMVTT_EN
CPUMEM_S0
PLT_RESET_L
1
10%
16V
2
0201
3
4
2
3
4
=PP1V5_S3_MEMRESET
345678
2 1
D
1V5 S0 "PGOOD" for CPU
=PP3V3_S5_CPU_VCCDDR
7
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
=PP1V5_S3_CPU_VCCDDR
7
10 12 15
61
OUT
1
R2820
27.4K
1%
1/20W
MF
201
2
P1V5_S0_DIV
NO STUFF
1
R2821
33.2K
1%
1/20W
MF
201
17 41 62
IN
8
OUT
2
C2820
1000PF
10%
16V
X7R
201
1
2
1
2
PM_MEM_PWRGD_L
3
5
4
R2822
10K
5%
1/20W
MF
201
CRITICAL
Q2820
DMB53D0UV
SOT-563
CRITICAL
G
2
PM_MEM_PWRGD
6
D
Q2820
DMB53D0UV
SOT-563
S
1
10 17 67
OUT
C
MEMVTT Clamp
Ensures CKE signals are held low in S3
=PPVTT_S0_VTTCLAMP
7
18 25
IN
7
27 28 29 30
OUT
=PP5V_S3_MEMRESET
7
26
SSM6N37FEAPE
=DDRVTT_EN
8
56
IN
CPUMEM_S0
R2851
CPUMEM_S0
Q2850
SOT563
5
100K
1/20W
201
1
5%
MF
2
D
SG
CPUMEM_S0
SSM6N37FEAPE
VTTCLAMP_EN
NO STUFF
3
C2851
1000PF
4
Q2850
SOT563
10%
16V
X7R
201
2
1
2
VTTCLAMP_L
6
D
SG
1
CPUMEM_S0
SYNC_MASTER=K21_MLB
PAGE TITLE
R2850
1/10W
MF-LF
603
1
10
5%
2
75mA max load @ 0.75V
60mW max power
CPU Memory S3 Support
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
28 OF 109
SHEET
26 OF 75
SIZE
B
A
D
36
Page 27
www.laptopblue.vn
345678
2 1
D
PP0V75_S3_MEM_VREFCA_A
27 28 29 30 31 68
K10M2M10
FBGA
J10
=PP1V5_S3_MEM_A
7
27 28 32
B10C2E3
VDDQ
OMIT_TABLE
DM/TDQS
NF/TDQS*
B3D2B9
L10
N10
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
VSSQ
DQ0
DQ1
DQ2
DQ3
DQS
DQS*
NC
C10
E10
D10
B4
MEM_A_DQ<7>
C8
MEM_A_DQ<4>
C3
MEM_A_DQ<2>
C9
MEM_A_DQ<3>
E4
MEM_A_DQ<5>
E9
MEM_A_DQ<1>
D3
MEM_A_DQ<6>
E8
MEM_A_DQ<0>
C4
MEM_A_DQS_P<0>
D4
MEM_A_DQS_N<0>
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C2902
0.47UF
20%
4V
2
CERM-X5R-1
201
11 11 27 28 32 68
11 68
11
11 68
11 68
11 68
11 68
11 68
11 68
11 68
68
68
PP0V75_S3_MEM_VREFDQ_A
9
27 28 29
30 31 68
C2900
20%
0.47UF
CERM-X5R-1
201
4V
MEM_A_ODT<0>
11 27
68 32 28
R2900
C
68 32 28 27
68 32 28 27
26 27 30 29 28
240
1 2
1%
MF
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11
11
11 68 32 28 27
11 68 32 28 27
11 68 32 28 27
11 27 68 32 28
11 68 32 28 27
11 68 32 28 27
11 27 28 32 68
11 68 32 28 27
MEM_RESET_L
1/20W
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
B
1
C2901
0.47UF
2
CERM-X5R-1
MEM_A_ZQ0
201
1
20%
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
E2
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J9
VREFCA
A3
A10D8G9G3K2
U2900
DDR3-1333
VDD
VSS
A2
B2
J2L2N2F3A9D9F9
27 28 29 30 31 68
PP0V75_S3_MEM_VREFDQ_A
9
27 28 29 30 31 68
C2910
0.47UF
CERM-X5R-1
11
27
28
32 68
26 27 28
29 30
240
R2910
1 2
MF
1%
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
68
11 27 28 32
11 27 28 32 68
11
27 28 32 68
32
11 27 28 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 28 32 68
11 27 68 32 28
11 27
68 32 28
11 27
68 32 28
11 68 32 28 27
11 68 32 28 27
11 68 32 28 27
11 27 68 32 28
11 68 32 28 27
11 27 28 32 68
11 68 32 28 27
PP0V75_S3_MEM_VREFCA_A
1
1
C2911
20%
20%
0.47UF
2
2
CERM-X5R-1
201
201
4V
4V
201
MEM_A_ZQ1
G10
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
H3
F4
G4
H4
MEM_A_ODT<0>
MEM_RESET_L
1/20W
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A3
A10D8G9G3K2
DDR3-1333
VSS
=PP1V5_S3_MEM_A
7
27 28 32
K10M2M10
VDD
U2910
FBGA
L10
J10
OMIT_TABLE
B3D2B9
N10
B10C2E3
VDDQ
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DM/TDQS
NF/TDQS*
VSSQ
DQ0
DQ1
DQ2
DQ3
DQS
DQS*
NC
C10
E10
D10
PP0V75_S3_MEM_VREFCA_A
27 28 29 30 31 68
PP0V75_S3_MEM_VREFDQ_A
9
68 32 28
30 29 28
R2920
68 32 28 27
68 32 28 27
68 32 28 27
27 28 29 30 31 68
C2920
27
27
240
1 2
1%
MF
27 28 32 68
28 32 68 27 11
1
20%
0.47UF
2
CERM-X5R-1
201
4V
MEM_A_ODT<0>
11
MEM_RESET_L
26
201
1/20W
MEM_A_A<0>
MEM_A_A<1>
11 27 28 32 68
MEM_A_A<2>
11
MEM_A_A<3>
11 27 28 32 68
MEM_A_A<4>
11 27 28 32 68
MEM_A_A<5>
11 27 28 32 68
MEM_A_A<6>
11 27 28 32 68
MEM_A_A<7>
11 27 28 32 68
MEM_A_A<8>
11 27 28 32 68
MEM_A_A<9>
11 27 28 32 68
MEM_A_A<10>
11 27 28 32 68
MEM_A_A<11>
11 27 28 32 68
MEM_A_A<12>
11 27 28 32 68
MEM_A_A<13>
11 27 28 32 68
MEM_A_BA<0>
11
MEM_A_BA<1>
11
MEM_A_BA<2>
11
MEM_A_CLK_P<0>
11 68 32 28 27
MEM_A_CLK_N<0>
11 68 32 28 27
MEM_A_CKE<0>
11 68 32 28 27
MEM_A_CS_L<0>
MEM_A_RAS_L
11 68 32 28 27
MEM_A_CAS_L
11 27 28 32 68
MEM_A_WE_L
11 68 32 28 27
C2921
20%
0.47UF
CERM-X5R-1
MEM_A_ZQ2
1
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
E2
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J9
VREFCA
A3
A10D8G9G3K2
DDR3-1333
U2920
1
C2912
0.47UF
20% 0.47UF
4V
2
CERM-X5R-1
201
B4
MEM_A_DQ<8>
C8
MEM_A_DQ<14>
C3
MEM_A_DQ<15>
C9
MEM_A_DQ<12>
E4
MEM_A_DQ<10>
E9
MEM_A_DQ<13>
D3
MEM_A_DQ<11>
E8
MEM_A_DQ<9>
C4
MEM_A_DQS_P<1>
D4
MEM_A_DQS_N<1>
11 68 11 27 28 32 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
VSS
J2L2N2F3A9D9F9
A2
B2
VDD
FBGA
=PP1V5_S3_MEM_A
7
27 28 32
K10M2M10
L10
N10
J10
B10C2E3
VDDQ
DM/TDQS
NF/TDQS*
VSSQ
B3D2B9
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DQS
DQS*
NC
C10
E10
D10
B4
MEM_A_DQ<19>
C8
MEM_A_DQ<17>
C3
MEM_A_DQ<23>
C9
MEM_A_DQ<20>
E4
MEM_A_DQ<22>
E9
MEM_A_DQ<16>
D3
MEM_A_DQ<18>
E8
MEM_A_DQ<21>
C4
MEM_A_DQS_P<2>
D4
MEM_A_DQS_N<2>
B8
A8
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
N11
NC
1
C2922
0.47UF
20%
4V
2
CERM-X5R-1
201
11 68 11 27 28 32 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
68
30
R2930
68 32 27
68 32 28 27
68 32 28 27
68 32
PP0V75_S3_MEM_VREFCA_A
27 28 29 30 31 68
PP0V75_S3_MEM_VREFDQ_A
9
27 28 29 30 31 68
C2930
20%
0.47UF
CERM-X5R-1
MEM_A_ODT<0>
11
28 27
32
MEM_RESET_L
26
27
28 29
240
1 2
MF
1%
1/20W
MEM_A_A<0>
MEM_A_A<1>
11 27 28 32 68
MEM_A_A<2>
11 27 28 32 68
MEM_A_A<3>
11 27 28 32 68
MEM_A_A<4>
11 27 28 32 68
MEM_A_A<5>
11 27 28 32 68
MEM_A_A<6>
11 27 28 32 68
MEM_A_A<7>
11 27 28 32 68
MEM_A_A<8>
11 27 28 32 68
MEM_A_A<9>
11 27 28 32 68
MEM_A_A<10>
11 27 28 32 68
MEM_A_A<11>
11 27 28 32 68
MEM_A_A<12>
11 27 28 32 68
MEM_A_A<13>
11 27 28 32 68
MEM_A_A<14>MEM_A_A<14>
MEM_A_BA<0>
28
11
MEM_A_BA<1>
11
MEM_A_BA<2>
11
MEM_A_CLK_P<0>
11 27 68 32 28
MEM_A_CLK_N<0>
27 11 68 32 28
MEM_A_CKE<0>
27 11 28
MEM_A_CS_L<0>
11 27 28 68 32
MEM_A_RAS_L
11 27 28
32 68
MEM_A_CAS_L
27 28 32 68
11
MEM_A_WE_L
11 27 68 32 28
=PP1V5_S3_MEM_A
7
27 28 32
1
1
C2931
20%
0.47UF
2
2
CERM-X5R-1
201
201
4V
4V
G2
N3
H9
MEM_A_ZQ3
201
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
A3
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A10D8G9G3K2
VDD
U2930
DDR3-1333
FBGA
VSS
K10M2M10
L10
J10
N10
B10C2E3
VDDQ
OMIT_TABLEOMIT_TABLE
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DQS*
DM/TDQS
NF/TDQS*
NC
VSSQ
B3D2B9
C10
DQ0
DQ1
DQ2
DQ3
DQS
E10
D10
B4
MEM_A_DQ<28>
C8
MEM_A_DQ<26>
C3
MEM_A_DQ<27>
C9
MEM_A_DQ<30>
E4
MEM_A_DQ<25>
E9
MEM_A_DQ<24>
D3
MEM_A_DQ<29>
E8
MEM_A_DQ<31>
C4
MEM_A_DQS_P<3>
D4
MEM_A_DQS_N<3>
B8
A8
NCNC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NCNC
N11
NC
1
C2932
20%
4V
2
CERM-X5R-1
201
11 68 11 27 28 32 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
D
C
B
A14/A15 FOR 2G/4G MONO ONLY
CS1 IS FOR 2G DDP RANK CONTROL
A
SYNC_MASTER=K78_MLB
PAGE TITLE
DDR3 DRAM CHANNEL A (0-31)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 5 4 2 1
36
SYNC_DATE=12/07/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
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SHEET
27 OF 75
SIZE
A
D
Page 28
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345678
2 1
D
PP0V75_S3_MEM_VREFCA_A
27 28 29 30 31 68
PP0V75_S3_MEM_VREFDQ_A
9
27 28 29 30
31 68
C3000
20%
0.47UF
CERM-X5R-1
201
4V
32 28 27 11
240
1 2
1%
MF
27 28 32 68 11
27 28 32 68 11
27 28 32 68 11
28 32 68 27 11
27 28 32 68 11
27 28 32 68 11
MEM_A_ODT<0>
MEM_RESET_L
26 27 28 29
1/20W
MEM_A_A<0>
MEM_A_A<1>
11 27 28 32 68
MEM_A_A<2>
11 27 28 32 68
MEM_A_A<3>
11 27 28 32 68
MEM_A_A<4>
11 27 28 32 68
MEM_A_A<5>
11 27 28 32 68
MEM_A_A<6>
11 27 28 32 68
MEM_A_A<7>
11 27 28 32 68
MEM_A_A<8>
11 27 28 32 68
MEM_A_A<9>
11 27 28 32 68
MEM_A_A<10>
11 27 28 32 68
MEM_A_A<11>
11 27 28 32 68
MEM_A_A<12>
11 27 28 32 68
MEM_A_A<13>
11 27 28 32 68
MEM_A_A<14>
MEM_A_BA<0>
11 27 28 32 68
MEM_A_BA<1>
11 27 28 32 68
MEM_A_BA<2>
11 27 28 32 68
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CAS_L
11 27 28 32 68
MEM_A_WE_L
68
30
R3000
C
B
201
1
2
C3001
20%
0.47UF
CERM-X5R-1
MEM_A_ZQ8
1
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
E2
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J9
VREFCA
A3
A10D8G9G3K2
U3000
DDR3-1333
VDD
VSS
A2
B2
J2L2N2F3A9D9F9
28 32 27
K10M2M10
FBGA
J10
=PP1V5_S3_MEM_A
7
B10C2E3
VDDQ
OMIT_TABLE
DM/TDQS
NF/TDQS*
B3D2B9
L10
N10
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
VSSQ
DQ0
DQ1
DQ2
DQ3
DQS
DQS*
NC
C10
E10
D10
B4
MEM_A_DQ<39>
C8
MEM_A_DQ<33>
C3
MEM_A_DQ<34>
C9
MEM_A_DQ<35>
E4
MEM_A_DQ<36>
E9
MEM_A_DQ<37>
D3
MEM_A_DQ<38>
E8
MEM_A_DQ<32>
C4
MEM_A_DQS_P<4>
D4
MEM_A_DQS_N<4>
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C3002
0.47UF
20%
4V
2
CERM-X5R-1
201
68 31 30 29 28 27
68 31 30 29 28 27
68 32 27 28 11
30 29 27 28 26
R3010
11 68 11 27 28 32 68
68 32 28 27 11 68 11
11 68
68 32 28 27 11
11 68
68 32 28 27 11
11 68
68 32 28 27 11
11 68
68 32 28 27 11
11 68
68 32 28 27 11
11 68
68 32 28 27 11
11 68
68 32 28 27 11
68 32 28 27 11
11 68
68 32 28 27 11
11 68
68 32 28 27 11
68 32 28 27 11
68 32 28 27 11
68 32 28 27 11
68 32 28 27 11
9
C3010
0.47UF
CERM-X5R-1
240
1 2
1%
MF
28 32 68
27 11
28 32 68
27 11
28 32 68
11 27
27 28 32 68 11
27 28 32 68 11
27 28 32 68 11
27 28 32 68 11
27 28 32 68 11
27 28 32 68 11
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFDQ_A
1
C3011
20%
20%
0.47UF
2
CERM-X5R-1
201
4V
MEM_A_ODT<0>
MEM_RESET_L
MEM_A_ZQ9
201
1/20W
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
C3020
32 28 27 11
240
1 2
1%
MF
27 28 32 68
27 28 32 68
27 28 32 68
27 28 32 68 11
27 28 32 68 11
27 28 32 68 11
28 32 68 11 27
32 68 11 27 28
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFDQ_A
9
1
C3021
20%
0.47UF
0.47UF
2
CERM-X5R-1
CERM-X5R-1
201
4V
MEM_A_ODT<0>
MEM_RESET_L
MEM_A_ZQ10
201
1/20W
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_BA<0>
11
MEM_A_BA<1>
11
MEM_A_BA<2>
11
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
11 68 32 28 27
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
68 31 30 29 28 27
=PP1V5_S3_MEM_A
32 28 27
7
1
20%
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A3
A10D8G9G3K2
DDR3-1333
VSS
VDD
U3020
J10
K10M2M10
OMIT_TABLE
L10
N10
B10C2E3
VDDQ
DM/TDQS
NF/TDQS*
VSSQ
B3D2B9
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DQS
DQS*
NC
C10
E10
1
C3022
0.47UF
20%
4V
2
CERM-X5R-1
201
B4
MEM_A_DQ<50>
C8
MEM_A_DQ<51>
C3
MEM_A_DQ<55>
C9
MEM_A_DQ<48>
E4
MEM_A_DQ<52>
E9
MEM_A_DQ<53>
D3
MEM_A_DQ<54>
E8
MEM_A_DQ<49>
C4
MEM_A_DQS_P<6>
D4
MEM_A_DQS_N<6>
B8
A8
NC NC
A1
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
D10
68 31 30 29 28 27
68 11 27 28 32
30 28 29 27 26
R3030
68 32 28 27 11 68 11
68
68 11
68
11
68 32 28 27 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68
68 11
68 11
68 32 28 27
68 11
68 32 28 27 11
68 32 28 27 11
68 11
68 32 28 27 11
68 32 28 27 11
68 11
68 32 28 27 11
68 32 28 27 11
68 32 28 27 11
68
68
68
68 32 28 27 11
=PP1V5_S3_MEM_A
32 28 27
7
D10
B4
MEM_A_DQ<46>
C8
MEM_A_DQ<41>
C3
MEM_A_DQ<43>
C9
MEM_A_DQ<44>
E4
MEM_A_DQ<45>
E9
MEM_A_DQ<40>
D3
MEM_A_DQ<47>
E8
MEM_A_DQ<42>
C4
MEM_A_DQS_P<5>
D4
MEM_A_DQS_N<5>
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C3012
0.47UF
20%
4V
2
CERM-X5R-1
201
1
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A3
A10D8G9G3K2
DDR3-1333
VSS
VDD
U3010
FBGA
J10
K10M2M10
OMIT_TABLE
L10
N10
B10C2E3
VDDQ
DM/TDQS
NF/TDQS*
VSSQ
B3D2B9
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DQS*
NC
C10
DQ0
DQ1
DQ2
DQ3
DQS
E10
68 31 30 29 28 27
68 31 30 29 28 27
68
30 29 28 27 26
R3020
68 32 28 27 11 68 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68 32 28 27 11
68 11
68 32 28 27 11
68 11
68 32 28 27 11
68 32 28 27 11
68 32 28 27 11
68 32 28 27 11
68 32 28 27 11
C3030
240
1 2
1%
MF
32 28 27 11
32 28 27 11
32 28
27
32 28
27
32 28 27 11
27 28 32 68 11
27 28 32 68 11
28 32 68 27 11
28 32 68 11 27
28 32 68 11 27
28 32 68 11 27
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFDQ_A
9
1
C3031
20%
0.47UF
0.47UF
2
CERM-X5R-1
201
4V
MEM_A_ODT<0>
MEM_RESET_L
MEM_A_ZQ11
201
1/20W
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
11
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_BA<0>
11
MEM_A_BA<1>
11
MEM_A_BA<2>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
20%
CERM-X5R-1
=PP1V5_S3_MEM_A
32 28 27
7
D10
B4
MEM_A_DQ<59>
C8
MEM_A_DQ<57>
C3
MEM_A_DQ<63>
C9
MEM_A_DQ<56>
E4
MEM_A_DQ<58>
E9
MEM_A_DQ<61>
D3
MEM_A_DQ<62>
E8
MEM_A_DQ<60>
C4
MEM_A_DQS_P<7>
D4
MEM_A_DQS_N<7>
B8
A8
A1
NCNC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C3032
0.47UF
20%
4V
2
CERM-X5R-1
201
1
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
A3
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A10D8G9G3K2
VDD
U3030
DDR3-1333
FBGAFBGA
VSS
K10M2M10
L10
J10
OMIT_TABLE
B3D2B9
N10
B10C2E3
VDDQ
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DM/TDQS
NF/TDQS*
VSSQ
DQ0
DQ1
DQ2
DQ3
DQS
DQS*
NC
C10
E10
D
C
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
B
A14/A15 FOR 2G/4G MONO ONLY
CS1 IS FOR 2G DDP RANK CONTROL
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
DDR3 DRAM CHANNEL A (32-63)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/07/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
30 OF 109
SHEET
28 OF 75
SIZE
A
D
Page 29
www.laptopblue.vn
345678
2 1
D
C
B
27 28 29 30
68 32 30 29
R3100
1 2
MF
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29 11
PP0V75_S3_MEM_VREFCA_A
27 28 29 30 31 68
PP0V75_S3_MEM_VREFDQ_A
9
31 68
1
C3100
20%
0.47UF
2
CERM-X5R-1
201
4V
MEM_B_ODT<0>
11
MEM_RESET_L
26 30 29 28 27
240
MEM_B_ZQ0
1%
1/20W
201
MEM_B_A<0>
MEM_B_A<1>
11 29 30 32 68
MEM_B_A<2>
11 29 30 32 68
MEM_B_A<3>
11 29 30 32 68
MEM_B_A<4>
11 29 30 32 68
MEM_B_A<5>
11 29 30 32 68
MEM_B_A<6>
11 29 30 32 68
MEM_B_A<7>
11 29 30 32 68
MEM_B_A<8>
11 29 30 32 68
MEM_B_A<9>
11 29 30 32 68
MEM_B_A<10>
11 29 30 32 68
MEM_B_A<11>
11 29 30 32 68
MEM_B_A<12>
11 29 30 32 68
MEM_B_A<13>
11 29 30 32 68
MEM_B_A<14>
MEM_B_BA<0>
11 68 32 30 29
MEM_B_BA<1>
11
MEM_B_BA<2>
11
MEM_B_CLK_P<0>
11 68 32 30 29
MEM_B_CLK_N<0>
11
MEM_B_CKE<0>
11 68 32 30 29
MEM_B_CS_L<0>
11 68 32 30 29
MEM_B_RAS_L
MEM_B_CAS_L
11 29 30 32 68
MEM_B_WE_L
11 68 32 30 29
C3101
20%
0.47UF
CERM-X5R-1
D
PP0V75_S3_MEM_VREFCA_A
R3110
32 30
68
30 29 28
1 2
MF
68 32 30 29
68 32 30 29
68 32 30
27 28 29 30 31 68
PP0V75_S3_MEM_VREFDQ_A
9
27 28 29 30 31 68
C3110
20%
0.47UF
CERM-X5R-1
201
4V
MEM_B_ODT<0>
29 11
MEM_RESET_L
27 26
240
1%
201
1/20W
MEM_B_A<0>
MEM_B_A<1>
11 29 30 32 68
MEM_B_A<2>
11 29 30 32 68
MEM_B_A<3>
11 29 30 32 68
MEM_B_A<4>
11 29 30 32 68
MEM_B_A<5>
11 29 30 32 68
MEM_B_A<6>
11 29 30 32 68
MEM_B_A<7>
11 29 30 32 68
MEM_B_A<8>
11 29 30 32 68
MEM_B_A<9>
11 29 30 32 68
MEM_B_A<10>
11 29 30 32 68
MEM_B_A<11>
11 29 30 32 68
MEM_B_A<12>
11 29 30 32 68
MEM_B_A<13>
11 29 30 32 68
MEM_B_A<14>
MEM_B_BA<0>
11 68 32 30 29
MEM_B_BA<1>
11
MEM_B_BA<2>
11
MEM_B_CLK_P<0>
11 29 68 32 30
MEM_B_CLK_N<0>
11 29
MEM_B_CKE<0>
29 11 30 32 68
MEM_B_CS_L<0>
11 68 32 30 29
MEM_B_RAS_L
11 29 68 32 30
MEM_B_CAS_L
11 29 30 32 68
MEM_B_WE_L
29 11 68 32 30
1
2
C3111
20%
0.47UF
CERM-X5R-1
MEM_B_ZQ1
=PP1V5_S3_MEM_B
7
29 30 32
D10
B4
MEM_B_DQ<10>
C8
MEM_B_DQ<9>
C3
MEM_B_DQ<15>
C9
MEM_B_DQ<13>
E4
MEM_B_DQ<14>
E9
MEM_B_DQ<12>
D3
MEM_B_DQ<11>
E8
MEM_B_DQ<8>
C4
MEM_B_DQS_P<1>
D4
MEM_B_DQS_N<1>
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C3112
0.47UF
20%
4V
2
CERM-X5R-1
201
1
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A3
A10D8G9G3K2
DDR3-1333
VSS
VDD
U3110
FBGA
J10
K10M2M10
OMIT_TABLE
L10
N10
B10C2E3
VDDQ
DM/TDQS
NF/TDQS*
VSSQ
B3D2B9
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DQS*
NC
C10
DQ0
DQ1
DQ2
DQ3
DQS
E10
=PP1V5_S3_MEM_B
7
29 30 32
D10
B4
MEM_B_DQ<2>
C8
MEM_B_DQ<5>
C3
MEM_B_DQ<3>
C9
MEM_B_DQ<4>
E4
MEM_B_DQ<6>
E9
MEM_B_DQ<0>
D3
MEM_B_DQ<7>
E8
MEM_B_DQ<1>
C4
MEM_B_DQS_P<0>
D4
MEM_B_DQS_N<0>
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C3102
0.47UF
20%
4V
2
CERM-X5R-1
201
11 68 11 29 30 32 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
1
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
A3
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
A2
B2
J2L2N2F3A9D9F9
A10D8G9G3K2
VDD
U3100
DDR3-1333
FBGA
VSS
K10M2M10
L10
J10
OMIT_TABLE
B3D2B9
N10
B10C2E3
VDDQ
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DM/TDQS
NF/TDQS*
VSSQ
DQ0
DQ1
DQ2
DQ3
DQS
DQS*
NC
C10
E10
11 68 11 29 30 32 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
11 68
68 31 30 29 28 27
68 31 30 29 28 27
68 32 30 29
30 29 28 27
R3120
68 32 30 29 11 68 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32
68 32
68 32
68 32 30 29
68 32 30 29
68 32 30 29 11
9
C3120
0.47UF
CERM-X5R-1
11
26
240
1 2
MF
1%
30 11 29
30 29 11
30 29 11
11
11
29 11 30 32 68
11 68 32 30 29
30 32 68 29 11
30 29 11 68 32
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFDQ_A
1
C3121
20%
20%
0.47UF
2
CERM-X5R-1
201
201
4V
4V
MEM_B_ODT<0>
MEM_RESET_L
MEM_B_ZQ2
1/20W
201
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
G10
1
2
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
H3
F4
G4
H4
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A3
A10D8G9G3K2
DDR3-1333
VSS
VDD
U3120
J10
7
29 30 32
K10M2M10
OMIT_TABLE
L10
N10
B10C2E3
VDDQ
DM/TDQS
NF/TDQS*
VSSQ
B3D2B9
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DQS
DQS*
NC
C10
E10
D10
B4
MEM_B_DQ<19>
C8
MEM_B_DQ<17>
C3
MEM_B_DQ<23>
C9
MEM_B_DQ<21>
E4
MEM_B_DQ<22>
E9
MEM_B_DQ<16>
D3
MEM_B_DQ<18>
E8
MEM_B_DQ<20>
C4
MEM_B_DQS_P<2>
D4
MEM_B_DQS_N<2>
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C3122
0.47UF
20%
4V
2
CERM-X5R-1
201
68 31 30 29 28 27
68 31 30 29 28 27
68 32 30
30 29 28
R3130
68 32 30 29 11 68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 32 30 29 11
68 11
68 32 30 29 11
68 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29 11
68 32 30 29
68 32 30 29
68 32 30 29
68 32 30 29 11
C3130
240
1 2
1%
MF
29 30 32 68 11
29 30 32 68 11
29 30 32 68 11
29 30 32 68 11
32 68 30 29 11
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFDQ_A
9
1
C3131
20%
0.47UF
0.47UF
2
CERM-X5R-1
201
4V
MEM_B_ODT<0>
11 29
MEM_RESET_L
26 27
MEM_B_ZQ3
201
1/20W
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_BA<0>
11
MEM_B_BA<1>
11
MEM_B_BA<2>
11
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<0>
11 30 32 68 29
MEM_B_CS_L<0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
20%
CERM-X5R-1
=PP1V5_S3_MEM_B=PP1V5_S3_MEM_B
7
29 30 32
D10
B4
MEM_B_DQ<30>
C8
MEM_B_DQ<29>
C3
MEM_B_DQ<26>
C9
MEM_B_DQ<28>
E4
MEM_B_DQ<27>
E9
MEM_B_DQ<25>
D3
MEM_B_DQ<31>
E8
MEM_B_DQ<24>
C4
MEM_B_DQS_P<3>
D4
MEM_B_DQS_N<3>
B8
A8
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
H2
NC
H10
NC
J8
NC
N1
NC
N11
NC
1
C3132
0.47UF
20%
4V
2
CERM-X5R-1
201
C
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
68 11
B
1
2
201
4V
G2
N3
H9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J3
K9
J4
F8
G8
G10
H3
F4
G4
H4
A3
J9
E2
VREFCA
VREFDQ
ODT
RESET*
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
BA0
BA1
BA2
CK
CK*
CKE
CS*
RAS*
CAS*
WE*
J2L2N2F3A9D9F9
A2
B2
A10D8G9G3K2
VDD
U3130
DDR3-1333
FBGAFBGA
VSS
K10M2M10
L10
J10
OMIT_TABLE
B3D2B9
N10
B10C2E3
VDDQ
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
DM/TDQS
NF/TDQS*
VSSQ
DQ0
DQ1
DQ2
DQ3
DQS
DQS*
NC
C10
E10
A14/A15 FOR 2G/4G MONO ONLY
CS1 IS FOR 2G DDP RANK CONTROL
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
DDR3 DRAM CHANNEL B (0-31)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/07/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
31 OF 109
SHEET
29 OF 75
SIZE
A
D
Page 30
www.laptopblue.vn
Page 31
www.laptopblue.vn
345678
2 1
NOTE: Must not enable more than two SO-DIMM margining
=PP3V3_S3_VREFMRGN
7
OMIT
R3318
SHORT
1 2
D
1 2
C
NONE
NONE
NONE
402
OMIT
R3319
SHORT
NONE
NONE
NONE
402
PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
44
44
BI
Addr=0x98(WR)/0x99(RD)
PP3V3_S3_VREFMRGN_CTRL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
Addr=0x30(WR)/0x31(RD)
44
44
BI
IN
IN
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
VREFMRGN
C3300
2.2UF
402-LF
20%
6.3V
CERM
VREFMRGN
1
2
C3302
0.1UF
VREFMRGN
1
C3301
0.1UF
10%
16V
2
X5R-CERM
0201
6
SCL
7
SDA
9
A0
10
A1
1
10%
6.3V
2
X5R
201
3
A0
4
A1
5
A2
1
SCL
2
SDA
THRM
PAD
CRITICAL
VREFMRGN
U3300
8
VDD
MSOP
GND
VCC
U3301
PCA9557
QFN
GND
17
DAC5574
3
16
8
VOUTA
VOUTB
VOUTC
VOUTD
CRITICAL
VREFMRGN
(OD)
RESET*
1
VREFMRGN_SODIMMA_DQ
2
NC
4
VREFMRGN_SODIMMS_CA
5
VREFMRGN_MEMVREG_FBVREF
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!
6
P0
NC
7
VREFMRGN_DQ_SODIMMA_EN
P1
9
P2
NC
10
VREFMRGN_CA_SODIMMA_EN
P3
11
P4
NC
12
VREFMRGN_MEMVREG_EN
P5
13
VREFMRGN_FRAMEBUF_EN
P6
14
P7
NC
15
12
1
2
VREFMRGN
R3301
100K
5%
1/20W
MF
201
VREFMRGN
R3307
100K
5%
1/20W
MF
201
VREFMRGN
C3303
0.1UF
X5R-CERM
1
10%
16V
2
0201
C2
C3
VREFMRGN
B1
A2
A3
U3302
MAX4253
V+
UCSP
A1
A4
V-
B4
VREFMRGN
B1
U3302
MAX4253
V+
UCSP
C1
C4
V-
B4
buffers at once or VRef source may be overloaded.
VREFMRGN
=PPVTT_S3_DDR_BUF
56
7
10mA max load
VREFMRGN_DQ_SODIMMA_BUF
VREFMRGN_CA_SODIMMA_BUF
R3303
200
1 2
1%
1/20W
MF
201
VREFMRGN
R3304
133
1 2
1%
1/20W
MF
201
VREFMRGN
R3309
200
1 2
1%
1/20W
MF
201
VREFMRGN
R3310
133
1 2
1%
1/20W
MF
201
PLACE_NEAR=U2900.E1:2.54mm
PP0V75_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
PLACE_NEAR=U2900.J8:1mm
PLACE_NEAR=J2900.126:2.54mm
PP0V75_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
PLACE_NEAR=R3309.2:1mm
68 30 29 28 27
9
D
68 30 29 28 27
C
B
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM options provided by this page:
VREFMRGN - Stuffs VREF Margining
Circuitry.
VREFMRGN_NOT - Bypasses VREF Margining
Circuitry.
A
DAC Channel:
PCA9557D Pin:
Nominal value
Margined target:
DAC range:
VRef current:
DAC step size:
PCA9557D_RESET_L
25
IN
RST* on ’platform reset’ so that system
watchdog will disable margining.
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
Required zero ohm resistors when no VREF margining circuit stuffed
Page Notes
MEM A VREF DQ
PART NUMBER
116S0004
116S0004
QTY
2
2
MEM B VREF DQ
A
1 2
0.75V (DAC: 0x3A)
0.300V - 1.200V (+/- 450mV)
0.000V - 1.501V (0x00 - 0x74)
+3.4mA - -3.4mA (- = sourced)
7.69mV / step @ output
DESCRIPTION
RES,MTL FILM,0,5%,0402,SM,LF
RES,MTL FILM,0,5%,0402,SM,LF
MEM A VREF CA
B
REFERENCE DES
C
3
R3303
R3309
MEM B VREF CA
CRITICAL
C
4
BOM OPTION
VREFMRGN_NOT
VREFMRGN_NOT
MEM VREG
1.5V (DAC: 0x3A)
1.998V - 1.002V (+/- 498mV)
0.000V - 1.501V (0x00 - 0x74)
+33uA - -33uA (- = sourced)
8.59mV / step @ output
VREFMRGN
1
R3313
100K
5%
1/20W
MF
201
2
VREFMRGN
1
R3315
100K
5%
1/20W
MF
201
2
D
5
8 7 5 4 2 1
VREFMRGN
1
C3305
0.1UF
X5R-CERM
10%
16V
2
0201
B1
C2
V+
C3
V-
B4
VREFMRGN_FRAMEBUF_BUF
B1
A2
V+
A3
V-
B4
GPU Frame Buffer (1.8V, 70% VRef)
1.267V (DAC: 0x8B)
1.056V - 1.442V (+/- 180mV)
0.000V - 3.300V (0x00 - 0xFF)
+6.0mA - -5.0mA (- = sourced)
1.51mV / step @ output
VREFMRGN
U3304
MAX4253
UCSP
C4
VREFMRGN
U3304
MAX4253
UCSP
A4
D
6
VREFMRGN
R3314
C1
A1
VREFMRGN_MEMVREG_BUF
unused buffer
33.2K
1 2
1%
1/20W
MF
201
DDRREG_FB
PLACE_NEAR=R7315.2:1mm
SYNC_MASTER=K78_MLB
PAGE TITLE
FSB/DDR3/FRAMEBUF Vref Margining
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
36
OUT
56
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
33 OF 109
SHEET
31 OF 75
SYNC_DATE=01/10/2011
3.13.0
SIZE
B
A
D
Page 32
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345678
2 1
=PP1V5_S3_MEM_A
32 28 27
7
1
C3408
2.2UF
20%
6.3V
2
CERM
402-LF
D
1
C3409
2.2UF
20%
6.3V
2
CERM
402-LF
2 CAPS ALONG PACKAGE EDGE
1
C3400
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3401
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3404
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3405
2.2UF
20%
6.3V
2
CERM
402-LF
C
COLUMN OF THREE CAPS BETWEEN PACKAGES
1
C3410
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3411
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3412
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3414
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3415
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3416
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3420
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3421
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3424
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3425
2.2UF
20%
6.3V
2
CERM
402-LF
=PP1V5_S3_MEM_A
32 28 27
7
1
C3418
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3419
2.2UF
20%
6.3V
2
CERM
402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES
1
C3430
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3431
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3434
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3435
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3440
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3441
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3442
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3444
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3445
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3446
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3450
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3451
2.2UF
20%
6.3V
2
CERM
402-LF
2 CAPS ALONG PACKAGE EDGE
1
C3454
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3455
2.2UF
20%
6.3V
2
CERM
402-LF
JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
=PP0V75_S0_MEM_VTT_A
7
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
68 28 27 11
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
MEM_A_CKE<0>
MEM_A_A<10>
MEM_A_A<7>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_A<3>
MEM_A_A<6>
MEM_A_A<1>
MEM_A_A<11>
MEM_A_CS_L<0>
MEM_A_A<4>
MEM_A_BA<1>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_BA<2>
MEM_A_A<0>
MEM_A_A<14>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<2>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_A<9>
RP3401
RP3402
RP3406
RP3403
RP3402
RP3401
RP3403
RP3407
RP3406
RP3406
RP3402
RP3404
RP3403
RP3404
RP3407
RP3402
RP3403
RP3407
RP3407
RP3404
RP3404
RP3401
RP3401
RP3406
4 5
36
2 7
36
2 7
36
1 8
36
1 8
36
2 7
36
2 7
36
3 6
36
1 8
36
4 5
36
3 6
36
3 6
36
4 5
36
1 8
36
2 7
36
4 5
36
3 6
36
1 8
36
4 5
36
2 7
36
4 5
36
3 6
36
1 8
36
3 6
36
=PP0V75_S0_MEM_VTT_B
7
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
1
C3480
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3482
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3484
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3486
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3488
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3489
0.47UF
20%
4V
2
CERM-X5R-1
201
1
2
1
2
1
2
C3483
0.47UF
20%
4V
CERM-X5R-1
201
C3485
0.47UF
20%
4V
CERM-X5R-1
201
C3487
0.47UF
20%
4V
CERM-X5R-1
201
D
C
68 30 29 11
68 30 29 11
68 30 29 11
MEM_A_CLK_TERM_R
VOLTAGE=0V
MEM_B_CLK_TERM_R
VOLTAGE=0V
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
68 30 29 11
C3469
1
0.1UF
10%
X5R
201
6.3V
C3479
1
0.1UF
10%
X5R
201
6.3V
=PP1V5_S3_MEM_B
30 29
7
32
1
C3428
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3429
2.2UF
20%
6.3V
2
CERM
402-LF
B
2 CAPS ALONG PACKAGE EDGE
COLUMN OF THREE CAPS BETWEEN PACKAGES
C3402
2.2UF
20%
6.3V
CERM
402-LF
1
C3403
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3406
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3407
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3470
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3471
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3472
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3474
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3475
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3476
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3422
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3423
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3426
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3427
2.2UF
20%
6.3V
2
CERM
402-LF
32 30 29
7
A
=PP1V5_S3_MEM_B
1
C3438
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3439
2.2UF
20%
6.3V
2
CERM
402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES
1
C3432
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3433
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3436
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3437
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3490
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3491
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3492
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3494
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3495
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3496
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3452
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3453
2.2UF
20%
6.3V
2
CERM
402-LF
2 CAPS ALONG PACKAGE EDGE
1
C3456
2.2UF
20%
6.3V
2
CERM
402-LF
1
C3457
2.2UF
20%
6.3V
2
CERM
402-LF
MEM CLOCK TERMINATION
Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM
R3468
30
5%
25V
CERM
201
5%
25V
CERM
201
1
2
1
2
1 2
5%
1/20W
MF
201
R3469
30
1 2
5%
1/20W
MF
201
R3478
30
1 2
5%
1/20W
MF
201
R3479
30
1 2
5%
1/20W
MF
201
68 28 27 11
68 28 27 11
68 30 29 11
68 30 29 11
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
C3468
3.3PF
C3478
3.3PF
8 7 5 4 2 1
2
2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
36
MEM_B_CKE<0>
MEM_B_A<8>
MEM_B_BA<2>
MEM_B_A<1>
MEM_B_A<10>
MEM_B_A<13>
MEM_B_BA<0>
MEM_B_CAS_L
MEM_B_A<7>
MEM_B_RAS_L
MEM_B_A<9>
MEM_B_WE_L
MEM_B_A<0>
MEM_B_A<3>
MEM_B_CS_L<0>
MEM_B_A<6>
MEM_B_A<12>
MEM_B_BA<1>
MEM_B_A<14>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_ODT<0>
MEM_B_A<5>
MEM_B_A<11>
RP3413
RP3410
RP3409
RP3411
RP3409
RP3410
RP3408
RP3413
RP3411
RP3413
RP3411
RP3409
RP3408
RP3408
RP3409
RP3410
RP3414
RP3408
RP3410
RP3414
RP3414
RP3413
RP3414
RP3411
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
1 8
1 8
1 8
4 5
3 6
3 6
4 5
3 6
2 7
4 5
3 6
4 5
2 7
3 6
2 7
4 5
4 5
1 8
2 7
2 7
1 8
2 7
3 6
1 8
1/32W365%
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
1/32W365%
4X0201
5%361/32W
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
1/32W
5%
4X0201
5%
1/32W
4X0201
5%
1/32W
4X0201
SYNC_MASTER=K78_MLB
PAGE TITLE
DDR3 DRAM Channel B (32-63)
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
1
C3481
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3460
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3461
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3463
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3465
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3466
0.47UF
20%
4V
2
CERM-X5R-1
201
Apple Inc.
1
C3462
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3464
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C3467
0.47UF
20%
4V
2
CERM-X5R-1
201
SYNC_DATE=12/16/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
34 OF 109
SHEET
32 OF 75
SIZE
B
A
D
Page 33
www.laptopblue.vn
345678
2 1
D
=PP3V3_S3_CARDREADER
7
2
CRITICAL
L3500
0.22UH
0805-1
1
PP3V3_S3_CARDREADER_AVDD
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
C3514
4.7UF
X5R-CERM1
1
20%
6.3V
2
402
C
USB_SDCARD_P
69
24
BI
USB_SDCARD_N
24 69
1
R3510
2
Q3500
SOT563
BI
GL137_RREF
1
10K
5%
1/20W
MF
201
2
5
GL137_GPIO0
GL137_GPIO1
GL137_RESET_L
NO STUFF
C3513
3
D
SG
4
SDCARD_PLT_RST
0.1UF
10%
6.3V
X5R
201
Q3500
SSM6N37FEAPE
NO STUFF
1
R3507
10K
5%
1/20W
MF
201
2
R3506
1
R3509
10K
1/20W
201
PDMOD: POWER DOWN MODES
NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE
715
5%
MF
1%
1/20W
MF
201
2
SSM6N37FEAPE
B
R3590
0
12
18 23
IN
1/20W
201
SDCONN_STATE_RST_RSDCONN_STATE_RST_L
5%
MF
25
R3500
10K
5%
1/20W
MF
201
SDCARD_PLT_RST_L
IN
1
2
BYPASS=U3500.3:5:5 mm
1
C3504
2
1
2
SOT563
2
BYPASS=U3500.1:16:5 mm
1
C3503
0.1UF
10%
6.3V
2
X5R
201
0.1UF
10%
6.3V
X5R
201
5
AVDD
3
DP
2
DM
4
RREF
22
GPIO0
(IPU)
6
GPIO1
17
GPIO2
NC
26 23
RSTZ*
27
TEST
1716
DVDD
U3500
GL822
CRITICAL
THRM_PAD
SDCARD_IOVDD
82528
QFN
29
6
D
SG
1
BYPASS=U3500.8:5 mm
SDCARD_PLLVDD
1
2
15
IOVDD
PLLVDD
SD_CLK
(IPD)
SD_WP
(IPD)
SD_CMD
(IPU)
SD_CDZ
(IPU)
MS_INS
C3502
0.1UF
10%
6.3V
X5R
201
PMOS
D0
D1
D2
D3
D4
D5
D6
D7
13
SD_D_R<0>
14
SD_D_R<1>
9
SD_D_R<2>
10
SD_D_R<3>
18
SD_D_R<4>
19
SD_D_R<5>
20
SD_D_R<6>
21
SD_D_R<7>
12
24
11
SD_CLK_R
SD_CMD_R
NC
BYPASS=U3500.8:5 mm
1
C3501
0.1UF
10%
6.3V
2
X5R
201
R3527
R3525
R3523
R3521
R3520
1/20W
5%
R3519
5%
1 2
5%
1/16W
1 2
5%
1/16W
1 2
5%
1/16W
1 2
5%
1/16W0402
1 2
1 2
1/16W
C3507
X5R-CERM1
402
402
402
33
MF
0
402
R3505 is for rail discharge. GL822 may cycle PMOS to
recover from card error. Off duration is 100ms and card
voltage must be less than 0.5V for at least 1ms per spec.
Keep this net short!
1
4.7UF
20%
6.3V
2
402
R3528
5%
1/16W
0
MF-LF
R3526
0
MF-LF
R3524
0
MF-LF
R3522
MF-LF
L3504
1 2
SD_CLK_L
201
MF-LF
1
2
1
1
1/16W5%402
1 2
5%
1/16W
1
5%
1/16W
33NH
NO STUFF
1
C3519
10PF
5%
50V
2
CERM
402
C3505
0.1UF
10%
6.3V
X5R
201
2
0
402
MF-LF
2
0
402
2
402
0402
NO STUFF
C3515
10PF
1
R3505
47K
5%
1/20W
MF
201
2
MF-LF
0
MF-LF
0
MF-LF
1
5%
NO STUFF
25V
1
2
C3520
NPO
201
10PF
5%
50V
2
CERM
402
PP3V3_SW_SD_PWR
6
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
R3529
1 2
5%
1/16W
NO STUFF
1
C3521
10PF
5%
50V
2
CERM
402
NO STUFF
1
C3522
5%
50V
2
CERM
402
Max Current = 800 mA
SD_CLK_R2SD_CLK_R1
0
MF-LF
402
10PF
5%
CERM
402
CERM
NO STUFF
1
C3525
10PF
5%
50V50V
2
CERM
402
1
5%
50V
2
402
NO STUFF
1
C3523
2
NO STUFF
C3524
10PF10PF
R3531
1
2
1 2
1/16W
5%
NO STUFF
R3530
0
5%
1/16W
MF-LF
402
NO STUFF
C3526
10PF
5%
50V
CERM
402
402
0
MF-LF
6
1
2
6
6
6
6
6
6
6
6
6
6
SD_WP
6
SD_CD_L
1
2
SD_CLK
SD_CMD
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
NO STUFF
C3527
10PF
5%
50V
CERM
402
CRITICAL
J3500
SD-CARD-K16
F-RT-TH
3
6
5
2
7
8
9
1
10
11
12
13
14
15
16
4
17
18
19
20
516-0237
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
D
C
B
A
SYNC_MASTER=(MASTER)
PAGE TITLE
SecureDigital Card Reader
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 5 4 2 1
36
SYNC_DATE=(MASTER)
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
35 OF 109
SHEET
33 OF 75
SIZE
A
D
Page 34
www.laptopblue.vn
CRITICAL
PCIE_T29_R2D_C_P<0>
70
8
IN
PCIE_T29_R2D_C_N<0>
70
8
IN
PCIE_T29_R2D_C_P<1>
70
8
IN
PCIE_T29_R2D_C_N<1>
70
8
IN
PCIE_T29_R2D_C_P<2>
70
8
IN
D
1
1
3.3K
1/20W
1
R3691
3.3K
5%
5%
1/20W
MF
MF
201
201
2
2
R3690
(T29_SPI_MOSI)
C
(T29_SPI_CLK)
(T29_SPI_CS_L)
T29ROM_WP_L
T29ROM_HOLD_L
C3690
1.0UF
20%
6.3V
2
X5R
0201-MUR
5
6
1
3
7
D
C
S_L
W_L
HOLD_L
VSS
4
8
VCC
U3690
M95160
2KX8-1.8V
MLP
70
8
IN
70
8
IN
70
8
IN
CRITICAL
OMIT_TABLE
Q
THM
PAD
9
PCIE_T29_R2D_C_N<2>
PCIE_T29_R2D_C_P<3>
PCIE_T29_R2D_C_N<3>
DEBUG: For monitoring current/voltage
DEBUG: For monitoring clock
36 35 34
R3692
2
(T29_SPI_MISO)
3.3K
1/20W
7
5%
MF
201
C3600
C3601
C3602
C3603
C3604
C3605
C3606
C3607
TP_T29_MONDC0
TP_T29_MONDC1
TP_T29_MONOBSP
TP_T29_MONOBSN
=PP3V3_T29_RTR
1
2
1
R3693
3.3K
5%
1/20W
MF
201
2
SNK0 AC Coupling
DP_T29SNK0_ML_C_P<0>
72
8
IN
DP_T29SNK0_ML_C_N<0>
72
8
IN
DP_T29SNK0_ML_C_P<1>
72
8
IN
DP_T29SNK0_ML_C_N<1>
72
8
IN
B
72
8
IN
72
8
IN
72
8
IN
72
8
IN
72
8
BI
72
8
BI
DP_T29SNK0_ML_C_P<2>
DP_T29SNK0_ML_C_N<2>
DP_T29SNK0_ML_C_P<3>
DP_T29SNK0_ML_C_N<3>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
36 35 34
A
C3620
C3621
C3622
C3623
C3624
C3625
C3626
C3627
C3628
C3629
=PP3V3_T29_RTR
7
T29_HDMI_SCL_IN
34
T29_HDMI_SDA_IN
34
T29_CIO_PLUG_EVENT
34
T29_HDMI_OUT_HPD
34
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
10% 16V
X5R-CERM
1
R3670
10K
5%
1/20W
MF
201
2
0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
DP_T29SNK0_ML_P<0>
DP_T29SNK0_ML_N<0>
DP_T29SNK0_ML_P<1>
DP_T29SNK0_ML_N<1>
DP_T29SNK0_ML_P<2>
DP_T29SNK0_ML_N<2>
DP_T29SNK0_ML_P<3>
DP_T29SNK0_ML_N<3>
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N
1
R3671
10K
5%
1/20W
MF
201
2
1
R3673
10K
5%
1/20W
MF
201
2
1
R3674
10K
5%
1/20W
MF
201
2
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1 2
1 2
1 2
10% X5R
1 2
1 2
10% 201
1 2
10%
1 2
10%
1 2
10% X5R 201
R3610
R3611
C3615
C3616
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
0
0
0.1UF
0.1UF
X5R10%
201
PCIE_T29_R2D_P<0>
70
PCIE_T29_R2D_N<0>
70 70
20110%
X5R
201
PCIE_T29_R2D_P<1>
70
PCIE_T29_R2D_N<1>
70
20110%
X5R
X5R
X5R 201
X5R
NO STUFF
1 2
1 2
NO STUFF
70
70
201
70
70
1 2
1 2
10% 201
36
OUT
PCIE_T29_R2D_P<2>
PCIE_T29_R2D_N<2>
PCIE_T29_R2D_P<3>
PCIE_T29_R2D_N<3>
T29_MONDC0
1/20W
5% MF
T29_MONDC1
1/20W
5% MF
T29_MONOBSP
20110%
6.3V
X5R
T29_MONOBSN
X5R
6.3V
=T29_CLKREQ_L
201
201
P14
PERP_0
P15
PERN_0
K14
PERP_1
K15
PERN_1
F14
PERP_2
F15
PERN_2
B15
PERP_3
B14
PERN_3
A14
MONDC0
A15
MONDC1
A13
MONOBSP
B13
MONOBSN
P1
PCIE_CLKREQ_0*
RECEIVE
CLK REQUEST
T29_SPI_MOSI
72
T29_SPI_MISO
72
T29_SPI_CS_L
72
T29_SPI_CLK
72
TP_T29_THERM_DP
47
1
R3625
0
5%
1/20W
MF
201
2
1
R3629
0
5%
1/20W
MF
8
OUT
R3630
100K
1/20W
201
2
1
5%
MF
201
2
72 34
72 34
72 34
72 34
72 34
72 34
72 34
72 34
72 34
72 34
Use B1 GND ball for THERM_DN
T29_TEST_EN
T29_TEST_POINT_3
DP_T29SNK0_ML_P<3>
72 34
DP_T29SNK0_ML_N<3>
72 34
DP_T29SNK0_ML_P<2>
72 34
DP_T29SNK0_ML_N<2>
72 34
DP_T29SNK0_ML_P<1>
72 34
DP_T29SNK0_ML_N<1>
72 34
DP_T29SNK0_ML_P<0>
72 34
DP_T29SNK0_ML_N<0>
72 34
DP_T29SNK0_AUXCH_P
72 34
DP_T29SNK0_AUXCH_N
72 34
DP_T29SNK0_HPD
TP_T29_HDMI_5V_OUT
I2C_T29_SCL
72 44
OUT
I2C_T29_SDA
72 44
BI
U6
EE_DI
P2
EE_DO
U3
EE_CS*
EEPROM
EE_CLK
THERM_DP
TEST_EN
TEST_PWR_GOOD
DPSNK0_ML_LANE_3P_IN0_HDMI_TMDS_CLK_P
DPSNK0_ML_LANE_3N_IN0_HDMI_TMDS_CLK_N
DPSNK0_ML_LANE_2P_IN0_HDMI_TMDS_O_P
DPSNK0_ML_LANE_2N_IN0_HDMI_TMDS_0_N
DPSNK0_ML_LANE_1P_IN0_HDMI_TMDS_1_P
DPSNK0_ML_LANE_1N_IN0_HDMI_TMDS_1_N
DPSNK0_ML_LANE_0P_IN0_HDMI_TMDS_2_P
DPSNK0_ML_LANE_0N_IN0_HDMI_TMDS_2_N
DPSNK0_AUX_CHP
DPSNK0_AUX_CHN
TEST PORT
DPSNK0_HDMI_IN_HOT_PLUG_DET
HDMI_5V_OUT
CIO_MDC
CIO_MDIO
HDMI
T10
U10
T11
U11
N1
B2
E2
D1
T8
U8
T9
U9
T7
U7
T4
U1
C1
F1
8 7 5 4 2 1
OMIT_TABLE
U3600
EAGLE_RIDGE-192
FCBGA
(1 OF 2)
PCIE GEN2
MISC
DPSRC0_ML_LANE_3P_OUT0_HDMI_TMDS_2_P
DPSRC0_ML_LANE_3N_OUT0_HDMI_TMDS_2_N
SINK PORT 0
DPSRC0_ML_LANE_0P_OUT0_HDMI_TMDS_CLK_P
DPSRC0_ML_LANE_0N_OUT0_HDMI_TMDS_CLK_N
SOURCE PORT 0
HDMI/
DISPLAYPORT
PORTS
PCIE_RST_0*
PCIE_RST_1*
PCIE_RST_2*
PCIE_RST_3*
POWER ON RESET
REFCLK_100_IN_P
REFCLK_100_IN_N
XTAL_25_IN
XTAL_25_OUT
CLOCKS
TMU_CLK_OUT
TMU_CLK_IN
DPSRC0_HOT_PLUG_DET
HDMI_SCL_IN
HDMI
HDMI_OUT_HOT_PLUG_DET
HDMI_SDA_IN
PRT0_CIOT_P
PRT0_CIOT_N
PRT0_CIOR_P
PRT0_CIOR_N
CIO_0_LSEO
CIO_0_LSOE
PRT1_CIOT_P
PRT1_CIOT_N
PRT1_CIOR_P
PRT1_CIOR_N
PORT1 PORT0
CIO_1_LSEO
CIO_1_LSOE
CIO_PLUG_EVENT
PETP_0
PETN_0
PETP_1
PETN_1
TRANSMIT
PETP_2
PETN_2
PETP_3
PETN_3
WAKE*
PERST*
RSENSE
RBIAS
JTAG
DP_ATEST
DP_RES
T14
T15
M14
M15
H14
H15
D14
D15
M2
C2
C8
C7
R1
L1
L2
G2
T3
TDI
T5
TMS
R2
TCK
U4
TDO
A12
B12
D11
C11
U5
M1
T12
U12
N12
R12
T6
U15
U14
B1
A2
F3
A6
B6
A4
B4
H2
K1
B10
A10
A8
B8
J1
K2
H1
NOTE: All unused LSOE/EO pairs should be aliased
together. Other signals okay to float (TP/NC).
345678
PCIE_T29_D2R_C_P<0>
70
PCIE_T29_D2R_C_N<0>
PCIE_T29_D2R_C_P<1>
70
PCIE_T29_D2R_C_N<1>
70
PCIE_T29_D2R_C_P<2>
70
PCIE_T29_D2R_C_N<2>
70
PCIE_T29_D2R_C_P<3>
70
PCIE_T29_D2R_C_N<3>
70
T29_PCIE_WAKE_L
T29_RESET_L
T29_RSENSE
T29_RBIAS
Not used in host mode.
TP_T29_PCIE_RESET0_L
TP_T29_PCIE_RESET1_L
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L
JTAG_T29_TDI
JTAG_T29_TMS
JTAG_T29_TCK
JTAG_T29_TDO
PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N
SYSCLK_CLK25M_T29_R
70
TP_T29_XTAL25OUT
T29_TMU_CLK_OUT
T29_TMU_CLK_IN
DP_T29SRC_ML_CP<3>
DP_T29SRC_ML_CN<3>
DP_T29SRC_ML_CP<0>
DP_T29SRC_ML_CN<0>
DP_T29SRC_HPD
T29_DP_ATEST
T29_DP_RES
T29_HDMI_SCL_IN
T29_HDMI_SDA_IN
T29_HDMI_OUT_HPD
T29_R2D_C_P<0>
T29_R2D_C_N<0>
T29_D2R_P<0>
T29_D2R_N<0>
T29_LSEO<0>
T29_LSOE<0>
T29_R2D_C_P<1>
T29_R2D_C_N<1>
T29_D2R_P<1>
T29_D2R_N<1>
T29_LSEO<1>
T29_LSOE<1>
T29_CIO_PLUG_EVENT
36
34
34
34
34
R3685
1/20W
14K
1%
MF
201
NO STUFF
R3699
10K
1/20W
R3661
R3662
R3663
R3664
1
2
OUT
OUT
OUT
OUT
OUT
OUT
1
R3655
1.0K
0.1%
1/16W
TF
402
2
1
5%
MF
201
2
1
R3632
100K
5%
1/20W
MF
201
2
IN
IN
IN
IN
IN
IN
C3640
C3641
C3642
C3643
C3644
C3645
C3646
C3647
R3651
IN
IN
IN
IN
OUT
IN
IN
1 2
1 2
0
1 2
1 2
72 64
72 64
72 64
72 64
64
64
72 64
72 64
72 64
72 64
64
64
36
8
16
8
8
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
70 16
70 16
10K
2 1
1 2
PCIE_T29_D2R_P<0>
0201
16V10%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
5%01/20W
5%01/20W
C3685
100PF
CERM
X5R-CERM
PCIE_T29_D2R_N<0>
0201
16V10%
X5R-CERM
PCIE_T29_D2R_P<1>
10%
10%
10%
=PP3V3_T29_RTR
1
R3698
10K
5%
1/20W
MF
201
2
1/20W
1/20W0MF5%
0201
16V
X5R-CERM
PCIE_T29_D2R_N<1>
0201
16V10%
X5R-CERM
PCIE_T29_D2R_P<2>
0201
16V10%
X5R-CERM
PCIE_T29_D2R_N<2>
0201
16V10%
X5R-CERM
PCIE_T29_D2R_P<3>
0201
16V
X5R-CERM
PCIE_T29_D2R_N<3>
X5R-CERM
16V
0201
=PP3V3_T29_RTR
1/20W
MF5%
R3695
1 2
1
R3696
1K
5%
1/20W
MF
201
2
201
MF
201
MF5%
201
MF
201
806
1/20W
201
1%
MF
201
7
7
SYSCLK_CLK25M_T29
100pF SRF > 40MHz
1
1
C3686
5%
25V
201
0.01UF
10%
10V
2
2
X5R
201
SYNC_MASTER=K78_MLB
PAGE TITLE
T29 Host (1 of 2)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
70
8
OUT
70
8
OUT
70
8
OUT
70
8
OUT
70
8
OUT
70
8
OUT
70
8
OUT
70
8
OUT
36 35 34
36 35 34
=PP3V3_T29_RTR
IN
36 35 34
7
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
36 OF 109
SHEET
34 OF 75
D
C
70 25
B
A
SIZE
D
Page 35
www.laptopblue.vn
345678
2 1
D
=PP1V05_T29_RTR
35
7
2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA
C3700
10UF
CERM-X5R
C3701
10UF
CERM-X5R
6.3V
0402
6.3V
0402
1
1
C3705
20%
20%
1.0UF
20%
6.3V
2
2
X5R
0201-MUR
1
1
C3710
1.0UF
20%
6.3V
2
2
X5R
0201-MUR
1
2
1
2
C3706
1.0UF
20%
6.3V
X5R
0201-MUR
C3711
1.0UF
20%
6.3V
X5R
0201-MUR
1
2
1
2
C3707
1.0UF
20%
6.3V
X5R
0201-MUR
C3712
1.0UF
20%
6.3V
X5R
0201-MUR
1
2
1
2
C3708
1.0UF
20%
6.3V
X5R
0201-MUR
C3713
1.0UF
20%
6.3V
X5R
0201-MUR
1
2
1
2
C3709
1.0UF
20%
6.3V
X5R
0201-MUR
C3714
1.0UF
20%
6.3V
X5R
0201-MUR
H10
J10
C10
C12
D10
D12
F11
F12
G11
G12
H3
H5
H6
H7
H8
J3
J5
J6
J7
J8
D7
D8
VCC1P0
VCC1P0_PE
CRITICAL
OMIT_TABLE
U3600
EAGLE_RIDGE-192
FCBGA
(2 OF 2)
VCC
VCC3P3
VCC3P3_CIO
VCC3P3_DP
VDD1P0_DP
C3
D3
C5
C6
D5
D6
N8
N10
R8
R10
N5
N6
R5
R6
C3744
1.0UF
0201-MUR
C3753
1.0UF
0201-MUR
=PP3V3_T29_RTR
135 mA (Single-Port)
152 mA (Dual-Port)
1
20%
6.3V
2
X5R
1
20%
6.3V
2
X5R
1
2
C3720
1.0UF
20%
6.3V
X5R
0201-MUR
C3743
1.0UF
0201-MUR
C3752
1.0UF
0201-MUR
1
20%
6.3V
2
X5R
1
20%
6.3V
2
X5R
1
2
C3721
1.0UF
20%
6.3V
X5R
0201-MUR
C3745
1.0UF
0201-MUR
C3751
1.0UF
0201-MUR
1
1
C3746
20%
6.3V
X5R
20%
6.3V
X5R
1.0UF
20%
6.3V
2
2
X5R
0201-MUR
1
C3750
1.0UF
1
2
C3722
1.0UF
20%
6.3V
X5R
0201-MUR
0201-MUR
6.3V
2
1
2
PP3V3_T29_DP
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
20%
2
X5R
PP1V05_T29_VDD_DP
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
C3747
1.0UF
20%
6.3V
X5R
0201-MUR
1
C3748
10UF
20%
6.3V
2
CERM-X5R
0402
1
C3749
10UF
20%
6.3V
2
CERM-X5R
0402
R3750
1 2
5%01/20W
MF
201
R3720
1 2
1/20W05%
201
MF
EDP: 200 mA
0-ohms are placeholders for now, replace
with proper values after characterization.
=PP1V05_T29_RTR
2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA
36 34
7
35
7
C
A1
F5
F6
F7
F8
F10
G3
G5
G6
G7
G8
G10
L3
L5
VSS
L6
L7
L8
L10
M3
M5
M10
M11
M12
N11
R11
T13
U13
M6
M7
M8
N3
N7
R3
VSSDP
R7
J2
GPIO_0
N2
GPIO_4
U2
GPIO_5
D2
GPIO_6
B
1
R3723
10K
1/20W
1
5%
MF
201
2
2
1
R3722
10K 10K
5%
1/20W
MF
201
2
R3721
5%
1/20W
MF
201
1
R3724
10K
5%
1/20W
MF
201
2
T29_GPIO<0>
T29_GPIO<4>
T29_GPIO<5>
T29_GPIO<6>
GND
VSSPE
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
A3
A5
A7
A9
A11
B3
B5
B7
B9
B11
C14
C15
E14
E15
G14
G15
H11
H12
J11
J12
J14
J15
L11
L12
L14
L15
N14
N15
R14
R15
E1
F2
G1
T2
T1
T29_GPIO<7>
T29_GPIO<8>
T29_GPIO<9>
T29_GPIO<10>
T29_GPIO<11>
R3733
10K
1/20W
R3730
10K10K
5%
1/20W
MF
1
R3734
10K
5%
1/20W
MF
201201
2
1
5%
MF
201
2
R3732
10K
5%
1/20W
MF
2
R3731
5%
1/20W
MF
201201
2
2
1
1
1
D
C
B
A
Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
8 7 5 4 2 1
SIZE
A
D
SYNC_MASTER=K78_MLB
PAGE TITLE
T29 Host (2 of 2)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
37 OF 109
SHEET
35 OF 75
36
Page 36
Page Notes
Power aliases required by this page:
- =PPVIN_SW_T29BST (8-13V Boost Input)
- =PP18V_T29_REG (18V Boost Output)
- =PP3V3_T29_P3V3T29FET (3.3V FET Input)
- =PP3V3_T29_FET (3.3V FET Output)
- =PP3V3_S0_T29PWRCTL
- =PP1V05_T29_P1V05T29FET (1.05V FET Input)
- =PP1V05_T29_FET (1.05V FET Output)
Signal aliases required by this page:
- =T29_CLKREQ_L
D
- =T29_RESET_L
BOM options provided by this page:
T29BST:Y - Stuffs 18V boost circuitry.
C
=PP3V3_S0_T29PWRCTL
7
Platform (PCIe) Reset
=T29_RESET_L
25
IN
Open-Drain GPIO
T29_SW_RESET_L
19
IN
T29_CLKREQ_L
16
OUT
Pull-up provided by SB page.
Supervisor & CLKREQ# Isolation
R3803
1/20W
10K
1
C3800
0.1UF
10%
16V
2
X5R-CERM
0201
12
5%
MF
201
3
MR*
6
EN
8
OUT
(OD)
1
VDD
U3800
SLG4AP016V
TDFN
+
-
DLY
THRM
GND
PAD
5
CRITICAL
SENSE
0.7V
RESET*
IN
9
=PP3V3_T29_RTR
1
R3807
100K
5%
1/20W
MF
201
2
2
4
DLY = 60 ms +/- 20%
7
=PPVIN_SW_T29BST
7 8
8-13V Input
Changes required
for 2S.
PP1V05_T29
T29_RESET_L
=T29_CLKREQ_L
T29_CLKREQ_ISOL_L
MAKE_BASE=TRUE
T29BST:Y
R3880
470K
1/20W
T29BST:Y
R3881
150K
1/20W
64 65
IN
7
34 35
6 7
1
5%
MF
201
2
1
5%
MF
201
2
T29_A_HV_EN
T29BST:Y
1
C3880
0.1UF
10%
25V
2
X5R
402
T29BST_PWREN_DIV_L
T29BST_PWREN_L
T29BST:Y
Q3805
SSM3K15FV
SOD-VESM-HF
34
OUT
34
IN
www.laptopblue.vn
SI8409DB:
CRITICAL
T29BST:Y
Q3880
SI8409DB
R3820
0.010
1 2
1%
1/4W
MF
805
1
G S
4
PPVIN_SW_T29BST_R
3
D
2
UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
SGD
1
T29BST:Y
C3892
T29BST:Y
1
R3892
73.2K
1%
1/20W
MF
201
2
<R2>
4.7UF
Vds(max): -30V
Vgs(max): +/-12V
Vgs(th): -1.4V
Rds(on): 46mOhm @ 4.5V Vgs
Id(max): 3.7A @ 70C
BGA
2 3
1
10%
10V
2
X5R
805
PPVIN_SW_T29BST
6 7
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
Voltage not specified here,
add property on another page.
1
C3887
47PF
5%
25V
2
NP0-C0G
201
T29BST_VC_RC
T29BST:Y
1
C3893
3300PF
10%
10V
2
X7R
201
T29BST:Y
R3893
10K
1/20W
T29BST:Y
1
1%
MF
201
2
R3894
41.2K
1/20W
T29BST:Y
R3891
200K
1/20W
1
1%
MF
201
2
201
<R1>
6
1
1
1%
MF
2
D
S G
1
2
T29BST:Y
C3890
10UF
T29BST_EN_UVLO
T29BST_INTVCC
T29BST_VC
T29BST_RT
T29BST_SS
T29BST:Y
C3894
0.33UF
10%
6.3V
CERM-X5R
402
GND_T29BST_SGND
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
T29BST:Y
Q3888
SSM6N37FEAPE
SOT563
Max Vgs: 10V
2
T29BST_SHDN_DIV
T29BST:Y
1
R3887
330K
5%
1/20W
MF
201
2
T29 18V Boost Regulator
T29BST:Y
1
10%
25V
2
X5R
805
C3891
10UF
1
10%
25V
2
X5R
805
3
4
1
2
D
S G
25
28
30
33
32
34
T29BST:Y
R3888
330K
5%
1/20W
MF
201
T29BST:Y
Q3888
SSM6N37FEAPE
SOT563
CRITICAL
T29BST:Y
L3895
6.8UH-4.0A
1 2
PIMB062D-SM
27
VIN
CRITICAL
EN/UVLO
INTVCC
T29BST:Y
U3890
LT3957
QFN
VC
RT
SS
SYNC
SGND
4
232437
SGND shorted to
GND inside package,
no XW necessary.
5
1213141516
SMC_DELAYED_PWRGD
345678
T29BST_BOOST
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
8
9
202138
SW
6
SNS1
3
SNS2
1
2
10
NC
35
36
31
FBX
GND
17
T29BST_SNS1
T29BST:Y
R3889
1/20W
201
T29BST_SNS2
XW3895
T29BST_VSNS
NC
1
C3888
10PF
5%
50V
2
CERM
402
T29BST_FBX
NO STUFF
1
C3889
100PF
5%
50V
2
CERM
402
T29BST:Y
R3895
T29BST:Y
R3896
2 1
CRITICAL
12
1
1%
2
1
1%
402
2
T29BST:Y
1
D3895
POWERDI-123
DFLS230L
2
PLACE_NEAR=C3895.1:2 mm
T29BST:Y
1
C3895
4.7UF
10%
50V
2
X7R-CERM
1206
T29BST:Y
1
C3896
4.7UF
10%
50V
2
X7R-CERM
1206
T29BST:Y
1
C3897
4.7UF
10%
50V
2
X7R-CERM
1206
T29BST:Y
C3898
4.7UF
X7R-CERM
10%
50V
1206
1
0
5%
MF
2
133K
1/16W
MF-LF
<Ra>
15.8K
1/16W
MF-LF
<Rb>
SM
402
=PP15V_T29_REG
Vout = 15.1V
Max Current = 1.0A
Freq = 300KHz
T29BST:Y
1
1
C3899
0.001UF
10%
50V
2
2
X7R
402
D
7 8
Vout = 1.6V * (1 + Ra / Rb)
C
25 41
IN
B
=PP3V3_S0_P3V3T29FET
7
1
C3810
1UF
10%
6.3V
2
CERM
402
3.3V T29 Switch
U3810
TPS22924
CSP
A2
B2
C2
VIN
CRITICAL
ON
GND
A1
VOUT
B1
C1
=PP3V3_T29_FET
Max Current = 1.7A (85C)
U3810 & U3815/U3816
Part
Type
R(on)
7
TPS22924C
Load Switch
18 mOhm Typ
50 mOhm Max
B
Max Output: 2A per IC
1.05V T29 Switch
U3815
=PP1V05_S0_P1V05T29FET
C3815
1UF
1
10%
6.3V
2
CERM
402
A2
B2
C2
TPS22924
VIN
CRITICAL
ON
CSP
VOUT
GND
C1
A
U3816
TPS22924
CSP
T29_PWR_EN
19
IN
Pull-up provided by SB page.
A2
B2
C2
VIN
CRITICAL
ON
VOUT
GND
C1
8 7 5 4 2 1
=PP1V05_T29_FET
A1
Max Current = 3.4A (85C)
B1
A1
B1
U3816.A2:
PLACE_NEAR=U3815.B2:3 mm
7 7
SIZE
A
D
SYNC_MASTER=K78_MLB
PAGE TITLE
T29 Power Support
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
38 OF 109
SHEET
36 OF 75
36
Page 37
www.laptopblue.vn
MOSFET
CHANNEL
RDS(ON)
LOADING
345678
3V S3 WLAN FET
TPCP8102
P-TYPE
20-30 MOHM @2.5V
0.750 A (EDP)
2 1
D
CRITICAL
R4052
0.020
1%
MIN_LINE_WIDTH=1 mm
AIRPORT
CRITICAL
J4001
SSD-K99
F-RT-SM1
1
2
3
4
5
6
7
8
9
10
C
11
12
13
14
15
16
17
18
19
20
21
PCIE_AP_R2D_N
70
6
70
6
PCIE_AP_R2D_P
C4030
PLACEMENT_NOTE=Place close to J4001.
1 2
6.3V
0.1UF
0.1UF
X5R20110%
10% 201X5R
PLACEMENT_NOTE=Place close to J4001.
C4031
1 2
6.3V
WIFI_EVENT_L
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_WAKE_L
41
6
OUT
70 16
IN
70 16
IN
70 16
6
IN
70 16
6
IN
70 16
6
OUT
70 16
6
OUT
17
6
OUT
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
1
C4021
0.1UF
10%
6.3V
2
X5R
201
PLACEMENT_NOTE=Place close to Q4050.
PP3V3_WLAN_F
6
1
C4020
10UF
20%
10V
2
X5R
603
PLACEMENT_NOTE=Place close to Q4050.
0.25W
MF-LF
805
1 2
3 4
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
PP3V3_WLAN_R
ISNS_AIRPORT_P
ISNS_AIRPORT_N
TPCP8102
5 6 7 8
C4050
0.1UF
1 2
10%
16V
X5R-CERM
0201
CRITICAL
Q4050
23V1K-SM
D
G
4
74 46
OUT
74 46
OUT
S
1 2 3
C4051
0.033UF
P3V3WLAN_SS
10%
16V
X5R
402
1
2
R4050
100K
1 2
5%
1/20W
MF
201
1
R4051
10K
5%
1/20W
MF
201
2
=PP3V3_S3_WLAN
PM_WLAN_EN_L
IN
D
37
7
62
C
514S0335
BLUETOOTH
B
A
8 7 5 4 2 1
1
C4032
0.1UF
10%
6.3V
2
X5R
201
PLACE_NEAR=J4001.18:1.5mm
USB_BT_N
USB_BT_P
=PP3V3_S3_BT
BI
BI
7 6
R4053
100K
1/20W
201
69 24
6
69 24
6
B
=PP3V3_S3_WLAN
DLY = 60 MS +/- 20%
1
CRITICAL
VDD
1
5%
MF
2
R4054
232K
1/20W
R4055
100K
1/20W
201
201
1
1%
MF
2
1
1%
MF
2
P3V3WLAN_VMON
AP_RESET_CONN_L
6
AP_CLKREQ_Q_L
6
SLG4AP016V
2
SENSE
0.7V
4
RESET*
7
IN
U4002
TDFN
+
-
THRM
PAD
9
DLY
GND
3
MR*
6
EN
8
OUT
(OD)
5
C4053
0.1UF
6.3V
10%
X5R
201
1
2
37
7
AP_RESET_L
AP_PWR_EN
AP_CLKREQ_L_R
SYNC_MASTER=K21_MLB
PAGE TITLE
IN
IN
25
62 18
R4090
1/20W
201
0
5%
MF
X21 WIRELESS CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
12
AP_CLKREQ_L
OUT
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
40 OF 109
SHEET
37 OF 75
23 16
A
SIZE
D
36
Page 38
www.laptopblue.vn
345678
2 1
D
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
1
C4501
0.1UF
10%
16V
2
X5R-CERM
0201
PLACE_NEAR=J4501.1:1.5mm
PP3V3_S0_HDD_R
SATA SSD
C
B
CRITICAL
J4501
SSD-K99
F-RT-SM1
1
2
3
4
5
6
7
8
9
10
11
12
13
NC
14
NC
15
16
17
18
19
20
21
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
SMC_HDD_OOB_TEMP_CONN
6
SMC_HDD_TEMP_CTL_CONN
6
TP_SSD_RSRVD
69
6
SATA_HDD_D2R_C_N
69
6
69
69
SATA_HDD_D2R_C_P
SATA_HDD_R2D_N
6
SATA_HDD_R2D_P
6
R4510
0
1 2
5%
1/20W
MF
201
R4511
0
1 2
5%
1/20W
MF
201
C4516
1 2
0.01UF
PLACE_NEAR=J4501.3:1.5MM
PLACE_NEAR=J4501.4:1.5MM
C4515
1 2
0.01UF
10%
20110V X5R
X5R10% 10V
201
SMC_HDD_OOB_TEMP
SMC_HDD_TEMP_CTL
41
41
6
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
VOLTAGE=5V
C4511
C4510
PLACE_NEAR=J4501.7:1.5MM
1 2
0.01UF
1 2
0.01UF
PLACE_NEAR=J4501.8:1.5MM
CRITICAL
R4599
0.003
1%
1W
MF
0612
12
34
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_R2D_C_N
X5R10% 10V 201
SATA_HDD_R2D_C_P
X5R10% 20110V
=PP3V3_S0_HDD
OUT
OUT
IN
IN
7
ISNS_HDD_P
ISNS_HDD_N
69 16
69 16
69 16
69 16
74 46
OUT
74 46
OUT
D
C
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
SATA CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
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A
D
Page 39
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345678
2 1
D
D
USB Port Power Switch
Right USB Port A
CRITICAL
U4600
TPS2561DR
SON
USB_EN2
1/20W
201
2
IN_0
3
IN_1
10
FAULT1*
6
FAULT2*
NC
4
EN1
5
EN2
1
0
5%
MF
2
GND
1
=PP5V_S3_RTUSB
7
C
USB_EXTA_OC_L
24
OUT
=USB_PWR_EN
62 40
6
C4690
10UF
CERM-X5R
1
1
C4691
20%
6.3V
0402
0.1UF
10%
2
16V
2
X5R-CERM
0201
CRITICAL
1
C4696
220UF-35MOHM
20%
6.3V
2
POLY-TANT
CASE-B2-SM1
R4601
THRM
PAD
11
OUT1
OUT2
ILIM
9
8
7
NC
USB_ILIM
R4600
23.2K
1/16W
MF-LF
PP5V_S3_RTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
1
1%
402
2
C4695
10UF
CERM-X5R
1
20%
6.3V
2
0402
USB2_EXTA_MUXED_N
74
USB2_EXTA_MUXED_P
74
C4605
0.01UF
X5R-CERM
1
10%
16V
2
0201
Current limit (R4600): 2.3A max
CRITICAL
L4605
FERR-120-OHM-3A
1 2
0603
CRITICAL
L4600
90-OHM-100MA
DLP11S
SYM_VER-1
1 2
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
34
USB2_LT1_N
74
USB2_LT1_P
74
CRITICAL
J4600
USB-RIGHT-K99
F-RT-TH
5
VBUS
1
D-
2
D+
3
GND
4
5 4
2 3
IOIONC
NC
6
VBUS
1
GND
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
Place L4605 at connector pin
6
C
B
B
USB/SMC Debug Mux
=PP3V42_G3H_SMCUSBMUX
7
SMC_DEBUG_YES
69 24
69 24
SMC_RX_L
6
IN
SMC_TX_L
6
OUT
USB_EXTA_P
BI
USB_EXTA_N
BI
43 42 41
43 42 41
A
C4650
0.1UF
X5R-CERM
1
10%
16V
2
0201
5
4
7
6
8
M+
M-
PI3USB102ZLE
D+
D-
SMC_DEBUG_YES
VCC
U4650
TQFN
CRITICAL
GND
9
3
1
Y+
2
Y-
10
SELOE*
SMC_DEBUG_NO
R4651
1 2
1/20W
8 7 5 4 2 1
SMC_DEBUG_YES
1
R4650
10K
5%
1/20W
MF
201
2
USB_DEBUGPRT_EN_L
SEL=0 Choose SMC
SEL=1 Choose USB
0
5%
MF
201
SMC_DEBUG_NO
R4652
0
1 2
5%
1/20W
MF
201
41
IN
SIZE
A
D
SYNC_MASTER=K21_MLB
PAGE TITLE
External USB Connectors
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
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46 OF 109
SHEET
39 OF 75
36
Page 40
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345678
2 1
D
CRITICAL
J4700
AXK736327G
F-ST-SM
=PP3V42_G3H_ONEWIRE
7 6
SYS_ONEWIRE
41
6
BI
6
OUT
6
IN
6
OUT
44
6
BI
44
6
IN
44
6
IN
44
6
BI
19
6
IN
18
6
OUT
18
6
OUT
51
6
OUT
6
OUT
6
OUT
SMC_BC_ACOK
=USB_PWR_EN
SMC_LID
=I2C_LIO_SDA
=I2C_LIO_SCL
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
AUD_IPHS_SWITCH_EN
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
AUD_GPIO_3
SPKRAMP_INR_N
SPKRAMP_INR_P
PLACE_NEAR=J4700.23:1.5mm
C4710
0.1UF
X5R-CERM
0201
10%
16V
42 41
62 39
49 42 41
C
(Right Speaker Enable)
74 51
74 51
37
1
2
3
4
5
6
7
8
9
516S0862
10
12
14
16
18
20
22
24
26
28
30
32
34
36
11
13
15
17
19
21
23
25
27
29
31
33
35
1
38
2
=PP3V3_S0_AUDIO
USB_EXTD_N
USB_EXTD_P
USB_CAMERA_N
USB_CAMERA_P
HDA_SDOUT
HDA_BIT_CLK
HDA_SDIN0
USB_EXTD_OC_L
HDA_RST_L
HDA_SYNC
PLACE_NEAR=J4700.26:1.5mm
1
C4700
0.1UF
10%
16V
2
X5R-CERM
0201
7 6
69 24
6
BI
69 24
6
BI
69 18
6
BI
69 18
6
BI
70 16
6
IN
70 16
6
IN
70 16
6
OUT
24
6
OUT
70 16
6
IN
IN
70 16
6
=PP3V3R1V5_S0_AUDIO
PLACE_NEAR=J4700.34:1.5mm
1
C4720
0.1UF
10%
16V
2
X5R-CERM
0201
7 6
D
C
SIZE
B
A
D
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K21_MLB
PAGE TITLE
Left I/O (LIO) Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=11/09/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
47 OF 109
SHEET
40 OF 75
Page 41
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
D
SMC_P10
42
SMC_RSTGATE_L
42
OUT
36 25
23 17
70 25
62
17
6
6
6
6
6
25
6
38
38
44
42
49
6
6
44
ALL_SYS_PWRGD
IN
S5_PWRGD
IN
PM_DSW_PWRGD
OUT
OUT
PM_PWRBTN_L
OUT
SMC_P20
42
SMC_P24
42
SMC_P26
42
LPC_AD<0>
BI
LPC_AD<1>
BI
LPC_AD<2>
BI
LPC_AD<3>
BI
LPC_FRAME_L
IN
SMC_LRESET_L
IN
LPC_CLK33M_SMC
IN
LPC_SERIRQ
BI
SMC_HDD_TEMP_CTL
OUT
SMC_HDD_OOB_TEMP
IN
SMB_MGMT_DATA
BI
SMC_P43
42
SMC_GFX_THROTTLE_L
OUT
SMC_SYS_KBDLED
OUT
SMC_TX_L
OUT
SMC_RX_L
IN
SMB_0_S0_CLK
BI
62 52 25 23
70 43 16
70 43 16
70 43 16
C
70 43 16
70 43 16
43 16
43 42 41 39
43 42 41 39
NC
NC
NC
NC
NC
NC
(OC)
NC
NC
(OC)
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PP3V3_S5_AVREF_SMC
42
=PP3V3_S5_SMC
42
7
1
C4902
22UF
20%
10V
X5R-CERM
805
B12
P10
A13
P11
A12
P12
B13
P13
D11
P14
C13
P15
C12
D10
P17
D13
P20
E11
P21
D12
P22
F11
P23
E13
P24
E12
P25
F13
P26
E10
P27
A9
P30
D9
P31
C8
P32
B7
P33
A8
P34
D8
P35
D7
P36
D6
P37
D4
P40
A5
P41
B4
P42
A1
P43
C2
P44
B2
P45
C1
P46
C3
P47
G2
P50
F3
P51
E4
P52
U4900
DF2117RVPLP20HV
TLP-145V
(1 OF 3)
OMIT_TABLE
P60
P61
P62
P63
P64
P65
P66P16
P67
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P82
P83
P84
P85
P86
P90
P91
P92
P93
P94
P95
P96
P97
L13
K12
K11
J12
K13
J10
J11
H12
N10
M11
L10
N11
N12
M13
N13
L12
A7
B6
C7
D5
A6
B5
C6
J4
G3
H2
G1
H4
G4
F4
F1
SMC_PM_G2_EN
NC
NC
NC
SMC_ADAPTER_EN
NC
SMC_PROCHOT_3_3_LSMC_DELAYED_PWRGD
SMC_BIL_BUTTON_L
SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7
SMC_SCI_L
NC
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_PME_S4_WAKE_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_CLK32K
SMB_0_S0_DATA
(OC)
62
OUT
62 42 17
OUT
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
19 16
OUT
43 17
6
OUT
43 17
6
IN
OUT
IN
BI
IN
IN
IN
IN
IN
IN
IN
BI
43 42 41 39
6
43 42 41 39
6
44
49 42
6
42 40
6
49 42
6
62 26 17
62 49 26 17
62 17
42
44
1
C4903
0.1UF
20%
2
10V
2
CERM
402
R4999
4.7
1 2
5%
1/20W
MF
201
1
C4904
2
PLACE_NEAR=U4900.M12:3mm
PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V
53 43 42
6
IN
42
42
0.1UF
20%
10V
CERM
402
SMC_RESET_L
SMC_XTAL
SMC_EXTAL
345678
1
C4905
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U4900.M12:3mm
C4920
0.1UF
20%
10V
CERM
402
1
C4906
0.1UF
20%
10V
2
CERM
402
1
2
M12
AVCC
DF2117RVPLP20HV
B1
M1
VCC
U4900
TLP-145V
(3 OF 3)
L11
H10
E1
VCL
AVREF
OMIT_TABLE
D3
RES*
A3
XTAL
A2
EXTAL
ETRST*
VSS
D2
L3
C5
F10
B11
AVSS
XW4900
SM
PLACE_NEAR=U4900.L3:4mm
2 1
BYPASS=U4900.E1:D2:3 mm
SMC_VCL
1
C4907
0.47UF
20%
4V
2
CERM-X5R-1
MD1
MD2
NMI
201
E5
NC
NC
D1
H1
E3
H3
L9
12
SMC_KBC_MDE
1
R4902
10K
5%
1/20W
MF
201
2
GND_SMC_AVSS
R4909
1
R4998
10K
5%
1/20W
MF
201
2
1/20W
10K
1
5%
MF
201
2
46 45 42
1
R4901
10K
5%
1/20W
MF
201
2
SMC_MD1
SMC_NMI
SMC_TRST_L
NO STUFF
1
R4903
0
5%
1/20W
MF
201
2
D
43
6
IN
43
6
IN
43
6
IN
C
SMC_PA0_PU
42
SPI_DESCRIPTOR_OVERRIDE_L
16
OUT
PM_SYSRST_L
25 17
OUT
USB_DEBUGPRT_EN_L
39
OUT
MEM_EVENT_L
42
BI
WIFI_EVENT_L
B
A
40
62 42
42 19
62 42
6
6
42
42
48
42
42
42
48
42
42
42
42
42
42
42
42
42
42
42
SYS_ONEWIRE
BI
SMC_BATLOW_L
OUT
SMC_RUNTIME_SCI_L
OUT
SMC_S4_WAKESRC_EN
OUT
SMC_PB4
42
SMC_DP_HPD_L
IN
SMC_GFX_OVERTEMP_L
IN
SMC_FAN_0_CTL
OUT
SMC_FAN_1_CTL
OUT
SMC_FAN_2_CTL
OUT
SMC_FAN_3_CTL
OUT
SMC_FAN_0_TACH
IN
SMC_FAN_1_TACH
IN
SMC_FAN_2_TACH
IN
SMC_FAN_3_TACH
IN
SMC_ADC8
IN
SMC_ADC9
IN
SMC_ADC10
IN
SMC_ADC11
IN
SMC_ADC12
IN
SMC_ADC13
IN
SMC_ADC14
IN
SMC_ADC15
IN
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
NC
NC
NC
N3
PA0
N1
PA1
M3
PA2
M2
PA3
N2
PA4
L1
PA5
K3
PA6
L2
PA7
B8
PB0
C9
PB1
B9
PB2
A10
PB3
C10
PB4
B10
PB5
C11
PB6
A11
PB7
G11
PC0
G13
PC1
F12
PC2
H13
PC3
G10
PC4
G12
PC5
H11
PC6
J13
PC7
M10
PD0
N9
PD1
K10
PD2
L8
PD3
M9
PD4
N8
PD5
K9
PD6
L7
PD7
8 7 5 4 2 1
U4900
DF2117RVPLP20HV
TLP-145V
(2 OF 3)
OMIT_TABLE
PECI/PH3
PEVREF/PH4
PEVSTP/PH5
PE0
PE1
PE2
PE3
PE4
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
K1
J3
K2
J1
K4
K5
N5
M6
L5
M5
N4
L4
M4
M8
N7
K8
K7
K6
N6
M7
L6
E2
F2
J2
A4
B3
C4
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
NC
NC
NC
NC
NC
NC
NC
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
G3_POWERON_L
SMC_LID
SMC_PF5
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
CPU_PECI_R
PVCCIO_S0_SMC_R
PM_PECI_PWRGD_R
C4910
0.1UF
CERM
42
IN
43 42
6
IN
43 42
6
IN
43 42
6
OUT
43 42
6
IN
42 37
INBI
49 42 40
6
IN
42
42
IN
44
BI
44
BI
44
BI
44
BI
44
BI
44
BI
42
OUT
42
OUT
1
20%
10V
2
402
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
R4910
43
1 2
5%
1/20W
MF
201
R4911
0
1 2
5%
1/20W
MF
201
R4912
0
1 2
5%
1/20W
MF
201
CPU_PECI
=PPVCCIO_S0_SMC
PM_PECI_PWRGD
67 19 10
7
62
SYNC_MASTER=K78_MLB
PAGE TITLE
SMC
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
49 OF 109
SHEET
41 OF 75
SIZE
B
A
D
36
Page 42
2 1
1
R5061
100K
5%
1/20W
MF
201
2
CPU_PROCHOT_BUF
3
Q5060
DMB53D0UV
SOT-563
4
2
Check with SMC pullup S0
R5075
R5070
R5072
R5071
R5073
R5074
R5077
R5078
R5079
R5080
R5081
R5087
R5093
R5091
R5094
R5085
R5086
R5088
R5090
1
R5060
10K
5%
1/20W
MF
201
2
SMC_PROCHOT_3_3_L
6
D
G
S
1
10K
1 2
10K
1 2
10K
1 2
100K
1 2
10K
1 2
100K
1 2
10K
1 2
10K
1 2
10K
1 2
10K
1 2
10K
1 2
470K
1 2
10K
1 2
NOSTUFF
100K
1 2
100K
1 2
NOSTUFF
10K
1 2
10K
1 2
10K
1 2
100K
1 2
Q5060
DMB53D0UV
SOT-563
42
7
5%
42 41
7
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
=PP3V3_S0_SMC
1/20W
MF
=PP3V3_S5_SMC
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
MF
1/20W
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
MF
1/20W
MF
1/20W
TO SMC
OUT
IN
IN
201
201
201
201
201
201
201
201
201
201
201
201
201
201
201
201
201
201
201
41
D
41
C
41
B
6
1
3
4
345678
1 2
D
S G
D
S G
R5062
3.3K
CPU_PROCHOT_L_R
5%
1/20W
MF
201
Q5059
SSM6N37FEAPE
SOT563
2
SMC_PROCHOT
Q5059
SSM6N37FEAPE
SOT563
5
SMC_THRMTRIP
PROCHOT Level Shifting to 3V3
=PP3V3_S0_SMC
42
7
5
MEM_EVENT_L
41
SMC_ONOFF_L
49 42 41
6
G3_POWERON_L
41
SMC_LID
49 41 40
6
SMC_TX_L
43 41 39
6
SMC_RX_L
43 41 39
6
SMC_TMS
43 41
6
SMC_TDO
43 41
6
SMC_TDI
43 41
6
SMC_TCK
43 41
6
SMC_BIL_BUTTON_L
41
SMC_BC_ACOK
42 41 40
6
SMS_INT_L
42
SMC_PA0_PU
42 41
SMC_RUNTIME_SCI_L
41 19
SMC_ADAPTER_EN
62 41 17
SMC_CASE_OPEN
41
SMC_PB4
41
SMC_S4_WAKESRC_EN
62 41
www.laptopblue.vn
R5012
1 2
1/20W
201
41
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
22
5%
MF
NC_SMC_FAN_2_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_CTL
NC_SMC_FAN_3_TACH
SMC_BC_ACOK
SMS_INT_L
SMC_CPU_VSENSE
SMC_CPU_ISENSE
SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_GFX_VSENSE
SMC_GFX_ISENSE
SMC_1V5S3_ISENSE
SMC_CPUVCCIO_ISENSE
SMC_LCDBKLT_ISENSE
SMC_WLAN_ISENSE
SMC_HDD_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
TP_SMC_ADC13
TP_SMC_ADC15
TP_SMC_P10
TP_SMC_P20
TP_SMC_P24
SMC_BMON_MUX_SEL
TP_SMC_P43
TP_SMC_PF5
TP_SMC_RSTGATE_L
SMC_CLK32K
42 41 40
6
42
45
45
45
46
45
45
46
45
46
46
46
45
46
46
41
OUT
1
R5076
100K
5%
1/20W
MF
201
2
SMC_PME_S4_WAKE_L
TO CPU
67 57 10
19
=PP3V3_S4_SMC
MAKE_BASE=TRUE
CPU_PROCHOT_L
BI
PM_THRMTRIP_L_R
OUT
42
7
49 41
6
OUT
SMC_FAN_2_CTL
D
53 43 41
1
R5020
100K
2
3
2
5%
1/20W
MF
201
41
SMC_FAN_2_TACH
41
SMC_FAN_3_CTL
41
SMC_FAN_3_TACH
41
=CHGR_ACOK
53 45
=SMC_SMS_INT
41
SMC_ADC0
41
SMC_ADC1
41
SMC_ADC2
41
SMC_ADC3
41
SMC_ADC4
41
SMC_ADC5
41
SMC_ADC6
41
SMC_ADC7
41
SMC_ADC8
41
SMC_ADC9
41
SMC_ADC10
41
SMC_ADC11
41
SMC_ADC12
41
SMC_ADC13
41
SMC_ADC15
41
SMC_P10
41
SMC_P20
41
SMC_P24
41
SMC_P26
41
SMC_P43
41
SMC_PF5
41
SMC_RSTGATE_L
41
PLACE_NEAR=U1800.N14:5.1mm
=PP3V3_S4_SMC
SMC_DP_HPD_L
42
7
OUT
SMC Reset "Button", Supervisor & AVREF Supply
=PP3V3_S5_SMC
42 41
7
=PPVIN_S5_SMCVREF
7
Desktops: 5V
Mobiles: 3.42V
1
C5020
0.47UF
10%
6.3V
2
CERM-X5R
C5001
0.01UF
402
1
10%
10V
2
X5R
201
49 42 41
IN
SMC_ONOFF_L
6
IN
SMC_MANUAL_RST_L
OMIT
1
R5001
0
5%
1/10W
MF-LF
603
2
SILK_PART=SMC_RST
D
SMC_TPAD_RST_L
49
6
1
V+
VREF-3.3V-VDET-3.0V
6
MR1*
(IPU)
7
MR2*
(IPU)
4
DELAY
GND
2
U5010
DFN
SN0903048
3
VIN
RESET*
REFOUT
THRM
PAD
9
PLACEMENT_NOTE=Place R5001 on BOTTOM side
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
5
8
C5025
10uF
20%
6.3V
X5R
603 201
1
R5000
100K
5%
1/20W
MF
201
2
1
2
SMC_RESET_L
PP3V3_S5_AVREF_SMC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
1
C5026
0.01UF
10%
10V
2
X5R
GND_SMC_AVSS
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V
6
OUT
41
46 45 41
NOTE: Internal pull-ups are to VIN, not V+.
Debug Power "Buttons"
SMC_ONOFF_L
1
0
5%
603
2
OMIT
1
R5015
0
PLACE_SIDE=TOP
5%
1/10W
MF-LF
603
2
SILK_PART=PWR_BTN
C
PLACE_SIDE=BOTTOM
R5016
1/10W
MF-LF
SILK_PART=PWR_BTN
OMIT
49 42 41
6
OUT
PM_CLK32K_SUSCLK_R
17
IN
SMC Crystal Circuit
R5010
0
SMC_XTAL
41
B
SMC_EXTAL
41
NO STUFF
1
R5011
1M
5%
1/20W
MF
201
2
1 2
5%
1/20W
MF
201
SMC_XTAL_R
CRITICAL
Y5010
20MHZ
SM-2.5X2.0MM
C5010
15PF
1 2
5%
25V
NPO
NC
201
2 4
NC
C5011
1 3
15PF
1 2
5%
25V
NPO
201
DP_A_EXT_HPD
64
IN
Q5020
SSM3K15FV
SOD-VESM-HF
1
G S
BATLOW# Isolation
=PP3V3_S5_SMCBATLOW
7
CRITICAL
1
R5040
100K
5%
1/20W
MF
201
2
SMC_BATLOW_L
62 41
A
IN
Q5040
SSM3K15FV
SOD-VESM-HF
3
D
R5041
0
1 2
5%
1/20W
MF
201
NOSTUFF
Internal 20K pull-up on PM_BATLOW_L in PCH.
8 7 5 4 2 1
1
GS
2
=PP3V3_SUS_SMC
PM_BATLOW_L
7
Below connections are different from K91
SMC_PA0_PU
SMC_FAN_1_CTL
41
SMC_FAN_1_TACH
17
OUT
41
SMC_ADC14
41
SMC_GFX_THROTTLE_L
41
SMC_GFX_OVERTEMP_L
41
R5095
HISIDE_ISENSE_OC
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_1_TACH
MAKE_BASE=TRUE
SMC_HS_COMPUTING_ISENSE
MAKE_BASE=TRUE
TP_SMC_GFX_THROTTLE_L
MAKE_BASE=TRUE
10K
1 2
42 41
=PP3V3_S5_SMC
7
5%
1/20W
46 42 41
SIZE
A
D
SYNC_MASTER=K78_MLB
PAGE TITLE
SMC Support
46
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MF
201
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Apple Inc.
R
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
50 OF 109
SHEET
42 OF 75
36
Page 43
www.laptopblue.vn
345678
2 1
D
=PP3V3_S5_LPCPLUS
6 7
=PP5V_S0_LPCPLUS
6 7
LPC_AD<0>
6
16 41 70
BI
LPC_AD<1>
6
16 41 70
BI
SPI_ALT_MOSI
6
43
IN
SPI_ALT_MISO
6
43
OUT
LPC_FRAME_L
6
16 41 70
IN
PM_CLKRUN_L
6
17 41
OUT
SMC_TMS
6
41 42
OUT
LPCPLUS_RESET_L
6
25
IN
SMC_TDO
6
41 42
OUT
SMC_TRST_L
6
41
IN
SMC_MD1
6
41
OUT
SMC_TX_L
6
39 41 42
IN
C
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
31
32
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
33
34
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
6
25 70
IN
6
16 41 70
BI
6
16 41 70
BI
6
19 50
OUT
6
43
IN
6
43
IN
6
16 41
BI
6
17 41
IN
6
41 42
OUT
6
41 42
OUT
6
41 42 53
OUT
6
41
OUT
6
39 41 42
OUT
6
19
OUT
D
C
516S0573
SPI Bus Series Termination
SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
47
5%
PLACE_NEAR=R5125.2:5mm
1/20W
MF
201
SPI_ALT_CS_L
PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
SPI_MLB_CS_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
47
5%
PLACE_NEAR=R5126.2:5mm
1/20W
MF
201
LPCPLUS
1
R5125
47
5%
1/20W
MF
201
2
R5120
1 2
15
5%
PLACE_NEAR=U6100.2:5mm
1/20W
MF
201
LPCPLUS
1
R5127
47
5%
1/16W
MF-LF
402
2
R5122
1 2
1/20W
LPCPLUS
1
R5126
47
5%
1/20W
MF
201
2
47
5%
PLACE_NEAR=R5127.2:5mm
MF
201
R5121
1 2
LPCPLUS
1
R5128
0
5%
1/16W
MF-LF
402
2
SPI_CS0_R_L
16 70
IN
B
16 70
PLACE_NEAR=U1800.W8:5mm
16 70
16 70
IN
IN
OUT
SPI_CLK_R
SPI_MOSI_R
SPI_MISO
PLACE_NEAR=U1800.AD12:5mm
PLACE_NEAR=U1800.AB8:5mm
R5112
15
1 2
5%
1/20W
MF
201
R5111
1 2
1/20W
R5110
15
1 2
15
5%
MF
201
5%
1/20W
MF
201
SPI_CS0_L
70
SPI_CLK
70
SPI_MOSI
70
R5123
1 2
6
43
6
43
6
43
6
43
50 70
OUT
50 70
OUT
50 70
OUT
50 70
IN
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
LPC+SPI Debug Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
51 OF 109
SHEET
43 OF 75
SIZE
A
D
Page 44
www.laptopblue.vn
345678
2 1
PCH SMBus "0" Connections
=PP3V3_S0_SMBUS_PCH
44
7
1
1
Cougar-Point
U1800
(MASTER)
SMBUS_PCH_CLK
70 16 66
D
70 16
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
R5200
R5201
1K
1K
5%
5%
1/20W1/20W
MF
MF
201
201
2
2
LED BACKLIGHT
(WRITE: 0x58 READ: 0x59)
=I2C_BKL_1_SCL
=I2C_BKL_1_SDA
U9701
SMC
U4900
(MASTER)
SMB_0_S0_CLK
41
66
SMB_0_S0_DATA
41
=PP3V3_S0_SMBUS_SMC_0_S0
7
SMC "0" SMBus Connections
1
R5250
4.7K
5%
1/20W
MF
201
73
MAKE_BASE=TRUE
73
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
2
1
R5251
4.7K
5%
1/20W
MF
201
2
Internal DP
J9000
(See Table)
=I2C_TCON_SCL
=I2C_TCON_SDA
SMC
U4900
(MASTER)
63
63
SMB_BSA_CLK
41
SMB_BSA_DATA
41 53
VRef DACs
(Write: 0x98 Read: 0x99)
=I2C_VREFDACS_SCL
31
=I2C_VREFDACS_SDA
31
U3300
Battery
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
SMC "Battery A" SMBus Connections
=PP3V42_G3H_SMBUS_SMC_BSA
7
R5280
SMBUS_SMC_BSA_SCL
73
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
73
2.0K
1/20W
1
1
R5281
2.0K
5%
5%
1/20W
MF
MF
201
201
2
2
Battery Charger
(Write: 0x12 Read: 0x13)
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
ISL6258 - U7000
53
D
Battery
J6955
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
(See Table)
52
6
52
6
Margin Control
U3301
(Write: 0x30 Read: 0x31)
=I2C_PCA9557D_SCL
31
=I2C_PCA9557D_SDA
31
Mikey
U6800
C
XDP Connectors
J2600 & J2650
=SMBUS_XDP_SCL
23
=SMBUS_XDP_SDA
23
(MASTER)
(Write: 0x72 Read: 0x73)
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
40
6
40
6
Internal DP
Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *
Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *
DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N
SMC "A" SMBus Connections
=PP3V3_S3_SMBUS_SMC_A_S3
7
NOTE: SMC RMT bus remains powered and may be active in S3 state
SMC
U4900
(MASTER)
SMB_A_S3_CLK
41
SMB_A_S3_DATA
41
MAKE_BASE=TRUE
MAKE_BASE=TRUE
K21 K78
Samsung LGD Samsung LGD AUO
R5270
1/20W
SMBUS_SMC_A_S3_SCL
73
SMBUS_SMC_A_S3_SDA
73
201
1
1
1K
5%
MF
2
2
(* = Multiple options)
R5271
1K
5%
1/20W
MF
201
=I2C_LIO_SCL
=I2C_LIO_SDA
Left I/O Board
J4700
(See Table)
SMC
U4900
(MASTER)
SMB_MGMT_CLK
41
SMB_MGMT_DATA
41
40
6
40
6
SMC "Management" SMBus Connections
=PP3V3_S3_SMBUS_SMC_MGMT
7
R5290
SMBUS_SMC_MGMT_SCL
73
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
73
MAKE_BASE=TRUE
T29 I2C Connections
2.0K
1/16W
MF-LF
Trackpad
1
1
R5291
2.0K
5%
5%
1/16W
MF-LF
402
402
2
2
=I2C_TPAD_SCL
=I2C_TPAD_SDA
J5700
(Write: 0x90 Read: 0x91)
49
6
49
6
C
T29 & Inlet Temp
EMC1704: U5400
(Write: 0x98 Read: 0x99)
=I2C_T29_INLET_THMSNS_SCL
=I2C_T29_INLET_THMSNS_SDA
46
46
B
A
SMLink 1 is slave port to
access PCH & CPU via PECI.
Left I/O Board
ALS - (write: 0x72 Read: 0x73)
Finstack Temp - (Write: 0x92 Read: 0x93)
T29 IC
U3600
(MASTER)
I2C_T29_SDA
72 34
72 34
For Compliance Testing
SDRVI2C:SB
0
R5236
R5237
1 2
SDRVI2C:SB
0
1 2
MAKE_BASE=TRUE
I2C_T29_SCL
MAKE_BASE=TRUE
70 16
70 16
Cougar-Point
(MASTER)
SML_PCH_0_CLK
MAKE_BASE=TRUE
SML_PCH_0_DATA
MAKE_BASE=TRUE
U1800
PCH "SMLink 0" Connections
=PP3V3_S0_SMBUS_PCH
44
7
R5210
8.2K
1/20W
1
1
R5211
8.2K
5%
5%
1/20W
MF
MF
201
201
2
2
SMC "B" SMBus Connections
=PP3V3_S0_SMBUS_SMC_B_S0
7
PCH "SMLink 1" Connections
1
1
R5260
4.7K
1/20W
Cougar-Point
(Write: 0x88 Read: 0x89)
SML_PCH_1_CLK
70 16
MAKE_BASE=TRUE
SML_PCH_1_DATA
70 16
MAKE_BASE=TRUE
U1800
=PP3V3_S0_SMBUS_PCH
44
7
NO STUFF
R5220
8.2K
1/20W
SMC
U4900
NO STUFF
1
1
R5221
8.2K
5%
5%
1/20W
MF
MF
201
201
2
2
R5223
0
5%
1/20W
MF
201
1 2
1 2
R5222
0
5%
1/20W
MF
201
SMB_B_S0_CLK
41
SMB_B_S0_DATA
41
(MASTER)
SMBUS_SMC_B_S0_SCL
73
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
73
MAKE_BASE=TRUE
8 7 5 4 2 1
R5261
4.7K
5%
5%
1/20W
MFMF
201
201
2
2
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
CPU Temp
EMC1414-A: U5570
(Write: 0x98 Read: 0x99)
47
47
36
7
5%
MF
5%
MF
=PP3V3_S0_T29I2C
1/20W
201
1/20W
201
I2C_DPSDRVA_SCL
MAKE_BASE=TRUE
I2C_DPSDRVA_SDA
MAKE_BASE=TRUE
Microcontroller abstracts
R5230
4.7K 4.7K
1/20W
SDRVI2C:MCU
R5234
1/20W
201
SYNC_MASTER=K78_MLB
PAGE TITLE
1
5%
MF
201
2
SDRVI2C:MCU
1
1
R5235
0
5%
MF
2
2
1
R5231
5%
1/20W
MF
201
2
0
5%
1/20W
MF
201
actual CDR(s) in plug.
SMBus Connections
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
T29 Plug uC
(Write: 0xA0 Read: 0xA1)
=I2C_T29AMCU_SDA
=I2C_T29AMCU_SCL
DP Re-driver
U9310
(Write: 0x94 Read: 0x95)
=I2C_DPSDRVA_SCL
=I2C_DPSDRVA_SDA
U9330
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
52 OF 109
SHEET
44 OF 75
SYNC_DATE=01/10/2011
3.13.0
64
B
64
64
64
A
SIZE
D
Page 45
www.laptopblue.vn
345678
2 1
PBUS Voltage Sense Enable & Filter
Q5300
NTUD3169CZ
SOT-963
N-CHANNEL
D
7
=PBUSVSENS_EN
62
IN
Enables PBUS VSense
divider when in S0.
=PPBUS_S0_VSENSE
R5301
100K
1/20W
201
1
1%
MF
2
G
2
1
G
5
4
P-CHANNEL
PBUSVSENS_EN_L_DIV
6
D
S
D
S
PBUSVSENS_EN_L
3
PBUS_S0_VSENSE
1
R5302
100K
1%
1/20W
Max VOut: 3.3V at 19.77V Input
MF
201
2
R5303
27.4K
PLACE_NEAR=U4900.L8:5MM
R5304
5.49K
1
1%
PLACE_NEAR=U4900.L8:5MM
1/20W
MF
RTHEVENIN = 4573 Ohms
201
2
SMC_PBUS_VSENSE
PLACE_NEAR=U4900.L8:5MM
1
1
C5304
0.22UF
1%
MF
2
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
1/20W
201
41 42 45 46
42
OUT
Sense R is R7510
Sense R is 0.75mOhm
EDP: 33A TDP :28.05A
CPU VCore Load Side Current Sense / Filter
=PP3V3_S0_IMVPISNS
7
PLACE_NEAR=R7510.3:5MM
THRM
V+
V-
9
CRITICAL
U5340
OPA2333
8
DFN
1
4
R5345
487K
1 2
0.1%
SIGNAL_MODEL=EMPTY
1/16W
MF
0402
CPUIMVP_ISUM_IOUT
57 58 74
IN
58 74
IN
CPUIMVP_ISNS1_P
CPUIMVP_ISNS1_N
R5342
4.42K
1 2
R5343
1 2
NOSTUFF
C5344
470PF
X5R-X7R
74
0.1%
1/16W
MF
0402
PLACE_NEAR=R7510.4:5MM
4.42K
74
0.1%
1/16W
MF
0402
1
10%
16V
2
201
CPUIMVP_ISUM_R_P
CPUIMVP_ISUM_R_N
1
R5344
487K
0.1%
1/16W
MF
0402
2
3
2
NOSTUFF
C5345
470PF
1 2
SIGNAL_MODEL=EMPTY
10%
16V
X5R-X7R
201
PLACE_NEAR=U5340.8:3MM
1
C5340
0.1UF
10%
6.3V
2
X5R
201
R5341
4.53K
1 2
1%
1/20W
MF
201
Gain:110.181x
Scale: 12.1A / V
Max VOut: 2.73V at 39.934A
PLACE_NEAR=U4900.M11:5MM
SMC_CPU_ISENSE
PLACE_NEAR=U4900.M11:5MM
1
C5341
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
41 42 45 46
D
42
OUT
GFX/IG VCore Load Side Current Sense / Filter
C
DC-In Voltage Sense Enable & Filter
CRITICAL
THRM
9
U5340
OPA2333
8
DFN
V+
7
V-
R5355
1 2
CPUIMVP_ISUMG_IOUT
4
715K
0.1%
SIGNAL_MODEL=EMPTY
1/16W
MF
402
PLACE_NEAR=U4900.M13:5MM
R5351
4.53K
1 2
1%
1/20W
MF
201
SMC_GFX_ISENSE
PLACE_NEAR=U4900.M13:5MM
1
C5351
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
41 42 45 46
Gain:161.765x
Scale: 8.24A / V
Max VOut: 2.18V at 27.2A
42
OUT
Q5310
NTUD3169CZ
SOT-963
N-CHANNEL
G
=CHGR_ACOK
42 53
IN
Enables DC-In VSense
divider when AC present.
=PPDCIN_S5_VSENSE
7
R5311
100K
1/20W
1
1%
MF
201
2
2
1
G
5
4
P-CHANNEL
PDCINVSENS_EN_L_DIV
B
6
D
S
D
S
DCINVSENS_EN_L
3
DCIN_S5_VSENSE
1
R5312
100K
1%
1/20W
MF
201
2
PLACE_NEAR=U4900.N9:5MM
Max VOut: 3.3V at 19.77V Input
1
R5313
27.4K
1%
PLACE_NEAR=U4900.N9:5MM
1/20W
MF
RTHEVENIN = 4573 Ohms
201
2
SMC_DCIN_VSENSE
PLACE_NEAR=U4900.N9:5MM
1
R5314
5.49K
1/20W
1
C5314
0.22UF
1%
20%
6.3V
MF
2
2
X5R
0201
GND_SMC_AVSS
201
41 42 45 46
42
OUT
CPUIMVP_ISNS1G_P
58 74
IN
CPUIMVP_ISNS1G_N
58 74
IN
Sense R is R7550
Sense R is 0.75mOhm
EDP: 18A TDP: 15.3A
R5352
4.42K
1 2
0.1%
1/16W
MF
0402
R5353
4.42K
1 2
0.1%
1/16W
MF
0402
CPUIMVP_ISUMG_R_P
74
CPUIMVP_ISUMG_R_N
74
NOSTUFF
C5354
470PF
10%
16V
X5R-X7R
201
5
6
1
R5354
1
715K
0.1%
1/16W
MF
2
402
2
NOSTUFF
C5355
470PF
1 2
SIGNAL_MODEL=EMPTY
10%
16V
X5R-X7R
201
C
B
CPU 1.05V VCCIO Current Sense / Filter
CPU Vcore Voltage Sense / Filter
=PPCPUVCORE_S0_VSENSE
7
XW5320
SM
1 2
PLACE_NEAR=R7510.2:5 MM
CPUVSENSE_IN
PLACE_NEAR=U4900.N10:5MM
R5320
4.53K
1 2
1%
1/20W
MF
201
SMC_CPU_VSENSE
PLACE_NEAR=U4900.N10:5MM
1
C5320
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
41 42 45 46
42
OUT
59 74
59 74
Sense R is R7640, 2mOhm
EDP: 8.5A TDP :7.225A
GFX/IG Vcore Voltage Sense / Filter
XW5330
SM
=PPGFXVCORE_S0_VSENSE
A
7
1 2
PLACE_NEAR=R7550.2:5 MM
GFXVSENSE_IN
PLACE_NEAR=U4900.N12:5MM
R5330
4.53K
1 2
1%
1/20W
MF
201
SMC_GFX_VSENSE
PLACE_NEAR=U4900.N12:5MM
1
C5330
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
41 42 45 46
42
OUT
8 7 5 4 2 1
=PP3V3_S0_CPUVCCIOISNS
7
PLACE_NEAR=R7640.4:5MM
CPUVCCIOS0_CS_N
IN
CPUVCCIOS0_CS_P
IN
VCCIOISNS_ENG
5
IN-
4
(200V/V)
3
V+
U5360
INA210
SC70
CRITICAL
GND
2
OUT
VCCIOISNS_ENG
1
C5360
0.1UF
10%
6.3V
2
X5R
201
6
CPUVCCIO_IOUT
1
REFIN+
Gain: 200x
Scale: 2.5A / V
Max VOut: 3.3V at 8.25A
VCCIOISNS_ENG
PLACE_NEAR=U4900.L12:5MM
R5361
4.53K
1 2
1/20W
201
SMC_CPUVCCIO_ISENSE
1%
MF
PLACE_NEAR=U4900.L12:5MM
1
C5361
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
42
OUT
VCCIOISNS_ENG
41 42 45 46
SYNC_MASTER=K78_MLB
PAGE TITLE
SYNC_DATE=01/10/2011
Voltage & Load Side Current Sensing
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
53 OF 109
SHEET
45 OF 75
SIZE
A
D
36
Page 46
46
ISNS_HS_COMPUTING_N
46
IN
74
ISNS_HS_COMPUTING_P
46
IN
74
D
EDP Current: 15.5 A
Max Vdiff: 31 mV
Sense R is R5400, 2mOhm
COMPUTING High Side Current Sense / Filter & T29/Inlet Temp Sensor
C
=PPVIN_S5_HS_COMPUTING_ISNS_R
7
IN
=PPVIN_S5_HS_COMPUTING_ISNS
7
OUT
B
Sense R is R7050, 10mOhm
A
345678
=PP3V3_S3_1V5S3ISNS
3
V+
U5460
INA214
5
SC70
IN-
4
IN+ REF
(100V/V)
GND
2
AirPort Current Sense / Filter
=PP3V3_S3_WLANISNS
AIRPORTISNS_ENG
5
4
IN-
3
V+
U5470
INA210
SC70
(200V/V)
GND
2
HDD Current Sense / Filter
=PP3V3_S0_HDDISNS
HDDISNS_ENG
5
4
IN-
3
V+
U5480
INA211
SC70
(500V/V)
GND
2
OUT
OUT
OUT
6
1
6
1
REFIN+
6
1
REFIN+
1
C5460
0.1UF
10%
6.3V
2
X5R
201
ISNS_1V5S3_IOUT
GAIN: 100X
SCALE: 5A / V
MAX VOUT: 2.4V AT 16.5A
AIRPORTISNS_ENG
1
C5470
0.1UF
10%
6.3V
2
X5R
201
ISNS_P5VWLAN_IOUT
Gain: 200x
Scale: 0.25A / V
MAX VOUT: 3V AT 0.825A
HDDISNS_ENG
1
C5480
0.1UF
10%
6.3V
2
X5R
201
ISNS_P5VHDD_IOUT
GAIN: 500X
SCALE: 0.667A / V
MAX VOUT: 3.3V AT 2.2A
=PP3V3_S0_HS_COMPUTING_ISNS
7
5
IN-
4
IN+ REF
=PP3V3_S0_HS_COMPUTING_ISNS
46
7
CRITICAL
123
R5400
0.002
1%
1W
MF
0612
EDP: 15.5A TDP :13.175A
Sense R is R5400, 2mOhm
U5450
INA214
(100V/V)
47
47
74 47
74 47
74 46
74 46
4
SC70
GND
R5405
3
V+
6
OUT
1
2
INLET_THMSNS_D1_P
INLET_THMSNS_D1_N
=T29THMSNS_D2_P
=T29THMSNS_D2_N
ISNS_HS_COMPUTING_P
ISNS_HS_COMPUTING_N
HS_DUR_SEL
HS_TH_SEL
1
R5406
82
130
5%
1/20W
1%
MF
1/20W
MF
201
2
201
COMPUTING High Side Current Sense / Filter
1
C5450
0.1UF
10%
6.3V
2
X5R
201
ISNS_HS_COMPUTING_IOUT
GAIN: 100X
SCALE: 5A/ V
MAX VOUT: 3.1V at 16.5A
PLACEMENT_NOTEs:
Place close to SMC
(For R and C)
CRITICAL
U5400
EMC1704-2
2
4
5
16
15
13
14
1
2
QFN
DP1
DN1
DP2/DN3
DN2/DP3
SENSE+
SENSE-
DUR_SEL
TH_SEL
GND
8
Write Address: 0x98
Read Address: 0x99
1
VDD
THERM*
ALERT*
SMDATA
ADDR_SEL
THRM_PAD
17
SMCLK
GPIO
R5455
1 2
9
103
11
12
6
7
4.53K
1%
1/20W
1
MF
201
2
C5401
1
0.1UF
10%
16V
X5R-CERM
2
0201
HISIDE_ISENSE_OC
T29THMSNS_ALERT_L
=I2C_T29_INLET_THMSNS_SDA
=I2C_T29_INLET_THMSNS_SCL
HS_ADDR_SEL
R5411
5%
1/20W
MF
201
SMC_HS_COMPUTING_ISENSE
C5455
0.22UF
20%
6.3V
X5R
0201
GND_SMC_AVSS
NOSTUFF
R5408
10K
5%
1/20W
MF
201
HS_GPIO
1
NOSTUFF
R5412
0
2
1/20W
NOSTUFF
1
R5413
0
5%
1/20W
MF
201
2
www.laptopblue.vn
DC-IN (AMON) Current Sense Filter
PLACE_NEAR=U4900.K10:5MM
R5431
4.53K
CHGR_AMON
53
IN
42
OUT
Sense R is R7020, 20mOhm
1 2
1%
1/20W
MF
201
DC-In AMON
46 45 42 41
1
1
R5409
10K
5%
1/20W
MF
201
2
2
44
BI
44
BI
1
0
5%
MF
201
2
ISL6259 Gain: 20x
Scale: 2.5A / V
Max VOut: 1.4V at 8.25A
EDP Current: 3.5A
42
SMC_DCIN_ISENSE
PLACE_NEAR=U4900.K10:5MM
1
C5431
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
42
OUT
46 45 42 41
Sense R is R7350, 2mOhm
74 56
74 56
EDP Current: 12 A
Max Vdiff: 24 mV
Sense R is R4052, 20mOhm
74 37
74 37
EDP Current: 0.750 A
Max Vdiff: 15 mV
Sense R is R4599, 3mOhm
74 38
74 38
EDP Current: 2.36A
Max Vdiff: 7.0 mV
DDR3 1V5R1V35 Current Sense / Filter
7
ISNS_1V5_S3_N
IN
ISNS_1V5_S3_P
IN
7
ISNS_AIRPORT_N
IN
ISNS_AIRPORT_P
IN
7
ISNS_HDD_N
IN
ISNS_HDD_P
IN
CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter
=PP3V3_S3_BMON_ISNS
7
Charger/Load side
CHGR_CSO_R_P BMON_INA_OUT
74 53
IN
CHGR_CSO_R_N
74 53
IN
Battery side
NOTE: Monitoring current from
battery to PBUS (battery discharge)
across R7050
CHGR_BMON
53
IN
From charger
INA (Engineering) Solution
Gain: 50x
Scale: 2A / V
Max VOut: 3.3V at 6.6A
EDP Current: 10A
PLACE_NEAR=R7050.4:5MM
3
V+
CRITICAL
U5420
INA213
5
SC70
IN-
4
For engineering, stuff BMON_ENG
For production, stuff BMON_PROD
BMON:ENG
(50V/V)
GND
OUT
REFIN+
2
BMON:ENG
1
C5420
0.1UF
10%
6.3V
2
X5R
201
6
1
Charger BMON (Production) Solution
ISL6259 Gain: 36x
Scale: 2.78A / V
Max VOut: 3.3V at 9.167A
EDP Current: 310A
BMON:ENG
C5421
0.1UF
10%
6.3V
X5R
201
PLACE_NEAR=U5421.3:5MM
1
2
BMON:ENG
U5421
NC7SB3157P6XG
SC70
B1
1
1
2
GND
0
B0
VER 1
BMON:PROD
R5420
1 2
1/20W
201
SEL
6
5
VCC
43
A
0
5%
MF
SMC_BMON_MUX_SEL
BMON_AMUX_OUT
BMON:ENG
1
R5423
100K
5%
1/20W
MF
201
2
42
IN
PLACE_NEAR=U4900.M9:5MM
R5422
300K
1 2
1%
1/20W
MF
201
SMC_BMON_ISENSE
PLACE_NEAR=U4900.M9:5MM
1
C5422
3300PF
10%
10V
2
X7R
201
GND_SMC_AVSS
42
OUT
46 45 42 41
8 7 5 4 2 1
LCD Backlight Driver Input Current Sense / Filter
=PP3V3_S0_BKLTISNS
7
LCDBKLTISNS_ENG
1
C5490
0.1UF
10%
6.3V
2
X5R
201
6
ISNS_LCDBKLT_IOUT
1
GAIN: 500X
SCALE: 0.2A / V
MAX VOUT: 3.3V AT 0.66A
Sense R is R0910, 10mOhm
IN
IN
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
74
8
74
8
EDP Current: 0.67 A
Max Vdiff: 6.7 mV
LCDBKLTISNS_ENG
5
IN-
4
3
V+
U5490
INA211
SC70
(500V/V)
GND
2
OUT
REFIN+
36
2 1
R5465
4.53K
1 2
1%
1/20W
MF
201
PLACEMENT_NOTEs:
Place close to SMC
(For R and C)
AIRPORTISNS_ENG
R5475
4.53K
1 2
1%
1/20W
MF
201
PLACEMENT_NOTEs:
Place close to SMC
(For R and C)
HDDISNS_ENG
R5485
4.53K
1 2
1%
1/20W
MF
201
PLACEMENT_NOTEs:
Place close to SMC
(For R and C)
LCDBKLTISNS_ENG
R5495
4.53K
1 2
1%
1/20W
MF
201
PLACEMENT_NOTEs:
Place close to SMC
(For R and C)
SYNC_MASTER=K78_MLB
PAGE TITLE
High Side Current Sensing
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SMC_1V5S3_ISENSE
1
C5465
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
SMC_WLAN_ISENSE
AIRPORTISNS_ENG
1
C5475
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
SMC_HDD_ISENSE
HDDISNS_ENG
1
C5485
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
SMC_LCDBKLT_ISENSE
LCDBKLTISNS_ENG
1
C5495
0.22UF
20%
6.3V
2
X5R
0201
GND_SMC_AVSS
46 45 42 41
46 45 42 41
46 45 42 41
46 45 42 41
SYNC_DATE=01/16/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
54 OF 109
SHEET
46 OF 75
D
42
OUT
42
OUT
C
42
OUT
B
42
OUT
A
SIZE
D
Page 47
www.laptopblue.vn
345678
2 1
CPU Proximity Sensor
R5510
47
=PP3V3_S0_CPUTHMSNS
7
D
Detect CPU Die Temperature
Q5510
BC846BMXXH
SOT732-3
Placement note:
Place Q5510 next to DDR/5V/3.3V supply on TOP side
74
9
BI
74
9
BI
3
1
2
Detect DDR/5V/3.3V Proximity Temperature
CPU_THERMD_P
CPU_THERMD_N
CPUTHMSNS_D2_P
74
CPUTHMSNS_D2_N
74
PLACE_NEAR=U5510.2:5mm
PLACE_NEAR=U5510.3:5mm
1 2
5%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U5510.4:5mm
PLACE_NEAR=U5510.5:5mm
PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
1
C5511
2200PF
10%
10V
2
X7R-CERM
0201
C5512
2200PF
10%
10V
X7R-CERM
0201
1
C5510
0.1UF
R5511
1
VDD
U5510
EMC1413
DP1
CRITICAL
DN1
DP2/DN3
DN2/DP3
GND
6
DFN
THERM*/ADDR
ALERT*
SMDATA
SMCLK
THRM_PAD
11
Write Address: 0x98
Read Address: 0x99
2
4
5
1
2
10%
6.3V
2
X5R
201
7
CPUTHMSNS_THM_L
83
CPUTHMSNS_ALERT_L
9
=I2C_CPUTHMSNS_SDA
10
=I2C_CPUTHMSNS_SCL
Placement note:
Place U5510 under CPU
1/20W
10K
1
1
R5512
10K
5%
5%
1/20W
MF
MF
201
201
2
2
44
BI
44
BI
Use GND pin B1 on U3600 for N leg
PART NUMBER
117S0008
117S0008
117S0008
117S0008
Detect T29 Die Temperature
QTY
1
1
1
1
TP_T29_THERM_DP
34
BI
DESCRIPTION
RES,MF,1/20W,100K OHM,5,0201,SMD
RES,MF,1/20W,100K OHM,5,0201,SMD
RES,MF,1/20W,100K OHM,5,0201,SMD
RES,MF,1/20W,100K OHM,5,0201,SMD
PLACE_NEAR=U3600.B1:2mm
T29 Die
T29_THERMD_P
74
MAKE_BASE=TRUE
1 2
XW5520
T29_THERMD_N
74
SM
REFERENCE DES
C5361
C5475
C5485
C5495
PLACE_SIDE=BOTTOM
CRITICAL
NOSTUFF
R5523
10K
1/16W
MF-LF
1
5%
402
2
BOM OPTION
VCCIOISNS_PROD
AIRPORTISNS_PROD
HDDISNS_PROD
LCDBKLTISNS_PROD
D
C
C
Replacing caps with 100K PD on ISENSE SMC inputs
T29,MLB Bottom & Inlet Proximity Sensors
INLET_THMSNS_D1_P
SIGNAL_MODEL=EMPTY
INLET_THMSNS_D1_N
C5523
2200PF
X7R-CERM
0201
1
10%
10V
2
Q5530
BC846BMXXH
SOT732-3
3
1
2
B
=T29THMSNS_D2_P
SIGNAL_MODEL=EMPTY
=T29THMSNS_D2_N
=MLBBOT_THMSNS_D3_N
=MLBBOT_THMSNS_D3_P
C5522
2200PF
X7R-CERM
0201
1
10%
10V
2
Q5520
BC846BMXXH
SOT732-3
Q5540
BC846BMXXH
SOT732-3
3
1
2
3
1
2
46
Placement note:
Place Q5530 between near rear vent on bottom side
46
74 47 46
Placement note:
Place Q5520 close to T29 on TOP side
74 47 46
47
Placement note:
Place Q5540 on MLB bottom side opposite U5400
47
B
74 47 46
A
=T29THMSNS_D2_P
=T29THMSNS_D2_N
T29_MLBBOT_THMSNS_P
MAKE_BASE=TRUE
T29_MLBBOT_THMSNS_N
MAKE_BASE=TRUE
8 7 5 4 2 1
=MLBBOT_THMSNS_D3_P
=MLBBOT_THMSNS_D3_N
47
47 74 47 46
SYNC_MASTER=K78_MLB
PAGE TITLE
Thermal Sensors
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/16/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
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SIZE
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36
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345678
2 1
D
D
FAN CONNECTOR
C
=PP5V_S0_FAN
6 7
=PP3V3_S0_FAN
7
CRITICAL
J5600
FF14A-4C-R11DL-B-3H
NC
NC
F-RT-SM
5
1
5V DC
2
TACH
3
MOTOR CONTROL
4
GND
6
518S0793
47K
1/20W
201
1
5%
MF
2
R5660
R5665
47K
SMC_FAN_0_TACH
41
R5661
100K
5%
1/20W
MF
201
SMC_FAN_0_CTL
B
41
1 2
1/20W
1
1
GS
2
2
5%
MF
201
FAN_RT_TACH
6
Q5660
SSM3K15FV
SOD-VESM-HF
D
FAN_RT_PWM
6
3
C
B
A
SYNC_MASTER=K78_MLB
PAGE TITLE
Fan
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 5 4 2 1
36
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
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PAGE
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Page 49
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345678
2 1
D
=PP3V3_S5_TPAD
49
7
R5730
1
2
0
1 2
MF5%
1/20W
201
PLACE_NEAR=J5700.1:1.5MM
FERR-120-OHM-1.5A
PLACE_NEAR=J5700.10:1.5MM
PLACE_NEAR=J5700.13:1.5MM
VOLTAGE=3.3V
L5720
1 2
0402-LF
7 6
C5720
0.1UF
PP3V3_TPAD_CONN
6
1
C5700
0.1UF
10%
6.3V
2
X5R
201
1
10%
6.3V
2
X5R
201
1
C5701
0.1UF
10%
1
5%
MF
201
2
1
5%
MF
201
2
16V
2
X5R-CERM
0201
USB_TPAD_M_P
USB_TPAD_M_N
R5704
1 2
5% MF
1/20W
201
9
VCC
5
M+
4
M-
U5700
PI3USB102ZLE
TQFN
7
D+
CRITICAL
6
D-
8
GND
3
0
USB_TPAD_MUX_SEL =PP3V42_G3H_TPAD
NOSTUFF
1
C5704
0.1UF
10%
16V
2
X5R-CERM
0201
1
Y+
2
Y-
10
SELOE*
USB_TPAD_P
USB_TPAD_N
SEL=0 Choose pull up/down
SEL=1 Choose USB
R5703
10K
1/20W
24
BI
24
BI
USB_TPAD_HUB_P
USB_TPAD_HUB_N
R5702
10K
1/20W
C
62 41 26 17
PM_SLP_S4_L
IN
FIXME: CHECK SEL
=PP3V3_S5_TPAD
49
7
BI
69 49
69 49
=PP5V_S5_TPAD
7
C5710
0.1uF
20%
10V
CERM
402
PLACE_NEAR=J5700.10:1.5MM
IPD Flex Connector
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm
6
OUT
6
BIBI
6
BI
6
BI
6
BI
6
OUT
6
IN
6
OUT
SMC_PME_S4_WAKE_L
USB_TPAD_CONN_P
USB_TPAD_CONN_N
=I2C_TPAD_SDA
=I2C_TPAD_SCL
SMC_ONOFF_L
SMC_LID
SMC_TPAD_RST_L
VOLTAGE=5V
6
42 41
74 49
74 49
49 44
49 44
PP5V_TPAD_FILT
MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm
49 42 41
49 42 41 40
49 42
CRITICAL
J5700
FF14A-14C-R11DL-B-3H
F-RT-SM
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
518S0794
69 49
69 49
USB_TPAD_P
BI
USB_TPAD_N
BI
PLACE_NEAR=J5700.8:1.5MM
1 2
C5732
100PF
5%
25V
CERM
201
PLACE_NEAR=J5700.9:1.5mm
PLACE_NEAR=J5700.11:1.5MM
L5710
90-OHM
DLP0NS
SYM_VER-1
1
2
1
C5733
100PF
5%
25V
2
CERM
201
PLACE_NEAR=J5700.12:1.5MM
34
1
C5734
100PF
5%
25V
2
C5735
CERM
201
PLACE_NEAR=J5700.14:1.5MM
USB_TPAD_CONN_P
USB_TPAD_CONN_N
=I2C_TPAD_SDA
=I2C_TPAD_SCL
1
100PF
5%
25V
2
C5736
CERM
201
100PF
SMC_ONOFF_L
SMC_LID
SMC_TPAD_RST_L
1
5%
25V
2
CERM
201
74 49
6
BI
74 49
6
BI
49 44
6
49 44
6
49 42 41
6
49 42 41 40
6
49 42
6
D
C
Keyboard Backlight Driver & Detection
=PP5V_S0_KBDLED
7
B
41
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:
If LOW, keyboard backlight present
If HIGH, keyboard backlight not present
R5853 always stuffed, R5854 only
grounded when KB BL flex connected.
BI
BYPASS=U5750.1:2:2 MM
SMC_SYS_KBDLED
KBDLED_FB
KB_BL
C5750
402-1
KB_BL
1
R5755
4.7
5%
1/16W
MF-LF
402
2
1UF
1
10%
10V
2
X5R
NC
3
6
5
EN
FB
NC
GND
U5750
MIC2292
CRITICAL
4
CRITICAL
L5750
10UH-0.58A-0.35OHM
1 2
2
VIN
MLF
SW
OUT
KB_BL
THRM
PAD
8
9
KB_BL
1098AS-SM
7
1
KBDLED_SW
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
KBDLED_ANODE
6 6
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
OMIT_TABLE OMIT_TABLE
C5755
0.33UF
0603
1
1
C5756
10%
50V
X5R
0.33UF
10%
50V
2
2
X5R
0603
Keyboard Backlight Connector
FF14A-4C-R11DL-B-3H
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
NC
NC
KB_BL
CRITICAL
J5715
F-RT-SM
5
1
2
3
4
6
518S0793
J5815 pin 1 is grounded
on keyboard backlight flex
B
C5756 SYMBOL NOT READY FOR 0.22UF
A
PART NUMBER
138S0704
QTY
2
DESCRIPTION
CAP,CER,0.22UF,10%,50V,X5R,0603
8 7 5 4 2 1
REFERENCE DES
C5755,C5756
CRITICAL
BOM OPTION
KB_BL
36
SYNC_MASTER=K78_MLB
PAGE TITLE
IPD / KBD Backlight
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
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2 1
D
C
=PP3V3_S5_ROM
7
1
R6101
3.3K
5%
1/20W
MF
201
2
70 43 70 43
70 43
43 19
6
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.
SPI_MLB_CLK
IN IN
SPI_MLB_CS_L
IN
SPI_WP_L
SPIROM_USE_MLB
IN
C6100
0.1UF
1
10%
16V
2
X5R
402
6
SCK
1
CE*
3
WP*
7
RST*/HOLD*
CRITICAL
VDD
U6100
64MBIT
WSON
SST25VF064C
OMIT_TABLE
VSS
THRM_PAD
984
SI/SIO0
SO/SOI1
5
2
SPI_MLB_MOSI
SPI_MLB_MISO
70 43
OUT
D
C
SIZE
B
A
D
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
SPI ROM
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
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SPEAKER AMPLIFIERS
APN:353S2888
345678
2 1
SPEAKER LOWPASS
D
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM
=PP5V_S3_AUDIO_AMP
7
CRITICAL
C6210
0.1UF
6.3V
1 2
10%
6.3V
X5R
201
10%
X5R
201
R6210
0
1 2
5%
1/20W
MF
201
74 40
6
74 40
6
40
C
6
IN
IN
IN
SPKRAMP_INR_P
SPKRAMP_INR_N
AUD_GPIO_3
1
R6211
100K
5%
1/20W
MF
201
2
CRITICAL
C6211
0.1UF
1 2
R6214
1 2
1/20W
201
R_SPKRAMP_SHDN
80 HZ < FC < 132 HZ
6DBGAIN
0
5%
MF
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
PP5V_S3_U6210
MAX98300_R_P
74
MAX98300_R_N
74
C6207
0.1UF
6.3V
D
1
10%
2
X5R
201
A1
PVDD
U6210
MAX98300
WLP
A3
IN+
B3
IN-
C2
B2
NC
PGND
A2
OUT+
OUT-
GAINSHDN*
NOSTUFF
R6213
100K
1/20W
B1
C1
C3
R_AMP_GAIN
1
5%
MF
201
2
1
2
R6212
100K
5%
1/20W
MF
201
C6201
47UF
20%
6.3V
2
POLY-TANT
2012-LLP
MIN_LINE_WIDTH=0.10 mm
MIN_NECK_WIDTH=0.10 MM
SPKRAMP_R_P_OUT
MIN_LINE_WIDTH=0.10 mm
MIN_NECK_WIDTH=0.10 MM
SPKRAMP_R_N_OUT
74 52
6
74 52
6
C
CRITICAL
1
SIZE
B
A
D
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
AUDI0: SPEAKER AMP
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
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62 OF 109
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2 1
MLB to LIO Power Cable Connector
CRITICAL
J6900
WTB-PWR-M82
M-RT-SM
1
2
3
D
4
5
6
518S0508
C6905
0.01UF
20%
50V
CERM
603
1
2
=PP18V5_DCIN_CONN
=PP5V_S3_LIO_CONN
1
C6906
0.01UF
10%
16V
2
CERM
402
7 6
7 6
PPBUS_G3H
7 6
PPDCIN_G3H_OR_PBUS
53
R6905
1 2
1/8W
MF-LF
10
5%
805
R6920
4.7
1 2
PPBUS_G3H_R
5%
1/8W
MF-LF
805
PPDCIN_G3H_OR_PBUS_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
Debug LEDs
(For development only)
=PP3V3_S3_DBGLEDS
7
C
S3_S0_LED
R6940
1/20W
DBGLED_S3
DBGLED_S0
S3_S0_LED
D6910
GREEN-3.6MCD
2.0X1.25MM-SM
A
K
S3_S0_LED
A
D6920
GREEN-3.6MCD
2.0X1.25MM-SM
K
DBGLED_S0_D
S3_S0_LED
1
1
R6941
1K
1K
5%
5%
1/16W
MF-LF
MF
402201
2
2
S3_S0_LED
Q6940
SSM3K15FV
3
D
SOD-VESM-HF
CRITICAL
D6905
BAT30CWFILM
SOT-323
1
2
3
PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
C6990
2.2UF
X5R-CERM
3.425V "G3Hot" Supply
Supply needs to guarantee 3.31V delivered to SMC VRef generator
6
U6990
LT3470A
DFN
CRITICAL
GND
5
3
BOOST
THRM
PAD
BIAS
9
SW
1
FB
1
25V
2
603
NC
VIN
8 4
SHDN*
7
NC
2
P3V42G3H_BOOST
DIDT=TRUE
1
C6994
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
0.22UF
10%10%
10V
CERM
402
2
33UH-20%-0.39A-0.435OHM
1
C6995
22PF
5%
50V
2
CERM
201
CRITICAL
1 2
P3V42G3H_FB
Vout = 1.25V * (1 + Ra / Rb)
L6995
DP418C-SM
<Ra>
R6995
348K
1/20W
<Rb>
R6996
200K
1/20W
1
1%
MF
201
2
1
2
1
1%
MF
201
2
=PP3V42_G3H_REG
Vout = 3.425V
60MA MAX OUTPUT
(Switcher limit)
CRITICAL
C6999
22UF
20%
6.3V
X5R-CERM-1
603
D
7
C
1
GS
2
62 41 25 23
B
ALL_SYS_PWRGD
IN
Right Speaker Connector
B
CRITICAL
J6903
78171-0002
M-RT-SM
3
K16-Specific
74 51
74 51
6
IN
6
IN
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
Battery Connector
PPVBAT_G3H_CONN
1
CRITICAL
J6950
WTB-PWR-M82
M-RT-SM
1
2
3
4
5
A
6
7
8
9
518S0540
1
C6951
1UF
10%
16V
2
X5R
402
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SYS_DETECT_L
6
C6950
0.1UF
10%
25V
2
X5R
402
R6950
1/20W
10K
1
1
5%
MF
201
2
3
8 7 5 4 2 1
2
53
6
44
6
IN
44
6
BI
CRITICAL
NO STUFF
D6950
RCLAMP2402B
SC-75
36
1
2
4
518S0519
SYNC_MASTER=JACK_K90I
PAGE TITLE
DC-In & Battery Connectors
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=08/20/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
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2 1
PLACE_NEAR=Q7030.5:1.5mm
1
C7037
0.001UF
10%
50V
2
X7R
402
CRITICAL
F7040
8AMP-24V
1 2
1206
PLACE_NEAR=L7030.2:1.5mm
C7045
1000PF
10%
16V
X7R
201
TO/FROM BATTERY
PPVBAT_G3H_CONN
6
52
TO SYSTEM
=PPBUS_G3H
D
C
7
B
2
CRITICAL
345678
33UF-0.06OHM
C7040
62UF
20%
11V
ELEC
CASE-B2
CRITICAL
C7031
POLY-TANT
CASE-D3L
1
2
1
20%
25V
2
CRITICAL
C7041
CASE-B2
62UF
1
C7035
1UF
10%
25V
2
X5R
603-1
1
20%
11V
2
ELEC
CRITICAL
SI7615DN
PWRPK-1212-8
S
1 2 3
CRITICAL
Q7055
G
4
C7043
62UF
CASE-B2
1
C7036
1UF
10%
25V
2
X5R
603-1
1
1
20%
11V
2
2
ELEC
MIN_LINE_WIDTH=0.6 mm
D
MIN_NECK_WIDTH=0.4 mm
5
VOLTAGE=8.4V
www.laptopblue.vn
This node is powered
Reverse-Current Protection
CRITICAL
Q7080
SOT-323
NO STUFF
R7002
100K
1/20W
1
5%
MF
201
SI5419DU
D
3
1
2
POWERPAK
G
5A
5
S
4
CHGR_SGATE_DIV
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm
1
R7081
62K
5%
1/20W
MF
201
2
CHGR_DCIN_D_R
12
13
11
10
4
6
3
5
7
8
18
17
1
C7002
1UF
10%
10V
2
X5R
402
R7001
4.7
1 2
1/16W
MF-LF
402
VDD
VHST
SMB_RST_N
SCL
SDA
VFRQ
CELL
ACIN
ICOMP
VCOMP
VNEG
CSOP
CSON
(AGND)
R7080
100K
5%
1/20W
MF
201
5%
19
20
VDDP
U7000
TQFN
ISL6259HRTZ
20V/V
36V/V
(OD)
THRM_PAD
PGND
22
29
XW7000
SM
1 2
PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm
1
2
R7005
1 2
FIXME: C7001 SAME AS C7000?
PP5V1_CHGR_VDDP
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
CRITICAL
OMIT_TABLE
DCIN
SGATE
AGATE
CSIP
CSIN
BOOT
UGATE
PHASE
LGATE
BGATE
AMON
BMON
ACOK
FROM ADAPTER
=PPDCIN_S5_CHGR
7
D
CRITICAL
D7005
BAT30CWFILM
1
2
ACIN pin threshold is 3.2V, +/- 50mV
DIVIDER SETS ACIN THRESHOLD AT 12.18V
Input impedance of ~40K meets
sparkitecture requirements
1
C
B
R7010
30.1K
1%
1/20W
MF
201
2
1
R7011
10.5K
1%
1/20W
MF
201
2
R7013
1/20W
100
201
SMC_RESET_L
6
41 42 43
IN
Float CELL for 1S
1
1%
MF
1
2
2
1
2
R7015
255K
1%
1/20W
MF
201
CHGR_VCOMP_R
CHGR_VNEG_R
C7016
470PF
10%
16V
X5R-X7R
201
C7015
470PF
X5R-X7R
R7016
220
1/20W
1 2
10%
16V
201
1%
MF
201
R7000
0
5%
1/20W
MF
201
1
2
1
2
30mA max load
PP5V1_CHGR_VDD
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5.1V
=PP3V42_G3H_CHGR
7
CHGR_RST_L
=SMBUS_CHGR_SCL
44
IN
=SMBUS_CHGR_SDA
44
BI
CHGR_VFRQ
62
IN
CHGR_CELL
CHGR_ACIN
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
73
CHGR_CSO_N
73
1
C7050
0.47UF
10%
10V
2
X5R
402
through body diodes:
* DCIN through Q7080.
* PBUS through Q7085,
Charger TOP FETs and
Q7055.
(CHGR_SGATE)
20
(CHGR_DCIN)
5%
1/20W
MF
201
2
26
1
28
73
27
73
25
24
23
21
16
9
15
14
(GND)
(CHGR_CSO_P)
(CHGR_CSO_N)
(PPVBAT_G3H_CHGR_R)
PPDCIN_G3H_OR_PBUS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
1
C7085
0.1UF
10%
25V
2
X5R
402
1
C7001
1UF
10%
10V
2
X5R
402
CHGR_DCIN
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
CHGR_LGATE
CHGR_BGATE
CHGR_AMON
CHGR_BMON
=CHGR_ACOK
1
R7085
470K
2
GATE_NODE=TRUE
GATE_NODE=TRUE
OUT
OUT
OUT
1%
1/20W
MF
201
46
46
42 45
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
Inrush Limiter
CRITICAL
Q7085
SI5419DU
52
1
2
C7020
0.047UF
10%
16V
X7R
402
C7022
0.1UF
POWERPAK
5A
5
S
4
(CHGR_AGATE)
10%
25V
X5R
402
1
2
G
1
2
4
D
1
2
PLACE_NEAR=U7000.25:2mm
C7025
0.22UF
10%
10V
CERM
402
G
1
R7021
1 2
1/20W
R7022
1 2
1/20W
C7021
0.1UF
10%
25V
X5R
402
5
D
S
1 2 3
10
5%
MF
201
10
5%
MF
201
R7051
R7052
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm
4
Q7035
FDMS0349
POWER56
PPDCIN_G3H_INRUSH
CHGR_AGATE_DIV
CHGR_CSI_R_P
74
CHGR_CSI_R_N
74
5
D
G
S
1 2 3
CRITICAL
2.2
1 2
0
1 2
1
R7086
332K
1%
1/20W
MF
201
2
CRITICAL
Q7030
FDMS0355S
POWER56
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
74
5%
5%
4
CRITICAL
R7020
0.020
MF-LF
0612
123
PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
CHGR_CSO_R_P
46
1/20W
MF
CHGR_CSO_R_N
46 74
1/20W
MF
(PPVBAT_G3H_CHGR_R)
0.5%
1W
CRITICAL
33UF-0.06OHM
Max Current = 8A
f = 400 kHz
3
1
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.4V
R7050
0.01
0.5%
1W
MF
0612-3
2 1
4 3
201
201
1
C7030
20%
25V
2
POLY-TANT
CASE-D3L
CRITICAL
L7030
4.7UH-13.1A
FDA1240F-SM
PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.4V
(CHGR_BGATE)
1
C7042
2
0.1UF
10%
6.3V
X5R
201
C7011
0.01UF
10%
10V
X5R
201
1
1
2
C7000
2
1UF
10%
10V
X5R
402-1
C7005
0.22UF
20%
25V
X5R
603
1
2
GND_CHGR_AGND
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
C7026
1000PF
1
10%
16V
2
X7R
201
* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
C7017
10UF
1
1
C7014
10%
25V
X5R
805
1UF
25V
2
2
X5R
603-1
1
C7013
0.1UF
10%10%
25V
2
X5R
402
1
C7012
2
0.01UF
10%
25V
X7R
402
A
SYNC_MASTER=K78_MLB
PAGE TITLE
PBus Supply & Battery Charger
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 5 4 2 1
36
SYNC_DATE=12/03/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
70 OF 109
SHEET
53 OF 75
SIZE
A
D
Page 54
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345678
2 1
D
=PPVIN_S0_VCCSAS0
7
=PP5V_S0_VCCSA
7
1
R7101
2.2
5%
1/16W
MF-LF
402
EN
FB
SREF
VO
OCSET
PGOOD
4
RTN
FSEL
8
SET0
9
SET1
6
VID0
5
VID1
2
19
VCC
U7100
ISL95870AH
CRITICAL
GND
3
XW7100
SM
1 2
PLACE_NEAR=U7100.3:1mm
PP5V_S0_VCCSAS0_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
C
CPU_VCCSASENSE
12
IN
62
IN
VCCSAS0_SREF
1
R7147
113K
1%
1/20W
MF
201
2
1
C7103
0.022UF
10%
16V
2
CERM-X5R
402
1
C7105
47PF
5%
25V
2
NP0-C0G
201
B
1
R7148
140K
1%
1/20W
MF
201
2
1
R7149
47.5K
1%
1/20W
MF
201
2
1
2
62
XW7101
C7102
2.2UF
10%
16V
X5R
603
12
IN
OUT
=PVCCSA_EN
VCCSAS0_VO
VCCSAS0_OCSET
PVCCSA_PGOOD
VCCSAS0_RTN
2
SM
R7103
1
0
5%
1/20W
MF
201
PLACE_NEAR=C1763.2:3mm
CPU_VCCSA_VID<1>
VCCSAS0_AGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
VCCSAS0_FSEL
VCCSAS0_SET0
VCCSAS0_SET1
1
2
10
7
12
11
14
13
UTQFN
PVCC
PGND
1
C7101
2
20
BOOT
UGATE
PHASE
LGATE
2
10UF
20%
10V
X5R
603
CRITICAL
1815
17
16
1
VCCSAS0_BOOT_RC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
VCCSAS0_VBST
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
VCCSAS0_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
VCCSAS0_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
VCCSAS0_DRVL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
(VCCSAS0_OCSET)
(VCCSAS0_VO)
R7130
1/10W
MF-LF
CRITICAL
C7119
1
C7130
1
0.22UF
0
5%
603
10%
10V
2
CERM
402
2
2 3 7
1
10UF
X5R-CERM
0805
CRITICAL
Q7100
SIZ710DT
POWERPAK-6X3.7
8
CRITICAL
1
10%
16V
2
1
C7120
10UF
10%
16V
2
X5R-CERM
0805
CRITICAL
L7100
1.0UH-7.7A
1 2
FDV0630H-SM
6
4 5
1
R7141
1K
1%
1/20W
MF
C7140
201
2
1000PF
12
5%
25V
NP0-C0G
402
PLACE_NEAR=Q7100.2:1.5mm
1
C7121
0.1UF
10%
16V
2
X7R-CERM
402
PPVCCSA_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
VCCSAS0_CS_P
74
VCCSAS0_CS_N
74
1
R7142
1K
1%
1/20W
MF
201
2
C7122
1000PF
NP0-C0G
1
5%
25V
2
402
C7123
62UF
CASE-B2
CRITICAL
R7140
0.001
MF-1
0612
1 2
3 4
1
20%
11V
2
ELEC
1%
1W
CRITICAL
OCP = R7141 x 8.5uA / R7140
OCP = 8.5A
1
2
C7141
270UF
20%
2V
TANT
CASE-B2-SM
=PPVCCSA_S0_REG
6A Max Output
f = 300 kHz
7
D
C
B
VID1 VID0 Voltage
0 0 0.9V
1 0 0.8V
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
System Agent Supply
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/16/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
71 OF 109
SHEET
54 OF 75
SIZE
A
D
Page 55
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345678
2 1
D
=PPVIN_S5_P5VP3V3
7
62UF
CASE-B2
CRITICAL
1
C7240
20%
11V
ELEC
62UF
2
CASE-B2
CRITICAL
C7242
F=400KHZ
=PP5V_S3_REG
55
62UF
1
20%
6.3V
2
ELEC
7
PLACE_NEAR=L7220.1:3mm
CRITICAL
1
C7252
150UF
20%
6.3V
2
POLY-TANT
CASE-B2-SM
CRITICAL
1
C7253
150UF
20%
6.3V
2
POLY-TANT
CASE-B2-SM
PLACE_NEAR=L7220.1.2:1.5mm
1
2
C7250
10UF
20%
10V
X5R
603
C7271
1000PF
10%
16V
X7R
201
P5VS3_VFB1-R
1.5UH-20%-18A-15MOHM
1
2
PLACE_NEAR=L7220.1:3mm
2
XW7222
SM
1
1
R7220
41.2K
1%
1/20W
MF
201
2
1
R7221
10K
1%
1/20W
MF
201
2
C
Vout = 5.0V
7.2A MAX OUTPUT 6.5A MAX OUTPUT
CRITICAL
C7254
CASE-B2S
B
PLACE_NEAR=Q7220.5.2:1.5mm
1
1
C7270
20%
11V
ELEC
1000PF
2
2
CRITICAL
L7220
1 2
PCMC063T-SM
152S1424
2
XW7220
SM SM
1
10%
16V
X7R
201
1
C7241
1UF
10%
16V
2
X5R
402
CRITICAL
Q7220
RJK03E0DNS
HWSON-8
PLACE_NEAR=L7220.2:3mm
2
XW7221
CRITICAL
1
Q7225
RJK03E0DNS
HWSON-8
P5VS3_CSP1_R
=PP5V_S5_LDO
7
=PP5V_S3_REG
55
7
1
C7200
1UF
10%
16V
2
X5R
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
P5VS3_PGOOD
P3V3S5_PGOOD
NO STUFF
R7248
1 2
5%0201MF1/20W
NO STUFF
1
R7237
20K
1%
1/20W
MF
201
2
C7237
270PF
X7R-CERM
0201
402
GATE_NODE=TRUE
SWITCH_NODE=TRUE
GATE_NODE=TRUE
1
10%
16V
2
P5VS3_VBST
P5VS3_DRVH
P5VS3_LL
P5VS3_DRVL
P5VS3_CSP1
P5VS3_CSN1
P5VS3_FUNC
P5VS3_VFB1
P5VS3_COMP1
P5VS3_EN_R
1
R7249
0
5%
1/20W
MF
201
2
GND_P5VP3V3_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
4
4
R7256
4.22K
1/20W
P5VS3_VBST_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
C7224
0.1UF
10%
25V
2
X5R
402
1
1%
MF
201
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
C7218
0.1UF
1 2
10%
16V
X5R
402
R7247
1.33K
1 2
1%
1/20W
MF
201
R7245
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
55
P5VS3_COMP1_R
55
1
0
5%
2
P5VP3V3_VREG3
C7236
4700PF
10%
10V
X7R
201
P5VP3V3_VREF2
1
R7236
7.5K
1%
1/20W
MF
201
2
1
2
62
OUT
62
OUT
5
D
G
S
123
5
D
G
S
123
1
2
=P5VS3_EN
62 62
IN IN
2
23
VIN
V5SW
6
SKIPSEL1
19
SKIPSEL2
14
OCSEL
31
1
32
30
DRVL1
7
CSP1
8
11
MODE
9
VFB1 VFB2
10
4
5
CRITICAL
GND
28
1 2
PLACE_NEAR=U7201.28:1mm
PLACE_NEAR=U7201.4:2mm
R7251
0
5%
1/20W
MF
201
29
VREG5
U7201
QFN
TPS51980
XW7200
SM
THRM_PAD
22
VREG3
33
55
55
13
VREF2
EN
VBST2VBST1
DRVH2DRVH1
SW2SW1
DRVL2
CSP2
CSN2CSN1
RF
COMP2COMP1
EN2EN1
PGOOD2PGOOD1
353S2678
=P3V3S5_EN
P5VP3V3_VREG3
P5VP3V3_VREF2
12
26
24
25
27
18
17
3
16
15
21
20
C7201
0.22UF
10%
10V
CERM
402
=P5V3V3_REG_EN
P3V3S5_RF
P3V3S5_EN_R
1
2
P3V3S5_VBST
P3V3S5_DRVH
GATE_NODE=TRUE
P3V3S5_LL
SWITCH_NODE=TRUE
P3V3S5_DRVL
GATE_NODE=TRUE
P3V3S5_CSP2
P3V3S5_CSN2
1
R7206
249K
1%
1/20W
MF
201
2
C7238
4700PF
55
PLACE_NEAR=U7201.21:2mm
1
R7252
0
5%
1/20W
MF
201
2
C7203
1UF
10%
6.3V
CERM
402
62
IN
P3V3S5_VFB2
P3V3S5_COMP2
1
R7238
2
P3V3S5_COMP2_R
1
10%
10V
2
X7R
201
P5VP3V3_VREF2
7.5K
1
1
C7205
10UF
P3V3S5_VBST_R
20%
MIN_LINE_WIDTH=0.6 mm
10V
2
1
R7239
20K
2
C7239
X5R
0603
NO STUFF
1%
1/20W
MF
201
220PF
X7R-CERM
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
2
R7264
0
5%
1/16W
MF-LF
402
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
1
10%
25V
2
201
C7264
0.1UF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
C7288
0.1UF
1 2
10%
16V
X5R
402
R7246
1.54K
1 2
1%
1/20W
MF
201
10%
25V
X5R
402
1
2
1
2
R7216
4.42K
1%
1/20W
MF
201
2 3 7
1
6
4 5
P3V3S5_CSP2_R
2
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
1%
1/20W
MF
201
CRITICAL
C7284
CRITICAL
Q7260
SIZ710DT
POWERPAK-6X3.7
8
62UF
CASE-B2
20%
11V
ELEC
CRITICAL
1
C7282
62UF
2
CASE-B2
XW7260
PLACE_NEAR=L7260.1:3mm
1
20%
11V
2
ELEC
2
SM
1
1
C7281
1UF
10%
16V
2
X5R
402
CRITICAL
L7260
2.5UH-14A
1 2
PCMC063T-SM
XW7261
PLACE_NEAR=L7260.2:3mm
SM
XW7262
2
1
SM
PLACE_NEAR=Q7260.2:1.5mm
1
C7283
1000PF
10%
16V
2
X7R
201
=PP3V3_S5_REG
Vout = 3.3V
F=400KHZ
1
C7290
10UF
20%
10V
2
X5R
603
2
1
PLACE_NEAR=L7260.2:3mm
P3V3S5_VFB2_R
1
R7260
23.2K
1%
1/20W
MF
201
2
1
R7261
10K
1%
1/20W
MF
201
2
CRITICAL
150UF-0.018OHM-1.8A
1
C7292
20%
6.3V
2
TANT
CASE-B2-SM
PLACE_NEAR=L7260.2:1.5mm
1
2
7
C7272
1000PF
10%
16V
X7R
201
D
C
B
A
SYNC_MASTER=K78_MLB
PAGE TITLE
5V / 3.3V Power Supply
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 5 4 2 1
36
SYNC_DATE=01/16/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
72 OF 109
SHEET
55 OF 75
SIZE
A
D
Page 56
www.laptopblue.vn
345678
2 1
D
=PPVIN_S3_DDRREG
7
CRITICAL
1
C7330
62UF
20%
11V
2
ELEC
OUT
XW7360
1 2
PLACE_NEAR=C7361.1:3mm
CRITICAL
PLACE_NEAR=C3101.1:1mm
402
8
SM
C7360
CASE-B2
R7325
5%
1 2
10UF
20%
6.3V
X5R
603
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
MF-LF
1/16W
0
CRITICAL
1
1
C7361
10UF
20%
6.3V
2
2
X5R
603
PLACE_NEAR=C3101.1:3mm
=PPVIN_S0_DDRREG_LDO
7
=PP5V_S3_DDRREG
7
1
C7300
10UF
20%
10V
2
X5R
603
PLACE_NEAR=U7300.12:1mm
C
=DDRVTT_EN
26
8
IN
=DDRREG_EN
62
IN
DDRREG_1V8_VREF
1
1
C7315
0.1UF
10%
16V
2
X5R
402
PLACE_NEAR=U7300.6:1mm
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
B
VOLTAGE=0V
R7315
20K
1%
1/20W
MF
201
2
PLACE_NEAR=U7300.8:5mm
1
R7316
100K
1%
1/20W
MF
201
2
PLACE_NEAR=U7300.8:5mm PLACE_NEAR=U7300.8:1mm
1
2
C7316
0.01UF
10%
16V
CERM
402
1
R7317
200K
1%
1/20W
MF
201
2
PLACE_NEAR=U7300.19:3mm
VDDQ/VTTREF Enable
31
PLACE_NEAR=U7300.18:3mm
VTT Enable
DDRREG_FB
DDRREG_MODE
DDRREG_TRIP
1
R7318
68K
1%
1/20W
MF
201
2
1
C7301
10UF
20%
10V
2
X5R
603
PLACE_NEAR=U7300.2:1mm
2
VLDOIN
12 15
V5IN
PGND
U7300
TPS51916
CRITICAL
GND
7
10
17
S3
16
S5
6
VREF
8
REFIN
19
MODE
18
TRIP
VBST
DRVH
DRVL
PGOOD
VDDQSNS
VTTSNS
SW
VTT
QFN
VTTREF
THRM
VTT
PADGND
4
21
XW7300
14
13
11
20
9
3
1
31
5
SM
PLACE_NEAR=U7300.21:1mm
DDRREG_DRVH
GATE_NODE=TRUE
DDRREG_LL
SWITCH_NODE=TRUE
DDRREG_DRVL
GATE_NODE=TRUE
DDRREG_PGOOD
DDRREG_VDDQSNS
=PPVTT_S0_DDR_LDO
7
DDRREG_VTTSNS
=PPVTT_S3_DDR_BUF
7
10mA max load
2
1
C7350
0.22UF
10%
10V
CERM
402
DDRREG_VBST
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
1
2
C7360, C7361 close to memory
DDRREG_VBST_RC
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
CRITICAL
1
C7331
62UF
20%
11V
2
ELEC
CASE-B2
C7325
0.1UF
1 2
10%
25V
X5R
402
(DDRREG_LL)
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
(DDRREG_DRVL)
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
1
C7332
1UF
10%
25V
2
X5R
603-1
(DDRREG_DRVH)
1
2
C7333
0.001UF
10%
50V
X7R
402
CRITICAL
1
C7334
62UF
20%
11V
2
ELEC
CASE-B2
5
D
CRITICAL
S
1 2 3
D
S
Q7330
IRFHM831PBF
PQFN3.3X3.3
CRITICAL
L7330
0.88UH-20%-19A-2.3MOHM
1 2
MPCG1040LR88-SM
74 46
CRITICAL
Q7335
IRFHM830DPBF
PQFN3.3X3.3
46
74
OUT
OUT
PPDDR_S3_REG_R
ISNS_1V5_S3_P
ISNS_1V5_S3_N
CRITICAL
R7350
0.002
MF-LF
1/4W
1206
1%
1 2
3 4
1
2
CRITICAL
C7340
330UF
20%
2.0V
POLY-TANT
B2-SM
CRITICAL
C7341
330UF
POLY-TANT
=PPDDR_S3_REG
1
C7346
0.001UF
10%
50V
2
X7R
1
2
C7345
20%
10UF
6.3V
X5R
603
402
2
XW7301
SM
1
PLACE_NEAR=C7340.1:1mm
1
20%
2.0V
2
B2-SM
7
Vout = 1.5V
14.1A max output
(Q7335 limit)
f = 400 kHz
G
4
5
G
4
1 2 3
D
C
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
1.5V DDR3 Supply
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
SHEET
SYNC_DATE=01/10/2011
3.13.0
73 OF 109
56 OF 75
SIZE
A
D
Page 57
www.laptopblue.vn
345678
2 1
=PP5V_S0_CPUIMVP
D
R7401
10
31
39
5
19
10
1
16
18
17
33
34
32
29
30
1 2
5%
1/16W
MF-LF
402
402415
VCC
U7400
MAX15092GTL
QFN
DRVPWMA
CRITICAL
CSPA3
VRHOT*
POKA
POKB
EN
VDIO
CLK
ALERT*
THERMA
THERMB
SR
IMAXA
IMAXB
GNDSB
GNDSA
3
7
VDDA
VDDB
BSTA1
CSPA1
CSPAAVE
CSNA
CSPA2
BSTA2
DHA2
LXA2
DLA2
BSTB
CSPB1
CSNB
THRM
41
TON
DHA1
LXA1
DLA1
FBA
DHB
LXB
DLB
FBB
PAD
XW7400
2
CPUIMVP_TON
20
CPUIMVP_BOOT1
22
CPUIMVP_UGATE1_R
21
CPUIMVP_PHASE1
23
CPUIMVP_LGATE1
36
CPUIMVP_ISUM1_P
35
CPUIMVP_ISUM
37
CPUIMVP_ISUM_N
4
CPUIMVP_FBA
38
28
NC
26
NC
27
NC
25
NC
11
CPUIMVP_BOOT1G
13
CPUIMVP_UGATE1G
12
CPUIMVP_PHASE1G
14
CPUIMVP_LGATE1G
8
CPUIMVP_ISUMG_P
9
CPUIMVP_ISUMG_N
6
CPUIMVP_FBB
SM
12
1
C7402
2.2UF
20%
10V
2
X5R-CERM
402
PLACE_NEAR=U7400.24:2mm
PLACE_NEAR=U7400.15:2mm
1
2
NO STUFF
C7418
100PF
5%
25V
CERM
201
1
2
NO STUFF
C7419
100PF
5%
25V
CERM
201
1
2
OUT
OUT
OUT
57
OUT
OUT
OUT
OUT
57
C7403
2.2UF
20%
10V
X5R-CERM
402
58
58
58
R7402
90.9K
1 2
1%
1/16W
MF-LF
402
5%
58
58
58
58
NO STUFF
1
C7414
100PF
5%
25V
2
CERM
201
R7403
1 2
1/16WMF-LF
P5V_S0_CPUIMVP_VDD
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
=PPVCCIO_S0_CPUIMVP
7
R7479
54.9
1/20W
PLACE_NEAR=U7400.18:2mm
1
1
R7480
130
1%
1%
1/20W
MF
MF
201
201
2
2
PLACE_NEAR=U7400.16:2mm
C7401
2.2UF
X5R-CERM
1
20%
10V
2
402
NC
67 42 10
C
62
IN
67 12
IN
67 12
IN
67 12
IN
CPU_PROCHOT_L
OUT
CPUIMVP_VR_ON
CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L
CPUIMVP_PGOOD
25
OUT
CPUIMVP_AXG_PGOOD
62
OUT
CPUIMVP_NTC
CPUIMVP_NTCG
CPUIMVP_SLEW
CPUIMVP_IMAXA
1
R7468
5.76K
1%
1/20W
MF
201
2
0603
1
2
CRITICAL
100KOHM-1%-100MW
R7469
B
1
R7466
5.76K
1%
1/20W
MF
201
2
1
CRITICAL
R7467
100KOHM-1%-100MW
0603
2
NO STUFF
1
R7464
200K
1%
1/20W
MF
201
2
1
R7465
10K
1%
1/20W
MF
201
2
1
R7462
215K
1%
1/20W
MF
201
2
1
R7463
137K
1%
1/20W
MF
201
2
1
R7460
215K
1%
1/20W
MF
201
2
1
R7461
137K
1%
1/20W
MF
201
2
CPUIMVP_IMAXB
NO STUFF
1
C7444
47PF
5%
25V
2
NP0-C0G
201
7
=PPVIN_S0_CPUIMVP
2.2
CPUIMVP_UGATE1
402
NO STUFF
1
C7415
100PF
5%
25V
2
CERM
201
1
C7404
2200PF
10%
10V
2
X7R-CERM
0201
D
58
7
R7406
CPUIMVP_ISNS1_P
300
1 2
5%
1/20W
MF
201
58
OUT
OUT
NO STUFF
C7408
0.039UF
58
OUT
1 2
10%
10V
X5R-CERM
0402
58
C7409
470PF
1 2
5%
50V
NP0-C0G
402
CPUIMVP_ISUM_R
R7410
1 2
1
C7407
0.0022UF
10%
50V
2
CERM
402
1/20W
1
5%
MF
201
74 58
OUT
74 58
OUT
74 58 45
IN
C
B
GND_CPUIMVP_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
A
8 7 5 4 2 1
1
2
1
C7441
1000PF
10%
16V
2
X7R
201
CPU_VCCSENSE_R
C7440
1000PF
10%
16V
X7R
201
CPU_AXG_SENSE_R
VOLTAGE=0V
VOLTAGE=0V
NO STUFF
1
C7442
0.01UF
10%
10V
2
X5R
201
NO STUFF
1
C7443
0.01UF
10%
10V
2
X5R
201
R7440
10
1 2
5%
1/20W
MF
201
R7441
10
1 2
5%
1/20W
MF
201
CPU_AXG_SENSE_N
CPU_VCCSENSE_N
1
C7412
1000PF
10%
12
67
IN
CPUIMVP_FBA
57
67
12
IN
CPUIMVP_FBB
57
R7412
6.34K
1 2
1%
1/20W
MF
201
R7422
8.25K
1 2
1%
1/20W
MF
201
16V
2
X7R
201
CPUIMVP_FBA_R
C7422
1000PF
10%
16V
X7R
201
CPUIMVP_FBB_R
SYNC_MASTER=K78_MLB
PAGE TITLE
R7413
10
1 2
5%
1/20W
MF
201
1
2
R7423
10
1 2
5%
1/20W
MF
201
CPU IMVP7 & AXG VCore Regulator
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CPU_VCCSENSE_P
CPU_AXG_SENSE_P
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
74 OF 109
SHEET
57 OF 75
67 12
IN
67 12
IN
SYNC_DATE=01/10/2011
SIZE
A
D
36
Page 58
www.laptopblue.vn
CPU=Sandy Bridge ULV, AXG=GT2
345678
2 1
D
=PPVIN_S0_CPUIMVP
57
7
CPUIMVP_BOOT1_RC
MIN_LINE_WIDTH=0.25 MM
PHASE 1
CPUIMVP_BOOT1
57
IN
MIN_LINE_WIDTH=0.7 MM
CPUIMVP_UGATE1
57
IN
MIN_LINE_WIDTH=0.7 MM
MIN_NECK_WIDTH=0.2 MM
C
57
DIDT=TRUE
GATE_NODE=TRUE
IN
57
IN
MIN_LINE_WIDTH=0.7 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_PHASE1
CPUIMVP_LGATE1
MIN_LINE_WIDTH=0.7 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
R7511
1/16W
MF-LF
DIDT=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
1
0
5%
402
2
1
C7511
0.22UF
10%
10V
2
CERM
402
376S0984
3
376S0985
CRITICAL
Q7510
IRF6811STRPBF
SQ
D
G
S
1 2 6 7
G
5
1
2
5
64
CRITICAL
D
Q7520
IRF6894MTRPBF
DIRECTFET-MX
S
1
2
CRITICAL
C7513
62UF
20%
11V
ELEC
CASE-B2
1
C7514
62UF
2
CRITICAL
20%
11V
ELEC
CASE-B2
1
2
CRITICAL
C7515
10UF
20%
25V
X5R-CERM
0603
1
2
CRITICAL
C7516
10UF
20%
25V
X5R-CERM
0603
0.36UH-20%-30A-1.2MOHM
3 4
THESE TWO CAPS ARE FOR EMC
1
C7517
1UF
10%
16V
2
X5R
402
CRITICAL
L7510
1 2
PIMB104T-SM
152S1323
1
C7518
0.001UF
10%
50V
2
X7R
402
PPVCORE_S0_CPU_PH1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
1
2
C7519
0.001UF
10%
50V
X7R
402
CRITICAL
1
C7540
62UF 62UF
20%
11V
2
ELEC
CASE-B2
CRITICAL
R7510
0.00075
0612
1 2
3 4
1
R7513
46.4
1%
1/20W
MF
201
2
CRITICAL
1
C7541
20%
11V
2
ELEC
CASE-B2
1%
1W
MF
CPUIMVP_ISNS1_N
74 45
1
R7514
10
1%
1/20W
MF
201
2
CRITICAL
1
C7510
62UF
20%
11V
2
ELEC
CASE-B2
=PPVCORE_S0_CPU_REG
CPUIMVP_ISNS1_P
NO STUFF
1
C7571
2200PF
10%
10V
2
X7R-CERM
0201
CRITICAL
1
C7520
62UF
20%
11V
2
ELEC
CASE-B2
CPUIMVP_ISUM_N
CPUIMVP_ISUM1_P
7
74 57 45
OUT
57
IN
57
IN
D
C
SIZE
B
A
D
B
=PPVIN_S0_CPUAXG
7
CPUIMVP_UGATE1G_R
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.5 MM
AXG PHASE
R7551
CPUIMVP_BOOT1G
57
IN
MIN_LINE_WIDTH=0.7 MM
57
57
DIDT=TRUE
GATE_NODE=TRUE
IN
IN
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_PHASE1G
MIN_LINE_WIDTH=0.7 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE1G
MIN_LINE_WIDTH=0.7 MM
MIN_NECK_WIDTH=0.2 MM
A
MIN_LINE_WIDTH=0.7 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_UGATE1G
57
IN
DIDT=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
CPUIMVP_BOOT1G_RC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
DIDT=TRUE
1
10
5%
1/16W
MF-LF
402
2
R7555
4.7
1 2
5%
1/16W
MF-LF
402
DIDT=TRUE
GATE_NODE=TRUE
C7551
0.22UF
376S0906
CRITICAL
Q7550
CSD58864Q5D
VIN
SON5X6
TG
3
1
10%
10V
2
CERM
402
TGR
4
BG
5
1
VSW
6
7
8
PGND
9
1
C7553
62UF
20%
11V
2
ELEC
CASE-B2
CPUIMVP_VSWG
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
DIDT=TRUE
CRITICAL
CRITICAL
1
C7554
62UF
20%
11V
2
ELEC
CASE-B2
0.36UH-20%-30A-1.2MOHM
NOSTUFF
1
R7552
2.2
5%
1/10W
MF-LF
603
2
CPUIMVP_AXG_SNUB
NOSTUFF
1
C7552
0.001UF
10%
50V
2
CERM
402
CRITICAL
1
C7555
10UF
20%
25V
2
X5R-CERM
0603
DIDT=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V
CRITICAL
1
C7556
10UF
20%
25V
2
X5R-CERM
0603
CRITICAL
L7550
1 2
PIMB104T-SM
152S1323
8 7 5 4 2 1
THESE TWO CAPS ARE FOR EMC
1
2
1
10%
16V
X5R
402
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
C7558
2
C7557
1UF
PPVCORE_S0_AXG_R
1
0.001UF
10%
50V
X7R
402
C7559
0.001UF
10%
50V
2
X7R
402
CPUIMVP_ISNS1G_P
74 45 74 45
1
2
C7560
62UF
20%
11V
ELEC
CASE-B2
R7553
CRITICAL
46.4
1/20W
201
R7550
0.00075
1 2
3 4
1
1%
MF
2
CRITICAL
1
C7561
62UF
20%
11V
2
ELEC
CASE-B2
CRITICAL
1%
1W
MF
0612
CPUIMVP_ISNS1G_N
1
R7554
10
1%
1/20W
MF
201
2
=PPVCORE_S0_AXG_REG
CPUIMVP_ISUMG_N
NO STUFF
1
C7574
1000PF
10%
16V
2
X7R
201
CPUIMVP_ISUMG_P
7
SYNC_MASTER=K78_MLB
PAGE TITLE
74 57
IN
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
74 57
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CPU IMVP7 & AXG VCore Output
Apple Inc.
R
DRAWING NUMBER
051-8870
REVISION
BRANCH
PAGE
SHEET
SYNC_DATE=12/07/2010
3.13.0
75 OF 109
58 OF 75
36
Page 59
www.laptopblue.vn
345678
2 1
D
D
CPU VCCIO (1.05V S0) Regulator
=PPVIN_S0_CPUVCCIOS0
7
=PP5V_S0_CPUVCCIOS0
7
CRITICAL
UTQFN
PVCC
PGND
1
2
14
BOOT
UGATE
PHASE
LGATE
16
1
R7601
2.2
5%
1/20W
MF
3
EN
6
FB
4
SREF
8
VO
7
OCSET
9
PGOOD
2
RTN
5
FSEL
201
2
13
VCC
U7600
ISL95870
CRITICAL
GND
1
XW7600
SM
1 2
PLACE_NEAR=U7600.1:1mm
C
IN
OUT
2.2UF
1
10%
16V
2
X5R
603
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
PP5V_S0_CPUVCCIOS0_VCC
=CPUVCCIOS0_EN
CPUVCCIOS0_FB
CPUVCCIOS0_SREF
CPUVCCIOS0_VO
CPUVCCIOS0_OCSET
CPUVCCIOS0_PGOOD
CPUVCCIOS0_RTN
CPUVCCIOS0_FSEL
1
R7603
0
5%
1/20W
MF
201
2
CPUVCCIOS0_AGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
CPU_VCCIOSENSE_P
67 12
CPU_VCCIOSENSE_N
67 12
1
1/20W
1/20W
1
R7644
3.01K
1%
1%
1/20W
MF
MF
201
201
2
2
<Ra>
1
1
R7645
2.74K
1%
1%
1/20W
MF
MF
201
201
2
2
<Rb>
1
C7604
47PF
NP0-C0G
1
C7605
5%
25V
201
47PF
5%
25V
2
2
NP0-C0G
201
1
C7603
0.047UF
10%
16V
2
X7R
402
62
62
C7602
R7604
3.01K
R7605
2.74K
B
C7601
10UF
20%
10V
X5R
603
12
11
10
15
CPUVCCIOS0_BOOT_RC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
CPUVCCIOS0_VBST
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
CPUVCCIOS0_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
CPUVCCIOS0_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
CPUVCCIOS0_DRVL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
(CPUVCCIOS0_OCSET)
(CPUVCCIOS0_VO)
R7630
0
5%
1/10W
MF-LF
603
1 2
1UF
10%
16V
2
X5R
402
2
R7631
0
CPUVCCIOS0_R
5%
1/16W
MF-LF
402
OCP = R7641 x 8.5uA / R7640
OCP = 25.6A
Vout = 0.5V * (1 + Ra / Rb)
1
C7630
1
CSD58864Q5D
TG
3
TGR
4
BG
5
Q7630
SON5X6
CRITICAL
C7620
PGND
9
62UF
CASE-B2
VIN
VSW
20%
11V
ELEC
1
2
1
6
7
8
R7641
3.01K
1/20W
CRITICAL
1
C7621
62UF
20%
11V
2
ELEC
CASE-B2
0.68UH-22A-2.7MOHM
PPCPUVCCIO_S0_REG
1
1%
MF
C7640
201
2
1000PF
12
5%
25V
NP0-C0G
402
1
C7622
1000PF
5%
25V
2
NP0-C0G
402
PLACE_NEAR=Q7630.1:1.5mm
L7630
1 2
PIMB104T-SM
CRITICAL
CPUVCCIOS0_CS_P
74 45
CPUVCCIOS0_CS_N
74 45
1
R7642
3.01K
1%
1/20W
MF
201
2
CRITICAL
1
C7619
62UF
20%
11V
2
ELEC
CASE-B2
PPCPUVCCIO_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
CRITICAL
R7640
0.001
1%
1W
MF
0612
12
34
PLACE_NEAR=L7630.2:1.5mm
C7623
1000PF
NP0-C0G
C
=PPCPUVCCIO_S0_REG
270UF
1
20%
2V
2
TANT
Vout = 1.05V
21A Max Output
f = 300 kHz
CRITICAL
C7649
1
5%
25V
2
402
1
2
CRITICAL
C7648
270UF
20%
2V
TANT
CASE-B2-SM
CASE-B2-SM
7
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
CPU VCCIO (1.05V) Power Supply
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
76 OF 109
SHEET
59 OF 75
SIZE
A
D
Page 60
www.laptopblue.vn
345678
2 1
1.05V SUS LDO
D
=PP3V3_S0_P1V8S0
7
CRITICAL
1
C7724
1000PF
10%
16V
2
X7R
201
=P1V8S0_EN
62
IN
P1V8S0_PGOOD
62
OUT
C
C7720
22UF
X5R-CERM-1
1
20%
6.3V
2
603
5
EN
7
PG
4
SYNCH
SGND
9
10
1
2
VIN
U7720
ISL8014A
QFN
CRITICAL
PGND
11
12
3
VDD
THRM_PAD
17
VFB
14
LX
SWITCH_NODE=TRUE
15
LX
DIDT=TRUE
8
16
NC
6
NC
NC
13
NC
1.8V S0 Regulator
152S1302
L7720
1.0UH-20%-4.5A-24MOHM
PIMB042T-SM
P1V8S0_SW
P1V8S0_FB
1 2
CRITICAL
R7720
113K
1/20W
<Ra>
R7721
90.9K
1/20W
<Rb>
=PP1V8_S0_REG
CRITICAL
1
C7723
47PF
5%
1
1%
MF
201
2
1
1%
MF
201
2
25V
2
NP0-C0G
201
1
C7721
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
C7722
X5R-CERM-1
Vout = 1.794V
Max Current = 1.8A
Freq = 1 MHz
1
22UF
20%
6.3V
2
603
7
Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
CRITICAL
XDP_PCH
U7740
=PP3V3_SUS_P1V05SUSLDO
7
XDP_PCH
C7740
1UF
6.3V
CERM
1
10%
2
402
TPS720105
SON
4
BIAS
6
IN
3
EN
OUT
NC
THRM
PADGND
5
7
=PP1V05_SUS_LDO
Vout = 1.05V
1
Max Current = 0.020A
2
NC
XDP_PCH
1
C7741
2.2UF
10%
6.3V
2
X5R
402
7
Vout = 0.8V * (1 + Ra / Rb)
D
C
SIZE
B
A
D
B
1.5V S0 LDO
CRITICAL
U7770
TPS72015
SON
=PP3V3_S0_P1V5S0
7
=PP1V8_S0_P1V5S0
7
IN
=P1V5S0_EN
62
IN
1
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U7770.6:1mm
C7771
C7770
A
PLACE_NEAR=U7770.4:1mm
4
BIAS
6
IN
3
EN
1
1UF
10%
6.3V
2
CERM
402
OUT
NC
THRM
PADGND
5
7
=PP1V5_S0_REG
Vout = 1.5V
1
Max Current = 0.02A
2
NC
1
C7772
2.2UF
10%
6.3V
2
X5R
402
7
=PP3V3_S0_P1V05S0LDO
7
=PP1V8_S0_P1V05S0LDO
7
=1V05_S0_LDO_EN
62
C7782
PLACE_NEAR=U7780.4:1mm
1
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U7780.6:1mm
8 7 5 4 2 1
1.05V S0 LDO
CRITICAL
U7780
TPS720105
4
BIAS
6
IN
3
EN
1
C7780
1UF
10%
6.3V
2
CERM
402
5
SON
OUT
NC
THRM
PADGND
7
=PP1V05_S0_LDO
Vout = 1.05V
1
Max Current = 0.35A
2
NC
1
C7781
2.2UF
10%
6.3V
2
X5R
402
7
SYNC_MASTER=K78_MLB
PAGE TITLE
Misc Power Supplies
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/16/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
77 OF 109
SHEET
60 OF 75
36
Page 61
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345678
2 1
3.3V S0 FET
=PP3V3_S0_P3V3S0FET
7
1
R7832
3
SOT563
D
5
SG
4
D
=P3V3S0_EN
62
IN
Q7812
SSM6N37FEAPE
10K
5%
1/20W
MF
201
2
P3V3S0_EN_L
R7830
1 2
C7831
0.033UF
91K
5%
1/20W
MF
201
1
10%
16V
2
X5R
402
P3V3S0_SS
3.3V_SUS FET
=PP3V3_S5_P3V3SUSFET
7
12K
5%
1/20W
MF
201
3.3K
5%
1/20W
MF
201
10%
16V
X5R
402
10%
16V
X5R
402
1
2
P3V3SUS_SS
1
2
P5VSUS_SS
1
6
SOT563
SOT563
D
2
SG
1
3
D
5
SG
4
Q7822
SSM6N37FEAPE
3.3V S3 FET
=PP3V3_S3_P3V3S3FET
7
1
6
SOT563
D
2
SG
1
C
=P3V3S3_EN
62
IN
Q7812
SSM6N37FEAPE
R7812
100K
5%
1/20W
MF
201
2
P3V3S3_EN_L
1 2
C7811
0.033UF
R7810
47K
5%
1/20W
MF
201
1
10%
16V
2
X5R
402
P3V3S3_SS
4 7
CRITICAL
Q7810
SIA427DJ
SC70-6L
S
G
3
C7810
0.01UF
1 2
10%
10V
X5R
201
=P5V_3V3_SUS_EN
61 62
IN
D
1
=PP3V3_S3_FET
7
3.3V S3 FET
CHANNEL
RDS(ON)
LOADING
SiA427MOSFET
P-TYPE 8V/5V
31 mOhm @1.8V
1.608 A (EDP)
61 62
IN
=PP5V_S5_P5VSUSFET
7
Q7822
SSM6N37FEAPE
=P5V_3V3_SUS_EN
R7822
100K
5%
1/20W
MF
201
2
P3V3SUS_EN_L
5V_SUS FET
1
R7842
220K
5%
1/20W
MF
201
2
P5VSUS_EN_L
C7821
0.033UF
R7820
1 2
C7841
0.033UF
R7840
1 2
4 7
CRITICAL
Q7820
SIA427DJ
S
4 7
3
CRITICAL
Q7840
SIA413DJ
SC70-6L
S
4 7
3
CRITICAL
Q7830
SIA427DJ
SC70-6L
S
G
3
C7830
0.01UF
1 2
10%
10V
X5R
201
SC70-6L
D
G
C7820
0.01UF
1 2
10%
10V
X5R
201
D
G
C7840
0.01UF
1 2
10%
16V
CERM
402
D
1
1
1
=PP3V3_S0_FET
7
3.3V S0 FET
MOSFET
CHANNEL
RDS(ON)
LOADING
=PP3V3_SUS_FET
7
3.3V SUS FET
MOSFET
CHANNEL
RDS(ON)
LOADING
=PP5V_SUS_FET
7
5V SUS FET
MOSFET
CHANNEL
RDS(ON)
LOADING
SiA427
P-TYPE 8V/5V
26 mOhm @1.8V
3.2 A (EDP)
SiA427
P-TYPE 8V/5V
26 mOhm @1.8V
100? mA (EDP)
SiA427
P-TYPE 12V/8V
29 mOhm @4.5V
100? mA (EDP)
D
C
1.5V S3/S0 FET
=PP1V5_S3_P1V5S3RS0_FET
=PP5V_S5_P1V5DDRFET
7
C7801
0.1UF
CERM
B
26
IN
P1V5CPU_EN
NO STUFF
C7802
X5R-CERM
4.7UF
6.3V
1
10%
2
603
7
1
20%
10V
2
402
2
3
VCC
U7801
SLG5AP020
TDFN
ON
CRITICAL
SHDN*
GND
4
1
D
G
4
S
THRM
PAD
9
5
D
7
G
6
S
8
PG
P1V5S0FET_GATE
P1V5S3RS0_RAMP_DONE
R7801
0
1 2
5%
1/16W
MF-LF
402
P1V5S0FET_GATE_R
8
OUT
APN 376S0928
5
CRITICAL
Q7801
FDMC2514SDC
POWER33
1 2 3
PP1V5_S3RS0_FET_R
CRITICAL
R7850
0
1 2
5%
1/4W
MF-LF
1206
=PP1V5_S3RS0_FET
=PP5V_S3_P5VS0FET
7
7
=P5VS0_EN
62
IN
Q7802
SSM6N37FEAPE
SOT563
D
5
SG
5.0V S0 FET
1
R7862
220K
5%
1/20W
MF
201
2
P5V0S0_EN_L
3
4
C7861
0.033UF
R7860
10K
1 2
5%
1/20W
MF
201
10%
16V
X5R
402
1
2
P5V0S0_SS
1.5V S3/S0 FET
MOSFET
CHANNEL
RDS(ON)
LOADING
PQFN2X2
N-TYPE
9.4 mOhm @4.5V
5 A (EDP)
A
8 7 5 4 2 1
36
CRITICAL
Q7860
TPCP8102
1 2 3
23V1K-SM
S
G
4
D
C7860
0.01UF
1 2
10%
16V
CERM
402
=PP5V_S0_FET
7
5.0V S0 FET
5 6 7 8
SYNC_MASTER=K78_MLB
PAGE TITLE
MOSFET TPCP8102
CHANNEL
RDS(ON)
LOADING
Power FETs
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
P-TYPE
18 MOHM @4.5V
1.678 A (EDP)
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
78 OF 109
SHEET
61 OF 75
SIZE
B
A
D
Page 62
D
C
B
A
41
IN
=PP3V3_S0_VMON
62
7
S0PGOOD_ISL
S0PGOOD_ISL
MAKE_BASE=TRUE
www.laptopblue.vn
345678
S5 Rail Enables & PGOOD
=PP3V42_G3H_PWRCTL
62
7
C7940
0.1UF
10%
6.3V
X5R
201
SMC_PM_G2_EN
=PP3V3_S5_PWRCTL
62
7
Threshold: ??
DLY > 10 ms
S5PGOOD_DLY
1
C7941
220PF
10%
25V
2
X7R-CERM
201
1
R7951
15K
1%
1/20W
MF
201
2
1
R7952
7.15K
1%
1/20W
MF
201
2
62
62
ALL_SYS_PWRGD
PLACE_NEAR=U7400.1:5mm
R7976
1 2
1/20W
201
=PP3V3_S5_VMON
7
VMON_3V3_DIV VMON_Q2_BASE
=PP1V5_S3RS0_VMON
7
PP1V5_S3RS0
=PP1V05_S0_VMON
7
62 52 41 25 23
S0 Rail PGOOD Circuitry
(ISL Version in development)
Thresholds:
VDD: 2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
=PP5V_S0_VMON
7
R7960
R7961
6.04K
1/20W
1/20W
201
15K
201
62
1%
MF
1%
MF
=PP1V5_S3RS0_VMON
7
S0PGOOD_ISL
R7970
10K
1/20W
201
P5V_DIV_VMON
S0PGOOD_ISL
R7971
10K
1/20W
201
62
1%
MF
1%
MF
1
2
1
2
=PP1V05_S0_VMON
7
1
S0PGOOD_ISL
R7972
6.04K
1/20W
2
P1V5_DIV_VMON
1
S0PGOOD_ISL
R7973
15K
1/20W
2
1%
MF
201
1%
MF
201
8 7 5 4 2 1
Internal pull-ups 100K +/- 20%
1
2
2
IN_A
(IPD)
6
IN_B
1.3V
7
DLY_1C
R7974
0
1 2
5%
1/20W
MF
201
0
5%
MF
1
CRITICAL
343S0497
VDD
U7941
SLG4AP012
TDFN
OUT_A*
(OD,IPU)
DLY
THRM
PAD
(OD,IPU)
OUT_B
(OD,IPU)
9
2:1
GND
+
-
5
CPUVCORE ENABLE
PLACE_NEAR=U7400.1:5mm
CPUVCCIOS0_PGOOD
62 59
4
NC
3
OUT_A
P5V3V3_REG_EN
MAKE_BASE=TRUE
8
PLACE_NEAR=U7400.1:5mm
NO STUFF
R7975
1 2
5%
1/20W
MF
201
S0 Rail PGOOD (BJT Version)
1
R7956
150K
1%
1/20W
MF
201
2
R7953
1 2
1/20W
R7954
1 2
1/20W
R7955
1K
1 2
5%
1/20W
MF
201
=PP3V3_S0_VMON
62
7
S0PGOOD_ISL
C7960
1
2
P1V05_DIV_VMON
1
2
1K
5%
MF
201
1K
5%
MF
201
VMON_Q3_BASE
VMON_Q4_BASE
Worst-Case Thresholds:
Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V
P1V5S0_PGOOD from U7710
1
0.1UF
10%
6.3V
2
X5R
201
3
V2MON
5
V3MON
6
S0PGD_C
5
8
NC
7
2
NC
1
2
7
VDD
U7960
ISL88042IRTEZ
TDFN
CRITICAL
S0PGOOD_ISL
GND
THRM_PAD
4
9
6
Q2
Q3
Q4
(IPU)
1
MR*
8
RST*V4MON
353S2310
CRITICAL
3
NC
ALL_SYS_PWRGD_R
R7941
100
1 2
5%
MF
201
1
2
1/20W
=P5V3V3_REG_EN
S5_PWRGD
MAKE_BASE=TRUE
S5_PWRGD (old name RSMRST_PWRGD)-->SMC
SMC-->PM_DSW_PWRGD
0
4
Q1
353S2809
S0PGD_BJT_GND_R
57
IN
60
IN
55
IN
55
IN
62 59
IN
54
IN
CPUIMVP_VR_ON
ALL_SYS_PWRGD
Q7950
ASMCC0179
DFN2015H4-8
R7957
CPUIMVP_AXG_PGOOD
P1V8S0_PGOOD
P3V3S5_PGOOD
P5VS3_PGOOD
CPUVCCIOS0_PGOOD
PVCCSA_PGOOD
OUT
PM_PECI_PWRGD
SMC_BATLOW_L:100K pull up on SMC page
1
100
5%
1/20W
MF
201
2
=PP3V3_S0_PWRCTL
7
R7965
100
1 2
5%
1/20W
MF
201
R7963
1 2
1/20W
S0PGOOD_ISL
R7962
330
1 2
5%
1/20W
MF
201
C7942
0.033UF
10%
16V
X5R
402
NO STUFF
OUT
OUT
57
41
OUT
42 41
PLACE_NEAR=U1800.A15:5mm
Delete R when pull-down added to PCH page
R7967
NO STUFF
R7968
100
1 2
5%
1/20W
R7966
MF
201
1 2
1/20W
R7901
100
1 2
5%
1/20W
R7964
MF
201
1 2
100
201
5%
MF
1/20W
ALL_SYS_PWRGD
P3V3S5_EN
MAKE_BASE=TRUE
=P3V3S5_EN
55
41
=PP3V3_S5_PWRCTL
62
7
PLACE_NEAR=U7940.5:2.3mm
SMC_BATLOW_L
IN
62 52 41 25 23
PM_SLP_SUS_L
17
IN
R7918
100K
5%
1/20W
MF
201
=PP3V3_SUS_PWRCTL
62
7
1
10K
5%
1/20W
MF
201
2
100
5%
MF
201
100
5%
MF
201
OUT
55
OUT
3.3V S4 ENABLE
PM_SLP_S5_L
41 17
IN
1
R7915
100K
Delete R when pull-down added to PCH page
1/20W
5%
MF
201
2
3.3V/5.0V Sus ENABLE
1
C7943
0.1UF
10%
6.3V
2
X5R
201
1
2
NO STUFF
R7917
1 2
No stuff C7931, 12ms
Min delay time
U7930 Sense input
threhold is 3.07V
U7940
74AUP1G3208
SOT891
1
A
3
B
6
C
0
5%
1/20W
MF
201
=PP3V3_S5_PWRCTL
62
7
VCC
GND
CRITICAL
SENSE
S4_PGOOD_CT
TPS3808G33DBVRG4
4
CT
1
C7931
1000PF
10%
16V
2
X7R
201
NO STUFF
DP S4 Power Enable
SMC_S4_WAKESRC_EN
42 41
IN
MAKE_BASE=TRUE
PSOC USB Power Enable
62 52 41 25 23
State
Run (S0)
Sleep (S3)
Deep Sleep (S4)
Deep Sleep (S5)
Battery Off (G3Hot)
Delete R when pull-down added to PCH page
5
4
PM_SUS_EN
Y
MAKE_BASE=TRUE
2
3.3V SUS Detect
PLACE_NEAR=U7930.6:2.3mm
U7930
SOT23-6
C7930
6
VDD
RESET*
(90K IPU)
GND
2
=DPAPWRSW_EN
0.1UF
6.3V
MR*
SMC_PM_G2_ENABLE
1
1
1
1
0
=P5V_3V3_SUS_EN
=PP3V3_SUS_PWRCTL
1
10%
X5R
201
R7933
100K
2
15
3
NC
OUT
5%
1/20W
MF
201
PM_RSMRST_L
PM_RSMRST_L goes to U1800.C21
65
42 41 17
62 41 26 17
62 41 26 17
1
2
37 18
OUT
17
OUT
AP_PWR_EN
IN
SMC_ADAPTER_EN
IN
PM_SLP_S3_L
IN
PM_SLP_S4_L
1
1
1
0
0
PM_SLP_S3_L
IN
PLACE_NEAR=U1800.D4:5mm
61
1
R7979
100K
5%
1/20W
MF
201
2
=PP3V42_G3H_PWRCTL
7
62
Q7931
SSM3K15FV
SOD-VESM-HF
CHGR VFRQ Generation
Q7925
2N7002DW-X-G
PM_SLP_S3_LPM_SLP_S5_L
1 1
1
0
00
0
0
0
0
S0 ENABLE
R7978
100
1 2
5%
1/20W
MF
201
R7931
10K
5%
1/20W
MF
1 2
201
CHGR_VFRQ
OUT
3
D
1
G S
2
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
6
2
SOT-363
2
G
G
D
S
(AC_EN_L)
1
AC_EN_L
6
D
S
1
NO STUFF
R7929
1/20W
SOT-363
Q7920
2N7002DW-X-G
Delete R when pull-down added to PCH page
IN
R7987
5%
1/20W
MF
201
PVCCSA_EN
MAKE_BASE=TRUE
C7987
0.47UF
10%
6.3V
CERM-X5R
402
PM_SLP_S4_L
MAKE_BASE=TRUE
R7910
100K
1/20W
2
1
PLACE_NEAR=U7600.3:6mm
CPUVCCIOS0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U7600.3:6mm
1
2
37
OUT
3
D
S
4
(PM_SLP_S3_L)
1
5%
MF
201
2
R7981
20K
5%
1/20W
MF
201
C7981
0.47UF
10%
6.3V
CERM-X5R
402
G
49 41 26 17
(PM_SLP_S3_R_L)
2
33K
1
PLACE_NEAR=U7100.15:6mm
53
PLACE_NEAR=U7100.15:6mm
1
2
VFRQ Low: Fix Frequency
VFRQ High: Variable Frequency
1
0
5%
MF
201
2
PLACE_NEAR=U7300.16:6mm
R7911
2
5.1K
5%
1/20W
MF
201
1
PLACE_NEAR=U7300.16:6mm
1
C7910
0.47UF
10%
6.3V
2
CERM-X5R
402
2N7002DW-X-G
Q7920
2N7002DW-X-G
SOT-363
5
36
2 1
3.3V,5V S3 ENABLE
R7913
0
1 2
2
R7912
9.1K
5%
1/20W
MF
201
1
PLACE_NEAR=Q7812.2:6mm
PLACE_NEAR=Q7812.2:6mm
1
C7912
0.47UF
10%
6.3V
2
CERM-X5R
402
PM_SLP_S3_R_L
MAKE_BASE=TRUE
2
R7988
39K
5%
1/20W
MF
1
201
PLACE_NEAR=U7770.3:6mm
P1V5S0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U7770.3:6mm
1
C7988
0.47UF
10%
6.3V
2
CERM-X5R
402
Q7925
SOT-363
NC
5
G
2
R7986
5.1K
5%
1/20W
MF
1
201
PLACE_NEAR=U7720.5:6mm
P1V8S0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U7720.5:6mm
1
C7986
0.47UF
10%
6.3V
2
CERM-X5R
402
NC
3
D
S
4
NC
SYNC_MASTER=K78_MLB
PAGE TITLE
Power Control 1/ENABLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
P5VS3_EN
MAKE_BASE=TRUE
5%
1/20W
MF
201
MAKE_BASE=TRUE
DDRREG_EN
MAKE_BASE=TRUE
Unused fet
Apple Inc.
R
P3V3S3_EN
=P5VS3_EN
NO STUFF
1
C7913
0.068UF
10%
10V
2
CERM
402
=P3V3S3_EN
=DDRREG_EN
=USB_PWR_EN
=P5VS0_EN
=P3V3S0_EN
=PBUSVSENS_EN
=P1V8S0_EN
=P1V5S0_EN
=1V05_S0_LDO_EN
=CPUVCCIOS0_EN
=PVCCSA_EN
SYNC_DATE=01/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
79 OF 109
SHEET
62 OF 75
55
OUT
D
61
OUT
56
OUT
40 39
6
OUT
61
OUT
61
OUT
45
OUT
60
OUT
60
OUT
60
OUT
59
OUT
54
OUT
C
B
A
SIZE
D
Page 63
www.laptopblue.vn
345678
2 1
D
D
LCD Connector
Internal DP Connector: 518S0787
CRITICAL
J9000
CABLINE-CA
F-RT-SM
R9061
0
=I2C_TCON_SDA
44
BI
=I2C_TCON_SCL
44
IN
C
B
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP
8
IN
=PP3V3_S5_LCD
7
LCD_IG_PWR_EN
R9014
1/20W
1
1
C9009
1K
0.1UF
5%
10%
6.3V
MF
2
X5R
201
201
2
2
3
ON
VIN_1
VIN_2
CRITICAL
U9000
FPF1009
MFET-2X2-8IN
GND
617
VOUT_1
VOUT_2
THRM
PAD
4
5
C9011
0.1UF
10% 20%
6.3V
X5R
201
1
2
PP3V3_SW_LCD_UF
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
1
C9012
10UF
6.3V
2
X5R
603
9
9
70
9
70
9
70
9
70
9
70
70
9
DP_INT_HPD
OUT
DP_INT_AUX_CH_N
BI
DP_INT_AUX_CH_P
BI
DP_INT_ML_P<0>
IN
DP_INT_ML_N<0>
IN
DP_INT_ML_P<1>
IN
DP_INT_ML_N<1>
IN
C9024
0.1UF
1 2
10%
16V
X5R-CERM
0201
C9020
0.1UF
1 2
10%
16V
X5R-CERM
0201
C9022
0.1UF
1 2
10%
16V
X5R-CERM
0201
1 2
R9062
1 2
C9025
0.1UF
1 2
10%
16V
X5R-CERM
0201
C9021
0.1UF
1 2
10%
16V
X5R-CERM
0201
C9023
0.1UF
1 2
10%
16V
X5R-CERM
0201
1/20W
1/20W
5%
MF
201
0
5%
MF
201
I2C_TCON_SDA_R
6
I2C_TCON_SCL_R
6
(DP_INT_AUX_CH_C_N)
(DP_INT_AUX_CH_C_P)
Pull-ups on panel side,
4.7 kOhm to 3.3V
L9004
FERR-120-OHM-1.5A
1 2
0402-LF
C9015
1000PF
10%
16V
X7R
201
R9050
100K
1/20W
6
66
6
66
6
66
6
66
6
66
66
6
R9060
0
1 2
5%
1/20W
MF
201
1
1
R9070
100K
5%
1/20W
2
MF
201
2
1
1
R9080
100K
5%
5%
1/20W
MF
MF
201
201
2
2
PPVOUT_SW_LCDBKLT
6
66
LED_RETURN_6
OUT
LED_RETURN_5
OUT
LED_RETURN_4
OUT
LED_RETURN_3
OUT
LED_RETURN_2
OUT
LED_RETURN_1
OUT
DP_INT_HPD_CONN
6
PP3V3_SW_LCD
6
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
DP_INT_AUX_CH_C_N
6
70
DP_INT_AUX_CH_C_P
6
70
DP_INT_ML_F_P<0>
6
70
DP_INT_ML_F_N<0>
6
70
DP_INT_ML_F_P<1>
6
70
DP_INT_ML_F_N<1>
70
6
PLACE_NEAR=J9000.25:1mm
R9017
1/20W
1
1
R9018
1M
1M
5%
5%
1/20W
MF
MF
201201
2
2
PLACE_NEAR=J9000.24:1mm
PLACE_NEAR=J9000.3:2mm
C9017
1000PF
C0G-CERM
1
5%
50V
2
603
31
1
2
NC
3
4
5
NC
6
7
8
LED Backlight I/F
9
10
11
12
NC
13
14
15
16
DisplayPort I/F
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
35
36
37
38
39
40
41
32
C
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K78_MLB
PAGE TITLE
Internal DisplayPort Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/10/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
90 OF 109
SHEET
63 OF 75
SIZE
A
D
Page 64
DP_EXTA_ML_C_P<0>
70
8
IN
DP_EXTA_ML_C_N<0>
70
8
IN
DP_EXTA_ML_C_P<1>
70
8
IN
DP_EXTA_ML_C_N<1>
70
8
IN
DP_EXTA_ML_C_P<2>
70
8
D
IN
DP_EXTA_ML_C_N<2>
70
8
IN
DP_EXTA_ML_C_P<3>
70
8
IN
DP_EXTA_ML_C_N<3>
70
8
IN
DP_EXTA_AUXCH_C_P
70
8
BI
DP_EXTA_AUXCH_C_N
70
8
BI
If GPU uses common pins for AUX_CH
and DDC, alias nets together at GPU.
=PP3V3_S0_DPSDRVA
64
7
C9300
C9301
C9302
C9303
C9304
C9305
C9306
C9307
C9308
C9309
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
10%
X5R-CERM
X5R-CERM
X5R-CERM
X5R-CERM
X5R-CERM
X5R-CERM
10% 16V
X5R-CERM
X5R-CERM
X5R-CERM
10% 16V
X5R-CERM
C9310
PS8301 I2C Addresses:
C
A1 A0 Addr (W/R)
0 0 0x96/0x97
0 1 0xB6/0xB7
1 0 0x94/0x95
1 1 0xB4/0xB5
Note: Other Parade
devices use 96/B6,
so only 94/B4 are
used for this part.
NO STUFF
1
1/20W
1K
5%
MF
201
2
1
R9310
1K
5%
1/20W
MF
201
2
R9390
0
1 2
5%
1/20W
MF
201
SDRV_PD
R9318
OMIT
R9330
1/20W
12
0
5%
1/20W
MF
201
1
SWCLK
0
5%
MF
201
2
SWDIO
R9311
1
R9312
1K
5%
1/20W
MF
201
2
B
=T29_WAKE_L:
A
Desktops use PCIe WAKE#
Mobiles use S4 WAKE#
R9330 provides pads for programming/debug of MCU, please make accessible.
If project has space for 10-pin programming header it should be used.
23 16
DP_A_PWRDWN
64
DP_AUXCH_ISOL
IN
17
OUT
64
=T29_WAKE_L
T29_A_UC_ADDR
1
R9319
4.99K
1%
1/20W
MF
201
2
70 64
70 64
70 64
70 64
70 64
70 64
70 64
70
8
IN
8
BI
70 64
70 64
8
OUT
44
IN
44
BI
8 7 5 4 2 1
DP_EXTA_ML_P<0>
0201
16V
DP_EXTA_ML_N<0>
0201
16V10%
DP_EXTA_ML_P<1>
16V10%
0201
DP_EXTA_ML_N<1>
0201
16V10%
DP_EXTA_ML_P<2>
0201
16V10%
DP_EXTA_ML_N<2>
16V10%
0201
DP_EXTA_ML_P<3>
0201
DP_EXTA_ML_N<3>
0201
16V10%
16V10%
2.2UF
20%
6.3V
CERM
402-LF
DP_EXTA_ML_P<0>
DP_EXTA_ML_N<0>
DP_EXTA_ML_P<1>
DP_EXTA_ML_N<1>
DP_EXTA_ML_P<2>
DP_EXTA_ML_N<2>
DP_EXTA_ML_P<3>
DP_EXTA_ML_N<3>
64
DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
DP_EXTA_AUXCH_P
0201
DP_EXTA_AUXCH_N
0201
1
1
2
2
R9309
R9308
C9311
0.1UF
10%
16V
X5R-CERM
0201
DP_EXTA_HPD
DPSDRVA_I2C_CTL_EN
DPSDRVA_I2C_ADDR0
DPSDRVA_I2C_ADDR1
=I2C_DPSDRVA_SCL
=I2C_DPSDRVA_SDA
DPSDRVA_REXT
DP_AUXCH_ISOL_R
DP_A_PWRDWN_R
PS8301 has internal
~150K pull-down on PD
pin. Okay to drive this
pin even when VCC=0V per
Parade (pin is 5V-tolerant).
DP_A_CA_DET
64
T29_LSEO<0>
34
IN
=I2C_T29AMCU_SCL
44
IN
=I2C_T29AMCU_SDA
44
BI
T29DPA_HPD
65
IN
8
34
34
18
T29_A_BIAS
OUT
T29_LSOE<0>
OUT
T29_LSOE<1>
OUT
T29_MCU_INT_L
OUT
65 64
70 64
70 64
70 64
70 64
70 64
70 64
70 64
1 2
1M
1 2
1M
70 64
5%
MF
70 64
70 64
MF5%201
=PP3V3_S0_DPSDRVA
1/20W
201
R9308/R9309 maintain bias on C9308/C9309
to prevent spikes when U9310 AUXDDC_OFF
1/20W
transitions from high to low.
DP A Super-Driver
1
C9312
2
0.1UF
10%
16V
X5R-CERM
0201
1
IN_D0P
2
IN_D0N
4
IN_D1P
5
IN_D1N
7
IN_D2P
8
IN_D2N
9
IN_D3P
10
IN_D3N
14
IN_SCL
13
IN_SDA
16
IN_AUXP
15
IN_AUXN
3
IN_HPD
26
I2C_CTL_EN
36
I2C_ADDR0
35
I2C_ADDR1
38
SCL_CTL
37
SDA_CTL
12
REXT
39
AUXDDC_OFF
34
PD
21
VDD
U9310
PS8301TQFN40GTR-A2
QFN
CRITICAL
(IPU)
(IPD)
(IPD)
(IPD)
(IPD)
GND
6
33
40
OUT_D0P
OUT_D0N
OUT_D1P
OUT_D1N
OUT_D2P
OUT_D2N
OUT_D3P
OUT_D3N
AC_AUXP
AC_AUXN
OUT_AUXP_SCL
OUT_AUXN_SDA
OUT_HPD
(IPD)
THMPAD
41
CA_DET
Port A MCU
PP3V3_SW_DPAPWR
65 64
CRITICAL
1
RESET#/PIO0_0
2
PIO0_1/CLKOUT
7
PIO0_2/SSEL/CT16B0_CAP0
8
PIO0_4/SCL
9
PIO0_5/SDA
10
PIO0_6/SCK
11
PIO0_7/CTS#
12
PIO0_8/MISO/CT16B0_MAT0
13
PIO0_9/MOSI/CT16B0_MAT1
14
SWCLK/PIO0_10/SCK/CT16B0_MAT2
15
R/PIO0_11/AD0
(OD)
(OD)
CEXT
64
7
30
DP_SDRVA_ML_C_P<0>
72
29
DP_SDRVA_ML_C_N<0>
72
28
DP_SDRVA_ML_C_P<1>
72
27
DP_SDRVA_ML_C_N<1>
72
25
DP_SDRVA_ML_C_P<2>
72
24
DP_SDRVA_ML_C_N<2>
72
23
DP_SDRVA_ML_C_P<3>
72
22
DP_SDRVA_ML_C_N<3>
72
20
DP_SDRVA_AUXCH_C_P
72
19
DP_SDRVA_AUXCH_C_N
72
18
(DP_SDRVA_AUXCH_P)
17
(DP_SDRVA_AUXCH_N)
31
(DP_SDRVA_HPD)
32
DP_A_CA_DET
11
DPSDRVA_CEXT
PLACE_NEAR=U9310.11:2 mm
Must be 3.3V DP A port power
5
22
VDD
U9330
LPC1112A
HVQFN25
(IPU)
PIO1_4/AD5/WAKEUP
PIO1_8/CT16B1_CAP0
(OD)
THRM
VSS
PAD
3
25
21
www.laptopblue.vn
GND_VOID=TRUE
GND_VOID=TRUE
(C9370/C9371)
GND_VOID=TRUE
GND_VOID=TRUE
(C9380/C9381)
DP_SDRVA_ML_R_P<0>
DP_SDRVA_ML_R_N<0>
DP_SDRVA_ML_R_P<2>
DP_SDRVA_ML_R_N<2>
0201
0201
0201
0201
0201
0201
R9392
65
IN
65
IN
64 42
34
IN
1/20W
51
5%
MF
1
2
1 2
IN
1
C9319
2.2UF
20%
6.3V
2
CERM
402-LF
OMIT_TABLE
R/PIO1_0/AD1
R/PIO1_1/AD2
R/PIO1_2/AD3
SWDIO/PIO1_3/AD4
PIO1_6/RXD
PIO1_7/TXD
(OD)
XTALIN
OUT
34
OUT
34 72
34 72
T29_D2R_N<0>
T29_D2R_P<0>
T29_R2D_C_N<0>
IN
T29_R2D_C_P<0>
IN
72 34
72
T29 signals are
P/N-swapped after AC
caps to improve layout.
T29_D2R_N<1>
34 72
OUT
T29_D2R_P<1>
34
72
OUT
T29_R2D_C_N<1>
34 72
IN
T29_R2D_C_P<1>
72 34
IN
30
R9354
5%
MF
R9355
5% MF
R9350
5%
MF
R9351
5%
MF
64
1
C9330
2
16
17
18
19
20
23
24
6
4
1/20W
201
30
1/20W
30
1/20W
201
30
1/20W
201
0.1UF
10%
16V
X5R-CERM
0201
T29DPA_CONFIG1_RC
T29DPA_CONFIG2_RC
T29_A_HV_EN_R
T29_A_UC_ADDR
DP_A_EXT_HPD
T29_A_LSX_P2R
T29_A_LSX_R2P
T29_LSEO<1>
1
R9335
1K
5%
1/20W
MF
201
2
1 2
R9353
270
5%
1/20W
MF
C9363
C9362
C9367
C9366
C9369
C9368
1
C9331
2
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10%
16V
X5R-CERM
0201
1
R9336
10K
5%
1/20W
MF
201
2
201
201
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
AUXCH Snoop Port,
used by PS8301
during training.
1
72
72
2
72
72
1
R9352
270
5%
1/20W
MF
201
2
16V10%
X5R-CERM
16V10%
X5R-CERM
10%
16V
X5R-CERM
16V10%
X5R-CERM
16V10%
X5R-CERM
10% 16V
X5R-CERM
64
I2C Addr:
0x26/0x27 (Wr/Rd)
8
(C9372.2)
(C9373.2)
8
IN
8
(C9383.2)
(C9383.2)
8
IN
1
R9393
51
5%
1/20W
MF
201201
2
R9338
R9334
10K
5%
1/20W
MF
201
IN
IN
64
10K
1/20W
201
T29_A_BIAS_R2DP0
C9370
C9371
C9372
0.47UF
C9373
0.47UF
T29_A_BIAS_R2DN0
T29_A_BIAS_R2DP1
C9380
C9381
C9382
0.47UF
C9383
0.47UF
T29_A_BIAS_R2DN1
C9364
0.22UF
C9365
0.22UF
C9360
0.22UF
C9361
0.22UF
=PP3V3_S0_DPSDRVA
7
64
IC supports input
high while Vcc = 0V.
1
5%
MF
2
1 2
4V
1 2
GND_VOID=TRUE
1 2
1 2
GND_VOID=TRUE
1 2
1 2
GND_VOID=TRUE
1 2
1 2
GND_VOID=TRUE
1 2
1 2
1 2
1 2
20%
CERM-X5R-1
20%
CERM-X5R-1
20%
CERM-X5R-1
20%
CERM-X5R-1
20%
CERM-X5R-1
20%
CERM-X5R-1
20%
CERM-X5R-1
20%
CERM-X5R-1
20%
X5R
20%
X5R
20%
X5R
20%
X5R
C9359
201
4V
201
4V
201
4V
201
4V
201
4V
201
4V
201
4V
201
6.3V
0201
6.3V
0201
6.3V
0201
6.3V
0201
0.1UF
0.47UF
0.47UF
0.47UF
0.47UF
DP_A_PWRDWN
12
R9396
1K
5%
1/20W
MF
201
T29_A_HV_EN
P2R = Plug to Receptacle
R2P = Receptacle to Plug
1
R9339
1M
5%
1/20W
MF
201
2
345678
GND_VOID=TRUE
R9372
1.5K
1 2
SIGNAL_MODEL=EMPTY
T29_R2D_P<0>
72
T29_R2D_N<0>
72
GND_VOID=TRUE
1.5K
1 2
R9373
SIGNAL_MODEL=EMPTY
T29 Path
Biasing
GND_VOID=TRUE
R9382
1.5K
1 2
SIGNAL_MODEL=EMPTY
T29_R2D_P<1>
72
T29_R2D_N<1>
72
GND_VOID=TRUE
1.5K
1 2
R9383
SIGNAL_MODEL=EMPTY
DP_SDRVA_ML_P<0>
72
DP_SDRVA_ML_N<0>
72
DP_SDRVA_ML_P<2>
72
DP_SDRVA_ML_N<2>
72
1
10%
6.3V
2
X5R
201
2
CRITICAL
5
U9359
74LVC1G04DBDCK
3
4
SC70
72
72
72
72
72
72
DP_SDRVA_ML_N<3>
DP_SDRVA_ML_P<3>
DP_SDRVA_ML_N<1>
DP_SDRVA_ML_P<1>
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
DP_SDRVA_HPD
T29_A_RSVD_N
69
8
T29_A_RSVD_P
69
8
(T29_A_LSX_P2R)
(T29_A_LSX_R2P)
T29_D2R1_BIASP
65 64
65 36
T29_D2R1_BIASN
DP_A_PWRDWN
64
T29_A_BIAS
8
12
R9397
1K
5%
1/20W
MF
201
CBTL04DP081 (353S3151) and
PI3vEDP212 (353S3055) are
footprint-compatible parts with
similar pinouts. NXP uses pin
10 for ML and HPD, Pericom uses
pin 10 for ML and pin 11 for HPD.
OUT
36
2 1
T29 A High-Speed Signals
5%
MF
5%
MF
5%
MF
5%
MF
1/20W
201
1/20W
201
1/20W
201
1/20W
201
DP_A_BIAS
D9372/D9373:
D9364/D9365:
D9364
BAR90-02LRH
D9372
BAR90-02LRH
D9373
BAR90-02LRH
D9365
BAR90-02LRH
D9360
BAR90-02LRH
D9382
BAR90-02LRH
D9383
BAR90-02LRH
D9361
BAR90-02LRH
R9361
R9360
R9365
R9364
1 2
TSLP-2-7
1 2
TSLP-2-7
1 2
TSLP-2-7
1 2
TSLP-2-7
CRITICAL
CRITICAL
CRITICAL
CRITICAL
(All 4 D’s)
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1 2
TSLP-2-7
1 2
TSLP-2-7
1 2
TSLP-2-7
1 2
TSLP-2-7
CRITICAL
CRITICAL
CRITICAL
CRITICAL
(All 4 D’s)
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=T29PIN
(D9382/D9383)
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
(D9360/D9361)
DP Path Biasing
1.5K
1 2
1.5K
1 2
1.5K
1 2
1.5K
1 2
GND_VOID=TRUE
GND_VOID=TRUE
5%
1/20W
MF
5%
1/20W
MF
1/20W
MF5%201
5%
1/20W
MF
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
201
201
201
DP/T29 A Low-Speed MUX
PP3V3_SW_DPAPWR
Must be 3.3V DP A port power
65 64
VDD
TQFN
CRITICAL
LO=Port A
HI=Port B
GND
28
39121620
1
D0+
2
D0-
4
D1+
5
D1-
6
AUX+
7
AUX-
8
HPD
21
29
31
D0+A
30
D0-A
U9390
PI3VEDP212
27
D1+A
26
D1-A
19
AUX+A
18
AUX-A
17
HPD_A
25
D0+B
24
D0-B
23
D1+B
22
D1-B
15
AUX+B
14
AUX-B
13
HPD_B
NC
10
SEL
32
AUX_SEL
11
HPD_SEL
THMPAD
33
Note: U9390 ML/HPD defaults to T29 mode so that DP/T29
Display can detect host T29 support using I2C
pull-ups on ML<3>. U9390 AUX defaults to DP mode
because 100-ohm pull-downs would defeat DP Sink’s
detection of DP Source.
SYNC_MASTER=K21_MLB
PAGE TITLE
DisplayPort/T29 A MUXing
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
T29_D2R_C_P<0>
T29_D2R_C_N<0>
(D9364.2)
T29: TX_0
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>
(D9372/D9373)
(D9365.2)
GND_VOID=TRUE
1.5K
R9374
1.5K
R9375
GND_VOID=TRUE
T29_D2R_C_P<1>
T29_D2R_C_N<1>
(D9360.2)
T29: TX_1
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>
(D9382/D9383)
(D9361.2)
GND_VOID=TRUE
1.5K
R9384
GND_VOID=TRUE
1.5K
R9385
DP_A_BIAS_N_2
8
VOLTAGE=3.3V
DP_A_BIAS_P_2
8
VOLTAGE=3.3V
201
PLACE_NEAR=C9361.1:2mm
DP_A_BIAS_N_0
8
VOLTAGE=3.3V
PLACE_NEAR=C9361.1:2mm
DP_A_BIAS_P_0
8
VOLTAGE=3.3V
1
R9399
100K
5%
1/20W
MF
201
2
T29DPA_ML_N<3>
T29DPA_ML_P<3>
T29: Unused
T29DPA_ML_N<1>
T29DPA_ML_P<1>
T29: LSX_A_R2P/P2R (P/N)
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
T29: RX_1 Bias Sink
DP_A_EXT_HPD
1
R9398
100K
5%
1/20W
MF
201
2
1 2
1 2
1 2
1 2
PLACE_NEAR=C9361.1:2mm
R9366
51
5%
MF
R9367
201515%MF
1
C9390
0.1UF
10%
16V
2
X5R-CERM
0201
IN
IN
OUT
OUT
5%
1/20W
MF
201
1/20W
MF5%201
IN
IN
OUT
OUT
5%
1/20W
201
MF
5%MF1/20W
201
R9362
1 2
5%511/20W
201
MF
PLACE_NEAR=C9361.1:2mm
12
1/20W
R9363
51
201
5%MF
12
1/20W
1
C9391
0.1UF
10%
16V
2
X5R-CERM
0201
OUT
BI
BI
OUT
BI
BI
IN
SYNC_DATE=12/13/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
93 OF 109
SHEET
64 OF 75
12
1/20W
72 65
72 65
72 65
72 65
D
72 65
72 65
72 65
72 65
C
72 65
72 65
72 65
72 65
B
72 65
72 65
64 42
A
SIZE
D
Page 65
www.laptopblue.vn
345678
2 1
3.3V/HV Power MUX
PP3V3_SW_DPAPWR
64
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
Port A HV Power Switch
Nominal Min Max
IFLT 885mA 876mA 894mA (*)
ILIM 935mA 925mA 1A (*)
TFLT 18.3ms 13.4ms 26.7ms
D
=PPHV_SW_DPAPWRSW
7
20V Max
R9416
470K
1/20W
1
5%
MF
201
2
DPAPWRSW_HVEN_L_R
DPAPWRSW_CT
1
R9412
0
5%
1/16W
MF-LF
402
2
C9410
0.1UF
603-1
SN1010017
1
CRITICAL
2
VIN
U9410
SN1010017
QFN
EN*
(IPU-Weak!)
RTRY*
CT
GND
5
13
14
VOUT
FLT*
ILIM
IFLT
THRM
PAD
17
3
1
10%
50V
X7R
4
2
16 15
9
IFLT = 200k / RFLT = 885mA
Q9415
SSM3K15FV
SOD-VESM-HF
ILIM = 201k / RLIM = 935mA
3
D
TFLT = CCT * 38900
TSD = CCT * 100000
1
G S
C
T29_A_HV_EN
36 64 65
IN
1
R9490
51
5%
1/20W
MF
201
2
T29_A_BIAS_R
VOLTAGE=3.3V
R9498
GND_VOID=TRUE
C9490
0.1UF
1 2
PLACE_NEAR=C9490.1:2mm
2.2K
1/20W
201
T29_A_BIAS
8
64 65
IN
T29_A_BIAS_D2RP1
8
B
IN
8
IN
T29_A_BIAS_D2RN1
SIGNAL_MODEL=EMPTY
T29_D2R_C_P<1>
64 72
OUT
T29_D2R_C_N<1>
64 72
OUT
2
10%
6.3V
X5R
201
8
OUT
1
1
R9499
SIGNAL_MODEL=EMPTY
2.2K
5%
5%
1/20W
MF
MF
201
2
2
GND_VOID=TRUE
64 72
OUT
64 72
OUT
64 72
BI
64 72
BI
T29: Unused
D9498
BAR90-02LRH
D9499
BAR90-02LRH
64 72
BI
64 72
BI
T29_D2R_C_P<0>
T29_D2R_C_N<0>
T29DPA_ML_P<3>
T29DPA_ML_N<3>
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
Bleeder Resistor
2.5V / 249 ohm = 10mA
R9419
249
1 2
1/20W
201
Note: Bleeder active when
DPAPWRSW_HV_DET is
HIGH and T29_A_HV_EN
is LOW.
R9494
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=T29PIN
1 2
TSLP-2-7
1 2
TSLP-2-7
CRITICAL
CRITICAL
GND_VOID=TRUE
GND_VOID=TRUE
SIGNAL_MODEL=T29PIN
(Both L’s)
1%
MF
1K
5%
1/20W
MF
201
P = ~27mW
DPAPWR_BLDR_E
MIN_LINE_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.20 MM
GND_VOID=TRUEGND_VOID=TRUE
1
1
R9495
1K
5%
1/20W
MF
201
2
2
SIGNAL_MODEL=EMPTY
TSD 470ms 235ms 724ms
(*) U9410 tolerance unknown
10
11
PPHV_SW_DPAPWR
MIN_LINE_WIDTH=0.4 MM
12
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=15V
1
C9411
0.1UF
10%
50V
2
X7R
603-1
76
8
TP_DPAPWRSW_FLT_L
DPAPWRSW_ILIM
DPAPWRSW_IFLT
3
4
G
2
650NH-5%-0.430MA-0.052OHM
T29DPA_D2R1_AUXCH_P
72
T29DPA_D2R1_AUXCH_N
72
650NH-5%-0.430MA-0.052OHM
1
C9498
30PF
CERM
1
5%
2
2
402
Q9419
DMB53D0UV
SOT-563
5
C9499
30PF
5%
50V50V
CERM
402
1
R9410
100K
5%
1/20W
MF
201
2
<RFLT>
DPAPWR_BLDR_B
6
D
Q9419
DMB53D0UV
SOT-563
S
1
SIGNAL_MODEL=EMPTY
CRITICAL
L9498
0603
CRITICAL
L9499
0603
SIGNAL_MODEL=EMPTY
CRITICAL
D9410
SM
1 2
STPS2L30AF
1
R9411
210K
1%
1/20W
MF
201
2
<RLIM><CT>
GND_VOID=TRUE
12
12
GND_VOID=TRUE
C9400
0.01UF
1
R9427
100K
1%
1/20W
MF
201
2
1
R9428
21.5K
1%
1/20W
MF
201
2
1
C9426
0.1UF
10%
16V
2
X5R-CERM
0201
ZXRE060A REF range: 0.595-0.605V (0.600V nominal)
Circuit threshold range: 3.363-3.439V (3.395V nominal)
PP3V3RHV_SW_DPAPWR_UF
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
1
10%
50V
2
X7R
402
R9402
12
1 2
5%
1/20W
MF
201
1
C9402
0.01UF
1
C9401
0.01UF
10%
50V
X7R
402
10%
50V
2
2
X7R
402
SI8409DB:
Vds(max): -30V
Vgs(max): +/-12V
Vgs(th): -1.4V
Rds(on): 65mOhm @ 2.5V Vgs
Id(max): 3.7A @ 70C
3.3V/HV MUXed
1
R9424
22
5%
1/20W
MF
201
2
DPAPWRSW_VREF
CRITICAL
3
IN
OUT
U9426
ZXRE060A
SOT353
FB
GND
PGND
2
1
T29 Dir
T29DPA_HPD_R
DPACONN_20_RC
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
R9425
4.7K
1/20W
DPAPWR_ON_L_C
5
4
L9400
FERR-120-OHM-3A
1 2
DP Dir
Blocking FET, off
1
when Source >3.4V
or HV_EN high.
5%
MF
201
2
DPAPWRSW_P3V3_ON_L
C9424
DPAPWRSW_HV_DET_R_L
1
R9429
4.7K
5%
1/20W
MF
201
2
DPAPWRSW_HV_DET_L
NO STUFF
1
C9429
0.1UF
10%
16V
2
X5R-CERM
0201
0603
R9401
12
1 2
5%
1/20W
MF
201
1 2
402
CERM-X5R
10%
6.3V
PP3V3RHV_SW_DPAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
2
HOT_PLUG_DETECT
4
CONFIG1
6
CONFIG2
GND
10
ML_LANE3P
12
ML_LANE3N
GND
16
AUX_CHP
18
AUX_CHN
20
DP_PWR
CRITICAL
D9425
POWERDI-123
DFLS1100
CRITICAL
Q9425
SI8409DB
4
SGD
1
0.47UF
DisplayPort/T29 A Connector
CRITICAL
J9400
MDP-K21-K78
F-RT-TH
ML_LANE0P
ML_LANE0N
ML_LANE1P
ML_LANE1N
ML_LANE2P
ML_LANE2N
SHIELD PINS
28
BGA
12
R9418
1 2
1/20W
GND
GND
GND
RETURN
2 3
1K
5%
MF
201
21222324252627
3.3V Always
1
R9426
1K
5%
1/20W
MF
201
2
Q9426
MMDT3946XG
DPAPWRSW_HV_DET
GND_DPACONN_1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
1
3
5
713
9
11
814
15
17
19
GND_DPACONN_19
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
SOT363
631
GND_VOID=TRUE
DP Dir
GND_DPACONN_7
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
36 64 65
1
R9430
4.7K
5%
1/20W
MF
201
2
2
GND_VOID=TRUE
T29_A_HV_EN
5
DPAPWRSW_NPN_E
C9405
0.1UF
T29 Dir
Port A 3.3V Power Switch
CRITICAL
U9480
TPS2065DBV
SOT23
1
C9486
10UF
20%
6.3V
2
X5R
603
4
R9433
220
5%
1/20W
MF
201
T29DPA_ML_P<0>
72
T29DPA_ML_N<0>
72
R9405
1 2
1 2
10%
6.3V
X5R
201
GND_DPA1_R
T29: TX_0
C9406
0.1UF
1 2
GND_DPA7_R
10%
6.3V
X5R
201
T29: LSX_R2P/P2R (P/N)
T29DPA_ML_P<2>
72
T29DPA_ML_N<2>
72
T29: TX_1
L9408
FERR-120-OHM-3A
1 2
0603
R9408
12
1 2
5%
1/20W
MF
201
1
2
Q9430
SOT563
1
2
12
5%
1/20W
MF
201
1 2
1
OUT IN
3
OC*
C9485
0.1UF
10%
16V
X5R-CERM
0201
5
1
R9432
10K
5%
1/20W
MF
201
2
R9406
12
5%
1/20W
MF
201
3
D
SG
4
5
4
EN
GND
2
1
C9481
0.1UF
10%
16V
2
X5R-CERM
0201
DPAPWRSW_P3V3_ON
6
D
Q9430
SSM6N37FEAPESSM6N37FEAPE
SOT563
2
S G
1
T29_A_HV_EN
Circuit threshold range: 2.877-2.941V (2.903V nominal)
GND_VOID=TRUE
GND_VOID=TRUE
(Both C’s)
C9470
0.47UF
C9471
0.47UF
GND_VOID=TRUE
1
R9470
470K
5%
1/20W
MF
201
2
GND_VOID=TRUE
GND_VOID=TRUE
(Both C’s)
C9472
0.47UF
C9473
0.47UF
GND_VOID=TRUE
1
R9472
470K
5%
1/20W
MF
201
2
470k R’s for ESD protection
on AC-coupled signals.
CRITICAL
1
C9480
22UF
20%
6.3V
2
X5R-CERM-1
603
DPAPWRSW_ON_C
1 2
20%
CERM-X5R-1
1 2
20%
CERM-X5R-1
GND_VOID=TRUE
1
R9471
470K
5%
1/20W
MF
201
2
1 2
20%
CERM-X5R-1
1 2
20%
CERM-X5R-1
GND_VOID=TRUE
1
R9473
470K
5%
1/20W
MF
201
2
DP_PWR must be S4/S5 to support
wake from T29 devices.
=PP3V3_S4_DPAPWRSW
=DPAPWRSW_EN
CRITICAL
1
C9487
100UF
20%
6.3V
2
POLY-TANT
CASE-B2-SM
T29_A_BIAS
8
64 65
CRITICAL
5
OUT
U9435
C9436
R9437
36 64 65
4V
201
4V
201
4V
201
4V
201
1UF
10%
10V
X5R
402
1/20W
1
2
1
82
5%
MF
201
2
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>
T29DPA_ML_P<1>
T29DPA_ML_N<1>
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>
ZXRE060A
SOT353
4
FB
PGND
1
DPAPWR_FB_DIV
7
62
IN
D
GND
R9436
2
NO STUFF
24.9K
1/20W
201
R9435
100K
1
1%
MF
2
IN
IN
IN
BI
IN
IN
1
C9435
2
1/20W
201
64 72
64 72
64 72
64 72
64 72
0.1UF
10%
16V
X5R-CERM
0201
1
1%
MF
2
64 72
C
B
3
IN
T29DPA_HPD
64
A
8 7 5 4 2 1
OUT
64
OUT
64
OUT
T29DPA_CONFIG1_RC
T29DPA_CONFIG2_RC
R9452
1/20W
SIZE
A
D
DP Source must pull
down HPD input with
greater than or equal
10%
16V
X7R
201
to 100K (DPv1.1a).
Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V
1
1
R9451
1M
1M
5%
5%
1/20W
MF
MF
201
201
2
2
C9494
330PF
1
1
C9495
10%
16V
X7R
201
330PF
2
2
1
R9441
100K
5%
1/20W
MF
201
2
SYNC_MASTER=K78_MLB
PAGE TITLE
DisplayPort/T29 A Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/07/2010
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
94 OF 109
SHEET
65 OF 75
36
Page 66
www.laptopblue.vn
PPBUS S0 LCDBkLT FET
MOSFET
CHANNEL
1 2 5 6
RDS(ON)
LOADING
PPBUS_SW_LCDBKLT_PWR
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
7
=PP3V3_S0_BKL_VDDIO
CRITICAL
Q9706
FDC638APZ_SBMS001
F9700
3AMP-32V-467
D
=PPBUS_S0_LCDBKLT
7
1 2
8
IN
603-HF
BOTTOM
LCD_BKLT_EN
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
R9788
301K
1%
1/20W
MF
201
2
LCDBKLT_EN_DIV
1
R9789
147K
1%
1/20W
MF
201
2
LCDBKLT_EN_L
Q9707
SSM6N15FEAPE
SOT563
5
3
D
SG
4
C9782
0.1UF
LCDBKLT_DISABLE
Q9707
SSM6N15FEAPE
1
10%
16V
2
X5R
402
SOT563
SSOT6-HF
4
3
6
D
FDC638APZ
P-TYPE
43 mOhm @4.5V
0.65 A (EDP)
66
8
THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
AND PPBUS_SW_BKL
ON THE SENSOR PAGE
=PP5V_S0_BKL
7
=PPBUS_SW_BKL
8
PLACE_NEAR=L9701.1:3mm
CRITICAL
C9712
10UF
10%
25V
X5R
805
1
1
C9713
0.1UF
10%
25V
2
2
X5R
402
PLACE_NEAR=L9701.1:3mm
PLACE_NEAR=U9701.D1:5mm
PLACE_NEAR=U9701.C4:4mm
C9711
0.1UF
6.3V
*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
CRITICAL
L9701
15UH-2.8A
1 2
PIMB053T-SM
PLACE_NEAR=U9701.D1:3mm
1
C9710
1UF
10%
25V
X5R
603-1
1
10%
2
X5R
201
1
C9714
0.01UF
10%
10V
2
2
X5R
201
PPBUS_SW_LCDBKLT_PWR_SW
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
SWITCH_NODE=TRUE
DIDT=TRUE
345678
PPVOUT_SW_LCDBKLT_FB
VOLTAGE=50V
MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM
PLACE_NEAR=L9701.2:3mm
CRITICAL
D9701
SOD-123
1 2
RB160M-60G
XW9720
SM
1 2
PLACE_NEAR=C9797.1:5mm
C
2
SG
BKLT_PLT_RST_L
25
IN
1
2 1
PLACE_NEAR=U9701.A5:3mm
1
C9796
2
220PF
10%
50V
X7R-CERM
402
CRITICAL
1
C9797
10UF
10%
50V
2
X5R
1210-1
PLACE_NEAR=D9701.2:3mm
CRITICAL
1
C9799
10UF
10%
50V
2
X5R
1210-1
PLACE_NEAR=D9701.2:5mm
PPVOUT_SW_LCDBKLT
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
D
63
6
C
C4C1D1
VDDIO
BKL_VSYNC_R
R9741
10K
200K
1/20W
201
1 2
5%
1/20W
MF
201
1
R9715
1%
100K
MF
1%
1/20W
MF
201
2
PLACE_SIDE=BOTTOM
see spec for others
1
R9755
10K
5%
1/20W
MF
201
2
TP_BKL_FAULT
Fpwm=9.62kHz
R9716
90.9K
1/20W
R9753
0
=I2C_BKL_1_SCL
44
IN
=I2C_BKL_1_SDA BKL_SDA
44
BI
Addr: 0x58(Wr)/0x59(Rd)
PPBUS_SW_LCDBKLT_PWR
66
8
B
LCD_BKLT_PWM
8
IN
R9757
1 2
1/20W
R9704
1 2
1/20W
1 2
5%
1/20W
0
5%
MF
201
MF
201
1 2
R9731
33
5%
1
MF
201
2
C9704
33PF
5%
25V
NP0-C0G
201
BKL_FLTR
BKL_ISET
BKL_FSET
BKL_SCL
BKL_PWM
BKL_EN
I_LED=20.3mA
1
1
R9714
18.2K
1%
1%
1/20W
MF
MF
201
201
2
2
GND_BKL_SGND
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
I_LED=369/Riset
(EEPROM should set EN_I_RES=1)
D2
VSYNC
C2
FILTER
B3
ISET
B4
FSET
D3
SCLK
D4
SDA
A4
PWM
A3
EN
C3
FAULT
VLDO
U9701
25-BUMP-MICRO
LP8550
GND_S
GND_L
E4B5A1
VIN
B1
SW_0
B2
SW_1
A5
FB
E5
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
GND_SW
GND_SW
A2
XW9710
SM
1 2
BKL_ISEN1
D5
BKL_ISEN2
C5
BKL_ISEN3
E3
BKL_ISEN4
E2
BKL_ISEN5
E1
BKL_ISEN6
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)
PLACE_NEAR=U9701.E5:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.D5:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.C5:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.E3:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.E2:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.E1:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BKLT:PROD
R9717
0
1 2
5%
1/16W
MF-LF
402
BKLT:PROD
R9718
0
1 2
5%
1/16W
MF-LF
402
BKLT:PROD
R9719
0
1 2
5%
1/16W
MF-LF
402
BKLT:PROD
R9720
0
1 2
5%
1/16W
MF-LF
402
BKLT:PROD
R9721
0
1 2
5%
1/16W
MF-LF
402
BKLT:PROD
R9722
0
1 2
5%
1/16W
MF-LF
402
LED_RETURN_1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_4
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
63
6
OUT
63
6
OUT
B
63
6
OUT
63
6
OUT
63
6
OUT
63
6
OUT
A
PART NUMBER
103S0198
103S0198
QTY
3
3
DESCRIPTION
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
8 7 5 4 2 1
REFERENCE DES
R9717,R9718,R9719
R9720,R9721,R9722
CRITICAL
BOM OPTION
BKLT:ENG
BKLT:ENG
10.2 ohm resistors for current
measurement on LED strings.
36
SYNC_MASTER=K78_MLB
PAGE TITLE
LCD Backlight Driver
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/16/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
97 OF 109
SHEET
66 OF 75
SIZE
A
D
Page 67
CPU Signal Constraints
*
*
*
*
*
*
*
*
*
ALLOW ROUTE
ON LAYER?
=50_OHM_SE
=27P4_OHM_SE
LINE-TO-LINE SPACING
LAYER
CPU_50S
CPU_55S
CPU_27P4S
CPU_XDP_BPM
CPU_XDP_BPM
NOTE: CPU_XDP_BPM physical constraint is to prevent routing on outer layers.
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
D
SPACING_RULE_SET
CPU_AGTL
CPU_8MIL
CPU_COMP
CPU_ITP
CPU_VCCSENSE
Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7
TOP,BOTTOM
LAYER
=STANDARD
8 MIL
20 MIL
=2:1_SPACING
25 MIL
MINIMUM LINE WIDTH
=27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
SPACING_RULE_SET
PCI-Express
PCIE_85D
CLK_PCIE_90D
SPACING_RULE_SET
PCIE
CLK_PCIE
LAYER
LAYER
ALLOW ROUTE
ON LAYER?
*
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
*
=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
LINE-TO-LINE SPACING
*
*
=3X_DIELECTRIC
20 MIL
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
SPACING_RULE_SET
C
SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7
=50_OHM_SE =50_OHM_SE=50_OHM_SE
100 MIL100 MIL100 MIL
CPU_AGTL
www.laptopblue.vn
CPU Net Properties
ELECTRICAL_CONSTRAINT_SET
DMI_S2N
DMI_S2N
DMI_N2S
DMI_N2S
FDI_DATA PCIEPCIE_85D
CPU_PECI
PM_MEM_PWRGD CPU_AGTL
CPU_SM_RCOMP
CPU_SM_RCOMP CPU_COMP
CPU_SM_RCOMP
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M
DMI_CLK100M
DPLL_REF_CLK120M
DPLL_REF_CLK120M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
PHYSICAL
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50SPM_SYNC
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CLK_PCIE_90D
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D
CLK_PCIE_90D CLK_PCIE
CPU_27P4S
CPU_27P4S
NET_TYPE
SPACING
PCIE
PCIE
PCIE
PCIE
PCIEPCIE_85DFDI_DATA
CPU_AGTL
CPU_AGTL
CPU_AGTL
PCIE
CPU_AGTL
CPU_ITP
CPU_ITP
CPU_ITPCPU_50S
CPU_AGTL
CPU_AGTL
CPU_COMP
CPU_COMP
CPU_ITP
CPU_AGTLCPU_CATERR_L
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CLK_PCIE
CLK_PCIECLK_PCIE_90D
CLK_PCIECLK_PCIE_90D
CLK_PCIECLK_PCIE_90D
CLK_PCIE
CPU_COMP
CPU_COMP
DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>
FDI_FSYNC<1..0>
FDI_LSYNC<1..0>
FDI_INT
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
CPU_CFG<11..0>
CPU_CATERR_L
CPU_VCCIO_SEL
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
DPLL_REF_CLKP
DPLL_REF_CLKN
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
EDP_COMP
CPU_PEG_COMP
=STANDARD=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE
100 MIL
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
LAYER
PCIE
TOP,BOTTOM
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
7 MIL 7 MIL
=STANDARD
=CPU_50S=CPU_50S=CPU_50S =CPU_50S =CPU_50S=CPU_50S
LINE-TO-LINE SPACING
=2x_DIELECTRIC
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4X_DIELECTRIC
WEIGHT
WEIGHT
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
345678
9
17
9
17
9
17
9
17
17
9
17
9
17
9
17
9
17
9
41 19 10
17 10
26 17 10
25 23 10
10 23
23 10
10
10
10
9
23
10
12
42 10 57
19 10 23
10 19
10 16
10 16
16 10
16 10
10 16
10 16
16 23
23 16
23
23
9
9
2 1
D
C
XDP_TDO CPU_ITPCPU_50S
XDP_TCK CPU_ITPCPU_50S
XDP_TRST_L
XDP_BPM_L
XDP_BPM_R_L
(FSB_CPURST_L)
B
CPU_VCCAXG_SENSE
CPU_VCCAXG_SENSE
CPU_VCCSENSE
CPU_VCCAXG_SENSE
CPU_VCCAXG_SENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_SVIDALERT_L
CPU_SVIDSCLK CPU_COMP
CPU_SVIDSOUT CPU_COMP
CPU_XDP_BPM
CPU_50S CPU_ITP
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_50S
CPU_50S
CPU_50S
CPU_ITPCPU_50SXDP_TDI
CPU_ITPXDP_TMS CPU_50S
CPU_ITPCPU_50S
CPU_ITP
CPU_ITPCPU_50S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSECPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_COMP
A
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
8 7 5 4 2 1
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L<7..0>
CPU_CFG<15..12>
XDP_CPURST_L
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>
36
10 23
10 23
9
23
12
12
9
9
9
9
8
8
8
8
23 10
23 10
23 10
23 10
23
CPU_VCCSA_VID<0>
57 12
57 12
59 12
59 12
57 12
57 12
57 12
57 12
57 12
CPU_VCCSA_VID<1>
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
CPU Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
100 OF 109
SHEET
67 OF 75
SIZE
B
A
D
Page 68
Memory Bus Constraints
LAYER
MEM_37S
MEM_40S
MEM_55S
MEM_72D
MEM_50S
D
MEM_85D
MEM_50S
MEM_85D
TOP,BOTTOM
TOP,BOTTOM
ISL3,ISL4,ISL9,ISL10
ISL3,ISL4,ISL9,ISL10
ALLOW ROUTE
ON LAYER?
*
*
*
*
=37_OHM_SE =37_OHM_SE=37_OHM_SE
=40_OHM_SE =40_OHM_SE
=72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF
Y
Y
Y
Y
MINIMUM LINE WIDTH
=37_OHM_SE
=85_OHM_DIFF =85_OHM_DIFF
=50_OHM_SE =50_OHM_SE
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
MINIMUM NECK WIDTH
=40_OHM_SE=40_OHM_SE
=50_OHM_SE=50_OHM_SE
Memory to Power Spacing
NET_SPACING_TYPE1 NET_SPACING_TYPE2
C
Spacing Rule Sets
SPACING_RULE_SET
MEM_CLK2CLK
MEM_CTRL2CTRL
MEM_CMD2CTRL
MEM_CMD2CMD
MEM_DATA2DATA
MEM_DQS2DQS
MEM_MEM2OTHERMEM
MEM_2PWR
MEM_2GND
MEM_2OTHER
LAYER
Memory Bus Spacing Group Assignments
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK MEM_CLK
MEM_CLK
B
MEM_CLK
MEM_CLK MEM_DQS
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CTRL
MEM_CTRL MEM_CTRL
MEM_CTRL
MEM_CTRL MEM_DATA
MEM_CTRL
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_DQS MEM_CLK
MEM_DQS
MEM_DQS MEM_CMD
MEM_DQS
DDR3:
A
Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines
per Huron River SFF DG rev1.0 (#438297).
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQ to DQS matching per byte lane should be within 0.127mm.
DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm.
SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5
LINE-TO-LINE SPACING
*
*
*
*
*
*
* ?
*
*
0.6 MM
0.2 MM
0.2 MM
0.2 MM
0.14 MM
0.4 MM
0.4 MM
=PWR_P2MM
=GND_P2MM
0.6 MM
AREA_TYPE
*
MEM_CTRL
MEM_CMDMEM_CLK
MEM_DATA
*
*
*
*
AREA_TYPE
MEM_CLK
MEM_CMD
MEM_DQS
*
*
*
*
*
AREA_TYPE
*
MEM_CTRL
MEM_DATA
MEM_DQSMEM_DQS
*
*
*
* *
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
SPACING_RULE_SET
SPACING_RULE_SET
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK2CLK
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_MEM2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS2DQS
MEM_CLK
MEM_CTRL MEM_2PWR
MEM_CMD MEM_PWR
MEM_DATA MEM_2PWR
MEM_DQS
Memory to GND Spacing
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CTRL MEM_2GND
MEM_CMD
MEM_DATA MEM_2GND
MEM_DQS
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD MEM_DQS
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_DATA
MEM_DATA
MEM_DATA
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
Need to support MEM_*-style wildcards!
8 7 5 4 2 1
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE
=50_OHM_SE
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
=50_OHM_SE
MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR
GND
GND
GND
GND
GND
MEM_CLK
MEM_CTRL
MEM_CMDMEM_CMD
MEM_DATA
MEM_CLK
MEM_CTRLMEM_DATA
MEM_CMD
MEM_DATAMEM_DATA
MEM_DQS
*
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
=STANDARD =STANDARD
=STANDARD =STANDARD
=STANDARD
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
*
*
*
*
AREA_TYPE
**
**
**
**
SPACING_RULE_SET
SPACING_RULE_SET
SPACING_RULE_SET
MEM_MEM2OTHERMEM
MEM_MEM2OTHERMEM
MEM_MEM2OTHERMEM
SPACING_RULE_SET
MEM_MEM2OTHERMEM
MEM_MEM2OTHERMEM
MEM_MEM2OTHERMEM
MEM_MEM2OTHERMEM
SPACING_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
MEM_2PWR
MEM_2PWR
MEM_2PWR
MEM_2GND
MEM_2GND
MEM_2GND
MEM_CMD2CTRL
MEM_CMD2CMD
MEM_DATA2DATA
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
www.laptopblue.vn
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET
MEM_A_CLK
MEM_A_CLK
MEM_A_CTRL
MEM_A_CTRL
MEM_A_CTRL
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1 MEM_50S
MEM_A_DQ_BYTE2 MEM_50S
MEM_A_DQ_BYTE3 MEM_50S
MEM_A_DQ_BYTE4 MEM_50S
MEM_A_DQ_BYTE5 MEM_50S
MEM_A_DQ_BYTE6 MEM_50S
MEM_A_DQ_BYTE7 MEM_50S
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_B_CLK
MEM_B_CLK
MEM_B_CTRL
MEM_B_CTRL
MEM_B_CTRL
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
PHYSICAL
MEM_72D
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_50S
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_72D
MEM_72D
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_55S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_85D
MEM_85D MEM_DQS
MEM_85D MEM_DQS
MEM_85D
MEM_85D
MEM_85D MEM_DQS
MEM_85D MEM_DQS
MEM_85D
MEM_85D
MEM_85D MEM_DQS
=STANDARD=STANDARD
=STANDARD
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
NET_TYPE
SPACING
MEM_CLKMEM_72D
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DQS
MEM_DQSMEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMDMEM_55S
MEM_CMDMEM_55S
MEM_CMD
MEM_CMD
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DQS
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQS
MEM_DQSMEM_85D
MEM_DQS
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQS
MEM_DQSMEM_85D
MEM_DQS
MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR
345678
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
PP1V5_S3RS0
PP1V5_S3
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFDQ_A
36
2 1
32 28 27 11
8
32 28 27 11
8
32 28 27 11
8
32 28 27 11
8
32 28 27 11
8
32 28 27 11
8
32 28 27 11
32 28 27 11
32 28 27 11
32 28 27 11
27 11
27 11
27 11
27 11
28 11
28 11
28 11
28 11
27 11
27 11
27 11
27 11
27 11
27 11
27 11
27 11
28 11
28 11
28 11
28 11
28 11
28 11
28 11
28 11
32 30 29 11
8
32 30 29 11
8
32 30 29 11
8
32 30 29 11
8
32 30 29 11
8
32 30 29 11
8
32 30 29 11
32 30 29 11
32 30 29 11
32 30 29 11
29 11
29 11
29 11
29 11
30 11
30 11
30 11
30 11
29 11
29 11
29 11
29 11
29 11
29 11
29 11
29 11
30 11
30 11
30 11
30 11
30 11
30 11
30 11
30 11
7
7
31 30 29 28 27
31 30 29 28 27
9
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
Memory Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
101 OF 109
SHEET
68 OF 75
SIZE
D
C
B
A
D
Page 69
Digital Video Signal Constraints
LAYER
DP_85D
LVDS_90D
SPACING_RULE_SET
DISPLAYPORT
LVDS
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
D
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
LAYER
ALLOW ROUTE
ON LAYER?
*
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF
*
=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
LINE-TO-LINE SPACING
*
*
MINIMUM LINE WIDTH
=3x_DIELECTRIC
=3x_DIELECTRIC
SATA Interface Constraints
LAYER
SATA_90D
SPACING_RULE_SET
SATA
SATA_ICOMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
LAYER
ALLOW ROUTE
ON LAYER?
*
=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
LINE-TO-LINE SPACING
*
*
MINIMUM LINE WIDTH
=4x_DIELECTRIC
8 MIL
USB 2.0 Interface Constraints
LAYER
PCH_USB_RBIAS
USB_85D
SPACING_RULE_SET
C
USB
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
LAYER
ALLOW ROUTE
ON LAYER?
*
*
=STANDARD
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
LINE-TO-LINE SPACING
*
MINIMUM LINE WIDTH
8 MIL 8 MIL
=2x_DIELECTRIC
WEIGHT
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
SPACING_RULE_SET
DISPLAYPORT
LVDS
MINIMUM NECK WIDTH
SPACING_RULE_SET
SATA
MINIMUM NECK WIDTH
SPACING_RULE_SET
USB
MAXIMUM NECK LENGTH
LAYER
TOP,BOTTOM
TOP,BOTTOM
MAXIMUM NECK LENGTH
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
=STANDARD =STANDARD =STANDARD
LAYER
TOP,BOTTOM
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4x_DIELECTRIC
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=3x_DIELECTRIC
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4x_DIELECTRIC
WEIGHT
WEIGHT
WEIGHT
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DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
PCH Net Properties
ELECTRICAL_CONSTRAINT_SET
DP_ML
DP_ML
DP_EXTA_AUXCH
DP_EXTA_AUXCH
LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
SATA_HDD_D2R SATA_90D
NET_TYPE
PHYSICAL
DP_85D
DP_85D
DP_85D
DP_85D
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
LVDS_90D LVDS
SATA_90D SATA
SATA_90D
SATA_90DSATA_HDD_R2D
SATA_90DSATA_HDD_R2D
SATA_90D SATASATA_HDD_D2R
SATA_90D SATA
SATA_90D
SATA_90D SATA
SATA_90D SATA
SATA_90D SATASATA_ODD_R2D
SATA_90D SATASATA_ODD_R2D
SATA_90D SATASATA_ODD_D2R
SATA_90D SATASATA_ODD_D2R
SATA_90D SATA
SATA_90D SATA
SATA_90D SATA
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
SATA
SATA
SATA
SATA
SATA
SATASATA_90D
SPACING
DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_DATA_P<3..0>
LVDS_IG_B_DATA_N<3..0>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_HDD_R2D_RC_P
SATA_HDD_R2D_RC_N
SATA_HDD_D2R_RC_P
SATA_HDD_D2R_RC_N
345678
8
8
8
8
8
8
8
8
8
8
38 16
38 16
38
6
38
6
38 16
38 16
38
6
38
6
16
8
16
8
16
8
16
8
2 1
D
C
PCH_SATA_ICOMP
USB_HUB1_UP
USB_HUB2_UP
USB_EXTA
USB_EXTA
USB_EXTB
USB_EXTC
USB_EXTD
USB_EXTD
USB_CAMERA
USB_CAMERA
B
USB_BT
USB_BT
USB_TPAD
USB_IR
USB_SDCARD
USB_BRCRYPT
PCH_USB_RBIAS
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
LPC_CLK33M
GFX_CLK_DPLLSS
GFX_CLK_DPLLSS
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
PCH_USB_RBIAS
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CPU_50S
CPU_50S
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
SATA_ICOMP
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
PCH_SATAICOMP
USB_HUB1_UP_P
USB_HUB1_UP_N
USB_HUB2_UP_P
USB_HUB2_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
USB_EXTC_P
USB_EXTC_N
USB_EXTD_P
USB_EXTD_N
USB_T29A_P
USB_T29A_N
T29_A_RSVD_P
T29_A_RSVD_N
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_SDCARD_P
USB_SDCARD_N
USB_BRCRYPT_P
USB_BRCRYPT_N
PCH_USB_RBIAS
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
FSB_CLK133M_PCH_P
FSB_CLK133M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
GFX_CLK120M_DPLLSS_P
GFX_CLK120M_DPLLSS_N
16
24 18
24 18
24 18
24 18
39 24
39 24
40 24
6
40 24
6
24
8
24
8
64
8
64
8
40 18
6
40 18
6
37 24
6
37 24
6
49
49
33 24
33 24
18
25 16
25 16
8
8
25 16
25 16
25 16
25 16
25 16
25 16
B
A
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
PCH Constraints 1
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 5 4 2 1
36
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
102 OF 109
SHEET
69 OF 75
SIZE
A
D
Page 70
LPC Bus Constraints
*
*
*
*
*
*
ALLOW ROUTE
ON LAYER?
=50_OHM_SE
LINE-TO-LINE SPACING
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
LAYER
LPC_50S
CLK_LPC_50S
SPACING_RULE_SET
LPC
CLK_LPC
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
D
SMBus Interface Constraints
SMB_50S
SPACING_RULE_SET
SMB
LAYER
LAYER
LAYER
MINIMUM LINE WIDTH
6 MIL
8 MIL
MINIMUM LINE WIDTH
=2x_DIELECTRIC
HD Audio Interface Constraints
*
*
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
LAYER
HDA_50S
SPACING_RULE_SET
HDA
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
LAYER
MINIMUM LINE WIDTH
=2x_DIELECTRIC
SIO Signal Constraints
CLK_SLOW_55S
LAYER
ALLOW ROUTE
ON LAYER?
*
MINIMUM LINE WIDTH
C
*
*
*
*
*
*
*
*
*
*
*
*
LINE-TO-LINE SPACING
8 MIL
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
MINIMUM LINE WIDTH
8 MIL
MINIMUM LINE WIDTH
=3x_DIELECTRIC
MINIMUM LINE WIDTH
=3X_DIELECTRIC
20 MIL
MINIMUM LINE WIDTH
=2x_DIELECTRIC
=5x_DIELECTRIC
SPACING_RULE_SET
CLK_SLOW
LAYER
SPI Interface Constraints
LAYER
SPI_55S
SPACING_RULE_SET
SPI
LAYER
DisplayPort Signal Constraints
LAYER
DP_85D
B
SPACING_RULE_SET
DISPLAYPORT
LAYER
PCI-Express Signal Constraints
LAYER
PCIE_85D
CLK_PCIE_90D
SPACING_RULE_SET
PCIE
CLK_PCIE
LAYER
System Clock Signal Constraints
LAYER
CLK_SLOW_55S
CLK_25M_55S
A
SPACING_RULE_SET
CLK_SLOW
CLK_25M
LAYER
8 7 5 4 2 1
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
=55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?*
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
WEIGHT
WEIGHT
WEIGHT
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
DISPLAYPORT
MINIMUM NECK WIDTH
SPACING_RULE_SET
PCIE
MINIMUM NECK WIDTH
=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE
NOTE: 25MHz system clocks very sensitive to noise.
MAXIMUM NECK LENGTH
=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE
=50_OHM_SE=50_OHM_SE=50_OHM_SE
MAXIMUM NECK LENGTH
=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE
MAXIMUM NECK LENGTH
=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4X_DIELECTRIC
DIFFPAIR PRIMARY GAP
WEIGHT
WEIGHT
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PCH Net Properties
ELECTRICAL_CONSTRAINT_SET
LPC_AD
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M
LPC_CLK33M
LPC_CLK33M
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_PCH_1_CLK
SMBUS_PCH_1_DATA
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
PM_SUS_CLK
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS0
PCIE_ENET_R2D
PCIE_ENET_D2R
PCIE_AP_R2D
PCIE_AP_D2R
PCIE_FW_R2D
PCIE_FW_D2R
PCIE_AP_D2R
PCIE_AP_R2D
PCIE_CLK100M_ENET
MCP_PE1_REFCLK
MCP_PE2_REFCLK
NET_TYPE
PHYSICAL
LPC_50S
LPC_50S
LPC_50S
CLK_LPC_50S
CLK_LPC_50S
CLK_LPC_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
SPACING
LPC
LPC
LPC
CLK_LPC
CLK_LPC
CLK_LPC
SMB
SMB
SMB
SMB
SMB
SMB
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
CLK_SLOWCLK_SLOW_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIE
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
CLK_PCIE
CLK_PCIE
CLK_PCIECLK_PCIE_90D
CLK_PCIECLK_PCIE_90D
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R
PM_CLK32K_SUSCLK
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_MLB_CS_L
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
CONN_PCIE_AP_D2R_P
CONN_PCIE_AP_D2R_N
CONN_PCIE_AP_R2D_P
CONN_PCIE_AP_R2D_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>
TP_PCH_VSS_NCTF<7>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<22>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
=STANDARD=STANDARD
=STANDARD=STANDARD
=STANDARD=STANDARD
=STANDARD=STANDARD
=STANDARD
=STANDARD=STANDARD
=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF
=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF
=STANDARD=STANDARD
=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
345678
Chipset Net Properties
43 41 16
6
43 41 16
6
25
25 18
41 25
43 25
6
44 16
44 16
44 16
44 16
44 16
44 16
40 16
6
16
40 16
6
16
16
40 16
6
40 16
6
40 16
6
16
43 16
43
43 16
43
43 16
43 16
43
50 43
50 43
50 43
50 43
37
6
37
6
37 16
37 16
37 16
6
37 16
6
16
8
16
8
37 16
6
37 16
6
16
8
16
8
6
6
6
70
6
70
6
6
6
6
6
6
6
6
6
6
ELECTRICAL_CONSTRAINT_SET
DP_EXTA_ML
DP_EXTA_ML
DP_EXTA_AUXCH
DP_EXTA_AUXCH
DP_INT_ML
DP_INT_ML
DP_INT_AUXCH
DP_INT_AUXCH
PCIE_PEG_D2R_LANE3
PCIE_PEG_D2R_LANE2
PCIE_PEG_D2R_LANE1
PCIE_PEG_D2R_LANE0
PCIE_PEG_D2R_LANE3
PCIE_PEG_D2R_LANE2
PCIE_PEG_D2R_LANE1
PCIE_PEG_D2R_LANE0
PCIE_PEG_R2D_LANE3
PCIE_PEG_R2D_LANE2
PCIE_PEG_R2D_LANE1
PCIE_PEG_R2D_LANE0
PCIE_PEG_R2D_LANE3
PCIE_PEG_R2D_LANE2
PCIE_PEG_R2D_LANE1
PCIE_PEG_R2D_LANE0
PCIE_CLK100M_T29
PCIE_CLK100M_T29
Clock Net Properties
ELECTRICAL_CONSTRAINT_SET
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_T29
2 1
NET_TYPE
PHYSICAL
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
PCIE_85D
PCIE_85D
PCIE_85D PCIE
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D
CLK_PCIE_90D
CLK_PCIE_90D
PHYSICAL
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
NET_TYPE
SPACING
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
PCIE
PCIE
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIEPCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
CLK_PCIE
CLK_PCIE
SPACING
CLK_SLOWCLK_SLOW_55S
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
PCH Constraints 2
Apple Inc.
R
DP_EXTA_ML_C_P<3..0>
DP_EXTA_ML_C_N<3..0>
DP_EXTA_ML_P<3..0>
DP_EXTA_ML_N<3..0>
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
DP_INT_ML_C_P<3..0>
DP_INT_ML_C_N<3..0>
DP_INT_ML_P<3..0>
DP_INT_ML_N<3..0>
DP_INT_ML_F_P<3..0>
DP_INT_ML_F_N<3..0>
DP_INT_AUX_CH_C_P
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_P
DP_INT_AUX_CH_N
PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_D2R_P<3>
PCIE_T29_D2R_P<2>
PCIE_T29_D2R_P<1>
PCIE_T29_D2R_P<0>
PCIE_T29_D2R_N<3>
PCIE_T29_D2R_N<2>
PCIE_T29_D2R_N<1>
PCIE_T29_D2R_N<0>
PCIE_T29_R2D_P<3>
PCIE_T29_R2D_P<2>
PCIE_T29_R2D_P<1>
PCIE_T29_R2D_P<0>
PCIE_T29_R2D_N<3>
PCIE_T29_R2D_N<2>
PCIE_T29_R2D_N<1>
PCIE_T29_R2D_N<0>
PCIE_T29_D2R_C_P<3..0>
PCIE_T29_D2R_C_N<3..0>
PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_T29
SYSCLK_CLK25M_T29_R
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
103 OF 109
SHEET
70 OF 75
64
8
64
8
64
64
64
8
64
8
64
64
D
63
63
63
9
63
9
63
6
63
6
63
6
63
6
63
9
63
9
34
8
34
8
34
8
8
34
8
8
34
8
34
8
34
8
34
8
34
34
34
34
34
34
C
34
34
34
34
34 16
34 16
25 16
25 16
16
34 25
34
B
A
SIZE
D
36
Page 71
CAESAR IV (Ethernet) Constraints
ENET_50S
SPACING_RULE_SET
ENET_3X
SOURCE: Broadcom 5764-DS04-RDS Page 38
SPACING_RULE_SET
D
ENET_CR_DATA
LAYER
LAYER
LAYER
*
*
*
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
LINE-TO-LINE SPACING
CAESAR IV (Ethernet PHY) Constraints
*
*
ALLOW ROUTE
ON LAYER?
LINE-TO-LINE SPACING
LAYER
ENET_100D
SPACING_RULE_SET
ENET_MDI
SOURCE: Broadcom 5764-DS04-RDS Page 38
LAYER
MINIMUM LINE WIDTH
=50_OHM_SE
=3:1_SPACING
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF
0.6 MM
=50_OHM_SE =50_OHM_SE=50_OHM_SE
WEIGHT
WEIGHT
8MIL
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
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DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
Ethernet Net Properties
ELECTRICAL_CONSTRAINT_SET
CR_DATA
I166
CR_DATA
I167
CR_CLK
I168
CR_DATA
I169
CR_DATA
I170
CR_CLK
I171
NET_TYPE
PHYSICAL
ENET_50S
ENET_50S
ENET_50S
ENET_100D
ENET_100D
ENET_50S ENET_CR_DATA
ENET_50S ENET_CR_DATA
ENET_50S ENET_CR_DATA
ENET_50S ENET_CR_DATA
ENET_50S ENET_CR_DATA
ENET_50S ENET_CR_DATA
SPACING
ENET_3X
ENET_3X
ENET_3X
ENET_MDIENET_MDI
ENET_MDI
BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO
ENET_RESET_L
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
ENET_CR_DATA<7..0>
ENET_CR_CMD
ENET_CR_CLK
SDCONN_DATA<7..0>
SDCONN_CMD
SDCONN_CLK
345678
2 1
D
C
FireWire Interface Constraints
LAYER
FW_110D
SPACING_RULE_SET
FW_TP
*
LAYER
*
B
ALLOW ROUTE
ON LAYER?
=110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF
LINE-TO-LINE SPACING
=3:1_SPACING
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
FireWire Net Properties
ELECTRICAL_CONSTRAINT_SET
FW_P0_TPA
I158
FW_P0_TPA
I159
FW_P0_TPB
I160
FW_P0_TPB
I161
FW_P1_TPA
I162
FW_P1_TPA
I163
FW_P1_TPB
I164
FW_P1_TPB
I165
Port 2 Not Used
PHYSICAL
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
NET_TYPE
SPACING
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
C
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
Ethernet/FW Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
104 OF 109
SHEET
71 OF 75
SIZE
A
D
Page 72
DisplayPort Signal Constraints
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
T29 I2C Signal Constraints
T29_I2C_55S
SPACING_RULE_SET
T29_I2C =2x_DIELECTRIC
D
T29 SPI Signal Constraints
T29_SPI_55S
SPACING_RULE_SET
T29_SPI =2x_DIELECTRIC
LAYER
LAYER
LAYER
LAYER
*
*
*
*
ALLOW ROUTE
ON LAYER?
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
LINE-TO-LINE SPACING
ALLOW ROUTE
ON LAYER?
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
LINE-TO-LINE SPACING
DP/T29 Connector Signal Constraints
LAYER
T29DP_80D
T29DP_100D
SPACING_RULE_SET
T29DP
SOURCE: Bill Cornelius’s T29 Routing Notes
LAYER
ALLOW ROUTE
ON LAYER?
*
=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF
*
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
LINE-TO-LINE SPACING
=5x_DIELECTRIC
C
B
MINIMUM LINE WIDTH
WEIGHT
MINIMUM LINE WIDTH
WEIGHT
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
?
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
SPACING_RULE_SET
T29DP TOP,BOTTOM
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
LAYER
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=7x_DIELECTRIC
WEIGHT
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T29 Net Properties
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM
?*
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET
I263
I262
DP_T29SNK0_ML
I264
DP_T29SNK0_ML
I265
I266
I267
DP_T29SNK0_AUXCH
I268
DP_T29SNK0_AUXCH
I269
I270
I271
DP_T29SNK1_ML
I272
DP_T29SNK1_ML
I273
I274
I275
DP_T29SNK1_AUXCH
I276
DP_T29SNK1_AUXCH
I277
I282
I283
T29_SPI_CLK
I284
T29_SPI_MOSI
I285
T29_SPI_MISO
I286
T29_SPI_CS_L
I287
T29 IC Net Properties
I288
I289
I290
I291
T29_R2D0
I292
T29_R2D0
I293
T29_R2D1
I294
T29_R2D1
I295
I322
I323
T29_D2R0
I296
T29_D2R0
I298
T29_D2R1
I297
T29_D2R1
I299
I300
I301
I302
I303
I320
I321
DP_SDRVA_ML_EVEN
I304
DP_SDRVA_ML_EVEN
I305
DP_SDRVA_ML_ODD
I306
DP_SDRVA_ML_ODD
I308
DP_SDRVA_ML_EVEN
I307
DP_SDRVA_ML_EVEN
I309
DP_SDRVA_ML_ODD
I310
DP_SDRVA_ML_ODD
I311
DP_SDRVA_AUXCH
I312
DP_SDRVA_AUXCH
I313
I314
I315
T29DPA_ML_ODD
I326
T29DPA_ML_ODD
I327
T29DPA_ML_ODD
I328
T29DPA_ML_ODD
I329
I316
I317
I324
I325
DP_A_EXT_AUXCH
I318
DP_A_EXT_AUXCH
I319
PHYSICAL
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
T29_I2C_55S
T29_I2C_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
NET_TYPE
SPACING
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
T29_I2C
T29_I2C
T29_SPI
T29_SPI
T29_SPI
T29_SPI
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
345678
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_ML_P<3..0>
DP_T29SNK0_ML_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N
DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_ML_P<3..0>
DP_T29SNK1_ML_N<3..0>
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N
I2C_T29_SCL
I2C_T29_SDA
T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
T29_R2D_C_P<3..0>
T29_R2D_C_N<3..0>
T29_D2R_P<3..0>
T29_D2R_N<3..0>
T29_R2D_P<0>
T29_R2D_N<0>
T29_R2D_P<1>
T29_R2D_N<1>
T29_R2D_C_F_P<1..0>
T29_R2D_C_F_N<1..0>
T29_D2R_C_P<0>
T29_D2R_C_N<0>
T29_D2R_C_P<1>
T29_D2R_C_N<1>
T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N
DP_SDRVA_ML_C_P<3..0>
DP_SDRVA_ML_C_N<3..0>
DP_SDRVA_ML_R_P<3..0>
DP_SDRVA_ML_R_N<3..0>
DP_SDRVA_ML_P<0>
DP_SDRVA_ML_N<0>
DP_SDRVA_ML_P<1>
DP_SDRVA_ML_N<1>
DP_SDRVA_ML_P<2>
DP_SDRVA_ML_N<2>
DP_SDRVA_ML_P<3>
DP_SDRVA_ML_N<3>
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
T29DPA_ML_P<1>
T29DPA_ML_N<1>
T29DPA_ML_P<3>
T29DPA_ML_N<3>
T29DPA_ML_P<3..0>
T29DPA_ML_N<3..0>
T29DPA_ML_C_P<3..0>
T29DPA_ML_C_N<3..0>
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
8
8
34
34
8
8
34
34
34
34
34
34
8
8
8
8
64
64
64
64
64
64
65
65
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64 65
64
64 65
64
34
34
34
34
44 34
44 34
34 64
34 64
65 64
65 64
65 64
65 64
65 64
65 64
65 64
65 64
65 64
65 64
64 34
64 34
2 1
D
C
B
T29/DP Net Properties
A
8 7 5 4 2 1
36
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
T29 Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
105 OF 109
SHEET
72 OF 75
SIZE
A
D
Page 73
www.laptopblue.vn
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
1TO1_DIFFPAIR
LAYER
ALLOW ROUTE
ON LAYER?
*
=STANDARD =STANDARD =STANDARD =STANDARD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
0.1 MM 0.1 MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
D
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
PHYSICAL
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
NET_TYPE
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SPACING
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
345678
44
44
44
44
44
44
44
6
44
6
44
44
2 1
D
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
CHGR_CSI
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
C
PHYSICAL
NET_TYPE
SPACING
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO_P
CHGR_CSO_N
53
53
53
53
C
SIZE
B
A
D
B
A
8 7 5 4 2 1
36
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
SMC Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
106 OF 109
SHEET
73 OF 75
Page 74
SENSE_1TO1_55S
THERM_1TO1_55S
DIFFPAIR
SPACING_RULE_SET
D
SENSE
THERM
AUDIO
SPACING_RULE_SET
ENETCONN
SPACING_RULE_SET
GND
SPACING_RULE_SET
GND_P2MM
PWR_P2MM
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CMD
C
MEM_DQS
MEM_40S
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MEM_37S 0.09 MM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
PCIE_85D 0.076 MM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
CPU_27P4S
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
CLK_PCIE_90D
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
B
LAYER
LAYER
LAYER
LAYER
LAYER
LAYER
*
*
*
*
*
*
*
*
*
*
GND
GND
GND
GND
GND
*
*
*
*
*
TOP
TOP
TOP
ALLOW ROUTE
ON LAYER?
=1:1_DIFFPAIR
=1:1_DIFFPAIR
LINE-TO-LINE SPACING
LINE-TO-LINE SPACING
LINE-TO-LINE SPACING
LINE-TO-LINE SPACING
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=2:1_SPACING
=2:1_SPACING
=2:1_SPACING
25 MILS
=STANDARD
0.20 MM
0.20 MM
AREA_TYPE
*
*
*
*
*
MINIMUM NECK WIDTH
=55_OHM_SE =55_OHM_SE=55_OHM_SE
=55_OHM_SE =55_OHM_SE =55_OHM_SE
WEIGHT
?
?
?
WEIGHT
?
WEIGHT
?
WEIGHT
1000
1000
SPACING_RULE_SET
GND_P2MM
GND_P2MM
GND_P2MMMEM_CTRL
GND_P2MMMEM_DATA
GND_P2MM
MINIMUM LINE WIDTH
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1 NET_SPACING_TYPE2
NET_SPACING_TYPE1 NET_SPACING_TYPE2
NET_SPACING_TYPE1 NET_SPACING_TYPE2
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MINIMUM NECK WIDTH
0.09 MM 400 MIL
0.09 MM 400 MILMEM_72D
0.1 MM
0.09 MM
0.09 MM
MAXIMUM NECK LENGTH
CPU_COMP
CPU_VCCSENSE
ENET_MDI
CLK_PCIE
PCIE
SATA
USB GND
CLK_PCIE SB_POWER
SATA
USB
LVDS
DIFFPAIR PRIMARY GAP
=1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR
AREA_TYPE
GND
GND
AREA_TYPE
GND
AREA_TYPE
GND
GND
GND
SB_POWER
SB_POWER
AREA_TYPE
GND
MAXIMUM NECK LENGTH
400 MIL
400 MIL0.09 MMMEM_85D
10 mm
500 MILUSB_85D
400 MIL
400 MIL
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
SPACING_RULE_SET
*
*
SPACING_RULE_SET
*
SPACING_RULE_SET
*
*
*
*
*
*
*
SPACING_RULE_SET
*
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=1:1_DIFFPAIR=1:1_DIFFPAIR=1:1_DIFFPAIR
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
PWR_P2MM
PWR_P2MM
PWR_P2MM
GND_P2MM
www.laptopblue.vn
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET
I295
I298
I297
I296
SENSE_DIFFPAIR
CPU_THERMD
I287
I288
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SENSE_DIFFPAIR SENSE_1TO1_55S
I249
I250
SENSE_DIFFPAIR SENSE_1TO1_55S
I252
I251
SENSE_DIFFPAIR SENSE_1TO1_55S
I253
I254
SENSE_DIFFPAIR
I256
I255
SENSE_DIFFPAIR
I281
I282
SENSE_DIFFPAIR
I283
I284
SENSE_DIFFPAIR
I285
I286
I292
I291
I335
I336
I293
I294
Audio Net Properties
ELECTRICAL_CONSTRAINT_SET
SPKRAMP_INR
I331
I332
MAX98300_R
I334
I333
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
NET_TYPE
PHYSICAL
ENET_100D
ENET_100D
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
LVDS_90D LVDS
LVDS_90D LVDS
PHYSICAL
SPACING SPACING
ENETCONN
ENETCONN
SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
NET_TYPE
SPACING
AUDIO
AUDIO
AUDIO
AUDIO
ENETCONN_P<3..0>
ENETCONN_N<3..0>
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_HDD_D2R_RDRVR_OUT_P
SATA_HDD_D2R_RDRVR_OUT_N
SATA_HDD_R2D_RDRVR_IN_P
SATA_HDD_R2D_RDRVR_IN_N
SATA_HDD_D2R_RDRVR_IN_P
SATA_HDD_D2R_RDRVR_IN_N
SATA_HDD_R2D_RDRVR_OUT_P
SATA_HDD_R2D_RDRVR_OUT_N
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
T29_THERMD_P
T29_THERMD_N
T29_MLBBOT_THMSNS_P
T29_MLBBOT_THMSNS_N
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P
CPUIMVP_ISNS1_P
CPUIMVP_ISNS1_N
CPUIMVP_ISNS2_P
CPUIMVP_ISNS2_N
CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N
CPUIMVP_ISUM_R_P
CPUIMVP_ISUM_R_N
CPUIMVP_ISUMG_R_P
CPUIMVP_ISUMG_R_N
CPUIMVP_ISNS_P
CPUIMVP_ISNS_N
VCCSAS0_CS_P
VCCSAS0_CS_N
CPUIMVP_ISUMG_P
CPUIMVP_ISUMG_N
ISNS_CPU_N
ISNS_CPU_P
ISNS_HDD_N
ISNS_HDD_P
ISNS_HDD_R_N
ISNS_HDD_R_P
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
ISNS_ODD_N
ISNS_ODD_P
ISNS_ODD_R_N
ISNS_ODD_R_P
ISNS_1V5_S3_N
ISNS_1V5_S3_P
ISNS_P1V8GPU_R_N
ISNS_P1V8GPU_R_P
ISNS_AIRPORT_N
ISNS_AIRPORT_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
SPKRAMP_INR_P
SPKRAMP_INR_N
MAX98300_R_P
MAX98300_R_N
47
47
9
9
47
47
46 47
46 47
46
46
45 58
45
45
45
45
54
54
8
8
6
6
51
51
345678
K21/K78 Specific Net PropertiesK21/K78 Specific Net Properties
ELECTRICAL_CONSTRAINT_SET
PCIE_CLK100M_AP
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
47
47
59 45
59 45
58 57 45
58 45
58 45
58 57
58 57
46 38
46 38
46
46
56 46
56 46
46 37
46 37
(USB_EXTA)
SPK_OUT
SPK_OUT
SPK_OUT
SPK_OUT
SPK_OUT
SPK_OUT
AUD_DIFF
I299
AUD_DIFF
I300
AUD_DIFF
I302
AUD_DIFF
I301
AUD_DIFF
I304
AUD_DIFF
I303
AUD_DIFF
I305
AUD_DIFF
I307
AUD_DIFF
I306
AUD_DIFF
I310
AUD_DIFF
I308
AUD_DIFF
I309
AUD_DIFF
I311
AUD_DIFF
I312
SPKRAMP_INR
I313
AUD_DIFF
I314
AUD_DIFF
I315
AUD_DIFF
I316
Misc Net Properties
ELECTRICAL_CONSTRAINT_SET
(USB_EXTA)
I317
(USB_EXTA)
I318
(USB_EXTA)
I319
(USB_EXTA)
I320
(USB_TPAD)
74 51 40
74 51 40
I322
(USB_TPAD)
I324
SMBUS_SMC_MGMT_SDA
I326
SMBUS_SMC_MGMT_SCL
I325
I328
I327
I330
I329
PHYSICAL
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
DP_85D
DP_85D
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
DIFFPAIR
DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_85D
USB_85D
PHYSICAL
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
2 1
NET_TYPE
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_LT1_P
USB2_LT1_N
CONN_USB2_BT_P
CONN_USB2_BT_N
USB_LT2_P
USB_LT2_N
DP_IG_AUX_CH_C_P
DP_IG_AUX_CH_C_N
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
SPKRAMP_SUB_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
SSM2315_SUB_N
SSM2315_SUB_P
SSM2315_L_N
SSM2315_L_P
SSM2315_R_N
SSM2315_R_P
AUD_LO2_N_R
AUD_LO2_P_R
AUD_LO1_N_R
AUD_LO1_P_R
AUD_LO2_N_L
AUD_LO2_P_L
SPKRAMP_INL_P
SPKRAMP_INL_N
SPKRAMP_INR_P
SPKRAMP_INR_N
SPKRAMP_INSUB_P
SPKRAMP_INSUB_N
USB_TPAD_R_P
USB_TPAD_R_N
PP3V3_S5
PP3V3_S0
GND
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_LT1_P
USB_LT1_N
USB_TPAD_CONN_P
USB_TPAD_CONN_N
I2C_SMC_SMS_SDA_R
I2C_SMC_SMS_SCL_R
I2C_TCON_SCL
I2C_TCON_SDA
I2C_TCON_SCL_CONN
I2C_TCON_SDA_CONN
NET_TYPE
CLK_PCIECLK_PCIE_90D
CLK_PCIECLK_PCIE_90D
USB
USB
USB
USB
USB
USB
USB
USB
DISPLAYPORT
DISPLAYPORT
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
USB
USB
SB_POWER
SB_POWER
GND
SPACING
USB
USB
USB
USB
USB
USB
SMB
SMB
SMB
SMB
SMB
SMB
53
53
53 46
53 46
39
39
39
39
52 51
6
52 51
6
D
C
74 51 40
6
74 51 40
6
7 6
7 6
B
49
6
49
6
Memory Constraint Relaxations
A
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
LAYER
MEM_72D
MEM_85D
BOTTOM
TOP 0.1 MM
8 7 5 4 2 1
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
0.127 MM
MAXIMUM NECK LENGTH
6.35 MM
6.35 MM
DIFFPAIR PRIMARY GAP
SIZE
A
D
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Project Specific Constraints
Apple Inc.
R
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
108 OF 109
SHEET
74 OF 75
36
Page 75
K90i Board-Specific Spacing & Physical Constraints
BOARD LAYERS
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
LAYER
DEFAULT
STANDARD
D
50_OHM_SE TOP,BOTTOM
LAYER
50_OHM_SE
LAYER
ALLOW ROUTE
ON LAYER?
* Y
* Y
ALLOW ROUTE
ON LAYER?
* Y
ALLOW ROUTE
ON LAYER?
40_OHM_SE TOP,BOTTOM
40_OHM_SE
40_OHM_SE
ISL3,ISL4,ISL9,ISL10
* Y
LAYER
ALLOW ROUTE
ON LAYER?
TOP,BOTTOM37_OHM_SE
37_OHM_SE
37_OHM_SE
ISL3,ISL4,ISL9,ISL10
*
LAYER
ALLOW ROUTE
ON LAYER?
TOP,BOTTOM27P4_OHM_SE
27P4_OHM_SE
C
55_OHM_SE 0.090 MM0.090 MM
TOP,BOTTOM
LAYER
ALLOW ROUTE
ON LAYER?
55_OHM_SE
LAYER
ALLOW ROUTE
ON LAYER?
72_OHM_DIFF
ISL3,ISL1072_OHM_DIFF
ISL4,ISL972_OHM_DIFF
TOP,BOTTOM72_OHM_DIFF
Y
Y
Y
Y
Y
Y
Y
Y*
Y
Y*
Y*
Y
Y
Y
BOARD AREAS
BOARD UNITS
(MIL or MM)
NO_TYPE,BGA MM 15.5.1
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=50_OHM_SE =50_OHM_SE 10 MM 0 MM 0 MM
=DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0.110 MM 0.090 MM
0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0.170 MM 0.170 MM
0.140 MM 0.140 MM =STANDARD =STANDARD =STANDARD
=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0.195 MM 0.1 MM
0.160 MM 0.1 MM =STANDARD =STANDARD =STANDARD
=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0.2 MM0.310 MM
MINIMUM LINE WIDTH
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
www.laptopblue.vn
TABLE_BOARD_INFO
ALLEGRO
VERSION
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SPACING_RULE_SET
DEFAULT
STANDARD
BGA_P1MM
BGA_P2MM
SPACING_RULE_SET
1.5:1_SPACING
2:1_SPACING
2.5:1_SPACING
3:1_SPACING
LAYER
LAYER
4:1_SPACING
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD=STANDARD0.2 MM0.250 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD=STANDARD0.076 MM0.076 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
1:1_DIFFPAIR
=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD
0.130 MM0.130 MM0.135 MM0.135 MM
0.130 MM0.130 MM0.155 MM0.155MM
0.130 MM0.130 MM0.165 MM0.165 MM
LAYER
*
*
*
*
*
*
*
*
*
*
LINE-TO-LINE SPACING
0.1 MM
=DEFAULT
=DEFAULT
=DEFAULT
LINE-TO-LINE SPACING
0.15 MM
0.2 MM
0.25 MM
0.3 MM
0.4 MM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
Y
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
* *
MEM_CLK
CLK_PCIE
CLK_SLOW
SPACING_RULE_SET
2X_DIELECTRIC
3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC
7X_DIELECTRIC
MINIMUM NECK WIDTH
*
*
*
LAYER
*
*
*
*
*
MAXIMUM NECK LENGTH
AREA_TYPE
BGA
BGA
BGA
BGA
LINE-TO-LINE SPACING
0.140 MM
0.210 MM
0.280 MM
0.350 MM
0.490 MM
DIFFPAIR PRIMARY GAP
0.1 MM 0.1 MM=STANDARD=STANDARD =STANDARD
345678
SPACING_RULE_SET
BGA_P1MM
BGA_P2MM
BGA_P2MM
BGA_P2MM
WEIGHT
?
?
?
?
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
2 1
D
C
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LAYER
85_OHM_DIFF
ALLOW ROUTE
ON LAYER?
*
ISL3,ISL1085_OHM_DIFF
ISL4,ISL985_OHM_DIFF
TOP,BOTTOM85_OHM_DIFF
LAYER
ALLOW ROUTE
ON LAYER?
90_OHM_DIFF =STANDARD=STANDARD=STANDARD=STANDARD=STANDARD
B
90_OHM_DIFF 0.210 MM0.210 MM0.089 MM0.089 MM
ISL3,ISL10
ISL4,ISL990_OHM_DIFF
TOP,BOTTOM90_OHM_DIFF
LAYER
100_OHM_DIFF
ALLOW ROUTE
ON LAYER?
*
ISL3,ISL10100_OHM_DIFF
ISL4,ISL9100_OHM_DIFF
TOP,BOTTOM100_OHM_DIFF
Y
Y
Y
Y
Y*
Y
Y
Y
Y
Y
Y
Y
MINIMUM LINE WIDTH
MINIMUM LINE WIDTH
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.
110_OHM_DIFF
LAYER
ALLOW ROUTE
ON LAYER?
ISL3,ISL10110_OHM_DIFF
ISL4,ISL9110_OHM_DIFF
TOP,BOTTOM110_OHM_DIFF
Y*
N
Y
Y
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
NOTE: These are Intel recommended impedances for PEG, unused on K90i.
A
TOP,BOTTOM48_OHM_SE
LAYER
ALLOW ROUTE
ON LAYER?
48_OHM_SE
LAYER
80_OHM_DIFF
ALLOW ROUTE
ON LAYER?
*
ISL3,ISL1080_OHM_DIFF
ISL4,ISL980_OHM_DIFF
TOP,BOTTOM80_OHM_DIFF
Y
Y*
Y
Y
Y
Y
MINIMUM LINE WIDTH
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
8 7 5 4 2 1
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0.165 MM0.120 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_ITEM
0.170 MM0.170 MM0.1 MM0.095 MM
TABLE_PHYSICAL_RULE_ITEM
0.170 MM0.170 MM0.115 MM0.115 MM
TABLE_PHYSICAL_RULE_ITEM
0.195 MM0.195 MM0.130 MM0.130 MM
0.210 MM0.210 MM0.105 MM0.105 MM
0.210 MM0.210 MM0.115 MM0.115 MM
=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD
0.250 MM0.250 MM0.074 MM0.074 MM
0.250 MM0.250 MM0.085 MM0.085 MM
0.200 MM0.200 MM0.091 MM0.091 MM
=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD
0.330 MM0.330 MM0.070 MM0.070 MM
0.300 MM0.300 MM0.071 MM0.071 MM
0.280 MM0.280 MM0.077 MM0.077 MM
=STANDARD=STANDARD=STANDARD0.090 MM0.097 MM
=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD
0.170 MM0.170 MM0.110 MM0.110 MM
0.170 MM0.170 MM0.129 MM0.129 MM
0.180 MM0.180 MM0.145 MM0.145 MM
NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers.
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_DIFF_BGA
NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers.
100_DIFF_BGA
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
LAYER
ISL3,ISL485_DIFF_BGA
ISL9,ISL1085_DIFF_BGA
LAYER
ISL3,ISL490_DIFF_BGA
ISL9,ISL1090_DIFF_BGA
LAYER
ISL3,ISL4100_DIFF_BGA
ISL9,ISL10100_DIFF_BGA
ALLOW ROUTE
ON LAYER?
*
=85_OHM_DIFF85_DIFF_BGA
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF
Y
Y
ALLOW ROUTE
ON LAYER?
=90_OHM_DIFF
*
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF
Y
Y
ALLOW ROUTE
ON LAYER?
=100_OHM_DIFF
*
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
Y
Y
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
0.125 MM0.125 MM0.075 MM0.075 MM
TABLE_PHYSICAL_RULE_ITEM
0.125 MM0.125 MM0.075 MM0.075 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
0.125 MM0.125 MM0.075 MM0.075 MM
TABLE_PHYSICAL_RULE_ITEM
0.125 MM0.125 MM0.075 MM0.075 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
0.125 MM0.125 MM0.075 MM0.075 MM
TABLE_PHYSICAL_RULE_ITEM
0.125 MM0.125 MM0.075 MM0.075 MM
SYNC_MASTER=K21_CONSTRAINTS
PAGE TITLE
PCB Rule Definitions
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/06/2011
DRAWING NUMBER
051-8870
REVISION
3.13.0
BRANCH
PAGE
109 OF 109
SHEET
75 OF 75
SIZE
B
A
D
36
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