Apple MacBook Air A1369 Schematics

SCHEM,EVT,MLB,K21

www.laptopblue.vn

04/18/11

DATE

2011-04-18

(.csa)

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29
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31
32
33
34
35
36
37
38
39
40

42
43
44
45

1

1 MASTER
2 K6_MLB
3
4 MASTER
5
6 (K99_MLB)
7
8
9

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

7

Functional Test / No Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU GROUNDS

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIE/CLK/LPC/SPI

19

PCH DMI/FDI/GRAPHICS

20

PCH PCI/FLASHCACHE/USB

21

PCH MISC

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

USB HUBS

27

Clock (CK505) and Chipset Support

28

CPU Memory S3 Support

29

DDR3 DRAM CHANNEL A (0-31)

30

DDR3 DRAM CHANNEL A (32-63)

31

DDR3 DRAM CHANNEL B (0-31)

32

DDR3 DRAM CHANNEL B (32-63)

33

FSB/DDR3/FRAMEBUF Vref Margining

34

DDR3 DRAM Channel B (32-63)

35

SecureDigital Card Reader

36

T29 Host (1 of 2)

37

T29 Host (2 of 2)

38

T29 Power Support

40

X21 WIRELESS CONNECTOR

45

SATA CONNECTOR

46

External USB Connectors

47

Left I/O (LIO) Connector

49

SMC41

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Voltage & Load Side Current Sensing

Contents

K17_REF

K91_MLB

K91_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K21_MLB

K21_MLB

K21_MLB

K21_MLB

K21_MLB

K78_MLB

K78_MLB

K21_MLB

K21_MLB

K78_MLB

K21_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

(MASTER)

K78_MLB

K78_MLB

K78_MLB

K21_MLB

K78_MLB

K21_MLB

K21_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

Date

SyncPage

MASTER

12/11/2009

19/01/2011

MASTER

05/28/2009

(02/16/2010)

05/15/2010

05/15/2010

01/10/2011

01/10/2011

01/10/2011

01/10/2011

01/10/2011

02/08/2011

01/10/2011

12/13/2010

12/13/2010

12/13/2010

12/13/2010

12/13/2010

01/10/2011

01/10/2011

12/13/2010

12/13/2010

11/29/2010

12/13/2010

12/07/2010

12/07/2010

12/07/2010

12/07/2010

01/10/2011

12/16/2010

(MASTER)

01/10/2011

01/10/2011

01/10/2011

12/13/2010

01/10/2011

12/13/2010

11/09/2010

01/10/2011

01/10/2011

01/10/2011

01/10/2011

01/10/2011

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Page

(.csa)

54

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

High Side Current Sensing

55

Thermal Sensors

56

Fan

57

IPD / KBD Backlight

61

SPI ROM

62

AUDI0: SPEAKER AMP

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPU VCCIO (1.05V) Power Supply

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

90

Internal DisplayPort Connector

93

DisplayPort/T29 A MUXing

94

DisplayPort/T29 A Connector

97

LCD Backlight Driver

100

CPU Constraints

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

104

Ethernet/FW Constraints

105

T29 Constraints

106

SMC Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

Contents

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

JACK_K90I

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K78_MLB

K21_MLB

K78_MLB

K78_MLB

K21_CONSTRAINTS

K21_CONSTRAINTS

K21_CONSTRAINTS

K21_CONSTRAINTS

K21_CONSTRAINTS

K21_CONSTRAINTS

K21_CONSTRAINTS

K21_CONSTRAINTS

K21_CONSTRAINTS

Sync

Date

01/16/2011

01/16/2011

01/10/2011

01/10/2011

01/10/2011

01/10/2011

08/20/2010

12/03/2010

01/16/2011

01/16/2011

01/10/2011

01/10/2011

12/07/2010

01/10/2011

01/16/2011

01/10/2011

01/10/2011

02/10/2011

12/13/2010

12/07/2010

01/16/2011

04/06/2011

04/06/2011

04/06/2011

04/06/2011

04/06/2011

04/06/2011

04/06/2011

04/06/2011

04/06/2011

D

C

B

DRAWING TITLE

SCHEM,MOCKUP,MLB,K21

QTY

1

1

DESCRIPTION

SCHEM,MLB,K21

PCBF,MLB,K21

8 7 6 5 4 2 1

REFERENCE DES

SCH

PCB

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

PRODUCT SAFETY REQUIREMENTS:

PCB,UL RECOGNIZED, MIN. 130-C TEMP RATING AND V-O FLAME RATING PER UL 796 & UL 94

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP RATING AND V-O FLAME RATING

3

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

051-8870

3.13.0

1 OF 109

1 OF 75

SIZE

A

D

www.laptopblue.vn

345678

2 1

1G/2GB

J2500

CPU

XDP CONN

PG 23

D

J9000

INTERNAL

DISPLAY

CONN

PG 63

JTAG

PG 10

PCIE

PG 9

U2900,U3030

U1000

INTEL CPU

EDP

PG 9

SANDYBRIDGE SFF

1.6 GHZ

FDI

PG 9

DMI

PG 9

MEMORY

PG 11

DDR3-1066/1333MHZ

A

DDR3-1066/1333MHZ

B

64-Bit

64-Bit

MEMORY

PG 27,38

U3100,3230

MEMORY

PG 29,30

1G/2GB

U7000

CHARGER

PG 52

D

POWER CIRCUITRY

PG 52-60

TEMP SENSOR

PG 47

U2700

SYSTEM

CLOCK

PG 25

J4501

SSD

C

CONN

PG 38

RTC

PG 16

CLOCK

BUFFER

PG16

SATA

PG 16

FDI

PG 17

DMI

PG 17

U1800

EDP OUT

HDMI OUT

U3600

T29 ROUTER

J9400

DISPLAY PORT+

T29

CONN

PG 65

1

U9390

MUX

PG 64

0

B

PG 34,35

PCIE

DP

J4610

PCH

XDP CONN

PG 23

X21

CONN

PG 37

PCIE

USB

J4001

WIRELESS

RGB OUT

DVI OUT

TMDS OUT
LVDS OUT

DP OUT

PG 17

JTAG

PG 16

PCIE

INTEL PCH

COUGAR POINT

PCI

PG 18PG 16

SMB

PG 16

GPIO

PG 15

SPI

PG 16

MISC

PG 19

LPC

PG 16

PWR

CTRL

PG 17

USB

PG 18

HDA

U6100

BOOTROM

PG 50

U4900

J5100

LPC+SPI

CONN

PG 43

U2600

USB

HUB-1

3

4
5 1

6

7 2

8 0
9

10

1112

13

PG 16

U2650

PG 24

USB

HUB-2

PG 24

U3500

SD CARD

CONTROLLER

PG 33

J5700

IPD FLEX

CONN

PG 49

J4600

RIGHT

EXT USB

CONN

PG 39

J3500

SERIAL
PORT

PM_SLP
S3/S4

SDCARD

CONN

PG 33

SMB_BSA SMB_B/0

SMC

PG 41

ADC

FAN0

LID

SMB_A

VOLTAGE/CURRENT SENSOR

PG 46

J5600

FAN CONN

PG 48

C

B

U6210

SPEAKER

J4700

HDA

LEFT I/O CONN

PG 40

U6201

AUDIO CODEC

PG 7

U6620

J6702

AMP

PG 9

LEFT

SPEAKER

CONN

A

LINE INSPEAKER

FILTER

PG 11

J6700

HEADPHONE/

LINE IN

JACK

PG 10

PG 10

CAM

HEADPHONE

FILTER

PG 8

USBUSB
EXT

J4702

CAMERA+ALS

CONN

LIO BOARD

J6955

HALL

EFFECT

PG 51

J4610

EXT USB

LEFT
CONN

PG 5PG 6

SPK

I2C

AMP

PG 51

8 7 5 4 2 1

J6903

RIGHT

SPEAKER

CONN

PG 52

SIZE

A

D

SYNC_MASTER=K6_MLB

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/11/2009

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

2 OF 109

SHEET

2 OF 75

36

PPDCIN_G3H_OR_PBUS

R6905

PPVIN_G3H_P3V42G3H

www.laptopblue.vn

D6905

2

R6920

ENABLE

3.425V G3HOT

LT3470A

U6990

(PAGE 52)

PP3V42_G3H_REG

345678

3

SMC POWER

SN0903048

U5010

(PAGE 42)

SMC_RESET_L

2 1

4

R7640

A

CPUIMVP_PGOOD

CPUIMVP_AXG_PGOOD

A

PPVTT_S0_DDR_LDO

16-1

DDRREG_PGOOD

PPVCCSA_S0_REG

15

10-4

PP5V_S0_VMON
PP1V5_S3RS0_VMON

PP1V05_S0_VMON

P1V8S0_PGOOD

PP1V8_S0_REG

1V05_S0_LDO_EN

PP3V3_T29_FET

PPCPUVCCIO_S0_REG

SMC_CPU_FSB_ISENSE

22-1

R5320

SMC_CPU_VSENSE

V

PPVCORE_S0_CPU_REG

R5330

SMC_GFX_VSENSE

V

PPVCORE_S0_AXG_REG

25-1

26-1

R7350

PPDDR_S3_REG

P1V5CPU_EN

23-1

PP3V3_S0_VMON

V2MON

ISL88042IRTEZ

V3MON

V4MON

(PAGE 62)

18

TPS720105

EN

U7780

(PAGE 60)

U7770

TPS72015

(PAGE 60)

PP1V5S0_EN

A

VDD

U7960

EN

R7140

6

U7801

PP1V05_S0_LDO.

36

TPS22924

U3816/U3815

(PAGE 36)

25

26

16

PP1V5_S3RS0_FET

23

CPUIMVP_AXG_PGOOD

P1V8S0_PGOOD

P5VS3_PGOOD

P3V3S5_PGOOD

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

ALL_SYS_PWRGD

R7962

4

19

PP1V5_S0_REG

22

D

T29_PWR_EN

PP1V05_T29_FET

27

U2850

25

S5_PWRGD

SMC_ONOFF_L

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

9

5

PAGE TITLE

COUGAR-POINT

(PCH)

U1800

PM_PCH_PWRGD

(PAGE 17~21)

CPU

U1000

UNCOREPWRGOOD

(PAGE 9~15)

SMC

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

U4900

(PAGE 41)

SYS_RERST#

PROCPWRGD

DRAMPWROK

SM_DRAMPWROK

RESET*

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

SYSRST(PA2)

P17(BTN_OUT)

PWRBTN#

RSMRST#

DPWROK

PLTRST#

P15

RES*

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PM_DSW_PWRGD

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

30

PM_DSW_PWRGD

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

29

28

10

12

26
6-1

4

SYNC_DATE=19/01/2011

DRAWING NUMBER

051-8870

REVISION

BRANCH

PAGE

3 OF 109

SHEET

3.13.0

3 OF 75

SIZE

C

B

A

D

EN

VCC

EN

VR_ON

PP3V3_S0

VIN

1.05V

ISL95870

U7600

(PAGE 59)

VIN

CPU VCORE

MAX15092GTL

U7400

(PAGE 57)

1.5V

S5

S3

0.75V

TPS51916

U7300

(PAGE 56)

VCC

ISL95870A

EN

(PAGE 54)

VID1

16

ISL8014A

EN

(PAGE 60)

TPS22924

EN

(PAGE 36)

VOUT

PGOOD

VOUT

VOUT

PGOOD

PGOODG

VIN

VLDOIN

VOUT1

VOUT2

PGOOD

U7100

VOUT

PGOOD

PP1V05_SUS_LDO

U7720

U3810

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

PP5V_S0_FET

J6900

F6905

D

AC

ADAPTER

DCIN(14.5V)

IN

6A FUSE

SMC_DCIN_ISENSE

4

J6950

PPVBATT_G3H_CONN

2S3P

(6 TO 8.4V)

1

R7020

A

SMC_RESET_L

VIN

BATTERY CHARGER

Q7055

CHGR_BGATE

U7000

ISL6259HRTZ

PBUS SUPPLY/

(PAGE 53)

PPVBAT_G3H_CHGR_R

VOUT

PPVBAT_G3H

R7050

SMC_BATT_ISENSE

A

1

F7040

PPBUS_G3H

R5400

A

K78/K21 POWER SYSTEM ARCHITECTURE

C

B

A

SMC

U4900

(PAGE 41)

COUGAR-POINT

(PCH)

U1800

(PAGE 17~21)

1V05_S0_LDO_EN

CPUVCCIOS0_EN

RC

DELAY

PVCCSA_EN

RC

DELAY

P1V5S0_EN

RC

DELAY

P1V8S0_EN

RC

DELAY

P60

SLP_S5#(E4)

SLP_SUS#

SLP_S4#(H4)

SLP_S3#(F4)

6

SMC_PM_G2_EN

PM_SLP_SUS_L

PM_SLP_S3_R_L

21
21

22
19

17

RC

DELAY

PM_SLP_S5_L

U7940

RC

DELAY

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

R7978

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

P3V3S5_EN

PG 17

P5V_3V3_SUS_EN

P3V3S3_EN

DDRREG_EN

P5VS3_EN

PG 17

PG 17

PG62

14-1
14-1
14-1

PG62

PG62

PG62

7

11

10-1

PG61

13
15
13-2
13
14

F9700

LCD_BKLT_EN

BKLT_PLT_RST_L

&&

PPBUS_SW_LCDBKLT_PWR

Q5300

PBUSVSENS_EN

T29_A_HV_EN

T29BST_EN_UVLO

Q9706

Q3880

EN

13-1

VIN

LP8550

U9701

(PAGE 66)

PPVIN_S5_P5VP3V3

P5VS3_EN

P3V3S5_EN

7

VOUT

VIN

LT3957

U3890

EN/UVLO

(PAGE 36)

EN1

EN2

PPVOUT_SW_LCDBKLT

SMC_PBUS_VSENSE

PP15V_T29_REG

VOUT

VIN

5V

(L/H)

3.3V

(R/H)

TPS51980

U7201

(PAGE 55)

PGOOD

P5VS3_PGOOD

P3V3S5_PGOOD

VOUT1

VOUT2

PP5V_S3_REG

PP3V3_S5_REG

14-1

9

PP3V3_S5

P5V_3V3_SUS_EN

P5V_3V3_SUS_EN

P3V3S0_EN

14

22

Q7820

Q7810

P3V3S3_EN

Q7840

Q7830

15

PP5V_S0_CPUVCCIOS0.

CPUVCCIOS0_EN

21

CPUIMVP_VR_ON

DDRREG_EN

DDRVTT_EN

PP5V_S0_VCCSA

PVCCSA_EN

CPU_VCCSA_VID<1>

14

8

10-3

PP3V3_SUS_FET

PP3V3_S3_FET

PP5V_SUS_FET

24

Q7860

P5VS0_EN

TPS720105

U7740

(PAGE 60)

14-1

10-2

P1V8_S0_EN

17

T29_PWR_EN

8 7 5 4 2 1

www.laptopblue.vn

345678

2 1

BOM Variants

BOM NUMBER

D

C

085-2684

607-8041

639-2553

639-2554

639-2558

639-2549

639-2555

639-2557

639-2548

639-2550

639-2551

639-2552

639-2556

639-2559

BOM NAME

K21i MLB DEVELOPMENT BOM

CMN PTS,PCBA,MLB,K21

PCBA,MLB,1.8GHZ,HY 2GB,K21

PCBA,MLB,1.7GHZ,SA 4GB,K21

PCBA,MLB,1.8GHZ,EL 4GB,K21

PCBA,MLB,1.7GHZ,EL 4GB,K21

PCBA,MLB,1.8GHZ,HY 4GB,K21

PCBA,MLB,1.8GHZ,SA 4GB,K21

PCBA,MLB,1.7GHZ,HY 2GB,K21

PCBA,MLB,1.8GHZ,MI 2GB,K21

PCBA,MLB,1.7GHZ,HY 4GB,K21

PCBA,MLB,1.7GHZ,SA 2GB,K21

PCBA,MLB,1.8GHZ,SA 2GB,K21

PCBA,MLB,1.7GHZ,MI 2GB,K21

BOM OPTIONS

K21_DEVEL:ENG

K21_COMMON

K21_CMNPTS,EEEE:DP1F,CPU:1.8GHZ,DDR3:HYNIX_2GB

K21_CMNPTS,EEEE:DP1G,CPU:1.7GHZ,DDR3:SAMSUNG_4GB

K21_CMNPTS,EEEE:DP1H,CPU:1.8GHZ,DDR3:ELPIDA_4GB

K21_CMNPTS,EEEE:DP1J,CPU:1.7GHZ,DDR3:ELPIDA_4GB

K21_CMNPTS,EEEE:DP1K,CPU:1.8GHZ,DDR3:HYNIX_4GB

K21_CMNPTS,EEEE:DP1L,CPU:1.8GHZ,DDR3:SAMSUNG_4GB

K21_CMNPTS,EEEE:DP1M,CPU:1.7GHZ,DDR3:HYNIX_2GB

K21_CMNPTS,EEEE:DP1N,CPU:1.8GHZ,DDR3:MICRON_2GB

K21_CMNPTS,EEEE:DP1P,CPU:1.7GHZ,DDR3:HYNIX_4GB

K21_CMNPTS,EEEE:DP1Q,CPU:1.7GHZ,DDR3:SAMSUNG_2GB

K21_CMNPTS,EEEE:DP1R,CPU:1.8GHZ,DDR3:SAMSUNG_2GB

K21_CMNPTS,EEEE:DP1T,CPU:1.7GHZ,DDR3:MICRON_2GB

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEEE #’s

PART NUMBER

825-7563

825-7563

825-7563

825-7563

825-7563 CRITICAL

825-7563

825-7563

825-7563

825-7563 CRITICAL

825-7563 CRITICAL

825-7563

825-7563

QTY

1

1

1

1

1

1

1

1

1

1

1

1

DESCRIPTION

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

LABEL,LIO,K99

REFERENCE DES

[EEEE_DP1F]

[EEEE_DP1G]

[EEEE_DP1H]

[EEEE_DP1J]

[EEEE_DP1K]

[EEEE_DP1L]

[EEEE_DP1M]

[EEEE_DP1N]

[EEEE_DP1P]

[EEEE_DP1Q]

[EEEE_DP1R]

[EEEE_DP1T]

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

EEEE:DP1F

EEEE:DP1G

EEEE:DP1H

EEEE:DP1J

EEEE:DP1K

EEEE:DP1L

EEEE:DP1M

EEEE:DP1N

EEEE:DP1P

EEEE:DP1Q

EEEE:DP1R

EEEE:DP1T

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=MASTER

PAGE TITLE

Revision History

Sub BOM

PART NUMBER

QTY

1

1

DESCRIPTION

K21 MLB DEVELOPMENT

CMN PTS,PCBA,MLB,K21

8 7 5 4 2 1

REFERENCE DES

DEVEL

CMNPTS

CRITICAL

CRITICAL085-2684

CRITICAL607-8041

BOM OPTION

DEVEL_BOM

K21_CMNPTS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

36

Apple Inc.

R

SYNC_DATE=MASTER

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

4 OF 109

SHEET

4 OF 75

K21 BOM GROUPS

BOM GROUP

K21_COMMON

K21_MISC

K21_PROGPARTS

K21_DEVEL:ENG

K21_DEVEL:PVT

K21_DEBUG:ENG

D

K21_DEBUG:PVT

K21_DEBUG:PROD

DDR3:HYNIX_2GB

DDR3:HYNIX_4GB

DDR3:SAMSUNG_2GB

DDR3:SAMSUNG_4GB

DDR3:MICRON_2GB

DDR3:ELPIDA_4GB

Programmable Parts

PART NUMBER

C

341T0352 CRITICAL

337S3997

338S0895

341T0348

335S0809

341T0349

Alternate Parts

PART NUMBER

376S0855

376S0977

376S0972

377S0107

138S0676

371S0679 371S0652

138S0679

B

138S0671

337S4092

337S4093

353S3312

376S0790 376S0928

128S0333

152S1462

104S0035

152S1085

514-0744 998-3941

376S0874

138S0684

338S0721

152S1493

A

www.laptopblue.vn

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

ALTERNATE FOR
PART NUMBER

376S0613

376S0859

376S0612

377S0066

138S0691

138S0678

138S0673

337S4100

337S4101

353S3055

128S0294

152S1295

104S0011

152S1307

376S0895

138S0648138S0703

138S0660

338S0923

152S1300

QTY

1

1

1

1

1

1

1

1

1

DESCRIPTION

IC,EEPROM,SERIAL,SPI,1Kx8,1.8V,MLP8,LF

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

IC,SMC,RENESAS,H8S/2117RP,9MM,TLP,HF

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

IC,EFI ROM,K21 K78

BOM OPTION

BOM OPTIONS

ALTERNATE,COMMON,K21_MISC,K21_DEBUG:ENG,K21_PROGPARTS,USBHUB_2513B,T29BST:Y,EDP,PCH:B3

CPUMEM_S0,HUB1_2NONREM,HUB2_2NONREM,T29:YES,SDRVI2C:MCU,SDRV_PD,KB_BL

BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

IC,T29-ROM,K21

IC,T29-MCU,K21

IC,SMC,K21

REF DES

COMMENTS:

Diodes alt to Toshiba

ALL

ALL

Diodes alt to Toshiba

Rohm alt to Toshiba

ALL

ALL

ONsemi alt to Semtech

ALL

Murata alt to Samsung

ALL

NXP alt to NXP

ALL

Murata/Samsung to Taiyo

ALL

Taiyo alt to Murata

ALL

EARLY 1.5GHZ CPU SAMPLES

EARLY 1.4GHZ CPU SAMPLES

ALL

NXP alt to Pericom

ALL

ALL

TI alt to Fairchild

ALL

Sanyo alt for Sanyo/Frederick

ALL

Toko alt for NEC inductor

Panasonic alt to Cyntec

ALL

Toko alt for Cyntec

ALL

ALL

Old J9400 alt to New J9400

ALL

FDMC0202S alt to RJK03E0DNS

Murata alt to Taiyo Yuden

ALL

Murata alt to Taiyo Yuden

ALL

SMSC USX2061 alt to USB2513B

ALL

ALL

Coilcraft alt to Murata

BOOTROM_PROG,SMC_PROG,T29ROM:PROG,T29MCU:PROG

LPCPLUS,XDP_CONN,XDP_PCH

DEVEL_BOM,SMC_DEBUG_YES,XDP

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB

DRAM_CFG0:H,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB

REFERENCE DES

U3690

U3690

U9330

U9330

U4900

U4900

U6100

U6100

U6100

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL

CRITICAL335S0550

CRITICAL

CRITICAL341T0353

CRITICAL

CRITICAL

CRITICAL

CRITICAL335S0803

CRITICAL

BOM OPTION

T29ROM:BLANK

T29ROM:PROG

T29MCU:BLANK

T29MCU:PROG

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_BLANK

BOOTROM_PROG

8 7 5 4 2 1

Module Parts

PART NUMBER

337S4121

337S4119

337S4101

337S4100

337S4099

337S4098

337S4080

337S4091

338S0976

333S0585

333S0585

333S0585

333S0585

333S0586

333S0586

333S0586

333S0586

333S0587

333S0587

333S0587

333S0587

333S0588

333S0588

333S0588

333S0588

333S0590

333S0590

333S0590

333S0590

333S0589

333S0589

333S0589

333S0589

353s2929

QTY

PD Module Parts

806-2333

806-2356

806-2347

806-2376

806-2377

DRAM CFG CHART

VENDOR

HYNIX

SAMSUNG

MICRON

ELPIDA

SIZE

2GB

4GB

DESCRIPTION

1

SNB,QAYS,QS,J1,1.8,17W,2+2,1.20,4M,BGA

SNB,QAYM,QS,J1,1.7,17W,2+2,1.20,3M,BGA

1

1

1

1

1

1

1

1

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

1

1

1

1

1

1

SNB,QAM1,QS,J1,1.6,17W,2+2,1.1,4M,BGA

SNB,QAM2,QS,J1,1.5,17W,2+2,1.1,4M,BGA

SNB,QAM3,QS,J1,1.4,17W,2+2,1.05,3M,BGA

SNB,QALV,QS,J1,1.3,17W,2+2,1.05,3M,BGA

COUGAR POINT,SLHAG,PRQ,BD82QS67

COUGAR POINT,B3,SLJ4K,PRQ,BD82QS67

IC,T29 Eagle Ridge,192 FCBGA,8x9MM

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,T-DIE,HYNIX

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,B-DIE,HYNIX

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,G-DIE,SAMSUNG

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,D-DIE,SAMSUNG

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,V68A-D,MICRON

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,C-DIE,ELPIDA

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28

K21, T29 Fence

K21, T29 Can

K21, T29 Filter Can

K78, mDP Can

K78, mDP Spring

CFG 0CFG 1

0 0

1

0

1

CFG 2

0

1

1

0

1

DIE REV

A

B

345678

REFERENCE DES

U1000

U1000

U1000

U1000

U1000

U1000

U1800

U1800

U3600

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U3100,U3110,U3120,U3130

U3200,U3210,U3220,U3230

U7000

T29FENCE

T29CAN

T29FILTERCAN

MDPCAN

MDPSPRING

CFG 3

0

1

36

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

DRAM_TYPE:HYNIX_2GB

DRAM_TYPE:HYNIX_2GB

DRAM_TYPE:HYNIX_2GB

DRAM_TYPE:HYNIX_2GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:SAMSUNG_2GB

DRAM_TYPE:SAMSUNG_2GB

DRAM_TYPE:SAMSUNG_2GB

DRAM_TYPE:SAMSUNG_2GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:MICRON_2GB

DRAM_TYPE:MICRON_2GB

DRAM_TYPE:MICRON_2GB

DRAM_TYPE:MICRON_2GB

DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:ELPIDA_4GB

2 1

CPU:1.8GHZ

CPU:1.7GHZ

CPU:1.6GHZ

CPU:1.5GHZ

CPU:1.4GHZ

CPU:1.3GHZ

PCH:B2

PCH:B3

T29:YES

NOSTUFF

NOSTUFF

SYNC_MASTER=K17_REF

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM Configuration

Apple Inc.

R

SYNC_DATE=05/28/2009

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

5 OF 109

SHEET

5 OF 75

SIZE

D

C

B

A

D

www.laptopblue.vn

345678

2 1

Functional Test Points

J4001: AirPort / BT Connector

FUNC_TEST

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

D

C

B

A

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

J4501: SATA SSD Connector

FUNC_TEST

TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

FUNC_TEST

TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

J4800: SD Card Connector

FUNC_TEST

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

J5100: LPC+SPI Connector

FUNC_TEST

TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE

PP3V3_WLAN_F
WIFI_EVENT_L
PCIE_AP_R2D_N
PCIE_AP_R2D_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
USB_BT_P
USB_BT_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_WAKE_L
AP_RESET_CONN_L
AP_CLKREQ_Q_L
=PP3V3_S3_BT

(Need to add 8 GND TPs)

PP3V3_S0_HDD_R
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_R2D_N
SATA_HDD_R2D_P
SMC_HDD_OOB_TEMP_CONN
SMC_HDD_TEMP_CTL_CONN

(Need to add 6 GND TPs)

J4700: LIO Connector

=PP3V42_G3H_ONEWIRE
=PP3V3_S0_AUDIO
=PP3V3R1V5_S0_AUDIO
SYS_ONEWIRE
SMC_BC_ACOK
=USB_PWR_EN
SMC_LID
=I2C_LIO_SDA
=I2C_LIO_SCL
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
AUD_IPHS_SWITCH_EN
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
AUD_GPIO_3
SPKRAMP_INR_N
SPKRAMP_INR_P
USB_EXTD_N
USB_EXTD_P
USB_CAMERA_N
USB_CAMERA_P
HDA_SDOUT
HDA_BIT_CLK
HDA_SDIN0
USB_EXTD_OC_L
HDA_RST_L
HDA_SYNC

(Need to add 5 GND TPs)

PP3V3_SW_SD_PWR
SD_CLK
SD_CMD
SD_D<7..0>
SD_CD_L
SD_WP

(Need to add 2 GND TPs)

=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_AD<3..0>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
LPC_CLK33M_LPCPLUS
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO

(Need to add 6 GND TPs)

(Need 5 TPs)

37

41 37

70 37

70 37

70 37 16

70 37 16

69 37 24

69 37 24

70 37 16

70 37 16

37 17

37

37

37

7

(Need 5 TPs)

38

69 38

69 38

69 38

69 38

38

38

40

7

(Need 2 TPs)

40

7

40

7

41 40

42 41 40

62 40 39

49 42 41 40

6

44 40

44 40

44 40

44 40

40 19

40 18

40 18

51 40

74 51 40

74 51 40

69 40 24

69 40 24

69 40 18

69 40 18

70 40 16

70 40 16

70 40 16

40 24

70 40 16

70 40 16

33

33

33

33

33

33

43

7

43

7

70 43 41 16

43

43

70 43 41 16

43 41 17

43 42 41

43 25

43 42 41

43 41

43 41

43 42 41 39

70 43 25

50 43 19

43

43

43 41 16

43 41 17

43 42 41

43 42 41

53 43 42 41

43 41

43 42 41 39

43 19

I628

I629
I630

I631
I632

I633

I634
I636

I635

I638
I637

I639

I641
I640

I643
I642

I644

I646
I645

I648

I647
I649

I650

I651
I653

I652
I654

I655

I657
I656

I624

I623

J5600: Fan Connector

FUNC_TEST

TRUE
TRUE

TRUE

J5700: IPD Flex Connector

FUNC_TEST

TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE

J6900: DC-In Connector

FUNC_TEST

TRUE

TRUE

J6903: Speaker Connector

FUNC_TEST

TRUE

TRUE

J6950: Battery Connector

FUNC_TEST

TRUE
TRUE

TRUE

TRUE

J9000: Internal DP Connector

FUNC_TEST

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE

=PP5V_S0_FAN
FAN_RT_TACH
FAN_RT_PWM
(Need to add 1 GND TP)

PP3V3_TPAD_CONN
PP5V_TPAD_FILT
=PP3V42_G3H_TPAD
USB_TPAD_CONN_P
USB_TPAD_CONN_N
=I2C_TPAD_SDA
=I2C_TPAD_SCL
SMC_ONOFF_L
SMC_LID
SMC_TPAD_RST_L
SMC_PME_S4_WAKE_L
(Need to add 5 GND TPs)

=PP18V5_DCIN_CONN
=PP5V_S3_LIO_CONN
(Need to add 5 GND TPs)

SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT

(Need to add 3 GND TPs)

PPVBAT_G3H_CONN
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SYS_DETECT_L
(Need to add 4 GND TPs near
J6950 and 1 for shield)

PPVOUT_SW_LCDBKLT
PP3V3_SW_LCD
I2C_TCON_SDA_R
I2C_TCON_SCL_R
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
DP_INT_HPD_CONN
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P
DP_INT_ML_F_P<0>
DP_INT_ML_F_N<0>
DP_INT_ML_F_P<1>
DP_INT_ML_F_N<1>
(Need to add 5 GND TPs)

Misc Voltages & Control Signals

FUNC_TEST

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

PPBUS_G3H
PPVIN_SW_T29BST
PPBUS_S5_HS_COMPUTING_ISNS
PPDCIN_G3H
PP3V42_G3H
PPVRTC_G3H
PP5V_S5
PP5V_SUS
PP3V3_S5
PP3V3_SUS
PP3V3_S3
PP1V8_S0
PP3V3_S0
PP1V5_S3
PP1V5_S3RS0
PP1V5_S0
PP1V05_S0
PPVTTDDR_S3
PP0V75_S0_DDRVTT
PPVCCSA_S0_CPU
PP1V05_SUS
PP15V_T29
PP3V3_T29
PP1V05_T29
PP1V05_S0_PCH_VCCADPLL
PPVCORE_S0_CPU
PPVCORE_S0_AXG
PP1V5_S3_CPU_VCCDQ
PP1V05_S0_CPU_VCCPQE
PP1V8_S0_CPU_VCCPLL_R

(Need to add 27 GND TPs)

48

7

48

48

49

49

49

7

74 49

74 49

49 44

49 44

49 42 41

49 42 41 40

6

49 42

49 42 41

(Need 6 TPs)

52

7

52

7

74 52 51

74 52 51

(Need 4 TPs)

53 52

52 44

52 44

52

(Need 2 TPs)

66 63

(Need 2 TPs)

63

63

63

66 63

66 63

66 63 18

66 63

66 63

66 63

63

70 63

70 63

70 63

70 63

70 63

70 63

52

7

36

7

7

7

7

7

7

7

74

7

7

7

7

74

7

68

7

68

7

7

7

7

7

7

7

7

7

36

7

7

7

7

7

7

7

16

16

16

18

I627

I626

TP_HDA_SDIN1
TP_HDA_SDIN2

TP_HDA_SDIN3

16

16

16

16

16

8 7 5 4 2 1

J5715: KB BKLT CONNECTOR

FUNC_TEST

TRUE
TRUE

NO_TEST Nets

NO_TEST

TP_CRT_IG_BLUE

17

TP_CRT_IG_GREEN

17

TP_CRT_IG_RED

17

TP_CRT_IG_DDC_CLK

17

TP_CRT_IG_DDC_DATA

17

TP_CRT_IG_HSYNC

17

TP_CRT_IG_VSYNC

17

TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA

TP_PCH_LVDS_VBG

TP_PCI_PME_L
TP_PCI_CLK33M_OUT3

TP_CLINK_CLK

TP_CLINK_DATA
TP_CLINK_RESET_L

TP_PCIE_CLK100M_PEBN

TP_PCIE_CLK100M_PEBP

I593

I592

I595
I594

I596
I597

I598

I599
I600

I601

I602

TP_SDVO_TVCLKINN

17

TP_SDVO_TVCLKINP

17

TP_SDVO_STALLN

17

TP_SDVO_STALLP

17

TP_SDVO_INTN

17

TP_SDVO_INTP

17

TP_XDP_PCH_OBSFN_A<0..1>

23

TP_XDP_PCH_OBSFN_B<0..1>

23

TP_XDPPCH_HOOK2

23

TP_XDPPCH_HOOK3

23

TP_XDP_PCH_OBSFN_D<0..1>

23

TP_XDP_PCH_HOOK4

23

TP_XDP_PCH_HOOK5

23

TP_PCH_GPIO64_CLKOUTFLEX0

16

TP_PCH_GPIO65_CLKOUTFLEX1

16

TP_PCH_GPIO66_CLKOUTFLEX2

16

TP_PCH_GPIO67_CLKOUTFLEX3

16

KBDLED_FB
KBDLED_ANODE

(Need to add 2 GND TP)

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

XDP_PCH_AP_PWR_EN

TRUE

XDP_PCH_USB_HUB_SOFT_RST_L

TRUE

XDP_PCH_SDCONN_STATE_RST_L

TRUE

XDP_PCH_ENET_PWR_EN

TRUE

XDP_PCH_SDCONN_DET_L

TRUE

XDP_PCH_S5_PWRGD

TRUE

XDP_PCH_PWRBTN_L

TRUE

XDP_PCH_ISOLATE_CPU_MEM_L

TRUE

XDP_FW_CLKREQ_L

TRUE

XDP_AP_CLKREQ_L

TRUE

XDP_PCH_AUD_IPHS_SWITCH_EN

TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_CRT_IG_BLUE

NC_CRT_IG_GREEN

NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK

NC_CRT_IG_DDC_DATA

NC_CRT_IG_HSYNC

NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_CLK

NC_LVDS_IG_CTRL_DATA

NC_PCH_LVDS_VBG

NC_HDA_SDIN1
NC_HDA_SDIN2

NC_HDA_SDIN3

NC_PCI_PME_L
NC_PCI_CLK33M_OUT3

NC_PCIE_CLK100M_PEBN

NC_PCIE_CLK100M_PEBP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

36

49

49

NC_CLINK_CLK

NC_CLINK_DATA
NC_CLINK_RESET_L

23

23

23

23

23

23

23

23

23

NC_SDVO_TVCLKINN

NC_SDVO_TVCLKINP

NC_SDVO_STALLN

NC_SDVO_STALLP

NC_SDVO_INTN
NC_SDVO_INTP

NC_TP_XDP_PCH_OBSFN_A<0..1>
NC_TP_XDP_PCH_OBSFN_B<0..1>

NC_TP_XDPPCH_HOOK2

NC_TP_XDPPCH_HOOK3
NC_TP_XDP_PCH_OBSFN_D<0..1>

NC_TP_XDP_PCH_HOOK4

NC_TP_XDP_PCH_HOOK5

NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3

NC_EDP_TXP<0..3>

MAKE_BASE=TRUE

NC_EDP_TXN<0..3>

MAKE_BASE=TRUE

NC_EDP_AUXP

MAKE_BASE=TRUE

NC_EDP_AUXN

MAKE_BASE=TRUE

NC_CPU_THERMDA

MAKE_BASE=TRUE

NC_CPU_THERMDC

MAKE_BASE=TRUE

NC_CPU_RSVD<30..45>

MAKE_BASE=TRUE

NC_CPU_RSVD<8..27>

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..4>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..4>

MAKE_BASE=TRUE

NC_PEG_D2RP<15..4>

MAKE_BASE=TRUE

NC_PEG_D2RN<15..4>

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE5N

16

TP_PCIE_CLK100M_PE5P

16

TP_PCIE_CLK100M_PE6N

16

TP_PCIE_CLK100M_PE6P

16

TP_PCIE_CLK100M_PE7N

16

TP_PCIE_CLK100M_PE7P

16

TP_PSOC_P1_3
TP_SATA_B_D2RN

16

TP_SATA_B_D2RP

16

TP_SATA_B_R2D_CN

16

TP_SATA_B_R2D_CP

16

TP_SATA_D_D2RN

16

TP_SATA_D_D2RP

16

TP_SATA_D_R2D_CN

16

TP_SATA_D_R2D_CP

16

TP_SATA_E_D2RN

16

TP_SATA_E_D2RP

16

TP_SATA_E_R2D_CN

16

TP_SATA_E_R2D_CP

16

TP_SATA_F_D2RN

16

TP_SATA_F_D2RP

16

TP_SATA_F_R2D_CN

16

TP_SATA_F_R2D_CP

16

TP_PCH_TP18

TP_PCH_TP17

TP_PCH_TP16
TP_PCH_TP15

TP_PCH_TP14

TP_PCH_TP13
TP_PCH_TP12

TP_PCH_TP10
TP_PCH_TP9

TP_PCH_TP8
TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5
TP_PCH_TP4

TP_PCH_TP3

TP_PCH_TP2
TP_PCH_TP1

PCH_VSS_NCTF<1>

TRUE

I566
I567

I568

I570

I571

I569

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE

TP_LVDS_IG_B_CLKN

8

TP_LVDS_IG_B_CLKP

8

TP_LVDS_IG_BKL_PWM

SYNC_MASTER=(K99_MLB)

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SMC_BS_ALRT_L

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

70

70

70

70

70

70

TRUE

MAKE_BASE=TRUE

TP_EDP_TX_P<0..3>

TP_EDP_TX_N<0..3>

TP_EDP_AUX_P

TP_EDP_AUX_N

TP_CPU_THERMDA

TP_CPU_THERMDC

TP_CPU_RSVD<30..45>

TP_CPU_RSVD<8..27>

=PEG_R2D_C_P<15..4>

=PEG_R2D_C_N<15..4>

=PEG_D2R_P<15..4>

=PEG_D2R_N<15..4>

NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_PE5N

NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE7P

NC_PSOC_P1_3
NC_SATA_B_D2RN

NC_SATA_B_D2RP

NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP

NC_SATA_D_D2RN

NC_SATA_D_D2RP
NC_SATA_D_R2D_CN

NC_SATA_D_R2D_CP
NC_SATA_E_D2RN

NC_SATA_E_D2RP

NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP

NC_SATA_F_D2RN

NC_SATA_F_D2RP
NC_SATA_F_R2D_CN

NC_SATA_F_R2D_CP

NC_PCH_TP18

NC_PCH_TP17

NC_PCH_TP16
NC_PCH_TP15

NC_PCH_TP14

NC_PCH_TP13
NC_PCH_TP12

NC_PCH_TP10
NC_PCH_TP9

NC_PCH_TP8
NC_PCH_TP7

NC_PCH_TP6

NC_PCH_TP5
NC_PCH_TP4

NC_PCH_TP3

NC_PCH_TP2
NC_PCH_TP1

PCH_VSS_NCTF<15>

TRUE

I500

I499

I501
I502

I503

I504
I505

I506

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

PCH_VSS_NCTF<17>

PCH_VSS_NCTF<19>
PCH_VSS_NCTF<19>

PCH_VSS_NCTF<21>
PCH_VSS_NCTF<25>

PCH_VSS_NCTF<27>

PCH_VSS_NCTF<29>

NC_LVDS_IG_B_CLKN

NC_LVDS_IG_B_CLKP

NC_LVDS_IG_BKL_PWM

NC_SMC_BS_ALRT_L

SYNC_DATE=(02/16/2010)

Functional Test / No Test

Apple Inc.

R

DRAWING NUMBER

051-8870

REVISION

BRANCH

PAGE

7 OF 109

SHEET

9

9

9

9

9

9

3.13.0

6 OF 75

D

C

B

70

70

70

6

70

6

70

70

70

70

A

SIZE

D

www.laptopblue.vn

=PPBUS_G3H

53

PPVIN_SW_T29BST

36

6

VOLTAGE=12.8V

=PPVIN_S5_HS_COMPUTING_ISNS

46

D

=PP18V5_DCIN_CONN

52

6

=PP3V42_G3H_REG

52

C

=PPVRTC_G3_OUT

25

=PP5V_S5_LDO

55

=PP5V_SUS_FET

61

B

=PP5V_S3_REG

55

=PP5V_S0_FET

61

A

"G3Hot" (Always-Present) Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

=PPBUS_S0_LCDBKLT
=PPBUS_S0_VSENSE
=PPVIN_SW_T29BST

=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_P5VP3V3

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_VCCSAS0
=PPVIN_S0_CPUAXG

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR
=PPDCIN_S5_VSENSE

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_CHGR
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
=PP3V42_G3H_ONEWIRE

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE

=PPVRTC_G3_PCH

5V Rails

PP5V_S5

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S5_P1V5DDRFET
=PP5V_S5_P5VSUSFET
=PP5V_S5_TPAD

PP5V_SUS

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP5V_SUS_PCH

PP5V_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_AUDIO_AMP

=PP5V_S3_DDRREG

=PP5V_S3_MEMRESET

=PP5V_S3_P5VS0FET
=PP5V_S3_RTUSB
=PP5V_S3_LIO_CONN

PP5V_S0

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSA

=PP5V_S0_PCH

=PP5V_S0_VMON

=PP5V_S0_KBDLED

52

6

66

45

36

8

46

55

6

56

59

54

58

6

53

45

6

43

6

53

62

44

39

49

6

42

25

40

6

6

6

61

61

49

6

22

51

56

26

61

39

52

6

66

57

59

48

6

43

6

54

22

62

49

58 57

42 41

20 17 16

=PP3V3_S5_REG

55

=PP3V3_SUS_FET

61

=PP3V3_S3_FET

61

=PP3V3_S0_FET

61

3.3V Rails

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

PP3V3_S5

=PP3V3_S5_XDP
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S5_LCD
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_ROM
=PP3V3_S5_USB_RESET
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_PWRCTL
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S5_P3V3SUSFET
=PP3V3_S5_TPAD
=PP3V3_S4_DPAPWRSW
=PP3V3_S4_SMC

PP3V3_SUS

=PP3V3_SUS_PCH_VCCSUS_USB
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_GPIO
=PP3V3_SUS_PCH
=PP3V3_SUS_PWRCTL
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_SMC

PP3V3_S3

=PP3V3_S3_BT
=PP3V3_S3_CARDREADER
=PP3V3_S3_MEMRESET
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_WLANISNS
=PP3V3_S3_BMON_ISNS
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_1V5S3ISNS
=PP3V3_S3_DBGLEDS

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_CPUVCCIOISNS
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_HS_COMPUTING_ISNS
=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_CPU_VCCIO_SEL
=PP3V3_S0_DP_DDC
=PP3V3_S0_FAN

=PP3V3_S0_P3V3T29FET

=PP3V3_S0_P1V8S0

=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_STRAPS
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMC
=PP3V3_S0_HDD
=PP3V3_S0_HDDISNS
=PP3V3_S0_VMON
=PP3V3_S0_P1V5S0
=PP3V3_S0_T29PWRCTL
=PP3V3_S0_DPSDRVA
=PP3V3_S0_P1V05S0LDO
=PP3V3_S0_IMVPISNS
=PP3V3_S0_XDP
=PP3V3_S0_T29I2C
=PP3V3_S0_BKLTISNS
=PP3V3_S0_SYSCLKGEN

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

74

6

23

61

61

26

63

19 17

25

42

50

24

22 20

25

62

62

22 20

61

49

65

42

6

22 20

22 20

20

22

62

60

42

6

37

6

33

26

44

44

24

8

24

31

37

46

46

19 18

46

52

74

6

45

40

6

66

46

47

12

8

48

36

60

22 19 16

18

22

22 20

22 20

22 20

22 20

22

19 17 16

62

25

25

44

44

44

42

38

46

62

60

36

64

60

45

23

44

46

25

19 18 17 16

=PP1V8_S0_REG

60

2A max supply

=PPDDR_S3_REG

56

=PP1V5_S3RS0_FET

61

=PP1V5_S0_REG

60

=PPVTT_S3_DDR_BUF

56 31

=PPVTT_S0_DDR_LDO

56

=PPVCCSA_S0_REG

54

=PP1V05_SUS_LDO

60

=PPCPUVCCIO_S0_REG

59

? mA

8 7 5 4 2 1

1.8V/1.5V/1.2V/1.05V Rails

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_P1V05S0LDO
=PP1V8R1V5_S0_PCH_VCCVRM
=PPVDDIO_S0_SBCLK
=PP1V8_S0_P1V5S0

PP1V5_S3

MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_P1V5S3RS0_FET
=PPVIN_S0_DDRREG_LDO

PP1V5_S3RS0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S3_CPU_VCCDDR
=PP1V5_S3RS0_VMON

PP1V5_S0

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP3V3R1V5_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PPVCCSA_S0_CPU

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_VMON
=PP1V05_S0_PCH_VCCIO_CLK
=PPVCCIO_S0_CPUIMVP
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
=PPVCCIO_S0_XDP
=PPVCCIO_S0_SMC
=PP1V05_S0_P1V05T29FET

345678

6

14

22 20 18

60

20

25

60

68

6

26

32 28 27

32 30 29

61

56

68

6

26 15 12 10

62

6

40

6

22 20 16

6

6

32

32

26

15 12

6

14 12

15 12

6

14 12

23

6

20

14 12 10

9

22 16

22 20

17

22 20 16

22 20

22 20

22 20

62

22 20

57

22 20 16

22 20

22 20

20

22 20

20

20

23

41

36

=PP15V_T29_REG

36

8

=PP3V3_T29_FET

36

=PP1V05_T29_FET

36

=PP1V05_S0_LDO

60

=PPVCORE_S0_CPU_REG

58

=PPVCORE_S0_AXG_REG

58

=PP1V5_S3_CPU_VCCDQ

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL_R

36

2 1

T29 Rails (off when no cable)

PP15V_T29

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE

=PPHV_SW_DPAPWRSW

PP3V3_T29

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PPVDDIO_T29_CLK
=PP3V3_T29_RTR
=PP3V3_T29_PCH_GPIO

PP1V05_T29

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_T29_RTR

1V05 S0 LDO

PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCADPLL

Chipset "VCore" Rails

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU
=PPCPUVCORE_S0_VSENSE

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU_VCCAXG
=PPGFXVCORE_S0_VSENSE

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

SYNC_MASTER=K91_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Power Aliases

Apple Inc.

R

6

65

6

25

6

35

6

20

SYNC_DATE=05/15/2010

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

8 OF 109

SHEET

7 OF 75

D

36 35 34

19 16

36

6

14 12

9

45

6

9

45

6

6

6

C

15 12

B

A

SIZE

D

www.laptopblue.vn

345678

2 1

=PEG_R2D_C_P<3..0>

CPU signals

MEMVTT_EN

Plated Board Slot

SL0900

TH-NSP

1

SL-2.3X3.9-2.9X4.5

D

STDOFF-4.5OD1.8H-SM

C

DisplayPort Pogo

CPU Heat Sink Mounting Bosses

Z0913

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

Fan Boss

Z0905

1

Z0911

1

1

4x 860-1327

X21 Boss

STDOFF-4.5OD1.9H-SM

1

Z0914

860-1327860-1327

EMI I/O Pogo Pins

CRITICAL

ZS0905

POGO-2.0OD-3.6H-K86-K87

SM

1

870-1938

Z0910

STDOFF-4.5OD1.8H-SM

1

Z0912

STDOFF-4.5OD1.8H-SM

1

USB/SD Card Pogo

POGO-2.0OD-3.6H-K86-K87

SSD Boss

Z0915

STDOFF-4.5OD1.9H-SM

1

860-1327

CRITICAL

ZS0906

SM

1

870-1938

DP_EXTA_ML_C_P<3..0>

70 64

MAKE_BASE=TRUE

DP_EXTA_ML_C_N<3..0>

70 64

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_P

70 64

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_N

70 64

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

16

PCIE_EXCARD_D2R_P

16

PCIE_EXCARD_R2D_C_N

16

PCIE_EXCARD_R2D_C_P

16

PCIE_CLK100M_EXCARD_N

70 16

PCIE_CLK100M_EXCARD_P

70 16

PEG_CLK100M_P

70 16

PEG_CLK100M_N

70 16

68 11

68 11

68 11

68 11

68 11

68 11

68 11

68 11

68 11

68 11

68 11

68

11

TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP

16

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>
MEM_A_A<15>
MEM_B_A<15>

MAKE_BASE=TRUE

69

69

69

69

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_IG_ML_P<3..0>

DP_IG_ML_N<3..0>

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

DPLL_REF_CLK_N

DPLL_REF_CLK_P

DisplayPort PCB Stiffener

(Provides PCB support for small finger above J9400)

NO STUFF

MT0900

STIFFENER-K16-K99

SM-SP

1

806-1176

B

Digital Ground

GND

VOLTAGE=0V
MIN_NECK_WIDTH=0.075MM
MIN_LINE_WIDTH=0.6MM

=PPVIN_SW_T29BST

36

7

T29_A_BIAS

65 64

C0960

0.01UF

1

10%
10V

2

X5R
201

T29BST:N

R0960

0

1 2

5%

1/8W

MF-LF

805

T29_A_BIAS_R

65

8

=PP15V_T29_REG

T29_A_BIAS caps

SIGNAL_MODEL=EMPTY

T29 Can Slots

SIGNAL_MODEL=EMPTY

SL0901

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL0903

TH-NSP TH-NSP

1

SL0905

TH-NSP

A

1

SL-1.1X0.45-1.4X0.75 SL-1.1X0.45-1.4X0.75

SL0902

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL0904

1

SL-1.1X0.45-1.4X0.75SL-1.1X0.45-1.4X0.75

SL0906

TH-NSP

1

65

8

T29_A_BIAS_R

65

8

T29_A_BIAS_R

65

8

T29_A_BIAS_R

SIGNAL_MODEL=EMPTY

R0933

1 2

SIGNAL_MODEL=EMPTY

R0934

1 2

1/20W

1 2

=DDRVTT_EN

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_B_MLN<3..0>

DP_IG_B_AUX_P

DP_IG_B_AUX_N

NC_PCIE_EXCARD_D2RN
NC_PCIE_EXCARD_D2RP
NC_PCIE_EXCARD_R2D_CN
NC_PCIE_EXCARD_R2D_CP
NC_PCIE_CLK100M_EXCARDN
NC_PCIE_CLK100M_EXCARDP

NC_PEG_CLK100MP
NC_PEG_CLK100MN

TP_MEM_A_CLKP<1>
TP_MEM_A_CLKN<1>
NC_MEM_A_CKE<1>
NC_MEM_A_CS_L<1>
NC_MEM_A_ODT<1>
TP_MEM_B_CLKP<1>
TP_MEM_B_CLKN<1>
NC_MEM_B_CKE<1>
NC_MEM_B_CS_L<1>
NC_MEM_B_ODT<1>
TP_MEM_A_A<15>
TP_MEM_B_A<15>

DPLL_REF_CLKN

DPLL_REF_CLKP

7

R0931

51

1 2

T29_A_BIAS_R2DP0

5%

1

1/20W

201

R0932

51

5%

1/20W

MF

201

51

5%

1/20W

MF

201

51

5%

MF

201

MF

C0901

0.01UF

10%

SIGNAL_MODEL=EMPTY

10V

2

X5R
201

T29_A_BIAS_R2DN0

1

C0902

0.01UF

10%
10V

SIGNAL_MODEL=EMPTY

2

X5R
201

T29_A_BIAS_R2DP1

1

C0903

0.01UF

10%

SIGNAL_MODEL=EMPTY

10V

2

X5R
201

T29_A_BIAS_R2DN1

1

C0904

0.01UF

10%

SIGNAL_MODEL=EMPTY

10V

2

X5R
201

56 26 26

17

17

17

17

TP_DP_IG_C_CTRL_CLK

17

TP_DP_IG_C_CTRL_DATA

17

TP_DP_IG_D_CTRL_CLK

17

TP_DP_IG_D_CTRL_DATA

17

DP_EXTA_DDC_CLK

64

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA

64

MAKE_BASE=TRUE

DP_EXTA_HPD

64

MAKE_BASE=TRUE

67 10

67 10

PPBUS_SW_LCDBKLT_PWR

66

MAKE_BASE=TRUE

74 46

74 46

ISNS_LCDBKLT_P

OUT

ISNS_LCDBKLT_N

OUT

NC_USB_HUB1_OCS4

MAKE_BASE=TRUE

NC_USB_HUB2_OCS4

MAKE_BASE=TRUE

R0908

100K

1/20W

1

5%

MF

201

2

8 7

8 7

CRITICAL

R0910

0.01

0.5%
1W MF

0612-1

1 2
3 4

=PP3V3_S0_DP_DDC

R0920

2.2K 2.2K

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

=PP3V3_S0_DP_DDC

DP_IG_B_DDC_CLK

DP_IG_B_DDC_DATA

DP_IG_B_HPD

T29_A_BIAS caps

SIGNAL_MODEL=EMPTY

R0926

51

T29_A_BIAS_R

65

8

36

T29_A_BIAS_R

65

8

64

64

64

64

64

1 2

1/20W

SIGNAL_MODEL=EMPTY

R0927

1 2

1/20W

C0962

0.01UF

10%
10V
X5R
201

DP_A_BIAS_N_2

24

5%

MF

201

51

5%

MF

201

DP_A_BIAS caps

1

2

1

C0905

0.01UF

10%
10V

2

X5R
201

T29 Aliases

Unused USB ports

=PP3V3_S3_USB_HUB

7

NO STUFF

R0917

69 64

T29_A_RSVD_N
T29_A_RSVD_P

R0918

201

1/20W

201

1/20W

9

9

9

9

1

R0921

5%

1/20W

R0924

1/20W

MF

201

2

DP_IG_C_CTRL_CLK
DP_IG_C_CTRL_DATA
DP_IG_D_CTRL_CLK
DP_IG_D_CTRL_DATA

1

R0925

2.2K

5%

1/20W

MF

201

2

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPBUS_SW_BKL

201

=USB_HUB1_OCS4

=USB_HUB2_OCS4

T29_A_BIAS_D2RP1

1

C0906

0.01UF

10%

SIGNAL_MODEL=EMPTY

10V

2

X5R
201

T29_A_BIAS_D2RN1

1

C0907

0.01UF

10%
10V

SIGNAL_=EMPTY

2

X5R
201

DP_A_BIAS_P_0DP_A_BIAS_P_2

64 64

C0964

0.01UF

DP_A_BIAS_N_0

64

SIGNAL_MODEL=EMPTYSIGNAL_MODEL=EMPTY

R0915

0

1 2

5%

0

1 2

MF

5%

MF

=PEG_R2D_C_N<3..0>
=PEG_D2R_P<3..0>
=PEG_D2R_N<3..0>

5%

MF

2.2K

10K

1/20W

1

2

1/20W

10%
10V
X5R
201

201

5%

MF

201

5%
MF

R0922

2.2K

1

2

1

2

1

2

1

2

1/20W

201

17

17

17

C0908

0.01UF

10%
10V
X5R
201

1

2

1

5%

MF

2

65

65

R0916

10K

5%
1/20W
MF
201

USB_T29A_N
USB_T29A_P

R0923

2.2K

1/20W

66

24

24

5%

MF

201

NO STUFF

8 7 5 4 2 1

36

PEG_R2D_C_P<3..0>

67

PEG_R2D_C_N<3..0>

67

PEG_D2R_P<3..0>

67

PEG_D2R_N<3..0>

67

TP_DP_IG_C_HPD

17

1

2

TP_DP_IG_C_MLP<3..0>

17

TP_DP_IG_C_MLN<3..0>

17

TP_DP_IG_C_AUXP

17 72 34

TP_DP_IG_C_AUXN

17

TP_DP_IG_D_HPD

17

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

T29 DP Ports

MAKE_BASE=TRUE

LVDS Aliases

TP_LVDS_IG_B_CLKP

6

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

6

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

LCD_IG_PWR_EN

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

SATA Aliases

Unused SATA ODD Signals

69 16

69 16

69 16

69 16

SATA_ODD_R2D_C_P

IN

SATA_ODD_R2D_C_N

IN

SATA_ODD_D2R_P

OUT

SATA_ODD_D2R_N

OUT

Unused PGOOD signal

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

23 19

19

19

69 24

69 24 69 64

IN

IN

OUT

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_ISP_TCK

JTAG_ISP_TDI

JTAG_ISP_TDO

SYNC_MASTER=K91_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

JTAG_T29_TCK_R

PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_T29SNK0_HPD

DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N

DP_IG_D_HPD

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<0..3>

LVDS_IG_B_DATA_N<0..3>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_BKL_PWM

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

NC_SATA_ODD_R2DCP

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

MAKE_BASE=TRUE

P1V5S3RS0_RAMP_DONE

DDRREG_PGOOD

T29 JTAG

JTAG_T29_TDI

JTAG_T29_TDO

Signal Aliases

Apple Inc.

R

R0990

0

1 2

5%

1/20W

MF

201

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

JTAG_T29_TCK

1

R0909

100K

5%

1/20W

MF

201

2

69

69

69

69

69

69

17 66

17 63

17 66

61

IN

56

IN

OUT

OUT

IN

SYNC_DATE=05/15/2010

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

9 OF 109

SHEET

8 OF 75

70 34

70 34

70 34

70 34

34

72 34

72 34

D

72 34

C

B

34

34

34

A

SIZE

D

www.laptopblue.vn

345678

2 1

67 17

67 17

67 17

67 17

D

C

=PP1V05_S0_CPU_VCCIO

14

9 7

10 12

R1030

24.9

1 2

1%

1/20W

MF

201

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

67 17

PLACE_NEAR=U1000.AF3:12.7MM

B

Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are
shared with other interfaces.

NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor

(refer to latest Processor EDS for DC specifications).

If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.

DMI_S2N_N<0>

IN

DMI_S2N_N<1>

IN

DMI_S2N_N<2>

IN

DMI_S2N_N<3>

IN

DMI_S2N_P<0>

IN

DMI_S2N_P<1>

IN

DMI_S2N_P<2>

IN

DMI_S2N_P<3>

IN

DMI_N2S_N<0>

OUT

DMI_N2S_N<1>

OUT

DMI_N2S_N<2>

OUT

DMI_N2S_N<3>

OUT

DMI_N2S_P<0>

OUT

DMI_N2S_P<1>

OUT

DMI_N2S_P<2>

OUT

DMI_N2S_P<3>

OUT

FDI_DATA_N<0>

OUT

FDI_DATA_N<1>

OUT

FDI_DATA_N<2>

OUT

FDI_DATA_N<3>

OUT

FDI_DATA_N<4>

OUT

FDI_DATA_N<5>

OUT

FDI_DATA_N<6>

OUT

FDI_DATA_N<7>

OUT

FDI_DATA_P<0>

OUT

FDI_DATA_P<1>

OUT

FDI_DATA_P<2>

OUT

FDI_DATA_P<3>

OUT

FDI_DATA_P<4>

OUT

FDI_DATA_P<5>

OUT

FDI_DATA_P<6>

OUT

FDI_DATA_P<7>

OUT

FDI_FSYNC<0>

IN

FDI_FSYNC<1>

IN

FDI_INT

IN

FDI_LSYNC<0>

IN

FDI_LSYNC<1>

IN

EDP_COMP

67

EDP_HPD_L

9

DP_INT_AUX_CH_N

70 63

DP_INT_AUX_CH_P

70 63

DP_INT_ML_N<0>

70 63

DP_INT_ML_N<1>

70 63

TP_EDP_TX_N<2>

6

TP_EDP_TX_N<3>

6

DP_INT_ML_P<0>

70 63

DP_INT_ML_P<1>

70 63

TP_EDP_TX_P<2>

6

TP_EDP_TX_P<3>

6

M2

DMI_RX_0*

P6

DMI_RX_1*

P1

DMI_RX_2*

P10

DMI_RX_3*

N3

DMI_RX_0

P7

DMI_RX_1

P3

DMI_RX_2

P11

DMI_RX_3

K1

DMI_TX_0*

M8

DMI_TX_1*

N4

DMI_TX_2*

R2

DMI_TX_3*

K3

DMI_TX_0

M7

DMI_TX_1

P4

DMI_TX_2

T3

DMI_TX_3

U7

FDI0_TX_0*

W11

FDI0_TX_1*

W1

FDI0_TX_2*

AA6

FDI0_TX_3*

W6

FDI1_TX_0*

V4

FDI1_TX_1*

Y2

FDI1_TX_2*

AC9

FDI1_TX_3*

U6

FDI0_TX_0

W10

FDI0_TX_1

W3

FDI0_TX_2

AA7

FDI0_TX_3

W7

FDI1_TX_0

T4

FDI1_TX_1

AA3

FDI1_TX_2

AC8

FDI1_TX_3

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AD2

EDP_ICOMPO

AF3

EDP_COMPIO

FIXME: Pin should be EDP_HPD*

AG11

EDP_HPD

AG4

EDP_AUX*

AF4

EDP_AUX

AC3

EDP_TX_0*

AC4

EDP_TX_1*

AE11

EDP_TX_2*

AE7

EDP_TX_3*

AC1

EDP_TX_0

AA4

EDP_TX_1

AE10

EDP_TX_2

AE6

EDP_TX_3

OMIT_TABLE

CRITICAL

U1000

SANDY-BRIDGE

MOBILE-2C-35W

BGA

(1 OF 9)

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*

PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*

PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

CPU_PEG_COMP

67

PLACE_NEAR=U1000.G3:12.7MM

=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>

=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>

=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>

R1010

24.9

1 2

1%

1/20W

MF

201

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

=PP1V05_S0_CPU_VCCIO

8

8

8

8

6

6

6

6

6

6

6

6

6

6

6

6

8

8

8

8

6

6

6

6

6

6

6

6

6

6

6

6

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

8

8

8

8

6

6

6

6

6

6

6

6

6

6

6

6

8

8

8

8

6

6

6

6

6

6

6

6

6

6

6

6

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_VCCAXG

NOSTUFF

R1064

49.9

NOSTUFF

R1065

49.9

NOTE: Intel validation sense lines per

NOSTUFF

1

1

R1070

49.9

1%

1%

1/20W

1/20W

MF

MF
201

201

2

2

PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=BOTTOM

Note. VOLTAGE=1.25V
Note. VOLTAGE=0V

Note. VOLTAGE=1.05V
Note. VOLTAGE=0V

NOSTUFF

1

1

R1071

49.9

1%

1%

1/20W

1/20W

MF

MF

201

201

2

2

PLACE_NEAR=U1000.K45:50.8MM

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.K43:50.8MM

PLACE_SIDE=BOTTOM

9 7

7

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

14 12 10

14 12

67 23

67 23

67 23

67 23

67 23

67 23

67 23

67 23

15 12

7

CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N

67 23

67 23

67 23

67 23

67 23

67 23

67 23

23

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN
IN
IN
IN
IN

23

IN

67

IN
IN
IN

9

IN

23

IN

CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>

TP_CPU_VCC_DIE_SENSE

CPU_THERMD_P

74 47

OUT

CPU_THERMD_N

47 74

OUT

NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.
This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core
to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.

68 31 30 29 28 27

PP0V75_S3_MEM_VREFDQ_A

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

H43
K43

H45
K45

F48

H48
K48

BA19

NC

AV19

NC

AT21

NC

BB21

NC

BB19

NC

AY21

NC

BA22

NC

AY22

NC

AU19

NC

AU21

NC

BD21

NC

BD22

NC

BD25

NC

BD26

NC

BG22

NC

BE22

NC

BG26

NC

BE26

NC

BF23

NC

BE24

NC

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17

VCC_VAL_SENSE
VSS_VAL_SENSE

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

VCC_DIE_SENSE

RSVD_6
RSVD_7

RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27

OMIT_TABLE

CRITICAL

U1000

NOSTUFF

R1021

0

1 2

5%

1/20W

MF

201

BGA

(5 OF 9)
RESERVED

SANDY-BRIDGE

MOBILE-2C-35W

DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

NOSTUFF

1

R1020

1K

1%
1/20W
MF
201

2

BE7

RSVD_28

BG7

RSVD_29

RSVD_30
RSVD_31
RSVD_32
RSVD_33

RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38

RSVD_39
RSVD_40

RSVD_41
RSVD_42
RSVD_43
RSVD_44

RSVD_45

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61

DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

NC
NC

NC
NC
NC

NC
NC
NC
NC
NC

NC
NC

NC
NC

NC
NC
NC

CPU_MEM_VREFDQ_A

CPU_MEM_VREFDQ_A

TP_CPU_DC_TEST_A4
CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_D1
TP_CPU_DC_TEST_A58
CPU_DC_TEST_C59_A59

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_D61
TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BE59_BE61

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BG58
TP_CPU_DC_TEST_BG4
CPU_DC_TEST_C4_BE3_BG3

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

9

9

D

C

B

CPU_CFG<16>

23

CPU_CFG<7>

23

9

67

CPU_CFG<6>

67 23

9

CPU_CFG<5>

67 23

9

CPU_CFG<4>

67 23

9

CPU_CFG<2>

67 23

9

R1042

EDP

1

1

R1044

1K

5%

1/16W

1/16W

MF-LF

MF-LF

402

2

1

R1045

1K

1K

5%

5%
1/16W
MF-LF

402

402

2

2

NOSTUFF

A

NOSTUFFNOSTUFF

R1046

NOSTUFF

1

1

R1047

1K

1K

5%

5%

1/16W

1/16W

MF-LF

MF-LF

402

402

2

2

FOR SANDYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

8 7 5 4 2 1

9

CPU_CFG<3>

67 23

9

CPU_CFG<1>

23

9

67

CPU_CFG<0>

67 23

9

NOSTUFF

R1040

These can be Placed close to J2500 and Only for debug access

1

1K

5%
1/16W
MF-LF

402

2

NOSTUFF NOSTUFF

1

R1041

R1043

1K

5%
1/16W
MF-LF

402

2

1K

5% 5%
1/16W
MF-LF

402

=PP1V05_S0_CPU_VCCIO

14 12 10

9 7

NOSTUFF

1

2

R1049

1

1K

1/16W
MF-LF

402

2

DP_INT_HPD

63

Q1031

SSM3K15FV

SOD-VESM-HF

1

G S

PLACE_NEAR=U1000.AG11:12.7MM

1

R1031

1K

5%
1/20W
MF
201

2

EDP_HPD_L

3

D

2

9

SIZE

A

D

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

10 OF 109

SHEET

9 OF 75

36

www.laptopblue.vn

345678

2 1

D

=PP1V05_S0_CPU_VCCIO

14 12 10

9 7

NOSTUFF NOSTUFF

1

R1100

1

R1101

62

5%
1/20W
MF
201

2

C

R1103

56

67 57 42

=PP1V5_S3_CPU_VCCDDR

26 15 12

7

67 26 17

IN

=PP1V05_S0_CPU_VCCIO

14 12 10

9 7

B

CPU_RESET_L

25 23

IN

CPU_PROCHOT_L

BI

PM_MEM_PWRGD

R1120

200

1/20W

1

1%
MF

201

2

R1126

1/20W

1

75

1%

MF

201

2

1 2

5%

1/20W

MF

201

R1121

1 2

R1125

1 2

130

1/20W

201

43.2

1/20W

201

CPU_PROCHOT_R_L

1%

MF

1%
MF

67 41 19

67 19

67 17

67 23 19

18

OUT

67

OUT

BI

OUT

IN

IN

26

OUT

PM_MEM_PWRGD_R

1K

5%

1/20W

MF

201

2

CPU_PROC_SEL_L

CPU_CATERR_L

CPU_PECI

PM_THRMTRIP_L

PM_SYNC
CPU_PWRGD

PLT_RESET_LS1V1_L

=MEM_RESET_L

1

1

R1113

R1112

25.5140

1%

1%

1/20W

1/20W

MF

MF

201

201

2

2

NOSTUFF

1

R1104

51

5%
1/20W
MF
201

2

CPU_SM_RCOMP<0>

67

CPU_SM_RCOMP<1>

67

CPU_SM_RCOMP<2>

67

1

R1114

200

1%
1/20W
MF
201

2

1

R1115

4.99K

1%
1/20W
MF
201

2

NOSTUFF

1

R1102

1K

5%
1/20W
MF
201

2

1

R1111

10K

5%
1/20W
MF
201

2

C57

NC

F49

C49

A48

C45

D45

C48

B46

BE45

D44

AT30

BF44
BE43
BG43

PROC_DETECT*

PROC_SELECT*

CATERR*

PECI

PROCHOT*

THERMTRIP*

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET*

SM_DRAMRST*

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

OMIT_TABLE

CRITICAL

U1000

SANDY-BRIDGE

MOBILE-2C-35W

BGA

(2 OF 9)

THERMAL

PWR MGMT

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

CLOCKS

BCLK_ITP*

(IPU)
(IPU)

(IPU)
(IPU)
(IPU)

(IPU)

(IPU)
(IPU)

JTAG & BPM

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

BCLK

BCLK*

PRDY*
PREQ*

TRST*

DBR*

BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*

TCK
TMS

TDI
TDO

J3
H2

AG3
AG1

N59
N58

N53
N55

L56
L55
J58

M60
L59

K58

G58
E55
E59
G55
G59
H60
J59
J61

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

DPLL_REF_CLKP
DPLL_REF_CLKN

ITPCPU_CLK100M_P
ITPCPU_CLK100M_N

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

67 16

IN

67 16

IN

67

8

IN

67

8

IN

67 16

IN

67 16

IN

67 23

OUT

67 23

IN

67 23

IN

67 23

IN

67 23

IN

67 23

IN

67 23

OUT

67 25 23

OUT

67 23

BI

67 23

BI

67 23

BI

67 23

BI

67 23

BI

67 23

BI

67 23

BI

67 23

BI

D

C

B

A

8 7 5 4 2 1

36

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

11 OF 109

SHEET

10 OF 75

SIZE

A

D

www.laptopblue.vn

345678

2 1

OMIT_TABLE

CRITICAL

MEM_A_DQ<0>

68 27

BI

MEM_A_DQ<1>

68 27

BI

MEM_A_DQ<2>

68 27

BI

MEM_A_DQ<3>

68 27

BI

MEM_A_DQ<4>

68 27

D

C

B

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 27

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 28

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

BI

MEM_A_DQ<5>

BI

MEM_A_DQ<6>

BI

MEM_A_DQ<7>

BI

MEM_A_DQ<8>

BI

MEM_A_DQ<9>

BI

MEM_A_DQ<10>

BI

MEM_A_DQ<11>

BI

MEM_A_DQ<12>

BI

MEM_A_DQ<13>

BI

MEM_A_DQ<14>

BI

MEM_A_DQ<15>

BI

MEM_A_DQ<16>

BI

MEM_A_DQ<17>

BI

MEM_A_DQ<18>

BI

MEM_A_DQ<19>

BI

MEM_A_DQ<20>

BI

MEM_A_DQ<21>

BI

MEM_A_DQ<22>

BI

MEM_A_DQ<23>

BI

MEM_A_DQ<24>

BI

MEM_A_DQ<25>

BI

MEM_A_DQ<26>

BI

MEM_A_DQ<27>

BI

MEM_A_DQ<28>

BI

MEM_A_DQ<29>

BI

MEM_A_DQ<30>

BI

MEM_A_DQ<31>

BI

MEM_A_DQ<32>

BI

MEM_A_DQ<33>

BI

MEM_A_DQ<34>

BI

MEM_A_DQ<35>

BI

MEM_A_DQ<36>

BI

MEM_A_DQ<37>

BI

MEM_A_DQ<38>

BI

MEM_A_DQ<39>

BI

MEM_A_DQ<40>

BI

MEM_A_DQ<41>

BI

MEM_A_DQ<42>

BI

MEM_A_DQ<43>

BI

MEM_A_DQ<44>

BI

MEM_A_DQ<45>

BI

MEM_A_DQ<46>

BI

MEM_A_DQ<47>

BI

MEM_A_DQ<48>

BI

MEM_A_DQ<49>

BI

MEM_A_DQ<50>

BI

MEM_A_DQ<51>

BI

MEM_A_DQ<52>

BI

MEM_A_DQ<53>

BI

MEM_A_DQ<54>

BI

MEM_A_DQ<55>

BI

MEM_A_DQ<56>

BI

MEM_A_DQ<57>

BI

MEM_A_DQ<58>

BI

MEM_A_DQ<59>

BI

MEM_A_DQ<60>

BI

MEM_A_DQ<61>

BI

MEM_A_DQ<62>

BI

MEM_A_DQ<63>

BI

MEM_A_BA<0>

OUT

MEM_A_BA<1>

OUT

MEM_A_BA<2>

OUT

MEM_A_CAS_L

OUT

MEM_A_RAS_L

OUT

MEM_A_WE_L

OUT

AG6
AJ6

AP11

AL6

AJ10

AJ8
AL8
AL7

AR11

AP6
AU6
AV9
AR6

AP8
AT13
AU13

BC7

BB7
BA13
BB11

BA7

BA9

BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS*
SA_RAS*
SA_WE*

U1000

BGA

(3 OF 9)

SANDY-BRIDGE

MOBILE-2C-35W

MEMORY CHANNEL A

SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*

SA_CK_0

SA_CK_0*

SA_CKE_0

SA_CK_1

SA_CK_1*

SA_CKE_1

SA_CS_0*
SA_CS_1*

SA_ODT_0
SA_ODT_1

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

AU36
AV36

AY26

AT40
AU40

BB26

BB40
BC41

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_N<1>
MEM_A_CKE<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_B_DQ<0>

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

68 32 28 27

68 32 28 27

68 32 28 27

68

8

68

8

68

8

68 32 28 27

68

8

68 32 28 27

68

8

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68 32 28 27

68

8

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 29

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 30

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

BI

MEM_B_DQ<1>

BI

MEM_B_DQ<2>

BI

MEM_B_DQ<3>

BI

MEM_B_DQ<4>

BI

MEM_B_DQ<5>

BI

MEM_B_DQ<6>

BI

MEM_B_DQ<7>

BI

MEM_B_DQ<8>

BI

MEM_B_DQ<9>

BI

MEM_B_DQ<10>

BI

MEM_B_DQ<11>

BI

MEM_B_DQ<12>

BI

MEM_B_DQ<13>

BI

MEM_B_DQ<14>

BI

MEM_B_DQ<15>

BI

MEM_B_DQ<16>

BI

MEM_B_DQ<17>

BI

MEM_B_DQ<18>

BI

MEM_B_DQ<19>

BI

MEM_B_DQ<20>

BI

MEM_B_DQ<21>

BI

MEM_B_DQ<22>

BI

MEM_B_DQ<23>

BI

MEM_B_DQ<24>

BI

MEM_B_DQ<25>

BI

MEM_B_DQ<26>

BI

MEM_B_DQ<27>

BI

MEM_B_DQ<28>

BI

MEM_B_DQ<29>

BI

MEM_B_DQ<30>

BI

MEM_B_DQ<31>

BI

MEM_B_DQ<32>

BI

MEM_B_DQ<33>

BI

MEM_B_DQ<34>

BI

MEM_B_DQ<35>

BI

MEM_B_DQ<36>

BI

MEM_B_DQ<37>

BI

MEM_B_DQ<38>

BI

MEM_B_DQ<39>

BI

MEM_B_DQ<40>

BI

MEM_B_DQ<41>

BI

MEM_B_DQ<42>

BI

MEM_B_DQ<43>

BI

MEM_B_DQ<44>

BI

MEM_B_DQ<45>

BI

MEM_B_DQ<46>

BI

MEM_B_DQ<47>

BI

MEM_B_DQ<48>

BI

MEM_B_DQ<49>

BI

MEM_B_DQ<50>

BI

MEM_B_DQ<51>

BI

MEM_B_DQ<52>

BI

MEM_B_DQ<53>

BI

MEM_B_DQ<54>

BI

MEM_B_DQ<55>

BI

MEM_B_DQ<56>

BI

MEM_B_DQ<57>

BI

MEM_B_DQ<58>

BI

MEM_B_DQ<59>

BI

MEM_B_DQ<60>

BI

MEM_B_DQ<61>

BI

MEM_B_DQ<62>

BI

MEM_B_DQ<63>

BI

MEM_B_BA<0>

OUT

MEM_B_BA<1>

OUT

MEM_B_BA<2>

OUT

MEM_B_CAS_L

OUT

MEM_B_RAS_L

OUT

MEM_B_WE_L

OUT

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9

BD9
BD13
BF12

BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

BG39
BD42
AT22

AV43
BF40
BD45

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS*
SB_RAS*
SB_WE*

OMIT_TABLE

CRITICAL

U1000

BGA

(4 OF 9)

SB_CK_0

SB_CK_0*

SB_CKE_0

SB_CK_1

SB_CK_1*

SB_CKE_1

SB_CS_0*

SANDY-BRIDGE

MOBILE-2C-35W

SB_CS_1*

SB_ODT_0
SB_ODT_1

SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*

SB_DQS_0

MEMORY CHANNEL B

SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

BA34
AY34

AR22

BA36
BB36

BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1>MEM_A_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

68 32 30 29

68 32 30 29

68 32 30 29

68

8

68

8

68

8

68 32 30 29

68

8

68 32 30 29

68

8

68 29

BI

68 29

BI

68 29

BI

68 29

BI

68 30

BI

68 30

BI

68 30

BI

68 30

BI

68 29

BI

68 29

BI

68 29

BI

68 29

BI

68 30

BI

68 30

BI

68 30

BI

68 30

BI

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68 32 30 29

68

8

D

C

B

A

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=01/10/2011

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

12 OF 109

SHEET

11 OF 75

SIZE

A

D

www.laptopblue.vn

345678

2 1

=PPVCORE_S0_CPU_VCCAXG

15 12

NOSTUFF

1

R1370

100

1%
1/20W
MF
201

2

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

15 12

1

1%

MF

2

9 7

=PPVCCSA_S0_CPU

7

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46

N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

F45
G45

BB3
BC1
BC4

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

VAXG_1
VAXG_2
VAXG_3
VAXG_4
VAXG_5
VAXG_6
VAXG_7
VAXG_8
VAXG_9
VAXG_10
VAXG_11
VAXG_12
VAXG_13
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_18
VAXG_19
VAXG_20
VAXG_21
VAXG_22
VAXG_23
VAXG_24
VAXG_25
VAXG_26
VAXG_27
VAXG_28
VAXG_29
VAXG_30
VAXG_31
VAXG_32
VAXG_33
VAXG_34
VAXG_35
VAXG_36
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43
VAXG_44
VAXG_45
VAXG_46
VAXG_47
VAXG_48
VAXG_49
VAXG_50
VAXG_51
VAXG_52
VAXG_53
VAXG_54
VAXG_55
VAXG_56

VAXG_SENSE
VSSAXG_SENSE

VCCPLL_1
VCCPLL_2
VCCPLL_3

VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14
VCCSA_15
VCCSA_16

=PPVCORE_S0_CPU

14 12

9 7

A26

VCC_1

A29

D

C

B

A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76

A

OMIT_TABLE

CRITICAL

U1000

BGA

(6 OF 9)

SANDY-BRIDGE

MOBILE-2C-35W

PEG AND DDR

CORE SUPLLY

RAIL

LINES

SENSE SVID QUIET

VSS_SENSE_VCCIO

VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8

VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29

VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49

VCCIO_50
VCCIO_51

VCCIO_SEL

VCCPQE_1
VCCPQE_2

VIDALERT*

VIDSCLK

VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

=PP1V05_S0_CPU_VCCIO

(NOT controlled by VCCIO_SEL)
Fixed at 1.05V

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16
W17

For Future Compatibility

BC22

CPU_VCCIO_SEL

AM25

=PP1V05_S0_CPU_VCCPQE

AN22

A44
B43
C44

F43
G43

AN16
AN17

CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

=PP3V3_S0_CPU_VCCIO_SEL

1

R1320

10K

5%

1/20W

MF

201

2

14

7

7

1

R1302

130

1%

PLACE_NEAR=U1000.C44:2.54mm
1/20W
MF
201

2

PLACE_NEAR=U1000.F43:50.8mm

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V
Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACE_NEAR=U1000.G43:50.8mm

R1310

43

1 2

201

1/20W

R1311

1 2

1/20W

201

R1312

1 2

1/20W

201

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=R1310.2:2.54mm

1

R1300

75

1%
1/20W
MF
201

2

5% MF

MF05%

MF05%

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

=PP1V05_S0_CPU_VCCIO

100

1/20W

100

1/20W

NOSTUFF

1

1

R1362

100

1%

1%

1/20W
MF

MF

201

201

2

2

NOSTUFF

1

1

R1363

100

1%

1%

PLACE_SIDE=BOTTOM

1/20W

MF

MF

201

201

2

2

NOSTUFF

R1360

NOSTUFF

R1361

14 12 10

9 7

IN

OUT

BI

=PPVCORE_S0_CPU

PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=BOTTOM

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

67 57

OUT

67 57

OUT

67 59

OUT

67 59

OUT

PLACE_NEAR=U1000.AN17:50.8mm

15 12

67 57

67 57

67 57

67 57

67 57

14 12

9 7

14 12 10

9 7

PLACE_NEAR=U1000.G45:50.8mm

=PPVCORE_S0_CPU_VCCAXG

9 7

PLACE_NEAR=U1000.F45:50.8mm

PLACE_SIDE=BOTTOM

CPU_AXG_SENSE_P

OUT

CPU_AXG_SENSE_N

OUT

=PP1V8_S0_CPU_VCCPLL_R

14

7

NOSTUFF

R1371

PLACE_SIDE=BOTTOM

100

1/20W

201

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

8 7 5 4 2 1

36

OMIT_TABLE

CRITICAL

U1000

BGA

(7 OF 9)

SANDY-BRIDGE

MOBILE-2C-35W

GRPHICS

DDR3-1.5V RAILS

(IPU)

RAIL

QUIET

VSS_SENSE_VDDQ

LINE

SENSE

(IPU)

LINE

SENSE

1.8V

RAIL

SA RAIL

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26

VCCDQ_1
VCCDQ_2

VDDQ_SENSE

VCCSA_SENSE

VCCSA_VID_0
VCCSA_VID_1

SM_VREF

=PP1V5_S3_CPU_VCCDDR

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

AM28
AN26

BC43
BA43

U10

D48
D49

AY43

R1314

1/20W

=PP1V5_S3_CPU_VCCDQ

CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N

CPU_VCCSASENSE
CPU_VCCSA_VID<0>

CPU_VCCSA_VID<1>

CPU_DDR_VREF

VOLTAGE=0.75V

1

1

R1313

10K

10K

5%

5%
1/20W

MF

MF

201

201

2

2

PLACE_NEAR=U1000.BC43:50.8mm

PLACE_NEAR=U1000.BA43:50.8mm

=PP1V5_S3_CPU_VCCDDR

26 15 12 10

7

PLACE_NEAR=U1000.U10:50.8mm

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

26 15 12 10

=PP1V5_S3_CPU_VCCDDR

7

SM_VREF_EXT

R1330

PLACE_NEAR=U1000.AY43:2.54mm

SM_VREF_EXT

R1331

PLACE_NEAR=U1000.AY43:2.54mm

SYNC_MASTER=K78_MLB

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

=PPVCCSA_S0_CPU

15 12

7

1

R1380

100

1%

1/20W

MF

201

2

15

7

Note. VOLTAGE=1.05V
Note. VOLTAGE=0V

54

OUT

12

1

100

5%

1/20W

MF

201

2

1

100

5%

1/20W

MF

201

2

R1381

100

1/20W

1

1%
MF

201

2

1

2

SM_VREF_EXT

C1330

0.1UF

10%
16V
X5R-CERM
0201

PLACE_NEAR=U1000.AY43:2.54mm

CPU POWER

1

R1382

100

1%

1/20W

MF

201

2

CPU_DDR_VREF

SYNC_DATE=01/10/2011

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

13 OF 109

SHEET

12 OF 75

OUT

D

C

54

B

12

A

SIZE

D

www.laptopblue.vn

OMIT_TABLE

OMIT_TABLE

CRITICAL

BG13

VSS

BG17

VSS

BG21

VSS

BG24

VSS

BG28

VSS

D

C

B

BG37
BG41

BG45

BG49
BG53

VSS
VSS
VSS
VSS
VSS

C29

VSS

C35

VSS

C40

VSS

D4

VSS

D6

VSS

D10

VSS

D14

VSS

D18

VSS

D22

VSS

D26

VSS

D29

VSS

D35

VSS

D40

VSS

D43

VSS

D46

VSS

D50

VSS

D54

VSS

D58

VSS

E3

VSS

E25

VSS

E29

VSS

E35

VSS

E40

VSS

F13

VSS

F15

VSS

F19

VSS

F29

VSS

F35

VSS

F40

VSS

F55

VSS

G6

VSS

G48

VSS

G51

VSS

G61

VSS

H4

VSS

H10

VSS

H14

VSS

H17

VSS

H21

VSS

H53

VSS

H58

VSS

J1

VSS

J49

VSS

J55

VSS

K8

VSS

K11

VSS

K21

VSS

K51

VSS

L16

VSS

L20

VSS

L22

VSS

L26

VSS

L30

VSS

L34

VSS

L38

VSS

L43

VSS

L48

VSS

L61

VSS

M4

VSS

M6

VSS

U1000

BGA

(9 OF 9)

VSS

SANDY-BRIDGE

MOBILE-2C-35W

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M11
M15

M58

N1
N17

N21
N25

N28

N33
N36

N40

N43
N47

N48

N51
N52

N56
N61

P9

P14
P16

P18

P21
P58

P59

R4
R17

R20
R46

T1

T47
T50

T51

T52
T53

T55

T56
U8

U13
V20

V61

W8
W13

W15

W18
W21

W46

Y4
Y47

Y58
Y59

A5

A57

BC61
BD3

BD59
BE4

BE58

BG5
BG57

C3

C58
D59

E1

E61

A

AA13
AA50

AA51

AA52
AA53

AA55
AA56

AB16

AB18
AB21

AB48

AB61

AC10

AC14
AC46

AD17

AD20

AD61

AE13

AF17

AF21

AF47
AF48

AF50
AF51

AF52

AF53
AF55

AF56

AF58
AF59

AG10
AG14

AG18
AG47

AG52

AG61

AH58

AJ13

AJ16

AJ20
AJ22

AJ26
AJ30

AJ34

AJ38
AJ42

AJ45

AJ48

AK52

AL10
AL13

AL17
AL21

AL25

AL28
AL33

AL36

AL40
AL43

AL47

AL61

AM13
AM20

AM22

AM26
AM30

A9

VSS

A13

VSS

A17

VSS

A21

VSS

A25

VSS

A28

VSS

A33

VSS

A37

VSS

A40

VSS

A45

VSS

A49

VSS

A53

VSS

AA1

VSS

AA8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AC6

VSS
VSS
VSS
VSS

AD4

VSS
VSS
VSS
VSS

AE8

VSS
VSS

AF1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AG7

VSS
VSS
VSS
VSS
VSS
VSS
VSS

AH4

VSS
VSS

AJ7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM4

VSS
VSS
VSS
VSS
VSS
VSS

8 7 5 4 2 1

CRITICAL

U1000

BGA

(8 OF 9)

VSS

SANDY-BRIDGE

MOBILE-2C-35W

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM34
AM38

AM42

AM45
AM48

AM58

AN1
AN21

AN25
AN28

AN33

AN36
AN40

AN43

AN47
AN50

AN54

AP7
AP10

AP51
AP55

AR7

AR13
AR17

AR21

AR41
AR48

AR61

AT4
AT14

AT19
AT36

AT45

AT52
AT58

AU1

AU7
AU11

AU28

AU32
AU51

AV17
AV21

AV22

AV34
AV40

AV48

AV55
AW7

AW13

AW43
AW61

AY4
AY9

AY14

AY19
AY30

AY36

AY41
AY45

AY49

AY55
AY58

BA1
BA11

BA17

BA21
BA26

BA32

BA48
BA51

BB53

BC5
BC13

BC57
BD8

BD12

BD16
BD19

BD23

BD27
BD32

BD36

BD40
BD44

BD48
BD52

BD56

BE5
BG9

345678

36

2 1

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CPU GROUNDS

Apple Inc.

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

14 OF 109

SHEET

13 OF 75

SIZE

D

C

B

A

D

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

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345678

2 1

CPU VCORE DECOUPLING

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

=PPVCORE_S0_CPU

12

9 7

D

C

CRITICAL

1

C1600

2.2UF

20%
4V

2

X5R
402

PLACEMENT_NOTE (C1655-C1666):

Place close to U1000 on top side.

CRITICAL

1

C1655

22UF

20%
4V

2

X5R
402

PLACEMENT_NOTE (C1667-C1679):

CRITICAL

1

C1601

2.2UF

20%
4V

2

X5R
402

CRITICAL

1

C1656

22UF

20%
4V

2

X5R
402

CRITICAL

1

C1602

2.2UF

20%
4V

2

X5R
402

CRITICAL

1

C1657

22UF

20%
4V

2

X5R
402

CRITICAL

1

2

C1603

2.2UF

20%
4V
X5R
402

CRITICAL

1

C1604

2.2UF

20%
4V

2

X5R
402

CRITICAL CRITICAL

1

C1658

22UF

20%
4V

2

X5R
402

CRITICAL

1

C1605

2.2UF

20%
4V

2

X5R
402

1

C1659

22UF

20%
4V

2

X5R
402

CRITICAL

1

C1606

2.2UF

20%
4V

2

X5R
402

CRITICAL

1

2

CRITICAL CRITICAL

1

2

C1660

22UF

20%
4V
X5R
402

C1607

2.2UF

20%
4V
X5R
402

CRITICAL

1

C1661

22UF

20%
4V

2

X5R
402

Processor Load Line : -2.9 mOhms

1

C1608

2.2UF

20%
4V

2

X5R
402

1

2

CRITICAL

C1662

22UF

20%
4V
X5R
402

CRITICAL

1

C1609

2.2UF

20%
4V

2

X5R
402

CRITICAL

1

C1663

22UF

20%
4V

2

X5R
402

CRITICAL

1

C1610

2.2UF

20%
4V

2

X5R
402

CRITICAL

1

C1664

22UF

20%
4V

2

X5R
402

CRITICAL

1

C1611

2.2UF

20%
4V

2

X5R
402

CRITICAL

1

2

CRITICAL

1

C1665

22UF

20%
4V

2

X5R
402

C1612

2.2UF

20%
4V
X5R
402

CRITICAL

1

2

CRITICAL

1

C1666

22UF

20%
4V

2

X5R
402

C1613

2.2UF

20%
4V
X5R
402

CRITICAL

1

C1614

2.2UF

20%
4V

2

X5R
402

CRITICAL

1

C1615

2.2UF

20%
4V

2

X5R
402

D

C

PLACEMENT_NOTE (C1640-C1645):

1

C1680

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1681

270UF

20%
2V

2

TANT TANT
CASE-B2-SM

1

C1682

270UF

20%
2V

2

CASE-B2-SM

1

C1683

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1679

270UF

20%
2V

2

TANT
CASE-B2-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

PLACEMENT_NOTE (C1684-C167F):

Place on bottom side of U1000Place on bottom side of U100.

Place on bottom side of U1000

=PP1V05_S0_CPU_VCCIO

12 10

9 7

B

A

8 7 5 4 2 1

Place on bottom side of U1000

1

C1684

1UF

10%
10V

2

X5R
402

1

C1697

1UF

10%
10V

2

X5R
402

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

1

C161E

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C167D

270UF

20%
2V

2

TANT
CASE-B2-SM

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

1 2

1%

1/4W

MF

0603

1

C1685

1UF

10%
10V

2

X5R
402

1

C1698

1UF

10%
10V

2

X5R
402

1

C161F

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C167E

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1686

2

1

C1699

2

1

C162A

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C167G

270UF

20%
2V

2

TANT
CASE-B2-SM

1UF

10%
10V
X5R
402

1UF

10%
10V
X5R
402

=PP1V05_S0_CPU_VCCPQE

1

C167F

1UF

10%

Note:The smallest 10mOhm available in the library are 0805s

10V

2

X5R
402

1

2

1

C169A

1UF

10%
10V

2

X5R
402

1

C162B

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C167H

270UF

20%
2V

2

TANT
CASE-B2-SM

12

7

C1687

1UF

10%
10V
X5R
402

1

C1688

1UF

10%
10V

2

X5R
402

1

C169B

1UF

10%
10V

2

X5R
402

1

C162C

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1689

1UF

10%
10V

2

X5R
402

1

C169C

1UF

10%
10V

2

X5R
402

1

C162D

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1690

1UF

10%
10V

2

X5R
402

1

C169D

1UF

10%
10V

2

X5R
402

1

C162E

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1691

1UF

10%
10V

2

X5R
402

1

C169E

1UF

10%
10V

2

X5R
402

1

C167A

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1692

2

1

C169F

2

1

C167B

10UF

20%

6.3V

2

CERM-X5R
0402-1

1UF

10%
10V
X5R
402

1UF

10%
10V
X5R
402

1

C1693

2

1

C161A

2

1

C167C

10UF

20%

6.3V

2

CERM-X5R
0402-1

1UF

10%
10V
X5R
402

1UF

10%
10V
X5R
402

1

C1694

1UF

10%
10V

2

X5R
402

1

C161B

1UF

10%
10V

2

X5R
402

1

C1695

1UF

10%
10V

2

X5R
402

1

C161C

1UF

10%
10V

2

X5R
402

1

C1696

1UF

10%
10V

2

X5R
402

1

C161D

1UF

10%
10V

2

X5R
402

=PP1V8_S0_CPU_VCCPLL

7

36

CPU VCCPLL DECOUPLING

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

PLACEMENT_NOTE (C1646-C1671):

Place near U1000 on top side

R1600

0

1 2

5%
1/16W
MF-LF

402

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

CPU VCCPLL Low pass filter

=PP1V8_S0_CPU_VCCPLL_R

1

C160X

1UF

10%
10V

2

X5R
402

SYNC_MASTER=K78_MLB

PAGE TITLE

1

C160Y

1UF

10%
10V

2

X5R
402

PLACE_NEAR=U1000.BC2:5mm

1

C160Z

270UF

20%
2V

2

TANT
CASE-B2-SM

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/08/2011

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

16 OF 109

SHEET

14 OF 75

12

7

B

A

SIZE

D

www.laptopblue.vn

345678

2 1

VAXG DECOUPLING

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

=PPVCORE_S0_CPU_VCCAXG

12

9 7

D

C

PLACEMENT_NOTE (C1700-C1710):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

Place on bottom side of U1000

CRITICAL

1

C1700

1UF 1UF

10%
10V

2

X5R
402

PLACEMENT_NOTE (C1711-C1716):

1

2

CRITICAL

1

C1711

10UF

20%

6.3V

2

CERM-X5R
0402-1

PLACEMENT_NOTE (C1717-C1722):

1

2

CRITICAL

1

C1717

22UF

20%

6.3V

2

X5R-CERM1
0603

PLACEMENT_NOTE (C1723-C1724):

1

C1723

270UF

20%
2V

2

TANT
CASE-B2-SM

1

2

CRITICAL

C1701

10%
10V
X5R
402

CRITICAL

C1712

10UF

20%

6.3V
CERM-X5R
0402-1

CRITICAL

C1718

22UF

20%

6.3V
X5R-CERM1
0603

1

C1724

270UF

20%
2V

2

TANT
CASE-B2-SM

1

2

1

2

C1713

10UF

20%

6.3V
CERM-X5R
0402-1

1

2

CRITICAL

C1702

1UF

10%
10V
X5R
402

CRITICAL

CRITICAL

C1719

22UF

20%

6.3V
X5R-CERM1
0603

1

C1725

270UF

20%
2V

2

TANT
CASE-B2-SM

1

2

1

C1703

2

C1714

10UF

20%

6.3V
CERM-X5R
0402-1

1

C1720

2

CRITICAL

1UF

10%
10V
X5R
402

CRITICAL

CRITICAL

22UF

20%

6.3V
X5R-CERM1
0603

1

2

1

2

C1715

10UF

20%

6.3V
CERM-X5R
0402-1

1

2

C1704

1UF

10%
10V
X5R
402

CRITICAL

CRITICAL

CRITICAL

C1721

22UF

20%

6.3V
X5R-CERM1
0603

Graphics Load Line : -3.9 mOhms

1

2

1

C1705

1UF

10%
10V

2

X5R
402

CRITICAL

C1716

10UF

20%

6.3V
CERM-X5R
0402-1

1

2

CRITICAL

CRITICAL

C1722

22UF

20%

6.3V
X5R-CERM1
0603

1

2

CRITICAL

C1706

1UF

10%
10V
X5R
402

1

2

CRITICAL

C1707

1UF

10%
10V
X5R
402

1

2

CRITICAL

C1708

1UF

10%
10V
X5R
402

1

2

CRITICAL

C1709

1UF

10%
10V
X5R
402

1

2

CRITICAL

C1710

1UF

10%
10V
X5R
402

D

C

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

=PP1V5_S3_CPU_VCCDDR

26 12 10

7

B

A

8 7 5 4 2 1

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U100.

1

C1738

1UF

10%
10V

2

X5R
402

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

1

C1748

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1756

270UF

20%
2V

2

TANT
CASE-B2-SM

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1702

1 2

0.010

1

C1739

1UF

10%
10V

2

X5R
402

1

C1749

10UF

20%

6.3V

2

CERM-X5R
0402-1 0402-1

=PP1V5_S3_CPU_VCCDQ

1%

1/4W

MF

0603

1

C1740

1UF

10%
10V

2

X5R
402

1

C1750

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1757

1UF

10%
10V

2

X5R
402

CPU VCCSA DECOUPLING

1

C1741

1UF

10%
10V

2

X5R
402

1

C1751

10UF

20%

6.3V

2

CERM-X5R

12

7

1

C1742

1UF

10%
10V 10V

2

X5R
402

1

C1752

10UF

20%

6.3V

2

CERM-X5R
0402-1 0402-1

1

C1743

1UF

10%

2

X5R X5R
402

1

C1753

10UF

20%

6.3V

2

CERM-X5R

1

2

1

C1744

2

C1754

10UF

20%

6.3V
CERM-X5R
0402-1

1

1UF

10%
10V

402

C1745

1UF

10% 10%
10V

2

X5R
402

1

C1755

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

2

C1746

1UF

10V
X5R
402

1

C1747

1UF

10%
10V

2

X5R
402

12

7

=PPVCCSA_S0_CPU

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

PLACEMENT_NOTE (C1758-C1762):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

Place on bottom side of U1000

1

C1758

1UF

10%
10V

2

X5R
402

1

C1763

10UF

20%

6.3V

2

CERM-X5R
0402-1 0402-1

1

C1768

270UF

20%
2V

2

TANT
CASE-B2-SM

1

2

1

2

C1759

1UF

10%
10V
X5R
402

C1764

10UF

20%

6.3V
CERM-X5R

1

2

1

2

C1765

10UF

20%

6.3V
CERM-X5R
0402-1

C1760

1UF

10%
10V
X5R
402

1

C1761

1UF

10%
10V

2

X5R
402

1

C1766

10UF

20%

6.3V

2

CERM-X5R
0402-1 0402-1

SYNC_MASTER=K78_MLB

PAGE TITLE

1

2

1

2

C1762

1UF

10%
10V
X5R
402

C1767

10UF

20%

6.3V
CERM-X5R

CPU DECOUPLING-II

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/10/2011

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

17 OF 109

SHEET

15 OF 75

SIZE

B

A

D

36

SYSCLK_CLK32K_RTC

IN

PCH_SRTCRST_L
RTC_RESET_L

D

PCH_INTRUDER_L
PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_SYNC_R

PCH_SPKR

HDA_RST_R_L

HDA_SDIN0

IN

TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3

HDA_SDOUT_R

JTAG_T29_TMS

IN

ENET_MEDIA_SENSE

IN

XDP_PCH_TCK

IN

XDP_PCH_TMS

IN

XDP_PCH_TDI

C

IN

XDP_PCH_TDO

OUT

SPI_CLK_R

OUT

SPI_CS0_R_L

OUT

TP_SPI_CS1_L
SPI_MOSI_R

OUT

SPI_MISO

IN

ENET_MEDIA_SENSE

1

R1899

10K

5%

1/20W

MF

201

2

B

=PPVRTC_G3_PCH

1

1

R1802

20K

1/20W

201

1

201

5%
MF

2

NOSTUFF

R1880

1 2

1/20W

1

R1801

1M

5%
1/20W
MF
201

2

C1802

1.0UF

0201-MUR

0

5%
MF

201

20%

6.3V
X5R

R1800

330K

1/20W

A

HDA_SDOUT_R

Pullup needed for SPI_DESCRIPTOR_OVERRIDE_L? PD needed for BCM_MEDIA_SENSE?

PLACE_NEAR=R1813.1:2.54mm

R1803

5%
MF

2

2

1

1

2

2

SPI_DESCRIPTOR_OVERRIDE_L

8 7 5 4 2 1

A19

RTCX1

C19

RTCX2

NC

A23

SRTCRST*

F19

RTCRST*

K22

INTRUDER*

C21

INTVRMEN

H35

HDA_BCLK

H37

HDA_SYNC

N1

SPKR

F35

HDA_RST*

D36

HDA_SDIN0

B36

HDA_SDIN1

C35

HDA_SDIN2

A35

HDA_SDIN3

K37

HDA_SDO

K35

HDA_DOCK_EN*/GPIO33

M35

HDA_DOCK_RST*/GPIO13

M17

JTAG_TCK

M15

JTAG_TMS

U12

JTAG_TDI

M12

JTAG_TDO

AD12

SPI_CLK

AB8

SPI_CS0*

AB6

SPI_CS1*

W8

SPI_MOSI

Y2

SPI_MISO

=PP3V3_T29_PCH_GPIO

=PP3V3_S0_PCH_STRAPS

R1851

10K

1/20W

201

20K

5%
1/20W
MF
201

RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L

C1803

1.0UF

20%

6.3V
X5R
0201-MUR

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME*

LDRQ1*/GPIO23

LPC

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN

SATA

SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO
SATAICOMPI

SATALED*

SATA0GP/GPIO21
SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

1

R1844

10K

5%

1/20W

MF

201

2

LDRQ0*

SERIRQ

5%
MF

1

R1846

2

U1800

COUGAR-POINT

MOBILE-SFF

FCBGA

(1 OF 10)

OMIT_TABLE

RTC

IHDA

JTAG

SPI

1

R1845

10K

5%

1/20W

MF

201

2

=PP3V3_S0_PCH_STRAPS

=PP3V3_SUS_GPIO

R1847

10K

1/20W

201

NOSTUFF

R1849

5%
MF

10K

1/20W

201

1

R1850

2

1

5%
MF

2

1

R1848

10K

5%

1/20W

MF

201

2

OUT

=PP3V3R1V5_S0_PCH_VCCSUSHDA

NOSTUFF

1

R1866

10K

5%

1/20W

MF

201

2

=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S0_PCH

A37
A39
C39
C37

K40

H40
F37

Y4

AN3
AN1
AU3
AU1

AN6
AN8
AR3
AR1

AD4
AD2
AL3
AL1

AD8
AD6
AG3
AG1

AE3
AE1
AH8
AH6

AC3
AC1
AJ3
AJ1

AB10
AB12

W10

M2
R1

AF12
AF10

AH4

1

10K

5%

1/20W

MF

201

2

NOSTUFF

R1833

10K

1/20W

201

1

10K

5%

1/20W

MF

201

2

HDA_SYNC_R

HDA_SDOUT_R

5%
MF

LPC_R_AD<0>
LPC_R_AD<1>
LPC_R_AD<2>
LPC_R_AD<3>
LPC_FRAME_R_L

TP_LPC_DREQ0_L
T29_PWR_EN_PCH

LPC_SERIRQ

SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P

TP_SATA_B_D2RN
TP_SATA_B_D2RP
TP_SATA_B_R2D_CN
TP_SATA_B_R2D_CP

SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P

TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP

TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP

TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP

PCH_SATAICOMP

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

PCH_SATALED_L
DP_AUXCH_ISOL

SATARDRVR_EN

PCH_SATA3COMP
PCH_SATA3RBIAS

1

4.7K

5%

1/20W

MF

201

R1834

R1842

2

10K

5%

1/20W

MF

201

1

2

R1878

1

2

PCIECLKRQ0_L_GPIO73
PCIECLKRQ5_L_GPIO44
PEG_B_CLKRQ_L_GPIO56

PLACE_NEAR=U1800.AF12:2.54mm

1

R1877

10K

1/20W

SATARDRVR_EN

4.7K

5%

1/20W

MF

201

2

DP_AUXCH_ISOL

www.laptopblue.vn

37.4

1/20W

5%

1/20W

MF

201

33

5%

1/20W

MF

201

33

5%

1/20W

MF

201

201

0

PLACE_NEAR=U1800.AB10:2.54mm

1

1%
MF

2

NOSTUFF

R1841

0

1 2

5%

1/20W

MF

201

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

NC_PCIE_1_D2RN
NC_PCIE_1_D2RP
NC_PCIE_1_R2D_CN
NC_PCIE_1_R2D_CP

PCIE_AP_D2R_N

IN

PCIE_AP_D2R_P

IN

PCIE_AP_R2D_C_N

OUT

PCIE_AP_R2D_C_P

OUT

NC_PCIE_3_D2RN
NC_PCIE_3_D2RP
NC_PCIE_3_R2D_CN
NC_PCIE_3_R2D_CP

PCIE_EXCARD_D2R_N

IN

PCIE_EXCARD_D2R_P

IN

PCIE_EXCARD_R2D_C_N

OUT

PCIE_EXCARD_R2D_C_P

OUT

NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP

NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP

NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP

TP_PCIE_CLK100M_PE0N
TP_PCIE_CLK100M_PE0P

PCIECLKRQ0_L_GPIO73
PCIE_CLK100M_AP_N

OUT

PCIE_CLK100M_AP_P

OUT

AP_CLKREQ_L

IN

TP_PCIE_CLK100M_PE2N
TP_PCIE_CLK100M_PE2P

PCIECLKRQ2_L_GPIO20
PCIE_CLK100M_EXCARD_N

OUT

PCIE_CLK100M_EXCARD_P

OUT

EXCARD_CLKREQ_L

IN

PCIE_CLK100M_T29_N

OUT

PCIE_CLK100M_T29_P

OUT

T29_CLKREQ_L

IN

TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P

PCIECLKRQ5_L_GPIO44
TP_PCIE_CLK100M_PEBN

TP_PCIE_CLK100M_PEBP
PEG_B_CLKRQ_L_GPIO56
TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE6P
WOL_EN
TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE7P
PCH_GPIO46
ITPXDP_CLK100M_N

ITPXDP_CLK100M_P

ITPCPU_CLK100M_N

OUT

OUT

OUT

OUT

IN

R1860

1 2

33

5%

1/20W

R1861

1 2

33

5%

1/20W

R1862

1 2

33

1/20W

5%

R1863

1 2

33

5%

1/20W

R1864

1 2

33

1/20W

5%

OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

LPC_AD<0>

MF

201

LPC_AD<1>

MF

201

LPC_AD<2>

201

MF

LPC_AD<3>

MF

201

LPC_FRAME_L

201

MF

(IPU)

BI

BI

BI

BI

BI

R1830

1

R1820

10K

5%
1/20W
MF
201

2

BI

=PP1V05_S0_PCH

1

R1831

49.9

1%

1/20W

MF

201

2

1

R1832

750

PLACE_NEAR=U1800.AH4:2.54mm

1%

1/20W

MF

201

2

R1876

10K

1/20W

201

1

5%
MF

2

HDA_BIT_CLK_R

HDA_SYNC_R

PLACE_NEAR=U1800.F35:1.27mm

HDA_RST_R_L

HDA_SDOUT_R

JTAG_T29_TMS
PCH_SPKR
AP_CLKREQ_L
PCH_SATALED_L
EXCARD_CLKREQ_L
T29_CLKREQ_L
PEG_CLKREQ_L
PCIECLKRQ2_L_GPIO20

NOSTUFF

R1840

33

5%
MF

33

5%
MF

1 2

PLACE_NEAR=U1800.H37:1.27mm

R1811

1 2

PLACE_NEAR=U1800.K37:1.27mm

R1813

1 2

ITPXDP_CLK100M_N

ITPXDP_CLK100M_P ITPCPU_CLK100M_P

PLACE_NEAR=U1800.H35:1.27mm

R1810

1 2

1/20W

201

R1812

1 2

1/20W

201

201

1

5%
MF

2

=PP3V3_SUS_GPIO

SML_PCH_0_ALERT_L
SML_PCH_1_ALERT_L

SMC_SCI_L

BJ33

PERN1

BL33

PERP1

BB30

PETN1

AY30

PETP1

BJ35

PERN2

BL35

PERP2

BB33

PETN2

AY33

PETP2

BH36

PERN3

BK36

PERP3

BF33

PETN3

BD33

PETP3

BJ37

PERN4

BL37

PERP4

BD35

PETN4

BF35

PETP4

BJ39

PERN5

BL39

PERP5

AY35

PETN5

BB35

PETP5

BH40

PERN6

BK40

PERP6

BD37

PETN6

BF37

PETP6

BJ41

PERN7

BL41

PERP7

AY37

PETN7

BB37

PETP7

BJ43

PERN8

BL43

PERP8

AY40

PETN8

BB40

PETP8

AD48

CLKOUT_PCIE0N

AD50

CLKOUT_PCIE0P

M4

PCIECLKRQ0*/GPIO73

AE49

CLKOUT_PCIE1N

AE51

CLKOUT_PCIE1P

U8

PCIECLKRQ1*/GPIO18

AD40

CLKOUT_PCIE2N

AD42

CLKOUT_PCIE2P

T4

PCIECLKRQ2*/GPIO20

AA49

CLKOUT_PCIE3N

AA51

CLKOUT_PCIE3P

B8

PCIECLKRQ3*/GPIO25

Y48

CLKOUT_PCIE4N

Y50

CLKOUT_PCIE4P

M19

PCIECLKRQ4*/GPIO26

AB40

CLKOUT_PCIE5N

AB42

CLKOUT_PCIE5P

K8

PCIECLKRQ5*/GPIO44

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

PEG_B_CLKRQ*/GPIO56

AB44

CLKOUT_PCIE6N

AB46

CLKOUT_PCIE6P

J3

PCIECLKRQ6*/GPIO45

W44

CLKOUT_PCIE7N

W46

CLKOUT_PCIE7P

H4

PCIECLKRQ7*/GPIO46

AR12

CLKOUT_ITPXDP_N

AR10

CLKOUT_ITPXDP_P

345678

U1800

COUGAR-POINT

MOBILE-SFF

FCBGA

(2 OF 10)

OMIT_TABLE

PCI-E*

SMBALERT*/GPIO11

SML0ALERT*/GPIO60

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

LINK

CNTRL

PEG_A_CLKRQ*/GPIO47

CLK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA1

CL_RST1*

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

2 1

=PP1V05_S0_PCH_VCCDIFFCLK

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

H12

F17
F10

H22

K12
A9

C9

D12
C11

L3

J1

M8

R8

AF44
AF46

BB24
AY24

AN10
AN12

BD17
BF17

BB26
AY26

M24
K24

AK8
AK6

J49

E51

W49
W51

AC49

H50

D48

G49

J51

NC

PCH_GPIO11
SMBUS_PCH_CLK

SMBUS_PCH_DATA

SML_PCH_0_ALERT_L
SML_PCH_0_CLK

SML_PCH_0_DATA

SML_PCH_1_ALERT_L
SML_PCH_1_CLK

SML_PCH_1_DATA

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

PEG_CLKREQ_L
PEG_CLK100M_N

PEG_CLK100M_P
DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P
TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP
PCIE_CLK100M_PCH_N

PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1

PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN

DOES THIS NEED LENGTH MATCH???

SYSCLK_CLK25M_SB_R

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

PLACE THIS RESISTOR NEAR THE PCH PIN

R1885

1 2

604

1/20W

1%201 MF

1.5V -> 1.1V

PLACE_NEAR=U1800.W49:2.54mm

OUT

BI

OUT

BI

OUT

BI

IN

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN

IN

PLACE_NEAR=U1800.W49:5.1mm

1

R1870

10K

5%

1/20W

MF

201

2

SYSCLK_CLK25M_SB

1

R1886

1K

1%
1/20W
MF
201

2

PLACE_NEAR=R1885.1:2.54mm

R1890

90.9

1/20W

201

1

R1871

10K

5%
1/20W
MF
201

2

IN

1

1%
MF

2

D

C

B

1

R1853

10K

5%
1/20W1/20W
MF

SYNC_MASTER=K21_MLB

201

PAGE TITLE

2

PCH SATA/PCIE/CLK/LPC/SPI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

18 OF 109

SHEET

16 OF 75

SIZE

A

D

NOSTUFF

R1888

0

1 2

5%

1/20W

MF

201

1

R1854

10K

5%
1/20W
MF
201

2

PCH_GPIO11

1

R1855

10K

5%
MF

201

2

36

R1905

D

C

B

10K

1/20W

201

www.laptopblue.vn

=PP3V3_SUS_GPIO

1

5%
MF

2

1

R1920

750

1%
1/20W
MF
201

2

=PP1V05_S0_PCH_VCCIO_PCIE

1

R1900

49.9

1%
1/20W
MF

PLACE_NEAR=U1800.BF19:12.7mm

201

2

PLACE_NEAR=U1800.BK20:2.54mm

DMI_N2S_N<0>

IN

DMI_N2S_N<1>

IN

DMI_N2S_N<2>

IN

DMI_N2S_N<3>

IN

DMI_N2S_P<0>

IN

DMI_N2S_P<1>

IN

DMI_N2S_P<2>

IN

DMI_N2S_P<3>

IN

DMI_S2N_N<0>

OUT

DMI_S2N_N<1>

OUT

DMI_S2N_N<2>

OUT

DMI_S2N_N<3>

OUT

DMI_S2N_P<0>

OUT

DMI_S2N_P<1>

OUT

DMI_S2N_P<2>

OUT

DMI_S2N_P<3>

OUT

PCH_DMI2RBIAS

PCH_DMI_COMP

PM_SYSRST_L

IN

PM_PCH_SYS_PWROK

IN

PM_PCH_PWROK

IN

PM_MEM_PWRGD

OUT

PM_DSW_PWRGD

IN

PM_PCH_APWROK

IN

PM_RSMRST_L

IN

PCH_SUSWARN_L

OUT

PM_PWRBTN_L

IN

SMC_ADAPTER_EN

IN

PM_BATLOW_L

IN

PCH_RI_L

BL21

DMI0RXN

BL23

DMI1RXN

BJ19

DMI2RXN

BL17

DMI3RXN

BJ21

DMI0RXP

BJ23

DMI1RXP

BL19

DMI2RXP

BJ17

DMI3RXP

BD22

DMI0TXN

BB22

DMI1TXN

BB19

DMI2TXN

BB17

DMI3TXN

BF22

DMI0TXP

AY22

DMI1TXP

AY19

DMI2TXP

AY17

DMI3TXP

BK20

DMI2RBIAS

BF19

DMI_ZCOMP

BD19

DMI_IRCOMP

L1 D8

SYS_RESET*

M10

SYS_PWROK

M22

PWROK

B12

DRAMPWROK

A21

DPWROK

G3

APWROK

B20

RSMRST*

C13

SUSWARN*/SUSPWRDNACK/GPIO30

K19

PWRBTN*

H19

ACPRESENT/GPIO31

H10

BATLOW*/GPIO72

F12

RI*

1

R1909

100K

5%
1/20W
MF
201

2

U1800

COUGAR-POINT

MOBILE-SFF

FCBGA

(3 OF 10)

DMI

MANAGEMENT

SYSTEM POWER

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low
Set to Vcc when High

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4

OMIT_TABLE

FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0
FDI_FSYNC1

FDI_LSYNC0
FDI_LSYNC1

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

PMSYNCH

SLP_LAN*/GPIO29

DSWVRMEN

SLP_SUS*

SUSACK*

BL13
BJ15
BD12
BJ11
AY15
AY12
BJ9
BF10

BJ13
BL15
BF12
BL11
BB15
BB12
BL9
BD10

BB10

BH12
BK8

BK12
BH8

T2

G6

D3

F6

K10

D4

C7

BB8

A7

F22
A15

F15

FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>

FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>

FDI_INT
FDI_FSYNC<0>

FDI_FSYNC<1>
FDI_LSYNC<0>

FDI_LSYNC<1>

=T29_WAKE_L

PCIE_WAKE_L

MAKE_BASE=TRUE

PM_CLKRUN_L

LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L

PM_SYNC
GPIO29_SLP_LAN_L

PCH_DSWVRMEN
PM_SLP_SUS_L
PCH_SUSACK_L

LVDS_IG_BKL_ON

OUT

LVDS_IG_PANEL_PWR

OUT

LVDS_IG_BKL_PWM

OUT

1

R1955

100K

5%

1/20W

MF

201

2

OUT

OUT
OUT

OUT
OUT

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

=PPVRTC_G3_PCH

1

R1915

390K

5%

1/20W

MF

201

2

TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA

TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC

PCH_DAC_IREF

IN

1

R1951

1K

5%
1/20W

PLACE_NEAR=U1800.R51:2.54mm

MF
201

2

M44
M42

L49

L51

NC

K46

NC

R42

NC

M40

NC

AH42

NC

AH40

NC

AG51

NC

AG49

NC

AK44

NC

AK46

NC

AR46

NC

AN49

NC

AN44

NC

AK40

NC

AR44

NC

AN51

NC

AN46

NC

AK42

NC

AH46

NC

AH44

NC

AM50

NC

AL49

NC

AJ51

NC

AH50

NC

AM48

NC

AL51

NC

AJ49

NC

AH48

NC

M46
R46
U46

R49
N49

M50
N51

R51
T48

345678

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK
L_DDC_DATA

L_CTRL_CLK
L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK*
LVDSA_CLK

LVDSA_DATA_0*
LVDSA_DATA_1*
LVDSA_DATA_2*
LVDSA_DATA_3*

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK*
LVDSB_CLK

LVDSB_DATA_0*
LVDSB_DATA_1*
LVDSB_DATA_2*
LVDSB_DATA_3*

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

U1800

COUGAR-POINT

MOBILE-SFF

FCBGA

(4 OF 10)

OMIT_TABLE

LVDS

CRT

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DIGITAL DISPLAY INTERFACE

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

2 1

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AU40
AU42

AR51
AR49

AT50
AT48

W42
R44

AW51
AW49
AY42

AY48
AY50
AY44
AY46
BB44

BB46
BA49

BA51

T50
U44

AU51
AU49
BE46

BC49
BC51
BD48
BD50
BF46
BF45
BE49
BE51

M48
U42

AU46
AU44
BK44

BG51
BG49
BF42
BD42
BJ47
BL47
BL45
BJ45

TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP

TP_SDVO_STALLN
TP_SDVO_STALLP

TP_SDVO_INTN
TP_SDVO_INTP

DP_IG_B_DDC_CLK
DP_IG_B_DDC_DATA

DP_IG_B_AUX_N
DP_IG_B_AUX_P
DP_IG_B_HPD

TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>

TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUXN
TP_DP_IG_C_AUXP
TP_DP_IG_C_HPD

TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>

D

C

B

R1986

0

PCH_SUSWARN_L

5%

1/20W

MF

201

12

=PP3V3_SUS_GPIO
=PP3V3_S5_PCH

=PP3V3_SUS_GPIO

NOSTUFF

R1925

1K

1/20W

201

1

1

R1985

1%
MF

1K

1%
1/20W
MF

2

2

201

R1984

10K

1/20W

201

1

R1982

5%
MF

10K

5%

1/20W

MF

201

2

A

8 7 5 4 2 1

1

2

PCH_SUSACK_L

R1983

10K

1/20W

201

1

5%
MF

2

GPIO29_SLP_LAN_L
PM_BATLOW_L

PM_PWRBTN_L
PCIE_WAKE_L

PCH_SUSWARN_L

=PP3V3_S0_PCH_STRAPS

R1991

8.2K

5%

1/20W

MF

201

1

2

PM_CLKRUN_L

SIZE

A

D

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

36

PCH DMI/FDI/GRAPHICS

Apple Inc.

R

.

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

19 OF 109

SHEET

17 OF 75

www.laptopblue.vn

345678

2 1

DF_TVS

USBP0N
USBP0P

USBP1N
USBP1P

USBP2N
USBP2P

USBP3N
USBP3P

USBP4N
USBP4P

USBP5N
USBP5P

USBP6N
USBP6P

USBP7N
USBP7P

USBP8N
USBP8P

USBP9N
USBP9P

USBP10N
USBP10P

USBP11N
USBP11P

USBP12N
USBP12P

USBP13N
USBP13P

BE3
BE1
AU8
BJ7

BA3
BH3

AU6
AW3
AW1
AY6
AY2
AY4
BC3
BC1
BG1
BG3
BE6
BH4
BF7
BJ4
BJ5
BK6

AY8
BC7

BL5

BB6

BD2
BD4

BA1
BF6

F24
H24

C25
A25

C27
A27

H28
F28

M26
K26

D28
B28

H26
F26

D32
B32

M28
K28

C29
A29

C31
A31

H33
F33

H30
F30

M33
K33

C33
A33

C17
A17
A13
D16
A11
B16
C23
H15

NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

NC
NC
NC

NC
NC

NC

PCH_DF_TVS

USB_HUB1_UP_N
USB_HUB1_UP_P

NC_USB_1N
NC_USB_1P

NC_USB_2N
NC_USB_2P

NC_USB_3N
NC_USB_3P

NC_USB_4N
NC_USB_4P

NC_USB_5N
NC_USB_5P

NC_USB_6N
NC_USB_6P

NC_USB_7N
NC_USB_7P

USB_HUB2_UP_N
USB_HUB2_UP_P

USB_CAMERA_N
USB_CAMERA_P

NC_USB_10N
NC_USB_10P

NC_USB_11N
NC_USB_11P

NC_USB_12N
NC_USB_12P

NC_USB_13N
NC_USB_13P

R2081

2.2K

1/20W

R2080

1K

1 2

5%

1/20W

MF

201

PCH_USB_RBIAS

68

=PP1V8_S0_PCH_VCC_DFTERM

1

5%
MF

201

2

CPU_PROC_SEL_L

24 68

BI

USB HUB 1

24 68

BI

Unused

Unused

Unused

Unused

Unused

Unused

Unused

BI

USB HUB 2

BI

BI

Camera

BI

Unused

Unused

Unused

Unused

R2060

1

R2070

22.6

1%

1/20W

MF

PLACE_NEAR=U1800.C33:2.54mm

201

2

10K

1/20W

201

D

C

B

=PP3V3_S3_PCH_GPIO
=PP3V3_SUS_GPIO

1

10K

201

R2065

10K

5%

201

1

R2067

MF

10K

2

5%
1/20W
MF
201

2

R2069

1/20W

1

R2064

1

10K

5%

5%

1/20W
MF
201

MF

2

2

1

R2061

10K

5%
1/20W
MF
201

2

NOSTUFF

1

R2062

5%
MF

1/20W

2

10K

1/20W

201

1

R2068

10K

5%
1/20W
MF
201

2

1

5%
MF

2

PCH_GPIO59_OC0_L

USB_HUB_SOFT_RESET_L

SDCONN_STATE_RST_L
ENET_PWR_EN
PCH_GPIO43_OC4_L
SDCONN_STATE_CHANGE
PCH_GPIO10_OC6_L
PCH_GPIO14_OC7_L

SYNC_MASTER=K21_MLB

PAGE TITLE

PUs TO S0 INSTEAD?

PCH PCI/FLASHCACHE/USB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

19

7

19 17 16

7

NOTE: PULLUP IS REQUIRED
ON AP_PWR_EN IF ISOLATION RESISTOR
R2090 IS UNSTUFFED

R2090

0

12

AP_PWR_EN

5%

1/20W

MF

201

23

23

23

23

23

23

DRAWING NUMBER

051-8870

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=12/13/2010

3.13.0

20 OF 109

18 OF 75

SIZE

A

D

36

BH24
BK24
BH20
BK16
BH16
AN42
AN40
AR40
AR42

D20
M30

AM4
AT4
AT2

AD10

B24

D24
AD44
AD46

BJ48

BL7

W40

K30
BH49
BB42

BJ25
BJ27
BJ31
BJ29
BL25
BL27
BL31
BL29
BF26
BB28
BF28
BF30
BD26
AY28
BD28
BD30

D49

C48

C47

C45

G46

K44

F46

F42

H42

D44

A47

C41

F45

F40

G51

E49

H48

J43

G45

E3

H2

F7

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

TP21
TP22
TP23
TP24
TP41
TP42

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA*
PIRQB*
PIRQC*
PIRQD*

REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54

GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55

PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5

PME*

PLTRST*

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

NC
NC
NC
NC

D

FIXME: NEED INTEL APPROVAL OF NC ON TPS

TP_PM_TEST_RST_L

C

=PP3V3_S0_PCH_GPIO

7

R2010
R2011
R2012
R2013

R2016
R2017
R2018

R2030

B

R2031

R2015

PCH_PCI_GNT3_L

18

PCH_PCI_GNT2_L

18

PCH_PCI_GNT1_L

18

NOSTUFF

A

R2052

1/20W

10K

201

10K
10K
10K
10K

10K
10K
10K

10K
10K

201 MF5%

10K

201

NOSTUFF

1

R2053

5%
MF

10K

1/20W

2

201

5%
MF

NOSTUFF

1

2

12
12
12
12

12
12
12

12
12

39

12

5%

NOSTUFF

R2054

10K

1/20W

63

201

1/20W
1/20W
1/20W
1/20W

1/20W
1/20W
1/20W

1/20W
1/20W

6

1/20W

5%
MF

MF201 5%
MF201 5%
MF201 5%
MF201 5%

MF201 5%
MF201 5%
MF201 5%

MF201 5%

IN
IN

MF

1

2

PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L

JTAG_GMUX_TMS
T29_A_HV_EN_L
PCI_REQ3_L

PCH_PCI_GNT1_L

18

PCH_PCI_GNT2_L

18

PCH_PCI_GNT3_L

18

PCI_INTE_L
AUD_IP_PERIPHERAL_DET

39

6

IN

T29_MCU_INT_L
AUD_I2C_INT_L

TP_PCI_PME_L

6

PLT_RESET_L

26 25

OUT

LPC_CLK33M_SMC_R

69 25

OUT

LPC_CLK33M_LPCPLUS_R

25

OUT

TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3

6

PCH_CLK33M_PCIOUT

25

OUT

NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

U1800

COUGAR-POINT

MOBILE-SFF

FCBGA

(5 OF 10)

OMIT_TABLE

RSVD

TP

PCI

USB

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43

OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

RSVD_BE3
RSVD_BE1
RSVD_AU8
RSVD_BJ7

RSVD_BA3
RSVD_BH3

RSVD_AU6
RSVD_AW3
RSVD_AW1
RSVD_AY6
RSVD_AY2
RSVD_AY4
RSVD_BC3
RSVD_BC1
RSVD_BG1
RSVD_BG3
RSVD_BE6
RSVD_BH4
RSVD_BF7
RSVD_BJ4
RSVD_BJ5
RSVD_BK6

RSVD_AY8

RSVD_BL5

RSVD_BB6

RSVD_BD2
RSVD_BD4

RSVD_BA1
RSVD_BF6

USBRBIAS*

USBRBIAS

8 7 5 4 2 1

www.laptopblue.vn

345678

2 1

D

C

B

JTAG_ISP_TCK
ODD_PWR_EN_L
GMUX_INT

=PP3V3_SUS_GPIO

NOSTUFF

R2195

=PP3V3_S5_PCH

R2191

10K

1/20W

=PP3V3_T29_PCH_GPIO
=PP3V3_S0_PCH_STRAPS

201

5%
MF

10K

1/20W

1

2

201

1

=PP3V3_S0_PCH

R2150

10K

5%

1/20W

MF

201

NOSTUFF

SMC_IG_THROTTLE_L

IN

FW_PME_L

IN

GMUX_INT

=PP3V3_S0_PCH

1

R2190

100K

5%

1/20W

MF

201

BI

R2112

1/20W

201

R2193

100K

5%
MF

1/20W

201

1

2

1

5%
MF

2

1

R2111

20K

5%

1/20W

MF

201

2

R2192

10K

1/20W

201

1

5%
MF

2

1

5%
MF

2

1

R2113

10K10K

5%

1/20W

MF

201

2

1

R2194

10K

5%

1/20W

MF

201

2

SPIROM_USE_MLB

ISOLATE_CPU_MEM_L

(NC-ed per Intel chklist)

PCH_GPIO12

PCH_GPIO24

2

(PU necessary?)

(PU necessary?)

(PUs necessary?)

IN

SMC_RUNTIME_SCI_L

IN

NC_GPIO8
PCH_GPIO12
PCH_GPIO15

AUD_IPHS_SWITCH_EN_PCH

OUT

LPCPLUS_GPIO

ODD_PWR_EN_L

OUT

PCH_GPIO24

SMC_SCI_L

IN

ISOLATE_CPU_MEM_L

OUT

T29_SW_RESET_L
PCH_GPIO35
PCH_GPIO36_SATA2GP
JTAG_ISP_TCK

OUT

JTAG_ISP_TDO

IN

JTAG_ISP_TDI
FW_PWR_EN
ENET_LOW_PWR
SPIROM_USE_MLB

BI

MLB_RAM_CFG3
MLB_RAM_CFG2
MLB_RAM_CFG1
MLB_RAM_CFG0

(IPU)

(IPU)

SMC_SCI_L

R2160

10K

1/20W

201

5%
MF

1

R2184

2

10K

201

5%
MF

1

2

R2185

10K

1/20W1/20W

201

1

5%
MF

2

R2186

10K

1/20W

201

1

5%
MF

2

AUD_IPHS_SWITCH_EN_PCH

IN

JTAG_ISP_TDO
FW_PME_L

FW_PWR_EN
SMC_IG_THROTTLE_L

BMBUSY*/GPIO0

B40

TACH1/GPIO1

C43

TACH2/GPIO6

A45

TACH3/GPIO7

H17

GPIO8
LAN_PHY_PWR_CTRL/GPIO12

K6

GPIO15

AA3

SATA4GP/GPIO16

B44

TACH0/GPIO17

W3

SCLOCK/GPIO22

K15

GPIO24/MEM_LED

C15

GPIO27

G1

GPIO28

R3

STP_PCI*/GPIO34

W12

GPIO35

W6

SATA2GP/GPIO36

M6

SATA3GP/GPIO37

N3

SLOAD/GPIO38

U10

SDATAOUT0/GPIO39

U1

SDATAOUT1/GPIO48

AA1

SATA5GP/GPIO49

K17

GPIO57

K42

TACH4/GPIO68

A43

TACH5/GPIO69

D40

TACH6/GPIO70

A41

TACH7/GPIO71

=PP3V3_S3_PCH_GPIO

T29_PWR_EN_PCH

IN

PM_PCH_PWROK

R2152

0

12

AUD_IPHS_SWITCH_EN_PCH_R

5%

1/20W

MF

201

PM_PCH_PWROK

U1800

COUGAR-POINT

MOBILE-SFF

FCBGA

(6 OF 10)

OMIT_TABLE

GPIO

5

A

U2150

6

B

MISC

NCTF

8

08

4

CPU

VSS_NCTF_A4
VSS_NCTF_A48
VSS_NCTF_A49

VSS_NCTF_A5
VSS_NCTF_A51
VSS_NCTF_BH1

VSS_NCTF_BH51

VSS_NCTF_BJ1
VSS_NCTF_BJ3

VSS_NCTF_BJ49
VSS_NCTF_BJ51

VSS_NCTF_BL1
VSS_NCTF_BL3
VSS_NCTF_BL4

VSS_NCTF_BL48
VSS_NCTF_BL49
VSS_NCTF_BL51

VSS_NCTF_C3
VSS_NCTF_C49
VSS_NCTF_C51

VSS_NCTF_D1
VSS_NCTF_D51

VSS_NCTF_E1

74LVC2G08GT

SOT833

3

Y

1

2

PROCPWRGD
THRMTRIP*
INIT3_3V*

A

U2150

B

A20GATE

PECI

RCIN*

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC_1

74LVC2G08GT

8

08

4

SOT833

7

Y

U3W1
AU12
U6
AU10
BC9
R6C5

AK10
AH12
AK12
AH10

U40

A4
A48
A49
A5
A51
BH1
BH51
BJ1
BJ3
BJ49
BJ51
BL1
BL3
BL4
BL48
BL49
BL51
C3
C49
C51
D1
D51
E1

PCH_A20GATE
PCH_PECI CPU_PECI
PCH_RCIN_L
PCH_PROCPWRGD
PM_THRMTRIP_L_R
PCH_INIT3V3_L

ALL RSVD TPs NC-ed per INTEL approval

1

2

2

R2170

43

1 2

1/20W

5%

C2152

0.1UF

10%
16V
X5R-CERM
0201

T29_PWR_EN

AUD_IPHS_SWITCH_EN

MF

201

OUT

1

R2155

10K

5%
1/20W
MF
201

2

R2140

0

1 2

201MF1/20W

5%

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

CPU_PWRGD

=PP3V3_T29_PCH_GPIO

OUT

R2156

OUT

390

1/20W

1 2

201

5%

PM_THRMTRIP_L

MF

=PP3V3_S0_PCH_STRAPS

1

R2196

10K

5%

1/20W

MF

201

2

1

R2199

10K

5%

1/20W

MF

201

2

NOSTUFF

1

R2198

10K

5%

1/20W

MF

201

2

IN

PCH_INIT3V3_L

NOSTUFF

R2197

10K

5%

1/20W

MF

201

1

R2110

10K

5%

1/20W

MF

201

2

NOSTUFF

R2130

1/20W

1

2

T29_SW_RESET_L

SMC_RUNTIME_SCI_L

PCH_GPIO36_SATA2GP

1

1K

5%
MF

201

2

JTAG_ISP_TDI

ENET_LOW_PWR

D

C

B

WOL_EN

R2114

1/20W

201

1

5%
MF

2

=PP3V3_SUS_GPIO

R2115

10K10K

1/20W

201

1

5%
MF

2

PCH_GPIO46

=PP3V3_S0_PCH_STRAPS

A

DRAM_CFG0:H

R2175

10K

1/20W

201

DRAM_CFG1:H

R2174

1

5%
MF

2

10K

1/20W

201

DRAM_CFG2:H

1

5%
MF

2

R2173

10K

1/20W

201

1

5%
MF

2

DRAM_CFG3:H

R2172

10K

1/20W

201

1

5%
MF

2

MLB_RAM_CFG3
MLB_RAM_CFG2
MLB_RAM_CFG1
MLB_RAM_CFG0

MLB_RAM_CFG3

MLB_RAM_CFG2

MLB_RAM_CFG1

MLB_RAM_CFG0

DRAM_CFG3:L

R2162

8 7 5 4 2 1

GPIO[68:71] have 15K-45K internal PUs

1

R2163

1K

5%
1/20W
MF
201

2

1/20W

1

1K

5%

MF

201

2

SIZE

A

D

SYNC_MASTER=K21_MLB

DRAM_CFG1:LDRAM_CFG2:L

R2164

1/20W

1

1K

5%

MF

201

2

DRAM_CFG0:L

1

R2165

1K

5%
1/20W
MF
201

2

PAGE TITLE

PCH MISC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

21 OF 109

SHEET

19 OF 75

36

www.laptopblue.vn

345678

2 1

D

C

B

PLACE_NEAR=U1800.R15:2.54mm

VCCACLK pin left as NC per DG

=PP3V3_S5_PCH_VCCDSW

7

22

TP_PPVOUT_PCH_DCPSUSBYP

PP3V3_S0_PCH_VCC3_3_CLK_F

22

=PP1V05_S0_PCH_VCCIO_CLK

7

20 22

AL24 left as NC per DG

=PP1V05_S0_PCH_VCCASW

7

20 22

PPVOUT_G3_PCH_DCPRTC

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C2210

0.1UF

10%
16V

2

X5R-CERM
0201

MIN_LINE_WIDTH=0.2 mm

PLACE_NEAR=U1800.U17:2.54mm

1

C2222

0.1UF

10%
16V

2

X5R-CERM
0201

PCH output, for decoupling only

=PP1V8R1V5_S0_PCH_VCCVRM

7

20

PP1V05_S0_PCH_VCCADPLLA

20

PP1V05_S0_PCH_VCCADPLLB

20

=PP1V05_S0_PCH_VCCIO_CLK

7

20 22

=PP1V05_S0_PCH_VCCDIFFCLK

7

16 22

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCSSC

7

22

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

7

22

=PPVRTC_G3_PCH

7

VCCAPLLDMI2 pin left as NC per DG

VOLTAGE=3.3V

=PP1V05_S0_PCH_V_PROC_IO

1

C2231

1UF

10%

6.3V

2

CERM
402

1

C2232

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=U1800.N16:2.54mm
PLACE_NEAR=U1800.N16:2.54mm
PLACE_NEAR=U1800.N16:2.54mm

1

C2233

0.1UF

10%
16V

2

X5R-CERM
0201

AC51

NC

R12

R10

V37
V39

AW31

NC

AP27

V13

NC

AR33

NC

AU33

NC

AB27
AB29
AB31
AC27
AC29
AC31
AE27
AE29
AE31

U21
V21
V23
V25
Y21
Y23
Y25
Y27
Y29
Y31

R15
U15

AC39

BF40
BD40

AJ17

AC37
AE37
AE39

AC35

U17

AM17

N16

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_V37
VCC3_3_V39

VCCAPLLDMI2

VCCIO_AP27

DCPSUS_V13

DCPSUS_AR33
DCPSUS_AU33

VCCASW_AB27
VCCASW_AB29
VCCASW_AB31
VCCASW_AC27
VCCASW_AC29
VCCASW_AC31
VCCASW_AE27
VCCASW_AE29
VCCASW_AE31
VCCASW_U21
VCCASW_V21
VCCASW_V23
VCCASW_V25
VCCASW_Y21
VCCASW_Y23
VCCASW_Y25
VCCASW_Y27
VCCASW_Y29
VCCASW_Y31

DCPRTC_R15
DCPRTC_U15

VCCVRM_AC39

VCCADPLLA
VCCADPLLB

VCCIO_AJ17

VCCDIFFCLKN_AC37
VCCDIFFCLKN_AE37
VCCDIFFCLKN_AE39

VCCSSC
DCPSST

V_PROC_IO

VCCRTC

COUGAR-POINT

U1800

MOBILE-SFF

FCBGA

(8 OF 10)

OMIT_TABLE

CLOCK/MISC

RTC CPU

VCCIO_R23
VCCIO_R25
VCCIO_U23
VCCIO_U25

VCCSUS3_3_R27
VCCSUS3_3_R29
VCCSUS3_3_U27
VCCSUS3_3_U29

USB

VCCSUS3_3_N27

VCCIO_N18

V5REF_SUS

DCPSUS_AU31

VCCSUS3_3_AM27

V5REF

VCCSUS3_3_R33
VCCSUS3_3_R35
VCCSUS3_3_U33
VCCSUS3_3_U35

VCC3_3_AB19
VCC3_3_AC19

PCI/GPIO/LPC

VCC3_3_R40

VCC3_3_AF6

VCCIO_AA13

VCCIO_AG13
VCCIO_AG15

VCCIO_AF15

SATA

VCCAPLLSATA

VCCVRM_AE19
VCCVRM_AF17

VCCIO_AB15
VCCIO_AC13
VCCIO_AC15

VCCASW_U19
VCCASW_R19
VCCASW_V19

FUSE

VCCSUSHDA

HDA

R23
R25
U23
U25

R27
R29
U27
U29
N27

N18

M37

AU31

AM27

N36

R33
R35
U33
U35

AB19
AC19
R40

AF6

AA13

AG13
AG15

AF15

AM2

AE19
AF17

AB15
AC13
AC15

U19
R19
V19

V31

7

=PP1V05_S0_PCH_VCCIO_USB

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP5V_SUS_PCH_V5REFSUS

NC-ed per DG

NC

=PP3V3_SUS_PCH_VCCSUS

=PP5V_S0_PCH_V5REF
=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCC3_3_SATA

=PP1V05_S0_PCH_VCCIO_SATA

VCCAPLLSATA pin left as NC per DG

NC

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCASW

=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

=PP1V05_S0_PCH_VCCADPLL

22

7

R2260

0

1 2

5%
1/16W
MF-LF

402

7

22

7

22

7

7

22

7

22

7

22

7

16 20 22

20

7

16 20 22

7

20 22

7

=PP1V05_S0_PCH_VCC_CORE

7

22

1.44 A Max, 474mA Idle

22

7

=PP1V05_S0_PCH_VCCIO_PLLPCIE

7

TP_1V05_S0_PCH_VCCAPLLEXP
=PP1V05_S0_PCH_VCCIO

7

22

=PP3V3_S0_PCH_VCC3_3_PCI

7

22

=PP1V8R1V5_S0_PCH_VCCVRM

7

20

VCCAFDIPLL pin left as NC per DG

=PP1V05_S0_PCH_VCCIO_PLLFDI

7

=PP1V05_S0_PCH_VCCDMI_FDI

16 22 17 16

PCH VCCADPLLA Filter

(PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2260

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2261

1UF

10%

6.3V

2

CERM
402

PLACE_NEAR=U1800.BF40:2.54MM

7

20

68 mA

AB21
AB23
AC21
AC23
AE21
AE23
AF21
AF23
AG21
AG23
AG25
AG27
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AK29
AK31
AK33
AM33
AM35

AM21

AP19

AR15
AT13

AR23
AR25
AR27
AR29
AU23
AU25
AU27
AU29

AU35
AW34

BK28

AU19
AW18

AP13

NC

AP15

NC

AK21

AU15
AW16

VCCCORE_AB21
VCCCORE_AB23
VCCCORE_AC21
VCCCORE_AC23
VCCCORE_AE21
VCCCORE_AE23
VCCCORE_AF21
VCCCORE_AF23
VCCCORE_AG21
VCCCORE_AG23
VCCCORE_AG25
VCCCORE_AG27
VCCCORE_AJ21
VCCCORE_AJ23
VCCCORE_AJ25
VCCCORE_AJ27
VCCCORE_AJ29
VCCCORE_AJ31
VCCCORE_AK29
VCCCORE_AK31
VCCCORE_AK33
VCCCORE_AM33
VCCCORE_AM35

VCCIO_AM21

VCCAPLLEXP

VCCIO_AR15
VCCIO_AT13

VCCIO_AR23
VCCIO_AR25
VCCIO_AR27
VCCIO_AR29
VCCIO_AU23
VCCIO_AU25
VCCIO_AU27
VCCIO_AU29

VCCIO_AU35
VCCIO_AW34

VCC3_3_BK28

VCCVRM_AU19
VCCVRM_AW18

VCCAFDIPLL_AP13
VCCAFDIPLL_AP15

VCCIO_AK21

VCCDMI_AU15
VCCDMI_AW16

U1800

COUGAR-POINT

MOBILE-SFF

FCBGA

(7 OF 10)

OMIT_TABLE

LVDS

VCCTX_LVDS_AF37
VCCTX_LVDS_AG37
VCCTX_LVDS_AG39

VCC CORE

VCCTX_LVDS_AJ37

HVCMOS

DMI

VCCDFTERM_AJ13
VCCDFTERM_AJ15
VCCDFTERM_AK15
VCCDFTERM_AL13

NAND/SPI

VCCIO

FDI

VCCADAC

CRT

VSSADAC

VCCALVDS_AF33
VCCALVDS_AG33

VSSALVDS_AC33
VSSALVDS_AE33

VCC3_3_T39

VCC3_3_U37

VCCVRM_AU21
VCCVRM_AW21

VCCDMI_AM23

VCCCLKDMI

VCCSPI

U51

V50

AF33
AG33

AC33
AE33

AF37
AG37
AG39
AJ37

T39

U37

AU21
AW21

AM23

AP39

AJ13
AJ15
AK15
AL13

Y19

PP3V3_S0_PCH_VCCA_DAC_F

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCC_DMI

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V8_S0_PCH_VCC_DFTERM

=PP3V3_S5_PCH_VCC_SPI

22

D

7

22

7

20

7

22

22

7

18 22

7

22

C

B

PCH VCCADPLLB Filter

10%
16V
X5R-CERM
0201

(PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2266

1UF

10%

6.3V

2

CERM
402

PLACE_NEAR=U1800.BF40:2.54MM

69 mA

20

SIZE

A

D

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

22 OF 109

SHEET

20 OF 75

36

R2265

0

1 2

5%
1/16W
MF-LF

402

1

C2265

0.1UF

2

A

8 7 5 4 2 1

www.laptopblue.vn

345678

2 1

BB50
BC11

G7

AA7

AA9
AA11
AA39
AA41

D

C

B

A

AA43
AA45

AB2

AB4
AB17
AB25
AB33
AB35
AB37
AB48
AB50

AC7

AC9
AC11
AC17
AC25
AC41
AC43
AC45

AE7

AE9
AE11
AE13
AE15
AE17
AE25
AE35
AE41
AE43
AE45

AF2

AF4

AF8
AF19
AF25
AF27
AF29
AF31
AF35
AF48
AF50

AG7

AG9
AG11
AG17
AG19
AG29
AG31
AG35
AG41
AG43
AG45

AH2

AJ7

AJ9
AJ11
AJ19
AJ33
AJ35
AJ39
AJ41
AJ43
AJ45

AK2

AK4
AK17
AK19
AK23
AK25
AK27
AK35
AK37
AK48
AK50
BA11
BA13
BA16
BA18
BA21
BA23
BA25
BA27
BA29

BA9 BB2

VSS_G7

VSS_AA7
VSS_AA9
VSS_AA11
VSS_AA39
VSS_AA41
VSS_AA43
VSS_AA45
VSS_AB2
VSS_AB4
VSS_AB17
VSS_AB25
VSS_AB33
VSS_AB35
VSS_AB37
VSS_AB48
VSS_AB50
VSS_AC7
VSS_AC9
VSS_AC11
VSS_AC17
VSS_AC25
VSS_AC41
VSS_AC43
VSS_AC45
VSS_AE7
VSS_AE9
VSS_AE11
VSS_AE13
VSS_AE15
VSS_AE17
VSS_AE25
VSS_AE35
VSS_AE41
VSS_AE43
VSS_AE45
VSS_AF2
VSS_AF4
VSS_AF8
VSS_AF19
VSS_AF25
VSS_AF27
VSS_AF29
VSS_AF31
VSS_AF35
VSS_AF48
VSS_AF50
VSS_AG7
VSS_AG9
VSS_AG11
VSS_AG17
VSS_AG19
VSS_AG29
VSS_AG31
VSS_AG35
VSS_AG41
VSS_AG43
VSS_AG45
VSS_AH2
VSS_AJ7
VSS_AJ9
VSS_AJ11
VSS_AJ19
VSS_AJ33
VSS_AJ35
VSS_AJ39
VSS_AJ41
VSS_AJ43
VSS_AJ45
VSS_AK2
VSS_AK4
VSS_AK17
VSS_AK19
VSS_AK23
VSS_AK25
VSS_AK27
VSS_AK35
VSS_AK37
VSS_AK48
VSS_AK50
VSS_BA11
VSS_BA13
VSS_BA16
VSS_BA18
VSS_BA21
VSS_BA23
VSS_BA25
VSS_BA27
VSS_BA29
VSS_BA9

U1800

FCBGA

(9 OF 10)

VSS

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

VSS_AL7

VSS_AL9
VSS_AL11
VSS_AL39
VSS_AL41
VSS_AL43
VSS_AL45
VSS_AM15
VSS_AM19
VSS_AM25
VSS_AM29
VSS_AM31
VSS_AM37

VSS_AP2

VSS_AP4

VSS_AP7

VSS_AP9
VSS_AP11
VSS_AP17
VSS_AP21
VSS_AP23
VSS_AP25
VSS_AP29
VSS_AP31
VSS_AP33
VSS_AP35
VSS_AP37
VSS_AP41
VSS_AP43
VSS_AP45
VSS_AP48
VSS_AP50

VSS_AR6

VSS_AR8
VSS_AR17
VSS_AR19
VSS_AR21
VSS_AR31
VSS_AR35
VSS_AR37

VSS_AT7

VSS_AT9
VSS_AT11
VSS_AT39
VSS_AT41
VSS_AT43
VSS_AT45
VSS_AU17
VSS_AU37

VSS_AV2

VSS_AV4
VSS_AV48
VSS_AV50

VSS_AW7

VSS_AW9
VSS_AW11
VSS_AW13
VSS_AW23
VSS_AW25
VSS_AW27
VSS_AW29
VSS_AW36
VSS_AW39
VSS_AW41
VSS_AW43
VSS_AW45
VSS_AY10

VSS_B6
VSS_B10
VSS_B14
VSS_B18
VSS_B22
VSS_B26
VSS_B30
VSS_B34
VSS_B38
VSS_B42
VSS_B46
VSS_BA7

VSS_BB48
VSS_BA31
VSS_BA34
VSS_BA36
VSS_BA39
VSS_BA41
VSS_BA43
VSS_BA45

VSS_BB4
VSS_BB2

AL7
AL9
AL11
AL39
AL41
AL43
AL45
AM15
AM19
AM25
AM29
AM31
AM37
AP2
AP4
AP7
AP9
AP11
AP17
AP21
AP23
AP25
AP29
AP31
AP33
AP35
AP37
AP41
AP43
AP45
AP48
AP50
AR6
AR8
AR17
AR19
AR21
AR31
AR35
AR37
AT7
AT9
AT11
AT39
AT41
AT43
AT45
AU17
AU37
AV2
AV4
AV48
AV50
AW7
AW9
AW11
AW13
AW23
AW25
AW27
AW29
AW36
AW39
AW41
AW43
AW45
AY10
B6
B10
B14
B18
B22
B26
B30
B34
B38
B42
B46
BA7
BB48
BA31
BA34
BA36
BA39
BA41
BA43
BA45
BB4

BC13
BC16
BC18
BC21
BC23
BC25
BC27
BC29
BC31
BC34
BC36
BC39
BC41
BC43
BC45
BD15
BD24

BE7

BE9
BE11
BE13
BE16
BE18
BE21
BE23
BE25
BE27
BE29
BE31
BE34
BE36
BE39
BE41
BE43
BE45

BF2

BF4
BF15
BF24
BF48
BF50

BH6
BH10
BH14
BH18
BH22
BH26
BH28
BH30
BH32
BH34
BH38
BH42
BH44
BH46
BH48
BK10
BK14
BK18
BK22
BK26
BK30
BK32
BK34
BK38
BK42
BK46

D10

D14

D18

D22

D26

D30

D34

D38

D42

D46

F48

F50

G11

G13

G16

G18

G21

G23

G25

G27

G29

G31

D6

F2
F4

G9

VSS_BB50
VSS_BC11
VSS_BC13
VSS_BC16
VSS_BC18
VSS_BC21
VSS_BC23
VSS_BC25
VSS_BC27
VSS_BC29
VSS_BC31
VSS_BC34
VSS_BC36
VSS_BC39
VSS_BC41
VSS_BC43
VSS_BC45
VSS_BD15
VSS_BD24
VSS_BE7
VSS_BE9
VSS_BE11
VSS_BE13
VSS_BE16
VSS_BE18
VSS_BE21
VSS_BE23
VSS_BE25
VSS_BE27
VSS_BE29
VSS_BE31
VSS_BE34
VSS_BE36
VSS_BE39
VSS_BE41
VSS_BE43
VSS_BE45
VSS_BF2
VSS_BF4
VSS_BF15
VSS_BF24
VSS_BF48
VSS_BF50
VSS_BH6
VSS_BH10
VSS_BH14
VSS_BH18
VSS_BH22
VSS_BH26
VSS_BH28
VSS_BH30
VSS_BH32
VSS_BH34
VSS_BH38
VSS_BH42
VSS_BH44
VSS_BH46
VSS_BH48
VSS_BK10
VSS_BK14
VSS_BK18
VSS_BK22
VSS_BK26
VSS_BK30
VSS_BK32
VSS_BK34
VSS_BK38
VSS_BK42
VSS_BK46
VSS_D6
VSS_D10
VSS_D14
VSS_D18
VSS_D22
VSS_D26
VSS_D30
VSS_D34
VSS_D38
VSS_D42
VSS_D46
VSS_F2
VSS_F4
VSS_F48
VSS_F50
VSS_G9
VSS_G11
VSS_G13
VSS_G16
VSS_G18
VSS_G21
VSS_G23
VSS_G25
VSS_G27
VSS_G29
VSS_G31

U1800

FCBGA

(10 OF 10)

VSS

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

8 7 5 4 2 1

VSS_G34
VSS_G36
VSS_G39
VSS_G41
VSS_G43

VSS_J7

VSS_J9
VSS_J11
VSS_J13
VSS_J16
VSS_J18
VSS_J21
VSS_J23
VSS_J25
VSS_J27
VSS_J29
VSS_J31
VSS_J34
VSS_J36
VSS_J39
VSS_J41
VSS_J45

VSS_K2

VSS_K4
VSS_K48
VSS_K50

VSS_L7

VSS_L9
VSS_L11
VSS_L13
VSS_L16
VSS_L18
VSS_L21
VSS_L23
VSS_L25
VSS_L27
VSS_L29
VSS_L31
VSS_L34
VSS_L36
VSS_L39
VSS_L41
VSS_L43
VSS_L45

VSS_N7

VSS_N9
VSS_N11
VSS_N13
VSS_N21
VSS_N23
VSS_N25
VSS_N29
VSS_N31
VSS_N34
VSS_N39
VSS_N41
VSS_N43
VSS_N45

VSS_P2

VSS_P4
VSS_P48
VSS_P50
VSS_R17
VSS_R21
VSS_R31
VSS_R37

VSS_T7

VSS_T9
VSS_T11
VSS_T13
VSS_T41
VSS_T43
VSS_T45
VSS_U31
VSS_U49

VSS_V2

VSS_V4

VSS_V7

VSS_V9
VSS_V11
VSS_V15
VSS_V17
VSS_V27
VSS_V29
VSS_V33
VSS_V35
VSS_V41
VSS_V43
VSS_V45
VSS_V48
VSS_Y15
VSS_Y17
VSS_Y33
VSS_Y35
VSS_Y37

36

G34
G36
G39
G41
G43
J7
J9
J11
J13
J16
J18
J21
J23
J25
J27
J29
J31
J34
J36
J39
J41
J45
K2
K4
K48
K50
L7
L9
L11
L13
L16
L18
L21
L23
L25
L27
L29
L31
L34
L36
L39
L41
L43
L45
N7
N9
N11
N13
N21
N23
N25
N29
N31
N34
N39
N41
N43
N45
P2
P4
P48
P50
R17
R21
R31
R37
T7
T9
T11
T13
T41
T43
T45
U31
U49
V2
V4
V7
V9
V11
V15
V17
V27
V29
V33
V35
V41
V43
V45
V48
Y15
Y17
Y33
Y35
Y37

SYNC_MASTER=K78_MLB

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/10/2011

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

23 OF 109

SHEET

21 OF 75

SIZE

D

C

B

A

D

www.laptopblue.vn

345678

2 1

16

7

D

=PP3V3_S0_PCH_VCCADAC

7

C

B

=PP1V05_S0_PCH

PLACE_NEAR=U1800.N36:2.54mm

L2406

10UH-0.12A-0.36OHM

1 2

0603

R2450

0

1 2

5%

1/20W

MF

201

C2450

10UF

CERM-X5R

PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm

=PP3V3_S0_PCH

19 16

7

=PP5V_S0_PCH

7

1 mA

=PP3V3_SUS_PCH

7

=PP5V_SUS_PCH

7

1 mA S0-S5

PLACE_NEAR=U1800.M37:2.54mm

R2415

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V

PLACE_NEAR=U1800.AP39:2.54mm

1

C2451

0.1UF

201

20%
10V

402

5%
MF

201

10

5%
MF

X5R-CERM

12

NC

1

2

12

1

2

10%
16V

0201

NC

20%

6.3V

2

0402

R2405

1/20W

C2439

1UF

R2404

C2438

0.1UF

100

10%
10V
X5R
402

1/20W

CERM

1 2

1

C2455

0.01UF

2

X5R-CERM

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

1

5

D2400

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)

4

2

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

1

5%

1/20W

MF

201

PP3V3_S0_PCH_VCCA_DAC_F

1

10%
16V

2

0201

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

1

C2411

10UF

20%

6.3V

2

CERM-X5R
0402-1

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

NEED PWR CONSTRAINT

<1 MA

=PP5V_S0_PCH_V5REF

NEED PWR CONSTRAINT

20

<1 MA S0-S5

PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)

=PP3V3_SUS_PCH_VCCSUS_USB

20

20

20

=PP3V3_S0_PCH_VCC3_3_CLK

7

20

7

1

2

PLACE_NEAR=U1800.R27:2.54mm

=PP1V05_S0_PCH_V_PROC_IO

20

7

PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm

PCH VCCIO BYPASS

=PP1V05_S0_PCH_VCC_DMI

20

7

PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)

PLACE_NEAR=U1800.AM23:2.54mm

R2451

1

1 2

PP3V3_S0_PCH_VCC3_3_CLK_R

5%
1/16W
MF-LF

402

C2484

0.1UF

10%
16V
X5R-CERM
0201

PLACE_NEAR=U1800.U27:2.54mm

C2416

4.7UF

1

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

=PP1V05_S0_PCH_VCCIO

20

7

1

C2413

0.1UF

10%
16V

2

X5R-CERM
0201

20%

6.3V
X5R
402

C2419

1UF

20%

6.3V
X5R
0201

1

C2429

1UF

20%

6.3V

2

X5R
0201

1

1

C2417

0.1UF

10%
16V

2

2

X5R-CERM
0201

10UH-0.12A-0.36OHM

1

C2414

1UF

20%

6.3V

2

X5R
0201

1

C2430

0.1UF

10%
16V

2

X5R-CERM
0201

L2451

1 2

0603

C2453

CERM-X5R

PLACE_NEAR=U1800.V37:2.54mm

1

C2407

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm

20

PLACE_NEAR=U1800.R12:2.54mm

PP3V3_S0_PCH_VCC3_3_CLK_F

20

10UF

20%

6.3V

0402-1

=PP1V8_S0_PCH_VCC_DFTERM

20 18

7

PLACE_NEAR=U1800.AJ15:2.54mm

PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

=PP3V3R1V5_S0_PCH_VCCSUSHDA

20 16

7

PLACE_NEAR=U1800.V31:2.54mm

=PP3V3_S5_PCH_VCC_SPI

20

7

PLACE_NEAR=U1800.Y19:2.54mm

=PP3V3_S5_PCH_VCCDSW

7

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

1

C2463

1UF

20%

6.3V

2

X5R
0201

C2401

10UF

6.3V

CERM-X5R

0402

PLACE_NEAR=U1800.V37:2.54mm

1

20%

2

C2499

0.1UF

X5R-CERM

0201

1

C2454

1UF

20%

6.3V

2

X5R
0201

10%
16V

1

2

1

C2441

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2442

1UF

20%

6.3V

2

X5R
0201

1

2

C2440

0.1UF

10%
16V
X5R-CERM
0201

PLACE_NEAR=U1800.AC35:2.54mm

PLACE_NEAR=U1800.AJ17:2.54mm

=PP1V05_S0_PCH_VCCIO_SATA

20 16

7

PLACE_NEAR=U1800.AG13:2.54mm

=PP1V05_S0_PCH_VCCSSC

20

7

=PP1V05_S0_PCH_VCCDIFFCLK

20 16

7

PLACE_NEAR=U1800.AE37:2.54mm

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

=PP1V05_S0_PCH_VCCIO_USB

20

7

PLACE_NEAR=U1800.U23:2.54mm

=PP1V05_S0_PCH_VCC_CORE

20

7

1

C2481

1UF

20%

6.3V

2

X5R
0201

=PP1V05_S0_PCH_VCCIO_CLK

20

7

1

C2444

1UF

20%

6.3V

2

X5R
0201

1

2

1

C2482

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AC21:2.54mm
PLACE_NEAR=U1800.AF23:2.54mm
PLACE_NEAR=U1800.AJ25:2.54mm
PLACE_NEAR=U1800.AK33:2.54mm

1

C2452

1UF

20%

6.3V

2

X5R
0201

C2475

1UF

20%

6.3V
X5R
0201

1

C2434

1UF

20%

6.3V

2

X5R
0201

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)

1

C2483

1UF

20%

6.3V

2

X5R
0201

1

C2469

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AC13:2.54mm

=PP3V3_SUS_PCH_VCCSUS_GPIO

20

7

PLACE_NEAR=U1800.U33:2.54mm

1

C2446

1UF

20%

6.3V

2

X5R
0201

1

C2460

10UF

20%

6.3V
2

CERM-X5R

0402

1

C2476

1UF

20%

6.3V

2

X5R
0201

D

C

B

=PP3V3_S0_PCH_VCC3_3_PCI

20

7

1

C2421

0.1UF

10%
16V

2

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

0201

A

=PP3V3_S0_PCH_VCC3_3_HVCMOS

20

7

1

C2424

0.1UF

10%
16V

2

X5R-CERM

PLACE_NEAR=U1800.T39:2.54mm

0201

8 7 5 4 2 1

=PP3V3_S0_PCH_VCC3_3_SATA

20

7

PLACE_NEAR=U1800.AF6:2.54mm

=PP3V3_S0_PCH_VCC3_3_GPIO

20

7

PLACE_NEAR=U1800.AC19:2.54mm

1

C2486

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2423

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

C2485

0.1UF

10%
16V
X5R-CERM
0201

PLACE_NEAR=U1800.R40:2.54mm

=PP1V05_S0_PCH_VCCASW

20

7

1

C2426

1UF

20%

6.3V

2

X5R
0201

1

C2456

1UF

20%

6.3V

2

X5R
0201

1

C2496

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm

C2428

22UF

6.3V

X5R-CERM1

0603

SIZE

A

D

C2420

22UF

6.3V

X5R-CERM1

0603

1

20%

2

1

20%

2

SYNC_MASTER=K78_MLB

PAGE TITLE

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/10/2011

DRAWING NUMBER

051-8870

REVISION

3.13.0

BRANCH

PAGE

24 OF 109

SHEET

22 OF 75

36

www.laptopblue.vn

PROCESSOR MICRO2-XDP CONNECTOR

NOTE: This is not the standard XDP pinout

Use with 920-0782 Adapter Flex to support chipset debug

=PP3V3_S0_XDP

D

1K

201

1K

201

MF

MF

5%
MF-LF
5%
MF-LF
5%
MF-LF
5%
MF-LF

1 2

5%

MF-LF

1 2

5%

MF-LF

5%
MF-LF
5%
MF-LF

0

1 2

0

1 2

0

1 2

0

1 2

0

0

0

1 2

0

1 2

1/20W

R2502

1 2

5%

1/20W

1 2

5%

5%

5%

R2564
R2565
R2566
R2567

R2560
R2561
R2562
R2563

XDP

R2500

1 2

XDP

R2501

1 2

XDP_BPM_L<4>

IN

XDP_BPM_L<5>

IN

XDP_BPM_L<6>

IN

XDP_BPM_L<7>

IN

CPU_CFG<12>

IN

CPU_CFG<13>

IN

CPU_CFG<14>

IN

CPU_CFG<15>

IN

PLACE_NEAR=U1000.B46:1MM

C

PLACE_NEAR=U1000.B50:2.54MM

CPU_PWRGD

IN

PLACE_NEAR=U4900.D10:2.54MM

OUT

CPU_CFG<0>

OUT

PM_PCH_SYS_PWROK

OUT

PM_PWRBTN_L

XDP

0

MF

201

XDP

R2504

MF-LF

XDP_CPU:BPM

1/16W

402

XDP_CPU:BPM

1/16W

402

XDP_CPU:BPM

1/16W

402

XDP_CPU:BPM

1/16W

402

XDP_CPU:CFG

1/16W

402

XDP_CPU:CFG

1/16W

402

XDP_CPU:CFG

1/16W

402

XDP_CPU:CFG

1/16W

402

1/20W

910

1/16W

402

XDP_CPU_PREQ_L

BI

XDP_CPU_PRDY_L

IN

XDP_BPM_L<0>

IN

XDP_BPM_L<1>

IN

XDP_BPM_L<2>

IN

XDP_BPM_L<3>

IN

CPU_CFG<10>

IN

CPU_CFG<11>

IN

XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>

XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>

XDP_CPU_PWRGD

XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0>

XDP_VR_READY

=SMBUS_XDP_SDA

BI

=SMBUS_XDP_SCL

IN

XDP_CPU_TCK

OUT

=PPVCCIO_S0_XDP

NOSTUFF

1

R2540

1K

5%
1/16W
MF-LF

402

2

OBSFN_A0

OBSFN_A1 OBSFN_C1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

SDA
SCL

TCK1
TCK0

XDP

1

C2500

0.1UF

10%
16V

2

X5R
402

Even pins should be facing edge of the board

PCH MICRO2-XDP CONNECTOR

NOTE: This is not the standard XDP pinout

Use with 920-0782 Adapter Flex to support chipset debug

=PP3V3_S5_XDP

B

PLACE_NEAR=U1800.H4:2.54MM

PCH_GPIO59_OC0_L

IN

PLACE_NEAR=U1800.A17:2.54MM

USB_HUB_SOFT_RESET_L

IN

PLACE_NEAR=U1800.A13:2.54MM

SDCONN_STATE_RST_L

IN

PLACE_NEAR=U1800.D16:2.54MM

ENET_PWR_EN

IN

PLACE_NEAR=U1800.B16:2.54MM

SDCONN_STATE_CHANGE

IN

PLACE_NEAR=J2550.39:2.54MM

ALL_SYS_PWRGD

IN

PLACE_NEAR=U4900.D10:2.54MM

PM_PWRBTN_L

OUT

A

XDP

5%

5%

5%

5%

5%

5%
MF-LF

5%

MF

MF

MF

MF

MF

MF

R2582

0

1 2

XDP

R2580

0

1 2

XDP

R2586

0

1 2

XDP

R2587

0

1 2

XDP

R2581

0

1 2

XDP

R2584

1K

1 2

XDP

R2585

0

1 2

201

201

201

201

201

402

201

1/20W

1/20W

1/20W

1/20W

1/20W

1/16W

1/20W

TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>

XDP_PCH_GPIO59_OC0_L
XDP_PCH_USB_HUB_SOFT_RST_L

XDP_PCH_SDCONN_STATE_RST_L
XDP_PCH_ENET_PWR_EN

TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>

PCH_GPIO43_OC4_L

IN

XDP_PCH_SDCONN_DET_L

PCH_GPIO10_OC6_L

IN

PCH_GPIO14_OC7_L

IN

XDP_PCH_S5_PWRGD

XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3

=SMBUS_XDP_SDA

BI

=SMBUS_XDP_SCL

IN

XDP_PCH_TCK

OUT

Even pins should be facing edge of the board

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

C2580

TCK1
TCK0

0.1UF

SDA
SCL

XDP

1

10%
16V

2

X5R
402

8 7 5 4 2 1

XDP_CONN
CRITICAL

J2500

DF40RC-60DP-0.4V

M-ST-SM

62

61

1

2

3

4

5

6

78

10

9
1112
1314
1516
1718
19

20

2122
2324
2526
2728
29

30

3132
3334
3536
3738
39

40

4142
4344
4546
4748
49

50

5152
5354

NC

5556
5758
59

60

6364

998-2516

XDP_CONN
CRITICAL

J2550

DF40RC-60DP-0.4V

M-ST-SM

62

61

1

2

3

4

5

6

78

10

9
1112
1314
1516
1718
19

20

2122
2324
2526
2728
29

30

3132
3334
3536
3738
39

40

4142
4344
4546
4748
49

50

5152
5354

NC

5556
5758
59

60

6364

998-2516

OBSFN_C0

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0

OBSFN_D1

OBSDATA_D0

OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6
DBR#/HOOK7

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

TDO
TRSTn

TDI
TMS

XDP_PRESENT#

XDP

1

C2501

0.1UF

10%
16V

2

X5R
402

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

TDO
TRSTn
TDI
TMS
XDP_PRESENT#

XDP

1

C2581

0.1UF

10%
16V

2

X5R
402

PCH_GPIO15
SMC_IG_THROTTLE_L

XDP_PCH_ISOLATE_CPU_MEM_L

PCH_GPIO35

DP_AUXCH_ISOL
SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>

PCH_GPIO36_SATA2GP
JTAG_ISP_TCK

XDP_PCH_AUD_IPHS_SWITCH_EN
ENET_LOW_PWR

TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5

XDPPCH_PLTRST_L
XDP_DBRESET_L

XDP_PCH_TDO
TP_XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

CPU_CFG<16>
CPU_CFG<17>

CPU_CFG<0>
CPU_CFG<1>

CPU_CFG<2>
CPU_CFG<3>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<4>
CPU_CFG<5>

CPU_CFG<6>
CPU_CFG<7>

XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N

XDP_CPURST_L
XDP_DBRESET_L

XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

OUT

IN
OUT
OUT
OUT

IN

IN

5%

MF

IN

IN

IN

IN

IN

IN

IN
OUT

IN

OUT
OUT

XDP

R2515

0

1 2

5%

MF
201

XDP

R2516

0

1 2

5%

MF
201

XDP

R2505

1K

1 2

5%

MF
201

XDP

R2578

0

1 2

1/20W

201

XDP

R2579

0

1 2

5%

MF

1K series R on PCH Support P. 28

345678

PLACE_NEAR=R1841.1:2.54MM

1/20W

ITPXDP_CLK100M_P

PLACE_NEAR=R1840.1:2.54MM

1/20W

ITPXDP_CLK100M_N

PLACE_NEAR=R1125.1:2.54MM

1/20W

CPU_RESET_L

PLACE_NEAR=U1800.G1:2.54MM

ISOLATE_CPU_MEM_L

PLACE_NEAR=U1800.AA3:2.54MM

1/20W

AUD_IPHS_SWITCH_EN_PCH

201

36

PLACE_NEAR=J2500.52:2.54MM

XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L

PLACE_NEAR=U1000.J58:2.54MM

IN

IN

IN

PLACE_NEAR=J2550.52:2.54MM.

XDP_PCH_TDO
XDP_PCH_TDI
XDP_PCH_TMS
XDP_PCH_TCK

IN

IN

2 1

DESIGN NOTE:

ODT AVAILABLE ON JTAG

PLACEMENT NOTE:

PLACE TDO TERM NEAR
SNB XDP CONN

PLACEMENT NOTE:

PLACE TDO TERM NEAR
PCH XDP CONN

SYNC_MASTER=K21_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R2510

R2513

R2550

XDP

1/16W
MF-LF

XDP

1/20W

1

51

5%

402

2

1

51

5%

MF

201

2

XDP

1

51

5%
1/16W
MF-LF

402

2

PLACE_NEAR=U1000.M60

PLACE_NEAR=U1000.L56:2.54MM

R

PLACE_NEAR=U1000.L55:2.54MM

XDP

1

R2511

R2514

R2551

PLACE_NEAR=U1800.U12:2.54MM

PLACE_NEAR=U1800.M17:2.54MM

51

5%
1/16W
MF-LF

402

2

XDP

1

51

5%
1/20W

MF

201

2

XDP

1

51

5%

1/20W

MF

201

2

R2512

PLACEMENT NOTE:
PLACE TCK/TDI/TMS/TRST*

TERM NEAR CPU

R2552

R2556

PLACEMENT NOTE:

PLACE TCK/TDI/TMS/TRST*
TERM NEAR PCH

CPU & PCH XDP

Apple Inc.

=PPVCCIO_S0_XDP

XDP

1

51

5%
1/16W
MF-LF

402

2

=PP1V05_SUS_PCH_JTAG

XDP

1

51

5%

1/20W

PLACE_NEAR=U1800.M15:2.54MM

MF

201

2

XDP

1

51

5%

1/20W

MF

201

2

SYNC_DATE=12/13/2010

DRAWING NUMBER

051-8870

REVISION

BRANCH

PAGE

25 OF 109

SHEET

23 OF 75

3.13.0

SIZE

D

C

B

A

D