Apple M51 Schematic Rev 21

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_TABLEOFCONTENTS_ITEM

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

DVT -- 06/29/06

SANTANA - M51 MLB

Schematic / PCB #’s

80

06/29/2006

1.5V_S0 & 1.05V_S0 VREG

63

M51_PAUL

ETHERNET CONTROLLER

4135

M50_DOUG

06/29/2006

94

(MASTER)

Internal Display Conns

68

M51_DAVE

76

(MASTER)

CPU & SYSTEM SENSE

59

M51_DAVE

54

06/29/2006

43

M51_DOUG

PCI-E CONNECTIONS

58

06/29/2006

SMC44

M51_HENRY

11

06/29/2006

11

M50_HENRY

CPU ITP700FLEX DEBUG

ASIC TEMP SENSORS

10

(MASTER)

10

M51_DAVE

CPU 2 OF 2-PWR/GND

8

06/29/2006

8

M50_HENRY

25

06/29/2006

25

M51_DOUG

SB:DECOUPLING

78

06/29/2006

3V DC/DC 2.5V

61

M51_PAUL

POWER CONN / MISC

6

06/29/2006

6

M51_PAUL

SB: 4 OF 4

24

06/29/2006

24

M50_DOUG

ETHERNET CONNECTOR

43

06/29/2006

37

M51_DOUG

42

06/29/2006

36

M51_DOUG

ETHERNET MISC

Disk Connectors

38

06/29/2006

34

M51_DOUG

CLOCKS: TERMINATIONS

34

06/29/2006

33

M51_HENRY

CLOCKS33

06/29/2006

32

M50_HENRY

Memory Vtt Supply

31

06/29/2006

31

M50_HENRY

Memory Active Termination

30

06/29/2006

30

M50_HENRY

DDR2 SO-DIMM Connector B

29

06/29/2006

29

M51_HENRY

28

06/29/2006

28

M51_HENRY

DDR2 SO-DIMM Connector A

27

(MASTER)

27

M51_DAVE

M51 SMBus Connections

26

06/29/2006

26

SB: MISC

M50_DOUG

SB: 3 OF 4

2323

M51_DOUG

06/29/2006

SB: 2 OF 4

22

06/29/2006

22

M50_DOUG

SB: 1 OF 4

21

06/29/2006

21

M50_DOUG

NB Config Straps

20

06/29/2006

20

M50_HENRY

NB (GM) Decoupling

19

(MASTER)

19

M51_DAVE

1818

M50_HENRY

NB Grounds

06/29/2006

NB Power 2

17

06/29/2006

17

M51_HENRY

NB Power 1

16

06/29/2006

16

M51_HENRY

NB DDR2 Interfaces

1515

M50_HENRY

06/29/2006

NB Misc Interfaces

06/29/2006

14

M50_HENRY

14

NB PEG / Video Interfaces

13

06/29/2006

13

M50_HENRY

NB CPU Interface

12

06/29/2006

12

M50_HENRY

9

06/29/2006

9

M51_HENRY

CPU DECAPS & VID<>

7

06/29/2006

7

M50_HENRY

CPU 1 OF 2-FSB

FUNC TEST 1 OF 2

5

06/29/2006

5

M51_HENRY

BOM Config

4

(MASTER)

4

M51_DAVE

Power Block Diagram

3

06/29/2006

3

M51_PAUL

97

(MASTER)

External Display Conns

69

M51_DAVE

85

(MASTER)

MXM I/O

67

M51_DAVE

84

(MASTER)

MXM PCI-E & PWR

66

M51_DAVE

83

06/29/2006

S0 AND S3 FETS

65

M51_PAUL

82

06/29/2006

5V DC/DC

64

M50_PAUL

79

06/29/2006

1.8V & 1.2V VREG

62

M51_PAUL

77

06/29/2006

PWR GOOD

60

M51_PAUL

75

06/29/2006

IMVP6 CPU VCore Regulator

58

M51_PAUL

74

06/29/2006

AUDIO: POWER SUPPLIES

57

AUDIO

73

06/29/2006

AUDIO: CONNECTORS

56

AUDIO

72

06/29/2006

AUDIO: SPEAKER AMP

55

AUDIO

71

06/29/2006

AUDIO: SPEAKER AMP_1

54

AUDIO

70

06/29/2006

AUDIO: COMBO OUT AMP

53

AUDIO

69

06/29/2006

AUDIO: LINE INPUT AMP

52

AUDIO

68

06/29/2006

AUDIO: CODEC

51

AUDIO

67

06/29/2006

TPM50

M51_HENRY

66

06/29/2006

CPU FAN, HD & OD TEMP

49

M51_HENRY

65

HD AND OD FAN

48

M51_HENRY

06/29/2006

63

06/29/2006

SPI BOOTROM

47

M50_DOUG

60

06/29/2006

LPC+ CONN

46

M51_HENRY

53

06/29/2006

AIRPORT CONN

42

M51_DOUG

06/29/2006

USB Device Interfaces

41

M51_DOUG

47

46

FIREWIRE CONNECTORS

40

M51_DOUG

06/29/2006

45

06/29/2006

FW: 1394B MISC

39

M51_DOUG

1

PCB,FAB,MLB,M51

820-1984 MLB1

CSAPDF MASTER

CONTENTS

DATE

06/29/2006

2

M51_PAUL

2

System Block Diagram

MASTER DATE

CONTENTS

CSAPDF

1

PCB,SCHEM,MLB,M51

051-7039 SCH1

44

06/29/2006

FW: 1394B-LINK/PHY

38

M51_DOUG

051-7039

SCHEM SANTANA

21

1

97

06/29/06 06/22/04

21

446951 ENGINEERING RELEASED

59

06/29/2006

SMC & TPM SUPPORT

M51_HENRY

45

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SEE I2C PG 27

TEMP SENSE

PG 3

POWER SENSE

SEE POWER BLOCK DIAGRAM

ADC

PAGE 28-29

B,0

A

SMB

U5800

FAN

PAGE 27

CORE (1.05V)

CK410M

PAGE 22

PAGE 63

CONTROL = 2.5V

64-BIT

1.8V/667MHZ

DDR2 - DUAL CHAN

J2800

AZALIA

U6800

STA9221

PAGE 68

PORT A

J2901 ALS+AMBIENT TSENS P. 59

U6300/01

FSB

USB

CONNECTORS

CAMERA

JE310/JE320/JE330

PAGE 47

4-BIT (3.3V/33MHZ)

PAGE 67

CAMERA

PAGE 47

JE351

IR RCV

PAGE 58

IR

7

PAGE 47

J5300 (AIRPORT CONN)

TPM

LPC+

JE350

NB- GM

(TMDS - VGA)

2 Diff pairs

JE000, JE001

FIREWIRE B CONNECTORS

PAGE 21

PAGE 14

DMI

PAGE 16-17

CORE (1.05V)

J5300

0

1.2V/1.5GHZ

PAGE 15

PCI-E

PAGE 12

U1200

MAIN MEMORY

PAGE

6DUAL CHANNEL LVDS - 6BIT

MXM CONNECTOR

LVDS

PAGE 97 PAGE 94

8-BIT

TSB82AA2

33MHZ

PAGE 46

3.3V/133MHZ

PAGE 38

OPTICAL

CONNECTOR

PCI-E

UATA

PAGES 84-85

J8400

U2100

667MHZ

J0700

CORE

CONNECTOR

SATA

JC900

(1.83/2.17GHZ)

PAGE 7

PAGE 8

CORE (~1.2V)

CPU

MINI-DVI

(INTERNAL)

J9402J9700

SB

SATA2

PAGE 38

HARD DRIVE

SATA0

PAGE 21

SATA

UATA/133

UATA

JC901

PORT

#0

#2-5

PAGE 22

#1

MINI-PCIE

PAGE 53

AIRPORT

X1 - 1.5GHZ

YUKON

GIG ETHERNET

ETHERNET CONNECTOR

JD600

PAGE 43

U4101

PAGE 41

PAGES 30

PARALLEL

TERM

J2900

DIMM

PAGE 21

PORT PORT

PAGE 22

PCI

DMI

PAGE 22 PAGE 22

SPI

PAGE 21

0 4

J5300

3,7

2 3

156

PAGE 48

J4700

CONN

BT

USB

AIRPORT

U3301

DIMM’S

J2900

J2800

PAGE 24

GPIOS

PAGE 23

ITP CONN

J1101

PAGE 11

PAGE 60

J6000

PAGE 34

TERMS

CLOCKS

PAGE 33

CK410

U3301

64-BIT

4 Diff pairs

MISC

SPI

CONN

DMI

SMC

U6700

4-BIT

LPC

0,2,4

BOOTROM

SMB

100MHZ

FIREWIRE B

2

PAGE 45

1

TSB81BA3

32-BIT

PAGE 73

COMBO OUT CONNECTOR

J7303

OPTICAL OUT

S/PDIF

R/L SPEAKER

CONNECTORS

PAGE 73

J7301,J7302

LINE OUT

PAGE 72

SPEAKER

AMP

AUDIO CODEC

PORT B

PORT C

MIC IN

JE350

BNDI

INTERFACE

PORT F

CONNECTOR

J7303

OPTICAL IN

COMBO IN

LINE IN

PAGE 73

PAGE 44

FIREWIRE B

13

PAGE 14

1.2V/800MHZ

J6500,J6501,J6600 FAN CONNS

System Block Diagram

97

051-7039

21

2

SYNC_MASTER=M51_PAUL SYNC_DATE=06/29/2006

Preliminary

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PAGE 78

5.8A PEAK

0.2A PEAK

3.3V, 7.1A PK [4.1A AVG]

LINEAR PG 82

1.5A PEAK

FET PG 83

1.1A PEAK

0.9A AVG

24V, 3.7A PK [3.3A AVG]

FET PG 83

2.2A AVG

3.4A PEAK FET PG 83

24V, ?A

PAGE 45

LINEAR PAGE 83

0.2A AVG

0.6A PEAK

GRAPHICS

LINEAR

0.2A AVG

0.6A PEAK

ON IN RUN AND SLEEP

"S3" RAILS

"S5" RAILS

"S0" RAILS

ONLY ON IN RUN

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

U7650

ISENSE AND VSENSE

SYSTEM (12V)

S5S5

3.3A PEAK

3.0A AVG FET PG ?

0.4A PEAK

0.3A AVG AC/DC

FET PG 83

6.0A PEAK

3.4A AVG

PAGE 78

SWITCHER

ODD

HDD

0.2A AVG

LINEAR

0.1A AVG

0.1A PEAK LINEAR

12V, ?A

1.5A AVG

?A AVG

?A PEAK

PAGE 82

SWITCHER

1.7A PEAK

AC/DC BOARD

?A PEAK ?A AVG

FET PG 83

?A AVG

FET PG 83

ISENSE + VSENSE U8450

MXM_PWRSRC (12V)

12V, 14.5A PK [9.4A AVG]

PAGE 81

8.4A PEAK SWITCHER

4.5A AVG

PAGE 79

0.3A AVG

0.4A PEAK

5.5A AVG

7.4A PEAK

14.5A PEAK

6.3A AVG SWITCHER PAGE 79

LINEAR

0.4A AVG

1.0A PEAK

PAGE 31

FET PG 83

1.2A AVG

2.4A AVG SWITCHER PAGE 80

ISENSE AND VSENSE U7600

5V, 3.4A PK [2.2A AVG]

230W AC/DC POWER SUPPLY

3.5A PEAK

CPU VCORE (1.25V)

36A PEAK 34A AVG SWITCHER PAGE 75

1.7A AVG

?A PEAK

83 78

5

OMIT

SM

XW302

1 2

1UH-20A-4.5MOHM

TH-VERT-LF

L300

1 2

SM

OMIT

XW301

1 2

SYNC_DATE=06/29/2006

Power Block Diagram

051-7039

21

973

SYNC_MASTER=M51_PAUL

=PP1V5_S0_AIRPORT

=PP1V5_S0_NB

=PP1V5_S0_NB_PCIE

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_VCCD_HMPLL

=PP1V5_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCCUSBPLL

=PP2V5_S0_MXM

=PP2V5_S0_NB_VCCA_3GBG

=PP1V05_S0_CPU =PP1V05_S0_FSB_NB =PP1V05_S0_NB_VTT

=PP1V05_S0_SB_CPU_IO

=PPVCORE_S0_NB

=PPVCORE_S0_SB

PP1V05_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.15MM

VOLTAGE=1.05V

VOLTAGE=12V

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15MM

PP12V_S0_B

VOLTAGE=12V

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.3MM

PP12V_S5_CPU_REG

=PPVCORE_S0_CPU

PPVCORE_CPU

VOLTAGE=1.25V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.15MM

=PP0V9_S0_MEMVTT_LDO

=PP0V9_S0_MEM_TERM

=PP1V8_S3_MEM

=PP1V8_S0_MEMVTT

=PP1V8_S3_MEM_NB

=PP1V8_S0_MXM

MIN_LINE_WIDTH=0.3MM

PP0V9_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15MM

VOLTAGE=0.9V

=PP12V_S0_SATA

PP12V_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=12V

MIN_NECK_WIDTH=0.15MM

MAKE_BASE=TRUE

PP12V_S5_AUDIO_SPKRAMP

=PP12V_S5_AUDIO_SPKRAMP

PP1V2_S3

VOLTAGE=1.8V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

PP3V3_S0

MAKE_BASE=TRUE

=PP3V3_S0_SB_PM

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S0_SB_GPIO

=PP3V3_S0_MXM

=PP12V_S0_FAN

=PPV_S0_LCD

=PP5V_S5_AUDIO_LDO

=PP5V_S0_SATA

=PP5V_S0_SB

=PP5V_S3_USB

=PP5V_S5_SB

=PP3V3_S3_ENET

=PP3V3_S0_AUDIO

=PP3V3_S0_IMVP

MIN_NECK_WIDTH=0.25MM

PP5V_S0

VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

=PP3V3_S0_AIRPORT

=PP3V3_S0_CK410

=PP3V3_S0_FAN

=PP3V3_S0_HD_TSENS

=PP3V3_S0_NB

=PP3V3_S0_NB_VCC_HV

=PP3V3_S0_ODD_TSENS

=PP3V3_S0_PATA

=PP3V3_S0_SATA

=PP3V3_S0_SB

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_PCI

=PP3V3_S0_SB_VCC3_3

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCCLAN3_3

=PP3V3_S0_TPM

=PP3V3_S0_VIDEO

=PPSPD_S0_MEM

VOLTAGE=4.5V

MIN_NECK_WIDTH=0.25MM

PP4V5_S5_AUDIO_ANALOG

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

=PP4V5_S5_AUDIO_ANALOG

=PP5V_S3_BNDI

=PP1V2_S3_LAN

=PP5V_S0_MXM

=PP3V3_S5_ROM

=PP3V3_S5_2V5_LDO

=PP3V3_S5_SMC

=PP3V3_S5_FW

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S5_SB_PM

=PPV_S5_FW

=PPV_S0_INVERTER

PP24V_S5

VOLTAGE=24V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

PP24V_S0

MIN_NECK_WIDTH=0.25MM

VOLTAGE=24V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

=PP5V_S0_DEBUG

=PP3V3_S3_TPM

=PP1V95_S5_FWPHY

=PP3V3_S5_DEBUG

=PP5V_S0_PATA

=PP3V3_S5_SB_IO

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S5_SB_USB

=PP3V3_S5_SB

PP5V_S3

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

=PP5V_S0_AUDIO

=PP5V_S0_MEMVTT

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.15MM

MIN_NECK_WIDTH=0.2MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MM

PP1V8_S3

=PP1V8_S3_1V2_LDO

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

PP5V_S5

MIN_NECK_WIDTH=0.2MM

=PP3V3_S3_FW

=PP3V3_S3_I2C

=PP3V3_S3_BT

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

PP3V3_S3

VOLTAGE=3.3V

=PPV_S0_MXM_PWRSRC

=PP1V5_S0_CPU

VOLTAGE=12V

MIN_LINE_WIDTH=0.60MM

PP12V_S5

MIN_NECK_WIDTH=0.25MM

MAKE_BASE=TRUE

=PP1V5_S0_NB_PLL

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_SB_VCCSATAPLL

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.15MM

MAKE_BASE=TRUE

PP2V5_S5

VOLTAGE=2.5V

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PP3V3_S5

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

VOLTAGE=1.95V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V95_S5

MAKE_BASE=TRUE

PP2V5_S0

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.3MM

VOLTAGE=2.5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.3MM

PP1V5_S0

VOLTAGE=1.5V

83 80

84

83

79

83

82

78 76

80 83

77 41

79 82

76 27

74

97 78 80

66

11

26

73

83 77

83

79

65

19

9

25

80

76

19

10

27

43

72

75

66

59

46

26

83

75

53

78

26

17

25

19

8

19

24

19

25

34

83

9

75

30

29

16

72

79

6

25

23

66

42

71

59

34

65

20

19

25

97

29

58

45

23

83 83

45

25

83

79

59

45

27

77

25

6

83

80

53

19

13

19

16

17

25

24

85

17

7

12

17

21

16

24

5

76

75

8

5

31

29

28

31

14

84

79

6

83

71

5

26

24

21

85

65

94

82

6

25

47

25

41

68

75

5

53

33

59

66

14

17

66

38

6

22

24

26

24

67

94

28

82

68

47

42

84

63

78

27

44

24

11

46

94

6 5

60

67

44

60

38

22

24

22

23

59

70

31

83

5

79

5

44

47

6

84

8

76

19

24

19

24

5

45

78

5

Preliminary

TABLE_5_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

WHEN DEVELOPMENT SENSORS ARE GONE

FOR DVT, TRYING AN EVEN BRIGHTER LED ON 2.16GHZ CONFIG

MUST STUFF WHEN SYS_PWR_SENSE IS NOT STUFFED (I.E. WHEN DEVELOPMENT BOM IS NOT STUFFED)

SENSOR STUFFING OPTIONS

MUST STUFF WHEN CPU_PWR_SENSE IS NOT STUFFED (IF THIS MOVES TO DEV BOM)

WHEN DEVELOPMENT SENSORS ARE GONE

MUST STUFF WHEN MXM_PWR_SENSE IS NOT STUFFED (IF THIS MOVES TO DEV BOM)

MEROM BOM OPTION DUE TO PAGE 76 SHARING W/ M50

PULL-DOWNS FOR UNUSED PINS

BOMOPTION Groups

(335S0384)

(338S0274)

Misc. Parts

BATTERY IS INSTALLED AT FATP

(335S0382)

Alternate Parts

BarCode Label / EEE #’s

Module Parts

PULL-DOWNS FOR UNUSED PINS

Development BOM

Production BOM

1946-0743 ADH1 CRITICAL

IO ALIGNMENT BOARD ADHESIVE

MEROM 2.3GHZ, M51

CPU M51_BEST1 CRITICAL337S3292

[EEE:VMD]

1 CRITICAL

BAR CODE LABLE, MLB, M51

825-6447 EEE_VMD

1 U3301359S0101

IC,CY28445-5,CLK GEN,68PIN QFN

CRITICAL

F9710

DVI DDC (LITTLEFUSE)

740S0028740S0044

U3301

SILEGO CK410 CLOCK

359S0101359S0117

Sanyo alt for Nich.

126S0099 126S0073

ALL

Sanyo alt for Nich.

ALL

126S0078126S0086

Sanyo alt for Nich.

126S0068

ALL

126S0088

SANYO ALT

ALL

124-0361 124-0339

378S0141

GREEN LED ALT.

ALL

378S0140

IC,945PM,NORTHBRIDGE

U1200338S0328 1 CRITICAL

341T0019 U63011

IC,EFI BOOT ROM,M51

CRITICAL

630-7512

PCBA,MLB,2.33GHz,M51

M51_COMMON,M51_BEST,EEE_V4K

630-7595

PCBA,MLB,2.16GHz,M51 M51_COMMON,M51_BETTER,EEE_VMD,PRODUCTION

353S1465

U7500

CPU VREG NEW REV

353S1461

J8400

516S0460516S0511

MXM CONN SPEEDTECH

M51_COMMON

COMMON,M51_COMMON1,M51_COMMON2,ALTERNATE

M51_COMMON1

CPU_TSENS_EXT,GPU_TSENS_INT,GPU_TSENS_EXT,MXM_ROM,NBCFG_PEG_REVERSE

M51_COMMON2

SB_SYSRST_4_PVT,ITP,MEROM,AMB_TSENS,CPU_PWR_SENSE,MXM_PWR_SENSE

M51_DEV1

CPU_TSENS_INT,SYS_PWR_SENSE

[EEE:V4K]

CRITICAL

BAR CODE LABLE, MLB, M51

1825-6447 EEE_V4K

102S0699

1

R7650

PRODUCTION

RES,0-OHM,2010

1

116S0090

RES,10K-OHM,5%,0402

C7650

PRODUCTION

1

116S0090

C7650

PRODUCTION

RES,10K-OHM,5%,0402

1

116S0090

RES,10K-OHM,5%,0402

NOSTUFF

C7612

116S0090

C7602

1

NOSTUFF

RES,10K-OHM,5%,0402

1

C8459

116S0090

NOSTUFF

RES,10K-OHM,5%,0402

C8458

1

116S0090

NOSTUFF

RES,10K-OHM,5%,0402

1

R8450

107S0070

NOSTUFFRES,0-OHM,2512

U21001343S0385

IC,SB,652BGA

CRITICAL

IC,CPU-SKT,479BGA

511S0025 1 J0700 CRITICAL

IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO

1338S0270 CRITICALU4101

IC,ENET LAN ROM

341S1797 U41021 CRITICAL

CRITICAL341S1789 1

IC,TPM,TSSOP,28P

U6700 TPM

1353S1465

IC,CPU VREG,IMVP,TWO PHASE,SCREENED

U7500 CRITICAL

MXM_ROM341S1892 1

IC,2K I2C EEPROM,MXM,M51

U8570 CRITICAL

341T0020 U58001

IC,SMC,M51

CRITICAL

MEROM 2.16GHZ, M51

CPU1 CRITICAL337S3293

M51_BETTER

BAT,COIN,3V,220MAH,CR2032

1 BT2600742-0048 CRITICAL NOSTUFF

IO ALIGNMENT BOARD, M51

PCB21820-2038 CRITICAL

1378S0193 CRITICAL M51_BESTLED5950

LED,WHITE,740MCD,LF,3X2MM

1378S0199 LED5950 CRITICAL

M51_BETTER

LED,WHITE,DUAL,2500MCD,SMD

603-8960

PCBA,DEVBOM,M51 M51_DEVELOPMENT

M51_DEVELOPMENT

DEVELOPMENT,M51_DEV1

SYNC_MASTER=M51_DAVE

051-7039

21

4 97

SYNC_DATE=(MASTER)

BOM Config

Preliminary

PP

PP PP

PP

PP PP

PP

IN IN IN IN IN

IN IN

IN

IN IN

IN

IN IN

PP PP

PP

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN

IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN

IN

PP

IN IN IN IN IN IN IN

IN IN IN IN IN IN IN IN IN IN IN

IN

IN IN IN

IN

IN IN IN

IN

IN IN IN

IN

IN IN

IN

IN IN

PP

PP PP

PP

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

INVERTER DOES NOT USE THIS SIGNAL

LAYOUT NOTE: PLACE NEAR NORTHBRIDGE

ALL I2C BUSSES (PLACE IN ACCESSIBLE LOCATION TOP SIDE)

SPARE USB PORT

LAYOUT NOTE: PLACE NEAR SOUTHBRIDGE

MISC GROUND VIAS

FSB SIGNALS

* OPPOSITE END FROM CLOCK BUFFER

LAYOUT: PLACE CLOSE TO DESTINATION

P4MM

SM

OMIT

PP6C5

1

OMIT

SM

P4MM

PP6C4

1

P4MM

OMIT

SM

PP6C6

1

OMIT

P4MM

SM

PP6C8

1

SM

P4MM

OMIT

PP6C7

1

OMIT

P4MM

SM

PP6D0

1

OMIT

P4MM

SM

PP6D3

1

OMIT

P4MM

SM

PP6D4

1

OMIT

SM

P4MM

PP6D8

1

P4MM

OMIT

SM

PP6D9

1

SM

OMIT

P4MM

PP6E0

1

SM

OMIT

P4MM

PP6E1

1

60 59 58

60 58

11

7

11

7

11

7

11

7

11

7

60 59 58

59

5

26

5

HOLE-VIA

ZH500

1

HOLE-VIA

ZH501

1

HOLE-VIA

ZH502

1

HOLE-VIA

ZH503

1

HOLE-VIA

ZH504

1

HOLE-VIA

ZH505

1

HOLE-VIA

ZH506

1

HOLE-VIA

ZH507

1

HOLE-VIA

ZH508

1

HOLE-VIA

ZH509

1

HOLE-VIA

ZH510

1

HOLE-VIA

ZH511

1

HOLE-VIA

ZH512

1

HOLE-VIA

ZH513

1

HOLE-VIA

ZH514

1

HOLE-VIA

ZH515

1

HOLE-VIA

ZH516

1

HOLE-VIA

ZH517

1

HOLE-VIA

ZH518

1

HOLE-VIA

ZH519

1

HOLE-VIA

ZH520

1

HOLE-VIA

ZH521

1

HOLE-VIA

ZH522

1

HOLE-VIA

ZH523

1

HOLE-VIA

ZH524

1

HOLE-VIA

ZH525

1

HOLE-VIA

ZH526

1

HOLE-VIA

ZH527

1

HOLE-VIA

ZH528

1

HOLE-VIA

ZH529

1

P4MM

OMIT

SM

PP600

1

OMIT

P4MM

SM

PP601

1

P4MM

OMIT

SM

PP604

1

SM

P4MM

OMIT

PP605

1

P4MM

OMIT

SM

PP611

1

SM

OMIT

P4MM

PP610

1

P4MM

OMIT

SM

PP612

1

SM

OMIT

P4MM

PP613

1

84 13

84

84 13

I473

I474

I475

I476

I477

I478

I479

I480

I481

I482

I483

68

59

68

59

NC_AUD_BI_PORT_E_L

68

59

68

84

SM

P4MM

OMIT

PP626

1

P4MM

OMIT

SM

PP627

1

I513

NB_TSENS_HS_DXP

10

NB_TSENS_HS_DXN

10

CPU_XDP_CLK_N

34 11

CPU_XDP_CLK_P

34 11

11

7

11

7

11

7

11

7

11

7

26 11

7

26

5

59

5

67 60 58 21

5

60 58 22

67 60 58 23

60 59 21

60

6

67 60 58 23

60 34

60 58

67 60 58 23

60 59 58

60 23

60 58

76 58

94

94 85

75

8

75

8

75

8

75

8

75

8

75

8

75

8

75 23 14

75 26 14

5

75 21

7

26 23

84 77 58 26

77 58 23

76 75

3

80 79 77 58 23

83

80 79 78 77 76 66 65 26

6 5 3

83 78

3

83 79

3

80

3

79

3

80 34

3

83 82 80 79 78 77 75 59

5 3

11

7

97 83 75 59

3

83

80 79 78 77 76 66 65 26

6 5 3

83 82 80 79 78 77 75 59

5 3

84 83 76 41 27 26 10

6 3

83

3

NC_J7302_3

73

29

P4MM

SM

OMIT

PP621

1

SM

OMIT

P4MM

PP666

1

P4MM

SM

OMIT

PP665

1

P4MM

SM

OMIT

PP673

1

P4MM

SM

OMIT

PP674

1

SM

OMIT

P4MM

PP675

1

SYNC_DATE=06/29/2006

SYNC_MASTER=M51_HENRY

FUNC TEST 1 OF 2

051-7039

975

21

NO_TEST=TRUE

NC_AUD_BI_PORT_E_R

TP_MEM_B_A<14>

NO_TEST=TRUE

TP_MEM_B_A<15>

NO_TEST=TRUENO_TEST=TRUE

NC_AUD_BI_PORT_H_L

NO_TEST=TRUE

NC_SMC_MEM_ISENSE

NO_TEST=TRUE

NC_J7302_6

NO_TEST=TRUE

NC_AUD_BI_PORT_H_R

NO_TEST=TRUE

NC_AUD_VREF_PORT_B

SB_CLK48M_USBCTLR

PEG_R2D_N<0>

NO_TEST=TRUE

PEG_R2D_P<0>

NO_TEST=TRUE

NC_SMC_SYS_VSET

FSB_CPURST_L

SB_CLK14P3M_TIMER

SB_CLK100M_SATA_P SB_CLK100M_SATA_N

PP1V05_S0

FUNC_TEST=TRUE

PP1V5_S0

FUNC_TEST=TRUE

SMBUS_SMC_A_S3_SDA

LPC_FRAME_L

FUNC_TEST=TRUE

BOOT_LPC_SPI_L

FUNC_TEST=TRUE

PP24V_S0

FUNC_TEST=TRUE

PP3V3_S0

PP5V_S5

FUNC_TEST=TRUE FUNC_TEST=TRUE

PP3V3_S5

PP5V_S0

FUNC_TEST=TRUE

PP5V_S5

FUNC_TEST=TRUE

PP1V2_S3

FUNC_TEST=TRUE

PP1V8_S3

FUNC_TEST=TRUE

PPVCORE_CPU

FUNC_TEST=TRUE

PP3V3_S5

FUNC_TEST=TRUE

PP2V5_S5

FUNC_TEST=TRUE

PM_SLP_S4_L

FUNC_TEST=TRUE

PM_SLP_S3_L

FUNC_TEST=TRUE

VR_PWRGD_CK410

FUNC_TEST=TRUE

ALL_SYS_PWRGD

FUNC_TEST=TRUE

VR_PWRGOOD_DELAY

FUNC_TEST=TRUE

CPU_DPRSTP_L

FUNC_TEST=TRUE

CPU_VID<6>

FUNC_TEST=TRUE

CPU_VID<5>

FUNC_TEST=TRUE

CPU_VID<4>

FUNC_TEST=TRUE

CPU_VID<3>

FUNC_TEST=TRUE

CPU_VID<2>

FUNC_TEST=TRUE

CPU_VID<1>

FUNC_TEST=TRUE

LCD_PWM

FUNC_TEST=TRUE

INV_ENABLE_BL

FUNC_TEST=TRUE

CPU_VID<0>

ISENSE_CAL_EN

FUNC_TEST=TRUE

SV_SET_UP

FUNC_TEST=TRUE

SMC_RST_L

FUNC_TEST=TRUE

SMC_NMI

FUNC_TEST=TRUE

SMC_MD1

FUNC_TEST=TRUE

PM_SUS_STAT_L

FUNC_TEST=TRUE

INT_SERIRQ

FUNC_TEST=TRUE

FWH_INIT_L

FUNC_TEST=TRUE

PCI_CLK_PORT80

FUNC_TEST=TRUE

DEBUG_RST_L

FUNC_TEST=TRUE

PM_CLKRUN_L

LPC_AD<3>

FUNC_TEST=TRUE

LPC_AD<1>

FUNC_TEST=TRUE

LPC_AD<2>

FUNC_TEST=TRUE

LPC_AD<0>

FUNC_TEST=TRUE

SW_RST_BTN_L

FUNC_TEST=TRUE

POWER_BUTTON_L

FUNC_TEST=TRUE

XDP_DBRESET_L

FUNC_TEST=TRUE

XDP_BPM_L<1>

FUNC_TEST=TRUE

XDP_BPM_L<0>

FUNC_TEST=TRUE

XDP_BPM_L<3>

FUNC_TEST=TRUE

XDP_BPM_L<2>

FUNC_TEST=TRUE

NO_TEST=TRUE

PEG_R2D_N<2>

PEG_R2D_P<1>

NO_TEST=TRUE

NC_SMC_BATT_ISET

FUNC_TEST=TRUE FUNC_TEST=TRUE

FUNC_TEST=TRUE

XDP_BPM_L<5>

FUNC_TEST=TRUE

XDP_BPM_L<4>

FUNC_TEST=TRUE

ITPRESET_L

FUNC_TEST=TRUE

SMC_TX_L

FUNC_TEST=TRUE

SMC_TRST_L

FUNC_TEST=TRUE

SMC_TMS

FUNC_TEST=TRUE

SMC_TDI

FUNC_TEST=TRUE

SMC_TDO

FUNC_TEST=TRUE

SMC_MANUAL_RST_L

FUNC_TEST=TRUE

XDP_TMS

FUNC_TEST=TRUE

POWER_BUTTON_L

FUNC_TEST=TRUE

XDP_TDO

FUNC_TEST=TRUE

XDP_TDI

FUNC_TEST=TRUE

SMC_RX_L

FUNC_TEST=TRUE

XDP_TCK

FUNC_TEST=TRUE

SW_RST_BTN_L

NO_TEST=TRUE

PEG_D2R_P<3>

PEG_R2D_C_P<0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCI_GNT3_L

PCI_GNT3_L

DMI_S2N_N<0>

MEM_VREF_NB_1

MEM_VREF_NB_0

LPC_FRAME_L

SPI_SO

DMI_N2S_N<0>

PCIE_B_D2R_P

PCI_CLK_SB

NO_TEST=TRUE

NC_AUD_VREF_PORT_D

NO_TEST=TRUE

NC_SMS_X_AXIS

NO_TEST=TRUE

NC_SMC_P23

NO_TEST=TRUE

PEG_R2D_C_P<15>

NO_TEST=TRUE

PEG_R2D_C_N<15>

NO_TEST=TRUE

PEG_R2D_C_P<14>

NO_TEST=TRUE

PEG_R2D_C_N<14>

NO_TEST=TRUE

PEG_R2D_C_N<13>

NO_TEST=TRUE

PEG_R2D_C_P<13>

NO_TEST=TRUE

PEG_R2D_C_P<12>

NO_TEST=TRUE

PEG_R2D_C_N<12>

NO_TEST=TRUE

PEG_R2D_C_P<11>

NO_TEST=TRUE

PEG_R2D_C_N<11>

NO_TEST=TRUE

PEG_R2D_C_P<10>

NO_TEST=TRUE

PEG_R2D_C_N<10>

NO_TEST=TRUE

PEG_R2D_C_P<9>

NO_TEST=TRUE

PEG_R2D_C_N<9>

NO_TEST=TRUE

PEG_R2D_C_P<8>

NO_TEST=TRUE

PEG_R2D_C_N<8>

NO_TEST=TRUE

PEG_R2D_C_P<7>

NO_TEST=TRUE

PEG_R2D_C_N<7>

NO_TEST=TRUE

PEG_R2D_C_P<6>

NO_TEST=TRUE

PEG_R2D_C_N<6>

NO_TEST=TRUE

PEG_R2D_C_P<5>

NO_TEST=TRUE

PEG_R2D_C_N<5>

NO_TEST=TRUE

PEG_R2D_C_P<4>

NO_TEST=TRUE

PEG_R2D_C_N<4>

NO_TEST=TRUE

PEG_R2D_C_P<3>

NO_TEST=TRUE

PEG_R2D_C_N<3>

NO_TEST=TRUE

PEG_R2D_C_P<2>

NO_TEST=TRUE

PEG_R2D_C_N<2>

PEG_R2D_C_P<1>

NO_TEST=TRUE

PEG_R2D_C_N<1>

NO_TEST=TRUE

PEG_R2D_P<15>

NO_TEST=TRUE

PEG_R2D_N<15>

NO_TEST=TRUE

PEG_R2D_P<14>

NO_TEST=TRUE

PEG_R2D_N<14>

NO_TEST=TRUE

PEG_R2D_N<13>

NO_TEST=TRUE

PEG_R2D_P<13>

NO_TEST=TRUE

PEG_R2D_P<12>

NO_TEST=TRUE

PEG_R2D_N<12>

NO_TEST=TRUE

PEG_R2D_P<11>

NO_TEST=TRUE

PEG_R2D_N<11>

NO_TEST=TRUE

PEG_R2D_P<10>

NO_TEST=TRUE

PEG_R2D_N<10>

NO_TEST=TRUE

PEG_R2D_N<9>

NO_TEST=TRUE

PEG_R2D_P<9>

NO_TEST=TRUE

PEG_R2D_P<8>

NO_TEST=TRUE

PEG_D2R_P<15>

NO_TEST=TRUE

PEG_D2R_N<15>

NO_TEST=TRUE

PEG_D2R_N<14>

NO_TEST=TRUE

PEG_D2R_P<14>

NO_TEST=TRUE

PEG_D2R_P<13>

NO_TEST=TRUE

PEG_D2R_N<13>

NO_TEST=TRUE

PEG_D2R_P<12>

NO_TEST=TRUE

PEG_D2R_N<12>

NO_TEST=TRUE

PEG_D2R_P<11>

NO_TEST=TRUE

PEG_D2R_N<11>

NO_TEST=TRUE

PEG_D2R_P<10>

NO_TEST=TRUE

PEG_D2R_P<9>

NO_TEST=TRUE

PEG_D2R_N<9>

NO_TEST=TRUE

PEG_D2R_N<10>

NO_TEST=TRUE

PEG_D2R_P<8>

NO_TEST=TRUE

PEG_R2D_P<7>

NO_TEST=TRUE

PEG_R2D_N<7>

NO_TEST=TRUE

PEG_R2D_N<8>

NO_TEST=TRUE

PEG_R2D_P<6>

NO_TEST=TRUE

PEG_R2D_N<6>

NO_TEST=TRUE

PEG_R2D_N<5>

NO_TEST=TRUE

PEG_R2D_P<4>

NO_TEST=TRUE

PEG_R2D_P<3>

NO_TEST=TRUE

PEG_R2D_N<3>

NO_TEST=TRUE

PEG_D2R_N<8>

NO_TEST=TRUE

PEG_D2R_N<7>

NO_TEST=TRUE

PEG_D2R_P<7>

NO_TEST=TRUE

PEG_D2R_P<6>

NO_TEST=TRUE

PEG_D2R_N<5>

NO_TEST=TRUE

PEG_D2R_P<5>

NO_TEST=TRUE

PEG_D2R_N<6>

NO_TEST=TRUE

PEG_D2R_P<4>

NO_TEST=TRUE

PEG_D2R_N<3>

NO_TEST=TRUE

PEG_D2R_N<1>

MAKE_BASE=TRUE

NC_NB_CFG<12>

NB_CFG<12>

NB_CFG<11>

NB_CFG<8>

NB_CFG<4>

MAKE_BASE=TRUE

NC_NB_CFG<6>

NB_CFG<3>

MAKE_BASE=TRUE

NC_NB_CFG<3>

MAKE_BASE=TRUE

NC_NB_CFG<4>

NB_CFG<6>

NC_NB_CFG<13>

MAKE_BASE=TRUE

NB_CFG<14>

NB_CFG<15>

NB_CFG<17>

NB_CFG<13>

NB_CFG<10>

MAKE_BASE=TRUE

NC_NB_CFG<10>

MAKE_BASE=TRUE

NC_NB_CFG<8>

MAKE_BASE=TRUE

NC_NB_CFG<11>

NC_NB_CFG<14>

MAKE_BASE=TRUE

NC_NB_CFG<15>

MAKE_BASE=TRUE

NC_NB_CFG<17>

MAKE_BASE=TRUE

FUNC_TEST=TRUE

SMC_TCK

FUNC_TEST=TRUE

XDP_TRST_L

NB_RST_IN_L_R

DMI_S2N_P<0>

SMBUS_SB_SCL

SMBUS_SMC_A_S3_SCL

VR_PWRGOOD_DELAY

SMBUS_SB_SDA

TP_LVDS_BKLTEN

MAKE_BASE=TRUE

USB_F_P

DMI_N2S_P<0>

IDE_PDIOR_L

IDE_PDD<9>

IDE_PDIORDY

PCIE_B_D2R_N

SPI_SI

PCI_CLK_FW

PCI_CLK_SMC

NO_TEST=TRUE

PEG_R2D_N<1>

FUNC_TEST=TRUE

PM_DPRSLPVR

PEG_D2R_N<4>

NO_TEST=TRUE

PEG_D2R_N<2>

NO_TEST=TRUE

PEG_D2R_P<1>

PEG_D2R_P<0>

NO_TEST=TRUE

PEG_D2R_N<0>

MAKE_BASE=TRUE

TP_USB_F_N

USB_F_N

MAKE_BASE=TRUE

TP_USB_F_P

LVDS_BKLTEN

NO_TEST=TRUE

NC_SMC_BATT_TRICKLE_EN_L

NO_TEST=TRUE

NC_SMC_BATT_VSET

NO_TEST=TRUE

NC_SMC_P20

NO_TEST=TRUE

NC_SMC_SYS_ISET

NO_TEST=TRUE

NC_SMC_P27

NC_SMC_P26

NO_TEST=TRUE

NC_SMC_P21

PEG_D2R_P<2>

NO_TEST=TRUE

NC_SMC_BATT_CHG_EN

NO_TEST=TRUE

NC_SMC_P22

NO_TEST=TRUE

NC_AUD_BI_PORT_G_L

NO_TEST=TRUE

NC_ALS_GAIN NC_AUD_VREF_PORT_C

NO_TEST=TRUE

NC_SMS_Y_AXIS NC_SMS_Z_AXIS

NO_TEST=TRUE

PEG_R2D_C_N<0>

NO_TEST=TRUE

PEG_R2D_P<5>

NO_TEST=TRUE

PEG_R2D_N<4>

NO_TEST=TRUE

PEG_R2D_P<2>

NO_TEST=TRUE

67 60

75

12

58

63

26

63

34

11

34

22

19

21

58

22

54

34

22

14

22

38

54

58

44

58

19

23

7

23

21

27

22

14

5

22

14

22

14

27

5

27

19

22

14

21

22

34

22

13

Preliminary

125

OUT

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SILKSCREEN:EFI OK

FROM AC/DC

NEEDED AND THERE IS NO FREE PIN ON THE CONNECTOR

NOT SENDING 3.3V TO THE DRIVE BECAUSE IT IS NOT

TO HDD

SILKSCREEN:3

SILKSCREEN:RUN

CHASSIS HOLE UPPER RIGHT CORNER OF BOARD

CHASSIS HOLE NEAR POWER SWITCH CONNECTOR (BOT RIGHT)

TO NONPLATED HOLE TO LEFT OF EXTERNAL AUDIO CONNECTORS

SILKSCREEN:1

SYSTEM STATUS

GND RAILS

TO SYS ISENSE

CHASSIS GND

TO NONPLATED SLOT TO RIGHT OF EXTERNAL IO

CHASSIS NEXT TO AUDIO CONNECTORS

CHASSIS HOLE NEAR MXM

LOCATED NORTH OF CPU

HEATSINK BACKER PLATE STANDOFFS

CHASSIS HOLE NEAR ODD CONNECTOR (TOP MID)

AC/DC CONN

SILKSCREEN:2

SM

OMIT

XW601

1 2

SM

OMIT

XW602

1 2

74LC125

TSSOP

CRITICAL

U600

2

7 1

14

3

10V

20%

402

CERM

0.1UF

C600

1

2

GREEN-3.6MCD

2.0X1.25MM-SM

LED601

1

2

OMIT

4P25R3P5

ZH631

1

20% CERM

16V 402

0.01UF

NOSTUFF

C631

1

2

1K

1/16W

5% MF-LF

402

R602

1

2

4P25R3P5

OMIT

ZH630

1

0.01UF

20%

402

NOSTUFF

CERM

16V

C630

1

2

74LC125

CRITICAL

TSSOP

U600

5

7 4

14

6

74LC125

TSSOP

CRITICAL

U600

9

7

10

14

8

TSSOP

74LC125

CRITICAL

U600

12

7

13

14

11

402

5%

1/16W

68

MF-LF

R612

1 2

4025%MF-LF

1/16W

68

R611

1 2

5%

402

MF-LF

1/16W

68

R614

1 2

402

5%

1/16W MF-LF

68

TPM

R615

1 2

5%

402

1/16W MF-LF

68

R616

1 2

402

5%

68

MF-LF

1/16W

R617

1 2

5%

68

402

MF-LF

1/16W

R618

1 2

1/16W MF-LF

68

5%

402

R619

1 2

1/16W 402

1K

5% MF-LF

R600

1

2

GREEN-3.6MCD

2.0X1.25MM-SM

LED602

1

2

1K

1/16W MF-LF

DEVELOPMENT

402

5%

R605

1

2

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

LED600

1

2

CRITICAL

HM9606E-M2

M-RT-TH

J601

1

10 11 12

2 3 4 5 6

7 8 9

2.0X1.25MM-SM

GREEN-3.6MCD

LED603

1

2

3.3K

402

1/16W MF-LF

5%

R601

1

2

1K

1/16W MF-LF

5%

402

R604

1

2

2.0X1.25MM-SM

GREEN-3.6MCD

LED604

1

2

100PF

NOSTUFF

402

CERM

50V

5%

C620

1

2

100PF

NOSTUFF

5% 50V CERM 402

C621

1

2

1/16W

1% MF-LF

1.5K

402

R606

1

2

3

NOSTUFF

100PF

402

CERM

50V

5%

C622

1

2

SM

OMIT

XW603

1 2

4P25R3P5

OMIT

ZH611

1

NOSTUFF

6.3X5.5-SM

ELEC

16V

20%

100UF

C624

1

2

NOSTUFF

150UF

20%

6.3V SM

ELEC

C623

1

2

HSK-NUT-6.5MM

TH

SDF600

1

TH

HSK-NUT-6.5MM

SDF601

1

OMIT

4P25R3P5

ZH632

1

OMIT

4P25R3P5

ZH633

1

20%

0.01UF

CERM

16V 402

NOSTUFF

C633

1

2

OMIT

4P25R3P5

ZH634

1

0.01UF

20% CERM

16V 402

NOSTUFF

C634

1

2

402

MF-LF

1/16W

5%

10K

R607

1

2

SM1-LF

35V

100UF

ELEC

20%

NOSTUFF

C625

1

2

2N7002

SOT23-LF

Q600

3

1

2

5% MF-LF

1/16W

10K

402

R609

1

2

051-7039

6 97

21

SYNC_DATE=06/29/2006

POWER CONN / MISC

SYNC_MASTER=M51_PAUL

GPU_PRESENT

PP3V3_S0

PP24V_S5

=PP5V_S0_SATA

GND_CHASSIS_POWER_CONN

pp3v3_s5

SYS_POWERFAIL_L

GND_AUDIO

PP12V_S5_AC_DC

GND_CHASSIS_USB

PLT_RST_L

LCD_SHOULD_ON

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0

GND_CHASSIS_NEAR_PWR_SW

GND_CHASSIS_CPU_TEMP

VOLTAGE=0

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND_CHASSIS_NEAR_ODD_CON

GND_CHASSIS_RJ45

GND_CHASSIS_GPU_TEMP

GND_CHASSIS_AUDIO_INTERNAL

GND_CHASSIS_IO_RIGHT

MAKE_BASE=TRUE VOLTAGE=0 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GND_CHASSIS_DVI

GND_CHASSIS_ODD_TEMP

MIN_LINE_WIDTH=0.6MM VOLTAGE=0 MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

GND_CHASSIS_BNDI

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0

MAKE_BASE=TRUE

GND_CHASSIS_TOP_RIGHT

GND_CHASSIS_HDD_TEMP

=PP3V3_S0_SATA

GND_AUDIO_SPKRAMP

FW_RST_L

GND_CHASSIS_AUDIO_EXTERNAL

GND_CHASSIS_FIREWIRE

ITS_ALIVE

ITS_PLUGGED_IN

U600_11

ENET_RST_L

U600_3

SMC_LRESET_L

NB_RST_IN_L

PEG_RESET_L

TPM_LRESET_L

AIRPORT_RST_L

PP12V_LCD_CONN

PP3V3_S3PP3V3_S5

DEBUG_RST_L

ITS_RUNNING

GND_CHASSIS_IO_LEFT

VOLTAGE=0 MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

PP3V3_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0

GND_CHASSIS_NEAR_MXM

GPU_PRESENT_R

PP3V3_S0

=PP12V_S0_SATA

ACDC_TEMP

PP3V3_S5

U600_8

U600_6

83

80

84

79

84

79

83

78

83

78

76

77

76

77

41

76

41

76

27

66

27

66

26

65

26

65

10

26

83 26

10

26

6

82

53

6

5

83

5

78

72

74

27

5

60

5

3

76

74

76

47

22

10

43

10

73

97

66

47

66

71

45

73

46

42

58

14

85

67

53

94

3 3

5

3

23

3

59

3

Preliminary

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IN

IN IN

IN

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

OUT

IN

IN IN

IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

IN

A3* A4* A5* A6*

A8*

A10* A11* A12* A13*

A16*

A15*

A14*

ADSTB0*

REQ2*

REQ0* REQ1*

REQ3* REQ4*

A17* A18* A19* A20* A21*

A23*

A22*

A24* A25* A26*

A29*

A28*

A27*

A31*

A30*

ADSTB1*

A20M* FERR* IGNNE*

STPCLK*

LINT1

LINT0

SMI*

RSVD10

RSVD9

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD8

RSVD7

RSVD6

RSVD11

ADS* BNR*

BPRI*

DEFER*

DRDY* DBSY*

BR0*

IERR* INIT*

LOCK*

RESET*

RS0* RS1* RS2*

TRDY*

HIT*

HITM*

BPM0*

BPM2*

BPM1*

BPM3* PRDY* PREQ*

TCK TDI TDO TMS

TRST*

DBR*

PROCHOT*

THERMDA THERMDC

THERMTRIP*

RSVD12

RSVD13

RSVD16

RSVD19

RSVD18

RSVD17

RSVD20

BCLK0 BCLK1

RSVD15

RSVD14

A7*

A9*

ADDR GROUP0

XDP/ITP SIGNALS

CONTROL

ADDR GROUP1

RESERVED

HCLK

THERM

(1 OF 4)

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2 COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52* D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45* D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0 BSEL1

TEST2

GTLREF

DINV1*

DSTBP1*

D31*

D30*

D29*

D26* D27* D28*

D24* D25*

D23*

D21* D22*

D20*

D19*

D18*

D16* D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

TEST1

NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LAYOUT NOTE:

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE

TRACE LENGTH SHORTER THAN 0.5".

CPU IS HOT

AND CPU VR TO INFORM

CPU_PROCHOT_L TO SMC

CONNECTOR, NEED TERM

NO SPACE FOR ITP

ON ITP SIGNALS?

FSB_IERR# WITH A GND

SYMBOL NEED TO CHECK

0.1" AWAY

PLACE TESTPOINT ON

SHOULD CONNECT TO

PM_THRMTRIP#

ICH6-M AND GMCH

WITHOUT T-ING (NO STUB)

NOTE:

DUMMY PIN PIN ACTUALLY DRIVEN BY ITP

LAYOUT NOTE: 0.5" MAX LENGTH

CPU SCH AND PCB

TP_CPU_M_TEST4

PLACE GND VIA W/IN 1000 MILS

ROUTE TO TP VIA AND

SPARE[7-0],HFPLL:

TP_CPU_M_TEST3

NO STUFF R0701 IF USING ITP

1/16W

402

MF-LF

54.9

1%

R0703

1

2

68

1/16W

5%

402

MF-LF

R0704

1

2

1K

MF-LF 402

1% 1/16W

R0705

1

2

2.0K

MF-LF 402

1% 1/16W

R0706

1

2

1/16W

1%

402

MF-LF

54.9

R0720

1 2

1/16W

402

MF-LF

54.9

1%

R0721

1 2

1/16W

1%

402

MF-LF

54.9

R0722

1 2

54.9

402

1%

R0719

1 2

27.4

R0718

1 2

54.9

402

1%

R0717

1 2

402

27.4

R0716

1 2

NOSTUFF

402

0

R0730

1 2

NOSTUFF

1/16W

5%

402

MF-LF

1K

R0712

1

2

51

1/16W

5%

402

MF-LF

R0707

1

2

OMIT

CPU

YONAH-SKT

BGA

J0700

N3 P5 P2 L1 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U2 R4 T5 T3 W3 W5 Y4

J4

W2 Y1

L4 M3 K5 M1 N2 J1

H1

L2

V4

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6 B4

H4

AC2 AC1

D21

K3 H2 K2 J3 L5

B1 F3 F4 G3

AA1

C3

B25

T22

D2 F6 D3 C1 AF1 D22 C23

AA4

C24

AB2 AA3

M4 N5 T2 V3 B2

A3

D5

AC5 AA6 AB3

A24 A25

C7

AB5

G2

AB6

OMIT

YONAH-SKT

CPU

BGA

J0700

B22 B23 C21

R26 U26 U1 V1

E22 F24

J24 J23 H26 F26 K22 H25

N22 K25 P26 R23

E26

L25 L22 L23 M23 P25 P22 P23 T24 R24 L26

H22

T25 N24

AA23 AB24 V24 V26 W25 U23 U25 U22

F23

AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24

AC22 AC23

G25

AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21

E25

AE25 AF25 AF22 AF26

E23 K24 G24

J26

M26

V23

AC20

E5 B5 D24

H23

M24

W24

AD23

G22

N25

Y25

AE24

AD26

A2

AE6

D6 D7

C26

D25

402

MF-LF

1/16W

54.9

1%

R0702

1

2

54.9

MF-LF 402

1% 1/16W

R0701

1

2

SYNC_DATE=06/29/2006

SYNC_MASTER=M50_HENRY

CPU 1 OF 2-FSB

7

21

051-7039

97

CPU_INIT_L

FSB_BREQ0_L

=PP1V05_S0_CPU

FSB_A_L<6>

TP_CPU_A39_L

TP_CPU_EXTBREF

TP_CPU_A32_L

TP_CPU_SPARE0

XDP_BPM_L<2>

XDP_TDI

XDP_TRST_L

FSB_RS_L<2>

XDP_BPM_L<5>

XDP_BPM_L<4>

=PP1V05_S0_CPU

CPU_PROCHOT_L

FSB_DINV_L<0>

XDP_BPM_L<3>

CPU_PWRGD

XDP_TDI

XDP_TCK

XDP_TMS

=PP1V05_S0_CPU

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5>

FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_ADSTB_L<0>

FSB_REQ_L<2>

FSB_REQ_L<0> FSB_REQ_L<1>

FSB_REQ_L<3> FSB_REQ_L<4>

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<24> FSB_A_L<25> FSB_A_L<26>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<31>

FSB_A_L<30>

FSB_ADSTB_L<1>

CPU_A20M_L CPU_FERR_L CPU_IGNNE_L

CPU_STPCLK_L

CPU_NMI

CPU_INTR

CPU_SMI_L

TP_CPU_APM1_L

TP_CPU_APM0_L

TP_CPU_A36_L

TP_CPU_A35_L

TP_CPU_A34_L

TP_CPU_A33_L

TP_CPU_A38_L

TP_CPU_A37_L

TP_CPU_HFPLL

FSB_ADS_L FSB_BNR_L

FSB_BPRI_L

FSB_DEFER_L

FSB_DRDY_L FSB_DBSY_L

FSB_LOCK_L

FSB_CPURST_L

FSB_RS_L<0> FSB_RS_L<1>

FSB_TRDY_L

FSB_HIT_L

FSB_HITM_L

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_TCK

XDP_TDO XDP_TMS

XDP_DBRESET_L

CPU_THERMD_P CPU_THERMD_N

PM_THRMTRIP_L

TP_CPU_SPARE6

TP_CPU_SPARE5

FSB_CLK_CPU_P FSB_CLK_CPU_N

TP_CPU_SPARE1

FSB_A_L<7>

CPU_TEST1

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15>

FSB_DSTBN_L<0>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<18> FSB_D_L<19> FSB_D_L<20>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<23>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<29> FSB_D_L<30> FSB_D_L<31>

FSB_DSTBP_L<1> FSB_DINV_L<1>

CPU_TEST2

CPU_BSEL<1>

CPU_BSEL<0>

FSB_DSTBN_L<1>

CPU_BSEL<2>

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44>

FSB_D_L<46>

FSB_D_L<45>

FSB_DSTBP_L<2>

FSB_D_L<47>

FSB_DSTBN_L<2>

FSB_DINV_L<2>

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_DINV_L<3>

FSB_DSTBN_L<3> FSB_DSTBP_L<3>

CPU_COMP<0> CPU_COMP<1>

CPU_COMP<3>

CPU_COMP<2>

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_SLPCPU_L

CPU_PSI_L

FSB_DSTBP_L<0>

FSB_IERR_L

CPU_GTLREF

TP_CPU_SPARE2 TP_CPU_SPARE3 TP_CPU_SPARE4

TP_CPU_SPARE7

11

9

8

11

8

11

8

12

11

26

59

75

7

11

7

11

7

11

7

11

7

11

7

11

21

12

3

12

5

12

5

3

59

12

5

21

5

3

12

21

12

5

12

5

10

14

34

12

34

12

34

12

21

5

12

75

12

Preliminary

OUT OUT

OUT

OUT OUT

OUT

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59 VCC_60

VCC_58

VCC_57

VCC_56

VCC_54 VCC_55

VCC_53

VCC_51 VCC_52

VCC_49 VCC_50

VCC_48

VCC_47

VCC_46

VCC_44 VCC_45

VCC_43

VCC_41 VCC_42

VCC_40

VCC_39

VCC_38

VCC_36 VCC_37

VCC_33

VCC_35

VCC_34

VCC_31 VCC_32

VCC_29 VCC_30

VCC_28

VCC_26 VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18 VCC_19

VCC_17

VCC_16

VCC_15

VCC_13 VCC_14

VCC_12

VCC_10 VCC_11

VCC_8 VCC_9

VCC_7

VCC_6

VCC_5

VCC_3 VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82 VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90 VCC_91 VCC_92

VCC_94

VCC_93

VCC_95 VCC_96 VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12 VCCP_13 VCCP_14

VCCP_16

VCCP_15

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VSSSENSE

VCCSENSE

VCC_73

(3 OF 4)

VSS_82 VSS_83 VSS_84 VSS_85

VSS_87

VSS_86

VSS_88 VSS_89 VSS_90

VSS_92

VSS_91

VSS_93 VSS_94 VSS_95

VSS_97

VSS_96

VSS_100

VSS_98 VSS_99

VSS_102

VSS_101

VSS_105

VSS_103 VSS_104

VSS_106 VSS_107

VSS_110

VSS_109

VSS_108

VSS_111 VSS_112

VSS_115

VSS_114

VSS_113

VSS_116 VSS_117 VSS_118

VSS_120

VSS_119

VSS_123

VSS_121 VSS_122

VSS_124 VSS_125

VSS_128

VSS_126 VSS_127

VSS_129 VSS_130

VSS_133

VSS_131 VSS_132

VSS_134 VSS_135

VSS_138

VSS_136 VSS_137

VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_146

VSS_144 VSS_145

VSS_147 VSS_148

VSS_151

VSS_150

VSS_149

VSS_152 VSS_153

VSS_156

VSS_155

VSS_154

VSS_157 VSS_158 VSS_159

VSS_161

VSS_160

VSS_162

VSS_1 VSS_2 VSS_3

VSS_5

VSS_4

VSS_6 VSS_7 VSS_8

VSS_10

VSS_9

VSS_11 VSS_12

VSS_15

VSS_13 VSS_14

VSS_16 VSS_17 VSS_18 VSS_19 VSS_20

VSS_23

VSS_22

VSS_21

VSS_24 VSS_25

VSS_28

VSS_27

VSS_26

VSS_29 VSS_30

VSS_33

VSS_32

VSS_31

VSS_34 VSS_35

VSS_38

VSS_37

VSS_36

VSS_39 VSS_40 VSS_41 VSS_42 VSS_43

VSS_46

VSS_44 VSS_45

VSS_47 VSS_48

VSS_51

VSS_49 VSS_50

VSS_52 VSS_53

VSS_56

VSS_54 VSS_55

VSS_57 VSS_58 VSS_59 VSS_60 VSS_61

VSS_63

VSS_62

VSS_64 VSS_65 VSS_66

VSS_69

VSS_68

VSS_67

VSS_70 VSS_71

VSS_74

VSS_73

VSS_72

VSS_75 VSS_76

VSS_79

VSS_78

VSS_77

VSS_80 VSS_81

(4 OF 4)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LAYOUT NOTE:

TO CONNECT A DIFFERENCTIAL PROBE

TRANSMISSION LINE

RESISTORS TERMINATE THE 55 OHM

LOCATION WHERE THE TWO 54.9 OHM

BETWEEN VCCSENSE AND VSSSENSE AT THE

PROVIDE A TEST POINT (WITH NO STUB)

TO VCCSENSE_P/N WITH NO STUB

LAYOUT NOTE: CONNECT R0802-03

VCCA=1.5 ONLY

0.01UF

CERM

402

20% 16V

C0800

1

2

6.3V

20%

10UF

CERM 805-1

C0801

1

2

1/16W

1%

402

MF-LF

100

R0803

1

2

1/16W

1%

402

MF-LF

100

R0802

1

2

YONAH-SKT

BGA

CPU

OMIT

J0700

A7

B7

AF20

B9 B10 B12 B14 B15 B17 B18 B20

C9

A9

C10 C12 C13 C15 C17 C18

D9 D10 D12 D14

A10

D15 D17 D18

E7

E9 E10 E12 E13 E15 E17

A12

E18 E20

F7

F9 F10 F12 F14 F15 F17 F18

A13

F20 AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

A15

AB9

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7

A17

AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10

A18

AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15

A20

AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18

B26

V6

N6 R21 R6 T21 T6 V21 W21

G21 J6 K6 M6 J21 K21 M21 N21

AF7

AD6 AF5 AE5 AF4 AE3 AF2 AE2

AE7

BGA

YONAH-SKT

CPU

OMIT

J0700

A4

B8

V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2

B11

AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4

B13

AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8

B16

AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11

B19

AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14

B21

AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16

B24

AF19 AF21 AF24

C5 C8

C11

A8

C14 C16 C19

C2 C22 C25

D1

D4

D8 D11

A11

D13 D16 D19 D23 D26

E3

E6

E8 E11 E14

A14

E16 E19 E21 E24

F5

F8 F11 F13 F16 F19

A16

F2 F22 F25

G4

G1 G23 G26

H3

H6 H21

A19

H24

J2

J5 J22 J25

K1

K4 K23 K26

L3

A23

L6 L21 L24

M2

M5 M22 M25

N1

N4 N23

A26

N26

P3

P6 P21 P24 R2 R5 R22 R25 T1

B6 T4

T23 T26 U3 U6 U21 U24 V2 V5 V22

CPU 2 OF 2-PWR/GND

051-7039

21

8 97

SYNC_DATE=06/29/2006

SYNC_MASTER=M50_HENRY

CPU_VID<1>

CPU_VID<3> CPU_VID<4>

CPU_VID<6>

CPU_VCCSENSE_P

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

=PP1V5_S0_CPU

CPU_VCCSENSE_N

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

CPU_VID<0>

CPU_VID<2>

CPU_VID<5>

76

11

9

75

8

7

75

5

75

3

75

3

5

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SECONDARY)

PRIMARY)

SECONDARY)

PLACE 6 INSIDE SOCKET

PLACE 8 INSIDE SOCKET CAVITY ON L8 (NORTH SIDE

PLACE 8 INSIDE SOCKET CAVITY ON L8 (SOUTH SIDE

SOUTH SIDE SECONDARY

PRIMARY)

DESIGN FOR 44 CERAMIC AND 3 ELECT BULK 1800UF

VCC CORE DECOUPLING

NEED LARGE BULK FOR 1.05V

PLACE INSIDE SOCKET CAVITY ON L8 (NORTH SIDE SECONDARY)

VCCP CORE DECOUPLING

CPU HEATSINK MOUNTING HOLES

WE HAD A 330UF ELEC CAP HERE FOR 1.05V RAIL - CHECK WE CAN REMOVE

CAVITY ON L1 (SOUTH SIDE

PLACE 6 INSIDE SOCKET

CAVITY ON L1 (NORTH SIDE

805

X5R

20%

6.3V

22UF

C900

1

2

6.3V

20%

805

X5R

22UF

C996

1

2

6.3V

20%

805

X5R

22UF

C993

1

2

X5R 805

20%

6.3V

22UF

C994

1

2

6.3V

20%

805

X5R

22UF

C995

1

2

6.3V

20%

805

X5R

22UF

C988

1

2

X5R 805

20%

6.3V

22UF

C992

1

2

X5R 805

20%

6.3V

22UF

C991

1

2

6.3V

20%

805

X5R

22UF

C990

1

2

X5R 805

20%

6.3V

22UF

C989

1

2

X5R

20%

22UF

805

6.3V

C941

1

2

805

20% X5R

6.3V

22UF

C942

1

2

805

20% X5R

6.3V

22UF

C943

1

2

805

20% X5R

22UF

6.3V

C944

1

2

805

20%

6.3V

22UF

X5R

C945

1

2

805

20% X5R

6.3V

22UF

C946

1

2

20%

2.5V TANT D2T

470UF

NOSTUFF

C947

1

23

805

X5R

6.3V

20%

22UF

C901

1

2

X5R

20%

6.3V

22UF

805

C902

1

2

805

X5R

20%

6.3V

22UF

C904

1

2

6.3V

20%

805

22UF

NOSTUFF

X5R

C905

1

2

X5R

6.3V

20%

805

22UF

C906

1

2

805

X5R

6.3V

22UF

20%

C907

1

2

805

X5R

6.3V

20%

22UF

C908

1

2

805

X5R

6.3V

20%

22UF

C909

1

2

805

X5R

6.3V

20%

22UF

C910

1

2

805

X5R

6.3V

20%

22UF

C911

1

2

805

X5R

20%

6.3V

22UF

C912

1

2

805

6.3V X5R

20%

22UF

C913

1

2

X5R

6.3V

20%

805

22UF

NOSTUFF

C914

1

2

X5R

20%

22UF

805

6.3V

NOSTUFF

C915

1

2

22UF

20%

6.3V X5R 805

C916

1

2

X5R

20%

805

6.3V

22UF

NOSTUFF

C917

1

2

805

6.3V

20% X5R

22UF

C918

1

2

X5R

20%

805

6.3V

22UF

C919

1

2

805

X5R

20%

6.3V

22UF

C920

1

2

20%

805

X5R

22UF

6.3V

C921

1

2

805

20% X5R

6.3V

22UF

C922

1

2

20%

805

X5R

6.3V

22UF

C923

1

2

805

X5R

20%

6.3V

22UF

C924

1

2

20%

805

X5R

22UF

6.3V

C925

1

2

20%

0.1UF

402

10V CERM

C926

1

2

805

X5R

6.3V

20%

22UF

C928

1

2

805

X5R

6.3V

20%

22UF

C929

1

2

X5R

20%

6.3V 805

22UF

C930

1

2

805

6.3V X5R

22UF

20%

C931

1

2

6.3V X5R

20%

22UF

NOSTUFF

805

C932

1

2

0.1UF

CERM

10V 402

20%

C934

1

2

20% 402

10V CERM

0.1UF

C935

1

2

CERM

10V 402

0.1UF

20%

C936

1

2

20%

0.1UF

402

10V CERM

C937

1

2

CERM

10V 402

0.1UF

20%

C938

1

2

805

X5R

20%

6.3V

22UF

C939

1

2

6.3V X5R

20%

805

22UF

NOSTUFF

C903

1

2

4P75R4

OMIT

ZH607

1

16V

20%

CERM

0.01UF

402

C950

1

2

4P75R4

OMIT

ZH608

1

16V

20%

CERM

0.01UF

402

C951

1

2

4P75R4

OMIT

ZH609

1

16V

20%

CERM

0.01UF

402

C952

1

2

4P75R4

OMIT

ZH610

1

16V

20%

CERM

0.01UF

402

C953

1

2

X5R 805

20%

6.3V

22UF

C999

1

2

6.3V

20%

805

X5R

22UF

C998

1

2

X5R 805

20%

6.3V

22UF

C997

1

2

SYNC_MASTER=M51_HENRY

SYNC_DATE=06/29/2006

21

051-7039

9 97

CPU DECAPS & VID<>

=PPVCORE_S0_CPU

CPU_HS_ZH610CPU_HS_ZH607 CPU_HS_ZH609CPU_HS_ZH608

=PP1V05_S0_CPU

11

76 8 8 7 3

3

Preliminary

D+ D-

ALERT*/

THM*

SCLK

SDATA

VDD

GND

THM2*

DXP

SCLK

ALERT*

SDA THM PADGND

VCC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: I2C ADDR:98(1001 100) ON NVIDIA CARD

I2C ADDRESS: 90 (1001 000)

NB HEATSINK TEMPERATURE SENSE

CPU AND GPU REMOTE HEATSINK THERMAL SENSORS

ADD GND GUARD TRACES FOR CPU_THERMD_P/N

I2C ADDR:0x96

I2C ADDR:0x94

LAYOUT NOTE:

I2C ADDR:0x94

NOTE: SYMBOL SHOULD BE SHOWN ADT7461A

CPU INTERNAL DIODE THERMAL SENSOR

IF CPU T DIODE TO BE READ IN OFF STATE,

NOTE:

ROUTE ON SAME LAYER WITH 0.254MM TRACE WIDTH & SPACING.

THEN THIS SHOULD BE S5

MXM CARD TEMPERATURE SENSOR (GPU INTERNAL DIODE)

MAY NOT BE CONSISTENT WITH OTHER CARDS

AMBIENT TEMPERATURE (CPU FAN INTAKE) SENSOR

CPU_TSENS_INT

ADT7461

MSOP

CRITICAL

U1000

6

2 3

5

8 7

4

1

MF-LF

499

1%

1/16W

402

CPU_TSENS_INT

R1002

1 2

NOSTUFF

0.001UF

50V

402

CERM

10%

C1000

1

2

CPU_TSENS_INT

16V

10% X5R

0.1UF

402

C1001

1

2

499

CPU_TSENS_INT

1/16W

1%

MF-LF

402

R1017

1 2

1/16W

CPU_TSENS_INT

5%

MF-LF 402

10K

R1001

1

2

402

5%

MF-LF

10K

1/16W

CPU_TSENS_INT

R1000

1

2

GPU_TSENS_INT

5%

1/16W

0

R1060

12

GPU_TSENS_INT

0

1/16W

5%

R1061

12

M-ST-SM

GPU_TSENS_EXT

53398-05

CRITICAL

J1050

1

3 4 5

6

7

402

20%

0.1UF

10V CERM

CPU_TSENS_EXT

C1012

1

2

20%

CERM

16V

NOSTUFF

0.01UF

402

C1010

12

0.01UF

40216V

20%

CERM

NOSTUFF

C1011

12

GPU_TSENS_EXT

0.1UF

20% 10V

402

CERM

C1052

1

2

0.01UF

402

CERM

16V

NOSTUFF

20%

C1050

12

20%

NOSTUFF

16V

CERM

402

0.01UF

C1051

12

NB_TSENS_EXT

MAX6642ATT90

CRITICAL

TDFN

U1080

6

3

2

4

5

7

1

NOSTUFF

MF-LF

402

0

5%

1/16W

R1005

1 2

402

0.1UF

X5R

10% 16V

NB_TSENS_EXT

C1080

1

2

NB_TSENS_EXT

MF-LF

5%

1/16W

47

402

R1080

1 2

CERM

50V 402

0.0022uF

10%

NB_TSENS_EXT

C1082

1

2

SM

OMIT

XW1080

1 2

CRITICAL

SM-2MT-BLK-LF

NB_TSENS_EXT

J1080

3

4

1 2

5%

1/16W

0

NB_TSENS_EXT

R1085

12

NB_TSENS_EXT

0

1/16W

5%

R1086

12

M-RT-SM

CPU_TSENS_EXT

CRITICAL

HS8804F-B

J1000

5

6

1 2 3 4

53398-05

M-ST-SM

AMB_TSENS

CRITICAL

J1070

2 3 4 5

6

7

AMB_TSENS

CERM 402

10V

20%

0.1UF

C1072

1

2

NOSTUFF

20% 16V

CERM

402

0.01UF

C1070

12

0.01UF

402

CERM

16V

NOSTUFF

20%

C1071

12

1/16W

10K

MF-LF

5%

402

NB_TSENS_EXT

R1087

1

2

ASIC TEMP SENSORS

SYNC_DATE=(MASTER)

051-7039

21

10 97

SYNC_MASTER=M51_DAVE

THERM_DX_N

THRM_ALERT_L

THRM_THM

=SMB_THRM_CLK

=SMB_THRM_DATA

PP3V3_S0

GND_CHASSIS_CPU_TEMP

SMB_GPU_THRM_DATA

GND_CHASSIS_AMB_TEMP

PP3V3_S0

SMB_GPU_THRM_CLK

=SMB_GPU_THRM_CLK

=SMB_GPU_THRM_DATA

GND_CHASSIS_AMB_TEMP

=SMB_AMB_TEMP_CLK

=SMB_AMB_TEMP_DATA

GND_CHASSIS_GPU_TEMP

=SMB_GPU_HS_THRM_CLK

=SMB_GPU_HS_THRM_DATA

=SMB_CPU_HS_THRM_CLK

CPU_THERMD_P

GND_CHASSIS_CPU_TEMP

CPU_THERMD_N

THERM_DX_P

PM_THRM_L

=SMB_CPU_HS_THRM_DATA

PP3V3_S0

=SMB_NB_HS_THRM_DATA

=SMB_NB_HS_THRM_CLK

NB_TSENS_HS_DXN

U1080_VCC

SMB_U1080_SDA

U1080_ALERT

SMB_U1080_SCL

NB_TSENS_HS_DXP

84

83

76

41

27

26

10

6

5

10

5

10

58

5

27

3

6

85

10

3

85 27

27

10

27

6

27

7

6

7

23

27

3

27

5

Preliminary

OUT OUT

OUT

IN

IN IN

IO

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

ITP TCK SIGNAL LAYOUT NOTE:

THAT MAY IMPACT ITP FUNCTIONALITY

P7 HAS OTHER PULL UP RESISTORS

(FROM CK410M HOST 133/167MHZ)

(DEBUG PORT RESET)

(AND WITH RESET BUTTON)

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

NC

(DBA#)

(DBR#)

(DEBUG PORT ACTIVE)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(TCK)

518S0320

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S

CONNECTOR’S FBO PIN.

ITP

402

1/16W

1%

22.6

MF-LF

R1100

1 2

22.6

MF-LF

1/16W

1%

402

ITP

R1102

1 2

MF-LF

ITP

402

1% 1/16W

54.9

R1103

1

2

ITP

0.1UF

10% X5R

402

16V

C1100

1

2

ITP

1/16W

5% MF-LF

402

240

R1104

1

2

DEVELOPMENT

52435-2872

F-RT-SM

J1101

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28

29

3

30

4 5 6 7 8 9

1/16W MF-LF

1%

54.9

402

R1101

1

2

MF-LF

1/16W

5%

402

680

R1106

1

2

SYNC_MASTER=M50_HENRY

9711

21

051-7039

SYNC_DATE=06/29/2006

CPU ITP700FLEX DEBUG

XDP_DBRESET_L

XDP_TRST_L

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<3>

XDP_TCK

CPU_XDP_CLK_N CPU_XDP_CLK_P

XDP_TCK

XDP_TMS

XDP_TDI

XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_BPM_L<5>

=PP1V05_S0_CPU

=PP3V3_S5_SB_PM

ITP_TDO

ITPRESET_L

XDP_TDO

FSB_CPURST_L

=PP1V05_S0_CPU

11

11 9 9

26

11

8

12

8

7

23

7

5

3

5

3

Preliminary

IO

IO IO

OUT

IO

IO IO

IO

IO IO

IO

IO IO

IO

OUT

IO

OUT

IO IO

IO

IN

IO

IN

IO

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM* HLOCK*

HHIT*

HDSTBP2* HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1* HDSTBN2*

HDSTBN0*

HDINV2* HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10* HD11* HD12* HD13* HD14*

HD5*

HD7* HD8* HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21* HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10* HA11* HA12*

HADSTB1*

HREQ0* HREQ1* HREQ2* HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0.1uF

10% 16V X5R 402

C1211

1

2

402

MF-LF

1/16W

1%

200

R1211

1

2

402

MF-LF

1/16W

1%

100

R1210

1

2

402

MF-LF

1/16W

1%

54.9

R1220

1

2

24.9

1% 1/16W MF-LF

402

R1221

1

2

402

MF-LF

1/16W

1%

221

R1225

1

2

100

402

MF-LF

1/16W

1%

R1226

1

2

10% 16V X5R 402

0.1uF

C1226

1

2

0.1uF

10% 16V X5R 402

C1236

1

2

402

MF-LF

1/16W

1%

221

R1235

1

2

402

MF-LF

1/16W

1%

54.9

R1230

1

2

100

402

MF-LF

1/16W

1%

R1236

1

2

24.9

1% 1/16W MF-LF

402

R1231

1

2

OMIT

945GM

NB

BGA

U1200

H11 J12

G14

D9 J14

H13

J15 F14

D12 A11

C11

A12 A13

E13

G13 F12

B12

B14 C12

A14

H9

C14

D14

C9

E11 G11

F11 G12

F9

E8 B9

C13

J13 C6

F6

C7

AG2

AG1

B7

F1

J1

K7 J8

H4

J3

K11

G4 T10

W11

T3

U7

H1

U9

U11 T11

W9

T1

T8

T4

W7

U5

T9

J6

W6

T5

AB7 AA9

W4

W3

Y3

Y7

W5

Y10

H3

AB8

W2

AA4

AA7 AA2

AA6

AA10

Y8

AA1 AB4

K2

AC9

AB11 AC11

AB3

AC2 AD1

AD9

AC1 AD7

AC6

G1

AB5

AD10

AD4 AC8

G2

K9

K1

A7 C3

J7 W8

U3

AB10

J9

H8

K4

T7

Y5 AC4

K3

T6

AA5 AC5

K13

D3 D4

B3

D8

G8 B8

F8

A8

B4

E6 D6

E3

E7

E1

E2

E4

Y1

U1

W1

051-7039

9712

21

NB CPU Interface

SYNC_DATE=06/29/2006

SYNC_MASTER=M50_HENRY

NB_FSB_XRCOMP

=PP1V05_S0_FSB_NB

FSB_RS_L<2>

FSB_REQ_L<4>

FSB_D_L<30>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<17>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>

FSB_A_L<18> FSB_A_L<19> FSB_A_L<20>

FSB_A_L<31>

FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<15>

FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_ADSTB_L<0>

FSB_ADS_L

FSB_A_L<13>

NB_FSB_XSCOMP NB_FSB_XSWING

NB_FSB_YSCOMP

NB_FSB_YRCOMP

NB_FSB_YSWING

FSB_CLK_NB_P FSB_CLK_NB_N

FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L

FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L

FSB_DINV_L<3>

FSB_DSTBN_L<1>

FSB_DSTBP_L<0>

FSB_HIT_L

FSB_LOCK_L

FSB_HITM_L

FSB_RS_L<0> FSB_RS_L<1>

FSB_SLPCPU_L FSB_TRDY_L

FSB_D_L<16>

FSB_D_L<0>

FSB_D_L<3>

FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<2>

FSB_D_L<1>

FSB_DINV_L<2>

FSB_DINV_L<1>

FSB_DSTBN_L<0>

FSB_DINV_L<0>

FSB_DSTBP_L<3>

FSB_DSTBP_L<2>

FSB_DSTBP_L<1>

FSB_DSTBN_L<3>

FSB_DSTBN_L<2>

FSB_D_L<17>

NB_FSB_VREF

FSB_A_L<30>

FSB_A_L<29>

FSB_CPURST_L

12

3

7

34

7

Preliminary

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF TV_IRTNA

TV_DACB_OUT TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK L_DDC_DATA

EXP_A_COMPI EXP_A_COMPO

EXP_A_RXN0 EXP_A_RXN1 EXP_A_RXN2 EXP_A_RXN3 EXP_A_RXN4 EXP_A_RXN5 EXP_A_RXN6 EXP_A_RXN7 EXP_A_RXN8

EXP_A_RXN9 EXP_A_RXN10 EXP_A_RXN11 EXP_A_RXN12 EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11 EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9 EXP_A_TXN10 EXP_A_TXN11 EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9 EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13 EXP_A_TXP14 EXP_A_TXP15

L_CLKCTLB

L_BKLTEN L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

OUT

IN

OUT OUT

IN IN

OUT

IN

OUT

IO

IN

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

OUT

IN

IO IO

OUT

OUT OUT

OUT

OUT OUT

IN

OUT

IN

OUT

IO IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN# SDVO_INT#

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_RED SDVOC_GREEN SDVOC_BLUE SDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling.

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

filtering components. Unused DAC outputs should

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

connect to GND through 75-ohm resistors.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:

Composite: DACA only

TV-Out Disable

CRT Disable

Can leave all signals NC if LVDS is not implemented Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

BGA

NB

945GM

OMIT

U1200

E23

D23

C26

C25

C22

B22

J22

A21 B21

H23

D40 D38

F34

G38

V34 W38

Y34 AA38

AB34

AC38

H34

J38

L34 M38

N34

P38 R34

T38

D34 F38

T34

V38 W34

Y38

AA34 AB38

G34

H38 J34

L38

M34 N38

P34 R38

F36

G40

V36 W40

Y36 AA40

AB36

AC40

H36

J40

L36 M40

N36

P40 R36

T40

D36 F40

T36

V40 W36

Y40

AA36 AB40

G36

H40 J36

L40

M36 N40

P36 R40

G23

D32 J30

H30

H29 G26

G25 B38

C35

F32 C33

C32

A32

A33

B37

C37

B34

B35

A36

A37

E26

E27

F30

G30

D29

D30

F28

F29

A16

C18

A19

J20 B16

B18 B19

402

MF-LF

1/16W

1%

24.9

R1310

1

2

051-7039

21

9713

SYNC_MASTER=M50_HENRY

SYNC_DATE=06/29/2006

NB PEG / Video Interfaces

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT

TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

CRT_BLUE_L

CRT_BLUE

CRT_GREEN_L

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED_L

CRT_DDC_DATA

CRT_IREF

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_VDDEN

LVDS_VREFL

LVDS_VREFH

TP_LVDS_VBG

LVDS_IBG

LVDS_DDC_CLK LVDS_DDC_DATA

PEG_COMP

PEG_D2R_N<0> PEG_D2R_N<1> PEG_D2R_N<2>

PEG_D2R_P<0>

PEG_D2R_P<2>

PEG_D2R_P<4>

PEG_D2R_P<3>

PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<11> PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_P<0>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>

LVDS_BKLTEN

=PP1V5_S0_NB_PCIE

LVDS_CLKCTLB

CRT_VSYNC_R

CRT_HSYNC_R

PEG_D2R_P<1>

LVDS_CLKCTLA

LVDS_BKLTCTL

PEG_D2R_N<15>

PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14>

PEG_D2R_N<7>

PEG_D2R_N<9>

PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5> PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<10>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>

84

19

5

3

19

5

19

5

Preliminary

SM_CS0*

RSVD15

RSVD14

SM_CKE2

RSVD2 RSVD3

RSVD6

RSVD4 RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10 RSVD11 RSVD12 RSVD13

CFG1

CFG0

CFG2 CFG3 CFG4

CFG6

CFG5

CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14

CFG17

CFG16

CFG15

CFG18 CFG19 CFG20

PM_BM_BUSY* PM_EXTTS0* PM_EXTTS1* PW_THRMTRIP* PWROK RSTIN*

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC* CLK_REQ*

NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9

NC0 NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0 SM_CK1 SM_CK2

SM_CK0*

SM_CK3

SM_CK1* SM_CK2* SM_CK3*

SM_CKE0 SM_CKE1

SM_CKE3

SM_CS1* SM_CS2* SM_CS3*

SMOCDCOMP0 SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0 SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC PM

CLKDMI

MISC

(2 OF 10)

RSVD

IN

OUT

IN

IO IO

OUT

OUT OUT

OUT

OUT OUT

IN

IN IN

IN

IN IN

IN

IN IN

IN

OUT

IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

IPU

NC NC

IPU IPU IPU IPU

IPU IPU IPU

IPU

IPD

IPU

NC

NC NC

NC

(D_PLLMON1#)

(VSS_MCHDETECT)

(H_PCREQ#)

(H_PLLMON1#)

(H_PLLMON1)

(TV_DCONSEL1)

(TV_DCONSEL0)

(TESTIN#)

(H_PROCHOT#)

(D_PLLMON1)

(H_EDRDY#)

(LB_DATAP3)

(LB_DATAN3)

(LA_DATAP3)

(LA_DATAN3)

IPD

NC

OMIT

945GM

NB

BGA

U1200

K16

K18

E16 D15

G15

K15 C15

H16

G18 H15

J25 K27

J18

J26

F18

E15

F15 E18

D19 D16

G16

H32

A26

A27

D41

C40

AE35 AF39

AG35

AH39

AC35 AE39

AF35

AG39

AE37

AF41

AG37 AH41

AC37

AE41

AF37 AG41

AG33

AF33

K28

D1

C41

B2

AY41

AY1

AW41

AW1

A40

A4

A39

A3

C1

BA41

BA40 BA39

BA3

BA2 BA1

B41

G28

F25 H26

G6

AH33 AH34

T32

J29

A41

A35 A34

D28 D27

R32

F3 F7

AG11

AF11

H7

J19

K30

H28

H27

AY35

AW35

AR1

AT1

AW7

AY7

AW40

AY40

AU20

AT20

BA29 AY29

AW13

AW12 AY21

AW21

BA13 BA12

AY20 AU21

AL20

AF10

AT9

AV9

AK1

AK41

100

5% 1/16W MF-LF

402

R1430

1 2

1/16W MF-LF

5%

402

10K

R1441

1

2

MF-LF

1/16W

5%

402

10K

R1440

1

2

20% 10V CERM 402

0.1uF

C1416

1

2

20% 10V

CERM

402

0.1uF

C1415

1

2

80.6

MF-LF 402

1% 1/16W

R1410

1

2

80.6

MF-LF 402

1% 1/16W

R1411

1

2

10K

MF-LF

402

5%

1/16W

R1420

1

2

14 97

21

051-7039

NB Misc Interfaces

SYNC_DATE=06/29/2006

SYNC_MASTER=M50_HENRY

TP_NB_RSVD4_F7

TP_NB_RSVD3_F3

PM_EXTTS_L

NB_RST_IN_L_R

CLK_NB_OE_L

NB_CLK_DREFCLKIN_N NB_CLK_DREFCLKIN_P NB_CLK_DREFSSCLKIN_N NB_CLK_DREFSSCLKIN_P

=PP3V3_S0_NB

NB_TV_DCONSEL1

NB_TV_DCONSEL0

TP_NB_XOR_LVDS_A35

TP_NB_TESTIN_L

PM_DPRSLPVR

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<13>

NB_CFG<11>

NB_CFG<8>

NB_RST_IN_L

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0>

NB_CLK100M_GCLKIN_P

NB_CLK100M_GCLKIN_N

MEM_ODT<3>

MEM_ODT<0>

MEM_CKE<3>

MEM_CKE<1>

MEM_CKE<0>

MEM_CLK_N<3>

MEM_CLK_N<2>

MEM_CLK_N<1>

MEM_CLK_P<3>

MEM_CLK_N<0>

MEM_CLK_P<2>

MEM_CLK_P<1>

MEM_CLK_P<0>

NB_SB_SYNC_L

SDVO_CTRLDATA

SDVO_CTRLCLK

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

PM_BMBUSY_L

NB_CFG<20>

NB_CFG<19>

NB_CFG<15> NB_CFG<16> NB_CFG<17>

NB_CFG<14>

NB_CFG<10>

NB_CFG<9>

NB_CFG<7>

NB_CFG<5> NB_CFG<6>

NB_CFG<4>

NB_CFG<3>

NB_BSEL<2>

NB_BSEL<0>

MEM_CS_L<0>

NB_CFG<12>

MEM_ODT<2>

MEM_ODT<1>

MEM_CS_L<3>

MEM_CS_L<2>

MEM_CS_L<1>

MEM_CKE<2>

=PP1V8_S3_MEM_NB

MEM_RCOMP_L MEM_RCOMP

MEM_VREF_NB_0 MEM_VREF_NB_1

TP_NB_XOR_LVDS_A34 TP_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D27

TP_NB_XOR_FSB2_H7

NB_BSEL<1>

20

75

20

75

19

59

14

23

14

22

30

26

30

16

58

5

33

19

3

5

3

20

5

6

22

5

22

5

22

5

22

5

34

29

28

29

28

29

28

29

28

29

28

22

19

5

23

20

5

20

5

20

5

34

28

5

29

28

29

28

29

3

34

Preliminary

SA_DQ1

SA_DQ0

SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0 SA_DM1 SA_DM2 SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6 SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA1

SA_MA0

SA_MA2 SA_MA3

SA_MA5

SA_MA4

SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

IO

IO IO

IO

OUT

IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

SB_DQ1

SB_DQ0

SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0 SB_DM1 SB_DM2 SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6 SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7*

SB_MA1

SB_MA0

SB_MA2 SB_MA3

SB_MA5

SB_MA4

SB_MA6 SB_MA7

SB_MA9

SB_MA8

SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

IO IO

IO

IO IO

IO

OUT

IO

OUT

IO

OUT

IO

IO IO

IO

OUT

IO

OUT OUT

OUT

IO

OUT

IO

OUT

IO

OUT OUT

OUT

IO

OUT

IO

IO IO

IO

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

BGA

945GM

NB

OMIT

U1200

AU12

AV14

BA20

AY13 AJ33

AM35

AL26 AN22

AM14

AL9 AR3

AH4

AJ35

AJ34

AR31 AP31

AN38

AM36 AM34

AN33

AK26 AL27

AM26

AN24

AM31

AK28

AL28 AM24

AP26

AP23 AL22

AP21

AN20 AL23

AP24

AM33

AP20 AT21

AR12 AR14

AP13

AP12 AT13

AT12

AL14 AL12

AJ36

AK9

AN7 AK8

AK7 AP9

AN9

AT5 AL5

AY2

AW2

AK35

AP1

AN2

AV2 AT3

AN1 AL2

AG7

AF9 AG4

AF6

AJ32

AG9 AH6

AF4

AF8

AH31

AN35 AP33

AK33

AK32

AT33

AU33

AN28

AN27

AM22

AM21

AN12

AM12

AN8

AL8

AP3

AN3

AG5

AH5

AY16

AU14

AU13

AT17

AV20 AV12

AW16

BA16 BA17

AU16

AV17 AU17

AW17

AT16

AW14

AK23

AK24 AY14

BGA

945GM

NB

OMIT

U1200

AT24

AV23

AY28

AR24 AK36

AR38

AT36 BA31

AL17

AH8 BA5

AN4

AK39

AJ37

AU38 AV38

AP38

AR40 AW38

AY38

BA38 AV36

AR36

AP36

AP39

BA36

AU36 AP35

AP34

AY33 BA33

AT31

AU29 AU31

AW31

AR41

AV29 AW29

AM19 AL19

AP14

AN14 AN17

AM16

AP15 AL15

AJ38

AJ11

AH10

AJ9

AN10 AK13

AH11

AK10

AJ8

BA10

AW10

AK38

BA4

AW4

AY10

AY9

AW5 AY5

AV4

AR5 AK4

AK3

AN41

AT4 AK5

AJ5

AJ3

AP41

AT40 AV41

AM39

AM40

AT39

AU39

AU35

AT35

AR29

AP29

AR16

AP16

AR10

AT10

AR7

AT7

AN5

AP5

AY23

AW24

AV24

BA27

AY27 AR23

AY24

AR28 AT27

AT28

AU27 AV28

AV27

AW27

AU23

AK16

AK18 AR27

SYNC_DATE=06/29/2006

SYNC_MASTER=M50_HENRY

NB DDR2 Interfaces

051-7039

21

9715

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_BS<1>

MEM_B_BS<0>

MEM_B_BS<2>

MEM_B_CAS_L MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<3>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<2> MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4>

MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_BS<2>

MEM_A_CAS_L MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<2> MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

30

29

28

Preliminary

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47 VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37 VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34 VCCAUX_NCTF35

VCCAUX_NCTF32 VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27 VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24 VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42 VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19 VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14 VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7 VSS_NCTF8

VSS_NCTF5 VSS_NCTF6

VSS_NCTF4

VSS_NCTF2 VSS_NCTF3

VSS_NCTF0 VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61 VCC_NCTF62 VCC_NCTF63

VCC_NCTF60

VCC_NCTF57 VCC_NCTF58 VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53 VCC_NCTF54

VCC_NCTF52

VCC_NCTF50 VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46 VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38 VCC_NCTF39

VCC_NCTF36 VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF31 VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18 VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13 VCC_NCTF14

VCC_NCTF11 VCC_NCTF12

VCC_NCTF10

VCC_NCTF8 VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0 VCC_NCTF1

(7 OF 10)

NCTF

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place near pin BA15

Place near pin BA23

(Need to better define cavity)

Layout Note:

impacting part performance.

NCTF balls are Not Critical To Function

These connections can break without

Layout Note:

1.05V or 1.5V

Place in cavity

945GM

NB

BGA

OMIT

U1200

AA33

W33

P32

M19

L19

N18

M18

L18

P17

N17

M17

N16

M16

N32

L16

M32

L32

J32

AA31

W31

V31

T31

R31

P33

P31

N31

M31

AA30

Y30

W30

V30

U30

T30

R30

N33

P30

N30

M30

L30

AA29

Y29

W29

V29

U29

R29

L33

P29

M29

L29

AB28

AA28

Y28

V28

U28

T28

R28

J33

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

AA32

L26

N25

M25

L25

P24

N24

M24

AB23

AA23

Y23

Y32

P23

N23

M23

L23

AC22

AB22

Y22

W22

P22

N22

W32

M22

L22

AC21

AA21

W21

N21

M21

L21

AC20

AB20

V32

Y20

W20

P20

N20

M20

L20

AB19

AA19

Y19

N19

AU41

AT41

AR34

AR6

AP6

AN6

AL6

AK6

AJ6

AV1

AJ1

BA30

AY30

AW30

AV30

AU30

AT30

AR30

AP30

AN30

AM41

AM30

AM29

AL29

AK29

AJ29

AH29

AJ28

AH28

AJ27

AH27

AU40

BA26

AY26

AW26

AV26

AU26

AT26

AR26

AJ26

AH26

AJ25

BA34

AH25

AJ24

AH24

BA23

AJ23

BA22

AY22

AW22

AV22

AU22

AY34

AT22

AR22

AP22

AK22

AJ22

AK21

AK20

BA19

AY19

AW19

AW34

AV19

AU19

AT19

AR19

AP19

AK19

AJ19

AJ18

AJ17

AH17

AV34

AJ16

AH16

BA15

AY15

AW15

AV15

AU15

AT15

AR15

AJ15

AU34

AJ14

AJ13

AH13

AK12

AJ12

AH12

AG12

AK11

BA8

AY8

AT34

AW8

AV8

AT8

AR8

AP8

BA6

AY6

AW6

AV6

AT6

10%

0.47UF

CERM-X5R

6.3V

402

C1610

1

2

805-1

6.3V

20%

CERM

10UF

C1621

1

2

805-1

CERM

10UF

20%

6.3V

C1620

1

2

945GM

NB

BGA

OMIT

U1200

AD27 AC27

AD26

AC26 AB26

AA26

Y26 W26

V26

U26 T26

R26

AB27

AD25 AC25

AB25 AA25

Y25

W25 V25

U25

T25 R25

AA27

AD24

AC24 AB24

AA24

Y24

W24

V24 U24

T24

R24

Y27

AD23

V23

U23 T23

R23

AD22

V22

U22 T22

R22

W27

AD21

V21

U21

T21 R21

AD20

V20

U20

T20 R20

V27

AD19

V19 U19

T19

AD18 AC18

AB18 AA18

Y18

W18

U27

V18

U18

T18

T27

R27

AG27

AF27

AG22 AF22

AG21

AF21 AG20

AF20

AG19 AF19

R19 AG18

AG26

AF18

R18 AG17

AF17

AE17 AD17

AB17

AA17 W17

V17

AF26

T17

R17

AG16 AF16

AE16

AD16 AC16

AB16

AA16 Y16

AG25

W16 V16

U16

T16 R16

AG15

AF15 AE15

AD15

AC15

AF25

AB15

AA15 Y15

W15

V15 U15

T15

R15

AG24

AF24 AG23

AF23

AE27 AE26

AC17

Y17 U17

AE25

AE24 AE23

AE22

AE21 AE20

AE19

AE18

10%

0.47UF

CERM-X5R

6.3V

402

C1611

1

2

10%

0.47UF

CERM-X5R

6.3V

402

C1612

1

2

10%

0.47UF

CERM-X5R

6.3V

402

C1613

1

2

10%

0.47UF

CERM-X5R

6.3V

402

C1614

1

2

10%

0.47UF

CERM-X5R

6.3V

402

C1615

1

2

NB Power 1

SYNC_DATE=06/29/2006

SYNC_MASTER=M51_HENRY

051-7039

21

9716

NB_VCCSM_LF2 NB_VCCSM_LF1

=PPVCORE_S0_NB

=PP1V5_S0_NB_VCCAUX

=PPVCORE_S0_NB

NB_VCCSM_LF5

NB_VCCSM_LF4

=PP1V8_S3_MEM_NB

19

16

17

16

14

3

Preliminary

VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8

VTT9 VTT10 VTT11 VTT12 VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25

VTT27

VTT26

VTT28 VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35 VTT36 VTT37

VTT39

VTT38

VTT40 VTT41 VTT42 VTT43 VTT44 VTT45

VTT48

VTT46 VTT47

VTT49 VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58 VTT59 VTT60 VTT61 VTT62

VTT64

VTT63

VTT65 VTT66 VTT67

VTT69

VTT68

VTT70 VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2

VCC3G0 VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL VCCA_3GBG VSSA_3GBG

VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG VSSA_TVBG

VCCA_TVDACC0 VCCA_TVDACC1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACA0 VCCA_TVDACA1

VCCD_HMPLL0 VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0 VCCD_LVDS1

VCCD_TVDAC

VCC_HV1 VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14 VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23 VCCAUX24

VCCAUX22

VCCAUX25 VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30 VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34 VCCAUX35 VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39 VCCAUX40

POWER

(8 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

945GM

NB

BGA

OMIT

U1200

AJ41 AB41

Y41 V41

R41

N41 L41

A23 B23

B25

C30

B30

A30

G41

AC33

F21

E21

B26

C39

AF1

A38

AF2

H20

E19

F19

C20

D20

E20 F20

AK31 AF31

AE30

AD30 AC30

AG29

AF29 AE29

AD29

AC29 AG28

AF28

AE31

AE28

AH22

AJ21 AH21

AJ20

AH20 AH19

P19

P16

AH15

AC31

P15 AH14

AG14

AF14 AE14

Y14

AF13 AE13

AF12

AE12

AL30

AD12

AK30

AJ30 AH30

AG30 AF30

AH1

AH2

A28

B28

C28

H19

D21

H22

H41

G21

B39

G20

AC14

AB14

AD13 AC13

AB13 AA13

Y13

W13 V13

U13

T13 R13

W14

N13

M13 L13

AB12 AA12

Y12

W12 V12

U12

T12

V14

R12

P12

N12 M12

L12 R11

P11

N11 M11

R10

T14

P10 N10

M10

P9 N9

M9 R8

P8

N8 M8

R14

P7

N7 M7

R6

P6 M6

A6 R5

P5

N5

P14

M5

P4

N4 M4

R3

P3 N3

M3 R2

P2

N14

M2 D2

AB1

R1 P1

N1

M1

M14

L14

402

CERM-X5R

6.3V

0.47UF

10%

C1711

1

2

0.22UF

X5R

20%

6.3V

402

C1712

1

2

402

6.3V

CERM-X5R

0.47UF

10%

C1713

1

2

17 97

21

051-7039

SYNC_DATE=06/29/2006

NB Power 2

SYNC_MASTER=M51_HENRY

=PP1V05_S0_NB_VTT

NB_VTTLF_CAP3

PP2V5_S0_NB_VCCA_CRTDAC

=PP1V5_S0_NB_VCCAUX

PP1V5_S0_NB_VCCD_QTVDAC

=PP3V3_S0_NB_VCC_HV

PP1V5_S0_NB_VCCD_TVDAC

=PP1V5_S0_NB_VCCD_LVDS

=PP1V5_S0_NB_VCCD_HMPLL

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVBG

PP1V5_S0_NB_VCCA_MPLL

=PP2V5_S0_NB_VCCA_LVDS GND_NB_VSSA_LVDS

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_DPLLA

GND_NB_VSSA_CRTDAC

GND_NB_VSSA_3GBG

=PP2V5_S0_NB_VCCA_3GBG

PP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0_NB_VCC3G

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

PP1V5_S0_NB_VCCA_DPLLB

NB_VTTLF_CAP1

NB_VTTLF_CAP2

19

16

19

3

19

3

19

3

19

3

19

3

19

Preliminary

VSS_1

VSS_0

VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7

VSS_9

VSS_8

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17

VSS_19

VSS_18

VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26

VSS_28

VSS_27

VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

VSS_49

VSS_48

VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

VSS_73

VSS_72

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79

VSS_82

VSS_80 VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92 VSS_93 VSS_94

VSS_96

VSS_95

VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125

VSS_127

VSS_126

VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135

VSS_137

VSS_136

VSS_138 VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156

VSS_158

VSS_157

VSS_159 VSS_160 VSS_161 VSS_162

VSS_164

VSS_163

VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170

VSS_172

VSS_171

VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269 VSS_270

VSS_268

VSS_266 VSS_267

VSS_265

VSS_264

VSS_263

VSS_261 VSS_262

VSS_260

VSS_259

VSS_258

VSS_256 VSS_257

VSS_255

VSS_254

VSS_253

VSS_251 VSS_252

VSS_250

VSS_248 VSS_249

VSS_247

VSS_246

VSS_245

VSS_243 VSS_244

VSS_242

VSS_241

VSS_240

VSS_238 VSS_239

VSS_237

VSS_236

VSS_235

VSS_233 VSS_234

VSS_232

VSS_231

VSS_230

VSS_228 VSS_229

VSS_227

VSS_225 VSS_226

VSS_224

VSS_223

VSS_222

VSS_220 VSS_221

VSS_219

VSS_218

VSS_217

VSS_215 VSS_216

VSS_214

VSS_213

VSS_212

VSS_210 VSS_211

VSS_209

VSS_207 VSS_208

VSS_205 VSS_206

VSS_204

VSS_202 VSS_203

VSS_201

VSS_200

VSS_199

VSS_197 VSS_198

VSS_196

VSS_195

VSS_194

VSS_192 VSS_193

VSS_191

VSS_190

VSS_189

VSS_187 VSS_188

VSS_186

VSS_184 VSS_185

VSS_183

VSS_182

VSS_180 VSS_181

VSS_273 VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282 VSS_283 VSS_284

VSS_286

VSS_285

VSS_287 VSS_288 VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301 VSS_302

VSS_300

VSS_304

VSS_303

VSS_305 VSS_306 VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312 VSS_313 VSS_314 VSS_315

VSS_317

VSS_316

VSS_318 VSS_319 VSS_320

VSS_322

VSS_321

VSS_323 VSS_324 VSS_325

VSS_327

VSS_326

VSS_328 VSS_329 VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338 VSS_339 VSS_340

VSS_342 VSS_343

VSS_341

VSS_345

VSS_344

VSS_346 VSS_347 VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

VSS

(10 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB

945GM

BGA

OMIT

U1200

AC41

AA41

AN40

AE34

AC34 C34

AW33

AV33 AR33

AE33

AB33 Y33

V33

AK40

T33 R33

M33 H33

G33

F33 D33

B33

AH32 AG32

AJ40

AF32

AE32 AC32

AB32 G32

B32

AY31 AV31

AN31

AJ31

AH40

AG31

AB31

Y31 AB30

E30 AT29

AN29

AB29 T29

N29

AG40

K29 G29

E29

C29 B29

A29 BA28

AW28

AU28 AP28

AF40

AM28

AD28 AC28

W28

J28 E28

AP27 AM27

AK27

J27

AE40

G27

F27

C27 B27

AN26

M26 K26

F26 D26

AK25

B40

P25 K25

H25

E25 D25

A25

BA24 AU24

AL24 AW23

AY39 AW39

W41

AV39

AR39 AN39

AJ39

AC39 AB39

AA39

Y39

W39

V39

T41

T39

R39

P39 N39

M39

L39 J39

H39 G39

F39

P41

D39 AT38

AM38

AH38 AG38

AF38

AE38

C38

AK37 AH37

M41

AB37

AA37

Y37

W37

V37

T37

R37

P37

N37

M37

J41

L37

J37

H37

G37

F37

D37 AY36

AW36

AN36 AH36

F41

AG36 AF36

AE36

AC36

C36

B36

BA35 AV35

AR35

AH35

AV40

AB35

AA35

Y35

W35

V35

T35

R35

P35

N35

M35

AP40

L35

J35

H35

G35

F35

D35 AN34

AK34

AG34

AF34

NB

945GM

BGA

OMIT

U1200

AT23 AN23

AM23

AH23 AC23

W23 K23

J23

F23 C23

AA22

K22 G22

F22

E22 D22

A22 BA21

AV21

AR21 AN21

AL21

AB21

Y21

P21

K21

J21

H21

C21

AW20

AR20 AM20

AA20

K20

B20

A20

AN19 AC19

W19

K19

G19

C19 AH18

P18

H18

D18

A18

AY17 AR17

AP17 AM17

AK17

AV16 AN16

AL16

J16

F16

C16

AN15 AM15

AK15

N15

M15

L15

B15

A15

BA14 AT14

AK14

AD14 AA14

U14

K14

H14

E14 AV13

AR13

AN13 AM13

AL13

AG13

P13

F13

D13

B13

AY12 AC12

K12

H12

E12

AD11

AA11

Y11

J11 D11

B11

AV10 AP10

AL10 AJ10

AG10

AC10 W10

U10

BA9 AW9

AR9

AH9 AB9

Y9 R9

G9

E9 A9

AG8

AD8 AA8

U8

K8 C8

BA7 AV7

AP7

AL7 AJ7

AH7

AF7 AC7

R7

G7 D7

AG6 AD6

AB6

Y6 U6

N6

K6 H6

B6

AV5 AF5

AD5 AY4

AR4

AP4 AL4

AJ4

Y4 U4

R4

J4 F4

C4 AY3

AW3

AV3 AL3

AH3

AG3 AF3

AD3

AC3 AA3

G3 AT2

AR2

AP2 AK2

AJ2

AD2 AB2

Y2

U2 T2

N2 J2

H2

F2 C2

AL1

SYNC_DATE=06/29/2006

SYNC_MASTER=M50_HENRY

NB Grounds

051-7039

21

9718

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place in cavity

Layout Note:

Layout Note: Route to caps, then GND

be placed in cavity

3GPLL 10uF cap should

Layout Note:

1uH, 20%

be within 5 mm of NB edge

TVOUT DISABLE

close to MCH

Place L and C

be close to MCH

Place on the edge

Layout Note:

10uF caps should

on opposite side.

LVDS DISABLE

Layout Note:

DISPLAY DISABLE

TVOUT DISABLE

Layout Note:

These 4 0.1uF caps should

2.5V POLY SMB2

220UF

20%

C1970

1

2

0.22uF

402

6.3V

20%

X5R

C1967

1

2

2.2UF

10%

6.3V

603

CERM1

C1966

1

2

CERM

4.7uF

6.3V

603

20%

C1965

1

2

CERM

20%

402

10V

0.1uF

C1976

1

2

10uF

20%

6.3V X5R 603

C1975

1

2

0.51

1%

402

MF-LF

1/16W

R1975

1 2

0805

1.0UH-220MA-0.12-OHM

L1975

1 2

0.1uF

10V CERM 402

20%

C1918

1

2

0.1uF

20%

402

CERM

10V

C1915

1

2

10uF

20%

6.3V X5R 603

C1914

1

2

10V CERM 402

20%

0.1uF

C1916

1

2

5%

402

MF-LF

1/16W

1K

R1980

1 2

402

MF-LF

1/16W

5%

1K

R1981

1

2

MF-LF 402

1/16W

5%

1K

R1983

1

2

5%

402

MF-LF

1/16W

1K

R1982

1 2

1210

91NH

L1970

1 2

OMIT

SM

XW1900

1 2

330UF

NOSTUFF

ELEC

6.3V

20%

CASE-C1

C1968

1

2

0603

FERR-120-OHM-0.2A

L1934

1 2

6.3V

20%

0.22uF

402

X5R

C1907

1

2

10uF

20%

6.3V X5R 603

C1972

1

2

603

6.3V

10uF

20%

X5R

C1971

1

2

X5R

20%

0.22uF

6.3V

402

C1906

1

2

X5R

20%

0.22uF

6.3V

402

C1905

1

2

1UF

402

6.3V

10%

CERM

C1904

1

2

402

10V CERM

20%

0.1uF

C1937

1

2

0.1uF

402

CERM

10V

20%

C1935

1

2

6.3V

20%

805

22uF

X5R

C1934

1

2

0603

FERR-120-OHM-0.2A

L1936

1 2

22uF

X5R 805

6.3V

20%

C1936

1

2

10uF

603

20%

6.3V X5R

C1903

1

2

603

20%

X5R

6.3V

10uF

C1902

1

2

20%

6.3V

CASE-C1

ELEC

330UF

C1901

1

2

330UF

CASE-C1

6.3V

20%

ELEC

C1900

1

2

SYNC_MASTER=M51_DAVE

NB (GM) Decoupling

SYNC_DATE=(MASTER)

19 97

21

051-7039

=PPVCORE_S0_NB

CRT_BLUE

CRT_BLUE_L

CRT_GREEN

CRT_GREEN_L

CRT_IREF

CRT_RED

CRT_RED_L

PP2V5_S0_NB_VCCA_CRTDAC

SDVO_CTRLCLK

GND_NB_VSSA_TVBG

SDVO_CTRLDATA

CRT_DDC_DATA

GND_NB_VSSA_CRTDAC

TP_LVDS_CLKCTLA

TRUE

=PP1V5_S0_NB_3GPLL

PP1V5_S0_NB_3GPLL_F

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

=PP1V5_S0_NB_3GPLL

TP_NB_VCCA_DPLLA

TRUE

LVDS_DDC_CLK

LVDS_CLKCTLA

LVDS_BKLTCTL

=PP2V5_S0_NB_VCC_TXLVDS

TP_SDVO_CTRLDATA

TRUE

TP_SDVO_CTRLCLK

TRUE

TP_LVDS_BKLTCTL

TRUE

TP_LVDS_DDC_DATA

TRUE

=PP1V5_S0_NB_VCCD_LVDS

LVDS_VREFL

TP_LVDS_B_CLK_P

TRUE

TP_LVDS_B_CLK_N

TRUE

LVDS_A_DATA_P<0>

LVDS_VREFH

LVDS_B_DATA_N<1> LVDS_B_DATA_N<2>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_N

TP_LVDS_B_DATA_N<0>

TRUE

TP_LVDS_A_DATA_P<2>

TRUE

TP_LVDS_A_DATA_P<0>

TRUE

TP_LVDS_A_DATA_N<1>

TRUE

TP_LVDS_A_DATA_N<2>

TRUE

TP_LVDS_A_DATA_N<0>

TRUE

TP_LVDS_A_DATA_P<1>

TRUE

LVDS_A_DATA_P<1>

LVDS_B_DATA_P<2>

=PP2V5_S0_NB_VCCA_LVDS

TP_LVDS_VREFH

TRUE

GND_NB_VSSA_LVDS

LVDS_IBG

LVDS_VDDEN

LVDS_BKLTEN

TP_LVDS_IBG

TRUE

TP_GND_NB_VSSA_LVDS

TRUE

TP_LVDS_VDDEN

TRUE

TP_LVDS_BKLTEN

TRUE

TP_LVDS_CLKCTLB

TRUE

TP_LVDS_DDC_CLK

TRUE

LVDS_B_DATA_P<0> LVDS_B_DATA_P<1>

TP_LVDS_B_DATA_P<1>

TRUE

LVDS_B_CLK_P

LVDS_A_CLK_N

TP_LVDS_B_DATA_P<2>

TRUE

TP_LVDS_B_DATA_N<1>

TRUE

TP_LVDS_B_DATA_N<2>

TRUE

TP_LVDS_B_DATA_P<0>

TRUE

TP_LVDS_VREFL

TRUE

CRT_DDC_CLK

TRUE

TP_CRT_DDC_CLK

CRT_HSYNC_R

TRUE

TP_CRT_DDC_DATA

TP_NB_VCCA_DPLLB

TRUE

NB_CLK_DREFCLKIN_P

LVDS_A_CLK_P

TP_LVDS_A_CLK_P

TRUE

TP_LVDS_A_CLK_N

TRUE

=PP1V5_S0_NB_VCCAUX

=PP2V5_S0_NB_VCCSYNC

CRT_VSYNC_R

NB_CLK_DREFCLKIN_N

NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFSSCLKIN_P

PP1V5_S0_NB_VCCA_DPLLA PP1V5_S0_NB_VCCA_DPLLB

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.0 mm

PP1V5_S0_NB_VCCA_HPLL

=PP3V3_S0_NB_VCC_HV

=PP2V5_S0_NB_VCCA_3GBG

VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_3GPLL

MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.0 mm

PP1V5_S0_NB_VCC3G

MIN_LINE_WIDTH=1.0 mm

PP1V5_S0_NB_VCCA_MPLL

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

LVDS_DDC_DATA

LVDS_CLKCTLB

=PP1V8_S3_MEM_NB

GND_NB_VSSA_3GBG

=PP1V5_S0_NB_PLL

=PP1V05_S0_NB_VTT

MEM_VREF_NB_1 MEM_VREF_NB_0

TV_IRTNC

TV_IRTNB

TV_IRTNA

TV_IREF

TV_DACC_OUT

TV_DACB_OUT

TV_DACA_OUT

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVBG

PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QTVDAC

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB

19

17

16

19

13

16

17

14

17

14 14

3

13

17

14

17

14

13

17

3

13

17

13

17

13

5

13

14

13

3

17

13

14

17

3

17

13

3

17

3

5 5

13

17

3

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Internal pull-ups

Internal pull-up

RESERVED

NB_CFG<11>

NB_CFG<10>

High = Mobile CPU

NB_CFG<7>

RESERVED

Internal pull-up

DMI x2 Select

PROBABLY NOT NEEDED

Lane Reversal

NB_CFG<4>

NB_CFG<3>

RESERVED

NB_CFG<13:12>

NB_CFG<14>

NB_CFG<5>

NB_CFG<15>

NB_CFG<16>

NB_CFG<6>

NB_CFG<17>

NB_CFG<18>

NB_CFG<8>

NB_CFG<9>

NB_CFG<19>

NB_CFG<20>

Low = DMIx2

High = DMIx4

Low = RESERVED

High = Normal

PCIE Graphics

RESERVED

CPU Strap

RESERVED

Low = Reversed

Internal pull-up

11 = Normal Operation

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

00 = Partial Clock Gating Disable

RESERVED

Internal pull-up

RESERVED

High = Enabled

Low = Disabled

RESERVED

FSB Dynamic ODT

or PCIe x1

Low = Only SDVO

High = Both active

945 External Design Spec says reserved

Internal pull-down

Low = 1.05V

High = 1.5V

Low = Normal

High = Reversed DMI Lane Reversal

VCC Select

Interop. Mode

PCIe Backward

NBCFG_DMI_X2

MF-LF

1/16W

2.2K

5%

402

R2075

1

2

NBCFG_DYN_ODT_DISABLE

402

MF-LF

1/16W

5%

2.2K

R2085

1

2

MF-LF

NBCFG_VCC_1V5

2.2K

5% 1/16W

402

R2058

1

2

NBCFG_DMI_REVERSE

2.2K

5% 1/16W MF-LF 402

R2059

1

2

2.2K

5% 1/16W MF-LF 402

NBCFG_SDVO_AND_PCIE

R2060

1

2

NO STUFF

2.2K

5% 1/16W MF-LF 402

R2077

1

2

NBCFG_PEG_REVERSE

2.2K

5% 1/16W MF-LF 402

R2079

1

2

SYNC_DATE=06/29/2006

SYNC_MASTER=M50_HENRY

NB Config Straps

051-7039

21

9720

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<19>

NB_CFG<20>

NB_CFG<16>

NB_CFG<5>

NB_CFG<7>

NB_CFG<9>

20

14

3

14

Preliminary

IO

IN

OUT

IN

OUT

IN

IO

IO IO

IO

IN

IO

DDACK*

SATARBIASN SATARBIASP

SATA_CLKN SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1 ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0 LAN_TXD1

LAN_RXD1 LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0 LAD1

EE_DOUT EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY DDREQ

DD0 DD1

DD3

DD2

DD5

DD4

DD6 DD7 DD8

DD11

DD9

DD10

DD12 DD13 DD14 DD15

DA0 DA1 DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT

IN

OUT

IN IN

IN

OUT

IN

OUT

IN IN

IN

OUT

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(WEAK INT PU)

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: DDREQ HAS INTERNAL 11.5K PD

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

INTEL HIGH DEFINITION AUDIO

ACZ_SDOUT

ACZ_SYNC

ACZ_BIT_CLK

ACZ_RST#

ACZ_SDIN[0-2]

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

AC ’07

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

NONE

INTERNAL 20K PD

INTERNAL 20K PD ONLY ENABLED IN S3COLD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

NOTE: DD<7> HAS INTERNAL 11.5K PD

(HSTROBE) (STOP)

20K PD

(DSTROBE)

< 2 IN OF R2107 W/O STUB

LAYOUT NOTE: R2108 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2107 TO BE

< 2 IN OF SB

BOM CONSOLIDATION

NOTE: RISING-EDGE TRIGGERED AT CPU

NOTE: KEYBOARD CONTROLLER RESET CPU

POR IS SMC WILL PUT LAN INT’F

NOTE:

INTO RESET STATE TO SAVE PWR.

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTEL CONFIRMS OK TO LEAVE PINS AS NC

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

NOTE: PULLED UP PER INTEL

NOTE: R2110=56 IN CV. CHANGED TO 54.9 FOR BOM CONSOLIDATION

NOTE: R2108=56 IN CV.

(WEAK INT PD)

(INT PU)

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

NOSTUFF

1/16W

MF-LF

0

5%

402

R2100

1 2

NOSTUFF

402

2.2K

5% 1/16W MF-LF

R2101

1 2

MF-LF

5%

39

402

1/16W

R2195

1 2

39

R2198

1 2

39

R2197

1 2

39

R2196

1 2

402

10K

5% 1/16W MF-LF

R2199

1

2

BGA

SB

ICH7-M

OMIT

U2100

AE22 AH28

U1

R5 T2 T3 T1

T4

R6

AG27

AH17 AE17 AF17

AE16 AD16

AB15 AE14

AB13 AC14 AF14 AH13 AH14 AC15

AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12

AF16

AE15

AF15 AH15

W1

W3

Y2

Y1

AG26

AG24

AH16

AG22

AF22

AG21

AF25

Y5 W4

AG16

AA6 AB5 AC4 Y6

V3

U3

U5 V4 T5

U7 V6 V7

AC3 AA5

AB3

AH24

AG23

AA3

AB1 AB2

AF3 AE3 AG2 AH2

AF7 AE7 AG6 AH6

AF1 AE1

AF18

AH10 AG10

AF23

AH22

AF26

AF24 AH25

402

10K

5% 1/16W MF-LF

R2194

1

2

332K

402

1%

1/16W

MF-LF

R2105

1

2

24.9

MF-LF 1/16W

1%

402

R2107

1 2

402

MF-LF 1/16W

1%

54.9

R2108

1

2

MF-LF 1/16W

402

54.9

1%

R2110

1 2

21

21 97

051-7039

SYNC_MASTER=M50_DOUG SYNC_DATE=06/29/2006

SB: 1 OF 4

TP_SB_XOR_V7

TP_SB_XOR_V6

TP_SB_XOR_U7

TP_SB_XOR_Y2

TP_SB_XOR_Y1

TP_SB_XOR_W1

SB_INTVRMEN

=PP1V05_S0_SB_CPU_IO

CPU_FERR_L

SB_A20GATE

CPU_RCIN_L

SATA_C_D2R_P

IDE_PDDACK_L

SATA_RBIAS_N SATA_RBIAS_P

SB_CLK100M_SATA_N SB_CLK100M_SATA_P

SATA_C_R2D_C_P

SATA_C_R2D_C_N

SATA_C_D2R_N

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_A_D2R_P

SATA_A_D2R_N

TP_SB_SATALED_L

SB_ACZ_SDATAOUT

TP_SB_ACZ_SDIN1 TP_SB_ACZ_SDIN2

ACZ_SDATAIN<0>

SB_ACZ_SYNC

SB_ACZ_BITCLK

SB_SM_INTRUDER_L

SB_RTC_X1

CPU_THERMTRIP_R

CPU_STPCLK_L

CPU_NMI

CPU_SMI_L

CPU_INTR

CPU_INIT_L

FWH_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L

CPU_DPSLP_L

CPU_A20M_L

TP_CPU_CPUSLP_L

SB_ACZ_RST_L

IDE_PDIOR_L

IDE_IRQ14

IDE_PDIOW_L

IDE_PDIORDY IDE_PDDREQ

IDE_PDD<0> IDE_PDD<1>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<7> IDE_PDD<8>

IDE_PDD<11>

IDE_PDD<9> IDE_PDD<10>

IDE_PDD<12> IDE_PDD<13> IDE_PDD<14> IDE_PDD<15>

IDE_PDA<0> IDE_PDA<1> IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

ACZ_SYNC

SMC_RCIN_L

=PP1V05_S0_SB_CPU_IO

PM_THRMTRIP_L

ACZ_SDATAOUT

IDE_PDD<6>

=PP3V3_S0_SB_GPIO

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>

TP_SB_DRQ0_L TP_SB_GPIO23

LPC_FRAME_L

SB_RTC_X2

SB_RTC_RST_L

ACZ_BITCLK

ACZ_RST_L

PP3V3_S5_SB_RTC

TP_SB_XOR_U3

TP_SB_XOR_U5 TP_SB_XOR_V4 TP_SB_XOR_T5

TP_SB_XOR_W3

TP_SB_XOR_V3

IDE_PDD<2> IDE_PDD<3>

25

25 27

27

67

24

60

75

24

59

23

60

26

21

34

59

7

38

21

14

21

58

25

3

7

38

5

38

59

68

26

7

5

7

5

7

5

38

5

38

5

38

68 58

3

7

68

38

3

5

26

68

24

38

Preliminary