Apple iPhone 7 Schematic

PP6907_RF

PP6912_RF

C1710

C7130_RF

C6513_RF

R7110_RF

C6419_RF

FD0406

PP6900_RF

PP6903_RF

R5910_RF

R5501_RF

C5901_RF

C1719C1704C1705C1707

C1744

C1706

R1304

C1727

C1742

C1714

C1726

C7105_RF

R7108_RF

C7110_RF

C6420_RF

C6801_RF

C6806_RF

C6807_RF

C6802_RF

C6805_RF

C6803_RF

FD0400

PP7618_RF

PP1409

PP2002

PP5303

C5501_RF

C5502_RF

C7523_RF

C6501_RF

C7113_RF

SWDS M_RF

R6201_RF

C7132_RF

R7132_RF

C6021_RF

C1466

C1909

C5904_RF

R5511_RF

R5505_RF

R5503_RF

R5908_RF

PP6978_RF

C7501_RF

R7130_RF

C6506_RF

R7113_RF

C6324_RF

C6349_RF

C6348_RF

C6204_RF

R6007_RF

PP7614_RF

PP7615_RF

PP7616_RF

PP7612_RF

PP7613_RF

PP7609_RF

PP7619_RF

C0813

C0814

C0811

C0812

C2618

C7606_RF

C7602_RF

C7607_RF

C7603_RF

C1827

C1833

C1813

C1814

C1866

C1865

C1828

C1820

C1821

C1834

C1839

C1842

C1844C1807

C1838

C1843

C1832

C1826

C1845

C1825

C1831

C1819

C1837

C1818

C1801

C1803

C1501

C1840

C1864

C1436

C1829

C1822

C1835

C1841

C1836

C1802

C1874

C1830

C1823

C1816

PP6904_RF

C5905_RF

U3603

R5909_RF

R3605

C1850C1846

C5801_RF

C5636_RF

C5635_RF

PP6908_RF

C5607_RF

C5738_RF

C5609_RF

C5613_RF

C5602_RF

C5603_RF

Y5501_RF

R5907_RF

EPROM_RF

R5504_RF

C5601_RF

C6900_RF

C5610_RF

R5502_RF

R1118

R1707

C1734
C1731C1717

R1703

C1753

C1736

C1751

C7524_RF

C7103_RF

SE2_RF

C6336_RF

C6337_RF

C7201_RF

C6503_RF

C6514_RF

LBDS M_RF

C6505_RF

C6502_RF

C6515_RF

MHBDS M_RF

R6503_RF

C6512_RF

C6509_RF

C6504_RF

L7122_RF

RXFIL_RF

L6328_RF

C6344_RF

C6334_RF

C6350_RF

L6323_RF

C6345_RF

C6205_RF

L6322_RF

GFIL T_RF

L6201_RF

C6203_RF

R6008_RF

C6022_RF

C6024_RF
C6118_RF

L6111_RF

C6117_RF

C6105_RF

C6001_RF

C6414_RF

SWLATCP_RF

C3605

R5601_RF

C7104_RF

C7528_RF

C7114_RF

C7108_RF

C6002_RF

C7106_RF

C7013_RF

PP7611_RF

C1605

C5612_RF

C1511

R0413

C1506

C1414

R1506

R1504

R2010

R0801

C2011

R0806

C1514 C1612

C1859

C1510

C1848

R1502

C1849 C1847

R2700

C1507

R2000

R3601

C3601

R3604

R5206

RFBUF_ RF

C5615_RF

C5625_RFC5703_RF

C5611_RF

C1724

C6110_RF

C6112_RF

C6507_RF

R6501_RF

C7117_RF

R7002_RF

L6321_RF

L7123_RF

C6004_RF

C6012_RF

C6020_RF

R7109_RF

C6409_RF

C7006_RF

C7601_RF

L7600_RF

C1508

C1013

C1518

C1444

R0800

C0804

R5906_RF

C5631_RF

BBPMU_RF

C5629_RF

C1723

C1743

R7107_RF

R7112_RF

C7129_RF

C6109_RF

C6111_RF

C6510_RF

C6508_RF

R6502_RF

C6014_RF

XCVR0_RF

C7011_RF

C7007_RF

C7600_RF

C0803

C3602

C5608_RF

C7127_RF

R7111_RF

L6325_RF

C6338_RF

R7131_RF

C6318_RF

C6013_RF

R6005_RF

C7009_RF

C7014_RF

C1610

R0807

R0803

C5628_RF

C7126_RF

R6002_RF

L6324_RF

C6302_RF

C6346_RF

C1527

C1420

C2006

U3602

C5702_RF

C1725

C7133_RF

C7128_RF

L6310_RF

C6019_RF

C6011_RF

R6006_RF

C6407_RF

C7008_RF

C0906

C1002

C1001

C1440

C1857

R0804

C5630_RF

C5804_RF

C6007_RF

C6015_RF

C6005_RF

C6335_RF

C6325_RF

C6511_RF

C6320_RF

C6108_RF

C6107_RF

C6114_RF

C6804_RF

C6401_RF

C7001_RF

R0906

C1851

PP6930_RF

R6921_RF
R6922_RF

R5807_RF

C5604_RF

C5626_RF

R1702

C7530_RF

SE2LDO_RF

C7529_RF

C6003_RF

L6311_RF

L6109_RF

LATCP_RF

FL6402_RF

C1010

C1454

C1439

C1862

C0802

C2013

C3606

R3602

R3603

C5623_RF

PP6925_RF

C0807

R1101

DZ6901_RF

C1746

R7114_RF
R7511_RF

C7531_RF

C6023_RF

C7131_RF

C6016_RF

C6008_RF

C6323_RF

C6311_RF

C6319_RF

C6343_RF

C6106_RF

L6110_RF

C7012_RF
C7010_RF

C4709

TP0412

FD0410

PP7620_RF

SH0400

C1011

C7604_RF

C1870

XW1806

C1876

C3604

C5621_RF

C0808

R0802

C7101_RF

XCVR1_RF

R6301_RF

R7103_RF

C6410_RF

C4710

TP0410

C1004

C1457

C1425

L1802

C6017_RF

C6102_RF

C7122_RF

R7105_RF

L6301_RF

C6010_RF

L6102_RF

C6402_RF

GSMPA_RF

R3807

C0907

C1452

C1863

R2011

R5912_RF

C5902_RF

PP6924_RF

C5622_RF

C0809

C1750

C6351_RF

R6003_RF

C7119_RF

C6310_RF

C6317_RF

C6018_RF

C6115_RF

C7118_RF

R6402_RF

R3808

TP0408

PP7621_RF

R0907

C1922

U1801

C5734_RF

C5745_RF

C5735_RF

C5709_RF

C5718_RF

C5701_RF

R5801_RF

C0810

C1715

C6328_RF

L6312_RF

C7123_RF

R7106_RF

R7104_RF

C6309_RF

L6308_RF

C6342_RF

L6306_RF

L6304_RF

C6315_RF

C6113_RF

C6405_RF

R3801

FL3807

FL3811

C6400_RF

C3812

TP0409

C1006

L7502_RF

C1409

C1429

C1904

PP6909_RF

R4714

U1701

C6006_RF

L6320_RF

C6116_RF

R6400_RF

C7124_RF

R3809

WLAN_RF

PP7623_RF

R1001

R1601

FL0700

C0704

C5733_RF

C5731_RF

C5704_RF

C5737_RF

C5740_RF

R4713

C1735

C7016_RF

R7102_RF

R6004_RF

C6329_RF

GSMRX_RF

C6403_RF

R6401_RF

FL6401_RF

R3811

C7521_RF

C1604

C1918

C1932

C1854

C0703

C5605_RF

PP6911_RF

U3601

C3603

C1756

C7015_RF

C7112_RF

C7121_RF

C6009_RF

L6103_RF

C6103_RF

L6318_RF

C6340_RF

C6352_RF

L6313_RF

C7125_RF

L6307_RF

C6316_RF

L6309_RF
C6301_RF

C6314_RF

C6305_RF

C6306_RF

L6305_RF

R6001_RF

R2003

C2009

C6404_RF

C7120_RF

C6411_RF

C6101_RF

C7017_RF

C7005_RF

L6104_RF

R6404_RF

C3824

C1611

C7511_RF

C1459

C1432

C1426

C1902

R0701

C5744_RF

C5753_RF

C5732_RF

C5723_RF

C5627_RF

C1728

C1738

C6307_RF

C6415_RF

C1935

C0806

C1607

C1933

C5713_RF
R5803_RF

C5725_RF

C6332_RF

C6333_RF

C6308_RF

FL7001_RF

C6104_RF

C6406_RF

C6408_RF

NFBS T_RF

R0509

C1421

C1609C1613

C1401

C1858

Y0700

C5717_RF

C5729_RF

C5706_RF

C1709

L6319_RF

C6341_RF

SH0402

C7111_RF

L6101_RF

C7004_RF

C6416_RF

R6405_RF

C6417_RF

C3823

C1434

PP6926_RF

C5754_RF

C5722_RF
C5727_RF

R7101_RF

UATCP_RF

R5806_RF

C5715_RF

R3607

C3607

R4702

R4701

C6418_RF

C3929

PP7622_RF

C7522_RF

C1437

C1402

C1416

C1927

C1603

R0702

C0702

C5741_RF
C5750_RF

C5707_RF

R3611

C3204

C3203

C3211

C3224

PP2401

PP2402

C6704_RF

SUAT1_RF

C8008_RF

C6716_RF

L8008_RF

C6700_RF

L6707_RF

C6720_RF

R6706_RF

C6714_RF

C6721_RF

USPDT2_RF

FL6700_RF

SGND_RF

FL4407

FL4402

FL4401

R4402

C4418

C4401

R4406

C4420

R4405

C4731

C4405

C4404

C4403

C4406

C4419

C4408

DZ4402

DZ4401

DZ4404

DZ4403

FL4403

C0409

PP5302

C4402

C4409

C2611

C2612

C2613

MCEW_ RF

J4504

C4415

C4732

C4414

C4410

C4407

C4413

C4422

XW4501

FL4405

FD0404

C2610

C2614

C0411

FL4732

C4417

C4421

BS0402

FL4731

FL4406
C0410

R4401

FL4404

C4411

C4412

C0408

C4416

R6605_RF

C6610_RF

UPPDI_RF

C6611_RF

C6602_RF

C6601_RF

FD0405

C2609

C0407

R6601_RF

C0412

R2001

C2007

M2600

C6713_RF

R6715_RF

L6700_RF

R6705_RF

PPLXR_RF

C6728_RF

R6710_RF

C6622_RF

C6627_RF

C6726_RF

MLBLN_RF

R6708_RF

C6613_RF

R6606_RF

C6614_RF

FL6602_RF

C6625_RF

C6629_RF

C6620_RF

C6617_RF

LBLN_RF

C6619_RF

BS0403

C6729_RF

C6734_RF

C6732_RF

C6731_RF

C6733_RF

C6730_RF

R6711_RF

JUAT1_RF

C2422

C2414

R2403

R6709_RF

C6727_RF

C2423

R2422

C2413

FL6603_RF

GLNA_RF

C2405

C2421

C6201_RF

C6711_RF

R6703_RF

MHBL N_RF

U2403

L6200_RF

W5BPF_RF
C7711_RF

R7711_RF

C7729_RF

C6735_RF

C2408

R7702_RF

C7709_RF

FL2504

C2523

C2526

C2524

C2525

C2512

C2513

C2522

C2528

C2529

J4501

C2514

FL2501

R2008

C7525_RF

PP5301

L7709 _RF

C7731_RF

L6710_RF

C2420

JUAT2_RF

C771 0_ RF

R1306

C4108

C4127 C4133

FL4105

C4729

C4102

C6701_RF

C6702_RF

TUNFX_RF

FL6701_RF

C0413

TP0414

R2904

C3308

C3501

C3316

TP0421

TP0403 TP0402

C4118

C4131

FL4119

C4110

C4121

C4122

C4120

FL4108

C4119

FL4117

C4129

FL4118

C4130

C4116

R4102

C4101

C3529

C3542

C4136

C4135

C4103

C3434

XW2201

FL6702_RF

FL6703_RF

R2905

C6705_RF

FL2914

R4705

R4707

FL2904

FL2909

TP0423

TP7505_RF

FL2910

FL2903

C2927

R4706

C2909

FL2505

R4708

C3333

C3312

C3323

R3333

C3306

C3325

C3318

C3319

C3315

XW1401

XW1803

FL4815

R2915

C3331

U3301

XW1802

C6703_RF

XW3203

FL2911

R4815

C4803

C3332

R3332

R4604

XW1801

U0700

C4708

R4603

DZ2907

C2924

PP7603_RF

SH0401

R3301

XW2001

C2905

C2908

DZ2905

C2934

C2931

PP7604_RF

C3329

R7512_RF

C3313

XW1807

BB_RF

XW3202

PP6921_RF

PP6933_RF

PP6920_RF

PP6941_RF

PP6918_RF

PP6917_RF

PP6919_RF

PP6969_RF

PP6979_RF

PP6953_RF

PP6973_RF

PP6972_RF

PP6943_RF

C4105

C4109

TP0405TP0404

FL4115

FL4101

R4110

FL4112

R4104

C2117

C2118

C2204

C2202

TP0416

ZT0404

TP0407

R4710

C4106

TP0406

FL4102

R4709

C4111

C2620

C2619

R4109

M2800

no_refdes+3

TP0415

R2201

C2201

C1905

no_refdes+8

C2917

C2521

C2520

C2508

C2506

C2503

C2530

C2510

C1923

C1930

C3311

C1615

C3324

R7520_RF

NFCSW_ RF

C1512

PP7501_RF

R1305

R0901

SWPMX_RF

XW1402

C0909

C0905

C0908

C0904

C1910

L2301

C1911

C1907

C1901

C1914

C3531

PP6931_RF

C3532

R6900_RF

PP3602

PP3601

PP2003

XW2700

C4107

XW2707

C4104

C4132 C4128

C4117

J4101

FL4120

FL4116

C4730

C4134

C4126

J2201

XW2404

C2203

C2445

PP2440

R2404

C2449

R2441

C2448

C2442

U2404

C2443

R3901

R4711

FL3915

JLAT3_RF

C3927

JLAT1_RF

C4507

PP4501

TP0411

CL0401

C3916

no_refdes+7

FD0403

TP0420TP0422

BS0405

C3934

FL3922

R4712
FL3910
C3932

C3913

C3910

C3909

C3914

C3911

C3912

C3924

C3918

C3805

FL4741

C4741

C4742

FL4742
C4711

C4712

R4501

C3915

C3926

FL3919

R3908

C3923

C3928

FL3924

C3925

J4502

C3919

FL3916

C3930

C3936

L3903L3902 L3901

C3935

C3931

XW3801

U3801

D10
PCB: 820-00188-08

R2903

FL2913

FL2908

C2906

C3327

XW2004

PP6971_RF

PP6945_RF

PP7000_RF

PP6940_RF

PP6944_RF

UATDI_RF

FL3801

C3802

C3826

R4807

C4810

C4809

R4806

C3801

C3819

C3817

C3816

C3825

C3818

C3811

C4804

C2921

C2915

R4812

C2916

XW2002

PP6942_RF

LATD I_RF

C4707

J4503

C2903

C3326

C5730_RF

C2926

C1808

C1804

L1804

PP6916_RF

C5616_RF

PP7600_RF

PP7601_RF

PP6935_RF

PP6939_RF

SH0403

MLBPA_R F

J3801

C2933

FL2902

XW2003

C0816

C0817

PP6915_RF

L5601_RF

L5603_RF

PP6938_RF

PP1701

R4811

R4813

L7500_RF

C0818

C0815
PP6970_RF

C5903_RF

PP0801

PP0802

C5632_RF

PP1702

FL2907

C2910

C1869

C5614_RF

no_refdes+2

C2902

C2911

R4810

FL2901

R2002

C2008

FD0407

C7509_RF

C7507_RF

L7501_RF

C1810

C7508_RF

C1806

C1811

PP6923_RF

C0805

C0801

R5911_RF

PP6906_RF

C5624_RF

C5620_RF

L5602_RF

XW5616_RF

C3813

C3815

C3821

FL3803

C3804

C3822

FL3802

C3803

FL3804

C3807

C3806

C3902

FL3904

R4808

R3923

FL2906

DZ2906

C2935

C2932

C3328

XW2005

J_SIM_RF

PP6977_RF

PP6974_RF

C3922

FL3806

R3805

C3828

C4812

C4813

PP7608_RF

R4809

L3302

XW1403

XW1901
XW1902

XW1805

PP6905_RF

PP6952_RF

PP6936_RF

C3814

R3802

TP0413

C2904

C2901

C2914

no_refdes+10

TP7500_RF

C7515_RF

R7508_RF

BALUN_RF

C7516_RF

R7509_RF

C7510_RF

L1801

L1816

U5801_RF

C7518_RF

C7512_RF

C7514_RF

L1810

L1811

L1812

L1813

PP1410PP0902

C1872C1873

PP1411

L1809

L1808

L1807

L1806

L1803

C1867

C1871

L1814

C1861

L1815

L1818

PP6929_RF

C1860

L1817

PP7502_RF

L5604_RF

C5617_RF

C5633_RF

PP6914_RF

XW5614_RF

C5634_RF

C5618_RF

XW5615_RF

L5605_RF

no_refdes+5

no_refdes+5

PP6980_RF

LBPA_RF

TDDPA_RF

MBHBPA_RF

QPOET_RF

no_refdes+4

TP0400 TP0401

TP0419

FD04 08

BS0406

TP0424

no_refdes+1

PP3801

L800 9_RF

no_refdes+6

PP8000_RF

SUAT2_RF

C7730_RF

FD0409

FD0402

ZT0401

PP7606_RF

PP7607_RF

PP7605_RF

C7700_RF

R7700_RF

L7700_RF

C7702_RF

R7703_RF

C7705_RF

C7708_RF

C7707_RF

R7704_RF

PP7610_RF

PP7624_RF P P6981_RF

PP7506_RF

PP7507_RF

R3304

PP7508_RF

PP7505_RF

C1875

C0901

C0903 C0902

C7520_RF

C7517_RF

R0900

R0505

C1465

C1408

R1602

C1913

C1852

C1877

C1908

C0705

XW1804
C1601

C0910

PP2001

C5712_RF

C5721_RF
C5743_RF
C5728_RF

C5716_RF

C5705_RF

C3225

R4002

L2700

C3720

FL3918

FL3908

R3915

FL3909

C3940

C3725

NFC_RF

C1005

C7527_RF

C1448

C1456

C7503_RF

R7599_RF

PP7504_RF

C7526_RF

C7506_RF

C1410

C1413

PP1402PP1401

C1415

PP7509_RF

C1502

C1428

C1460

C1461

C1417

C1418

C1419

C1427

C1433

C1606

PP0701

Y2001

C2307

R2004

C2010

C2002

C1504

C4143

C0701

C1916

C1926

L1805

C5710_RF

C5719_RF

C3201

C3222

C3223

R0805

R1704

C1711

Q4001

C3710

C3403

C3432

C3404

C3526

C3539

C3524

C3538

C3407

U2700

C2703

C2701

R2705

Q2101

C3525

R2702

C3706

C3721

C3704

C3705

C3709C3708

L3704

C3921

FL3912

C3933

FL3902

C1411

C1424

C1431

C1430

C2004

C1412

PP1403

C1404

C1422

C2003

PP1408

C1503

C1442

C1438

C1523

C0800

R2012

FL1501

C1528

C1403

C0700

R2007

C1925

R1114

C1853

C1458

C2302

C2308

R0700

R1303

R1901

C2001

C1921

R2009

R2005

C5736_RF

C1809

C2303

C5755_RF

C2304

C2306

C3212

C1868

C5724_RF

C1805

C1912

C5708_RF

C5714_RF

R5802_RF

C3202

C3113

C2108

FL3901

C5749_RF

C5711_RF

C5742_RF

C5726_RF

C3209

C3208

C5720_RF

U3101

C3112

R3104

R3103

R1103

C3220

C3214

C3213

R3201

C3107

C3205

C3106

PP5304

R2710

C1732

C2710

C1712

C1747C1745

C4007

L4022

L4021

U4001

C4001

R4001

C3427

C4004

C3428

C4003

C2708

FL4106

C3429

U3402

C3430

C3535

C3537C3431

U3502

C3405

R2711

C3536

U2710

C2114

C2700

D2700

C3528

C2103C2112

C2702

C2101

U2101

R2102

C2102

C2110

R2104

C2106

PP4001

C4807

R2701

U4805

U2701

C5906_RF

C2706

R2706

R4803

R2704

R4804

U4802

R2703

R3701

R4805

U4806

FL3906

U3701

D3701D3702

C3424

C2113

C3703

C3719

C4601

U3702

L3703

C3702 C3724

C3711

FL3911

U3703

C3718

FL3920

C4701

C4702

C3920

C3714

FL3917
FL3913

C3901

C3917

C3904

C3903

C3905

C3939

FL3903

C7704_RF

C1407

C1101

U1101

C2111

R2101

C5907_RF

C3716

W25DI_RF

C7706_RF

C7703_RF

R7701_RF

PP7617_RF

R7600_RF

C1405

C1435

R4715

C2309

C1915

R3202

R6904_RF R1701

C1754

C1713

C1702

C1703C1708

C1730

C1729

C1722

C1720

C1733

C1752

C1718

C1749

Q2700

R3508

C5908_RF

C3530

C3722

C3715

C3717

R2006

PP7503_RF

C1423

C1406

C1529

C1602

C1513

R4716

U2301

C5739_RF

C5746_RF

C1721

C1701

C1737

C1739

C1740

C2109

C2105

C2115

R2103

C5909_RF

GPIO_RF

C3707

L7701_RF

PP7500_RF

R7510_RF

C7505_RF

C1509

R7502_RF

C7504_RF

C1515

R0504

R0508

R2020

R1505

R0501

R0503

C1522

R1113

R1210

R4703

C4703

C2301

C5748_RF

R1116

C3221

DZ6903_RF

DZ6905_RF

DZ6902_RF

DZ6904_RF

C1716

C1748

Q2701

C4608

C3422

C4002

C3527

C2104

R2105

Q2102

C3938

C3713 C3712

W2BPF_RF

C1519

C1449

C0900

C1614

C1608

R1501

R4704

C4704

R2301

C3217

C5752_RF
C3215

C5747_RF

C6901_RF

R3101

C4008

C2707 C3534

C4005

C4006

C3426

C2617

C3727 C3726

C0416

C2527

C0414

C0415

C7701_RF

L7702_RF

L7703_RF

C7502_RF

R1503

R7506_RF

C7500_RF

R4801

R4802

R2015

C1855

C1856

C1919

C2704

PP6913_RF

C5751_RF

C1741

MCNS_ RF

DZ6900_RF

C2705

FL4121

FL4107

FL4604

FL4729

FL4730

C3937

FL4103

FL4114

C3425

C2531

FL2502

C2507

U2501

FL2503

R4817

C2501

C2505

FL2500

C2519

C2504

FL2506

R4816

C2509

C4817

C4816

C2518

C2511

C2515

C2502

TP8000_RF

no_refdes+9

USPDT_RF

L8007_RF

C8005_RF

C8007_RF

U2402

PP2404

XW3333

C2401

PP2403

C2418

C0406

C0402

C0404

C0401

C0405
C0403

C0420

C0418

C0417

C0419

C0421

C0422

VIETMOBILE.VN

34567 8

2 1

D

C

B

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D10 MLB - DVT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

<CSA>

<CSA_PAGE1>

<CSA_PAGE2>

<CSA_PAGE3>

<CSA_PAGE4>

<CSA_PAGE5>

<CSA_PAGE6>

<CSA_PAGE7>

<CSA_PAGE8>

<CSA_PAGE9>

<CSA_PAGE10>

<CSA_PAGE11>

<CSA_PAGE12>

<CSA_PAGE13>

<CSA_PAGE14>

<CSA_PAGE15>

<CSA_PAGE16>

<CSA_PAGE17>

<CSA_PAGE18>

<CSA_PAGE19>

<CSA_PAGE20>

<CSA_PAGE21>

<CSA_PAGE22>

<CSA_PAGE23>

<CSA_PAGE24>

<CSA_PAGE25>

<CSA_PAGE26>

<CSA_PAGE27>

<CSA_PAGE28>

<CSA_PAGE29>

<CSA_PAGE30>

<CSA_PAGE31>

<CSA_PAGE32>

<CSA_PAGE33>

<CSA_PAGE34>

<CSA_PAGE35>

<CSA_PAGE36>

<CSA_PAGE37>

<CSA_PAGE38>

<CSA_PAGE39>

<CSA_PAGE40>

<CSA_PAGE41>

<CSA_PAGE42>

<CSA_PAGE43>

<CSA_PAGE44>

<CSA_PAGE45>

CONTENTSPAGE

TABLE OF CONTENTS

MLB SPECIFIC: BOM TABLE

SYSTEM:MECHANICAL, TESTPOINTS
SYSTEM:BOARDID

spare

SOC:JTAG,USB,XTAL

SOC:PCIE

SOC:MIPI AND ISP

SOC:LPDP

SOC:SERIAL

SOC:GPIO & UART

SOC:AOP

SOC:POWER (1/3)

SOC:POWER (2/3)

SOC:POWER (3/3)

NAND

SYSTEM POWER:PMU (1/3)

SYSTEM POWER:PMU (2/3)

SYSTEM POWER:PMU (3/3)

SYSTEM POWER:CHARGER

SYSTEM POWER:BATTERY CONN

SYSTEM POWER:BOOST

SENSORS

B2B FILTERS: UTAH

CAMERA:STROBE DRIVER

Accessory: Buck Circuit

TRINITY: FF SPECIFIC

B2B:FOREHEAD

spare

AUDIO:CALTRA CODEC (1/2)

AUDIO:CALTRA CODEC (2/2)

AUDIO:SPEAKER AMP 2

AUDIO:SPEAKER AMP 1

ARC:DRIVER

ARC:MAGGIE

DISPLAY & MESA:POWER

B2B:ORB & MESA

B2B FILTERS: DISPLAY & TOUCH

TRISTAR 2

B2B:DOCK FLEX

spare <SYNC_MASTER42>

spare

B2B: SMALL FF SPECIFIC

SYNC

<SYNC_MASTER1>

<SYNC_MASTER2>SYSTEM:BOM TABLES

<SYNC_MASTER3>

<SYNC_MASTER4>

<SYNC_MASTER6>

<SYNC_MASTER7>

<SYNC_MASTER8>

<SYNC_MASTER9>

<SYNC_MASTER10>

<SYNC_MASTER11>

<SYNC_MASTER12>

<SYNC_MASTER13>

<SYNC_MASTER14>

<SYNC_MASTER15>

<SYNC_MASTER16>

<SYNC_MASTER17>

<SYNC_MASTER18>

<SYNC_MASTER19>

<SYNC_MASTER20>

<SYNC_MASTER21>

<SYNC_MASTER22>

<SYNC_MASTER23>

<SYNC_MASTER24>

<SYNC_MASTER25>

<SYNC_MASTER26>

<SYNC_MASTER27>

<SYNC_MASTER28>

<SYNC_MASTER29>

<SYNC_MASTER30>

<SYNC_MASTER31>

<SYNC_MASTER32>

<SYNC_MASTER33>

<SYNC_MASTER34>

<SYNC_MASTER35>

<SYNC_MASTER36>

<SYNC_MASTER37>

<SYNC_MASTER38>

<SYNC_MASTER39>

<SYNC_MASTER40>

<SYNC_MASTER41>

<SYNC_MASTER43>

<SYNC_MASTER44>B2B FILTERS: RIGHT BUTTON FLEX

<SYNC_MASTER45>

LAST_MODIFICATION=Tue Jun 14 15:20:28 2016

<SYNC_DATE1>

<SYNC_DATE2>

<SYNC_DATE3>

<SYNC_DATE4>

<SYNC_DATE5>

<SYNC_DATE6>

<SYNC_DATE7>

<SYNC_DATE8>

<SYNC_DATE9>

<SYNC_DATE10>

<SYNC_DATE11>

<SYNC_DATE12>

<SYNC_DATE13>

<SYNC_DATE14>

<SYNC_DATE15>

<SYNC_DATE16>

<SYNC_DATE17>

<SYNC_DATE18>

<SYNC_DATE19>

<SYNC_DATE20>

<SYNC_DATE21>

<SYNC_DATE22>

<SYNC_DATE23>

<SYNC_DATE24>

<SYNC_DATE25>

<SYNC_DATE26>

<SYNC_DATE27>

<SYNC_DATE28>

<SYNC_DATE29>

<SYNC_DATE30>

<SYNC_DATE31>

<SYNC_DATE32>

<SYNC_DATE33>

<SYNC_DATE34>

<SYNC_DATE35>

<SYNC_DATE36>

<SYNC_DATE37>

<SYNC_DATE38>

<SYNC_DATE39>

<SYNC_DATE40>

<SYNC_DATE41>

<SYNC_DATE42>

<SYNC_DATE43>

<SYNC_DATE44>

<SYNC_DATE45>

<CSA>

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75 DIVERSITY RECEIVE LNA'S

76

77

78

79

80

81 ICEFALL, SIM, DEBUG_CONN

<CSA_PAGE46>

<CSA_PAGE47>

<CSA_PAGE48>

<CSA_PAGE49>

<CSA_PAGE50>

<CSA_PAGE51>

<CSA_PAGE52>

<CSA_PAGE53>

<CSA_PAGE54>

<CSA_PAGE55>

<CSA_PAGE56>

<CSA_PAGE57>

<CSA_PAGE58>

<CSA_PAGE59>

<CSA_PAGE60>

<CSA_PAGE61>

<CSA_PAGE62>

<CSA_PAGE63>

<CSA_PAGE64>

<CSA_PAGE65>

<CSA_PAGE66>

<CSA_PAGE67>

<CSA_PAGE68>

<CSA_PAGE69>

<CSA_PAGE70>

<CSA_PAGE71>

<CSA_PAGE72>

<CSA_PAGE73>

<CSA_PAGE74>

<CSA_PAGE75>

<CSA_PAGE76>

<CSA_PAGE77>

<CSA_PAGE78>

<CSA_PAGE79>

<CSA_PAGE80>

<CSA_PAGE81>

<CSA_PAGE82>

<CSA_PAGE83>

<CSA_PAGE84>

<CSA_PAGE85>

<CSA_PAGE86>

<CSA_PAGE87>

<CSA_PAGE88>

<CSA_PAGE89>

<CSA_PAGE90>

CONTENTSPAGEDATE

SMALL FORM FACTOR SPECIFIC

I2C MAP: AP, TOUCH, HOMER, I2C5

I2C MAP AOP

I2C TABLE

spare

spare

MLB UNIQUE

CELL,WIFI,NFC

WIFI_MLB SCHEMATIC

PERENNIAL

WIFI FRONT-END [77]

page1

NFC

page1 [1]

UAT MATCH AND TUNER CONNECTOR [2]

BOM LIST

page1

BOM_OMIT_TABLE

PMU: CONTROL AND CLOCKS

PMU: SWITCHERS AND LDOS

BASEBAND: POWER2

BASEBAND: CONTROL

BASEBAND GPIOS

TRANSCEIVER0/1: POWER

TRANSCEIVER0/1: TX PORTS

TRANSCEIVER0/1: PRX PORTS

RECEIVE MATCHING

LOWER ANTENNA & COUPLERS

DIVERSITY RECEIVE ASM'S

UPPER ANTENNA FEEDS

PMU: ET MODULATOR

TEST POINTS & BOOT CONFIG

TDD TRANSMIT

FDD TRANSMIT

<SYNC_MASTER46>

<SYNC_MASTER47>

<SYNC_MASTER48>

<SYNC_MASTER49>

<SYNC_MASTER50><SYNC_MASTER5>

<SYNC_MASTER51>

<SYNC_MASTER52>

<SYNC_MASTER53>

<SYNC_MASTER54>

<SYNC_MASTER55>

<SYNC_MASTER56>

<SYNC_MASTER57>

<SYNC_MASTER58>

<SYNC_MASTER59>

<SYNC_MASTER60>

<SYNC_MASTER61>

<SYNC_MASTER62>

<SYNC_MASTER63>

<SYNC_MASTER64>

<SYNC_MASTER65>

<SYNC_MASTER66>

<SYNC_MASTER67>

<SYNC_MASTER68>

<SYNC_MASTER69>

<SYNC_MASTER70>

<SYNC_MASTER71>

<SYNC_MASTER72>

<SYNC_MASTER73>

<SYNC_MASTER74>

<SYNC_MASTER75>

<SYNC_MASTER76>

<SYNC_MASTER77>

<SYNC_MASTER78>

<SYNC_MASTER79>

<SYNC_MASTER80>

<SYNC_MASTER81>

<SYNC_MASTER82>

<SYNC_MASTER83>

<SYNC_MASTER84>

<SYNC_MASTER85>

<SYNC_MASTER86>

<SYNC_MASTER87>

<SYNC_MASTER88>

<SYNC_MASTER89>

<SYNC_MASTER90>

ECNREV DESCRIPTION OF REVISION

DATESYNC

<SYNC_DATE46>

<SYNC_DATE47>

<SYNC_DATE48>

<SYNC_DATE49>

<SYNC_DATE50>

<SYNC_DATE51>

<SYNC_DATE52>

<SYNC_DATE53>

<SYNC_DATE54>

<SYNC_DATE55>

<SYNC_DATE56>

<SYNC_DATE57>

<SYNC_DATE58>

<SYNC_DATE59>

<SYNC_DATE60>

<SYNC_DATE61>

<SYNC_DATE62>

<SYNC_DATE63>

<SYNC_DATE64>

<SYNC_DATE65>

<SYNC_DATE66>

<SYNC_DATE67>

<SYNC_DATE68>

<SYNC_DATE69>

<SYNC_DATE70>

<SYNC_DATE71>

<SYNC_DATE72>

<SYNC_DATE73>

<SYNC_DATE74>

<SYNC_DATE75>

<SYNC_DATE76>

<SYNC_DATE77>

<SYNC_DATE78>

<SYNC_DATE79>

<SYNC_DATE80>

<SYNC_DATE81>

<SYNC_DATE82>

<SYNC_DATE83>

<SYNC_DATE84>

<SYNC_DATE85>

<SYNC_DATE86>

<SYNC_DATE87>

<SYNC_DATE88>

<SYNC_DATE89>

<SYNC_DATE90>

APPD

DATE

2016-06-1400064008778 ENGINEERING RELEASED

D

C

B

A

TABLE OF CONTENTS

Schematic & PCB Callouts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SCH1 SCH,MLB,D10051-00419

CRITICAL

CRITICALPCB1820-00188 PCBF,MLB,D10

8 7 5 4 2 1

BOM OPTIONCRITICAL

?

?

TABLE_5_HEAD

TABLE_5_ITEM

System Block Diagram:

<rdar://problem/16684269>

SCH 051-00419
BRD 820-00188

MCO 056-01342

36

TABLE OF CONTENTS

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

NAND BOM Options

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NAND,H,32GB,16nm,MLC

1 CRITICALU1701335S00169

335S00182 1 U1701 CRITICAL

335S00156 1 U1701 CRITICAL

138S0867 5

138S00003 CRITICAL

138S00003 CRITICAL

335S00180 T,15nm,TLC,128GBALTERNATE U1701335S00182

#22686038:See Radar

NAND,H,128GB,16nm,TLC

NAND,H,256GB,3Dv3,TLC

CAP,X5R,10UF,20%,6.3V,0.65MM,HRZTL,0402 C1748,C1713,C1716,C1721,C1733

5

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402 C1748,C1713,C1716,C1721,C1733

5

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402

PART NUMBER

C1748,C1713,C1716,C1721,C1733

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

335S00169335S00201 U1701 T,15nm,MLC,32GBALTERNATE

335S00169 ALTERNATE U1701 S,16nm,MLC,32GB335S00209

335S00182335S00195 U1701ALTERNATE SS,1Ynm,TLC,128GB

U1701335S00182 ALTERNATE335S00179 SD,15nm,TLC,128GB

335S00183 U1701 SD,3Dv2,TLC,256GBALTERNATE335S00148

U1701ALTERNATE335S00183 SS,3Dv3,TLC,256GB335S00190

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

NAND_32G

NAND_128G

NAND_256G

NAND_32G

NAND_128G

NAND_256G

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

Active Diode Alternate

PART NUMBER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

DDR PLL Alternate

PART NUMBER

155S00068155S00095

ALTERNATE FL1501

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

FERR BD,100OHM,25%,100MA,2OHM,01005

Power Inductor Alternates

PART NUMBER

152S00118 152S00075

152S00077 ALL152S00397

152S00121 152S00081

152S00366152S00402 ALLALTERNATE

152S1843

ALTERNATE ALL

ALTERNATE

ALTERNATE ALL

ALTERNATE152S1936152S00123 ALL

ALTERNATE152S00297 ALL

ALTERNATE152S00297 ALL152S00365

ALTERNATE152S00398 152S00204 ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

IND,PWR,SHLD,1.2 UH,3.0A,0.080 OHM,2016

IND,PWR,SHLD,1.0 UH,2.25A,0.150 OHM,2016

IND,PWR,SHLD,0.47 UH,3.8A,0.048 OHM,2012

IND,PWR,SHLD,15 UH,0.72A,0.900 OHM,3225

IND,MULT,1UH,1.2A,0.320 OHM,0603

CYNTEC 2012 1UH

CYNTEC 2012 1UH

IND,PWR,0.22UH,20%,6.7a,23MOHM,2012

TABLE_ALT_HEAD

TABLE_ALT_ITEM

ACC BUCK CIRCUIT Alternates

376S00166

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

reverted 11/13

TABLE_ALT_ITEM

TABLE_ALT_ITEM

For Chestnut inductor; so it doesn't interfere with PMU inducotr Buck 7 alts

PART NUMBER

371S00064DIODES INC. ACT DIODEALTERNATE376S00047376S00106 Q2101

ALTERNATE371S00087 D2700

152S00557152S00558 ALTERNATE

376S00164 ALTERNATE

353S01039 ALTERNATE U2710353S01007

L2700

Q2700,Q2701

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

DIODE,SHOTTKY,30V,200MA,0201

TABLE_ALT_ITEM

IND,MLD,0.47UH,2.5A,80Mohm,1608

TABLE_ALT_ITEM

PFET,12V,CSP4

TABLE_ALT_ITEM

IC,LOAD SWITCH,WLCSP4

D

C

Magnesium Alternates

PART NUMBER

338S00203338S00173 U2402

ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

Larger Wafer (-29 flow) Magnesium

TABLE_ALT_HEAD

TABLE_ALT_ITEM

152S00120 152S00077 ALTERNATE

152S00117 152S00074

ALTERNATE

ALL

L1806,L1810,L1814,L1816,L1817

Global R/C Alternates

PART NUMBER

118S0764 ALTERNATE ALL

138S0702 ALTERNATE ALL

138S00006

138S0648

132S0436 132S0400

118S0717

138S0657

ALTERNATE138S0835 ALL

138S00003 ALTERNATE138S00005 ALL

ALTERNATE138S00003138S00048

ALL

138S0652 ALTERNATE ALL

132S0436132S0400 ALTERNATE ALL

138S0986 ALL138S00024

138S0739 ALTERNATE

ALTERNATE

ALL138S0706

ALL138S0945 ALTERNATE138S0739

ALTERNATE

ALL

For Chestnut inductor only

IND,PWR,SHLD,1.0 UH,3.0A,0.060 OHM,2016

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

RES, 3.92K, 0.1%, 0201

CAP, X5R, 4.3UF, 4V, 0610

CAP, 3-TERM, 4.3UF, 4V, 0402

CAP,X5R,15UF,6.3V,0.65MM,0402,TAIYO

CAP,X5R,15UF,6.3V,0.65MM,0402,KYOCERA

CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

CAP,X5R,0.22UF,6.3V,01005,TDK

CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK

CAP,CER,1UF,20%,10V,X5R,0201,MURATA

CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA

CAP,CER,X5R,0.22UF,20%,6.3V,20%

Except BUCK5 LX (BUCK5 LX is Taiyo only)

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

C

B

Carbon Alternates

PART NUMBER

ALTERNATE338S00087 338S00226

UT LDO Alternates

PART NUMBER

ALTERNATE U2501353S00015353S00889

U2401,U2404

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

Updated version of Carbon

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ST, LDO REG, 2.925V, CSP 0.65x0.65

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Global Ferrite Alternates

PART NUMBER

155S0581 ALTERNATE ALL155S00067

155S00012 ALLALTERNATE155S00168

155S0610

152S00489 ALLALTERNATE152S00456

ALTERNATE155S0581 ALL155S00067

ALLALTERNATE155S00194

ALLALTERNATE155S00200 155S0610

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

FERR, 240OHM, 0.38OHM DCR, 0201

FERR, 240OHM, 0.38OHM DCR, 0201

FLTR, 65 OHMS, 0605

FERR BD, 150OHM, TDK

FERR BD, 150OHM, TY

FERR BD, 0.47UH, TY

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

B

A

Mamba LDO Alternates

PART NUMBER

U3801353S00932 353S00576 ALTERNATE

I2C5 Alternate

PART NUMBER

ALTERNATE335S00234 335S00233 U1101

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ST, LDO REG, 2.75V

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

I2C5 ALTERNATE

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Global Varistor Alternates

PART NUMBER

377S0140 ALL377S0168 ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

VARISTOR, 6.8V, 100PF, 01005

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

D

D10 EEEE CALLOUTS

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 EEEE CODE FOR 639-01754 EEEE_GXD5 CRITICAL825-6838

825-6838

1 CRITICALEEEE_H6TFEEEE CODE FOR 639-02372825-6838

1

EEEE CODE FOR 639-02374 EEEE_H6TH825-6838 CRITICAL1

EEEE_GXD7 CRITICAL1 EEEE CODE FOR 639-01756

EEEE_H6TGEEEE CODE FOR 639-02373825-6838

CRITICALEEEE_GXD6825-6838 1 EEEE CODE FOR 639-01755

CRITICAL

BOM OPTIONCRITICAL

EEEE_BEST

EEEE_SUPREME

EEEE_EXTREME

EEEE_BEST_ROW

EEEE_SUPREME_ROW

EEEE_EXTREME_ROW

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

34567 8

2 1

D

C

CAYMAN DDR Alternates

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TABLE_ALT_ITEM

339S00254

339S00255

PART NUMBER

339S00253

ALTERNATE ALL339S00253 DDR-H, 2G, B1

ALTERNATE ALL DDR-S, 2G, B1

Cap 2.2UF Alternates

PART NUMBER

138S00032

ALTERNATE138S00049

(C2507,C2531)

ALLALTERNATE138S00032138S0831

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CAP,CER,X5R,2,2UF,20%6.3V,20%, KYOCERA

CAP,CER,X5R,2,2UF,20%,6.3V,20%,MURATA

D10x Specific BOM Callouts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1152S00117 CRITICALL1803

TAIYO,IND,PWR,SHLD,1UH,3.6A,0.060OHM,2016

117S0156 2 CRITICAL

RES,MF,1K OHM, 5%, 1/32W, 01005

R4808,R4809

TABLE_ALT_HEAD

TABLE_ALT_ITEM

#25634778: Exclude Kyocera as 2.2UF alt at only C2507/C2531 REFDES (other refdes no impact)

TABLE_ALT_ITEM

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

B5LX_TAIYO

TABLE_5_ITEM

UTAH_C

#24681501

#24629229

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

Current as of D10 MCO 056-01342-78

NORTH_SCREW_EXPOSED

O

Contained in radio_mlb pages

1

C0413

100PF

5%
16V

2

NP0-C0G
01005

1

C0414

56PF

5%
25V

2

NP0-C0G-CERM
01005

O

O

ZT0401

2.70R1.80-NSP

1

CHASSIS_GND_BS401

1

C0401

220PF

5%
10V

2

C0G-CERM
01005

CHASSIS_GND_BS402

4

1

C0407

220PF

5%
10V

2

C0G-CERM
01005

1

C0402

220PF

5%
10V

2

C0G-CERM
01005

1

C0408

220PF

5%
10V

2

C0G-CERM
01005

44

1

2

1

2

BS0402

C0403

100PF

5%
16V
NP0-C0G
01005

C0409

100PF

5%
16V
NP0-C0G
01005

STDOFF-2.56OD1.4ID-1.10H-SM

1

CHASSIS_GND_BS402

1

C0404

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0410

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0405

18PF

2%
16V

2

CERM
01005

1

C0411

18PF

2%
16V

2

CERM
01005

4

1

2

1

2

BS0403

C0406

4PF

+/-0.1PF
16V
NP0-C0G
01005

C0412

4PF

+/-0.1PF
16V
NP0-C0G
01005

STDOFF-2.56OD1.4ID.99H-SM

CHASSIS_GND_BS403

1

4

1

C0415

18PF 4PF

2%
16V

2

CERM
01005

1

2

C0416

+/-0.1PF
16V
NP0-C0G
01005

41 40 21

22 21

28 27 26 25 23 21 19 18 10 9
52 46 41 40 39 37 35 34 33 31

53

DFU

TESTPOINTS

POWER

PP5V0_USB

PP_BATT_VCC

PP_VDD_MAIN

TP0419

1

TP-P55

ROOM=TEST

A

TP0420

ROOM=TEST

TP0421

ROOM=TEST

TP0415

ROOM=TEST

TP0422

ROOM=TEST

TP0408

ROOM=TEST

FD0408

0P5SM1P0SQ-NSP

ROOM=TEST

TP0424

ROOM=TEST

1

TP-P55

1

TP-P55

1

TP-P55

1

TP-P55

1

TP-P55

FID

1

1

TP-P55

A

POWER GROUND

A

VBUS

VBATT

A

A

A

A

VDD_MAIN

Note: Fiducial used as test point

FD0400

FID

0P5SQ-SMP3SQ-NSP

1

ROOM=TEST

GND TP

FIDUCIALS

FD0410

FID

0P5SM1P0SQ-NSP

1

FD0409

0P5SM1P0SQ-NSP

1

FD0405

0P5SM1P0SQ-NSP

1

FD0406

0P5SQ-SMP3SQ-NSP

1

FD0404

0P5SQ-SMP3SQ-NSP

1

FD0403

0P5SQ-SMP3SQ-NSP

1

FD0402

0P5SQ-SMP3SQ-NSP

1

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

D

C

CHASSIS_GND_BS403

4

1

C0417

220PF

5%
10V

2

C0G-CERM
01005

1

C0418

220PF

5%
10V

2

C0G-CERM

01005

1

C0419

100PF

5%
16V

2

NP0-C0G
01005

1

C0420

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0421

18PF

2%
16V

2

CERM
01005

1

C0422

4PF

+/-0.1PF
16V

2

NP0-C0G
01005

Back Shields

1

SH0400

SM

SHLD-EMI-UPPER-BK-D10

1

SH0402

SM

Front Shields

1

SH0401

SM

SHLD-EMI-UPPER-FRT-D10

1

SH0403

SM

PMU_TO_AP_FORCE_DFU

20 12

E75

90_TRISTAR_DP1_CONN_P

41 40

90_TRISTAR_DP1_CONN_N

41 40

90_TRISTAR_DP2_CONN_P

41 40

90_TRISTAR_DP2_CONN_N

41 40

PP_TRISTAR_ACC1

41 40

PP_TRISTAR_ACC2

41 40

TP0414

1

TP-P55

ROOM=TEST

TP0402

1

TP-P55

ROOM=TEST

TP0403

1

TP-P55

ROOM=TEST

TP0404

1

TP-P55

ROOM=TEST

TP0405

1

TP-P55

ROOM=TEST

TP0406

1

TP-P55

ROOM=TEST

TP0407

1

TP-P55

ROOM=TEST

A

FORCE DFU

A

A

A

A

A

ACCESSORY ID AND POWER

A

C

FD0407

FID

0P5SM1P0SQ-NSP

1

ROOM=TEST

B

SHLD-EMI-LOWER-BK-D10

ZT0404

2.70R1.80-NSP

1

SHLD-EMI-LOWER-FRT-D10

TRISTAR_CON_DETECT_L

41 40

AMUX

PMU_AMUX_AY

20

PMU_AMUX_BY

20

TP0416

1

TP-P55

ROOM=TEST

TP0412

1

TP-P55

ROOM=TEST

TP0423

1

TP-P55

ROOM=TEST

A

A

TP IS TO HELP WITH USB SI
IN THE FACTORY FIXTURE.

A

FOR DIAGS

TP0413

1

TP-P55

ROOM=TEST

1

R0413

200K

1%
1/32W
MF
01005

2

ROOM=PMU

A

ANALOG MUX A OUTPUT

#25244799

100k to 200k

ANALOG MUX B OUTPUT

B

A

BS0405

STDOFF-2.56OD1.4ID.99H-SM

1

CLIP-MLB-COAX-RETENTION-D10

CL0401

SM-SP

1

TOP SIDE

BS0406

STDOFF-2.9OD1.9ID-0.85H-SM

1

MOJAVE

MESA_TO_BOOST_EN

38 37

PP16V0_MESA

38 37

LCM

PP_LCM_BL_CAT1_CONN

45 39

PP_LCM_BL_CAT2_CONN

45 39

PP_LCM_BL_ANODE_CONN

45 39

TP0400

1

TP-P55

ROOM=TEST

TP0401

1

TP-P55

ROOM=TEST

TP0409

ROOM=TEST

TP0410

ROOM=TEST

TP0411

A

A

1

TP-P55

1

TP-P55

1

TP-P55

ROOM=TEST

A

A

A

LCM BACKLIGHT SINK1

LCM BACKLIGHT SINK2

LCM BACKLIGHT SOURCE

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

C

BOOTSTRAPPING:BOARD REV

BOARD_REV3

12

BOARD_REV2

12

BOARD_REV1

12

BOARD_REV0

12

BOARD_ID4=No connect

PP1V8

11

NOSTUFF

R0509

010055%MF 1/32W

NOSTUFF

R0505

R0508

NOSTUFF

R0504

01005

ROOM=SOC

ROOM=SOC

MF

ROOM=SOC

MF01005

ROOM=SOC

MF 1/32W

5%

5%

21

21

1/32W01005

21

1/32W

21

5%

1.00K

1.00K

1.00K

1.00K

MAKE_BASE=TRUE

BOARD ID
BOOT CONFIG

PP1V8

SELECTED -->

52 48 47 46 39

BOARD_REV[3:0]

FLOAT=LOW, PULLUP=HIGH

1111 Pre-Proto w/D520 (non enclosure)

1110 PROTO1

1101 PROTO2

1100 PROTO2v5

1011 EVT1
1010 EVT2
xxxx SPARE

1000 CARRIER

xxxx SPARE

0010 DVT

xxxx SPARE

0000 PVT

29 25 18 17 16 13 12 11 9 8 7

D

C

B

NOSTUFF

BOARD_ID2

11

0=EUREKA, 1=KAROO

R0503

01005 MF

NOSTUFF

BOARD_ID1

11

0=FORM FACTOR A, 1=FORM FACTOR B

BOARD_ID0=No connect

PP1V8

12

BOOT_CONFIG1=No connect

BOOT_CONFIG0=No connect

R0501

ROOM=SOC

5%

ROOM=SOC

5%

1.00K

21

1/32W

1.00K

21

1/32W01005 MF

MAKE_BASE=TRUE

BOARD_ID[4:0]

FLOAT=LOW, PULLUP=HIGH

SELECTED --> 01000 D10 MLB

01001 D10 DEV

01010 D11 MLB

01011 D11 DEV

01100 D101 MLB

01101 D101 DEV

01110 D111 MLB

01111 D111 DEV

0=MLB, 1=DEV

0=FORM FACTOR A, 1=FORM FACTOR B

0=EUREKA, 1=KAROO

BOOT_CONFIG[2:0]

FLOAT=LOW, PULLUP=HIGH

000 SPI0

001 SPI0 TEST MODE

010 NVME0_X2

011 NVME0 X2 TEST

SELECTED -->

100 NVME0 X1

101 NVME0 X1 TEST

110 SLOW SPI0 TEST

111 FAST SPI0 TEST

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

SOC - USB, JTAG, XTAL

VDD18_AMUX: 1.62-1.98V @1mA MAX

PP1V1_XTAL

C0700

1

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

1

C0704

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP3V3_USB

VDD18_USB: 1.71-1.89V @20mA MAX

FL0700

VDD11_XTAL:1.06-1.17V @TBD mA MAX

240-OHM-25%-0.20A-0.9DCR

21

01005

ROOM=SOC

19

1

C0705

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

PP1V1

PP1V8

52 48 47 46 39

29 25 18 17 16 13 12 11 9 8 7 5

D

18 15

C

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

PP1V8

CKPLUS_WAIVE=PWRTERM2GND

CL20

VDD12_UH1_HSIC0

AJ60

VDD18_AMUX

CE25

VDD18_USB

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

CG50

VDD11_XTAL

CG26

1

C0701

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

CC25

VDD33_USB

VDD_FIXED_USB

PP0V9_SOC_FIXED

3.14-3.46V @20mA MAX

18 15 10 9 8

tbd - tbd V @5mA MAX

C

B

Dev ONLY

40 37 20 13

PP0701

P2MM-NSM

SM

1

PP

SWD_DOCK_BI_AP_SWDIO

40

SWD_DOCK_TO_AP_SWCLK

40

PMU_TO_SYSTEM_COLD_RESET_L

20 13

PMU_TO_AOP_TRISTAR_ACTIVE_READY

AP_TO_PMU_TEST_CLKOUT

20

AP_TO_NAND_RESET_L

17

NC

NC

NC

NC

NC

CM22
CM20

CL31

CL29

CG37

CJ35
CK33
CH37

CM14

BJ3

BJ2

BL65

UH1_HSIC0_DATA
UH1_HSIC0_STB

JTAG_SEL

JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

COLD_RESET*

CFSB

TST_CLKOUT

S3E_RESET*

SYM 1 OF 16

ANALOGMUX_OUT

USB_DP

USB_DM

USB_VBUS

USB_ID

USB_REXT

N64

CM26
CL26

CH26

CJ26

CK26

AP_TO_PMU_AMUX_OUT

90_USB_AP_DATA_P
90_USB_AP_DATA_N

USB_VBUS_DETECT

NC

AP_USB_REXT

20

40

40

21

1

R0700

200

1%
1/32W
MF

2

01005

ROOM=SOC

B

BJ4

HOLD_RESET

BL3

TESTMODE

WDOG

XI0

XO0

CK35

CM42
CL42

AP_TO_PMU_WDOG_RESET

XTAL_AP_24M_IN
XTAL_AP_24M_OUT

20

1

R0701

511K

1%
1/32W

MF

01005

2

ROOM=SOC

R0702

0.00

0%

1/32W

MF

01005

ROOM=SOC

CRITICAL
ROOM=SOC

Y0700

1.60X1.20MM-SM

24.000MHZ-30PPM-9.5PF-60OHM

21

SOC_24M_O

1

C0702

12PF

5%
16V
CERM

2

01005

ROOM=SOC

31

42

1

C0703

12PF

5%

2

16V
CERM
01005

ROOM=SOC

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - PCIE INTERFACES

34567 8

2 1

D

19 16 10

PP1V2_SOC

1

C0805

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

R0804

0.00

1/32W

01005

ROOM=SOC

21

0%

MF

VDD12_PCIE: 1.14-1.26V @10mA MAX

1

C0801

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

VDD12_PCIE_REFBUF:1.08-1.26V @40mA MAX

PP1V2_SOC_PCIE_REFBUF

1

C0802

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

CE58

VDD12_PCIE

CE49

CC49

CA60

CA55

CC62

CC53

CE60

CE55

CC47

BW55

PP0V9_SOC_FIXED_PCIE_REFBUF

C0804

1

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

R0803

0.00

0%

1/32W

MF

01005

ROOM=SOC

VDD_FIXED_PCIE_xxx:0.855-0.990V @225mA MAX

PP0V9_SOC_FIXED

18 15 10 9 7

D

1

C0803

1

21

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

C0800

1

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=SOC

C0806

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

C

17

17

17

17

17

17

PCIE LINK 0

17

17

29 25 18 17 16 13 12 11 9 7 5

PCIE_NAND_BI_AP_CLKREQ_L

PP1V8

1

R0805

100K

5%
1/32W
MF
01005

2

ROOM=SOC

52 48 47 46 39

90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_AP_TO_NAND_REFCLK_N

#24557655:replace with 20% caps. SI no negative impact

GND_VOID=TRUE

21

C0807

ROOM=SOC

90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_NAND_TO_AP_RXD_N 90_PCIE_NAND_TO_AP_RXD_C_N

D10 NAND is now Gen3 (was Gen2). Caps intentionally 0.22uF

90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_NAND_TXD_N

PCIE_AP_TO_NAND_RESET_L

C0808

ROOM=SOC

C0809

ROOM=SOC

C0810

ROOM=SOC

20%
X5R 01005

20%
X5R

20%
X5R

20%
X5R

6.3V

GND_VOID=TRUE

21

6.3V
01005

GND_VOID=TRUE

21

6.3V
01005

21

GND_VOID=TRUE

6.3V
01005

0.22UF

0.22UF

0.22UF

0.22UF

90_PCIE_NAND_TO_AP_RXD_C_P

90_PCIE_AP_TO_NAND_TXD_C_P
90_PCIE_AP_TO_NAND_TXD_C_N

BC64

CJ48

CK48

CM46

CL46

CK44

CJ44

BJ65

PCIE_CLKREQ0*

PCIE_REF_CLK0_P
PCIE_REF_CLK0_N

PCIE_RX0_P
PCIE_RX0_N

PCIE_TX0_P
PCIE_TX0_N

PCIE_PERST0*

VDD12_PCIE_REFBUF

VDD_FIXED_PCIE_CLK

VDD_FIXED_PCIE_ANA

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 2 OF 16

VDD_FIXED_PCIE_REFBUF

PCIE_CLKREQ3*

PCIE_REF_CLK3_P

PCIE_REF_CLK3_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_TX3_P

PCIE_TX3_N

PCIE_PERST3*

BE66

CL64
CM64

CM61
CL61

CK63
CJ63

BJ66

PCIE_WLAN_BI_AP_CLKREQ_L

90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N

90_AP_PCIE3_RXD_C_P
90_AP_PCIE3_RXD_C_N

90_AP_PCIE3_TXD_C_P
90_AP_PCIE3_TXD_C_N

52

52

52

52

52

52

52

PCIE_AP_TO_WLAN_RESET_L

52

C

PCIE LINK 3PCIE LINK 2

B

PCIE LINK 1

1

R0802

100K

5%
1/32W
MF
01005

2

ROOM=SOC

LINK 1 USED ON AP_DEV ONLY

NC

NC

NC

NC

NC

NC

NC

NC

CL54

CM54

CK52

CJ52

CM50

CL50

CH57

CG57

PCIE_CLKREQ1*

PCIE_REF_CLK1_P
PCIE_REF_CLK1_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_PERST1*

PCIE_EXT_REF_CLK_P
PCIE_EXT_REF_CLK_N

LINK1

LINK3LINK0

LINK2

PCIE_CLKREQ2*

PCIE_REF_CLK2_P
PCIE_REF_CLK2_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_TX2_P

PCIE_TX2_N

PCIE_PERST2*

BE65BG66

CK59
CJ59

CK56
CJ56

CM57
CL57

BE64BG64

PCIE_BB_BI_AP_CLKREQ_L

90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N

WLAN RX PP's are now managed on Page 52

90_AP_PCIE2_RXD_C_P
90_AP_PCIE2_RXD_C_N

90_AP_PCIE2_TXD_C_P
90_AP_PCIE2_TXD_C_N

52

52

52

52

52

52

52

1

R0806

100K

5%
1/32W
MF
01005

2

ROOM=SOC

PCIE_AP_TO_BB_RESET_L

1

R0801

100K

5%
1/32W
MF
01005

ROOM=SOC

2

B

52

A

PCIE_REXT

CG63

AP_PCIE_RCAL

1

R0800

3.01K

1%
1/32W
MF
01005

2

ROOM=SOC

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

SOC - MIPI & ISP INTERFACES

34567 8

2 1

D

0.825-0.94V @25mA MAX

18 15 10 8 7

90_MIPI_NH_TO_AP_DATA0_P

45

45

90_MIPI_NH_TO_AP_DATA0_N

PP0V9_SOC_FIXED

1

2

C0902

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=SOC

1

C0900

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

A18

MIPI0C_DPDATA0

B18

MIPI0C_DNDATA0

G6

G17

G13

VDD_FIXED_MIPI

G10

G15

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 3 OF 16

G21

G19

VDD18_MIPI

ISP_I2C0_SCL

ISP_I2C0_SDA

1.62-1.98V @7mA MAX

1

2

N65
N66

1

C0901

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

I2C_ISP_UT_SCL
I2C_ISP_UT_SDA

PP1V8

C0903

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=SOC

48

48

D

52 48 47 46 39

29 25 18 17 16 13 12 11 8 7 5

C

R0900

4.02K

1/32W

01005

ROOM=SOC

D11/111 ONLY

1%

MF

U64
R65

U65
U66

W64
W66

AA64

B50
A48
C48

A50
E50
AA65
AE64
AC65

I2C_ISP_NV_SCL
I2C_ISP_NV_SDA

I2C_ISP_NH_SCL
I2C_ISP_NH_SDA

NC
NC

NC

Dev ONLY

Spare

AP_TO_UT_CLK_R
NC_AP_TO_NV_CLK_R

AP_TO_NH_CLK_R

AP_TO_UT_SHUTDOWN_L
NC_AP_TO_NV_SHUTDOWN_L
AP_TO_NH_SHUTDOWN_L

TP_SENSOR3_RST

NC

46

46

48

48

25

29

D11/111 ONLY

D11/111 ONLY

1

PP

PP0902

SM

P2MM-NSM

ROOM=SOC

R0906

33.2

1/32W

01005

ROOM=SOC

1%

MF

21

NOSTUFF

1

C0906

100PF

5%
35V

2

NP0-C0G
01005

R0907

33.2

1/32W

01005

ROOM=SOC

Radar 20511449

<--- Needed for Cayman debug; this pin cannot be input

1%

MF

21

NOSTUFF

1

C0907

100PF

5%
35V

2

NP0-C0G
01005

AP_TO_UT_CLK

AP_TO_NH_CLK

C

25

29

NC
NC

NC
NC

B20

MIPI0C_DPDATA1

C20

MIPI0C_DNDATA1

C24

MIPI0C_DPDATA2

B24

MIPI0C_DNDATA2

A26

MIPI0C_DPDATA3

B26

MIPI0C_DNDATA3

B22

MIPI0C_DPCLK

A22

MIPI0C_DNCLK

E24

MIPI0C_REXT

B4

MIPID_DPDATA0

A4

MIPID_DNDATA0

B5

MIPID_DPDATA1

C5

MIPID_DNDATA1

C9

MIPID_DPDATA2

B9

MIPID_DNDATA2

A11

MIPID_DPDATA3

B11

MIPID_DNDATA3

45

90_MIPI_NH_TO_AP_DATA1_P

45

90_MIPI_NH_TO_AP_DATA1_N

45

90_MIPI_NH_TO_AP_CLK_P

45

90_MIPI_NH_TO_AP_CLK_N

MIPI0C_REXT

1

39

90_MIPI_AP_TO_LCM_DATA0_P

39

2

90_MIPI_AP_TO_LCM_DATA0_N

39

90_MIPI_AP_TO_LCM_DATA1_P

39

90_MIPI_AP_TO_LCM_DATA1_N

NC_MIPI_AP_TO_LCM_DATA2_P
NC_MIPI_AP_TO_LCM_DATA2_N

NC_MIPI_AP_TO_LCM_DATA3_P
NC_MIPI_AP_TO_LCM_DATA3_N

ISP_I2C1_SCL

ISP_I2C1_SDA

ISP_I2C2_SCL

ISP_I2C2_SDA

ISP_I2C3_SCL

ISP_I2C3_SDA

SENSOR_INT

SENSOR0_CLK
SENSOR1_CLK
SENSOR2_CLK

SENSOR0_RST
SENSOR1_RST
SENSOR2_RST
SENSOR3_RST
SENSOR4_RST

B

39

90_MIPI_AP_TO_LCM_CLK_P

39

90_MIPI_AP_TO_LCM_CLK_N

26

AP_TO_STROBE_DRIVER_HWEN

36

SPI_AP_TO_MAGGIE_CS_L

1%

1/32W

MF

01005

1

2

R0901

4.02K

ROOM=SOC

MIPID_REXT

NC

B7

MIPID_DPCLK

A7

MIPID_DNCLK

BN4

DISP_TOUCH_BSYNC0

BR2

DISP_TOUCH_BSYNC1

BR4

DISP_TOUCH_EB

E11

MIPID_REXT

SENSOR0_ISTRB
SENSOR1_ISTRB

SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN

MIPI1C_REXT

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK

MIPI1C_DNCLK

E52
D50

C50
B48

E16

B12
C12

B16
C16

B14
A14

NC_SENSOR0_ISTRB

NC

NC

AP_TO_MUON_BL_STROBE_EN

Per Radar 21221938

37

B

Dev only

A

28 27 26 25 23 21 19 18 10 4
52 46 41 40 39 37 35 34 33 31

53

8 7 5 4 2 1

PP_VDD_MAIN

1

C0904

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

AC return path for LCM MIPI which is referenced to GND and VDD_MAIN
Radar 21203307

1

C0905

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0908

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0909

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0910

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

A

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

36

D

34567 8

2 1

D

PP1V2_SOC

1

C1013

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

VDD12_PLL_LPDP:1.14-1.26V @3mA MAX
VDD12_LPDP:1.14-1.26V @60mA MAX

1

C1001

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1004

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1005

0.01UF

10%

6.3V

2

X5R
01005

ROOM=SOC

90_LPDP_UT_TO_AP_D0_P

25

90_LPDP_UT_TO_AP_D0_N

25

1

C1002

15PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

Desense for Wifi frequencies

CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND

CAYMAN-2GB-20NM-DDR-M

A54

LPDPRX_RX_D0_P

B54

LPDPRX_RX_D0_N

G30

G28

G25

G55

VDD12_LPDP_TX

U0700

SYM 4 OF 16

G23

G62

G60

G58

VDD12_LPDP_RX

CSP

VDD12_PLL_LPDP

LPDP_TX0P

LPDP_TX0N

B27
C27

NC

NC

D

Dev ONLY

C

LPDP Lanes swapped between D10 and D11

D11/111 ONLY

D11/111 ONLY

90_LPDP_UT_TO_AP_D1_P

25

90_LPDP_UT_TO_AP_D1_N

25

NC_90_LPDP_NV_TO_AP_D2_P

46

NC_90_LPDP_NV_TO_AP_D2_N

46

NC_90_LPDP_NV_TO_AP_D3_P

46

NC_90_LPDP_NV_TO_AP_D3_N

46

GND ON MLB; other on Dev

LPDP_UT_BI_AP_AUX

25

NC_AP_LPDP_AUX2

46

NC

NC

NC

B56

LPDPRX_RX_D1_P

C56

LPDPRX_RX_D1_N

A61

LPDPRX_RX_D2_P

B61

LPDPRX_RX_D2_N

B63

LPDPRX_RX_D3_P

C63

LPDPRX_RX_D3_N

A64

LPDPRX_RX_D4_P

B64

LPDPRX_RX_D4_N

D54

LPDPRX_AUX_D0_P

E56

LPDPRX_AUX_D1_P

D61

LPDPRX_AUX_D2_P

E63

LPDPRX_AUX_D3_P

D64

LPDPRX_AUX_D4_P

LPDP_TX1P

LPDP_TX1N

LPDP_TX2P

LPDP_TX2N

LPDP_TX3P

LPDP_TX3N

LPDP_AUX_P
LPDP_AUX_N

LPDP_CAL_DRV_OUT

LPDP_CAL_VSS_EXT

A29
B29

B31
C31

A33
B33

D33
E33

E35
E31

NC

NC

C

NC

NC

NC

NC

NC

NC

NC

B

18 15 9 8 7

R1001

300

1%

1/32W

MF

01005-1

ROOM=SOC

C1006

100PF

5%

16V

NP0-C0G

01005

ROOM=SOC

GND ON MLB; other on Dev

PP0V9_SOC_FIXED

1

2

AP_LPDPRX_RCAL_NEG

1

2

#24401637:Unconnect LPDPRX_EXT_C

NC

B59

LPDPRX_BYP_CLK_P

C59

LPDPRX_BYP_CLK_N

A57

LPDPRX_RCAL_P

B57

LPDPRX_RCAL_N

D57

LPDPRX_EXT_C

EDP_HPD

DP_WAKEUP

BN3
AP2

NC

NC

Reserved for PanelID[1:0] on ap_dev board
Reserved for PanelID[1:0] on ap_dev board

B

A

28 27 26 25 23 21 19 18 9 4

52 46 41 40 39 37 35 34 33 31

8 7 5 4 2 1

53

PP_VDD_MAIN

1

C1010

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

AC return path for LCM LPDP which is referenced to GND and VDD_MAIN

1

C1011

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - SERIAL INTERFACES

34567 8

2 1

D

I2S_AP_TO_CODEC_MCLK

32

32

32

32

32

R1103

33.2

1%

1/32W

MF

MF

01005

ROOM=SOC

D

21

I2S_AP_TO_CODEC_MCLK_R
I2S_AP_TO_CODEC_MSP_BCLK

32

32

32

32

32

I2S_AP_TO_CODEC_MSP_LRCLK

32

32

32

32

32

I2S_CODEC_TO_AP_MSP_DIN

32

32

32

32

32

I2S_AP_TO_CODEC_MSP_DOUT

32

32

32

32

32

BV65

BY66
BU64
BR64
BU65

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

U0700

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CSP

CSP

CSP

CSP

CSP

SYM 6 OF 16

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

36 35 34 33 32

35 34 33 32

35 34 33 32

35 34 33 32

34 33 32

36 35 34 33 32

36 35 34 33 32

35 34 33 32

34 33 32

34 33 32

36

36

36

36

36

36

36

36

36

36

I2S1/2/3 MCLK NC #24559456

I2S_AP_TO_BT_BCLK
I2S_AP_TO_BT_LRCLK
I2S_BT_TO_AP_DIN
I2S_AP_TO_BT_DOUT

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
I2S_MAGGIE_TO_AP_DIN
I2S_AP_TO_MAGGIE_DOUT

NC

NC

D48
E48
A46
C46
E46

BU66
BR66
BN64
BN65

BJ64

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

I2C2_SDA

I2C3_SCL

I2C3_SDA

CK7
CG12

AG64
AG66

U3
U4

AE66
AE65

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

C

B

SPI_AP_TO_CODEC_MAGGIE_SCLK

36 32

36 32

36 32

36 32

36 32

Route as daisy-chain. No T's allowed.

SPI_AP_TO_TOUCH_SCLK

39

39

39

39

39

R1116

0.00

0.00

0.00

0.00

0.00

0%

0%

0%

0%

0%

1/32W

1/32W

1/32W

1/32W

1/32W

MF

MF

MF

MF

MF

01005

01005

01005

01005

01005

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

R1101

0.00

0.00

0.00

0.00

0.00

0%

0%

0%

0%

0%

1/32W

1/32W

1/32W

1/32W

1/32W

MF

MF

MF

MF

MF

01005

01005

01005

01005

01005

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

I2S_BB_TO_AP_BCLK

53

53

53

53

53

I2S_BB_TO_AP_LRCLK

53

53

53

53

53

I2S_BB_TO_AP_DIN

53

53

53

53

53

I2S_AP_TO_BB_DOUT

53

53

53

53

53

NC

CH11

CM7

CK9

CG18

CJ9

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

SPI4_SCLK

SPI4_MISO
SPI4_MOSI

I2C5_SCL

I2C5_SDA

CB2
BY4
BY3
CB4

N2
N3
N4
R3

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

BOARD_ID2

5

5

5

5

5

BOARD_ID1

5

5

5

5

5

BOARD_ID0

PP1V8

5

SPI_CODEC_MAGGIE_TO_AP_MISO

36 32

36 32

36 32

36 32

36 32

SPI_AP_TO_CODEC_MAGGIE_MOSI

36 32

36 32

36 32

36 32

36 32

21

SPI_AP_TO_CODEC_MAGGIE_SCLK_R
SPI_AP_TO_CODEC_CS_L

32

32

32

32

32

NC

GPIO_42
GPIO_43

PMU_SCLK
PMU_MISO
PMU_MOSI

DWI_CLK

C44
B44
A44
D44

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI_TOUCH_TO_AP_MISO

39

39

39

39

39

SPI_AP_TO_TOUCH_MOSI

39

39

39

39

39

21

SPI_AP_TO_TOUCH_SCLK_R
SPI_AP_TO_TOUCH_CS_L

39

39

39

39

39

DWI_DO

DROOP

GPU_TRIGGER

SOCHOT

B42
A42
E44
C42

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

CLK32K_OUT

NAND_SYS_CLK

SPI_MESA_TO_AP_MISO

38

38

38

38

38

SPI_AP_TO_MESA_MOSI

38

38

38

38

38

SPI_AP_TO_MESA_SCLK

38

38

38

38

38

MESA_TO_AP_INT

38

38

38

38

38

CJ12

NC

CG22

NC

CM9

NC

CH16
CJ14

CH20

NC

CH22

NC

AH65

SPI_PMGR_TO_PMU_SCLK

AH66

SPI_PMU_TO_PMGR_MISO

AK64

SPI_PMGR_TO_PMU_MOSI

AK65

DWI_PMGR_TO_BACKLIGHT_CLK

AM64

DWI_PMGR_TO_BACKLIGHT_DATA

I2C5_SCL
I2C5_SDA

AE3
BY2

AG4

AM66

AP_TO_CUMULUS_CLK32K

BN66

AP_TO_NAND_SYS_CLK_R

R1118

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

37

37

37

37

37

37

37

37

37

37

39

39

39

39

39

0.00

0.00

0.00

0.00

0.00

0%

0%

0%

0%

0%

1/32W

1/32W

1/32W

1/32W

1/32W

MF

MF

MF

MF

MF

01005

01005

01005

01005

01005

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

C

47 11

47 11

47 11

47 11

47 11

47 11

47 11

47 11

47 11

47 11

1

R1113

10K

10K

10K

10K

10K

5%

5%

5%

5%

5%
1/32W

1/32W

1/32W

1/32W

1/32W
MF

MF

MF

MF

MF
01005

01005

01005

01005

01005

2

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

PP1V8

1

R1114

10K

10K

10K

10K

10K

5%

5%

5%

5%

5%
1/32W

1/32W

1/32W

1/32W

1/32W
MF

MF

MF

MF

MF
01005

01005

01005

01005

01005

2

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

PMU_TO_AP_PRE_UVLO_L
PMU_TO_AP_THROTTLE_GPU_L

AP_TO_PMU_SOCHOT_L

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

B

21

AP_TO_NAND_SYS_CLK

17

17

17

17

17

A

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

52 48 47 46 39 29

52 48 47 46 39 29

52 48 47 46 39 29

52 48 47 46 39 29

PP1V8

I2C5

See Radar#25316444 for Details

1

C1101

1.0UF

1.0UF

1.0UF

1.0UF

1.0UF

20%

20%

6.3V

6.3V

2

X5R

X5R
0201-1

0201-1

0201-1

ROOM=SOC

ROOM=SOC

VCC

U1101

WLCSP

WLCSP

WLCSP

WLCSP

WLCSP

VSS

ROOM=SOC

CRITICAL

CRITICAL

CRITICAL

B2 A1

I2S_AP_TO_CODEC_MCLK

A2B1

SDASCL

I2C5_SDA
I2C5_SCL

I2S_AP_TO_CODEC_MCLK_R
I2S_AP_TO_CODEC_MSP_BCLK
I2S_AP_TO_CODEC_MSP_LRCLK
I2S_CODEC_TO_AP_MSP_DIN
I2S_AP_TO_CODEC_MSP_DOUT

47 11

47 11

47

47

I2S_AP_TO_BT_LRCLK
I2S_BT_TO_AP_DIN

I2S_AP_TO_BT_LRCLK

47 11

47 11

47 11

47 11

47 11
I2S_AP_TO_BT_LRCLK
I2S_BT_TO_AP_DIN
I2S_AP_TO_BT_DOUT
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_DIN
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
I2S_AP_TO_MAGGIE_DOUT

I2S_MAGGIE_TO_AP_DIN
I2S_AP_TO_MAGGIE_DOUT
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_DIN
I2S_AP_TO_BB_DOUT

BOARD_ID2
BOARD_ID2
BOARD_ID2
BOARD_ID2

To Cayman

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

I2C5_SCL
I2C5_SCL

I2C5_SDA
I2C5_SDA

I2C5_SCL
I2C5_SCL

I2C5_SDA
I2C5_SDA

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

C

B

36

36

36

36

29 25 18 17 16 13 11 9 8 7 5

29 25 18 17 16 13 11 9 8 7 5

29 25 18 17 16 13 11 9 8 7 5

29 25 18 17 16 13 11 9 8 7 5

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

20

20

20

20

#24557547:Delete R1204

MAGGIE_TO_AP_CDONE

PP1V8

Nostuff per #24511702

PMU_TO_AP_THROTTLE_CPU_L

D101/D111 ONLY

D101/D111 ONLY

D101/D111 ONLY

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

1

R1210

10K

10K

10K

10K

5%

5%

5%

5%
1/32W

1/32W

1/32W

1/32W
MF

MF

MF

MF
01005

01005

01005

01005

2

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

D10/D11 ONLY

Dev only

SOC - GPIO INTERFACES

AP_TO_ACC_BUCK_VSEL

27

27

27

27

AP_TO_MAGGIE_CRESETB_L

36

36

36

36

BUTTON_VOL_UP_L

44 20

44 20

44 20

44 20

DEV ONLY

AP_TO_BB_RESET_L

53

53

53

53

RESERVERD FOR SSHB ID ON DEV BOARD

NC_AP_TO_BB_IPC_GPIO2

NC_AP_TO_BB_IPC_GPIO2

NC_AP_TO_BB_IPC_GPIO2

NC_AP_TO_BB_IPC_GPIO2
NC_AP_TO_GNSS_WAKE

NC_AP_TO_GNSS_WAKE

NC_AP_TO_GNSS_WAKE

NC_AP_TO_GNSS_WAKE

53

53

53

53

AP_TO_BB_TIME_MARK
NC_AP_TO_GNSS_TIME_MARK

BB_TO_AP_RESET_DETECT_L

53

53

53

53

AP_TO_SPKAMP2_RESET_L

33

33

33

33

ALS_TO_AP_INT_L

29

29

29

29

53

53

53

53

AP_TO_NFC_FW_DWLD_REQ

AP_TO_NAND_FW_STRAP

17

17

17

17

TOUCH_TO_AP_INT_L

39

39

39

39

AP_TO_BBPMU_RADIO_ON_L

53

53

53

53

53

AP_TO_ICEFALL_FW_DWLD_REQ

AP_TO_LCM_RESET_L

39

39

39

39

AP_BI_HOMER_BOOTLOADER_ALIVE

36

36

36

36

PMU_TO_AP_FORCE_DFU

20 4

20 4

20 4

20 4

NC_DFU_STATUS

5

PP1V8

53

53

53

53

AP_TO_NFC_DEV_WAKE

PMU_TO_AP_BUF_RINGER_A

20

20

20

20

AP_TO_BT_WAKE

53

53

53

53

AP_TO_WLAN_DEVICE_WAKE

53

53

53

53

BOARD_REV3

5

5

5

5

BOARD_REV2

5

5

5

5

BOARD_REV1

5

5

5

5

BOARD_REV0

5

5

5

5

AP_TO_TOUCH_MAMBA_RESET_L

39

39

39

39

AP_TO_BB_MESA_ON

53

53

53

53

AP_TO_BB_COREDUMP

53

53

53

53

53

53

53

53

AP_TO_BB_IPC_GPIO1

BOOT_CONFIG0

#24608280

BOOT_CONFIG1

BOARD_ID4

NC

NC

NC

NC

NC

NC

BB64
BC65
BB66
AY65
AY66
AV65
AV67

AT67
AT66

AT64
AP66
AP65
AH64

AE4
AC3
AE2
BB2
BB4
BC3
BC4
BE2
BE4
BE3
BG2

CJ11

CL9
CH14
CK11
CG20

AA2
AA3

D42

E42

A41

C41

E41

A39

AT4

AT2

AV3
AY2
AY3

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41

U0700

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CSP

CSP

CSP

CSP

SYM 5 OF 16

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART0_RXD

UART0_TXD

UART1_CTS*
UART1_RTS*

UART1_RXD

UART1_TXD

UART2_CTS*
UART2_RTS*

UART2_RXD

UART2_TXD

UART3_CTS*
UART3_RTS*

UART3_RXD

UART3_TXD

UART4_CTS*
UART4_RTS*

UART4_RXD

UART4_TXD

UART5_RTXD

UART6_RXD

UART6_TXD

UART7_RXD

UART7_TXD

AG2
AH4
AH3

CL5
CJ7

E39
D39
C39
B39

AM4
AK3
AK4
AH2

AA4
W2
W4
U2

D37
C37
B37
A37

BG4

CG16
CG14

AP3
AM2

NC

PROX_BI_AP_AOP_INT_PWM_L
NC_BB_TO_AP_RESET_ACT_L

UART_AP_DEBUG_RXD
UART_AP_DEBUG_TXD

UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_RTS_L

UART_AP_TO_BT_RTS_L
UART_BT_TO_AP_RXD

UART_BT_TO_AP_RXD
UART_AP_TO_BT_TXD

NC_AP_UART2_CTS_L
NC_AP_UART2_RTS_L
NC_AP_UART2_RXD

NC_AP_UART2_RXD
NC_AP_UART2_TXD

NC_AP_UART2_TXD

NC_AP_UART2_TXD

NC_AP_UART2_TXD

UART_NFC_TO_AP_CTS_L

UART_NFC_TO_AP_CTS_L

UART_NFC_TO_AP_CTS_L

UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L

UART_AP_TO_NFC_RTS_L

UART_AP_TO_NFC_RTS_L

UART_AP_TO_NFC_RTS_L
UART_NFC_TO_AP_RXD

UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_TXD

UART_WLAN_TO_AP_CTS_L

UART_WLAN_TO_AP_CTS_L
UART_AP_TO_WLAN_RTS_L

UART_AP_TO_WLAN_RTS_L
UART_WLAN_TO_AP_RXD

UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD

UART_AP_TO_WLAN_TXD

SWI_AP_BI_TIGRIS

SWI_AP_BI_TIGRIS

UART_ACCESSORY_TO_AP_RXD

UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_ACCESSORY_TXD

UART_AP_TO_ACCESSORY_TXD

UART_HOMER_TO_AP_RXD

UART_HOMER_TO_AP_RXD
UART_AP_TO_HOMER_TXD

UART_AP_TO_HOMER_TXD

29 13

29 13

29 13

29 13

40

40

40

40

40

40

40

40

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53
UART_AP_TO_BT_RTS_L
53

53

53

53

53

53

53

53

53

53

53

53
NC_AP_UART2_RXD

NC_AP_UART2_RXD

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

21

21

21

21

40

40

40

40

40

40

40

40

36

36

36

36

36

36

36

36

D

D101/D111 ONLY

C

D101/D111 ONLY; for GNSS

B

A

PMU_TO_AP_BUF_POWER_KEY_L

20

20

20

20

PMU_TO_AP_BUF_VOL_DOWN_L

20

20

20

20

#25120460:REQUEST_DFU Assignment

BU2
BU3

REQUEST_DFU1
REQUEST_DFU2

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

A

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SOC - AOP

34567 8

2 1

D

C

#24512059: Remove R1300 PU

Use internal pullup in SOC (AOP side).

Internal pullup in AOP. Radar 21210869

20

20 15

24

24

29 12

24

24

24

24

53 39 23 20

40

36

24

24

24

35 34 33 32

48

20

AOP_TO_PMU_SLEEP1_REQUEST

PMU_TO_AOP_SLEEP1_READY

SPI_AOP_TO_COMPASS_CS_L
COMPASS_TO_AOP_INT
PROX_BI_AP_AOP_INT_PWM_L
ACCEL_GYRO_TO_AOP_DATARDY
SPI_AOP_TO_ACCEL_GYRO_CS_L
ACCEL_GYRO_TO_AOP_INT
SPI_AOP_TO_PHOSPHORUS_CS_L
LCM_TO_MANY_BSYNC
TRISTAR_TO_AOP_INT
AOP_TO_MAGGIE_EN

PHOSPHORUS_TO_AOP_INT_L
SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L

BOT_ACCEL_GYRO_TO_AOP_DATARDY

AUDIO_TO_AOP_INT_L

AOP_TO_MESA_I2C_ISO_EN

PMU_TO_AOP_IRQ_L

CM16
CM29

CK12
CK16
CK18

CJ29

CG31

CH31
CK20

CJ31
CK27
CK24
CK29
CK22

CM12

CK31

CG33

CJ33

CAYMAN-2GB-20NM-DDR-M

AOP_DDR_REQ
AOP_DDR_RESET*

AOP_FUNC_0
AOP_FUNC_1
AOP_FUNC_2
AOP_FUNC_3
AOP_FUNC_4
AOP_FUNC_5
AOP_FUNC_6
AOP_FUNC_7
AOP_FUNC_8
AOP_FUNC_9
AOP_FUNC_10
AOP_FUNC_11
AOP_FUNC_12
AOP_FUNC_13
AOP_FUNC_14
AOP_FUNC_15

U0700

CSP

SYM 7 OF 16

CFSB_AOP

AWAKE_REQ

AWAKE_RESET*

AOP_PDM_CLK0
AOP_PDM_DATA0
AOP_PDM_DATA1

RT_CLK32768

AOP_SWD_TCK_OUT

AOP_SWD_TMS0
AOP_SWD_TMS1

SWD_TMS2
SWD_TMS3

CH35

CM31
CJ37

CM37
CH41
CK39

CM33

CL14

CL16
CG35
BU4
BV3

PP1V8

NOSTUFF

1

R1304

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

PMU_TO_SYSTEM_COLD_RESET_L

AOP_TO_PMU_ACTIVE_REQUEST
PMU_TO_AOP_TRISTAR_ACTIVE_READY

AOP_TO_MESA_BLANKING_EN

AOP_TO_WLAN_CONTEXT_B
AOP_TO_WLAN_CONTEXT_A

PMU_TO_AOP_CLK32K

SWD_AP_TO_MANY_SWCLK

HOMER_TO_AOP_WAKE_INT
SWD_AOP_BI_BB_SWDIO
SWD_AP_BI_NAND_SWDIO
SWD_AP_BI_HOMER_SWDIO

D

52 48 47 46

39 29 25 18 17 16 12 11 9 8 7 5

20 7

20

40 37 20 7

38

53

53

20

C

36

53

17

36

53 36 17

BB_SWDIO has pullup in Radio_MLB pages

B

#25756894:North Carbon R1 (+Mg,P)

#25756894:South Carbon R2

24

SPI_AOP_TO_IMU_SCLK_R1

24

SPI_AOP_TO_IMU_SCLK_R2

36 35 34 33

I2S_AOP_TO_MAGGIE_L26_MCLK

R1305

49.9

21

1%

1/32W

MF

01005

ROOM=SOC

R1306

49.9

21

1%

1/32W

MF

01005

ROOM=SOC

I2C_AOP_SCL

48

I2C_AOP_SDA

48

SPI_IMU_TO_AOP_MISO

24

SPI_AOP_TO_IMU_MOSI

24

SPI_AOP_TO_IMU_SCLK

UART_BB_TO_AOP_RXD

53

UART_AOP_TO_BB_TXD

53

MAGGIE_TO_AOP_INT

36

UART_AOP_TO_MAGGIE_TXD

36

UART_TOUCH_TO_AOP_RXD

39

39

UART_AOP_TO_TOUCH_TXD

I2S_CODEC_XSP_TO_AOP_BCLK

R1303

33.2

1%

1/32W

MF

01005

ROOM=SOC

21

32

32

I2S_CODEC_XSP_TO_AOP_DIN
I2S_AOP_TO_MAGGIE_L26_MCLK_R
I2S_CODEC_XSP_TO_AOP_LRCLK

32

I2S_AOP_TO_CODEC_XSP_DOUT

32

CM11

CJ24

CJ18
CJ27
CJ16

CK14

CJ20

CJ22

CL11

CG29
CH29

CL35
CJ39

CM35

CK37

CG39

AOP_I2C0_SCL
AOP_I2C0_SDA

AOP_SPI_MISO
AOP_SPI_MOSI
AOP_SPI_SCLK

AOP_UART0_RXD
AOP_UART0_TXD

AOP_UART1_RXD
AOP_UART1_TXD

AOP_UART2_RXD
AOP_UART2_TXD

AOP_I2S_BCLK
AOP_I2S_DIN
AOP_I2S_MCK
AOP_I2S_LRCK

AOP_I2S_DOUT

DOCK_ATTENTION

DOCK_CONNECT

CG41

CL37

AOP_TO_SPKAMP1_ARC_RESET_L

MESA_TO_AOP_FDINT

35 34

38

DOCK_CONNECT can be GPIO, but input only. Radar 21680759

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - CPU, GPU & SOC RAILS

34567 8

2 1

D

C

B

PP_CPU_VAR

1.06V @17.4A MAX

0.9V @tbd A MAX

0.625V @tbd A MAX

1

C1401

15UF

20%

6.3V

2

X5R
0402-1

ROOM=SOC

C1404

7.5UF

20%

4V

CERM CERM

1

432

ROOM=SOC

C1405

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1406

0.47UF

20%

6.3V
CERM
0402

1

432

1

2

C1411

7.5UF

1

ROOM=SOC

C1412

4.3UF

1

C1413

1

1.06V @1.0A MAX

0.80V @TBDA MAX

PP_CPU_SRAM_VAR

18

ROOM=SOC

C1407

7.5UF

20%

4V
CERM
0402

1

1.03V @1.44A MAX

0.92V @1.50A MAX

0.80V @TBD A MAX

PP_GPU_SRAM_VAR

18

3

4

2

18 14

C1408

15UF

20%

6.3V
X5R

0402-1

ROOM=SOC

20%

4V

0402

432

20%

4V

CERM
0402

432

ROOM=SOC

0.47UF

20%

6.3V
CERM
0402

432

ROOM=SOC

C1435

7.5UF

20%

4V

CER

0402

1

2

ROOM=SOC

C1439

7.5UF

20%

4V

CER

0402

1

3

4

1

C1434

15UF

20%

6.3V

2

X5R
0402-1

ROOM=SOC

C1417

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1418

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1419

0.47UF

20%

6.3V
CERM
0402

1

432

ROOM=SOC

C1433

7.5UF

20%

4V
CERM
0402

1

ROOM=SOC

C1437

7.5UF

20%

4V
CERM
0402

1

ROOM=SOC

C1422

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1423

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1424

0.47UF

20%

6.3V
CERM
0402

1

432

BUCK0_PP_CPU_FB

18

1

C1458

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

432

1

C1459

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

1

C1449

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

ROOM=SOC

C1427

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1428

1UF 1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1460

7.5UF

20%

4V
CERM
0402

1

432

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

ROOM=SOC

C1430

4.3UF

1

ROOM=SOC

C1431

1

ROOM=SOC

C1461

7.5UF

1

XW1402

21

ROOM=SOC

20%

4V
CERM
04020402

20%

4V
CERM
0402

20%

4V
CERM
0402

OMIT

PP1401

P2MM-NSM

ROOM=SOC

SM

PP

1

PP_GPU_VAR

18 14

PP_SOC_VAR

18

0.80V @4.1A MAX

PP1402

P2MM-NSM

ROOM=SOC

XW1401

SHORT-20L-0.05MM-SM

AD10
AD15
AD19
AD23

AF13
AF17
AJ23
AL21

432

432

432

AL8
AN10
AN19
AN23
AR13
AR17
AR21
AU10
AU15

AW13
AW17
AW21

BA10
BA23
BD21

BD8
BF10
BF23

BH13
BH17
BH21
BK10
BK15

AJ10

AF8

AN15

AR8

AU19

AW8
BA15
BA19

BH8

AF43
AF47
AF51

P17
P21
P25
P30
P34
P38
P43
P47
P51
Y15
Y19
Y23
Y40
Y45
Y49
Y53

VDD_CPU

VDD_CPU_SRAM

VDD_GPU_SRAM

CAYMAN-2GB-20NM-DDR-M

U0700

CSP

SYM 8 OF 16

VDD_GPU

VDD_CPU_SENSE

VSS_CPU_SENSE

VDD_GPU_SENSE

VDD_SOC_SENSE

VSS_SENSE

AB13
AB17
AB21
AB25
AB43
AB47
AB51
AB55
AD40
AD45
AD49
AD53
AF55
AJ40
AJ49
AJ53
J25
J30
J38
J43
J47
J51
L15
L19
L23
L28
L32
L36
L40
L45
L49
L53
P13
T15
T36
T40
T53
V13
V25
V34
V38
V51
V55
Y28

BK23

BK21

TP_AP_VSS_CPU_SENSE

AJ45

AL47

TP_VDD_SOC_SENSE

AJ47

TP_VSS_SENSE

1

2

ROOM=SOC

C1402

4.3UF

20%

4V
CERM
0402

1

432

OMIT

NO_XNET_CONNECTION

C1414

15UF

20%

6.3V
X5R
0402-1

ROOM=SOC

ROOM=SOC

1

C1466

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

C1409

4.3UF

20%

4V
CERM
0402

1

432

SM

PP

21

1

1

1

1

1

1

1

C1448

2

ROOM=SOC

ROOM=SOC

C1452

4.3UF

20%

4V
CERM
0402

432

ROOM=SOC

C1410

1UF

20%

4V
CERM
0402

432

PP1403

SM

PP

PP

PP

P2MM-NSM

ROOM=SOC

PP1410

SM

P2MM-NSM

ROOM=SOC

PP1411

SM

P2MM-NSM

ROOM=SOC

PP_CPU_VAR

BUCK1_PP_GPU_FB

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

C1454

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

ROOM=SOC

C1416

7.5UF

1

C1415

1UF

20%

4V
CERM
0402

1

432

20%

4V
CERM
0402

432

ROOM=SOC

C1420

1UF

20%

4V
CERM
0402

1

432

AP_VDD_CPU_SENSE

SM

1

PP

AP_VDD_GPU_SENSE

SM

1

PP

18 14

18

ROOM=SOC

C1421

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC ROOM=SOC

C1425

0.47UF

20%

6.3V
CERM
0402

1

PP1408

P2MM-NSM

ROOM=SOC

PP1409

P2MM-NSM

ROOM=SOC

1

C1436

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

C1444

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

1.03V @12.9A MAX

0.92V @10.7A MAX

0.80V @TBD A MAX

0.67V @TBD A MAX

PP_GPU_VAR

ROOM=SOC

C1426

7.5UF

20%

4V
CERM
0402

1

432

C1429

0.47UF

20%

6.3V
CERM
0402

1

432

20

20

432

ROOM=SOC

C1432

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1456

0.47UF

6.3V
CERM
0402

1

20%

ROOM=SOC

C1457

0.47UF

20%

6.3V
CERM
0402

1

432

432

18 14

AD28
AD32
AF60

AJ28
AJ32
AJ36

AL6
AN28
AN32
AN36
AN40
AN45
AN49
AN53
AN58
AR25
AR30
AR34
AR38
AR43
AR47
AR51
AR55

AW30
AW34
AW38
AW43
AW47
AW51

|- - - |||||||- - |||==

AW55
AW60

BD25
BD30
BD34
BD38
BD43
BD47
BD51
BD55

BD6
BD60
BF28
BF32
BF36
BF45
BF49
BF53
BF58
BK28
BK32
BK36
BK40

CAYMAN-2GB-20NM-DDR-M

VDD_SOC

U0700

CSP

SYM 9 OF 16

C1403

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

ROOM=SOC

C1465

VDD_SOC

4.3UF

20%

4V
CERM
0402

1

432

BK45
BK49
BK53
BM55
BP15
BP19
BP23
BP28
BP32
BP36
BP40
BP45
BP49
BP53
BP58
BT13
BT17
BT21
BT25
BT30
BT34
BT38
BT43
BT47
BT51
BT55
BW10
CA13
CA17
CA21
CA25
CA30
CA34
CA38
CA43
CA47
CE13
CE17
CE45
J13
J21
J34
P55
T10
T60
V30
Y10
Y36
Y60
BF40
J60

AW25

OMIT

XW1403

SHORT-20L-0.05MM-SM

ROOM=SOC

NO_XNET_CONNECTION

0.67V @TBDA MAX

21

ROOM=SOC

C1438

1UF

CERM
0402

1

BUCK2_PP_SOC_FB

ROOM=SOC

C1440

20%

4V

432

7.5UF

20%

4V

CERM
0402

1

432

18

ROOM=SOC

C1442

0.47UF

20%

6.3V
CERM
0402

1

432

D

C

B

A

432

432

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - POWER SUPPLIES

34567 8

2 1

DDR IMPEDANCE CONTROL

D

C

B

18 10 9 8 7

TBD-TBDV @1.9A MAX

PP0V9_SOC_FIXED

ROOM=SOC

C1502

4.3UF

20%

4V
CERM
0402

1

432

C1501

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

ROOM=SOC

C1527

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1503

7.5UF

20%

CERM
0402

1

0.797-0.945V @9 mA MAX

0.765-0.840V @60mA MAX

PP0V8_AOP

19

1

2

4V

432

C1504

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

AB30
AB34
AB38

AD58

AF25
AF30
AF34
AF38
AF62

AJ58
AL25
AL30
AL34
AL38
AL43
AL51
AL55

AL60
AR60
AU28
AU32
AU36
AU40
AU45
AU49
AU53
AU58

AU6
BA28
BA32
BA36
BA40
BA45
BA49
BA53
BA58

BH25
BH30
BH34
BH38
BH43
BH47
BH51
BH55

BK58

AW23

CC36
CE30
CE40

1.06-1.17V @0.85A MAX

18 15 7

PP1V1

CAYMAN-2GB-20NM-DDR-M

VDD_FIXED

VDD_FIXED_CPU

VDD_LOW

1

C1506

10UF

20%

6.3V
CERM-X5R

2

0402-9

ROOM=SOC

U0700

CSP

SYM 10 OF 16

1

C1528

10UF

20%

6.3V
CERM-X5R

2

0402-9

ROOM=SOC

VDD_FIXED

BK6
BM13
BM17
BM21
BM25
BM30
BM34
BM38
BM43
BM47
BM51
BP10
BP60
BW15
BW19
BW23
BW28
BW32
BW36
BW40
BW45
BW49
BW53
BW58
BW8
CC10
CC15
CC19
CC23
CC28
CC32
CC45
G32
G36
J17
J23
J55
J62
L10
L58
L60
T32
T58
T8
Y58
Y8

1

C1518

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1519

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1514

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1522

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

BE1

BJ1

BL1

BM8

BP6

BT8

BW6

CA8
CC6
CD1
CH1

BE67

BH60

BJ67

BK62

BL67

BM60

BP62
BT60

BW62

CD67
CH67

AB8
AC1
AE1
AH1

E1
K1

L6
P8
T6
V8
Y6

AB60
AC67
AD62

AE67
AH67

E67
K67
P60
T62
V60
Y62

VDDIO11_DDR0

VDDIO11_DDR1

VDDIO11_DDR2

VDDIO11_DDR3

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 11 OF 16

VDDIO11_PLL_DDR0
VDDIO11_PLL_DDR1
VDDIO11_PLL_DDR2
VDDIO11_PLL_DDR3

VDDIO11_RET_DDR0
VDDIO11_RET_DDR1
VDDIO11_RET_DDR2
VDDIO11_RET_DDR3

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

VDD2

18 15 7

CD3
BY64
K3
K65

BN2
AA66

CF3
CB65
K4
K64

CE8
BW60
J8
P58

CG3
CD65
H4
H64

CF4
CB64
H3
H65

AM3
AM65
BB3
BB65
BR1
BR67
BV1
BV67
BY1
BY67
C2
C66
CJ2
CJ66
CK2
CK66
D2
D66
N1
N67
R1
R67
W1
W67

PP1V1

1

R1501

240

1%
1/32W
MF

2

01005

ROOM=SOC

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

PMU_TO_AOP_SLEEP1_READY

1.06 - 1.17V @4mA MAX

PP1V1_DDR_PLL

1

C1508

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

(CURRENT INCLUDED IN VDD2)

1

C1509

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

PP1V1_SDRAM

SYSTEM_ALIVE

1.06 - 1.17V @1.74A MAX

C1512

1

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

1

2

21 20 17

C1513

10UF

20%

6.3V
CERM-X5R
0402-9

ROOM=SOC

1

R1502

240

1%
1/32W
MF

2

01005

ROOM=SOC

1

C1523

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

C1507

1

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

19 18 15

1

R1503

240

1%
1/32W
MF

2

01005

ROOM=SOC

20 13

1

2

1

R1504

240

1%
1/32W
MF

2

01005

ROOM=SOC

FL1501

100OHM-25%-0.12A

01005

C1510

0.22UF

20%

6.3V
X5R
01005-1

ROOM=SOC

C1529

1

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

1

2

R1505

1

240

1%
1/32W
MF
01005

2

ROOM=SOC

21

1

2

PP1V1

PP1V1_SDRAM

C1511

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

1

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

R1506

240

1%
1/32W
MF
01005

ROOM=SOC

C1515

2.2UF

D

18 15 7

C

19 18 15

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - POWER SUPPLIES

34567 8

2 1

D

C

B

A12
A16

A2
A20
A24
A27
A31
A35

A5
A52
A56
A59
A63
A66

A9

AA1
AA67
AB10
AB15
AB19
AB23
AB28
AB32
AB36
AB40
AB45
AB49
AB53
AB58

AB6
AB62

AC2

AC4

AC64
AC66
AD13
AD17
AD21
AD25
AD30
AD34
AD43
AD47
AD51
AD55
AD60

AD8
AF10
AF15
AF19
AF23
AF28
AF32
AF36
AF40
AF45
AF49
AF53
AF58

AF6
AG1
AG3

AG65
AG67

AJ21
AJ25
AJ30
AJ34
AJ38
AJ43

AL10

AJ51
AJ55

AJ8
AK1
AK2

AK66
AK67

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 13 OF 16

VSS VSS

AL23
AL28
AL32
AL36
AL40
AL45
AL53
AL58
AL62
AN13
AN17
AN21
AN25
AN30
AN34
AN38
AN43
AN47
AN51
AN55
AN60
AN8
AP1
AP4
AP64
AP67
AR10
AR15
AR19
AR28
AR32
AR36
AR40
AR45
AR49
AR53
AR58
AR6
AR62
AT1
AT3
AT65
AU13
AU17
AU21
AU25
AU30
AU34
AU38
AU43
AU47
AU51
AU55
AU60
AU8
AV1
AV2
AV4
AV64
AV66
AW10
AW15
AW19
CH50
AW28
AW32
AW36

AW40

AW45
AW49
AW53
AW58
AW6
AW62
AY1
AY4
AY64
AY67

B1

B3
B35
B41
B46
B52
B65
B67

BA13
BA17
BA21
BA30
BA34
BA38
BA43
BA47
BA51
BA55
BA60

BA8
BC1
BC2

BC66
BC67
BD10
BD23
BD28
BD32
BD36
BD40
BD45
BD49
BD53
BD58
BD62

BF21
BF25
BF30
BF34
BF43
BF47
BF51
BF55

BF8
BG1
BG3

BG65
BG67
BH10
BH15
BH19
BH23
BH28
BH32
BH36
BH40
BH45
BH49
BH53
BH58

BH6

BH62

BK13
BK17

AL49
BK25
BK30
BK34
BK38
BK43
BK47
BK51
BK55
BK60

BK8

BL2
BL4

BL64

U0700

CSP

SYM 14 OF 16

VSS VSS

BL66
BM10
BM15
BM19
BM23
BM28
BM32
BM36
BM40
BM45
BM49
BM53
BM58
BM6
BM62
BN1
BN67
BP13
BP17
BP21
BP25
BP30
BP34
BP38
BP43
BP47
BP51
BP55
BP8
BR3
BR65
BT10
BT15
BT19
BT23
BT28
BT32
BT36
BT40
BT45
BT49
BT53
BT58
BT6
BT62
BU1
BU67
BV2
BV4
BV64
BV66
BW13
BW17
BW21
BW25
BW30
BW34
BW38
BW43
BW47
BW51
CE51
BY65
C11
C14
C18
C22
C26
C29
C33
C35
C4
C52
C54
C57
C61
C64
C7
CA10

CA15
CA19
CA23
CA28
CA32
CA36
CA40
CA45
CA49
CA53
CA58

CA6

CA62

CB1

CB3
CB66
CB67

CC13
CC17
CC21
CC30
CC34
CC38
CC43

CL22

T30
CC8
CD2
CD4

CD64
CD66

CE10
CE15
CE47
CE53

CE6

CE62

CF1
CF2

CF64
CF65
CF66
CF67

CG1

CG11

CG2
CG24
CG27

CG4
CG42
CG44
CG46
CG48

CG5
CG52
CG54
CG56
CG59
CG61
CG64
CG65
CG66
CG67
CH12
CH18

CH2
CH24
CH27

CH3
CH33
CH39

CH4
CH42
CH44
CH46
CH48

CH5

U0700

CAYMAN-2GB-20NM-DDR-MCAYMAN-2GB-20NM-DDR-M

SYM 15 OF 16

VSSVSS

CH52
CH54
CH56
CH59
CH61
CH63
CH64
CH65
CH66
CH7
CH9
CJ1
CJ3
CJ4
CJ41
CJ42
CJ46
CJ5
CJ50
CJ54
CJ57
CJ61
CJ64
CJ65
CJ67
CK4
CK41
CK42
CK46
CK5
CK50
CK54
CK57
CK61
CK64
CL1
CL12
CL18
CL24
CL27
CL3
CL33
CL39
CL4
CL41
CL44
CL48
CL52
CL56
CL59
CL63
CL65
CL67
CL7
CM18
CM2
CM24
CM27
CM39
CM4
CM41
CM44
CM48
CM5
CM52
CM56
CM59
CM63
CM66
D1
D11
D12
D14
D16
D18

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

D20
D22
D24
D26
D27
D29

D3
D31
D35

D4
D41
D46

D5
D52
D56
D59
D63
D65
D67

D7

D9

E12
E14
E18

E2

E20
E22
E26
E27
E29

E3

E37

E4

E5

E54
E57
E59
E61
E64
E65
E66

E7

E9

F1
F2
F3

F4
F64
F65
F66
F67

G38
G43
G47
G51

G8

H1

H2
H66
H67

J10
J15
J19
J28
J32
J40
J45
J49
J53

J6

K2

K66

L13
L17
L21
L25
L30
L34

U0700

CAYMAN-2GB-20NM-DDR-M

CSPCSP

SYM 16 OF 16

VSSVSS

L38
L43
L47
L51
L55
L62
L8
M1
M2
M3
M4
M64
M65
M66
M67
P10
P15
P19
P23
P28
P32
P36
P40
P45
P49
P53
P6
P62
R2
R4
R64
R66
T13
T25
T34
T38
T51
T55
U1
U67
V10
V15
V28
V32
V36
V40
V53
V58
V6
V62
W3
W65
Y13
Y17
Y21
Y25
Y30
Y43
Y47
Y51
Y55
BF38
J58

47 41 40 37 36 32 21 20 18 16

29 25 18 17 13 12 11 9 8 7 5

47 41 40 37 36 32 21 20 18 16

19 10 8

PP1V2_SOC

53 52 48

52 48 47 46 39

53 52 48

19

C1604

2.2UF

X5R-CERM

ROOM=SOC

PP1V8_SDRAM

1.62-1.98V @43mA MAX

PP1V8

PP1V8_SDRAM

1

C1603

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

PP1V2_REF

R1602

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1601

0.00

0%

1/32W

MF

01005

ROOM=SOC

20%

6.3V

0201-1

1

2

1

C1615

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1602

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

1

C1605

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1607

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1.62-1.98V @10mA MAX

1

C1601

0.1UF

20%

6.3V
X5R-CERM

2

01005

ROOM=SOCROOM=SOC

1.62-1.98V @2mA MAX

1.62-1.98V @1mA MAX

1.62-1.98V @1mA MAX

TBD-TBDV @30mA MAX

C1611

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

VDD12_PLL_CPU:1.14-1.26V @13mA MAX

PP1V2_PLL_CPU

21

1

C1606

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

VDD12_PLL_SOC:1.14-1.26V @31mA MAX

PP1V2_PLL_SOC

21

1

C1609

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1608

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1610

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1612

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1614

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1613

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

AM1

AM67

BB1

BB67

C3

C65

CK3

CK65

AJ62
AN62
AU62
BA62

BF62

G40
G45
G49
G53

AD6

AJ6
AN6
BA6

BF6

CE19
CE23

CE28
CE32
CE34
CE36
CE43
CE38

AR23
BK19

AF21

J36

CE21

BF60

CG9

CC40

AU23

T28

Y38

BA25

Y32
AD36
AD38

Y34

CAYMAN-2GB-20NM-DDR-M

VDD1

VDDIO18_GRP1

VDDIO18_GRP2

VDDIO18_GRP3

VDDIO18_GRP4

VDDIO18_GRP10

VDD18_TSADC0
VDD18_TSADC1
VDD18_TSADC2
VDD18_TSADC3
VDD18_TSADC4
VDD18_TSADC5

VDD18_FMON

VDD18_LPOSC

VDD12_CPU_UVD
VDD12_GPU_UVD
VDD12_SOC_UVD

VDD12_PLL_CPU

VDD12_PLL_SOC

U0700

CSP

SYM 12 OF 16

CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND

VDD18_EFUSE1
VDD18_EFUSE2

D

CG7
G34

C

B

1.70-1.95V @134mA MAX

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

315mA MAX

PP1V8

1

C1701

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1739

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

R1703

24.9

1%

1/32W

MF

01005

ROOM=NAND

21

PP1V8_NAND_AVDD

17

1

C1741

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

NAND_AGND

1

C1707

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1743

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1726

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=NAND

1

C1729

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1745

1.0UF

20%

2

6.3V
X5R

0201-1

ROOM=NAND

1

C1710

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=NAND

1

C1730

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1747

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

17 8

17 8

PROBE POINTS

90_PCIE_AP_TO_NAND_REFCLK_P

90_PCIE_AP_TO_NAND_REFCLK_N

D

SM

1

1

PP1701

PP

P2MM-NSM

ROOM=NAND

SM

PP1702

PP

P2MM-NSM

ROOM=NAND

C

19

PP0V9_NAND

1007mA MAX

1

C1737

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1708

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1704

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1738

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1711

22PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C1702

15UF

20%

6.3V
X5R

2

0402-1

ROOM=NAND

1

C1740

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1717

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C1705

15UF

20%

6.3V
X5R

2

0402-1

ROOM=NAND

1

C1742

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1723

39PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

C1722

1

15UF

20%

6.3V

2

0402-1

ROOM=NAND

1

C1744

1.0UF

20%

6.3V

2

X5R
0201-1 0201-1

ROOM=NAND

1

C1712

2

C1727

1

15UF

20%

6.3V
X5RX5R

2

0402-1

ROOM=NAND

1

C1746

2

100PF

5%
16V
NP0-C0G
01005

ROOM=NAND

1.0UF

20%

6.3V
X5R

ROOM=NAND

#24543147:10uF for 32GB
#26326159:10uF for C1719

OMIT

1

C1748

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1713

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1716

15UF

20%

6.3V

2

X5R
0402-1

1

C1719

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=NANDROOM=NAND

1230mA MAX (1us peak power)

PP3V0_NAND

OMIT

1

C1721

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1733

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

C

B

C1703

1

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

C1706

1

22PF

5%
16V

2

CERM
01005

ROOM=NAND

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

1

R1704

3.01K

1%
1/32W
MF
01005

2

ROOM=NAND

C1709

1

100PF

5%

2

16V
NP0-C0G
01005

ROOM=NAND

PP1V8

C1714

1

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1724

0.01UF

10%

6.3V

2

X5R
01005

ROOM=NAND

C1725

1

0.01UF

10%

2

6.3V
X5R
01005

ROOM=NAND

11

17 8

17 8

C1720

1

100PF

5%

2

16V
NP0-C0G
01005

ROOM=NAND

C1728

1

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

AP_TO_NAND_SYS_CLK

90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_AP_TO_NAND_REFCLK_N

8

PCIE_NAND_BI_AP_CLKREQ_L

PCIE_NAND_RESREF

8

90_PCIE_AP_TO_NAND_TXD_P

8

90_PCIE_AP_TO_NAND_TXD_N

8

90_PCIE_NAND_TO_AP_RXD_P

8

90_PCIE_NAND_TO_AP_RXD_N

NAND_VREF

NC

NC

NC

NC

M4

PCI_AVDD_CLK1

D2

CLK_IN

H8

PCIE_REFCLK_P

H6

PCIE_REFCLK_M

G9

PCIE_CLKREQ*

M6

PCI_RESREF

M8

PCIE_RX0_P

K8

PCIE_RX0_M

N5

PCIE_RX1_P

N3

PCIE_RX1_M

P8

PCIE_TX0_P

N7

PCIE_TX0_M

M2

PCIE_TX1_P

K2

PCIE_TX1_M

K6

K4

J7

J5

PCI_VDD2

PCI_VDD1

PCI_AVDD_H

PCI_AVDD_CLK2

C3

AVDD1

E5

VREF

A5

R7

R3

J9

J1

F2

A7

A3

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDIO

U1701

THGBX6T1T82LFXF

VLGA

VER-1

ROOM=NAND

BOMOPTION=OMIT_TABLE

CRITICAL

OB10

OB0

VDDIO

VDDIO

OF10

OF0

VDDIO

VDDIO

R5

VDDIO

OA0

VCC

OD0

OA10

VCC

OD10

VCC

VCC

EXT_NWE

OG10

OG0

VCC

VCC

EXT_D0
EXT_D1
EXT_D2
EXT_D3
EXT_D4
EXT_D5
EXT_D6
EXT_D7

EXT_NCE

EXT_NRE

EXT_RNB

EXT_CLE

EXT_ALE

G3
J3
H2
E3
E7
F6
C7
B8

G1

F4

C5

G5

H4

D4

1

C1749

1.0UF 1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1715

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1750

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1718

22PF

5%
16V

2

CERM
01005

ROOM=NAND

PMU_TO_NAND_LOW_BATT_BOOT_L
AP_TO_NAND_FW_STRAP

NC

NC

NC

NC

NC

SYSTEM_ALIVE

PCIE_AP_TO_NAND_RESET_L

SWD_AP_BI_NAND_SWDIO_R

SWD_AP_NAND_SWCLK_R

NC

NC

1

C1751

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1731

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

2

ROOM=NAND

ROOM=NAND

1/32W 0%

1

C1752

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

C1732

39PF

5%
16V
NP0-C0G
01005

ROOM=NAND

20

12

21 20 15

8

0.00

0%

0.00

R1702

21

01005 MF1/32W

R1707

21

01005 MF

1

C1753

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1734

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C1754

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1735

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1736

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

SWD_AP_BI_NAND_SWDIO

SWD_AP_TO_MANY_SWCLK

B

13

53 36 13

A

F8

D8

D6

RESET*

TRST*

ZQ

SYNC_MASTER=Sync

PAGE TITLE

7

AP_TO_NAND_RESET_L

NC

NAND_ZQ

spare

1

R1701

34.8

0.5%
1/32W
MF
01005

ROOM=NAND

2

17

NAND_AGND

VSSA

B2

VSS

B4

VSS

B6

VSS

G7

OE10

VSS

L3

VSS

VSS

L5

VSS

L7

P2

VSS

P4

VSS

P6

VSS

OC0

8 7 5 4 2 1

VSS

OC10

VSS

OE0

VSS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

36

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

C

B

A

BUCK5

3.2A MAX

BUCK6

1.5A MAX

BUCK7

1.5A MAX

BUCK8

1.5A MAX

BUCK9

0.75A MAX

15 10 9 8 7

25

28 27 26 25 23 21 19 10 9 4

52 46 41 40 39 37 35 34 33 31

1

C1867

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

19

PP1V25_BUCK

14

PP_CPU_SRAM_VAR

0.80V - 1.06V

14

PP_GPU_SRAM_VAR

0.80V - 0.92V

PP2V8_UT_AF_VAR

53

1

C1840

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1811

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1868

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1869

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1870

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP_VDD_MAIN

1

C1875

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1876

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1801

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1846

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1847

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1848

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1803

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1804

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1805

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1806

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1862

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1850

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1851

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1852

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1877

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1807

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1808

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1809

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1810

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1863

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

19

VDD_MAIN_SNS

1

C1853

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1854

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1855

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1849

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

D10/D101:#24681501,TY ONLY, D11/D11: Both Vendor

CRITICAL

1

C1857

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1858

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1859

2.2UF

20%

6.3V

2

X5R-CERM

0201-1

ROOM=PMU

1

C1856

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

L1803

1.0UH-3.6A-0.06OHM

2 1

MEKK2016T-SM

NO_XNET_CONNECTION=1

ROOM=PMU

OMIT

BUCK5_LX0PP0V9_SOC_FIXED

XW1802

SHORT-20L-0.05MM-SM

CRITICAL

21

L1804

BUCK5_FB

NO_XNET_CONNECTION=1ROOM=SOC

1UH-20%-2.1A-0.12OHM

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

BUCK6_LX0

XW1807

SHORT-20L-0.05MM-SM

21

ROOM=SOC

CRITICAL

L1805

1.0UH-20%-2.25A-0.086OHM

2 1

MCFE2016T-SM

ROOM=PMU

OMIT

XW1803

SHORT-20L-0.05MM-SM

21

ROOM=SOC NO_XNET_CONNECTION=1

CRITICAL

L1801

1UH-20%-2.1A-0.12OHM

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

XW1801

SHORT-20L-0.05MM-SM

21

CRITICAL

ROOM=SOC

L1802

NO_XNET_CONNECTION=1

1.0UH-20%-1.5A-0.161OHM

21

0603

OMIT

XW1806

SHORT-20L-0.05MM-SM

21

ROOM=SOC NO_XNET_CONNECTION=1

BUCK6_FB

NO_XNET_CONNECTION=1

BUCK7_LX0

BUCK7_FB

BUCK8_LX0

BUCK8_FB

BUCK9_LX0

BUCK9_FB

VDD_MAIN_SNS

M8

VDD_MAIN

N7

VDD_MAIN_E

H6

VDD_MAIN_N

F11

VDD_MAIN_SW

R13

VDD_MAIN_W

H14

VDD_MAIN_W

H13

A5
B5

VDD_BUCK0_01

C5
D5

A9
B9

VDD_BUCK0_23

C9
D9

A17
B17

VDD_BUCK1_01

C17
D17

A13
B13

VDD_BUCK1_23

C13
D13

H1

VDD_BUCK2

H2
H3

T2

VDD_BUCK3

T3

M1

VDD_BUCK4

M2
M3

B1

VDD_BUCK5

C1
D1

K18

VDD_BUCK6

K19

U6

VDD_BUCK7

V6

F18

VDD_BUCK8

F19

L18

VDD_BUCK9

L19

B2
C2

BUCK5_LX0

D2
A2

BUCK5_FB

F5

J18

BUCK6_LX0

J19

BUCK6_FB

H16

U7

BUCK7_LX0

V7

BUCK7_FB

R8

G18

BUCK8_LX0

G19

BUCK8_FB

H15

M18

BUCK9_LX0

M19

BUCK9_FB

P16

U1801

D2333A1

WLCSP

SYM 2 OF 4

ROOM=PMU

BAT/USBBUCK INPUT

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

BUCK1_LX1

BUCK1_LX2

BUCK1_LX3

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

BUCK2_FB

BUCK3_LX0

BUCK3_FB

VBUCK3_SW

BUCK4_LX0

BUCK4_LX1

BUCK4_FB

VBUCK4_SW

BUCK3_SW1

BUCK3_SW2
BUCK3_SW3

SWITCH OUTPUTS

BUCK4_SW1

BUCK0_LX0

B4
C4
D4
A4

A6
B6
C6
D6

A8
B8
C8
D8

A10
B10
C10
D10

BUCK0_PP_CPU_FB

F10

B18
C18
D18
A18

A16
B16
C16
D16

A14
B14
C14
D14

A12
B12
C12
D12

BUCK1_PP_GPU_FB

F12

G1
G2
G3

J1
J2
J3

BUCK2_PP_SOC_FB

J5

R2
R3
R1
R7

U2
V2

N1
N2
N3

L1
L2
L3

K5

U5
V5

T1
U1

U3
V3

U4
V4

NO_XNET_CONNECTION=1

BUCK0_LX1

NO_XNET_CONNECTION=1

BUCK0_LX2

NO_XNET_CONNECTION=1

BUCK0_LX3

NO_XNET_CONNECTION=1

BUCK1_LX0

NO_XNET_CONNECTION=1

BUCK1_LX1

NO_XNET_CONNECTION=1

BUCK1_LX2

BUCK1_LX3

NO_XNET_CONNECTION=1

BUCK2_LX0

BUCK2_LX1

NO_XNET_CONNECTION=1

BUCK3_LX0

NO_XNET_CONNECTION=1

BUCK3_FB

NO_XNET_CONNECTION=1

BUCK4_LX0

NO_XNET_CONNECTION=1

BUCK4_LX1

NO_XNET_CONNECTION=1

BUCK4_FB

NO_XNET_CONNECTION=1 ROOM=SOC

L1806

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1807

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

CRITICAL

L1808

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

ROOM=PMU

CRITICAL

L1809

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

14

CRITICAL

L1810

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1811

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

CRITICAL

L1812

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

ROOM=PMUNO_XNET_CONNECTION=1

CRITICAL

L1813

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

14

CRITICAL

L1814

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1815

0.47UH-20%-3.8A-0.048OHM

2 1

PIQA20121T-SM

ROOM=PMU

14

L1816

CRITICAL

ROOM=PMU

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

OMIT

XW1804

SHORT-20L-0.05MM-SM

ROOM=SOC

CRITICAL

21

L1817

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1818

0.47UH-20%-3.8A-0.048OHM

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

XW1805

SHORT-20L-0.05MM-SM

21

PP1V8

PP1V8_TOUCH
PP1V8_MAGGIE_IMU

PP1V1

CRITICAL

36 24

15 7

Voltages per Cayman Power Spec, Sec. 2.2, rev 0.9.2, #24557869

PP_CPU_VAR

1

C1818

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1819

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1825

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1826

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1831

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1832

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1837

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1838

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1842

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1843

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1844

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1845

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

2

0.625V - 1.06V

C1872

220PF

5%
10V
C0G-CERM
01005

ROOM=PMU

PP_GPU_VAR

1

C1813

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1814

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1820

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1821

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1827

15UF

20%

6.3V

2

X5R

0402-1

ROOM=PMU

1

C1828

15UF

20%

6.3V

2

X5R

0402-1

ROOM=PMU

1

C1833

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1834

15UF

20% 20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1839

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1866

15UF

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1865

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1873

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

0.67V - 0.92V

1.03V for overdrive only

PP_SOC_VAR

0.67V/0.80V

1

C1822

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1829

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1835

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1841

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1864

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1871

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP1V8_SDRAM

1

C1816

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1823

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1860

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP1V1_SDRAM

1

C1830

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

52 48 47 46

39 29 25 17 16 13 12 11 9 8 7 5

1

C1836

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1802

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1874

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

SYNC_MASTER=Sync

PAGE TITLE

1

C1861

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

14

14

14

D

13.4A MAX

BUCK1

C

4.7A MAX13.4A MAX

BUCK2BUCK0

(pending vendor qual)

53 52 48 47

19 15

41 40 37 36 32 21 20 16

1.7A MAX

4.7A MAX

B

BUCK3 BUCK4

A

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

47 46 39 38

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

Apple Inc.

R

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36

D

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

VDD_MAIN_SNS

18

PMU_PRE_UVLO_DET

20

53 52

PP_VDD_MAIN

OMIT

XW1901

SHORT-20L-0.05MM-SM

21

ROOM=PMU

NO_XNET_CONNECTION

OMIT

XW1902

SHORT-20L-0.05MM-SM

21

ROOM=PMU

1

2

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 52

C1901

15UF

20%

6.3V
X5R
0402-1

ROOM=PMU

1

C1910

10UF

20%

6.3V

2

0402-9

ROOM=PMU

PP_VDD_MAIN

1

C1914

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1911

10UF

20%

6.3V

2

CERM-X5RCERM-X5R
0402-9

1

C1907

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMUROOM=PMU

34567 8

ADELYN LDO SPECS

LDO#

LDO1 (Ca)

LDO2 (Ca)

LDO3 (Ca)

LDO4 (D)

LDO5 (F)

LDO6 (Cb)

ADJ.RANGE, LOW

1.2-2.475V

1.2-2.475V

1.2-2.475V

0.7-1.2V

2.5-3.6V(tbc)

1.2-2.475V

LDO7 (Cb) 1.2-2.475V 2.4-3.675V +/-30mV 250mA

LDO8 (Cb)

LDO9 (Cb)

1.2-2.475V

1.2-2.475V

ADJ.RANGE, HI

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

ACCURACY

+/-1.4%

+/-2.5%

+/-2.5%

+/-75mV

+/-2.5%

+/-30mV

+/-25mV

MAX.CURRENT

50mA

50mA

50mA

60mA+/-2.5%

1000mA

250mA

(500/100mA in bypass)

250mA

250mA

LDO#

LDO11 (Cb)

LDO12 (E)

LDO13 (Cb)

LDO14 (Gb)

LDO15 (Ca)

LDO16 (Cb)

LDO17 (Ca)

LDO18 (Gb)

LDO19 (Gb)

2 1

ADJ.RANGE, LOW

1.2-2.475V

1.8V

1.2-2.475V

0.7-1.4V

1.2-2.475V

1.2-2.475V

1.2-2.475V

0.7-1.4V

0.7-1.4V

ADJ.RANGE, HI

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

ACCURACY

+/-30mV

+/-5%

+/-30mV

+/-3.0%

+/-2.5%

+/-30mV

+/-2.5%

+/-3.0%

+/-3.0%

MAX.CURRENT

250mA

10mA

250mA

400mA

50mA

250mA

50mA

400mA

400mA

D

C

B

A

U1801

D2333A1

WLCSP

SYM 4 OF 4

A1
A11
A15

H8
A19
P13

A3

P14

A7
B11
B15
B19

B3

B7
C11
C15
C19

C3

C7
D11
D15
D19

D3

D7

VSS VSS

E1
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19

E2

E3

E4

E5

E6

E7

E8

E9

F1

F17

F2
F3
F4

PP1V1_SDRAM

18 15

53 38 37 32 25 23

G17
G4
H17
H18
H19
H4
J17
J4
J8
K1
K17
K2
K3
K4
K8
L17
L4
L8
M17
M4
N17
N18
N19
N4
P1
P2
P3
P4
P15
R17
R4
T5
T15
T4
T6
T7
T8
U15
T13
U8
V1
V12
V19
V8

U15 = PMU XTAL GND

PP_VDD_BOOST

1

C1915

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1908

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

PP1V25_BUCK

18

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

PMU_VSS_RTC

1

C1912

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1913

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

20

53 52

PP_VDD_MAIN

NC

R12

VDD_LDO1

V11

VDD_LDO2_15

R10

VDD_LDO3_17

R16

VDD_LDO4

V9

VDD_LDO5

V10
R14

VDD_LDO6_BYP
VDD_LDO7_8

P19
R19

VDD_LDO9
VDD_LDO10

R9

VDD_LDO11_13

V13

VDD_LDO14

V16

VDD_LDO16

T19

VDD_LDO18

V17

VDD_LDO19

V18

VDD_LDO19

U19

VPP_OTP

G15

TP_DET

VPUMP: 10nF min. @4.6V

1

C1905

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PMU

U1801

D2333A1

WLCSP

SYM 1 OF 4

LDO INPUT

LDO

1

2

1

C1909

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PMU_VPUMP

C1902

47NF

20%

6.3V
X5R-CERM
01005

ROOM=PMU

VLDO1
VLDO2
VLDO3

VLDO4
VLDO5_0
VLDO5_1

VLDO6

VBYPASS

VLDO7

VLDO8

VLDO9

VLDO9_FB

VLDO10
VLDO11
VLDO12
VLDO13
VLDO14
VLDO15
VLDO16
VLDO17
VLDO18
VLDO19

VBUF_1V2

VPUMP

T12
U11
T10
T16
U9
U10
T14

R15

T17
P18
R18

P17

T9
U13
P7
U14
U16
U12
T18
T11
U17
U18

P8J6

R5

NC

NC

1

C1916

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

LDO10 (Ga)

1

C1918

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1921

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1933

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1

C1922

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1923

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1925

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1

C1926

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

+/-4.5%

1

C1927

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1935

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1150mA0.7-1.2V

LDO_RTC

BUF_1V2

2.5V

1.2V

PP3V3_USB

PP1V8_VA
PP3V0_ALS_APS_CONVOY

PP0V8_AOP

PP3V0_NAND

PP_ACC_VAR

PP3V0_TRISTAR_ANT_PROX
PP2V9_NH_AVDD
PP1V8_HAWKING

PP0V9_NAND

7

29 25

15

52 17

29

44

17

+/-2.0%

+/-5.0%

35 34 33 32

53 41 40 29

46 40 27

10mA

10mA

LDO1
LDO2
LDO3
LDO4
LDO5

LDO6

LDO7
LDO8
LDO9

LDO10

C

LDO11

PP1V8_ALWAYS

PP3V0_MESA

PP1V2_SOC

PP1V8_MESA

#24989262

PP_LDO17

PP1V2_UT_DVDD

PP1V2_NH_NV_DVDD

PP1V2_REF

1/20W

1%

2 1

R1901

0.00

21 20

38

48 38

MF

NOSTUFF

0201

25

29

16

LDO12
LDO13

16 10 8

LDO14
LDO15
LDO16
LDO17
LDO18
LDO19

VBUF_1V2

New for ADELYN

1

C1930

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

2

1

C1904

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

C1932

0.22UF

20%

6.3V
X5R
01005-1

ROOM=PMU

1

C1919

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

B

#24989262:OTP-AO LDO17 default off,50mA Iout_max

A

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36

34567 8

2 1

BUTTON PULL-UP RESISTORS

D

47 41 40 37 36 32 21 20 18 16

53 52 48

PP1V8_SDRAM

1

R2006

100K

5%
1/32W
MF
01005

2

ROOM=PMU

PP1V8_ALWAYS

1

R2005

100K

5%
1/32W
MF
01005

2

ROOM=PMU

D101/D111 ONLY: TCXO_RF Supplies 32K

1

R2012

10K

5%
1/32W
MF
01005

2

ROOM=PMU

NO_XNET_CONNECTION

1

C2001

1000PF

10%
10V

2

X5R
01005

ROOM=PMU

21 20 19

40

13 7

13

15 13

13

40 37 13 7

13

21 17 15

53 39 23 13

13

AP_TO_PMU_WDOG_RESET

7

TRISTAR_TO_PMU_HOST_RESET

AP_TO_PMU_SOCHOT_L

11

PMU_TO_SYSTEM_COLD_RESET_L

Active high with int 200k PD

AOP_TO_PMU_SLEEP1_REQUEST
PMU_TO_AOP_SLEEP1_READY
AOP_TO_PMU_ACTIVE_REQUEST
PMU_TO_AOP_TRISTAR_ACTIVE_READY

PMU_TO_AOP_CLK32K

SYSTEM_ALIVE
LCM_TO_MANY_BSYNC

HIGH=FORCE PWM MODE

PMU_TO_AOP_IRQ_L

NC

NC

NC

1

SM

PP

1

SM

PP

1

SM

PP

RESET_IN1

P9

RESET_IN2

P10

RESET_IN3

P11

RESET*

M5

SHDN

P12

SLEEP1_REQ

R11

SLEEP1_RDY

L11
L12

ACTIVE_REQ

J12

ACTIVE_RDY

SLEEP_32K

M9

OUT_32K

M10

SYS_ALIVE

H5

FORCE_SYNC

L13

CRASH*

L10

IRQ*

G5

PP2001

P2MM-NSM

ROOM=SOC

PP2002

P2MM-NSM

ROOM=SOC

PP2003

P2MM-NSM

ROOM=PMU

U1801

D2333A1

WLCSP

SYM 3 OF 4

REFS

RESETS

COMPARATORADC

IREF

VREF

PRE_UVLO*

VDROOP0*
VDROOP1*

VDROOP0_DET
VDROOP1_DET

PMU_IREF

K6

J7

PMU_VREF

1

C2006

0.22UF

20%

6.3V

2

X5R
0201

ROOM=PMU

PMU_TO_AP_PRE_UVLO_L

N10

G6

PMU_TO_AP_THROTTLE_CPU_L
PMU_TO_AP_THROTTLE_GPU_L

G7

F6

AP_VDD_CPU_SENSE

F7

AP_VDD_GPU_SENSE

1

R2011

200K

1%
1/20W
MF
201

2

ROOM=PMU

11

12

11

14

14

1

2

44 20

44 20

BUTTON_RINGER_A

BUTTON_POWER_KEY_L

PP1V8_SDRAM

NOSTUFF

1

R2015

220K

5%
1/32W
MF
01005

2

44 20

BUTTON_VOL_DOWN_L

NOTE:VDROOP_DET filtering is now inside Adelyn

ROOM=PMU

PP1V8_SDRAM

NOSTUFF

R2008

100K

5%
1/32W
MF
01005

ROOM=PMU

PP1V8_ALWAYS

NOSTUFF

1

R2007

220K

5%
1/32W
MF
01005

ROOM=PMU

2

53 52 48

47 41 40 37 36 32 21 20 18 16

D

21 20 19

53 52 48

47 41 40 37 36 32 21 20 18 16

C

B

C2007

100PF

NP0-C0G

ROOM=PMU

ROOM=PMU

ROOM=PMU

01005

C2008

100PF

NP0-C0G

01005

C2009

100PF

NP0-C0G

01005

5%

16V

5%

16V

5%

16V

FOREHEAD NTC

1

1

2

R2001

10KOHM-1%

01005

2

ROOM=PMU

REAR CAMERA NTC

1

1

R2002

10KOHM-1%

2

2

01005
ROOM=PMU

RADIO PA NTC

1

1

2

R2003

10KOHM-1%

01005
ROOM=PMU

2

FOREHEAD_NTC_RETURN

RCAM_NTC_RETURN

PA_NTC_RETURN

I2C1_AP_SDA

47

#24825674: Add R2020 to meet timing spec
#26169957: R2020 to 100ohm (D10x only)

OMIT

XW2002

SHORT-20L-0.05MM-SM

ROOM=SOC

XW2003

SHORT-20L-0.05MM-SM

ROOM=SOC

XW2004

SHORT-20L-0.05MM-SM

ROOM=SOC

XW2005

SHORT-20L-0.05MM-SM

ROOM=SOC

21

OMIT

21

OMIT

21

OMIT

21

R2020

100

5%

1/32W

MF

01005

ROOM=PMU

1

C2013

1000PF

10%
10V

2

X5R
01005

ROOM=PMU
PLACE_NEAR=U1801:2mm

21

TBD

47

11

11

11

20

44 12

39 37

40 20

36

53

53

27

53 20

53

I2C1_AP_SCL

I2C_PMU_SDA_R

SPI_PMGR_TO_PMU_SCLK
SPI_PMGR_TO_PMU_MOSI
SPI_PMU_TO_PMGR_MISO

AP_TO_PMU_AMUX_OUT

7

PMU_ADC_IN

BUTTON_VOL_UP_L

LCM_TO_CHESTNUT_PWR_EN
TRISTAR_TO_PMU_USB_BRICK_ID

PP1V2_MAGGIE
PMU_AMUX_AY

4

BBPMU_TO_PMU_AMUX1
BBPMU_TO_PMU_AMUX2

ACC_BUCK_TO_PMU_AMUX

PMUGPIO_TO_WLAN_CLK32K

CHESTNUT_TO_PMU_ADCMUX

37

AP_TO_PMU_TEST_CLKOUT

7

BBPMU_TO_PMU_AMUX3

PMU_AMUX_BY

4

FOREHEAD_NTC

REAR_CAMERA_NTC
RADIO_PA_NTC

AP_NTC

PMU_TCAL

PMU_XTAL1

PMU_XTAL2

PMU_VDD_RTC

1

C2002

0.22UF

20%

2

6.3V
X5R
0201

ROOM=PMU

NC

NC

NC

NC

N13
M13

N6
N5
P5

J14
J15

J16
K16
K15
K14

J13
K13
K12

L14
L15
L16

M16
M15
M14
N16
N15
N14

R6

M6

P6

L5
L6

G16

V14
V15

N9

SCL
SDA

SCLK
MOSI
MISO

AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_A4
AMUX_A5
AMUX_A6
AMUX_A7
AMUX_AY

AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_B4
AMUX_B5
AMUX_B6
AMUX_B7
AMUX_BY

TDEV1
TDEV2
TDEV3
TDEV4
TDEV5
TCAL

XTAL1
XTAL2

VDD_RTC

PRE_UVLO_DET

PMGR

AMUX

BUTTONS

NTCXTAL

GPIO

GPIO21 = I2C SCL is for Chestnut dark current mitigation RS = requires sequencer

IBAT

VBAT

BRICK_ID

ADC_IN

BUTTON1
BUTTON2
BUTTON3
BUTTON4

BUTTONO1
BUTTONO2
BUTTONO3

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

PMU_PRE_UVLO_DET

N8

L7

NC

M7

NC

H7

TRISTAR_TO_PMU_USB_BRICK_ID

PMU_ADC_IN

K7

M12

BUTTON_VOL_DOWN_L

N12

BUTTON_POWER_KEY_L

M11

BUTTON_RINGER_A

N11

H11
J11
K11

F16
F15
G14
F14
F13
G13
G12
H12
G11
G10
F9
G9
F8
G8
H9
H10
J9
J10
K9
K10
L9

Reserved for MENU key on dev board

NC

PMU_TO_AP_BUF_VOL_DOWN_L
PMU_TO_AP_BUF_POWER_KEY_L
PMU_TO_AP_BUF_RINGER_A

TIGRIS_TO_PMU_INT_L
BB_TO_PMU_PCIE_HOST_WAKE_L
PMU_TO_BBPMU_RESET_R_L
WLAN_TO_PMU_HOST_WAKE
NFC_TO_PMU_HOST_WAKE
PMU_TO_NAND_LOW_BATT_BOOT_L

NC_PMU_TO_GNSS_EN

PMUGPIO_TO_WLAN_CLK32K
PMU_TO_BT_REG_ON

NC_GNSS_TO_PMU_HOST_WAKE

PMU_TO_WLAN_REG_ON
BT_TO_PMU_HOST_WAKE
PMU_TO_CODEC_DIGLDO_PULLDN
PMU_TO_ACC_BUCK_SW_EN
PMU_TO_BB_USB_VBUS_DETECT
PMU_TO_NFC_EN

PMU_TO_BOOST_EN

PMU_TO_LCM_PANICB

PMU_TO_HOMER_RESET_L

I2C0_AP_SCL

19

20

12

12

12

40 20

44 20

44 20

44 20

21

53

53

53

17

53

53

53

32

27

53

53

23

39

36

37 47

Button for two-finger reset: 20711463 and 21196187

R2000

ROOM=PMU

53 20

#24511807: Stuff for Carrier

R2009

0.00

RS

RS

RS

Sequencer controllable

1/32W

01005

1.00K

1/32W

01005

0%

MF

5%

MF

C

21

PMU_TO_BBPMU_RESET_L

53

B

21

PMU_TO_AP_FORCE_DFUPMU_TO_AP_FORCE_DFU_R

12 4

A

AP NTC

1

C2010

100PF

NP0-C0G

ROOM=PMU

01005

5%

16V

1

2

R2004

10KOHM-1%

01005

ROOM=PMU

2

AP_NTC_RETURN

NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC

1

C2011

100PF 3.92K

5%
16V

2

NP0-C0G
01005

ROOM=PMU

1

R2010

0.1%
1/20W
MF
0201
ROOM=PMU

2

C2003

22PF

5%

16V

CERM

01005

ROOM=PMU

1

2

19

CRITICAL

32.768KHZ-20PPM-12.5PF

Y2001

21

1.60X1.00-SM

ROOM=PMU

PMU_VSS_RTC

1

C2004

22PF

5%
16V

2

CERM
01005

ROOM=PMU

XW2001

SHORT-20L-0.05MM-SM

ROOM=PMU

21

OMIT

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

TIGRIS CHARGER

34567 8

2 1

D

See Charger C2113 on Pg46

1

C2114

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=CHARGER

PP_VDD_MAIN

D

31 28 27 26 25 23 19 18 10 9 4

53 52 46 41 40 39 37 35 34 33

C

B

40 4

20 19

20

PP5V0_USB

PP1V8_ALWAYS

TIGRIS_TO_PMU_INT_L

USB_VBUS_DETECT

7

1

R2101

100K

5%
1/32W

MF

01005

2

ROOM=CHARGER

#24558610: Change to 100ohm

1

C2101

4.2UF

10%
16V

2

X5R-CERM
0402-1

ROOM=CHARGER

R2103

100

5%

1/32W

MF

01005

R2104

30.1K

1%

1/32W

MF

01005

TIGRIS_PMID

1

C2103

330PF

10%
16V

2

CER-X7R
01005

ROOM=CHARGER

1

C2110

330PF

10%
16V

2

CER-X7R
01005

F4: 100 kOhm pullup to VLDO (regulated output voltage)

21

ROOM=CHARGER

21

ROOM=CHARGER

1

2

ROOM=CHARGER

20 17 15

1

C2109

4.2UF

10%
16V
X5R-CERM
0402-1

ROOM=CHARGER

47

I2C1_AP_SDA
I2C1_AP_SCL

47

C2111

4.2UF

10%
16V

2

X5R-CERM
0402-1

ROOM=CHARGER

SYSTEM_ALIVE

TRISTAR_TO_TIGRIS_VBUS_OFF

40

TIGRIS_TO_PMU_INT_R_L

TIGRIS_VBUS_DETECT

1

C2112

330PF

10%
16V

2

CER-X7R
01005

ROOM=CHARGER

F5

PMID

A5

VBUS

B5

VBUS

D5

VBUS

C5

VBUS

E5

VBUS

G3

SDA

E4

SCL

E3

SYS_ALIVE

F4

VBUS_OVP_OFF

G2

INT

F1

VBUS_DET

F3

TEST

C2

D2

B2

A2

VDD_MAIN

VDD_MAIN

VDD_MAIN

VDD_MAIN

U2101

SN2400AB0

WCSP

ROOM=CHARGER

CRITICAL

PGND

PGND

PGND

PGND

B3

A3

D3

C3

LDO

BOOT

BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW

BAT
BAT
BAT
BAT

BAT_SNS

ACT_DIODE

HDQ_HOST

HDQ_GAUGE

G4

G5

A4
B4
D4
C4

A1
B1
D1
C1

E1

E2

G1
F2

TIGRIS_LDO

1

C2104

220PF

5%
10V

2

C0G-CERM
01005

ROOM=CHARGER

NO_XNET_CONNECTION

C2105

0.047UF

10%
16V
X5R

0201

21

TIGRIS_BOOT

ROOM=CHARGER

TIGRIS_BUCK_LX

VBATT_SENSE

TIGRIS_ACTIVE_DIODE

SWI_AP_BI_TIGRIS
TIGRIS_TO_BATTERY_SWI_1V8

1

C2115

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CHARGER

22

12

28

TO TRINITY

#25112685,Remove Snub

48 47 41 40 37 36 32 20 18 16

53 52

PP1V8_SDRAM

C2106

330PF

10%
16V

CER-X7R

ROOM=CHARGER

01005

1

2

ROOM=CHARGER

C2102

220PF

5%

10V

C0G-CERM

01005

NOSTUFF

R2102

100K

5%

1/32W

MF

ROOM=CHARGER

01005

C

B3

B2

B1

A3

A2

A1

G

1

D

2

1

2

1

2

C3

C2

C1

C2108

330PF

10%
16V
CER-X7R
01005

ROOM=CHARGER

CRITICAL

S

Q2101

CSD68827W

BGA

ROOM=CHARGER

PP_BATT_VCC

1

2

C2117

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=CHARGER

1

C2118

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CHARGER

22 4

B

1

R2105

40.2K

1%
1/32W
MF
01005

2

2

1

G

S

SYM_VER_1

Q2102

RV3C002UN

DFN

D

TIGRIS_TO_BATTERY_SWI

3

22

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

D

BATTERY CONNECTOR

516S00172 (matches d10 mlb MCO rev 27)THIS ONE ON MLB --->

C

TIGRIS_TO_BATTERY_SWI

21

R2201

100

21

5%

1/32W

MF

01005

ROOM=BATTERY_B2B

TIGRIS_BATTERY_SWI_CONN

1

C2201

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=BATTERY_B2B

RCPT-BATT-SHORT

J2201

F-ST-SM

1
3 2
4

ROOM=BATTERY_B2B

CRITICAL

ALLOW_APPLE_PREFIX

11
87

5

6

109
12

XW2201

SHORT-20L-0.05MM-SM

PLACE_NEAR=J2201:2mm

ROOM=BATTERY_B2B

NO_XNET_CONNECTION=1

21

VBATT_SENSE

1

C2202

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=BATTERY_B2B

21

1

C2203

100PF

5%
16V

2

NP0-C0G
01005

ROOM=BATTERY_B2B

PP_BATT_VCC

1

C2204

220PF

5%
10V

2

C0G-CERM
01005

ROOM=BATTERY_B2B

C

21 4

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

D

C

28 27 26 25 21 19 18 10 9 4

52 46 41 40 39 37 35 34 33 31

53

PP_VDD_MAIN

1

C2309

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=BOOST

1

C2301

4.7UF

20%

6.3V

2

X5R-CERM1
402

ROOM=BOOST

PMU_TO_BOOST_EN

20

1

R2301

511K

1%
1/32W
MF
01005

2

L2301

ROOM=BOOST

0.47UH-20%-4.2A-0.048OHM

21

PIUA20121T-SM

47

I2C0_AP_SCL

I2C0_AP_SDA

47

SYS_BOOST_LX

BOOST

A3

VIN

A4

C3
C4

A1

B2

C2

B1

C1

VIN

SW
SW

EN

SCL

SDA

VSEL

BYP*

U2301

SN61280D

DSBGA

ROOM=BOOST

VOUT
VOUT

B3
B4

1

C2302

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2303

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2304

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2307

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2308

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2306

220PF

5%
10V

2

C0G-CERM
01005

ROOM=BOOST

When VDD_MAIN < 3.4, boosts to 3.4
Otherwise tracks VDD_MAIN

PP_VDD_BOOST

53 38 37 32 25 19

C

B

53 39 20 13

LCM_TO_MANY_BSYNC

HIGH=FORCE PWM MODE

Control details from Radar 19634006

A2

GPIO

PGND

D3

D2

D4

AGND

D1

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

C

36 24 18

36 24 18

PP1V8_MAGGIE_IMU

13

PP1V8_MAGGIE_IMU

1

2

BOMOPTION=CARBON_1

1

R2401

100K

5%
1/32W
MF
01005

2

ROOM=SOC

SPI_AOP_TO_ACCEL_GYRO_CS_L

GYRO_CHARGE_PUMP

ACCEL_GYRO_TO_AOP_INT

13

BOMOPTION=CARBON_1

1

C2403

0.1UF

10%

6.3V

2

X6S
0201

ROOM=CARBON

CARBON - ACCEL & GYRO

C2418

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=CARBON

INVENSENSE, MPU-6800: C2403=0.1UF

BOMOPTION=CARBON_1

1

C2402

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CARBON

BOMOPTION=CARBON_1

1

C2415

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CARBON

16

VDD

1

BOMOPTION=CARBON_1

VDDIO

U2401

MPU-6900-21

LGA

5
8

14

7

CS
FSYNC
REGOUT

INT

GND

9

ROOM=CARBON

CRITICAL

GND

GND

12

11

10

GND

GND

13

SPC

SDI

SDO

DRDY

GND

15

BOMOPTION: CARBON_1
#25765850:Update Carbon APN

2

SPI_AOP_TO_IMU_SCLK_R1

3

SPI_AOP_TO_IMU_MOSI

4

SPI_IMU_TO_AOP_MISO

6

ACCEL_GYRO_TO_AOP_DATARDY

13

MAGNESIUM - COMPASS

D

PP1V8_MAGGIE_IMU_FILT

24

1

C2401

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=MAGNESIUM

24 13

PP1V8_MAGGIE_IMU_FILT

24 13

24 13

BOMOPTION=CARBON_1

1

C2419

5PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=CARBON

24

1

C2408

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAGNESIUM

NC

NC
NC

NC

NC

C2

B1
B3
D1
D2

D4

C4

VDD

U2402

HSCDTD601A-19A

VPP

RSV
RSV
RSV
RSV

RST*

ROOM=MAGNESIUM

LGA

114K INT PU

114K INT PD1.09M INT PU

CRITICAL

VSS

C1

SDO

SDA/SDI

SCL/SCK

CSB

TRG/SE

DRDY

B4

A4

A3

A2

C3

A1

NC

SPI_IMU_TO_AOP_MISO

SPI_AOP_TO_IMU_MOSI

SPI_AOP_TO_IMU_SCLK_R1

SPI_AOP_TO_COMPASS_CS_L

COMPASS_TO_AOP_INT

PP2404

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

PP2401

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

24 13

24 13

24 13

13

13

C

B

36 24 18

PP1V8_MAGGIE_IMU

PP1V8_MAGGIE_IMU_R

24

13

#25782019:Add 0ohm

R2404

0.00

0%

1/32W

MF

ROOM=BOT_CARBON

01005

1

R2441

100K

5%
1/32W
MF
01005

2

ROOM=SOC

SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L

BOT_GYRO_CHARGE_PUMP

PP1V8_MAGGIE_IMU_R

24

21

1

C2448

2.2UF

20%

6.3V

2

X5R-CERM X5R-CERM
0201-1

ROOM=BOT_CARBON

XW2404

SHORT-20L-0.05MM-SM

NC

ROOM=BOT_CARBON

1

C2443

0.1UF

10%

6.3V

2

X6S
0201

ROOM=BOT_CARBON

NO_XNET_CONNECTION=1

XW2404 to balance Via/Cu at INT pin

OMIT

1

C2442

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=BOT_CARBON

21

BOT_ACCEL_GYRO_TO_XW_INT

1

C2445

0.1UF

20%

6.3V

2

01005

ROOM=BOT_CARBON

5
8

14

7

VDD

CS
FSYNC
REGOUT

INT

GND

9

16

1

VDDIO

U2404

MPU-6900-21

LGA

ROOM=BOT_CARBON

CRITICAL

GND

GND

GND

13

12

11

10

GND

SPC

SDI

SDO

DRDY

GND

15

#25740540:PP for South Carbon MOSI

2

SPI_AOP_TO_IMU_SCLK_R2

3

SPI_AOP_TO_IMU_MOSI

4

SPI_IMU_TO_AOP_MISO

6

BOT_ACCEL_GYRO_TO_AOP_DATARDY

PP2402

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

PP2403

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

1

PP

24 13

24 13

PP2440

SM

P2MM-NSM

ROOM=HOMER

13

NOSTUFF

1

C2449

5PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=BOT_CARBON

13

B

A

PP1V8_MAGGIE_IMU_FILT

24

BOSCH: Internal PU

13

NOSTUFF

1

R2403

100K

5%
1/32W
MF
01005

2

ROOM=SOC

SPI_AOP_TO_IMU_MOSI

24 13

SPI_AOP_TO_IMU_SCLK_R1

24 13

SPI_AOP_TO_PHOSPHORUS_CS_L

24

PP1V8_MAGGIE_IMU_FILT

8

VDD VDDIO

U2403

BMP284AA

SDI SDO

4

SCK

2

CS*

LGA

GND

PHOSPHORUS

#24593845, #25691124

BOSCH (APN:338S00188): nostuff C2420/C2421/C2422/C2423 and R2403 PU

R2422

0.00

NOSTUFF

13

1

C2420

4PF

+/-0.1PF
16V

2

NP0-C0G

01005

ROOM=PHOSPHORUS

24 13

1

C2413

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=PHOSPHORUS

6

53

7

IRQ

1

PHOSPHORUS_TO_AOP_INT_L

1

C2405

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=PHOSPHORUS

SPI_IMU_TO_AOP_MISO

NOSTUFF NOSTUFF

1

C2421

20PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

1/32W

01005

ROOM=PHOSPHORUS

0%

MF

21

1

C2422

20PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

NOSTUFF

1

C2423

5.6PF

+/-0.1PF
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

1

C2414

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PHOSPHORUS

PP1V8_MAGGIE_IMU

SYNC_MASTER=Sync

PAGE TITLE

36 24 18

A

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36

34567 8

2 1

THIS PAGE UNIQUE TO SMALL FORM FACTOR

D

53 38 37 32 23 19

PP_VDD_BOOST

PP2V8_UT_AF_VAR

18

UTAH POWER

NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM

IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC.

VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY

U2501

LP5907UVX2.925-S

C2527

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=RCAM_B2B

B1

VIN

VEN

DSBGA

ROOM=RCAM_B2B

GND

B2

VOUT

A2A1

33-OHM-25%-1500MA

ROOM=RCAM_B2B

VOLTAGE=2.925V

See Page46: D10x C2531/C2507 are 2.2UF

FL2500

0201

IO FILTERS

TI:353S00015
ST:353S00889

FL2504

150OHM-25%-200MA-0.7DCR

1

C2502

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=RCAM_B2B

PP2V9_UT_AVDD_CONN

C2504

1

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

AP_TO_UT_CLK

46 45

9

NOSTUFF

1

C2512

100PF

5%
16V

2

NP0-C0G
01005

ROOM=RCAM_B2B

01005

ROOM=RCAM_B2B

21

C2513

1

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=RCAM_B2B

AP_TO_UT_CLK_CONN

45

FL2501

21

C2505

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=RCAM_B2B

PP2V8_UT_AF_VAR_CONN

C2501

1

220PF

5%

2

10V
C0G-CERM
01005

ROOM=RCAM_B2B

45 9

AP_TO_UT_SHUTDOWN_L

150OHM-25%-200MA-0.7DCR

21

01005

ROOM=RCAM_B2B

1

C2514

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

AP_TO_UT_SHUTDOWN_CONN_L

45

D

C

29 19

19

29 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39

PP3V0_ALS_APS_CONVOY

PP1V2_UT_DVDD

PP1V8

FL2502

33-OHM-25%-1500MA

21

ROOM=RCAM_B2B

0201

FL2505

33-OHM-25%-1500MA

21

ROOM=RCAM_B2B

0201

FL2506

33-OHM-25%-1500MA

21

0201

ROOM=RCAM_B2B

1

C2506

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

1

C2519

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

1

C2508

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

ROOM=RCAM_B2B

1

C2510

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

1

C2509

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=RCAM_B2B

PP3V0_UT_SVDD_CONN

1

C2518

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

PP1V2_UT_VDD_CONN

1

C2503

220PF

5%
10V
C0G-CERM

2

01005

ROOM=RCAM_B2B

1

C2521

15PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=RCAM_B2B

PP1V8_UT_CONN

1

C2511

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

45

45

Desense for Wifi frequencies

45

UT_AND_NV_TO_STROBE_DRIVER_STROBE

26 45

28 27 26 23 21 19 18 10 9 4

52 46 41 40 39 37 35 34 33 31

53

LPDP FILTERS

PP_VDD_MAIN

1

C2522

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=RCAM_B2B

1

C2528

33PF

5%

2

16V
NP0-C0G-CERM
01005

ROOM=RCAM_B2B

FL2503

150OHM-25%-200MA-0.7DCR

21

01005

ROOM=RCAM_B2B

1

C2529

33PF

5%

2

16V
NP0-C0G-CERM
01005

ROOM=RCAM_B2B

1

C2515

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN

C

B

AC return path for LPDP which is referenced to GND and VDD_MAIN

90_LPDP_UT_TO_AP_D0_P

10

90_LPDP_UT_TO_AP_D0_N

10

90_LPDP_UT_TO_AP_D1_P

10

90_LPDP_UT_TO_AP_D1_N

10

LPDP_UT_BI_AP_AUX

10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

90_LPDP_UT_TO_AP_D0_P

90_LPDP_UT_TO_AP_D0_N

90_LPDP_UT_TO_AP_D1_P

90_LPDP_UT_TO_AP_D1_N

LPDP_UT_BI_AP_AUX

C2530

0.1UF

21

20%

6.3V

X5R-CERM

01005

ROOM=RCAM_B2B

C2523

ROOM=RCAM_B2B

X5R-CERM

C2524

ROOM=RCAM_B2B

X5R-CERM

C2525

ROOM=RCAM_B2B

X5R-CERM

C2526

ROOM=RCAM_B2B

X5R-CERM

20%

20%

21

6.3V20%
01005

21

6.3V20%
01005

21

6.3V

01005

21

6.3V

01005

1

C2520

56PF

5%
25V

2

NP0-C0G-CERM

01005

ROOM=RCAM_B2B

0.1UF

0.1UF

0.1UF

0.1UF

90_LPDP_UT_TO_AP_D0_CONN_P

90_LPDP_UT_TO_AP_D0_CONN_N

90_LPDP_UT_TO_AP_D1_CONN_P

90_LPDP_UT_TO_AP_D1_CONN_N

LPDP_UT_BI_AP_AUX_CONN

#24543254: Need to Scrub C2520 Value

B

45

45

45

45

45

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

STROBE DRIVERS INSIDE NEO SIP MODULE

D10/sip_neo

34567 8

2 1

D

AP_TO_STROBE_DRIVER_HWEN

9

UT_AND_NV_TO_STROBE_DRIVER_STROBE

25

BB_TO_STROBE_DRIVER_GSM_BURST_IND

53 37

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 52

ROOM=STROBE

PP_VDD_MAIN

C2609

10UF

CERM-X5R

0402-9

1

20%

6.3V

2

I2C_ISP_UT_SDA

48

I2C_ISP_UT_SCL

48

C2610

10UF

20%

6.3V

CERM-X5R

0402-9

ROOM=STROBE

M2600

D

NEO

SIP

5%

10V

1

B8

VDD

2

D2
D3

C9

C8

D8

B9

B10

VDD
VDD

HWEN1

STB1

GSM1

SDA1

SCL1

SYM 1 OF 3

ROOM=STROBE

CRITICAL

LED1
LED1

LED2
LED2

NTC

D9
D10

D6
D7

C10

PP_STROBE_DRIVER1_COOL_LED

PP_STROBE_DRIVER1_WARM_LED

45 44

45 44

STROBE_MODULE_NTC

44

1

C2613

220PF

2

C0G-CERM

01005

ROOM=STROBE

C

B

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 52

C2611

ROOM=STROBE2

PP_VDD_MAIN

1

10UF

20%

6.3V

CERM-X5R

0402-9

2

ROOM=STROBE2

I2C_ISP_NV_SDA

46

I2C_ISP_NV_SCL

46

C2612

10UF

20%

6.3V

CERM-X5R

0402-9

46 41 40 39 37 35 34 33 31 28

5%

10V

1

2

53 52

1

C2614

220PF

2

27 26 25 23 21 19 18 10 9 4

C0G-CERM

01005

ROOM=STROBE

VDD

B18

VDD

B19

VDD

D13

HWEN0

C12

STB0

C13

GSM0

B13

SDA2

D12

SCL2

D11

PP_VDD_MAIN

M2600

NEO

SIP

SYM 2 OF 3

LED1
LED1

LED2
LED2

1

C2617

220PF

5%
10V

2

C0G-CERM
01005

ROOM=STROBE2

AC return path for plane edge termination, which occurs near the Strobe modules.

NTC

B11
B12

B14
B15

C11

1

C2618

220PF

5%
10V

2

C0G-CERM
01005

ROOM=STROBE2

PP_STROBE_DRIVER2_COOL_LED

PP_STROBE_DRIVER2_WARM_LED

45 44

45 44

A2
A3
A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20

B2

B3

B4

B5

B6

B7
B16
B17
B20

C1

C2

C3

C4

C5

C6

C7

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

M2600

NEO

SIP

SYM 3 OF 3

GND1

GND1S

GND2

GND2S

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C14
C15
C16
C17
C18
C19
C20
D1
D4
D5
D14
D15
D16
D17
D18
D19
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19

C

B

A

B1

A1

SYNC_MASTER=Sync

PAGE TITLE

E20

D20

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

D

ACCESSORY BUCK

#25761020:Add Bypass 0ohm

NOSTUFF

R2711

0.00

1/20W

0201

ROOM=ACC_BUCK

21

1%

MF

34567 8

2 1

D

From PMU LDO6

C

28 26 25 23 21 19 18 10 9 4

52 46 41 40 39 37 35 34 33 31

53

20

From PMU GPIO14

PP_VDD_MAIN

PMU_TO_ACC_BUCK_SW_EN

1

R2700

100K

5%
1/32W
MF
01005

2

ROOM=ACC_BUCK

AP_TO_ACC_BUCK_VSEL

12

From AP GPIO1

B2

1

R2710

100K

1%
1/32W
MF
01005

2

ROOM=ACC_BUCK

U2710

FPF1204UCX

WLCSP-COMBO

VIN

ON

ROOM=ACC_BUCK

GND

B1

VOUT

A1A2

1

R2701

100K

5%
1/32W
MF
01005

2

ROOM=ACC_BUCK

C2700

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=ACC_BUCK

PP_VDD_MAIN_ACC_BUCK_VIN

ACC_BUCK_EN

1

C2710

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=ACC_BUCK

B2

A1

A2

U2700

FAN53612-1.5V-1.9V

WLCSP

C2

B1

ACC_BUCK_SW

C1

ACC_BUCK_FB

CRITICAL

L2700

0.47UH-20%-2.52A-0.08OHM

21

PIGA1608-SM

ROOM=ACC_BUCK

27

R2705

ROOM=ACC_BUCK

ACC_BUCK_TO_PMU_AMUX

20

PMU_AMUX_B3 FOR NOW

10K

5%

1/32W

MF

01005

1

C2705

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=PMU

K

D2700

SOD962-2

PMEG3002ESF

ROOM=ACC_BUCK

A

1

C2704

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=PMU

FET Changes per #25687842 4/12/2016

Q2700

PMCM4401VPE

#25370332: For EMC

#25919133: C2707 on P46

VOLTAGE=1.9V

1

C2702

10UF

20%

6.3V

2

CERM-X5R
0402-9

1

2

ROOM=ACC_BUCK

1

C2703

220PF

5%
10V

2

C0G-CERM
01005

ROOM=ACC_BUCK

1

C2701

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=ACC_BUCK

#25172498

PP_ACC_BUCK_VAR

ACC_BUCK_FB

27

1

R2702

200K

0.1%
1/32W
TF
01005

2

ROOM=ACC_BUCK

ACT_DIODE_TO_COMP_POS

OMIT

XW2700

SHORT-20L-0.05MM-SM

21

ROOM=ACC_BUCK

NO_XNET_CONNECTION=1

PLACE_NEAR=Q2700:2mm

B1

PMCM4401VPE

B1

ACT_DIODE_TO_COMP_OUT

WLCSP

D

G

ROOM=TRISTAR

A1

Q2701

WLCSP

D

G

ROOM=TRISTAR

A1

A2

S

B2

To Tristar on Pg40

C

PP_ACC_VAR

1

C2708

4UF

20%

6.3V

2

2

OMIT

XW2707

A2

S

B2

SHORT-20L-0.05MM-SM

ROOM=TRISTAR
NO_XNET_CONNECTION=1

1

ACT_DIODE_TO_COMP_SENSE

1

R2704

200K

0.1%
1/32W
TF
01005

2

ROOM=ACC_BUCK

#25741319: Change to 4UF

CER-X5R
0201

ROOM=TRISTAR

46 40 27 19

B

46 40 27 19

ACT_DIODE_TO_COMP_NEG

1

R2706

200K

0.1%
1/32W
TF
01005

2

ROOM=ACC_BUCK

PP_ACC_VAR

C2706

0.22UF

10%

6.3V

CER-X5R

01005

ROOM=ACC_BUCK

1

5

2

VCC

U2701

SCY992200A

4

IN+

3

IN-

UDFN

VEE

1

NC

6

2

NC

VOUT

ROOM=ACC_BUCK

#26434500: Divider to all 200kohm,0.1%
#25987909: To Resistor Divider

1

R2703

200K

0.1%
1/32W
TF
01005

2

ROOM=ACC_BUCK

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2

THIS PAGE UNIQUE TO SMALL FORM FACTOR

D

D

C

B

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 52

M2800

TRINITY

SIP

SYM 1 OF 5

PP_VDD_MAIN PP_VDD_MAIN BL_SW1_LX

D5

VDD TIG

D6

VDD

TIG

B5

TIGRIS_BUCK_LX

B6

21

27 26 25 23 21 19 18 10 9 4 37

46 41 40 39 37 35 34 33 31 28

53 52

D2
D3

F2
G2
H2

J2

VDD
VDD
VDD
VDD
VDD
VDD

M2800

TRINITY

SIP

SYM 4 OF 5

BL1
BL1
BL1
BL1

BL2
BL2

F6
G6
H6
J6

B2
B3

BL_SW2_LX

M2800

TRINITY

SIP

SYM 2 OF 5

L2

VDD ARC

L3

VDD

ARC

N2
N3

ARC1_LX

35

M2800

TRINITY

SIP

L5
L6

N5

SPEAKERAMP1_LX

N6

34

37

A3
A4
A5
A6
A7
B1
B4

B7
C1
C2
C3
C4
C5
C6
C7
D1
D4
D7

E1

E2

E3

E4

E5

E6

E7

F1

F3

F4

F5

F7
G1
G3
G4
G5
G7

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

M2800

TRINITY

SIP

SYM 5 OF 5

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

H1
H3
H4
H5
H7
J1
J3
J4
J5
J7
K1
K2
K3
K4
K5
K6
K7
L1
L4
L7
M1
M2
M3
M4
M5
M6
M7
N1
N4
N7
P1
P2
P3
P4
P5

C

B

A

GND1

GND1S

GND2

GND2S

P6

P7

A2

A1

SYNC_MASTER=Sync

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

spare

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

13 12 11 9 8 7 5
48 47 46 39 25 18

19

19

NEW HAMPSHIRE POWER

FL2901

33-OHM-25%-1500MA

PP1V8

0201

ROOM=FOREHEAD

FL2902

33-OHM-25%-1500MA

PP1V2_NH_NV_DVDD

0201

ROOM=FOREHEAD

FL2903

10-OHM-750MA

PP2V9_NH_AVDD

01005-1

ROOM=FOREHEAD

21

21

1

2

21

1

2

C2916

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=FOREHEAD

C2909

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=FOREHEAD

1

C2914

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=FOREHEAD

1

C2915

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=FOREHEAD

1

C2901

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=FOREHEAD

PP1V8_NH_IO_CONN

1

C2902

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

PP1V2_NH_DVDD_CONN

1

C2903

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

PP2V9_NH_AVDD_CONN

1

C2904

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

45

45

45

25 19

53 41 40 19

PROX, ALS, & CONVOY POWER

FL2913

150OHM-25%-200MA-0.7DCR

PP3V0_ALS_APS_CONVOY

150OHM-25%-200MA-0.7DCR

PP3V0_TRISTAR_ANT_PROX

01005

ROOM=FOREHEAD

FL2910

01005

ROOM=FOREHEAD

21

1

C2917

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=FOREHEAD

21

#24511567: Remove C2918

PP3V0_ALS_CONVOY_CONN

PP3V0_PROX_CONN

1

C2927

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=FOREHEAD

45

1

C2926

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

1

C2908

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

D

C

B

NEW HAMPSHIRE I/O

FL2907

150OHM-25%-200MA-0.7DCR

AP_TO_NH_CLK

9

01005

ROOM=FOREHEAD

FL2908

150OHM-25%-200MA-0.7DCR

9

01005

ROOM=FOREHEAD

CONVOY I/O

#25657495: Update FL2905 to 100ohm

R2905

100

5%

1/32W

MF

01005

ROOM=FOREHEAD

FL2906

150OHM-25%-200MA-0.7DCR

PDM_CONVOY_TO_ADARE_DATA

33

01005

ROOM=FOREHEAD

PROX/ALS I/O

21

1

C2910

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=FOREHEAD

21

1

C2911

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

21

21

#25170697: R2915 to 240ohm/C2921 to 220pF

PDM_ADARE_TO_CONVOY_CLK_CONNPDM_ADARE_TO_CONVOY_CLK

1

C2905

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=FOREHEAD

PDM_CONVOY_TO_ADARE_DATA_CONN

1

C2906

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=FOREHEAD

NO_XNET_CONNECTION=1

1

C2932

220PF

SPEAKER2

AP_TO_NH_CLK_CONN

AP_TO_NH_SHUTDOWN_CONN_LAP_TO_NH_SHUTDOWN_L

45

46 45 33

SPEAKERAMP2_TO_SPEAKER_OUT_POS

SPEAKERAMP2_TO_SPEAKER_OUT_NEG

NO_XNET_CONNECTION=1

C2931

220PF

C0G-CERM

ROOM=FOREHEAD

01005

5%

10V

1

2

1

2

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

NO_XNET_CONNECTION=1

C2935

220PF

5%
10V
C0G-CERM
01005

ROOM=FOREHEAD

C

46 45 33

R2903

SPEAKER_TO_SPEAKERAMP2_VSENSE_P

33

45 33

SPEAKER_TO_SPEAKERAMP2_VSENSE_N

33

45

MIC3

FL2914

0.00

1/32W

01005

ROOM=FOREHEAD

R2904

0.00

1/32W

01005

ROOM=FOREHEAD

150OHM-25%-200MA-0.7DCR

PP_CODEC_TO_FRONTMIC3_BIAS

32

01005

ROOM=FOREHEAD

0%

MF

0%

MF

21

21

21

SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P

NO_XNET_CONNECTION=1

1

C2933

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N

NO_XNET_CONNECTION=1

1

C2934

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

PP_CODEC_TO_FRONTMIC3_BIAS_CONN

1

DZ2905

6.8V-100PF

01005

ROOM=FOREHEAD

2

45

45

B

45

A

R2915

PROX_BI_AP_AOP_INT_PWM_L

13 12

21

1%

1/32W

MF

01005

ROOM=FOREHEAD

PROX_BI_AP_AOP_INT_PWM_L_CONN

1

C2921

220PF

5%
10V

2

C0G-CERM
01005

ROOM=FOREHEAD

240

FL2911

150OHM-25%-200MA-0.7DCR

ALS_TO_AP_INT_L ALS_TO_AP_INT_CONN_L

12 45

2 1

01005

ROOM=FOREHEAD

1

C2924

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=FOREHEAD

45

FRONTMIC3_TO_CODEC_AIN4_N

31

FRONTMIC3_TO_CODEC_AIN4_P

31

FL2904

150OHM-25%-200MA-0.7DCR

21

01005

ROOM=FOREHEAD

1

2

FL2909

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=FOREHEAD

1

2

NO_XNET_CONNECTION=1

FRONTMIC3_TO_CODEC_AIN4_CONN_N

DZ2906

6.8V-100PF

01005

ROOM=FOREHEAD

NO_XNET_CONNECTION=1

FRONTMIC3_TO_CODEC_AIN4_CONN_P

DZ2907

6.8V-100PF

01005

ROOM=FOREHEAD

45

45

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

CALTRA AUDIO CODEC (ANALOG INPUTS & OUTPUTS)

34567 8

2 1

D

LOWERMIC1_TO_CODEC_AIN1_P

41

LOWERMIC1_TO_CODEC_AIN1_N

41

LOWERMIC4_TO_CODEC_AIN2_P

41

LOWERMIC4_TO_CODEC_AIN2_N

41

REARMIC2_TO_CODEC_AIN3_P

44

REARMIC2_TO_CODEC_AIN3_N

44

L2
L1

K3

L3

K2
K1

AIN1+
AIN1-

AIN2+
AIN2-

AIN3+
AIN3-

CRITICAL

ROOM=CODEC

U3101

WLCSP-1

SYM 1 OF 3

CS42L71

AOUT1+

AOUT1-

AOUT2+

AOUT2-

HPOUTA
HPOUTB

HS3

HS4

HS3_REF
HS4_REF

L9
M9

L8
M8

K10
K11

M5

M4

L10
M10

NC
NC

NC

NC

NC
NC

D

WAS FOR RECEIVER; REPLACED BY SPEAKER IN D1xy

C

For Borealis

HAWKING_TO_CODEC_AIN7_P

44

HAWKING_TO_CODEC_AIN7_N

44

FRONTMIC3_TO_CODEC_AIN4_P

29

FRONTMIC3_TO_CODEC_AIN4_N

29

NC

NC

NC

NC

NC

NC

AIN4+

J3

AIN4-

J4

AIN5+

F1

AIN5-

G1

AIN6+

F2

AIN6-

F3

AIN7+

G2

AIN7-

G3

DMIC1_CLK

A4

DMIC1_DATA

B4

HSIN+

HSIN-

HPDETECT

DP

DN

J9

D1
E1

J12
H12

NC
NC

NC

90_MIKEYBUS_CALTRA_DATA_P
90_MIKEYBUS_CALTRA_DATA_N

R3104

20.0

5%

1/32W

MF

01005

ROOM=CODEC

C

ROOM=CODEC

C3107

100PF

21

5%

16V

NP0-C0G

01005

21

90_MIKEYBUS_DATA_P

40

B

PDM_CODEC_TO_SPKAMP2_CLK

33

PDM_CODEC_TO_SPKAMP2_DATA

33

NC

NC

NC

NC

NC

DMIC2_CLK

C4

DMIC2_DATA

C3

DMIC3_CLK

A3

DMIC3_DATA

B3

DMIC4_CLK

A2

DMIC4_DATA

B2

PDM_CLK

A9

PDM_DATA

B9

MBUS_REF

G10

MIKEYBUS_REFERENCE

1

R3101

100

5%
1/32W
MF
01005

2

ROOM=CODEC

41

R3103

20.0

5%

1/32W

MF

01005

ROOM=CODEC

21

C3106

100PF

21

5%

16V

NP0-C0G

01005

ROOM=CODEC

90_MIKEYBUS_DATA_N

40

B

A

53

27 26 25 23 21 19 18 10 9 4

52 46 41 40 39 37 35 34 33 28

PP_VDD_MAIN

1

C3112

220PF

5%

2

10V
C0G-CERM
01005

ROOM=CODEC

1

C3113

220PF

5%

2

10V
C0G-CERM
01005

ROOM=CODEC

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

AC return path for Mikeybus which is referenced to GND and VDD_MAIN

Radar 21203307

8 7 5 4 2 1

36

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

R

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

CALTRA AUDIO CODEC (POWER & I/O)

34567 8

2 1

D

C

47 41 40 37 36 32 21 20 18 16

LOWERMIC1_TO_CODEC_BIAS_FILT_RET

41

LOWERMIC4_TO_CODEC_BIAS_FILT_RET

41

REARMIC2_TO_CODEC_BIAS_FILT_RET

45

35 34 33 19

53 38 37 25 23 19

53 52 48

PP1V8_VA

PP_VDD_BOOST

PP1V8_SDRAM

C3203

4.7UF

21

20%

6.3V

X5R-CERM1

402

ROOM=CODEC

41

C3204

4.7UF

21

20%

6.3V

X5R-CERM1

402

ROOM=CODEC

41

C3201

4.7UF

21

44

1

C3209

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CODEC

CODEC_AGND

1

C3211

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=CODEC

1

C3212

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

1

C3213

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

32

1

2

1

2

PP_CODEC_TO_LOWERMIC1_BIAS
LOWERMIC1_BIAS_FILT_IN

PP_CODEC_TO_LOWERMIC4_BIAS
LOWERMIC4_BIAS_FILT_IN

PP_CODEC_TO_REARMIC2_BIAS
REARMIC2_BIAS_FILT_IN

C3214

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=CODEC

C3215

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=CODEC

1

C3205

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CODEC

PP1V2_VD_FILT

1

C3217

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=CODEC

1

C3221

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=CODEC

J11

VCP

MIC1_BIAS

M6

MIC1_BIAS_FILT

K7

MIC2_BIAS

L6

MIC2_BIAS_FILT

J7

MIC3_BIAS

K6

MIC3_BIAS_FILT

L5

D12

VD

G12

VD

E12

C1

VD_FILT

VD_FILT

U3101

WLCSP-1

SYM 2 OF 3

CS42L71

ROOM=CODEC

CRITICAL

A5

VL

H11

M7

VP

VPROG_CP

J1

VA

H10

VP_MBUS

FLYP

FLYC

K12

L12

NC

NC

47 41 40 37 36 32 21 20 18 16

SPI_AP_TO_CODEC_CS_L

11

53 52 48

R3202

ROOM=CODEC

PP1V8_SDRAM

1

100K

5%

1/32W

MF

01005

2

35 34 33 13

36 35 34 33 11

36 35 34 33 11

36 35 34 33

36 35 34 33

1

R3201

1.00K

5%
1/32W
MF
01005

2

ROOM=CODEC

CODEC_RESET_L

AUDIO_TO_AOP_INT_L

SPI_AP_TO_CODEC_MAGGIE_SCLK

36 11

SPI_AP_TO_CODEC_MAGGIE_MOSI

36 11

SPI_CODEC_MAGGIE_TO_AP_MISO

36 11

I2S_AP_TO_CODEC_MCLK

11

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
I2S_MAGGIE_TO_L26_CODEC_DOUT

I2S_L26_CODEC_TO_MAGGIE_DIN

I2S_CODEC_XSP_TO_AOP_BCLK

13

I2S_CODEC_XSP_TO_AOP_LRCLK

13

I2S_AOP_TO_CODEC_XSP_DOUT

13

I2S_CODEC_XSP_TO_AOP_DIN

13

NC

H3

RESET*

K8

WAKE*

K9

INT*

C9

CS*

C8

CCLK

MOSI

B8
A8

MISO

C12

MCLK

C6

ASP_SCLK

C5

ASP_LRCK/FSYNC

B5

ASP_SDIN

B6

ASP_SDOUT

XSP_SCLK

B11

XSP_LRCK/FSYNC

C11

XSP_SDIN/DAC2B_MUTE

A11

XSP_SDOUT

A10

U3101

WLCSP-1

SYM 3 OF 3

CS42L71

ROOM=CODEC

CRITICAL

JTAG_TMS

JTAG_TCK

JTAG_TDI

JTAG_TDO

TSTO
TSTO
TSTO
TSTO
TSTO
TSTO
TSTO
TSTO

TSTI
TSTI
TSTI
TSTI
TSTI
TSTI
TSTI
TSTI
TSTI

D3
D4
D2
C2

D11
B10
D5
D6
E5
E6
E7
K4

C10
D10
D7
D9
E8
E9
G11
H4
M1

NC
NC

NC
NC

NC
NC

NC

NC
NC

NC

NC

NC

D

C

B

FRONTMIC3_TO_CODEC_BIAS_FILT_RET

2

XW3203

SHORT-20L-0.05MM-SM

ROOM=FOREHEAD

NO_XNET_CONNECTION

1

OMIT

20%

6.3V

X5R-CERM1

402

ROOM=CODEC

C3202

4.7UF

21

20%

6.3V

X5R-CERM1

402

ROOM=CODEC

PP_CODEC_TO_FRONTMIC3_BIAS

29

FRONTMIC3_BIAS_FILT_IN

1

C3222

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=CODEC

1

C3223

1.0UF

20%

6.3V

2

X5R
0201-1 0201-1

ROOM=CODEC

1

2

1

2

C3225

1.0UF

20%

6.3V
X5R
0201-1

ROOM=CODEC

C3224

1.0UF

20%

6.3V
X5R

ROOM=CODEC

NC

NC

J6

MIC4_BIAS
MIC4_BIAS_FILT

K5

M3

HS_BIAS_FILT

M2

HS_BIAS_FILT_REF

FLYN

+VCP_FILT

GNDCP

-VCP_FILT

LP_FILT+

FILT+

M12

J10

L11

M11

F12

H1

NC

NC

NC

CALTRA_LP_FILTP

CALTRA_FILTP

1

C3220

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

I2S_AP_TO_CODEC_MSP_BCLK

11

I2S_AP_TO_CODEC_MSP_LRCLK

11

I2S_AP_TO_CODEC_MSP_DOUT

11

I2S_CODEC_TO_AP_MSP_DIN

11

20

PMU_TO_CODEC_DIGLDO_PULLDN

B7

MSP_SCLK

C7

MSP_LRCK/FSYNC

D8

MSP_SDIN

A7

MSP_SDOUT

H5

DIGLDO_PULLDN

J5

DIGLDO_PDN

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

A1
A12
B12
E2
E3
E4
E10
F4
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
H6
H7
H8
H9

J8

B

A

GNDD

F11

GNDHS

L4

GNDD

GNDD

GNDD

B1

A6

E11

XW3202

SHORT-10L-0.1MM-SM

21

ROOM=CODEC

GNDP

L7

GNDA

J2

FILT-

H2

1

C3208

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=CODEC

CODEC_AGND

32

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

27 26 25 23 21 19 18 10 9 4

52 46 41 40 39 37 35 34 31 28

53

PP_VDD_MAIN

C3327

10UF

20%
10V

X5R-CERM

0402-8

ROOM=SPKAMP2

D

(North)SPEAKER AMPLIFIER 2

PP1V8_VA

1

C3316

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SPKAMP2

20%

6.3V

1

2

1

C3326

10UF

2

CERM-X5R

0402-9

ROOM=SPKAMP2

20%

6.3V

1

2

C3328

10UF

20%

6.3V

CERM-X5R

ROOM=SPKAMP2

0402-9

1

2

C3313

10UF

CERM-X5R

0402-9

ROOM=SPKAMP2

C3329

2.2UF

X5R-CERM

0201-1

ROOM=SPKAMP2

20%

6.3V

1

2

1

C3315

0.1UF

20%

6.3V

2

X5R-CERM

01005

ROOM=SPKAMP2

35 34 32 19

C

AP_TO_SPKAMP2_RESET_L

12

1

R3301

100K

5%
1/32W
MF
01005

2

ROOM=SPKAMP2

1.2UH-20%-3.0A-0.080OHM

PDM_ADARE_TO_CONVOY_CLK

29

1

R3304

100K

5%
1/32W
MF
01005

2

ROOM=SPKAMP2

MAKE_BASE=TRUE

CRITICAL

L3302

PIQA20161T-SM

ROOM=SPKAMP2

36 35 34 32 11

36 35 34 32 11

21

47

47

35 34 32 13

34

36 35 34 13

36 35 34 32

36 35 34 32

SPEAKERAMP2_LX

I2C2_AP_SDA

I2C2_AP_SCL

AUDIO_TO_AOP_INT_L

SPKAMP1_TO_SPKAMP2_SYNC

PDM_ADARE_TO_CONVOY_CLK

I2S_AOP_TO_MAGGIE_L26_MCLK

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK

I2S_MAGGIE_TO_L26_CODEC_DOUT

I2S_L26_CODEC_TO_MAGGIE_DIN

A2

SW

B2

SW

D6

SDA

E6

SCL

A7

INT*

A6

RESET*

F6

ALIVE/SYNC

E5

AD0/PDM_CLK1

B7

MCLK

C7

SCLK

C6

LRCK/FSYNC

D7

SDIN

B6

SDOUT

A5

VP

F5

VA

U3301

CS35L26-A1

WLCSP

ROOM=SPKAMP2

CRITICAL

VBST_B
VBST_B

VBST_A
VBST_A

ISNS+

ISNS-

VSNS+

VSNS-

OUT+

OUT-

A1

PP_SPKR2_VBOOST

B1

C1
D1

F1

SPEAKERAMP2_ISENSE_P

E1

SPEAKERAMP2_ISENSE_N

E2

SPEAKER_TO_SPEAKERAMP2_VSENSE_P
SPEAKER_TO_SPEAKERAMP2_VSENSE_N

E3

D2
C2

1

C3312

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SPKAMP2

1

C3311

0.1UF

10%
16V

2

X5R-CERM
0201

ROOM=SPKAMP2

1

C3324

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP2

29

29

1

C3325

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP2

1

C3319

0.01UF

10%

6.3V

2

X5R
01005

ROOM=SPKAMP2

NO_XNET_CONNECTION

1

C3306

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP2

1

C3308

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP2

SPEAKERAMP2_TO_SPEAKER_OUT_POS
SPEAKERAMP2_TO_SPEAKER_OUT_NEG

C

46 45 29

46 45 29

B

PDM_CODEC_TO_SPKAMP2_CLK

31

PDM_CODEC_TO_SPKAMP2_DATA

31

PDM_CONVOY_TO_ADARE_DATA

29

F7

PDM_CLK0

E7

PDM_DATA0

D5

PDM_DATA1 AD1

A4

A3

GNDP GNDA

B4

B3

C3

C4

C5

D3

D4

B5

E4

F2

FILT+

F4

SPEAKERAMP2_FILT

F3

1

C3318

1UF

10%
10V

2

X5R
402-1

ROOM=SPKAMP2

C3331

1000PF

10%
10V
X5R

ROOM=SPKAMP2

01005

1

2

1

C3323

1000PF

10%
10V

2

X5R
01005

ROOM=SPKAMP2

Pg46: Compass Compensation Coil

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SPEAKER AMPLIFIER 1

34567 8

(South)

2 1

D

27 26 25 23 21 19 18 10 9 4

52 46 41 40 39 37 35 33 31 28

53

PP_VDD_MAIN

C3407

10UF

20%
10V

X5R-CERM

0402-8

ROOM=SPKAMP1

D

#25112685,Remove C3414
See SPKAMP1 C3424 on Pg46

1

C3405

10UF

2

CERM-X5R

0402-9

ROOM=SPKAMP1

20%

6.3V

1

2

1

C3425

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SPKAMP1

1

C3426

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SPKAMP1

PP1V8_VA

35 33 32 19

C

B

35 13

PULLED LOW ON PG 35

AOP_TO_SPKAMP1_ARC_RESET_L

TO TRINITY

MAKE_BASE=TRUE

28

48

48

35 33 32 13

33

36 35 33 13

36 35 33 32 11

36 35 33 32 11

36 35 33 32

36 35 33 32

SPEAKERAMP1_LX

I2C_AOP_SDA

I2C_AOP_SCL

AUDIO_TO_AOP_INT_L

SPKAMP1_TO_SPKAMP2_SYNC

GND

I2S_AOP_TO_MAGGIE_L26_MCLK

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK

I2S_MAGGIE_TO_L26_CODEC_DOUT

I2S_L26_CODEC_TO_MAGGIE_DIN

NC

NC

A5

VP

A2

SW

B2

SW

D6

SDA

E6

SCL

A7

INT*

A6

RESET*

F6

ALIVE/SYNC

E5

AD0/PDM_CLK1

B7

MCLK

C7

SCLK

C6

LRCK/FSYNC

D7

SDIN

B6

SDOUT

F7

PDM_CLK0

E7

PDM_DATA0

D5

PDM_DATA1 AD1

B4

B3

A4

A3

U3402

CS35L26-A1

WLCSP

ROOM=SPKAMP1

CRITICAL

GNDP GNDA

C5

C4

C3

D3

D4

F5

VA

B5

E4

VBST_B
VBST_B

VBST_A
VBST_A

ISNS+

ISNS-

VSNS+

VSNS-

OUT+

OUT-

FILT+

F2

A1
B1

C1
D1

F1

SPEAKERAMP1_ISENSE_P

E1

SPEAKERAMP1_ISENSE_N

E2

SPEAKER_TO_SPEAKERAMP1_VSENSE_P

E3

SPEAKER_TO_SPEAKERAMP1_VSENSE_N

D2
C2

F4

SPEAKERAMP1_FILT

F3

PP_SPKR1_VBOOST

1

C3427

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SPKAMP1

1

2

C3428

0.1UF

10%
16V
X5R-CERM
0201

ROOM=SPKAMP1

1

2

C3429

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SPKAMP1

1

C3403

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP1

41

41

1

C3404

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP1

1

C3430

0.01UF

10%

6.3V

2

X5R
01005

ROOM=SPKAMP1
NO_XNET_CONNECTION

1

C3431

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP1

SPEAKERAMP1_TO_SPEAKER_OUT_POS
SPEAKERAMP1_TO_SPEAKER_OUT_NEG

10%
10V
X5R

1

2

C3422

1000PF

01005

ROOM=SPKAMP1 ROOM=SPKAMP1

1

C3434

1000PF

10%
10V

2

X5R
01005

1

C3432

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=SPKAMP1

C

41

41

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

ARC DRIVER

34567 8

2 1

D

See ARC1 C3530 at Pg46

#25742582,Add back C3531 for D10x at Pg46

0201 C3525 is at Pg46

53

27 26 25 23 21 19 18 10 9 4

52 46 41 40 39 37 34 33 31 28

PP_VDD_MAIN

C3532

10UF

20%

6.3V

CERM-X5R

0402-9

ROOM=ARC1

D

PP1V8_VA

1

2

1

C3527

0.1UF

20%

6.3V

2

X5R-CERM
01005 0201-1

ROOM=ARC1

1

C3534

2

ROOM=ARC1

2.2UF

20%

6.3V
X5R-CERM

35 34 33 32 19

C

B

34 13

AOP_TO_SPKAMP1_ARC_RESET_L

1

R3508

100K

5%
1/32W
MF
01005

2

ROOM=ARC1

35 34 33 32 19

NOSTUFF

C3501

10PF

01005

ROOM=ARC1

PP1V8_VA

1

5%

16V

2

CERM

TO TRINITY

34 33 32 13

MAKE_BASE=TRUE

36 34 33 13

36 34 33 32 11

36 34 33 32 11

36 34 33 32

36 34 33 32

ARC1_LX

28

I2C_AOP_SDA

48

I2C_AOP_SCL

48

AUDIO_TO_AOP_INT_L

NC FROM HOMER PER #25452686

PP1V8_VA

I2S_AOP_TO_MAGGIE_L26_MCLK

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK

I2S_MAGGIE_TO_L26_CODEC_DOUT

I2S_L26_CODEC_TO_MAGGIE_DIN

NC

NC

NC

A5

VP

A2

SW

B2

SW

D6

SDA

E6

SCL

A7

INT*

A6

RESET*

F6

ALIVE/SYNC

E5

AD0/PDM_CLK1

B7

MCLK

C7

SCLK

C6

LRCK/FSYNC

D7

SDIN

B6

SDOUT

F7

PDM_CLK0

E7

PDM_DATA0

D5

PDM_DATA1 AD1

A4

A3

GNDP GNDA

B4

B3

U3502

CS35L26-A1

WLCSP

ROOM=SPKAMP2

CRITICAL

C5

C4

C3

D3

D4

F5

VA

B5

E4

F2

VBST_B
VBST_B

VBST_A
VBST_A

ISNS+

ISNS-

VSNS+

VSNS-

OUT+

OUT-

FILT+

A1
B1

C1
D1

F1

ARC1_ISENSE_P

E1

ARC1_ISENSE_N

E2

SOLENOID1_TO_ARC1_VSENSE_POS

E3

SOLENOID1_TO_ARC1_VSENSE_NEG

D2
C2

F4

ARC1_FILT

F3

PP_ARC1_VBOOST

1

C3526

220PF

5%
10V

2

C0G-CERM
01005

ROOM=ARC1

1

C3535

0.1UF

10%
16V

2

X5R-CERM
0201

ROOM=ARC1

C3536

1

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=ARC1

VOLTAGE=8.0V

1

C3537

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=ARC1

VOLTAGE=8.0V

VOLTAGE=8.0V

ROOM=ARC1

41

41

C3529

1

C3524

10UF

20%
10V

2

X5R-CERM
0402-8

1

2

1000PF

10%
10V
X5R

01005

ROOM=ARC1

C3528

0.01UF

10%

6.3V
X5R
01005

ROOM=ARC1

NO_XNET_CONNECTION

1

2

1

C3542

1000PF

10%
10V

2

X5R
01005

1

C3538

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=ARC1

1

C3539

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=ARC1

ARC1_TO_SOLENOID1_OUT_POS
ARC1_TO_SOLENOID1_OUT_NEG

ROOM=ARC1

C

41

41

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

47 41 40 37 36 32 21 20 18 16

53 52 48

MAGGIE LDO MAGGIE

APN: 353S00842

PP1V8_SDRAM

B1

U3603

LD39130S-1.2V/AP

IN

EN

CSP

GND

B2

OUT

A2A1

APN: 336S00020

PP1V2_MAGGIE

1

2

C3605

ROOM=ARC_CTRL

4UF

20%

6.3V
CER-X5R
0201

R3601

100

21

5%

1/32W

MF

01005

ROOM=ARC_CTRL

1

C3601

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=ARC_CTRL

PP1V2_MAGGIE_PLL

1

C3602

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=ARC_CTRL

D

C

B

HOMER STM32L0 MICRO

STM32L03 APN: 337S00231

PP3601

P2MM-NSM

ROOM=HOMER

PP3602

P2MM-NSM

ROOM=HOMER

12

UART_HOMER_TO_AP_RXD

12

UART_AP_TO_HOMER_TXD

R3607

100

5%

1/32W

MF

01005

ROOM=HOMER

21

AP_BI_HOMER_BOOTLOADER_ALIVE_R

47 41

47 41

53 17 13

47 41 40 37 36 32 21 20 18 16

1

SM

PP

SM

1

PP

36

MAGGIE_TO_HOMER_WAKE

13

HOMER_TO_AOP_WAKE_INT
I2C_HOMER_SCL

I2C_HOMER_SDA

13

SWD_AP_BI_HOMER_SWDIO

SWD_AP_TO_MANY_SWCLK

53 52 48

PP1V8_SDRAM

C3603

2.2UF

6.3V

X5R-CERM

0201-1

ROOM=HOMER

20%

1

2

NC

NC

NC

NC

E5

PA0_CLK_IN

B4

PA1

D4

PA2

E4

PA3

B3

PA4

D3

PA5

E3

PA6

C3

PA7

C1

PA8

B1

PA9

C2

PA10

A1

PA13

A2

PA14

C4

D1

VDDAVDD

U3601

STM32L031E6Y6D

ROOM=HOMER

WLCSP

PC14_OSC32_IN

PC15_OSC32_OUT

RST*

BOOT0

VSSA

E1

PB0
PB1
PB3
PB6
PB7

E2
D2

SPI_MAGGIE_TO_HOMER_POS_MOSI

B2
A3
A4

NC

B5

NC

C5

NC

D5

PMU_TO_HOMER_RESET_L

A5

AP_BI_HOMER_BOOTLOADER_ALIVE

NOTE: RESET HAS INTERNAL 65K PULLUP

1

R3611

27K

5%
1/32W
MF
01005

2

ROOM=HOMER

36 24 18

VPP_2V5 must be > 1.71V for SPI Slave programming

PP1V8_MAGGIE_IMU

36

MAGGIE_TO_HOMER_WAKE

SPI_MAGGIE_TO_HOMER_POS_SCLK

SPI_HOMER_TO_MAGGIE_POS_MISO

13

AOP_TO_MAGGIE_EN

13

MAGGIE_TO_AOP_INT

12

1

C3607

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=HOMER

1

C3604

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=ARC_CTRL

20

1

C3606

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=ARC_CTRL

NC

NC

NC

NC

NC

A2

IRLED

C6

RGB0

B6

RGB1

A6

RGB2

B5

IOT_46B_G0

F6

IOB_2A

E6

IOB_3B_G6

D6

IOB_4A

D5

IOB_5B

F5

IOB_6A

E5

IOB_7B

B3

C4

A4

VCCPLL

VCCIO_2

VCCIO_0

ICE5LP4K-SWG36I

U3602

WLCSP

BANK 0

BANK 2

ROOM=ARC_CTRL

CRITICAL

GND_LED

A1

D4

A5

VCC

VPP_2V5

IOB_10A

IOB_11B_G5

IOB_12A_G4_CDONE

IOB_16A
IOB_20A

IOB_25B_G3

IOB_26A

BANK 1

IOB_32A_SPI_SO

IOB_33B_SPI_SI

IOB_34A_SPI_SCK

IOB_35B_SPI_CSN

GND

GND

A3

C5

IOB_27B
IOB_29B
IOB_30A
IOB_31B

CRESET_B

C3

SPI_VCCIO1

B4
F4
E4
F3
E3
C2
B1
D2
E2
C1
B2
F2
D1
E1
F1

D3

NC

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK_R
MAGGIE_TO_AP_CDONE
UART_AOP_TO_MAGGIE_TXD
I2S_MAGGIE_TO_AP_DIN
I2S_AOP_TO_MAGGIE_L26_MCLK
I2S_MAGGIE_TO_L26_CODEC_DOUT
I2S_L26_CODEC_TO_MAGGIE_DIN
I2S_AP_TO_MAGGIE_DOUT

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
SPI_CODEC_MAGGIE_TO_AP_MISO
SPI_AP_TO_CODEC_MAGGIE_MOSI
SPI_AP_TO_CODEC_MAGGIE_SCLK
SPI_AP_TO_MAGGIE_CS_L

AP_TO_MAGGIE_CRESETB_L

1

R3603

511K

1%
1/32W
MF
01005

2

12

13

11

11

35

C

R3604

33.2

1%

1/32W

MF

01005

ROOM=ARC_CTRL

35 34 33 13

35 34 33 32

MAGGIE <-> ARC, SPKRS, CODEC (SDOUT)

35 34 33 32

MAGGIE <-> ARC, SPKRS, CODEC (SDIN)

MAGGIE <-> AP (SDOUT)

34 33 32 11

MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC

32 11

32 11

32 11

MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC

21

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

MAGGIE <-> AP (SDIN)

PP1V8_MAGGIE_IMU

1

R3605

10K

5%
1/32W
MF
01005

2

1

R3602

10K

5%
1/32W
MF
01005

2

9

12

35 34 33 32 11

36 24 18

B

A

#24543115: Scrub Value

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

DISPLAY & TOUCH - POWER SUPPLIES

34567 8

2 1

D

CHESTNUT DISPLAY PMU

APN:338S1172

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 52

1.0UH-20%-2.25A-0.15OHM

PP_VDD_MAIN

CRITICAL

L3704

PIXB2016FE-SM

ROOM=CHESTNUT

1

2

20 47

47

39 20

40 20 13 7

20

C3722 See Page46

C3710

10UF

20%

6.3V

CERM-X5R

0402-9

ROOM=CHESTNUT

CHESTNUT_LX

I2C0_AP_SCL

I2C0_AP_SDA

LCM_TO_CHESTNUT_PWR_EN

PMU_TO_AOP_TRISTAR_ACTIVE_READY

CHESTNUT_TO_PMU_ADCMUX

6.3V

PP_CHESTNUT_CP

1

C3707

10UF

20%
VOLTAGE=10V

2

X5R-CERM
0402-8

1

ROOM=CHESTNUT

PN_CHESTNUT_CN

D

NOSTUFF

1

2

D1

VIN

B2

SW

A2

SYNC

NO INT PULL

D3

SCL

D2

SDA

C3

LCM_EN

200K INT PD

C2

RESET*

NO INT PULL

E1

ADCMUX

U3703

TPS65730A0PYFF

BGA

ROOM=CHESTNUT

CF1

CF2

CRITICAL

LCMBST

CPUMP

VNEG

VNEG(SUB)

HVLDO1

HVLDO2

AGND

C1

B1

PGND2

PGND1

D4

HVLDO3

C4
E4

B3
B4

E3

E2

A4

A3

A1

PP6V0_LCM_BOOST

1

C3711

1UF

20%
16V

2

CER-X5R
0201

ROOM=CHESTNUT

1

2

C3712

10UF

20%
10V
X5R-CERM
0402-8

ROOM=CHESTNUT

1

C3713

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=CHESTNUT

C3726

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=CHESTNUT

1

C3714

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=CHESTNUT

NOSTUFF

1

C3727

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=CHESTNUT

1

2

#24543286: Densense Cap for Chestnut Charge Pump

C3715

4.7UF

20%
10V
X5R-CERM
0402

ROOM=CHESTNUT

1

C3716

4.7UF

20%
10V

2

X5R-CERM
0402

ROOM=CHESTNUT

1

C3717

220PF

5%
10V

2

C0G-CERM
01005

ROOM=CHESTNUT

PN5V7_LCM_MESON_AVDDN

PP5V7_MESON_AVDDH

PP5V7_LCM_AVDDH

PP5V1_TOUCH_VDDH

39

39

39

39

C

LED BACKLIGHT DRIVER - 6LED

APN:353s00640

27 26 25 23 21 19 18 10 9 4

41 40 39 37 35 34 33 31 28

48 47 41 40 36 32 21 20 18 16

53 52 46

PP_VDD_MAIN

C3702

VOLTAGE=6.3V

CERM-X5R

0402-9

ROOM=BACKLIGHT

PP1V8_SDRAM

53 52

DWI_PMGR_TO_BACKLIGHT_DATA

11

DWI_PMGR_TO_BACKLIGHT_CLK

11

10UF

20%

1

2

TO TRINITY

D4

IN OUT

D3

VIO/HWEN

C2

SDI

C3

SCK

BL_SW2_LX

28

BL_SW1_LX

28

U3701

LM3539A1

DSBGA

CRITICAL

25V

25V

SW1

SW2_1
SW2_2

A1

C4

A3
A4

CRITICAL

D3701

DSN2

KA

NSR05F30NXT5G

ROOM=BACKLIGHT

CRITICAL

D3702

NSR0530P2T5G

AK

SOD-923-1

ROOM=BACKLIGHT

#26634069:D1x, C3715/C3716 to 138S0719 0402 4.7uF

1

C3703

220PF

2%
50V 35V

2

C0G
0201

ROOM=BACKLIGHT
PLACE_NEAR=U3701:2MM

1

C3725

2.2UF

20%
35V

2

X5R
0402

1

C3704

2.2UF

20%
35V

2

0402

1

C3706

2.2UF

20%
35V

2

X5RX5R
0402

1

C3705

2.2UF

20%
35V

2

X5R
0402

1

C3721

2.2UF

20%

2

X5R
0402

PP_LCM_BL_ANODE

C

39

B

A

47

I2C0_AP_SDA
I2C0_AP_SCL

47

AP_TO_MUON_BL_STROBE_EN

9

BB_TO_STROBE_DRIVER_GSM_BURST_IND

53 26

MOJAVE MESA BOOST

APN:353S00671

L3703

1.0UH-20%-0.4A-0.636OHM

53 52

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 38 32 25 23 19

PP_VDD_MAIN POS18V0_MESA_LX

C3718

10UF

6.3V

CERM-X5R

0402-9

ROOM=MOJAVE

1

20%

2

ROOM=MOJAVE

CRITICAL

PP_VDD_BOOST

20%

6.3V

1

2

C3724

10UF

CERM-X5R

0402-9

ROOM=MOJAVE

0403

21

MESA_TO_BOOST_EN

38 4

PP17V0_MOJAVE_LDOIN

1

R3701

200K

1%
1/32W
MF
01005

2

ROOM=BACKLIGHT

B2
A2

D1

D2

B1

B2
A3

C2

SDA
SCL

TRIG

INHIBIT

SW

VIN

EN_M

EN_S

LDOIN

ROOM=BACKLIGHT

GND

GND

B4

B3

U3702

LM3638A0

BGA

ROOM=MOJAVE

CRITICAL

PGND

AGND

A1

B3

LED1
LED2

VOUT

PMID

C1
B1

C3A2

C1

1

C3708

100PF

5%
35V

2

NP0-C0G
01005

ROOM=MOJAVE

1

C3709

100PF

5%
35V

2

NP0-C0G
01005

ROOM=MOJAVE

PP_LCM_BL_CAT1
PP_LCM_BL_CAT2

PP16V0_MESA

1

C3720

2.2UF

20%
35V

2

X5R
0402

ROOM=MOJAVE

1

C3719

2.2UF

20%
35V

2

X5R
0402

ROOM=MOJAVE

39

39

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

B

A

8 7 5 4 2 1

36

34567 8

2 1

D

MESA POWER

19

PP3V0_MESA

1

C3813

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAMBA_MESA

1

C3814

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAMBA_MESA

1

C3815

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAMBA_MESA

1

C3821

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAMBA_MESA

FL3801

150OHM-25%-200MA-0.7DCR

21

ROOM=MAMBA_MESA

01005

1

C3802

220PF

5%
10V

2

C0G-CERM
01005

ROOM=MAMBA_MESA

FL3803

80-OHM-25%-0.52A-0.17OHM

21

0201

ROOM=MAMBA_MESA

PP1V8_MESA_CONNPP1V8_MESA

1

C3822

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=MAMBA_MESA

CRITICAL

MAMBA AND MESA CONNECTOR

MLB: 516S00141 (RCPT)
FLEX: 516S00142 (PLUG)

PP3V0_MESA_CONN

1

C3804

220PF

5%
10V

2

C0G-CERM
01005

ROOM=MAMBA_MESA

38 48 19

38

45

LCM_TO_MAMBA_MSYNC_CONN

1

C3807

56PF

5%

25V

2

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

P2MM-NSM

SM

1

PP

PP3801

PP3V0_MESA_CONN

38

PP16V0_MESA_CONN

38

MAMBA_TO_LCM_MDRIVE_CONN_MESA

38

AP_TO_TOUCH_MAMBA_RESET_CONN_L

45 39

TP_MAMBA_HINT_L

I2C_TOUCH_BI_MAMBA_SDA

47

I2C_TOUCH_TO_MAMBA_SCL

47

PP1V8_TOUCH_TO_MAMBA_CONN

38

GUARD

J3801

BB35C-RA24-3A

F-ST-SM

26 25

21
43
65

87
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23

28 27

29

Matches flex_x452_acf, schematic revision 1.5.0 pinout

PP1V8_MESA_CONN

MESA_TO_AOP_FDINT_CONN
I2C_MESA_TURTLE_SDA_CONN

I2C_MESA_TURTLE_SCL_CONN

MESA_TO_BOOST_EN_CONN
MESA_TO_AP_INT_CONN
SPI_AP_TO_MESA_SCLK_CONN

SPI_AP_TO_MESA_MOSI_CONN
AOP_TO_MESA_BLANKING_EN_CONN
SPI_MESA_TO_AP_MISO_CONN
PP2V75_MAMBA_CONN

38

38

48

48

38

38

38

38

38

38

38

D

C

FL3802

150OHM-25%-200MA-0.7DCR

ROOM=MAMBA_MESA

01005

21

1

C3803

100PF

5%
35V

2

NP0-C0G
01005

ROOM=MAMBA_MESA

PP16V0_MESA_CONNPP16V0_MESA

38 37 4

MESA DIGITAL I/O

FL3807

150OHM-25%-200MA-0.7DCR

SPI_AP_TO_MESA_MOSI SPI_AP_TO_MESA_MOSI_CONN

11 38

1

R3807

511K

1%
1/32W
MF
01005

2

ROOM=MAMBA_MESA

01005

ROOM=MAMBA_MESA

R3809

SPI_AP_TO_MESA_SCLK

11

1

R3808

511K

1%
1/32W
MF
01005

2

ROOM=MAMBA_MESA

0.00

0%

1/32W

MF

ROOM=MAMBA_MESA

01005

R3811

SPI_MESA_TO_AP_MISO SPI_MESA_TO_AP_MISO_CONN

11 38

33.2

1%

1/32W

MF

01005

ROOM=MAMBA_MESA

21

1

C3816

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

21

1

C3817

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

21

1

C3818

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

SPI_AP_TO_MESA_SCLK_CONN

38

47 46 39 38 18

53 37 32 25 23 19

PP_VDD_BOOST

PP1V8_TOUCH

MAMBA DIGITAL I/O

C3828

2.2UF

20%

6.3V

X5R-CERM

0201-1

ROOM=MAMBA_MESA

XW3801

SHORT-20L-0.05MM-SM

21

ROOM=PMU

OMIT

47 46 39 38 18

MAMBA_TO_LCM_MDRIVE

45

1

2

MAMBA_LDO_EN

PP1V8_TOUCH

NP0-C0G-CERM

ROOM=MAMBA_MESA

VIN

3

EN

C3805

56PF

5%

25V

01005

MAMBA POWER

NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM

IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC.
VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY

U3801

LP5907SNX-2.75

X2SON

ROOM=MAMBA_MESA

EPADGND

5

2

VOUT

14

FL3804

150OHM-25%-200MA-0.7DCR

21

1

2

01005

ROOM=MAMBA_MESA

1

C3823

10UF

20%
10V

2

X5R-CERM
0402-8

ROOM=MAMBA_MESA

R3805

0.00

1/32W

01005

ROOM=MAMBA_MESA

0%

MF

30

ROOM=MAMBA_MESA

TI:353S00576
ST:353S00932

PP2V75_MAMBA_CONN

1

C3812

220PF

5%
10V

2

C0G-CERM
01005

ROOM=MAMBA_MESA

21

1

C3824

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAMBA_MESA

PP1V8_TOUCH_TO_MAMBA_CONN

1

C3811

220PF

5%
10V

2

C0G-CERM
01005

ROOM=MAMBA_MESA

MAMBA_TO_LCM_MDRIVE_CONN_MESA

38

C

38

38

NOSTUFF

1

C3806

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

B

R3801

MESA_TO_AP_INT

11

681

1/32W

01005

ROOM=MAMBA_MESA

1%

MF

21

1

C3819

100PF

5%
16V

2

NP0-C0G
01005

ROOM=MAMBA_MESA

MESA_TO_AP_INT_CONN

R3802

MESA_TO_BOOST_EN

37 4

681

1/32W

01005

ROOM=MAMBA_MESA

1%

MF

21

1

C3801

100PF

5%
16V

2

NP0-C0G
01005

ROOM=MAMBA_MESA

MESA_TO_BOOST_EN_CONN

FL3811

150OHM-25%-200MA-0.7DCR

AOP_TO_MESA_BLANKING_EN

13 38

01005

21

1

2

AOP_TO_MESA_BLANKING_EN_CONN

C3825

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

38

38

FL3806

150OHM-25%-200MA-0.7DCR

MESA_TO_AOP_FDINT

13 38

01005

ROOM=MAMBA_MESA

21

1

C3826

100PF

5%
16V

2

NP0-C0G
01005

ROOM=MAMBA_MESA

MESA_TO_AOP_FDINT_CONN

#24543342: stuff 100pF

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

D

DISPLAY POWER DISPLAY MIPI

37

ROOM=DISPLAY_B2B

25 18 17 16 13 12 11 9 8 7 5

PP5V7_LCM_AVDDH

C3901

10UF

X5R-CERM

0402-8

1

20%
10V

2

52 48 47 46 29

1

2

PP1V8

C3929

10UF

20%
10V
X5R-CERM
0402-8

ROOM=DISPLAY_B2B

FL3912

240-OHM-25%-0.42A-0.31DCR

2 1

0201

ROOM=DISPLAY_B2B

1

C3933

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=DISPLAY_B2B

FL3906

240-OHM-25%-0.42A-0.31DCR

2 1

ROOM=DISPLAY_B2B

0201

1

C3934

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=DISPLAY_B2B

PP5V7_LCM_AVDDH_CONN

1

C3913

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

PP1V8_LCM_CONN

1

C3914

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

45

45

90_MIPI_AP_TO_LCM_CLK_P

9

90_MIPI_AP_TO_LCM_DATA0_P

9

90_MIPI_AP_TO_LCM_DATA0_N

9

90_MIPI_AP_TO_LCM_DATA1_P

9

L3901

65OHM-0.7-2GHZ-3.4OHM

TAM0605

SYM_VER-1

4

3 2

ROOM=DISPLAY_B2B

CRITICAL

1

L3902

65OHM-0.7-2GHZ-3.4OHM

TAM0605

SYM_VER-1

4

3 2

ROOM=DISPLAY_B2B

L3903

65OHM-0.7-2GHZ-3.4OHM

4

TAM0605

SYM_VER-1

CRITICAL

1

1

CRITICAL

90_MIPI_AP_TO_LCM_CLK_CONN_P

90_MIPI_AP_TO_LCM_CLK_CONN_N90_MIPI_AP_TO_LCM_CLK_N

90_MIPI_AP_TO_LCM_DATA0_CONN_P

90_MIPI_AP_TO_LCM_DATA0_CONN_N

90_MIPI_AP_TO_LCM_DATA1_CONN_P

45

45 9

45

45

45

34567 8

AP/TOUCH INTERFACE

2 1

D

C

B

PN5V7_LCM_MESON_AVDDN

37

PP5V7_MESON_AVDDH

37

47 46 38 18

PP1V8_TOUCH

PP5V1_TOUCH_VDDH

37

ROOM=DISPLAY_B2B

BACKLIGHT

37

37

37

PP_LCM_BL_ANODE

PP_LCM_BL_CAT1

PP_LCM_BL_CAT2

AC Coupling Caps

FL3908

240-OHM-25%-0.42A-0.31DCR

2 1

0201

ROOM=DISPLAY_B2B

FL3909

240-OHM-25%-0.42A-0.31DCR

2 1

0201

ROOM=DISPLAY_B2B

FL3910

33-OHM-25%-1500MA

21

C3932

2.2UF

20%

6.3V

X5R-CERM

0201-1

1

2

0201

ROOM=DISPLAY_B2B

FL3911

240-OHM-25%-0.42A-0.31DCR

2 1

0201

ROOM=DISPLAY_B2B

FL3901

33-OHM-25%-1500MA

21

0201

ROOM=DISPLAY_B2B

FL3902

33-OHM-25%-1500MA

21

0201

ROOM=DISPLAY_B2B

FL3903

33-OHM-25%-1500MA

21

0201

ROOM=DISPLAY_B2B

PN5V7_LCM_MESON_AVDDN_CONN

1

C3909

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

PP5V7_MESON_AVDDH_CONN

1

C3910

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

1

C3940

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=DISPLAY_B2B

PP1V8_TOUCH_CONN

1

C3911

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

PP5V1_TOUCH_VDDH_CONN

1

C3912

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

PP_LCM_BL_ANODE_CONN

NOSTUFF

1

C3903

220PF

2%
50V

2

C0G
0201

ROOM=DISPLAY_B2B

#26634069: nostuff C3903 to help desense

VOLTAGE=25.0V

PP_LCM_BL_CAT1_CONN

1

C3904

100PF

5%
35V

2

NP0-C0G
01005

ROOM=DISPLAY_B2B

PP_LCM_BL_CAT2_CONN

1

C3905

100PF

5%
35V

2

NP0-C0G
01005

ROOM=DISPLAY_B2B

90_MIPI_AP_TO_LCM_DATA1_N

9

37 20

LCM_TO_CHESTNUT_PWR_EN

AP_TO_LCM_RESET_L

12

R3901

ROOM=DISPLAY_B2B

PMU_TO_LCM_PANICB

20

AOP/TOUCH INTERFACE

53 23 20 13

LCM_TO_MANY_BSYNC

13

UART_TOUCH_TO_AOP_RXD

13

UART_AOP_TO_TOUCH_TXD

3 2

ROOM=DISPLAY_B2B

150OHM-25%-200MA-0.7DCR

150OHM-25%-200MA-0.7DCR

01005

1

100K

5%

1/32W

MF

01005

2

150OHM-25%-200MA-0.7DCR

150OHM-25%-200MA-0.7DCR

150OHM-25%-200MA-0.7DCR

FL3913

2 1

01005

ROOM=DISPLAY_B2B

FL3915

R3915

10

21

5%

1/32W

MF

01005

ROOM=DISPLAY_B2B

FL3916

2 1

01005

ROOM=DISPLAY_B2B

FL3917

2 1

01005

ROOM=DISPLAY_B2B

FL3918

2 1

01005

ROOM=DISPLAY_B2B

FL3904

90_MIPI_AP_TO_LCM_DATA1_CONN_N

LCM_TO_CHESTNUT_PWR_EN_CONN

1

C3916

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

21

AP_TO_LCM_RESET_CONN_L

1

C3917

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

PMU_TO_LCM_PANICB_CONN

1

C3918

100PF

5%
16V

2

NP0-C0G
01005

ROOM=DISPLAY_B2B

45

45

45

45

AP_TO_TOUCH_MAMBA_RESET_L

12

11

SPI_AP_TO_TOUCH_CS_L

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DISPLAY_B2B

To Display B2B

FL3922

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DISPLAY_B2B

1

2

1

C3915

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

C3924

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

AP_TO_TOUCH_MAMBA_RESET_CONN_L

1

C3902

220PF

5%
10V

2

C0G-CERM
01005

ROOM=MAMBA_MESA

45 38

To Mamba/Mesa B2B

SPI_AP_TO_TOUCH_CS_CONN_L

C

45

R3923

LCM_TO_MANY_BSYNC_CONN

1

C3919

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

45

SPI_AP_TO_TOUCH_SCLK SPI_AP_TO_TOUCH_SCLK_CONN

11 45

NOSTUFF

5%

25V

1

2

C3922

56PF

NP0-C0G-CERM

ROOM=DISPLAY_B2B

01005

0.00

1/32W

01005

ROOM=DISPLAY_B2B

FL3924

150OHM-25%-200MA-0.7DCR

SPI_AP_TO_TOUCH_MOSI

11

2 1

01005

ROOM=DISPLAY_B2B

0%

MF

21

1

C3923

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

45

B

1

C3925

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

SPI_AP_TO_TOUCH_MOSI_CONN

FL3919

150OHM-25%-200MA-0.7DCR

UART_TOUCH_TO_AOP_RXD_CONN

1

C3920

56PF

5%
25V

2

NP0-C0G-CERM
01005

45

11

SPI_TOUCH_TO_AP_MISO

2 1

01005

ROOM=DISPLAY_B2B

1

C3926

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

SPI_TOUCH_TO_AP_MISO_CONN

45

FL3920

ROOM=DISPLAY_B2B

UART_AOP_TO_TOUCH_TXD_CONN

1

C3921

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

45

12

TOUCH_TO_AP_INT_L

AP_TO_CUMULUS_CLK32K

11

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DISPLAY_B2B

1

C3927

100PF

5%
16V

2

NP0-C0G
01005

R3908

33.2

2

1/32W

ROOM=DISPLAY_B2B

01005

1%

MF

1

1

C3928

100PF

5%
16V

2

NP0-C0G
01005

ROOM=DISPLAY_B2B

AP_TO_CUMULUS_CLK_32K_CONN

ROOM=DISPLAY_B2B

TOUCH_TO_AP_INT_L_CONN

45

45

A

28 27 26 25 23 21 19 18 10 9 4

53 52 46 41 40 37 35 34 33 31

8 7 5 4 2 1

PP_VDD_MAIN

1

C3930

220PF 220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

AC return path for LCM MIPI which is referenced to GND and VDD_MAIN

1

C3931

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

1

C3935

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

1

C3936

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

1

C3937

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

For placement "along the way" as we route from SOC to B2B.

1

C3938

220PF220PF

5%
10V

2

C0G-CERM
01005

ROOM=DISPLAY_B2B

1

C3939

220PF

5%
10V

2

C0G-CERM
01005

A

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

36

D

34567 8

2 1

D

C

53 41 29 19

PP3V0_TRISTAR_ANT_PROX

TRISTAR 2

z=0.45mm

<rdar:/24285280> EVT: 343S00091 (P2:343S00078)

1

C4003

1.0UF

20%

6.3V

2

X5R
0201-1

1

C4002

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=TRISTARROOM=TRISTAR

48 47 41 37 36 32 21 20 18 16

53 52

PP1V8_SDRAM

1

C4004

0.01UF

10%

6.3V

2

X5R
01005

ROOM=TRISTAR

PP_ACC_VAR

46 27 19

TRISTAR_REVERSE_GATE

D

PP5V0_USB

3

D

CRITICAL

Q4001

1

G

RV3CA01ZP

DFN

41 21 4

C

B

20

TRISTAR_TO_PMU_USB_BRICK_ID

7

90_USB_AP_DATA_P

7

90_USB_AP_DATA_N

27 26 25 23 21 19 18 10 9 4

52 46 41 39 37 35 34 33 31 28

AC return path for USB pairs which is referenced to GND and VDD_MAIN

53

PP_VDD_MAIN

1

C4007

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

2

C4008

220PF

5%
10V
C0G-CERM
01005

ROOM=SOC

1

C4001

0.01UF

10%

6.3V

2

X5R
01005

ROOM=PMU

R4001

6.34K

1/32W

01005

ROOM=PMU

L4022

15NH-250MA

0201

ROOM=TRISTAR

L4021

15NH-250MA

0201

ROOM=TRISTAR

1%

MF

21

21

F4

F3

21

VDD_1V8

D5

VDD_3V0

ACC_PWR

1

R4002

10K

5%
1/32W
MF
01005

2

ROOM=TRISTAR

S

2

ROOM=TRISTAR

Sm Footprint: 376S00135

U4001

CBTL1610A3BUK

31

90_MIKEYBUS_DATA_P

31

90_MIKEYBUS_DATA_N

53

90_USB_BB_DATA_P

53

90_USB_BB_DATA_N

TRISTAR_USB_BRICK_ID_R

90_USB_AP_DATA_L_P
90_USB_AP_DATA_L_N

12

UART_AP_TO_ACCESSORY_TXD

12

UART_ACCESSORY_TO_AP_RXD

12

UART_AP_DEBUG_TXD

12

UART_AP_DEBUG_RXD

7

SWD_DOCK_TO_AP_SWCLK

7

SWD_DOCK_BI_AP_SWDIO

NC

C3

DIG_DP

C4

DIG_DN

A1

USB1_DP

B1

USB1_DN

C2

BRICK_ID

A3

USB0_DP

B3

USB0_DN

E2

UART0_TX

E1

UART0_RX

F2

UART1_TX

F1

UART1_RX

D2

UART2_TX

D1

UART2_RX

A5

JTAG_CLK

B5

JTAG_DIO

WLCSP

CON_DET_L

POW_GATE_EN*

SWITCH_EN

HOST_RESET

BYPASS

DVSS

DVSS

DVSS

F5

A6

C1

P_IN
ACC1
ACC2

DP1

DN1

DP2

DN2

21

SDA

SCL

INT

F6

PP5V0_USB_RVP

C5

PP_TRISTAR_ACC1

E5

PP_TRISTAR_ACC2

A2

90_TRISTAR_DP1_CONN_P

B2

90_TRISTAR_DP1_CONN_N

A4

90_TRISTAR_DP2_CONN_P

B4

90_TRISTAR_DP2_CONN_N

E3

TRISTAR_CON_DETECT_L

D6

TRISTAR_TO_TIGRIS_VBUS_OFF

POW_GATE_EN* is 6V-tolerant

E4

PMU_TO_AOP_TRISTAR_ACTIVE_READY

B6

TRISTAR_TO_PMU_HOST_RESET

D3

I2C0_AP_SDA

D4

I2C0_AP_SCL

C6

TRISTAR_TO_AOP_INT

E6

TRISTAR_BYPASS

1

C4005

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=TRISTAR

20

47

47

13

41 4

41 4

41 4

41 4

41 4

41 4

PP4001

37 20 13 7

P2MM-NSM

SM

1

PP

1

C4006

1UF

20%
16V

2

CER-X5R
0201

ROOM=TRISTAR

41 4

#25714843: Remove R4003 Weak PD

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

D

C

B

34567 8

ANTENNA LOWER MIC1/4

Please loop in Matt Mow (Antenna Team)
when changing these components!

150OHM-25%-200MA-0.7DCR

53 40 29 19

32 21 20 18 16
48 47 40 37 36

C4109

ROOM=DOCK_B2B

PP3V0_TRISTAR_ANT_PROX

53 52

PP1V8_SDRAM

BB_TO_LAT_ANT_SCLK

53

VOLTAGE=14.0V

40 21 4

0.1UF

10%
25V
X5R

0201

PP5V0_USB

1

C4105

0.1UF

2

ROOM=DOCK_B2B

10%
25V
X5R

0201

1

2

10%
25V
X5R

0201

1

2

C4106

0.1UF

ROOM=DOCK_B2B

150OHM-25%-200MA-0.7DCR

C4107

330PF

ROOM=DOCK_B2B

FL4103

2 1

01005

ROOM=DOCK_B2B

FL4107

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4108

2 1

01005

ROOM=DOCK_B2B

R4109

0.00

1/32W

01005

ROOM=DOCK_B2B

21

0%

MF

R4110

0.00

1/32W

01005

ROOM=DOCK_B2B

1

10% 10%
16V

CER-X7R

01005

2

21

0%

MF

C4108

330PF

16V

CER-X7R

01005

ROOM=DOCK_B2B

1

2

1

C4134

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DOCK_B2B

1

C4119

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DOCK_B2B

1

C4120

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DOCK_B2B

1

C4121

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=DOCK_B2B

1

C4122

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=DOCK_B2B

PP3V0_LAT_CONN

PP3V0_LAT1_CONN

VOLTAGE=3.0V

PP1V8_LAT_ARC_CONN

BB_TO_LAT_ANT_SCLK_CONN

BB_TO_LAT_ANT_DATA_CONNBB_TO_LAT_ANT_DATA

J4101

245857

F-ST-SM

53

5049

41

41

41

41 53

41

ARC CONTROL

#26118161: Update FL4104 to 49.9ohm

I2C_HOMER_SCL

47 36

I2C_HOMER_SDA

47 36

ARC1

ARC1_TO_SOLENOID1_OUT_POS

41 35

ARC1_TO_SOLENOID1_OUT_NEG

41 35

Antenna GPIO

BB_TO_LAT_GPO1

53

BB_TO_LAT_GPO2

53

R4104

49.9

1/32W

01005

ROOM=DOCK_B2B

21

1%

MF

FL4112

150OHM-25%-200MA-0.7DCR

21

01005

C4101

220PF

5%

10V

C0G-CERM

01005

ROOM=DOCK_B2B

FL4101

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4102

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

Per ANT Erdinc, change to cap

1

C4135

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DOCK_B2B

1

C4136

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DOCK_B2B

1

2

1

C4110

2

ROOM=DOCK_B2B

1

C4111

2

ROOM=DOCK_B2B

C4102

220PF

C0G-CERM

ROOM=DOCK_B2B

56PF

5%
25V
NP0-C0G-CERM
01005

56PF

5%
25V
NP0-C0G-CERM
01005

I2C_HOMER_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_HOMER_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

1

5%

10V

2

01005

BB_TO_LAT_GPO1_CONN

BB_TO_LAT_GPO2_CONN

41

41

41

41

SPEAKER1

SPEAKER_TO_SPEAKERAMP1_VSENSE_P

34

SPEAKER_TO_SPEAKERAMP1_VSENSE_N

34

LOWERMIC1_TO_CODEC_AIN1_P

31

LOWERMIC1_TO_CODEC_AIN1_N

31

PP_CODEC_TO_LOWERMIC1_BIAS

32

LOWERMIC4_TO_CODEC_AIN2_P

31

LOWERMIC4_TO_CODEC_AIN2_N

31

PP_CODEC_TO_LOWERMIC4_BIAS

32

SPEAKERAMP1_TO_SPEAKER_OUT_POS

41 34

2 1

FL4116

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4117

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4118

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4119

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4120

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4121

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4114

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

FL4115

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

LOWERMIC1_TO_CODEC_AIN1_CONN_POS

1

2

LOWERMIC1_TO_CODEC_AIN1_CONN_NEG

1

2

PP_CODEC_TO_LOWERMIC1_BIAS_CONN

1

2

LOWERMIC4_TO_CODEC_AIN2_CONN_POS

1

2

LOWERMIC4_TO_CODEC_AIN2_CONN_NEG

1

2

PP_CODEC_TO_LOWERMIC4_BIAS_CONN

1

2

SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS

1

2

SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG

1

2

1

2

C4128

56PF

5%
25V

NP0-C0G-CERM
01005

ROOM=DOCK_B2B

C4129

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=DOCK_B2B

C4130

220PF

5%
10V

C0G-CERM
01005

ROOM=DOCK_B2B

C4131

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=DOCK_B2B

C4132

56PF

5%
25V

NP0-C0G-CERM
01005

ROOM=DOCK_B2B

C4133

220PF

5%
10V
C0G-CERM
01005

ROOM=DOCK_B2B

C4126

220PF

5%
10V
C0G-CERM
01005

ROOM=DOCK_B2B

C4127

220PF

5%
10V
C0G-CERM
01005

ROOM=DOCK_B2B

C4103

220PF

5%
10V
C0G-CERM
01005

ROOM=DOCK_B2B

41

41

D

41

41

41

C

41

41

41

B

A

SPEAKERAMP1_TO_SPEAKER_OUT_NEG

41 34

SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG

41

BB_TO_LAT_GPO3_CONN

46

LOWERMIC4_TO_CODEC_AIN2_CONN_NEG

41

PP_CODEC_TO_LOWERMIC4_BIAS_CONN

41

PP_TRISTAR_ACC1_CONN

41

#22499940:Change Net Name to POS/NEG

90_TRISTAR_DP2_CONN_P

40 4

90_TRISTAR_DP2_CONN_N

40 4

90_TRISTAR_DP1_CONN_N

40 4

90_TRISTAR_DP1_CONN_P

40 4

MIKEYBUS_REFERENCE

31

LOWERMIC1_TO_CODEC_AIN1_CONN_POS LOWERMIC1_TO_CODEC_AIN1_CONN_NEG

41 41

LOWERMIC1_TO_CODEC_BIAS_FILT_RET

32

I2C_MIC1_SDA_CONN

47

I2C_MIC1_SCL_CONN

47

ARC1_TO_SOLENOID1_OUT_POS

41 35

SOLENOID1_TO_ARC1_VSENSE_POS

35

PP3V0_LAT_CONN

41

SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS

41

SPEAKERAMP1_TO_SPEAKER_OUT_POS

41 34

DOCK FLEX CONNECTOR

54

SPEAKERAMP1_TO_SPEAKER_OUT_NEG

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241
4443
4645
4847

5251

PP_TRISTAR_ACC2_CONN
BB_TO_LAT_GPO2_CONN

LOWERMIC4_TO_CODEC_AIN2_CONN_POS
LOWERMIC4_TO_CODEC_BIAS_FILT_RET
BB_TO_LAT_GPO1_CONN
BB_TO_LAT_ANT_SCLK_CONN
BB_TO_LAT_ANT_DATA_CONN
PP1V8_LAT_ARC_CONN

PP3V0_LAT1_CONN

PP_CODEC_TO_LOWERMIC1_BIAS_CONN
TRISTAR_CON_DETECT_CONN_L

ARC1_TO_SOLENOID1_OUT_NEG
ARC1_TO_SOLENOID1_OUT_POS
SOLENOID1_TO_ARC1_VSENSE_NEG
I2C_HOMER_SDA_CONN

I2C_HOMER_SCL_CONN

#25429221:Carrier Dock flex to add +1 ACC2 pin

41

41

41

32

41

41

41

41

41

41

41

41 35

41 35

35

41

41

TRISTAR

R4102

1.00K

TRISTAR_CON_DETECT_L

40 4

PP_TRISTAR_ACC1

40 4

FL4106

22-OHM-25%-1800MA

PP_TRISTAR_ACC2 PP_TRISTAR_ACC2_CONN

40 4 41

0201

ROOM=DOCK_B2B

#25098110: Decrease DCR

2 1

5%

1/32W

MF

01005

ROOM=DOCK_B2B

FL4105

10-OHM-1.1A

21

01005

ROOM=DOCK_B2B

21

1

C4116

27PF

5%
16V

2

NP0-C0G
01005

ROOM=DOCK_B2B

1

C4117

100PF

5%
16V

2

NP0-C0G
01005

ROOM=DOCK_B2B

1

C4118

100PF

5%
16V

2

NP0-C0G
01005

ROOM=DOCK_B2B

TRISTAR_CON_DETECT_CONN_L

PP_TRISTAR_ACC1_CONN

41 34

VOLTAGE=4.3V

VOLTAGE=4.3V

41

41

1

C4104

220PF

5%
10V

2

C0G-CERM
01005

ROOM=DOCK_B2B

USB AC Coupling

AC return path for USB pairs which is referenced to GND and VDD_MAIN

53

27 26 25 23 21 19 18 10 9 4

52 46 40 39 37 35 34 33 31 28

PP_VDD_MAIN

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

1

2

C4143

220PF

5%
10V
C0G-CERM
01005

ROOM=SOC

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

STROBE1

PP_STROBE_DRIVER1_WARM_LED

ROOM=RIGHT_BUTTON

PP_STROBE_DRIVER1_COOL_LED

ROOM=RIGHT_BUTTON

150OHM-25%-200MA-0.7DCR

STROBE_MODULE_NTC

26

R4401

27K

0.5%

1/32W

ROOM=RIGHT_BUTTON

#24544474: Can R4401 be changed to 5%?

01005

C4402

220PF

5%

10V

C0G-CERM

01005

C4406

220PF

5%

10V

C0G-CERM

01005

1

MF

2

1

2

1

2

FL4404

01005

ROOM=RIGHT_BUTTON

BUTTONSSTROBE2

R4402

45 26

1

C4409

27PF

5%
16V

2

NP0-C0G
01005

ROOM=RIGHT_BUTTON

45 26

1

C4408

27PF

5%
16V

2

NP0-C0G
01005

ROOM=RIGHT_BUTTON

21

1

C4407

220PF

5%
10V

2

C0G-CERM
01005

STROBE_MODULE_NTC_CONN

ROOM=RIGHT_BUTTON

45

PP_STROBE_DRIVER2_WARM_LED

C4410

220PF

10V

C0G-CERM

01005

ROOM=RIGHT_BUTTON

PP_STROBE_DRIVER2_COOL_LED

C4411

220PF

10V

C0G-CERM

01005

ROOM=RIGHT_BUTTON

5%

5%

1

2

1

2

1

C4413

27PF

5%
16V

2

NP0-C0G
01005

ROOM=RIGHT_BUTTON

1

C4412

27PF

5%
16V

2

NP0-C0G
01005

ROOM=RIGHT_BUTTON

45 26

45 26

BUTTON_POWER_KEY_L

20

ROOM=RIGHT_BUTTON

ROOM=LEFT_BUTTON

BUTTON_VOL_DOWN_L

20

ROOM=LEFT_BUTTON

C4401

27PF

5%

6.3V

NP0-C0G

0201

C4418

27PF

5%

6.3V

NP0-C0G

0201

C4419

100PF

5%

16V

NP0-C0G

01005

1

2

1

2

1

2

100

1/32W

01005

ROOM=RIGHT_BUTTON

FL4407

120-OHM-0.220A

ROOM=LEFT_BUTTON

ROOM=LEFT_BUTTON

21

5%

MF

01005

R4405

100

21

5%

1/32W

MF

01005

BUTTON_POWER_KEY_CONN_L

1

0201

45

5.5V-6.2PF

DZ4401

ROOM=RIGHT_BUTTON

2

CHASSIS_GND_BS401

21

1

0201

BUTTON_RINGER_A_CONNBUTTON_RINGER_A

44 4

45 20

D

5.5V-6.2PF

DZ4402

ROOM=LEFT_BUTTON

2

CHASSIS_GND_BS401

1

DZ4403

12V-33PF

01005-1

ROOM=LEFT_BUTTON

2

CHASSIS_GND_BS401

BUTTON_VOL_DOWN_CONN_L

44 4

45

44 4

C

HAWKING

31

31

HAWKING_TO_CODEC_AIN7_N

#24678255:DOE with 10% and/20% cap

C4417

0.22UF

21

20%

6.3V
X5R

01005

ROOM=RIGHT_BUTTON

C4421

0.22UF

21

20%

6.3V
X5R

01005

ROOM=RIGHT_BUTTON

HAWKING_TO_CODEC_AIN7_C_PHAWKING_TO_CODEC_AIN7_P

CKPLUS_WAIVE=MISS_N_DIFFPAIR

FL4405

150OHM-25%-200MA-0.7DCR

21

01005

ROOM=RIGHT_BUTTON

HAWKING_TO_CODEC_AIN7_N_CONN

HAWKING_TO_CODEC_AIN7_P_CONN

NOSTUFF

1

C4415

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=RIGHT_BUTTON

1

C4422

180PF

10%
10V

2

CERM
01005

ROOM=RIGHT_BUTTON

45

45

BUTTON_VOL_UP_L

20 12

C4420

100PF

NP0-C0G

01005

ROOM=LEFT_BUTTON

5%

16V

R4406

1

ROOM=LEFT_BUTTON

2

100

5%

1/32W

MF

01005

C

21

1

DZ4404

12V-33PF

01005-1

ROOM=LEFT_BUTTON

2

BUTTON_VOL_UP_CONN_L

CHASSIS_GND_BS401

45

44 4

B

MIC2 (ANC REF)

32

PP_CODEC_TO_REARMIC2_BIAS

19

PP1V8_HAWKING

FL4403

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=RIGHT_BUTTON

FL4406

150OHM-25%-200MA-0.7DCR

21

01005

ROOM=RIGHT_BUTTON

PP_CODEC_TO_REARMIC2_BIAS_CONN

1

C4403

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RIGHT_BUTTON

PP1V8_HAWKING_CONN

1

C4416

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RIGHT_BUTTON

45

1

C4414

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RIGHT_BUTTON

45

B

A

REARMIC2_TO_CODEC_AIN3_P

31

FL4401

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=RIGHT_BUTTON

1

2

FL4402

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=RIGHT_BUTTON

1

2

REARMIC2_TO_CODEC_AIN3_CONN_P

C4404

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=RIGHT_BUTTON

REARMIC2_TO_CODEC_AIN3_CONN_NREARMIC2_TO_CODEC_AIN3_N

C4405

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=RIGHT_BUTTON

45

45 31

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

UTAH-C FLEX CONNECTOR

THIS ONE ---> 516S00152 RCPT (USED ON MLB)

516S00151 PLUG

PP1V2_UT_VDD_CONN

25

LPDP_UT_BI_AP_AUX_CONN

25

AP_TO_UT_SHUTDOWN_CONN_L

25

UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN

25

I2C_UT_SDA_CONN

48

I2C_UT_SCL_CONN

48

PP3V0_UT_SVDD_CONN

25

PP2V9_UT_AVDD_CONN

46 25

PP1V8_UT_CONN

25

PP2V8_UT_AF_VAR_CONN

25

J4501

AA26D-S022VA1

F-ST-SM

ROOM=RCAM_B2B

24 23

2 1

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

26 25

90_LPDP_UT_TO_AP_D0_CONN_N
90_LPDP_UT_TO_AP_D0_CONN_P

90_LPDP_UT_TO_AP_D1_CONN_N
90_LPDP_UT_TO_AP_D1_CONN_P

AP_TO_UT_CLK_CONN

25

25

25

25

25

MAKE_BASE=TRUE

COMBINED BUTTON FLEX CONNECTOR

MLB APN: 516S00150

FLEX APN: 516S00149

J4504

GND

PP_CODEC_TO_REARMIC2_BIAS_CONN

44

44

REARMIC2_TO_CODEC_AIN3_CONN_N

REARMIC2_TO_CODEC_AIN3_CONN_P

44

REARMIC2_TO_CODEC_BIAS_FILT_RET

32

I2C_MIC2_SDA_CONN

47

I2C_MIC2_SCL_CONN

47

BUTTON_POWER_KEY_CONN_L

44

AA37D-S014SVA1

F-ST-SM

2019

1615

PP_STROBE_DRIVER2_COOL_LED

21

43

65

87

109

1211

1413

STROBE_MODULE_NTC_CONN
PP1V8_HAWKING_CONN

HAWKING_TO_CODEC_AIN7_P_CONN

BUTTON_RINGER_A_CONN
BUTTON_VOL_UP_CONN_L
BUTTON_VOL_DOWN_CONN_L

THIS PAGE UNIQUE TO SMALL FORM FACTOR

44 26

44

44

44

44

44

44

XW4501

SHORT-20L-0.05MM-SM

21

ROOM=RIGHT_BUTTON

HAWKING_TO_CODEC_AIN7_N_CONN

D

44

C

DISPLAY / TOUCH FLEX CONNECTOR

THIS ONE --->

#24543369: Keep PP

PP4501

P2MM-NSM

ROOM=TEST

LCM_TO_MAMBA_MSYNC_CONN

38

SM

PP

1

C4507

56PF

5%
25V

2

NP0-C0G-CERM
01005

516S00138 RCPT (USED ON MLB)
516S00137 PLUG

PP5V7_LCM_AVDDH_CONN

39

PP5V7_MESON_AVDDH_CONN

39

PN5V7_LCM_MESON_AVDDN_CONN

39

PP1V8_LCM_CONN

39

PP1V8_TOUCH_CONN

39

PP5V1_TOUCH_VDDH_CONN

39

TOUCH_TO_AP_INT_L_CONN

1

39

SPI_AP_TO_TOUCH_CS_CONN_L

39

UART_AOP_TO_TOUCH_TXD_CONN

39

TP_LCM_PIFA

PMU_TO_LCM_PANICB_CONN

39

UART_TOUCH_TO_AOP_RXD_CONN

39

LCM_TO_CHESTNUT_PWR_EN_CONN

39

MAMBA_TO_LCM_MDRIVE

38

ROOM=DISPLAY_B2B

AP_TO_LCM_RESET_CONN_L

39

PP_LCM_BL_CAT1_CONN

39 4

PP_LCM_BL_ANODE_CONN

39 4

PP_LCM_BL_CAT2_CONN

39 4

#25614112: Remove PP1V8_EEPROM Support

10MA

50MA

20MA

20MA

70MA

10MA

100MA

200MA

100MA

J4502

BB35C-RA40-3A

F-ST-SM

45

4241

21

43

65

87

109

1211

1413

1615

1817

2019

2221

2423

2625

2827

3029

3231

3433

3635

3837

4039

I2C_DISP_EEPROM_SDA_CONN
I2C_DISP_EEPROM_SCL_CONN

I2C_TOUCH_BI_MAMBA_SDA

I2C_TOUCH_SCL_CONN
AP_TO_TOUCH_MAMBA_RESET_CONN_L
SPI_TOUCH_TO_AP_MISO_CONN
SPI_AP_TO_TOUCH_SCLK_CONN
AP_TO_CUMULUS_CLK_32K_CONN
SPI_AP_TO_TOUCH_MOSI_CONN
LCM_TO_MANY_BSYNC_CONN

90_MIPI_AP_TO_LCM_DATA0_CONN_P
90_MIPI_AP_TO_LCM_DATA0_CONN_N

90_MIPI_AP_TO_LCM_DATA1_CONN_P
90_MIPI_AP_TO_LCM_DATA1_CONN_N

90_MIPI_AP_TO_LCM_CLK_CONN_P
90_MIPI_AP_TO_LCM_CLK_CONN_N

47

47

47

39

39

39

39

39

39

39

39

39

39

39

PP_STROBE_DRIVER1_COOL_LED

44 26

PP_STROBE_DRIVER1_WARM_LED

44 26

1817

2221

PP_STROBE_DRIVER2_WARM_LED

44 26

C

R4501

49.9

2 1

39 38

ROOM=DISPLAY_B2B

1%

1/32W

MF

01005

I2C_TOUCH_TO_MAMBA_SCL

47

B

FOREHEAD FLEX CONNECTOR

THIS ONE --->

516S00146 RCPT (USED ON MLB)
516S00145 PLUG

4443

46

J4503

245858036201829

F-ST-SM

41

3837

B

A

29

PP2V9_NH_AVDD_CONN
PP1V8_NH_IO_CONN

29

29

AP_TO_NH_SHUTDOWN_CONN_L
AP_TO_NH_CLK_CONN

29

29

SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P

29

PP3V0_ALS_CONVOY_CONN

47

I2C_ALS_CONVOY_SCL_CONN

48

I2C_PROX_SCL_CONN
PROX_BI_AP_AOP_INT_PWM_L_CONN

29

29

PDM_CONVOY_TO_ADARE_DATA_CONN

29

FRONTMIC3_TO_CODEC_AIN4_CONN_N

29

PP3V0_PROX_CONN

29

PDM_ADARE_TO_CONVOY_CLK_CONN

PP_CODEC_TO_FRONTMIC3_BIAS_CONN

29

29

FRONTMIC3_TO_CODEC_AIN4_CONN_P

42

CRITICAL

ROOM=FOREHEAD

21

43

65

87

109

1211

1413

1615

1817

2019

2221

2423

2625

2827

3029

3231

3433

3635

4039

90_MIPI_NH_TO_AP_DATA0_P
90_MIPI_NH_TO_AP_DATA0_N

90_MIPI_NH_TO_AP_CLK_P
90_MIPI_NH_TO_AP_CLK_N

90_MIPI_NH_TO_AP_DATA1_P
90_MIPI_NH_TO_AP_DATA1_N

PP1V2_NH_DVDD_CONN

I2C_NH_SCL_CONN

I2C_NH_SDA_CONN
SPEAKERAMP2_TO_SPEAKER_OUT_POS
SPEAKERAMP2_TO_SPEAKER_OUT_NEG

SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N
ALS_TO_AP_INT_CONN_L

I2C_ALS_CONVOY_SDA_CONN

I2C_PROX_SDA_CONN

9

9

9

9

9

9

29

48

48

29

29

47

48

A

46 33 29

46 33 29

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

D

8 7 5 4 2 1

36

#26682438:Move to Page 46

34567 8

2 1

THIS PAGE UNIQUE TO SMALL FORM FACTOR

OTHER SMALL FORM FACTOR SPECIFIC PAGES:

4 - MECHANICAL

D

ISP I2C1

25 18 17 16 13 12 11 9 8 7 5

I2C_ISP_NV_SCL

9

I2C_ISP_NV_SDA

9

52 48 47 39 29

UT B2B

PP1V8

1

R4603

2.2K

5%
1/32W
MF

ROOM=SOC

2

1

R4604

2.2K

5%
1/32W
MF
0100501005

ROOM=SOC

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

I2C_ISP_NV_SCL
I2C_ISP_NV_SDA

26

26

47 39 38 18

TOUCH I2C

PP1V8_TOUCH

NOSTUFF

1

R4711

10K

5%
1/32W
MF
01005

2

ROOM=MAMBA_MESA

I2C_TOUCH_TO_MAMBA_SCL

47

10

NC_AP_LPDP_AUX2

NC Nets in Small FF

NC_90_LPDP_NV_TO_AP_D2_P

10

NC_90_LPDP_NV_TO_AP_D2_N

10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_AP_LPDP_AUX2

NC_90_LPDP_NV_TO_AP_D2_P

NC_90_LPDP_NV_TO_AP_D2_N

D

C

PP2V9_UT_AVDD_CONN

45 25

VDD_MAIN Cap

28 27 26 25 23 21 19 18 10 9 4

52 46 41 40 39 37 35 34 33 31

VOLTAGE=10V

ROOM=BACKLIGHT

53

C4601

10UF

20%

X5R-CERM

0402-8

C2531

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=RCAM_B2B

C2507

1

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

#26634069:D10x Only, 5x VDD_MAIN CAPS Change to 10UF/10V

PP_VDD_MAIN

1

2

C2113

10UF

20%
10V

X5R-CERM

ROOM=CHARGER

0402-8

1

2

Pg34

C3424

10UF

20%
10V

X5R-CERM

0402-8

ROOM=SPKAMP1

1

C3530

10UF

2

X5R-CERM

0402-8

ROOM=ARC1

20%
10V

1

2

Pg37Pg35Pg21

C3722

10UF

X5R-CERM

ROOM=CHESTNUT

0402-8

20%
10V

NC_90_LPDP_NV_TO_AP_D3_P

10

NC_90_LPDP_NV_TO_AP_D3_N

10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_90_LPDP_NV_TO_AP_D3_P

NC_90_LPDP_NV_TO_AP_D3_N

C

Top Speaker Compass Coil

SPEAKERAMP2_TO_SPEAKER_OUT_POS
SPEAKERAMP2_TO_SPEAKER_OUT_NEG

1

2

1

R3332

910

1%
1/32W
TK
01005

2

ROOM=SPKAMP2

45 33 29

1

R3333

910

1%
1/32W
TK
01005

2

ROOM=SPKAMP2

45 33 29

B

#25742582,Add back C3531 in layout at ARC

53 52

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

PP_VDD_MAIN

C3531

10UF

20%
10V

X5R-CERM

0402-8

ROOM=ARC1

1

2

#26104509:C3525 Change to 1UF 0201 in DVT

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 52

PP_VDD_MAIN

C3525

1.0UF

20%

6.3V
X5R

0201-1

ROOM=ARC1

NEG_COMPASS_COIL_COMP POS_COMPASS_COIL_COMP

1

XW3333

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

ROOM=MAMBA_MESA

2

1

C3332

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SPKAMP2

1

2

OMIT

1

C3333

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SPKAMP2

B

A

Dock B2B (Pg 41)

53

BB_TO_LAT_GPO3

FL4604

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DOCK_B2B

1

2

C4608

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=DOCK_B2B

BB_TO_LAT_GPO3_CONN

41

40 27 19

ACC Buck Caps

PP_ACC_VAR

1

C2707

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=TRISTAR

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

AP

25 18 17 16 13 12 11 9 8 7 5

I2C0

I2C1

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

I2C0_AP_SCL

11

I2C0_AP_SDA

11

52 48 47 46 39 29

PP1V8

1%

1/32W

MF

01005

1

2

R4701

4.02K

ROOM=SOC

#24544434

PP1V8

R4703

4.02K

1%

1/32W

MF

01005

ROOM=SOC

1

2

R4702

4.02K

1%

1/32W

MF

01005

ROOM=SOC

NOSTUFF

NP0-C0G-CERM

R4704

4.02K

1%

1/32W

MF

01005

ROOM=SOC

1

2

C4701

56PF

01005

ROOM=SOC

1

2

5%

25V

TOUCH

46 39 38 18

#26682438:Move to Page 46

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NOSTUFF

C4702

1

2

1

56PF

5%

2

25V

NP0-C0G-CERM
01005

ROOM=SOC

I2C0_AP_SCL
I2C0_AP_SDA

I2C0_AP_SCL
I2C0_AP_SDA

I2C0_AP_SCL
I2C0_AP_SDA

I2C0_AP_SCL
I2C0_AP_SDA

37

37

23

23

40

40

20 37

37

PP1V8_TOUCH

NOSTUFF

1

R4712

10K

5%
1/32W
MF

01005

2

ROOM=MAMBA_MESA

I2C_TOUCH_TO_MAMBA_SCL

46

I2C_TOUCH_BI_MAMBA_SDA

NOTE:MAMBA I2C 2.2K PULL-UPS TO PP1V8_TOUCH INSIDE GALILEO
ADDING R3803, R3804 AS OPTION FOR TWEAKING VALUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NOSTUFF

C4709

NP0-C0G-CERM

ROOM=MAMBA_MESA

C4711

56PF

NP0-C0G-CERM

ROOM=DISPLAY_B2B

01005

56PF

5%

25V

01005

5%

25V

I2C_TOUCH_TO_MAMBA_SCL
I2C_TOUCH_BI_MAMBA_SDA

NOSTUFF

1

2

1

2

1

C4710

56PF

5%

2

25V

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

I2C_TOUCH_TO_MAMBA_SCL
I2C_TOUCH_BI_MAMBA_SDA

1

C4712

56PF

5%

2

25V

NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

TO MAMBA / MESA FLEX

38

38

TO DISPLAY / TOUCH FLEX

45

45

D

C

I2C1_AP_SCL

11

I2C1_AP_SDA

11

#24544426

I2C2

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

NOSTUFF

C4703

56PF

5%

NP0-C0G-CERM

PP1V8

R4705

2.2K

ROOM=SOC

01005

ROOM=PMU

5%

1/32W

MF

01005

25V

1

2

1

2

R4706

1

2

2.2K

1/32W

01005

ROOM=SOC

5%

MF

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NOSTUFF

C4704

56PF

5%

25V

NP0-C0G-CERM
01005

ROOM=PMU

1

2

I2C1_AP_SCL
I2C1_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

D11/111 ONLY

20

20

21

21

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

PP1V8

I2C3

HOMER

48 41 40 37 36 32 21 20 18 16

53 52

PP1V8_SDRAM

1

R4713

1.00K

5%
1/32W
MF

2

01005

ROOM=HOMER

1

R4714

1.00K

5%
1/32W
MF

2

01005

ROOM=HOMER

I2C_HOMER_SCL
I2C_HOMER_SDA

I2C5

25 18 17 16 13 12 11 9 8 7 5

41 36

41 36

52 48 47 46 39 29

R4715

2.2K

5%

1/32W

MF

01005

ROOM=SOC

PP1V8

1

2

R4716

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

I2C5_SCL
I2C5_SDA

11

11

C

B

I2C2_AP_SCL

11

I2C2_AP_SDA

11

MAKE_BASE=TRUE

MAKE_BASE=TRUE

ROOM=FOREHEAD

R4707

0.00

0% MF

1/32W 01005

21

R4708

0.00

0%

1/32W

ROOM=FOREHEAD

21

MF

01005

I2C2_AP_SCL
I2C2_AP_SDA

C4707

56PF

5%

NP0-C0G-CERM

ROOM=FOREHEAD

25V

01005

I2C_ALS_CONVOY_SCL_CONN

I2C_ALS_CONVOY_SDA_CONN

1

2

1

C4708

56PF

5%

2

25V
NP0-C0G-CERM
01005

ROOM=FOREHEAD

TO FOREHEAD FLEX

33

33

45

45

11

I2C3_AP_SCL

11

I2C3_AP_SDA

R4709

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R4710

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

ROOM=DOCK

2

150OHM-25%-200MA-0.7DCR

#26633265:mitigate MIC1 undershoot

FL4730

2 1

01005

FL4729

100

2 1

5%

1/32W

MF

01005

ROOM=DOCK

ROOM=RIGHT_BUTTON

C4730

56PF

5%

NP0-C0G-CERM

ROOM=DOCK_B2B

25V

01005

ckplus_waive=I2C_PULLUP

I2C_MIC1_SCL_CONN

41

TO DOCK FLEX

CKPLUS_WAIVE=I2C_PULLUP

I2C_MIC1_SDA_CONN

1

2

1

C4729

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DOCK_B2B

41

B

FL4732

150OHM-25%-200MA-0.7DCR

2 1

01005

FL4731

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=RIGHT_BUTTON

C4732

56PF

NP0-C0G-CERM

01005

5%

25V

1

2

I2C_MIC2_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_MIC2_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

1

C4731

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=RIGHT_BUTTONROOM=RIGHT_BUTTON

45

TO COMBINED BUTTON FLEX

45

A

FL4742

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DISPLAY_B2B

FL4741

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=DISPLAY_B2B

1

2

8 7 5 4 2 1

I2C_DISP_EEPROM_SCL_CONN

I2C_DISP_EEPROM_SDA_CONN

1

C4742

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

C4741

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=DISPLAY_B2B

45

TO DISPLAY FLEX

45

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

36

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

AOP

47 41 40 37 36 32 21 20 18 16

53 52 48

I2C

I2C_AOP_SCL

D

#24958320:Intentional R4815 Change

Reduce undershoot when Prox Driving

C

B

13

13

I2C_AOP_SDA

PP1V8_SDRAM

1

R4801

2.2K

5%
1/32W
MF
01005

2

47 41 40 37 36 32 21 20 18 16

1

R4802

2.2K

5%
1/32W
MF
01005

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

53 52 48

Intentional R4815 Change

AOP_TO_MESA_I2C_ISO_EN

13

PP1V8_SDRAM

1

C4807

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

U4802

MAX20312

A2

B2

IOVCC1

IOVCC2

WLP

ROOM=SOC

I2C_AOP_SCL
I2C_AOP_SDA

I2C_AOP_SCL
I2C_AOP_SDA

ROOM=FOREHEAD

FL4815

150OHM-25%-200MA-0.7DCR

2 1

01005

R4815

33.2

2 1

1%

1/32W

MF

01005

ROOM=FOREHEAD

6

S

4 1

Z

1

R4805

511K

1%
1/32W
MF
01005

2

6

S

4 1

Z

B1

VCC

GND

A1

34

34

35

35

1

2

PP1V8_SDRAM

5

VCC

U4805

74LVC1G3157GX

X2SON6

GND

2

PP1V8_SDRAM

5

VCC

U4806

74LVC1G3157GX

X2SON6

GND

2

#24544699: Support 1MHz

TO FCAM FLEX

I2C_PROX_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_PROX_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

C4803

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=FOREHEAD

3

Y0

Y1

Y0

Y1

NC

I2C_AOP_SCL_ISO

3

NC

I2C_AOP_SDA_ISO

1

C4804

56PF

5%
25V
NP0-C0G-CERM

2

01005

ROOM=FOREHEAD

53 52 48

53 52 48

38 19

47 41 40 37 36 32 21 20 18 16

47 41 40 37 36 32 21 20 18 16

PP1V8_MESA

1

R4803

4.7K

1%
1/32W
MF
01005

2

ROOM=MAMBA_MESA

45

45

1

R4804

4.7K

1%
1/32W
MF
01005

2

ROOM=MAMBA_MESA

R4806

0.00

2 1

1/32W0%
01005MF

R4807

0.00

2 1

0%

1/32W

MF

01005

ROOM=MAMBA_MESA

ROOM=MAMBA_MESA

ISP

I2C0

25 18 17 16 13 12 11 9 8 7 5

I2C_ISP_UT_SCL

9

I2C_ISP_UT_SDA

9

I2C1

See page 46

I2C2

25 18 17 16 13 12 11 9 8 7 5

I2C_ISP_NH_SCL

9

I2C_ISP_NH_SDA

9

I2C_MESA_TURTLE_SCL_CONN

I2C_MESA_TURTLE_SDA_CONN

52 48 47 46 39 29

1

C4809

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

1

C4810

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=MAMBA_MESA

52 48 47 46 39 29

PP1V8

PP1V8

1

2

1

R4810

5%
1/32W
MF
01005

2

ROOM=SOC

TO MAMBA/MESA FLEX

R4808

1.00K

5%
1/32W
MF
01005

ROOM=SOC

1

R4811

5%
1/32W
MF
01005

2

38

38

2.2K2.2K

ROOM=SOC

#24550735: ISP I2C0 PU

1

R4809

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

R4816

0.00

1/32W

01005

ROOM=RCAM_B2B

R4817

0.00

1/32W

01005

ROOM=RCAM_B2B

21

0%

MF

21

0%

MF

R4812

0.00

0%

1/32W

MF

01005

ROOM=FOREHEAD

R4813

0.00

0%

1/32W

MF

01005

ROOM=FOREHEAD

I2C_ISP_UT_SCL
I2C_ISP_UT_SDA

1

C4817

56PF

5%

2

25V
NP0-C0G-CERM
01005

ROOM=RCAM_B2B

1

C4816

56PF

5%
25V

NP0-C0G-CERM

2

01005

ROOM=RCAM_B2B

21

1

C4812

56PF

5%

2

25V
NP0-C0G-CERM
01005

ROOM=FOREHEAD

21

1

C4813

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=FOREHEAD

26

26

I2C_UT_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_UT_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_NH_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_NH_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

D

45

45

45

C

45

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

D

This page contains items which differ accross all MLB designs

PCIe lanes

PP0801

P2MM-NSM

ROOM=SOC

SM

PP0802

P2MM-NSM

ROOM=SOC

SM

PP

PP

1

90_AP_PCIE3_RXD_C_P
90_AP_PCIE3_RXD_C_N

1

52 8

52 8

34567 8

2 1

D

C

90_AP_PCIE2_RXD_C_P

8

90_AP_PCIE2_RXD_C_N

8

90_AP_PCIE2_TXD_C_P

8

90_AP_PCIE2_TXD_C_N

8

25 18 17 16 13 12 11 9 8 7 5

PCIE_WLAN_BI_AP_CLKREQ_L

52

48 47 46 39 29

PP1V8

C0816

ROOM=SOC

C0817

ROOM=SOC

C0815

ROOM=SOC

C0818

ROOM=SOC

X5R-CERM

X5R-CERM

1

R0807

100K

5%
1/32W
MF
01005

2

ROOM=SOC

21

6.3V20%
01005

21

20% 6.3V

20% 6.3V

01005X5R-CERM

21

6.3V20%
01005

21

01005X5R-CERM

0.1UF

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

90_PCIE_BB_TO_AP_RXD_P

90_PCIE_BB_TO_AP_RXD_N

90_PCIE_AP_TO_BB_TXD_P

90_PCIE_AP_TO_BB_TXD_N

53

53

53

53

MAKE_BASE=TRUE

MAKE_BASE=TRUE

C

MAKE_BASE=TRUE

MAKE_BASE=TRUE

B

90_AP_PCIE3_RXD_C_P

8

90_AP_PCIE3_RXD_C_N

8

90_AP_PCIE3_TXD_C_P

8

90_AP_PCIE3_TXD_C_N

8

90_PCIE_AP_TO_WLAN_REFCLK_P

8

90_PCIE_AP_TO_WLAN_REFCLK_N

8

90_PCIE_AP_TO_BB_REFCLK_P

8

90_PCIE_AP_TO_BB_REFCLK_N

8

PCIE_AP_TO_WLAN_RESET_L

8

PCIE_AP_TO_BB_RESET_L

8

PCIE_WLAN_BI_AP_CLKREQ_L

8

PCIE_BB_BI_AP_CLKREQ_L

8

C0811

ROOM=SOC

C0812

ROOM=SOC

C0814

ROOM=SOC

C0813

ROOM=SOC

X5R-CERM

X5R-CERM

X5R-CERM 01005

21

20%

20%

20% 6.3V

20%

6.3V
01005

21

6.3V
01005

21

01005X5R-CERM

21

6.3V

0.1UF

0.1UF

0.1UF

0.1UF

90_PCIE_WLAN_TO_AP_RXD_P

GND_VOID=TRUE

90_PCIE_WLAN_TO_AP_RXD_N

GND_VOID=TRUE

90_PCIE_AP_TO_WLAN_TXD_P

GND_VOID=TRUE

90_PCIE_AP_TO_WLAN_TXD_N

GND_VOID=TRUE

90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N
90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N

PCIE_AP_TO_WLAN_RESET_L
PCIE_AP_TO_BB_RESET_L

PCIE_WLAN_BI_AP_CLKREQ_L
PCIE_BB_BI_AP_CLKREQ_L

53

53

53

53

53

53

53

53

53

53

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

53 52

53 52

MAKE_BASE=TRUE

47 41 40 37 36 32 21 20 18 16

53 48

PP1V8_SDRAM

R5206

100K

1/32W

01005

ROOM=RADIO_BB

1%

MF

B

1

#24556007:Parallel to 100kohm R5906_RF(nostuff)

2

A

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53

#25811920: D10 CRB: 2x 01005 Cap for Backlight Desense

D101 CRB: No additional Cap

PP_VDD_MAIN

1

C2619

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C2620

220PF

5%
10V

2

C0G-CERM
01005

ROOM=STROBEROOM=STROBE

PCIE_BB_BI_AP_CLKREQ_L

53 52

#24535235: D10 EVT 1x Desense Cap (68pF)
#24535276: D101 EVT 1x Desense Cap (220pF)

PP3V0_NAND

1

C1756

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

19 17

A

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36

34567 8

2 1

D

C

B

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

47 41 40 37 36 32 21 20 18 16

68 60 58 55 53 52 48

77 58 55 53 52

PP_VDD_MAIN
PP1V8_SDRAM

PMUGPIO_TO_WLAN_CLK32K

55 20

PMU_TO_WLAN_REG_ON

55 20

PMU_TO_BT_REG_ON

55 20

BT_TO_PMU_HOST_WAKE

55 20

AP_TO_BT_WAKE

55 12

90_PCIE_AP_TO_WLAN_REFCLK_P

55 52

90_PCIE_AP_TO_WLAN_REFCLK_N

55 52

90_PCIE_AP_TO_WLAN_TXD_P

55 52

90_PCIE_AP_TO_WLAN_TXD_N

55 52

90_PCIE_WLAN_TO_AP_RXD_P

55 52

90_PCIE_WLAN_TO_AP_RXD_N

55 52

PCIE_AP_TO_WLAN_RESET_L

55 52

PCIE_WLAN_BI_AP_CLKREQ_L

55 52

WLAN_TO_PMU_HOST_WAKE

55 20

AP_TO_WLAN_DEVICE_WAKE

55 12

UART_AP_TO_WLAN_TXD

55 12

UART_WLAN_TO_AP_RXD

55 12

UART_AP_TO_WLAN_RTS_L

55 12

UART_AP_TO_BT_TXD

55 12

UART_BT_TO_AP_RXD

55 12

UART_AP_TO_BT_RTS_L

55 12

UART_BT_TO_AP_CTS_L

55 12

AOP_TO_WLAN_CONTEXT_A

55 13

AOP_TO_WLAN_CONTEXT_B

55 13

I2S_AP_TO_BT_BCLK

55 11

I2S_AP_TO_BT_LRCLK

55 11

I2S_BT_TO_AP_DIN

55 11

I2S_AP_TO_BT_DOUT

55 11

59
56

50_UAT_WLAN_5G_WEST
50_UAT_WLAN_2G_EAST
50_LAT_WLAN_5G_EAST
50_LAT_WLAN_G_1

50_LAT_WLAN_A_1

50_UAT2_M

RADIO_MLB_FF

50_WLAN_A_1

50_WLAN_G_1

50_UAT_WLAN_5G_EAST

50_UAT_WLAN_2G_EAST

50_UAT_WLAN_5G_WEST

50_UAT2_M

FF SPECIFIC

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

47 41 40 37 36 32 21 20 18 16

68 60 58 55 53 52 48

77 58 55 53 52

PP_VDD_MAIN
PP1V8_SDRAM

I15

50_UAT_WLAN_2G_WEST_PLEXER

50_UUAT_LB_MLB_NORTH

50_UAT_MB_HB_SOUTH

50_UAT_LB_MLB_SOUTH

50_UAT1_WEST

50_UAT1_TUNER

PP3V0_TRISTAR_ARC_PROX

VDD_TUNER_RFFE_VIO_1V8

UAT_TUNER_RFFE_CLK

UAT_TUNER_RFFE_DATA

BUFFER_GPO1

BUFFER_GPO2

BB_TO_LAT_ANT_SCLK

BB_TO_LAT_ANT_SDATA

PP_VDD_MAIN

PP1V8_SDRAM

PMU_TO_WLAN_32K

PMU_TO_WLAN_REG_ON

PMU_TO_BT_REG_ON

BT_TO_PMU_HOST_WAKE

AP_TO_BT_WAKE

100_PCIE_AP_TO_WLAN_REFCLK_P

100_PCIE_AP_TO_WLAN_REFCLK_N

100_PCIE_AP_TO_WLAN_TX_P

100_PCIE_AP_TO_WLAN_TX_N

100_PCIE_WLAN_TO_AP_RX_P

100_PCIE_WLAN_TO_AP_RX_N

PCIE_AP_TO_WLAN_PERST_L

PCIE_AP_BI_WLAN_CLKREQ_L

PCIE_WLAN_TO_PMU_WAKE

AP_TO_WLAN_DEV_WAKE

UART_AP_TO_WLAN_TXD

UART_WLAN_TO_AP_RXD

UART_AP_TO_WLAN_RTS_L

UART_WLAN_TO_AP_CTS_L

UART_AP_TO_BT_TXD

UART_BT_TO_AP_RXD

UART_AP_TO_BT_RTS_L

UART_BT_TO_AP_CTS_L

AOP_TO_WLAN_CONTEXT_A

AOP_TO_WLAN_CONTEXT_B

I2S_AP_TO_BT_BCLK

I2S_AP_TO_BT_LRCK

I2S_BT_TO_AP_DIN

I2S_AP_TO_BT_DOUT

UART_BB_TO_WLAN_COEX

UART_WLAN_TO_BB_COEX

50_UAT_WLAN_5G_WEST
50_UAT_WLAN_2G_EAST

50_UAT_WLAN_5G_EAST

50_WLAN_G_1

50_WLAN_A_1

50_UAT2_M

BB_TO_LAT_ANT_SCLK
BB_TO_LAT_ANT_DATA

P2MM-NSM

ROOM=UAT_DEBUG

P2MM-NSM

ROOM=UAT_DEBUG

P2MM-NSM

ROOM=UAT_DEBUG

P2MM-NSM

ROOM=UAT_DEBUG

PP_VDD_MAIN

PP1V8_SDRAM

SM

PP5304
PP5301

SM

PP5302

SM

PP5303

SM

Wifi/BT

1

PP

1

PP

1

PP

1

PP

27 26 25 23 21 19 18 10 9 4
41 40 39 37 35 34 33 31 28

47 41 40 37 36 32 21 20 18 16

77 58 55 53 52 46

68 60 58 55 53 52 48

65 38 37 32 25 23 19

Opposite polarity on Karoo -->

68 37 26

WIFI_MLB

64 39 23 20 13

68 55

68 55

81 58 53

78 58 53

AP_TO_ICEFALL_FW_DWLD_REQ

12

PP3V0_TRISTAR_ANT_PROX

PP1V8_SDRAM

68 60 53 41
68 60 53 41

To UAT

I2

60 41 40 29 19

68 60 58 55 53 52 48

47 41 40 37 36 32 21 20 18 16

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

78

81 58 53

78 58

36 17 13

76 59

73 59

73 59

75 59

75 59

76 60

68 60

68 60

To LAT

PP_VDD_MAIN

PP1V8_SDRAM

PP_VDD_BOOST

BBPMU_TO_PMU_AMUX1

65 20

BBPMU_TO_PMU_AMUX2

65 20

BBPMU_TO_PMU_AMUX3

69 20

AP_TO_BBPMU_RADIO_ON_L

64 12

PMU_TO_BBPMU_RESET_L

20
64

AP_TO_BB_RESET_L

64 12

BB_TO_AP_RESET_DETECT_L

68 12

BB_TO_STROBE_DRIVER_GSM_BURST_IND
AP_TO_BB_MESA_ON

68 12

AP_TO_BB_TIME_MARK

68 12

AP_TO_BB_COREDUMP

68 12

LCM_TO_MANY_BSYNC

AP_TO_BB_IPC_GPIO1

68 12

90_PCIE_AP_TO_BB_REFCLK_P

67 52

90_PCIE_AP_TO_BB_REFCLK_N

67 52

90_PCIE_AP_TO_BB_TXD_PUART_WLAN_TO_AP_CTS_L

67 52 55 12

90_PCIE_AP_TO_BB_TXD_N

67 52

90_PCIE_BB_TO_AP_RXD_P

67 52

90_PCIE_BB_TO_AP_RXD_N

67 52

PCIE_AP_TO_BB_RESET_L

68 52

PCIE_BB_BI_AP_CLKREQ_L

68 52

BB_TO_PMU_PCIE_HOST_WAKE_L

68 20

UART_AOP_TO_BB_TXD

68 13

UART_BB_TO_AOP_RXD

68 13

I2S_BB_TO_AP_BCLK

68 11

I2S_BB_TO_AP_LRCLK

68 11

I2S_AP_TO_BB_DOUT

68 11

I2S_BB_TO_AP_DIN

68 11

UART_BB_TO_WLAN_COEX
UART_WLAN_TO_BB_COEX

NFC_SWP

NFC_SWP_MUX

AP_TO_ICEFALL_FW_DWLD_REQ

SE2_PRESENT

ICEFALL_LDO_ENABLE

SWD_AP_TO_MANY_SWCLK

67

SWD_AOP_BI_BB_SWDIO

67 13

PMU_TO_BB_USB_VBUS_DETECT

64 20

90_USB_BB_DATA_P

67 40

90_USB_BB_DATA_N

67 40

50_UAT_WLAN_2G_WEST_PLEXER
50_UAT_LB_MLB_SOUTH
50_UAT_MB_HB_SOUTH
50_UUAT_LB_MLB_NORTH

50_UAT1_WEST

BB_TO_UAT_SCLK
BB_TO_UAT_DATA

50_UAT1_TUNER
BB_BUFFER_GPO1
BB_BUFFER_GPO2

PP_VDD_MAIN

PP1V8_SDRAM

PP_VDD_BOOST_RF

BBPMU_TO_PMU_AMUX1

BBPMU_TO_PMU_AMUX2

BBPMU_TO_PMU_AMUX3

AP_TO_BBPMU_RADIO_ON_L

PMU_TO_BBPMU_RESET_L

AP_TO_BB_RESET_L

BB_TO_AP_RESET_ACT_L

BB_TO_AP_RESET_DETECT_L

BB_TO_AP_GSM_TXBURST

AP_TO_BB_MESA_ON

AP_TO_BB_TIME_MARK

AP_TO_BB_COREDUMP_TRIG

TOUCH_TO_BBPMU_FORCE_PWM

AP_TO_BB_IPC_GPIO

AP_TO_BB_IPC_GPIO2

100_PCIE_AP_TO_BB_REFCLK_P

100_PCIE_AP_TO_BB_REFCLK_N

100_PCIE_AP_TO_BB_TX_P

100_PCIE_AP_TO_BB_TX_N

100_PCIE_BB_TO_AP_RX_P

100_PCIE_BB_TO_AP_RX_N

PCIE_AP_TO_BB_PERST_L

PCIE_AP_BI_BB_CLKREQ_L

PCIE_BB_TO_PMU_WAKE_L

UART_AP_TO_BB_TXD

UART_BB_TO_AP_RXD

UART_AOP_TO_BB_TXD

UART_BB_TO_AOP_RXD

UART_AOP_TO_GNSS_TXD

UART_GNSS_TO_AOP_RXD

I2S_AP_TO_BB_BCLK

I2S_AP_TO_BB_LRCLK

I2S_AP_TO_BB_DOUT

I2S_BB_TO_AP_DIN

UART_BB_TO_WLAN_COEX

UART_WLAN_TO_BB_COEX

NFC_SWP

NFC_TO_BB_CLKREQ

BB_TO_NFC_CLK

NFC_SWP_MUX

SE2_READY

AP_TO_ICEFALL_FW_DWLD

SE2_PWR_REQ

SE2_PRESENT

ICEFALL_LDO_ENABLE

SWD_AP_TO_BB_CLK

SWD_AP_BI_BB_IO

USB_BB_VBUS

90_USB_BB_P

90_USB_BB_N

50_UAT_WLAN_2G_WEST_PLEXER

50_UAT_LB_MLB_SOUTH

50_UAT_MB_HB_SOUTH

50_UUAT_LB_MLB_NORTH

50_UAT1_WEST

UAT_RFFE_CLK

UAT_RFFE_DATA

50_UAT1_TUNER

BUFFER_GPO1

BUFFER_GPO2

Cellular

RADIO_MLB

I16

ieee
ieee.std_logic_1164.all
work.all

TRUE

D

C

B

A

64 58

64 58

58 20

58 12

58 12

58 20

58 12

58 12

58 12

58 12

PMU_TO_NFC_EN

BB_TO_NFC_CLK
NFC_TO_BB_CLK_REQ

AP_TO_NFC_FW_DWLD_REQ
AP_TO_NFC_DEV_WAKE
NFC_TO_PMU_HOST_WAKE

UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_RTS_L
UART_NFC_TO_AP_CTS_L

81 58 53

78 58

78 58

81 58 53

78 58 53

NFC_SWP
SE2_READY

SE2_PWR_REQ
SE2_PRESENT

NFC_SWP_MUX

PMU_TO_NFC_EN

BB_TO_NFC_CLK

NFC_TO_BB_CLK_REQ

AP_TO_NFC_FW_DWLD

AP_TO_NFC_DEV_WAKE

NFC_TO_PMU_HOST_WAKE

UART_AP_TO_NFC_TXD

UART_NFC_TO_AP_RXD

UART_AP_TO_NFC_RTS_L

UART_NFC_TO_AP_CTS_L

NFC_SWP

SE2_READY

SE2_PWR_REQ

SE2_PRESENT

NFC_SWP_MUX

ICEFALL_LDO_ENABLE

STOCKHOLM_MLB

NFC

68 60 53 41

68 60 53 41

BB_TO_LAT_ANT_SCLK
BB_TO_LAT_ANT_DATA

68 41

68 41

68 46

BB_TO_LAT_GPO1
BB_TO_LAT_GPO2
BB_TO_LAT_GPO3

LAT_RFFE_CLK

LAT_RFFE_DATA

RFFE_GPO1

RFFE_GPO2

RFFE_GPO3

PMU_TO_GNSS_EN

UART_AP_TO_GNSS_TXD

UART_GNSS_TO_AP_RXD

UART_AP_TO_GNSS_RTS_L

UART_GNSS_TO_AP_CTS_L

GNSS_TO_PMU_HOST_WAKE

AP_TO_GNSS_TIME_MARK

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D1X WIFI_MLB (PERENNIAL)

34567 8

2 1

CK

ECNREV DESCRIPTION OF REVISION

APPD

DATE

2016-06-1400064008778 ENGINEERING RELEASED

D

C

B

A

FEBRUARY 1, 2016

PDF PAGE

TABLE_TABLEOFCONTENTS_HEAD

2

TABLE_TABLEOFCONTENTS_ITEM

3

TABLE_TABLEOFCONTENTS_ITEM

BOM OPTIONS:

D10_JP:

1131S0648

CAP,CER,0.3PF,+/-0.05,01005

152S00029 1

131S0893

117S0161 1

117S0161

152S1980 1

131S0404

152S2061

117S0161

117S0161

NOSTUFF:C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF

D10_ROW:

131S0648 C7705_RF1 CRITICAL

117S0161 RES,MF,0 OHM,1/32W,01005 R7711_RF CRITICAL1 D10_ROW

117S0161 CRITICAL D10_ROWRES,MF,0 OHM,1/32W,01005 R7702_RF1

152S1988 R7704_RFIND,2.4NH,UH-Q,010051 D10_ROWCRITICAL

TRUE

TRUE

TRUE

TRUE

TRUE D10_ROWCRITICALC6729_RF1 IND,9.1NH,UH-Q,01005152S1853

TRUE

152S1998 1 IND, 0.8NH,UH-Q,01005 CRITICALL7700_RF D10_ROW

TRUE

NOSTUFF:C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF

D101_WIFI:

131S0648 C7705_RF1 D101

117S0161

117S0161

152S1988

131S0648

118S0724

152S2054

152S1998 CRITICAL1 L7700_RF D101

152S2043 CRITICAL1 L7701_RF D101

NOSTUFF: C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF

IND,1.1NH,UH-Q,01005

1

CAP,CER,0.2PF,+/-0.05,01005

RES,MF,0 OHM,1/32W,01005

1

IND,1.0NH,UH-Q,01005

CAP,3.9PF,+/-1.0PF,01005

1

IND,7.5NH,UH-Q,01005

1

RES,MF,0 OHM,1/32W,01005

1 D10_JP

IND,6.2NH,UH-Q,01005152S2043

1

IND, 0.8NH,UH-Q,01005152S1998

1

1 CRITICAL152S2043 IND,6.2NH,UH-Q,01005

1

RES,MF,0 OHM,1/32W,01005

C7700_RF, C7703_RF,C7704_RF

CAP,CER,0.3PF,+/-0.05,01005

RES,MF,0 OHM,1/32W,01005 R7700_RF D10_ROWCRITICAL1117S0161

1 R7701_RF D10_ROW117S0161 CRITICAL

RES,MF,0 OHM,1/32W,01005

C7700_RF, C7703_RF,C7704_RF

CAP,CER,0.3PF,+/-0.05,01005

IND,1.1NH,UH-Q,01005152S00029 1 R7703_RF D101

TRUE

IND,2.4NH,UH-Q,010051 R7704_RF D101

TRUE

TRUE

RES,MF, 0 OHM,1/20W, 0201

1 CRITICALR6711_RF

TRUE

IND,9.1NH,UH-Q,0201

1 D101

RES,MF,0 OHM,1/32W,01005 D1011117S0161

TRUE

IND,6.2NH,UH-Q,01005152S2043

IND, 0.8NH,UH-Q,01005

IND,6.2NH,UH-Q,01005

RES,MF,0 OHM,1/32W,01005 D101R7701_RF117S0161 1 CRITICAL

C7700_RF, C7703_RF,C7704_RF

CSA PAGE
76
77

CONTENTS
PERENNIAL
WIFI FRONT-END

D11_JP:

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

C7705_RF

R7703_RF

C7706_RF

R7711_RF

CRITICAL

CRITICAL

CRITICAL

CRITICAL

R7702_RF CRITICALRES,MF,0 OHM,1/32W,01005

R7704_RF

R6711_RF

CRITICAL

C6729_RF

R7700_RF

CRITICAL

C7702_RF CRITICAL

L7700_RF

CRITICAL

L7701_RF

R7701_RF

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CRITICAL

CRITICALR7703_RF1152S00029 IND,1.1NH,UH-Q,01005

C7706_RFCAP,CER,0.2PF,+/-0.05,01005131S0893 1 CRITICAL

CRITICAL D10_ROWR6711_RF117S0161 1 RES,MF,0 OHM,1/32W,01005

CRITICALC7702_RF1

L7701_RF1 CRITICAL152S2043 IND,6.2NH,UH-Q,01005 D10_ROW

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CRITICAL

CRITICAL

C7706_RFCAP,CER,0.2PF,+/-0.05,01005131S0893 D1011

CRITICAL

CRITICAL

CRITICAL

CRITICAL

C7708_RF CRITICAL1 D101CAP,CER,0.3PF,+/-0.05PF,01005

C6729_RF

R7700_RF

C7702_RF

CRITICAL

CRITICAL

CRITICAL1 D101

BOM OPTIONCRITICAL

D10_JP

D10_JP

D10_JP

D10_JP

D10_JP

D10_JPCRITICAL

D10_JP

D10_JPCRITICAL

D10_JP

D10_JP

D10_JP

D10_JP

BOM OPTIONCRITICAL

D10_ROW

D10_ROW

D10_ROW

D10_ROW152S2043 IND,6.2NH,UH-Q,01005

BOM OPTIONCRITICAL

D101R7711_RF1 RES,MF,0 OHM,1/32W,01005

D1011 RES,MF,0 OHM,1/32W,01005 R7702_RF

D101

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

NOSTUFF:C7706_RF, C7711_RF,C7709_RF,C7710_RF, C7707_RF

D11_ROW:

152S00273 CRITICAL1 R7703_RF

152S1976 R7711_RF1

152S1986

118S0724

152S2054

117S0161

152S1853

117S0161

NOSTUFF:C7706_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF

D111_WIFI:

152S1986

118S0724

117S0161

117S0161

152S1853 CRITICAL

117S0161 R7701_RF D111CRITICAL1

NOSTUFF:C7706_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF

TRUE

TRUE

TRUE

1 CRITICALR7711_RF152S1976 IND,0.7NH,UH-Q,01005 D11_JP

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

1 CRITICAL D11_JPR7700_RF117S0161 RES,MF,0 OHM,1/32W,01005

TRUE

1 CRITICAL D11_JPL7700_RFRES,MF,0 OHM,1/32W,01005117S0161

TRUE

TRUE

1 CRITICAL117S0161 RES,MF,0 OHM,1/32W,01005 D11_JPR7701_RF

TRUE

1 CRITICALC7705_RF131S0893 CAP,CER,0.2PF,+/-0.05PF,01005 D11_JP

TRUE

1 CRITICALC7729_RF131S0893 CAP,CER,0.2PF,+/-0.05PF,01005 D11_JP

C7700_RF,C7702_RF, C7703_RF,C7704_RF

IND,0.6NH,UH-Q,01005

IND,0.7NH,UH-Q,01005

CAP,CER,3.5PF+/-0.1,01005131S0400 1 CRITICALR7702_RF

TRUE

TRUE

TRUE

IND,FILM,2.2NH,UH-Q,01005 D11_ROW

1

RES,MF,0 OHM,1/20W,0201

IND,9.1NH,UH-Q,0201

1

1

RES,MF,0 OHM,1/32W,01005

1

RES,MF,0 OHM,1/32W,01005

1

IND,9.1NH,UH-Q,01005

1

RES,MF,0 OHM,1/32W,01005

CAP,CER,0.2PF,+/-0.05PF,01005

CAP,CER,0.2PF,+/-0.05PF,01005

C7700_RF,C7702_RF, C7703_RF,C7704_RF

IND,0.6NH,UH-Q,01005152S00273 CRITICAL D1111 R7703_RF

IND,0.7NH,UH-Q,01005152S1976 R7711_RF CRITICAL1 D111

CAP,CER,3.5PF+/-0.1,01005131S0400 1 CRITICALR7702_RF D111

TRUE

TRUE

TRUE

IND,FILM,2.2NH,UH-Q,01005

1

RES,MF, 0 OHM,1/20W, 0201

1

IND,9.1NH,UH-Q,0201

1152S2054

RES,MF,0 OHM,1/32W,01005

1

1

RES,MF,0 OHM,1/32W,01005

IND,9.1NH,UH-Q,01005

1 D111

RES,MF,0 OHM,1/32W,01005

CAP,CER,0.2PF,+/-0.05PF,01005131S0893 C7705_RF D111CRITICAL1

CAP,CER,0.2PF,+/-0.05PF,01005131S0893 C7729_RF D111CRITICAL1

C7700_RF,C7702_RF, C7703_RF,C7704_RF

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

R7703_RF1 CRITICAL152S00273 IND,0.6NH,UH-Q,01005 D11_JP

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

53 55

IN

53 55

IN

R7702_RF CRITICAL1131S0400 CAP,CER,3.5PF+/-0.1,01005 D11_JP

TABLE_5_ITEM

D11_JPCRITICALR7704_RF1152S1986 IND,FILM,2.2NH,UH-Q,01005

TABLE_5_ITEM

53 55

IN

D11_JPCRITICALCAP,CER,0.3PF,+/-0.05PF,01005 C7708_RF1131S0648

TABLE_5_ITEM

CRITICALR6711_RFCAP,3.9PF,+/-1.0PF,0201,HI-Q D11_JP1131S0593

TABLE_5_ITEM

C6729_RFIND,7.5NH,UH-Q,02011 D11_JPCRITICAL152S2055

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL152S1853 IND,9.1NH,UH-Q,01005 D11_JPL7701_RF1

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

CRITICAL

D11_ROW

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

R7704_RF

R6711_RF

R7700_RF

L7700_RF

L7701_RF

R7701_RF

CRITICAL

CRITICAL1

CRITICALC6729_RF

CRITICAL117S0161

CRITICAL

CRITICAL

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

D11_ROWCRITICAL

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

53 55

IN

53 55

IN

53 55

OUT

53 55

IN

53 55

IN

53 55

IN

53 55

IN

53 55

IN

53 55

OUT

53 55

OUT

53 55

IN

2

IO

53 55

OUT

53 55

IN

53 55

OUT

53 55

IN

53 55

OUT

53 55

IN

53 55

IN

53 55

OUT

53 55

IN

53 55

OUT

53 55

IN

53 55

IN

D11_ROW131S0893 C7705_RF CRITICAL1

TABLE_5_ITEM

C7729_RF

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

R7704_RF

R6711_RF

CRITICAL

CRITICAL

CRITICALC6729_RF

R7700_RF

L7700_RF

CRITICAL

CRITICAL

D11_ROW131S0893 CRITICAL1

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

D111

TABLE_5_ITEM

D111

TABLE_5_ITEM

D111

TABLE_5_ITEM

D111

TABLE_5_ITEM

D111

TABLE_5_ITEM

53 55

IN

53 55

IN

53 55

OUT

53 55

IN

53 55

IN

53 55

OUT

3

IO

3

IO

3

IO

2

IO

2

IO

3

IO

L7701_RF

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

POWER

PP_VDD_MAIN

PP1V8_SDRAM

CLOCKS

PMUGPIO_TO_WLAN_CLK32K

CONTROL

PMU_TO_WLAN_REG_ON

PMU_TO_BT_REG_ON

BT_TO_PMU_HOST_WAKE

AP_TO_BT_WAKE

WLAN PCIE

90_PCIE_AP_TO_WLAN_REFCLK_P

90_PCIE_AP_TO_WLAN_REFCLK_N

90_PCIE_AP_TO_WLAN_TXD_P

90_PCIE_AP_TO_WLAN_TXD_N

90_PCIE_WLAN_TO_AP_RXD_P

90_PCIE_WLAN_TO_AP_RXD_N

PCIE_AP_TO_WLAN_RESET_L

PCIE_WLAN_BI_AP_CLKREQ_L

WLAN_TO_PMU_HOST_WAKE

AP_TO_WLAN_DEVICE_WAKE

WLAN UART

UART_WLAN_TO_AP_RXD

UART_AP_TO_WLAN_TXD

UART_WLAN_TO_AP_CTS_L

UART_AP_TO_WLAN_RTS_L

BLUETOOTH UART

UART_AP_TO_BT_TXD

UART_BT_TO_AP_RXD

UART_AP_TO_BT_RTS_L

UART_BT_TO_AP_CTS_L

AOP

AOP_TO_WLAN_CONTEXT_A

AOP_TO_WLAN_CONTEXT_B

AUDIO

I2S_AP_TO_BT_BCLK

I2S_AP_TO_BT_LRCLK

I2S_BT_TO_AP_DIN

I2S_AP_TO_BT_DOUT

COEX

UART_BB_TO_WLAN_COEX

UART_WLAN_TO_BB_COEX

ANTENNA

50_UAT_WLAN_5G_WEST

50_UAT_WLAN_2G_EAST

50_LAT_WLAN_5G_EAST

50_LAT_WLAN_G_1

50_LAT_WLAN_A_1

50_UAT2_M

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

D

C

B

A

8 7 5 4 2 1

36

WIFI/BT

34567 8

2 1

D

C

B

PP1V8_SDRAM

JTAG_WLAN_SEL

2

1

R7600_RF

10K

5%
1/32W
MF
01005

2

WLAN
NOSTUFF

55

53 54 55

53 54

53 54

53 54

53 54 55

53 54 55

53 54 55

53 54

53 54

53 54 55

53 54 55

56

56

1

1

PMUGPIO_TO_WLAN_CLK32K

IN

UART_BB_TO_WLAN_COEX

IN

UART_WLAN_TO_BB_COEX

OUT

PMU_TO_WLAN_REG_ON

IN

PMU_TO_BT_REG_ON

IN

JTAG_WLAN_SEL

2

JTAG_WLAN_TCK

2

JTAG_WLAN_TMS

2

JTAG_WLAN_TRST_L

2

UART_WLAN_TO_AP_RXD

OUT

UART_AP_TO_WLAN_TXD

IN

UART_WLAN_TO_AP_CTS_L

OUT

UART_AP_TO_WLAN_RTS_L

IN

AP_TO_WLAN_DEVICE_WAKE

IN

BT_TO_PMU_HOST_WAKE

OUT

50_WLAN_G_0

BI

50_LAT_WLAN_G_1

IO

50_WLAN_A_0

BI

50_LAT_WLAN_A_1

IO

PP1V8_SDRAM

2 1

1

C7600_RF

27PF

5%
16V

2

NP0-C0G
01005

WLAN

54

LPO_IN

8

SECI_RX

7

SECI_TX

92

WL_REG_ON

93

BT_REG_ON

61

JTAG_SEL

64

JTAG_TCK

62

JTAG_TMS

2

JTAG_TRST*

11

FAST_UART_TX

10

FAST_UART_RX

9

FAST_UART_RTS_OUT

12

FAST_UART_CTS_IN

WL_DEV_WAKE

56

BT_HOST_WAKE

52

2G_ANT_CORE0

5

2G_ANT_CORE1

59

5G_ANT_CORE0

66

5G_ANT_CORE1

1

C7601_RF

0.01UF

10%

6.3V

2

X5R
01005

WLAN

15

VDDIO_1P8V

29

28

VBAT_VCC

VBAT_VCC

WLAN_RF

LBEE5W11GJ-943

LGA

SYM 1 OF 2

1

C7602_RF

10UF

20%

6.3V

2

CERM-X5R
0402-9

31

30

VBAT_RF_VCC

VBAT_RF_VCC

BT_DEV_WAKE

BT_UART_RXD

BT_UART_TXD
BT_UART_CTS*
BT_UART_RTS*

BT_PCM_CLK

BT_PCM_SYNC

BT_PCM_OUT

BT_PCM_IN

WL_HOST_WAKE

PCIE_CLKREQ*

PCIE_PERST*

PCIE_RDP

PCIE_RDN

PCIE_TDP

PCIE_TDN

PCIE_REFCLK_P
PCIE_REFCLK_N

CXT_A/JTAG_TDI

CXT_B/JTAG_TDO

SR_VLX

VIN_LDO

1

C7606_RF

0.01UF

10%

6.3V

2

X5R
01005

WLAN WLAN

55

AP_TO_BT_WAKE

41

UART_AP_TO_BT_TXD

42

UART_BT_TO_AP_RXD

44

UART_AP_TO_BT_RTS_L

43

UART_BT_TO_AP_CTS_L

38

I2S_AP_TO_BT_BCLK

37

I2S_AP_TO_BT_LRCLK

40

I2S_BT_TO_AP_DIN

39

I2S_AP_TO_BT_DOUT

1413

WLAN_TO_PMU_HOST_WAKE

17

PCIE_WLAN_BI_AP_CLKREQ_L

16

PCIE_AP_TO_WLAN_RESET_L

19

90_PCIE_AP_TO_WLAN_TXD_P

20

90_PCIE_AP_TO_WLAN_TXD_N

22

90_PCIE_WLAN_TO_AP_RXD_P

23

90_PCIE_WLAN_TO_AP_RXD_N

25

90_PCIE_AP_TO_WLAN_REFCLK_P

26

90_PCIE_AP_TO_WLAN_REFCLK_N

63

AOP_TO_WLAN_CONTEXT_A

3

AOP_TO_WLAN_CONTEXT_B

33

SR_LVX

35

VIN_LDO

1

C7603_RF

100PF

5%
16V

2

NP0-C0G
01005

WLAN

PP_VDD_MAIN

1

C7607_RF

27PF

5%
16V

2

NP0-C0G
01005

53 54 55

IN

53 54 55

IN

53 54 55

OUT

53 54 55

IN

53 54 55

OUT

53 54

IN

53 54

IN

53 54

OUT

53 54

IN

53 54 55

OUT

BI

53 54 55

IN

53 54 55

IN

53 54 55

IN

53 54

OUT

53 54

OUT

53 54 55

IN

53 54 55

IN

53 54 55

IN

IN

53 54

55

1

L7600_RF

2.2UH-20%-0.68A-0.25OHM

21

0806

SR_LVX_1

C7604_RF

7.5UF

20%

4V
CERM
0402

1

3

4

2

18
21
24
27
32
34
36
45
46
47
48
49
50
51
53
57
58
60
65
67
68
69
70
71
72
73

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
94
95
96
97
98

99
100
101
102
103
104
105

1
4
6

GND

THRM_PAD

WLAN_RF

LBEE5W11GJ-943

LGA

SYM 2 OF 2

THRM_PAD

106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163

D

C

B

A

AOP_TO_WLAN_CONTEXT_A

2 1

TDI

AOP_TO_WLAN_CONTEXT_B

2 1

TDO

UART_WLAN_TO_AP_RXD

2 1

UART_AP_TO_WLAN_TXD

2 1

JTAG_WLAN_TCK

2

JTAG_WLAN_TMS

2

JTAG_WLAN_TRST_L

2

AP_TO_WLAN_DEVICE_WAKE

1 2

BT_TO_PMU_HOST_WAKE

2 1

PP7600_RF

P2MM-NSM

SM

1

PP

PP7601_RF

P2MM-NSM

SM

1

PP

PP7603_RF

P2MM-NSM

SM

1

PP

PP7604_RF

P2MM-NSM

SM

1

PP

PP7605_RF

P2MM-NSM

SM

1

PP

PP7606_RF

P2MM-NSM

SM

1

PP

PP7607_RF

P2MM-NSM

SM

1

PP

PP7608_RF

P2MM-NSM

SM

1

PP

PP7609_RF

P2MM-NSM

SM

1

PP

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

PP7610_RF

P2MM-NSM

SM

PMUGPIO_TO_WLAN_CLK32K

1 2

WLAN_TO_PMU_HOST_WAKE

1 2

90_PCIE_AP_TO_WLAN_REFCLK_P

1 2

90_PCIE_AP_TO_WLAN_REFCLK_N

2 1

90_PCIE_AP_TO_WLAN_TXD_P

1 2

90_PCIE_AP_TO_WLAN_TXD_N

1 2

PCIE_AP_TO_WLAN_RESET_L

1 2

JTAG_WLAN_SEL

2

PMU_TO_WLAN_REG_ON

2 1

PMU_TO_BT_REG_ON

2 1 2 1

1

PP

PP7611_RF

P2MM-NSM

SM

1

PP

PP7612_RF

P2MM-NSM

SM

1

PP

PP7613_RF

P2MM-NSM

SM

1

PP

PP7614_RF

P2MM-NSM

SM

1

PP

PP7615_RF

P2MM-NSM

SM

1

PP

PP7616_RF

P2MM-NSM

SM

1

PP

PP7617_RF

P2MM-NSM

SM

1

PP

PP7618_RF

P2MM-NSM

SM

1

PP

PP7619_RF

P2MM-NSM

SM

1

PP

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

2 1

OMIT

2 1

OMIT

2 1

OMIT

2 1

OMIT

UART_AP_TO_BT_TXD

UART_BT_TO_AP_RXD

UART_AP_TO_BT_RTS_L

UART_BT_TO_AP_CTS_L

AP_TO_BT_WAKE

PART NUMBER

339S00199339S00201 ALTERNATE ALT WIFI/BT MODULEWLAN_RF

PP7620_RF

P2MM-NSM

SM

1

PP

PP7621_RF

P2MM-NSM

SM

1

PP

PP7622_RF

P2MM-NSM

SM

1

PP

PP7623_RF

P2MM-NSM

SM

1

PP

PP7624_RF

P2MM-NSM

SM

1

PP

OMIT

OMIT

OMIT

OMIT

OMIT

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

A

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36

34567 8

2 1

D

WIFI UPPER ANTENNA FEEDS

OMIT_TABLE

R7704_RF

2.4NH+/-0.1NH-0.370A

21

55

55

50_WLAN_G_0

50_WLAN_A_0

BI

1

C7707_RF

0.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

WLAN_UP_RFFE

NOSTUFF

01005

OMIT_TABLE

R7703_RF

0.00

1

C7705_RF

0.2PF

+/-0.1PF

16V

2

NP0-C0G

01005
WLAN_UP_RFFE
OMIT OMIT

0%

1/32W

MF

01005

50_UAT_WLAN_2G_EAST

1

C7708_RF

0.6PF

+/-0.05PF
16V

2

CERM

01005
WLAN_UP_RFFE
OMIT_TABLE

21

50_LAT_WLAN_5G_EAST

1

C7706_RF

0.2PF

+/-0.1PF

16V

2

NP0-C0G

01005
WLAN_UP_RFFE

2GHZ UAT

53

BIBI

54

53

BI

54

5GHZ UAT

D

C

C

JUAT2_RF

MM8830-2600B

W5BPF_RF

OMIT_TABLE OMIT_TABLE

R7711_RF

53 54

BI

50_UAT_WLAN_5G_WEST

1

C7729_RF

+/-0.1PF
16V

2

NP0-C0G

01005
WLAN_UP_RFFE
OMIT

0.00

1/32W

01005

0%

MF

21

1

C7711_RF

0.2PF0.2PF

+/-0.1PF
16V

2

NP0-C0G

01005
WLAN_UP_RFFE
OMIT

5.15-5.85GHZ-1.2DB

LFB185G53CGZE200

31

2

R7702_RF

50_UAT2_BPF50_UAT_WLAN_5G_BPF 50_UAT2_TEST 50_UAT2_M

1

C7709_RF

0.2PF

+/-0.1PF
16V

2

NP0-C0G

01005
WLAN_UP_RFFE
OMIT

0.00

1/32W

01005

0%

MF

21

1

C7710_RF

0.2PF

+/-0.1PF
16V

2

NP0-C0G

01005
WLAN_UP_RFFE
OMIT

F-RT-SM

C R

GND

3

UP_RFFE

21

1

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

34567 8

2 1

CK

ECNREV DESCRIPTION OF REVISION

APPD

D

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

00064008778 ENGINEERING RELEASED

D

STOCKHOLM_MLB

C

JUNE 9, 2016

53 58

53 58

IN

53 58

IN

53 58

OUT

53 58

IN

53 58

IN

53 58

OUT

53 58

IN

53 58

IN

53 58

OUT

53 58

IN

53 58

OUT

PP_VDD_MAIN

PP1V8_SDRAM

PMU_TO_NFC_EN

NFC_TO_PMU_HOST_WAKE

AP_TO_NFC_DEV_WAKE

AP_TO_NFC_FW_DWLD_REQ

NFC_TO_BB_CLK_REQ

BB_TO_NFC_CLK

UART_AP_TO_NFC_TXD

UART_NFC_TO_AP_RXD

UART_AP_TO_NFC_RTS_L

UART_NFC_TO_AP_CTS_L

C

B

ALTERNATES

PART NUMBER

ALTERNATE FOR

PART NUMBER

132S0400 ?

2

IO

53 58

IN

53 58

IN

53 58

IN

53 58

OUT

53 58

OUT

NFC_SWP

SE2_READY

SE2_PWR_REQ

SE2_PRESENT

NFC_SWP_MUX

ICEFALL_LDO_ENABLE

DESCRIPTION BOM OPTIONREFERENCE DESIGNATOR(S)

C7504_RF132S0436

0.22UF 20% 6.3V 01005

B

A

BOM OPTIONS

PART# DESCRIPTIONQTY

220PF, 0201 2% 50V131S0883 D1011 C7514_RF

1131S00055 22PF, 0201 2% 50V D101C7512_RF

1131S00117 120PF, 0201 2% 50V C7518_RF D101

131S0883 1 220PF, 0201 2% 50V

22PF, 0201 2% 50V

131S00019 150PF, 0201 2% 50V

560PF, 0201 2% 50V

131S0883 C7514_RF1 D10_ROW220PF, 0201 2% 50V

131S00117 C7518_RF D10_ROW1 120PF, 0201 2% 50V

131S00026 1 820PF, 0201 2% 50V C7516_RF D10_ROW

C7512_RF131S00055 1 D10_JP

C7518_RF1 D10_JP

C7516_RF131S0825 1 D10_JP

C7512_RF131S00055 1 D10_ROW22PF, 0201 2% 50V

BOM OPTIONREFERENCE DESIGNATOR(S)

D101820PF, 0201 2% 50V1131S00026 C7516_RF

D10_JPC7514_RF

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTY

131S00081 270PF, 0201 2% 25V C7514_RF1 D111

131S00118 180PF, 0201 2% 50V

680PF, 0201 2% 50V1131S00033

270PF, 0201 2% 25V

131S0731 C7518_RF D11_JP1

131S00033 1 D11_JPC7516_RF

131S00118 180PF, 0201 2% 50V

131S00033 680PF, 0201 2% 50V

100PF, 0201 2% 50V

680PF, 0201 2% 50V

1 D11_ROWC7518_RF

1 C7516_RF D11_ROW

C7516_RF D111

C7514_RF D11_JP1131S00081

BOM OPTIONREFERENCE DESIGNATOR(S)

D1111 C7518_RF

D11_ROW270PF, 0201 2% 25V1131S00081 C7514_RF

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

A

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

34567 8

2 1

D

C

B

STOCKHOLM

NFC CONTROLLER

VDD_NFC_5V

PP1V8_SDRAM VDD_NFC_TVDD

1 2

PP_VDD_MAIN_NFC

2

VDD_NFC_DVDD

1

C7500_RF

1UF

20%

2

X5R
0201

NFC

1

C7502_RF

1UF

20%
10V10V

2

X5R

0201

NFC

NC

NC

D1

IRQ

A5

SVDD_REQ

B2

DWL

A2

CLK_REQ

A3

NFC_CLK_XTAL1

C1

RX

B1

TX

D2

CTS

A1

RTS

E1

VEN

E3

SMX_RST*

E4

SMX_CLK

F4

ESE_IO1

B3

SE2_BUSY

B4

IC2

E6

EXT_MUX

C3

XTAL2

C6

C7

B5

D3

VDD

VBAT

SIM_PMU_VCC

NFC_RF

PN67VEU3-B001D004

UFLGA

AVSS

D4

AVSS

F3

D6

VSS

E2

G2

PVDD

AVSS

B6

E7

D7

VUP

TVDD

AVDD

SIM_SWIO

TX_PWR_REQ

ESE_DWPM_DBG

ESE_DWPS_DBG

WKUP_REQ

SE2_ENABLE

SE2_SVDD_IN

PVSS

TVSS

DVSS

DVSS

G4

C2

C4

VDD_NFC_AVDD

VOLTAGE=1.80V

VDD_NFC_ESE

VOLTAGE=1.80V

B7

C5

SVDD

ESE_VDD

F1

IC00

A4

IC01

RX+

RX-

TX1
TX2

A7
A6
D5

G7
G6

F6
F5

G3
G5

E5

F7

F2
G1

1 2

GPIO0

VMID

VDD_NFC_AVDD

2

53 57 58

53 57

53 57

53 57

53 57

53 57 58

53 57 58

53 57 58

53 57 58

53 57 58

53 57

53 57

53 57

OUT

IN

IN

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

OUT

2

1

C7520_RF

1UF
20%
10V

2

X5R
0201

NFC

R7502_RF

0.00

0%

1/32W

MF

01005

NFC

NFC_TO_PMU_HOST_WAKE

SE2_PRESENT

AP_TO_NFC_FW_DWLD_REQ

NFC_TO_BB_CLK_REQ

BB_TO_NFC_CLK

UART_AP_TO_NFC_TXD

UART_NFC_TO_AP_RXD

UART_AP_TO_NFC_RTS_L

UART_NFC_TO_AP_CTS_L

PMU_TO_NFC_EN

VDD_NFC_ESE

2

SE2_READY

ICEFALL_LDO_ENABLE

NFC_SWP_MUX

21

2

1

C7504_RF

0.22UF
20%

6.3V

2

X5R
01005

NFC

NC

NFC_SWP

NFC_TEST_OUT

NC

NFC_BOOST_EN

NC

NC

NFC_RXP

NFC_RXN

NFC_TXP

NFC_TXN

AP_TO_NFC_DEV_WAKE

NFC_VMID

SE2_PWR_REQ

PP1V8_SDRAM

SE2_PWR_REQ

2

1

C7505_RF

1UF

20%
10V

2

X5R
0201

NFC

BI

2

2

2

2

2

2

IN

OUT

IN

1

R7599_RF

1.00K
5%

1/32W
MF
01005

2

1

C7506_RF

2

53 57

53 57 58

53 57 58

53 57 58

1

2

1

C7503_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

NFC

1

C7526_RF

2.2UF2.2UF 2.2UF
20%20% 20%

6.3V6.3V 6.3V
X5R-CERMX5R-CERM X5R-CERM
0201-10201-1 0201-1

C7527_RF

2

2

2

2

2

NFC_RXP

NFC_TXP

NFC_TXN

NFC_RXN

5V BOOSTER

PP_VDD_MAIN_NFC

2

L7502_RF

1

C7521_RF

2

1

C7511_RF

15UF

20% 20%

6.3V 6.3V

2

X5R X5R
0402-1

NFC

1.8UH-0.7A

0603

NFC

21

NFC_BOOST_SW

NFC_BOOST_EN

2

NFC FRONT END

C7507_RF

1000PF

21

2%

25V

C0G-NP0

0201

NFC

L7500_RF

160NH-10%-0.48A-0.33OHM

0402

NFC

L7501_RF

160NH-10%-0.48A-0.33OHM

0402

NFC

C7508_RF

1000PF

21

2%

25V

C0G-NP0

0201
NFC

NFC_RXP_CAP

21

21

NFC_RXN_CAP

1

C7509_RF

680PF
2%

25V

2

C0G-NP0
0201

NFC

1

C7510_RF

680PF
2%

25V

2

C0G-NP0
0201

NFC

R7508_RF

560

1%

1/20W

MF

201

NFC

NFC_BALP

BALUN_RF

NFC_BALN

R7509_RF

560

1%

1/20W

MF

201

NFC

21

GND

BAL0

SM

ATB161006F-20011

UNBAL

BAL1

4 1

3 2

NFC_ANT_MATCH

21

180 PHASE SHIFT INTRODUCED BY BALUN
DONE FOR BEST ROUTING

C7514_RF

220PF

21

2%

50V

C0G

0201

OMIT_TABLE

C7512_RF

22PF

21

2%

50V

C0G-CERM

0201

OMIT

B1
B2

B3

VIN

SW

SW

EN

NFBST_RF

WLCSP

NFC

A1A3
A2

1

C7516_RF

2

OMIT_TABLE

VOUT

VOUT

FAN48614BUC50X

PGND

PGND

C1

1

C7515_RF

1000PF 820PF
2% 2%

25V 25V

2

C0G-NP0 C0G-NP0
0201 0201

NFC NFC

C2

AGND

C3

1

C7517_RF

15UF

2

0402-1

NFC

NFC_TEST_OUT

2

VDD_NFC_5V

NFC_ANT

1

C7518_RF

120PF
2%

50V

2

NP0-C0G
0201

OMIT_TABLE

2

1

C7522_RF

100PF100PF

5%5%
16V16V

2

NP0-C0GNP0-C0G

0100501005

NFCNFC

SM-TP1P25-TOP

TP7500_RF

1

TP7505_RF

1

TP-P55

OMIT

A

OMIT

A

NFC

D

C

B

A

PP7503_RF

P2MM-NSM

SM

UART_AP_TO_NFC_TXD

1 2

UART_NFC_TO_AP_RXD

1 2

UART_AP_TO_NFC_RTS_L AP_TO_NFC_DEV_WAKE

UART_NFC_TO_AP_CTS_L

1 2

1

PP

OMIT

PP7504_RF

P2MM-NSM

SM

1

PP

OMIT

PP7505_RF

P2MM-NSM

SM

1

PP

OMIT

PP7506_RF

P2MM-NSM

SM

1

PP

OMIT

NFC_TO_PMU_HOST_WAKE

1 2

PMU_TO_NFC_EN

1 2

1 2 1 2

PP7507_RF

P2MM-NSM

SM

1

PP

OMIT

PP7508_RF

P2MM-NSM

SM

1

PP

OMIT

PP7509_RF

P2MM-NSM

SM

1

PP

OMIT

NFC LOAD SWITCH

NFCSW_RF

FPF1204UCX

PP_VDD_MAIN PP_VDD_MAIN_NFC

PP1V8_SDRAM

2 1

1 2 2

B2

WLCSP-COMBO

VIN

ON

GND

R7520_RF

0.00

1%

1/20W

MF

0201

NOSTUFF

VOUT

B1

21

A1A2

PP_VDD_MAIN_NFCPP_VDD_MAIN

2 2 1

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D10 RADIO_MLB_FF

FEB 19, 2016

ECNREV DESCRIPTION OF REVISION

DATE

2016-06-1400064008778 ENGINEERING RELEASED

D

C

B

D10 NORTH-SOUTH METROCIRC
339S00086

UPPER MLB

59 53

BI

53

50_UAT1_EAST

50_LAT_WLAN_NORTH

50_UUAT_LB_MLB_NORTH

6

SIGNAL1-U SIGNAL1-L

2

SIGNAL2-U

4

SIGNAL3-U

1
3
5

8
10
12
21
22
23
24
25
26
27
28
29
30
31
32

GND

MCNS_RF

FLTPSSL-381E

SM

SIGNAL2-L
SIGNAL3-L

GND

7
11
9

33
34
35
36
37
38

LOWER MLB

50_UAT_MB_HB_SOUTH

50_LAT_WLAN_SOUTH

50_UAT_LB_MLB_SOUTH

OUT

1 1

IOIN

D10 EAST-WEST METROCIRC
339S00110

59

IO

INOUT

IO

INOUT

BI

EAST MLB

50_UAT_WLAN_2G_EAST

50_LAT_WLAN_5G_EAST

50_UAT1_EAST

3
1
5

2
4
6
8

9
12
21
22

GND
TRUE

I11

MCEW_RF

FLTPSSL-382E

SIGNAL1-E
SIGNAL2-E
SIGNAL3-E

GND

SM

SIGNAL1-W
SIGNAL2-W
SIGNAL3-W

GND

1

WEST MLB

7

50_UAT_WLAN_2G_WEST

10

50_UAT_WLAN_5G_WEST

11

50_UAT1_WEST

23
24
25
26
27
28

GND
TRUE

I12

50_UAT_WLAN_2G_WEST

1

IO

INOUT

IO

INOUT

R6711_RF

3.9PF

21

50_UAT_WLAN_2G_WEST_PLEXER

+/-0.1PF

16V
NP0-C0G
01005-1

UP_RFFE

OMIT

INOUT

INOUT

C

IO

INOUT

1

INOUT

B

A

WIFI LOWER ANTENNA FEED

W2BPF_RF

WLAN-BT-LTE

885118

LGA

GND

3

2

WLAN_RFFE

5

OUTPUT

9.1NH-3%-0.17A-1.7OHM

41

L7702_RF

01005
WLAN_RFFE

IO

50_LAT_WLAN_A_1

1

WLAN_RFFE

2

1

C7700_RF

0.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

WLAN_RFFE
OMIT

C7701_RF

3.6PF

21

+/-0.1PF

16V

NP0-C0G

01005

L7703_RF

4.0NH-+/-0.1NH-0.27A

R7700_RF

0.00

0%

1/32W

MF

01005

WLAN_RFFE

OMIT

01005

WLAN_RFFE

21

50_WLAN_G_1_DPLX

50_WLAN_A_1_DPLX

50_LAT_WLAN_G_1

IO

TRUE

L7700_RF

0.00

0%

1/32W

MF

01005

WLAN_RFFE

OMIT

11

21

50_WLAN_G_1_BPF 50_WLAN_G_1_M

1

L7701_RF

9.1NH-3%-0.17A-1.7OHM

01005

OMIT

2

INPUT

ADD REV ID FOR D10/D11 HERE

1

2

1

C7702_RF

4.3NH-3%-0.270A

01005

WLAN_RFFE

OMIT

2

W25DI_RF

LFD212G45MP2E013

LGA

4

P1

6

P2

GND

5

3

1

2

P3

WLAN_RFFE

50_LAT_WLAN_M

1

C7703_RF

0.2PF

+/-0.1PF
16V

2

NP0-C0G

01005

WLAN_RFFE
OMIT

R7701_RF

0.00

1/32W

01005

WLAN_RFFE

21

0%

MF

OMIT

1

C7704_RF

0.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

WLAN_RFFE
OMIT

COAX

50_LAT_WLAN_SOUTH50_LAT_WLAN_NORTH

1 1

THROUGH METROCIRC

JLAT3_RF

MM7829-2700

F-ST-SM

2

1

3

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

C6729_RF

7.5NH+/-3%-0.2A

01005

UP_RFFE
OMIT

2

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

D

53

2 1

BB_TO_UAT_SCLK

2

1

C5904_RF

120PF

10%
10V

2

CER-X7R
01005

34567 8

PLEASE CONTACT ANTENNA (MATT MOW)
FOR ANY COMPONENT CHANGE.

UAT TUNER FLEX

FL6700_RF

150OHM-25%-200MA-0.7DCR

TUNFX_RF

505066-0620

F-ST-SM

87

21

43

65

109

0%

MF

21

21

VDD_TUNER_RFFE_VIO_1V8_FILT

1

C6701_RF

27PF

5%
16V

2

NP0-C0G
01005

UAT

UAT_TUNER_RFFE_DATA_FILT UAT_TUNER_RFFE_CLK_FILT

1

C6702_RF

27PF

5%
16V

2

NP0-C0G
01005

UAT

BB_TO_UAT_DATA

2

1

C5905_RF

68PF

2%

6.3V

2

NP0-C0G
01005

53

PP1V8_SDRAM

IN

01005

FL6701_RF

0.00

53 60 53 60

IO IN

IN

BB_TO_LAT_ANT_SCLK

1

C5908_RF

33PF

5%
16V

2

NP0-C0G-CERM
01005

1/32W

01005

PP3V0_TRISTAR_UAT_TUNER_B2B_FILT

1

C6705_RF

27PF

5%
16V

2

NP0-C0G
01005

UAT

1

C6703_RF

27PF

5%
16V

2

NP0-C0G
01005

UAT

150OHM-25%-200MA-0.7DCR

FL6702_RF

0.00

0%

1/32W

MF

01005

FL6703_RF

01005

21

BB_TO_UAT_SCLKBB_TO_UAT_DATA

PP3V0_TRISTAR_ANT_PROX

21

IN

D

53 60

C

B

53

IN

BB_TO_LAT_ANT_DATA

1

C5909_RF

33PF

5%
16V

2

NP0-C0G-CERM

C

01005

LB/MLB/GNSS/MB/HB
STANDOFF

53

BB_BUFFER_GPO2

IN

1

C6721_RF

33PF

5%
16V

2

NP0-C0G-CERM
01005

4

VDD

USPDT2_RF

RF1341

3

WLCSP

CB

GNDA

5

RF1

RFGND

2

1

USPDT2_RF

6

1

C6720_RF

0.01UF

10%

6.3V

2

X5R
01005

IO

50_UAT1_TUNER

PP3V0_TRISTAR_ANT_PROX

C6704_RF

0.00

1/20W

0201

21

1%

MF

UP_RFFE

50_UAT1_TUNER_M

2

R6706_RF

2.2NH+/-0.1NH-0.6A

21

1

0201-1

UP_RFFE

C6714_RF

5.6NH+/-3%-0.4A

0201

2

50_UAT1_NOTCH

1

C6700_RF

1.2PF

+/-0.05PF
25V

2

C0G-CERM
0201

C6716_RF

18PF

21

50_UAT1_FEED

2%

25V

C0H-CERM

1

0201

UP_RFFE

L6707_RF

9.1NH+/-0.3%-0.3A

0201

UP_RFFE

2

SUAT1_RF

STDOFF-2.56OD1.4ID.99H-SM

1

UP_RFFE

53

BB_BUFFER_GPO1

IN

ALT UAT1 GND

L8007_RF

560NH-5%-2.80OHM

USPDT_VDD

1

C8007_RF

0.01UF

10%

6.3V

2

X5R
01005

4

VDD

1

C8005_RF

33PF

5%
16V

2

NP0-C0G-CERM
01005

USPDT_RF

RF1341

3

WLCSP

CB

GNDA

5

RF1

RFGND

2

1
6

USPDT_RF

L8008_RF

3.0NH+/-0.1NH-0.6A

21

0201

0201

DC_BLOCK

1

2

PP3V0_TRISTAR_ANT_PROX

21

C8008_RF

18PF

2%
25V
C0H-CERM
0201

ALT_GND

SM-TP1P25-TOP

2

1

OMIT

B

TP8000_RF

A

A

1

C6734_RF

100PF

5%
16V

2

NP0-C0G
01005

UP_RFFE

1

C6735_RF

5%
16V

2

CERM
01005

UP_RFFE

UAT GROUND RING

CHASSIS_GND

2

1

C6730_RF

220PF18PF

5%

6.3V

2

CERM
01005

UP_RFFE

1

C6731_RF

56PF

5%
16V

2

NP0-C0G
01005

UP_RFFE

1

C6732_RF

4.0PF

+/-0.1PF
16V

2

NP0-C0G
01005

UP_RFFE

1

C6733_RF

220PF

5%

6.3V

2

CERM
01005

UP_RFFE

5G WIFI
STANDOFF

1

OMIT_TABLE

L8009_RF

9.1NH-0.4A

C7731_RF

1.2PF

IO

50_UAT2_M

+/-0.05PF

1

NOSTUFF

21

25V

C0G-CERM

0201

50_UAT2_FEED

1

C7730_RF

1.8NH+/-0.1NH-0.8A

0201

1

NOSTUFF

L7709_RF

3.0NH+/-0.1NH-0.6A

0201

STDOFF-2.56OD1.4ID.99H-SM

L6710_RF

4.3NH+/-3%-0.5A

0201

2

2

2

STDOFF-2.56OD1.4ID.99H-SM

SUAT2_RF

1

UP_RFFE

SGND_RF

1

UP_RFFE

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

03015

2

CHASSIS_GND

2

PP8000_RF

P2MM-NSM

SM

1

PP

DRAWING NUMBER SIZE

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

BOM LIST

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

LONGER PATH INDUCTOR

L8009_RF

34567 8

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

CRITICAL152S1860 1

LMBRF

2 1

D

152S0570 L8009_RF1

3.0 NH,03015

CRITICAL

NOLMBRF

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

C

B

81

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ICEFALL, SIM, DEBUG_CONN

MAV16 RADIO_MLB

LAST_MODIFICATION=Wed Jun 8 12:54:09 2016

DATESYNCCONTENTSCSAPAGE

62

page1

63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

<CSA_PAGE1>

<CSA_PAGE2>

<CSA_PAGE3>

<CSA_PAGE4>

<CSA_PAGE5>

<CSA_PAGE6>

<CSA_PAGE7>

<CSA_PAGE8>

<CSA_PAGE9>

<CSA_PAGE10>

<CSA_PAGE11>

<CSA_PAGE12>

<CSA_PAGE13>

<CSA_PAGE14>

<CSA_PAGE15>

<CSA_PAGE16>

<CSA_PAGE17>

<CSA_PAGE18>

<CSA_PAGE19>

<CSA_PAGE20>

<CSA_PAGE21>

<CSA_PAGE22>

<CSA_PAGE23>

<CSA_PAGE24>

<CSA_PAGE25>

<CSA_PAGE26>

<CSA_PAGE27>

<CSA_PAGE28>

<CSA_PAGE29>

<CSA_PAGE30>

page1
BOM_OMIT_TABLE
PMU: CONTROL AND CLOCKS

PMU: SWITCHERS AND LDOS
BASEBAND: POWER2

BASEBAND: CONTROL
BASEBAND GPIOS
TRANSCEIVER0/1: POWER
TRANSCEIVER0/1: TX PORTS
TRANSCEIVER0/1: PRX PORTS
RECEIVE MATCHING
LOWER ANTENNA & COUPLERS
DIVERSITY RECEIVE ASM'S
DIVERSITY RECEIVE LNA'S
UPPER ANTENNA FEEDS
PMU: ET MODULATOR
TEST POINTS & BOOT CONFIG
TDD TRANSMIT
FDD TRANSMIT

<SYNC_MASTER1>

<SYNC_MASTER2>

<SYNC_MASTER3>

<SYNC_MASTER4>

<SYNC_MASTER5>

<SYNC_MASTER6>

<SYNC_MASTER7>

<SYNC_MASTER8>

<SYNC_MASTER9>

<SYNC_MASTER10>

<SYNC_MASTER11>

<SYNC_MASTER12>

<SYNC_MASTER13>

<SYNC_MASTER14>

<SYNC_MASTER15>

<SYNC_MASTER16>

<SYNC_MASTER17>

<SYNC_MASTER18>

<SYNC_MASTER19>

<SYNC_MASTER20>

<SYNC_MASTER21>

<SYNC_MASTER22>

<SYNC_MASTER23>

<SYNC_MASTER24>

<SYNC_MASTER25>

<SYNC_MASTER26>

<SYNC_MASTER27>

<SYNC_MASTER28>

<SYNC_MASTER29>

<SYNC_MASTER30>

SCH: 951-00964

<SYNC_DATE1>

<SYNC_DATE2>

<SYNC_DATE3>

<SYNC_DATE4>

<SYNC_DATE5>

<SYNC_DATE6>

<SYNC_DATE7>

<SYNC_DATE8>

<SYNC_DATE9>

<SYNC_DATE10>

<SYNC_DATE11>

<SYNC_DATE12>

<SYNC_DATE13>

<SYNC_DATE14>

<SYNC_DATE15>

<SYNC_DATE16>

<SYNC_DATE17>

<SYNC_DATE18>

<SYNC_DATE19>

<SYNC_DATE20>

<SYNC_DATE21>

<SYNC_DATE22>

<SYNC_DATE23>

<SYNC_DATE24>

<SYNC_DATE25>

<SYNC_DATE26>

<SYNC_DATE27>

<SYNC_DATE28>

<SYNC_DATE29>

<SYNC_DATE30>

CK

ECNREV DESCRIPTION OF REVISION

APPD

AP CONNECTIONS

POWER

PP_VDD_MAIN

PP_VDD_BOOST

PP1V8_SDRAM

AMUX

BBPMU_TO_PMU_AMUX1

BBPMU_TO_PMU_AMUX2

BBPMU_TO_PMU_AMUX3

BB CONTROL

AP_TO_BBPMU_RADIO_ON_L

PMU_TO_BBPMU_RESET_L

AP_TO_BB_RESET_L

BB_TO_AP_RESET_DETECT_L

BB_TO_STROBE_DRIVER_GSM_BURST_IND

AP_TO_BB_MESA_ON

AP_TO_BB_TIME_MARK

AP_TO_BB_COREDUMP

LCM_TO_MANY_BSYNC

AP_TO_BB_IPC_GPIO1

PCIE

90_PCIE_AP_TO_BB_REFCLK_P

IN

90_PCIE_AP_TO_BB_REFCLK_N

IN

90_PCIE_AP_TO_BB_TXD_P

IN

90_PCIE_AP_TO_BB_TXD_N

IN

90_PCIE_BB_TO_AP_RXD_P

OUT

90_PCIE_BB_TO_AP_RXD_N

PCIE_AP_TO_BB_RESET_L

IN

PCIE_BB_BI_AP_CLKREQ_L

IO

BB_TO_PMU_PCIE_HOST_WAKE_L

OUT

AOP

UART_AOP_TO_BB_TXD

IN

UART_BB_TO_AOP_RXD

OUT

AUDIO

I2S_BB_TO_AP_BCLK

IN

I2S_BB_TO_AP_LRCLK

IN

I2S_AP_TO_BB_DOUT

IN

I2S_BB_TO_AP_DIN

OUT

WLAN

UART_BB_TO_WLAN_COEX

IN

UART_WLAN_TO_BB_COEX

OUT

NFC

NFC_SWP

IN

NFC_SWP_MUX

IN

SE2_READY

OUT

AP_TO_ICEFALL_FW_DWLD_REQ

IN

SE2_PWR_REQ

IN

NFC_TO_BB_CLK_REQ

IN

BB_TO_NFC_CLK

OUT

SE2_PRESENT

OUT

ICEFALL_LDO_ENABLE

IN

15

14

12

12

14

PP_VDD_BOOST

MAKE_BASE=TRUE

53 67 81

IN

6 20

IO

53 64 78 81

IN

6 17 20

IO

6 17 20

IO

IO

IO

IO

IO

IO

DEBUG

SWD_AP_TO_MANY_SWCLK

SWD_AOP_BI_BB_SWDIO

PMU_TO_BB_USB_VBUS_DETECT

90_USB_BB_DATA_P

90_USB_BB_DATA_N

ANTENNA

50_UAT_WLAN_2G_WEST_PLEXER

50_UAT1_WEST

50_UAT_LB_MLB_SOUTH

50_UAT_MB_HB_SOUTH

50_UUAT_LB_MLB_NORTH

65

65

65

53 64 65 77 81

53 68 81

53 64 78 81

53 64 78

53 64 81

53 68 78

53 68 78

53 68

53 68 78

53 68 78

53 64

53 68

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

53 67 78

53 67 78

53 67

53 67

53 67

53 67

53 64 68

7

53 68 78

53 68

53 68 78

53 68

53 68

53 68

53 68

53 68 78 81

53 68 78 81

53 81

53 78 81

53 78 81

53 78 81

53 78 81

53 64 78

53 64 78

53 81

53 78 81

DATE

2016-06-1400064008778 ENGINEERING RELEASED

D

4 20

C

B

A

BOM: 939-00826

ALTERNATES

PART NUMBER

197S0565 197S0593

197S0593 Y5501_RFALTERNATE197S0598

335S0894 IC EEPROM335S00013 EPROM_RFALTERNATE

353S00321 IC SWITCH SPDT353S00253 SWPMX_RFALTERNATE

Y5501_RFALTERNATE

UPPDI_RF155S00235 NOLMBRF155S00234 ALTERNATE

ALL:C5616_RF-C5618_RF,C5632_RF-C5634_RF

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

19P2 MHZ XTAL

19P2 MHZ XTAL

TRANSITION CAP138S00095138S00101 ALLALTERNATE

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

15

TUNER

MAKE_BASE=TRUE

BB_TO_UAT_SCLK

OUT

BB_TO_UAT_DATA

IO

50_UAT1_TUNER

IO

53 68

53 68

BB_BUFFER_GPO1

OUT

BB_BUFFER_GPO2

OUT

BB_TO_LAT_ANT_SCLK

OUT

BB_TO_LAT_ANT_DATA

IO

53 68

OUT

53 68

OUT

53 68

OUT

BB_TO_LAT_GPO1

BB_TO_LAT_GPO2

BB_TO_LAT_GPO3

SYNC_MASTER=Sync

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

BB_TO_UAT_SCLK

BB_TO_UAT_DATA

MAKE_BASE=TRUE

DOCK

MAKE_BASE=TRUE

BB_TO_LAT_ANT_SCLK

BB_TO_LAT_ANT_DATA

MAKE_BASE=TRUE

page1

spare

14 7

14 7

17 7

17 7

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

BOM OPTIONS:

34567 8

2 1

D

C

LMBRF:

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

353S00723

117S0002

152S2042

353S00627 CRITICAL1

117S0002

155S00139

118S0643 1 CRITICAL

155S00193 1

155S00158 1

337S00284

138S0739 1

132S0316

138S00032 1

138S00032

131S0217 CRITICAL

152S2006 1 CRITICAL

MLB PAD

1

MLB PAD LAT OUTPUT MATCH

1

MLB PAD UAT OUTPUT MATCH

MLB LNA

MLB LNA OUTPUT MATCH

PENTAPLEXER

1 CRITICAL

RES,MF,4.99K OHM,01005

FLTR,DIPLEXER,LB-MB-HB,DPX,SHIELD,0805

FLTR,DIPLEXER,LB-MB/HB,MIRROR,0805

IC,SECURE ELEMENT,BCM20211,WLBGA25

1 SE2_RF

CAP,1UF,0201

1

CAP,1UF,0201

1 C7501_RF

CAP,0.1UF,01005

CAP,1UF,0201

CAP,1UF,0201

1138S0739

CAP,2.2UF,0201

CAP,2.2UF,0201

CAP,100PF,01005

1

1118S0627

RES,10KOHM,01005

LDO,BGA,2X2

1353S00026 CRITICAL

CAP,CER,NPO/COG,27PF,2%,16V,01005

CAP,CER,COG,3.0PF,+/-0.05,25V,0201,HI-Q

IND,FILM,6.2NH,3%,400MA,UH-Q,0201

1131S0630 CRITICAL

CAP,CER,NPO/COG,27PF,2%,16V,01005

MLBPA_RF

R7105_RF

R7106_RF

MLBLN_RF

R6710_RF CRITICAL1

PPLXR_RF

R7506_RF

UATDI_RF

UPPDI_RF

C7201_RF138S0739

C7528_RF

C7523_RF1138S0739

C7524_RF

C7529_RF

C7530_RF

C7531_RF

R7512_RF

SE2LDO_RF

C6345_RF

C6348_RF

L6322_RF

C6315_RF

CRITICAL

CRITICAL 152S2020 L6320_RF

CRITICAL1

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL1

CRITICAL

CRITICAL1131S0630

CRITICAL1131S0341

BOM OPTIONCRITICAL

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

NOLMBRF:

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 R6301_RF131S0444 CRITICAL

DCS/PCS RX FILTER MATCH

1

DCS/PCS RX FILTER MATCH

155S00149 GSMRX_RF

131S0630 C6340_RF CRITICAL

152S2005 1 CRITICAL

155S00163 1

155S00199

152S2044

152S00157 1 R6703_RF

DCS/PCS RX FILTER

DCS/PCS RX MATCH (DCS)

DCS/PCS RX MATCH (DCS)

1

DCS/PCS RX MATCH (DCS)

1

DCS/PCS RX MATCH (DCS)

DCS/PCS RX MATCH (DCS)

1131S0385

DCS/PCS RX MATCH (DCS)

1

QUADPLEXER

FLTR,DPX,PASS THRU,LB-MB-HB,SHLD,0805

1

FLTR,DPX,PASS THRU,LB-MB-HB,UNSHLD,0805

1118S0724

RES,MF,0OHM,1/20W,0201

IND,2.2NH,+/-0.1NH,600MA,0201

1 R7104_RF CRITICAL

1.2NH,+/-0.05NH,1.1A,UH-Q,0201

18PF,0201,25V

CAP,CER,12PF,5%,25V,0201,HI-Q

1 CRITICAL131S0445

L6318_RF

C6332_RF CRITICAL131S0319

L6319_RF

C6333_RF CRITICAL

C6341_RF CRITICAL131S0630

PPLXR_RF

R6404_RF CRITICAL

R6606_RF

CRITICAL

CRITICAL1

CRITICAL152S2005 1

CRITICAL

CRITICALUATDI_RF1

CRITICALUPPDI_RF155S00234

CRITICAL

CRITICALR6708_RF131S0549 1

D10 SPECIFIC:

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

131S0278 1

CAP,CER,COG,1PF,+/-0.1PF,25V,0201,HI-Q

C7120_RF

CRITICAL

BOM OPTIONCRITICAL

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

NOLMBRF

BOM OPTIONCRITICAL

D10

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

D

C

B

152S2006 1

131S0630

152S2051

131S00001

131S0363

152S2002

131S0337

118S0724

118S0608 1 R5911_RF

IND,FILM,6.2NH,3%,400MA,UH-Q,0201

1131S0341

CAP,CER,COG,3.0PF,+/-0.05PF,25V,0201,HI-Q

1 CRITICAL

CAP,CER,NPO/COG,27PF,2%,16V,01005

1 CRITICAL

IND,1.3NH,1.1A,0201

IND,2.0NH,600MA,0201

1

CAP,CER,0.1PF,25V,0201

1 CRITICAL

1118S0724

RES,MF,0OHM,1/20W,0201

RES,MF,0OHM,1/20W,0201

CAP,CER,C0G,HQ,0.6PF,+/-0.05PF,25V,0201

1

1 CRITICAL

IND,2.7NH,+/-0.1NH,600MA,0201,UH-Q

1

CAP,1.5PF,+/-0.05PF,25V,0201,HQ

RES,MF,0OHM,1/20W,0201

1131S0275

CAP,CER,C0G,0.3PF,+/-0.1PF,25V,0201,HQ

RES,MF,1K OHM,1%,1/32W,01005

IND,10NH,3%,250MA,HI-Q,0201

1152S1356

L6305_RF

C6306_RF

C6106_RF

R6404_RF

R7104_RF

C7119_RF

R6703_RF

R6708_RF

R6605_RF

C6610_RF

R6606_RF

C6416_RF

C6613_RF

CRITICAL

CRITICAL

CRITICAL152S2000

CRITICAL

CRITICAL1118S0724

CRITICALC7123_RF

CRITICAL

CRITICAL1

CRITICAL

CRITICAL

CRITICAL

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

LMBRF

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

D11 SPECIFIC:

131S0425

CAP,CER,COG,0.5PF,+/-0.05PF,25V,0201,HI-Q

1

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

C7120_RF

CRITICAL

BOM OPTIONCRITICAL

TABLE_5_ITEM

D11

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

PMU: CONTROL AND CLOCKS

34567 8

RESET AND CONTROL: PMU

2 1

D

HW_REV_ID

0.10V

0.20V

0.30V

0.40V

0.50V

0.60V

0.70V

0.80V

R5505 R5501 REVISION
887K

422K
255K
180K
124K
102K

82.5K

63.4K

51.1K

51.1K

51.1K

51.1K

51.1K

51.1K

51.1K

51.1K

DEV1

DEV2

DEV 2.1

DEV 3
T181
PP/P1

DEV4
P2

53 62 81

67

AP_TO_BB_RESET_L

IN

PS_HOLD

IN

RADIO_PMIC

R5504_RF

20.0K

5%

1/32W

01005

RADIO_PMIC

21

MF

PP_1V8_LDO7

R5502_RF

1.00K

1%

1/32W

01005

21

MF

78 81

78

53 62

67 78

67 78

53 62

IN

67 78

OUT

BI

BI

3 4 5

BBPMU_RF

PMD9645

WLNSP

GND

GND

52

NC

PP_VDD_MAIN

98

53

67

PCIE PERST OPTION

PP_VDD_MAIN

MAKE_BASE=TRUE

1 4 16 20

IN

AP_TO_BBPMU_RADIO_ON_L

PMU_TO_BBPMU_RESET_L

PMIC_RESOUT_L

PS_HOLD_PMIC

SPMI_CLK

SPMI_DATA

58

CBL_PWR*

75 42

PON_1

43

RESIN*

63

PON_RST*

82

PS_HOLD

25

SPMI_CLK

31

SPMI_DATA

SYM 1 OF 5

CONTROL

RADIO_PMIC

OPT_1
OPT_2

BAT_ID_THERM

BBPMU_RF

PMD9645

WLNSP

36
46
57
62

SYM 5 OF 5

GND

RADIO_PMIC

GND
GND
GND

GND

D

MPPS AND GPIOS: PMU

C

0.90V

1.00V

1.10V

51.1K

51.1K

51.1K

1.20V

1.30V 39.0K DEV6

51.1K

63.4K

82.5K
100K50.0K
100K

DEV5

EVT
EVT DOE

EVT ALT/CARBON

1.40V 14.7K 51.1K CARRIER

1.50V 40.2K 200K

1.60V 6.34K

51.1K

DVT
PVT

REV_ID

1

R5505_RF

40.2K

1%
1/32W
MF
01005

2

1

R5501_RF

200K

1%
1/32W
MF
01005

2

C

BBPMU_RF

PMD9645

WLNSP

26

15

21

37

32

38

NC

NC

NFC_TO_BB_CLK_REQ

PCIE_AP_TO_BB_PERST_PMU_L

SIM1_REMOVAL_ALARM

LCM_TO_MANY_BSYNC

62
53

IN

PCIE PERST OPTION

78

R5511_RF

0.00

68 78

IN

53 62

IN

1/20W

0201

1%

MF

21

PCIE_AP_TO_BB_RESET_L

IN

53 62 68

NC

NC

13

MPP_01

51

MPP_02

61

MPP_03

9

MPP_04

4

MPP_05

20

MPP_06

83

PA_THERM1

88

PA_THERM2

53 62 78 81

IN

66

OUT

67

OUT

PMU_TO_BB_USB_VBUS_DETECT

HW_REV1_ID

VDDPX_BIAS_UIM2

VREF_DAC_BIAS

SYM 3 OF 5

GPIO_MPP

RADIO_PMIC

GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06

B

64 65 66

PP_1V8_LDO7

XTAL AND CLOCK: PMU

1

1

C5501_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

RADIO_PMIC

R5503_RF

100K

1%
1/32W
MF
01005

2

RADIO_PMIC

1

C5502_RF

1000PF

10%

6.3V

2

X5R-CERM
01005

RADIO_PMIC

XTAL_19P2M_OUT

XO_THERM

3

Y5501_RF

19.2MHZ-10PPM-7PF-80OHM

2.0X1.6-SM

1

4

RADIO_PMIC

3

2

XTAL_19P2M_IN

B

3 3

BBPMU_RF

PMD9645

WLNSP

67 78

IN

XO_OUT_D0_EN

XO_THERM

3

XTAL_19P2M_IN

3

XTAL_19P2M_OUT SHIELD_SLEEP_CLK_32K

3

56

BB_CLK_EN

76

XO_THERM

41

GND_XOADC

55

XTAL_19M_IN

65

XTAL_19M_OUT

71

GND_XO_CLK

GND_XO_CLK: VIA DOWN TO GND PLANE

SYM 2 OF 5

CLOCK

RADIO_PMIC

LN_BB_CLK

BB_CLK

RF_CLK1
RF_CLK2

SLEEP_CLK

45

50_MDM_PCIE_CLK

35

SHIELD_MDM_19P2M_CLK

66

SHIELD_WTR_19P2M_CLK

77

BB_TO_NFC_CLK

72

OUT

67 78

OUT

OUT

OUT

OUT

67 78

67

70

53 62 78

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

D

PMU: SWITCHERS AND LDOS

SWITCHERS BULK CAPS

MAKE_BASE=TRUE

53 62 64 65 77 81

IN

PP_VDD_MAIN

PP_VDD_MAIN

PP_VDD_MAIN

4

4

34567 8

2 1

D

C

B

81

1

C5620_RF

15UF

20%

6.3V

2

CERM
0402

RADIO_PMIC

53 62 64

IN

65 77

PP_VDD_MAIN

1

C5621_RF

15UF

20%

6.3V

2

CERM

0402
RADIO_PMIC

MAKE_BASE=TRUE

PP_VDD_MAIN

RADIO_PMIC

1

C5622_RF

15UF

20%

6.3V

2

CERM
0402

MAKE_BASE=TRUE

81

53 62 64

IN

65 77

PP_VDD_MAIN

PP_VDD_MAIN

1

C5623_RF

15UF

20%

6.3V

2

CERM
0402

RADIO_PMIC

MAKE_BASE=TRUE

53 62 64 65 77 81

IN

PP_VDD_MAIN

PP_VDD_MAIN

1

C5624_RF

15UF

20%

6.3V

2

CERM
0402

RADIO_PMIC

MAKE_BASE=TRUE

53 62 64 65 77 81

IN

PP_VDD_MAIN

PP_VDD_MAIN

1

C5625_RF

15UF

20%

6.3V

2

CERM

0402
RADIO_PMIC

DESENSE CAPS

53 62 64 65 77 81

IN

PP_VDD_MAIN

PLACE C5635 AND C5636 NEAR THE PMU

GND

4

GND

GND

4

GND

4

1

C5635_RF

100PF

5%
16V

2

NP0-C0G
01005

PP_VDD_MAIN

PP_VDD_MAIN

GND

4

PP_VDD_MAIN

PP_VDD_MAIN

1

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

4

4

MAKE_BASE=TRUE

4

4

MAKE_BASE=TRUE

81

4

4

MAKE_BASE=TRUE

C5636_RF

27PF

2%
16V
CERM
01005

L5601_RF

1UH-20%-0.054OHM-3.4A

PP_VSW_S1

2520

RADIO_PMIC

4

L5602_RF

2.2UH-20%-0.14OHM-1.6A

4

BBPMU_RF

PP_VSW_S2

0806

RADIO_PMIC

PMD9645

PP_VDD_MAIN

4

GND

4

PP_VDD_MAIN

4

GND

4

PP_VDD_MAIN

4

GND

4

PP_VDD_MAIN

4

GND

4

PP_VDD_MAIN

4

GND

4

PP_1V225_SMPS2

4

BBPMU_TO_PMU_AMUX2

4

BBPMU_TO_PMU_AMUX3-53[I16] 65 69

IN

IN

53 62 64 65 77

IN

81

67

OUT

1

2

AVDD_BYP_GND

BBPMU_TO_PMU_AMUX3

PP_VDD_BOOST

PP_VDD_MAIN

MDM_VREF_LPDDR2

AVDD_BYP

C5629_RF

0.47UF

10%

6.3V
CERM-X5R
0201

REF_BYP

1

C5601_RF

0.1UF

10%

6.3V

2

CER-X5R
01005

RADIO_PMIC

GND_REF

OMIT

2

XW5616_RF

SHORT-10L-0.1MM-SM

1

OMIT

2

XW5617_RF

SHORT-10L-0.1MM-SM

1

PLACE XW CLOSE TO PMU
VIA XW DOWN TO THE GND PLANE

VDD_OTP

1

R5601_RF

0.00

0%
1/32W
MF
01005

2

5

VDD_S1

16

VDD_S1

6

GND_S1

17

GND_S1

28

GND_S1

33

GND_S1

92

VDD_S2

103

VDD_S2

102

GND_S2

70

VDD_S3

49

GND_S3

54

GND_S3

8

VDD_S4

1

GND_S4

7

GND_S4

94

VDD_S5

93

GND_S5

86

VDD_L1_2_16

44

VDD_L3_4

14

VDD_L5_6_15

23

VDD_L7_8

89

VDD_L9

90

VIN_VPH1

47

VIN_VPH2

73

VDD_OTP

78

VREF_DDR

74

AVDD_BYP

79

REF_BYP

68

GND_REF

24

VDD_XO_RF

WLNSP

SYM 4 OF 5

POWER

RADIO_PMIC

VREG_XO

1

C5602_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

VREG_XO_GND

OMIT

2

4

XW5614_RF

SHORT-10L-0.1MM-SM

VREG_S1

VSW_S1
VSW_S1
VSW_S1

VREG_S2

VSW_S2

VREG_S3

VSW_S3
VSW_S3

VREG_S4

VSW_S4

VREG_S5

VSW_S5

VREG_L1
VREG_L2
VREG_L3

VREG_L4_16

VREG_L5
VREG_L6
VREG_L7
VREG_L8

VREG_L9
VREG_L10
VREG_L11
VREG_L12
VREG_L13
VREG_L14
VREG_L15

VREG_XO

GND_XO

VREG_RF

GND_RF_CLK

VREG_RF_CLK

4

1

C5603_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

VREG_RF_CLK_GND

OMIT

2

XW5615_RF

SHORT-10L-0.1MM-SM

10
11
22
27

91
97

69
59
64

12
2

87
99

80
81
39
48
19
3
18
29
100
84
95
85
96
101
30

34

VREG_XO

40

VREG_XO_GND

60

VREG_RF_CLK

50

VREG_RF_CLK_GND

1.0UH-20%-2.7A-0.056OHM

PP_VSW_S3

2.2UH-20%-0.14OHM-1.6A

PP_VSW_S4

1.0UH-20%-2.7A-0.056OHM

PP_VSW_S5

4

4

4

1

C5626_RF

1UF

20%
10V

2

X5R

4

0201

RADIO_PMIC

1

C5604_RF

10UF

20%

6.3V

2

CERM-X5R
0402

RADIO_PMIC

1

C5627_RF

10UF

20%

6.3V

2

CERM-X5R
0402

RADIO_PMIC

1

C5605_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

L5603_RF

2 1

0806

RADIO_PMIC

L5604_RF

0806

RADIO_PMIC

L5605_RF

0806

RADIO_PMIC

1

2

1

C5607_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

21

1

C5614_RF

43UF

20%
4V

2

X5R
0603

GND

21

1

C5615_RF

20UF

20%

6.3V

2

CERM-X5R
0402

GND

1

C5616_RF

25UF

20%

6.3V

2

X5R
0402

GND

21

1

C5617_RF

25UF

20%

6.3V

2

X5R
0402

GND

21

1

C5618_RF

25UF

20%

6.3V

2

X5R
0402

GND

MDM LOW VOLTAGE ANALOG

MDM EBI1, DDR CORE

MDM CORE

MDM PCIE

MDM HIGH VOLTAGE ANALOG

MDM 1.8V I/O, DDR, SHARED 1.8V VOLTAGE RAIL

MDM PLL

MDM LOW VOLTAGE USB

MEMORY

MDM HIGH VOLTAGE USB

UIM1

FRONT END SUPPLY

UIM2

GPS LNA
RFFE VIO

1

C5609_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

1

C5630_RF

20UF

20%

6.3V

2

CERM-X5R
0402

1

2

C5608_RF

4.7UF

20%

6.3V
X5R-CERM1
402

RADIO_PMIC

C5610_RF

1UF

20%
10V
X5R
0201

RADIO_PMIC

MDM MODEM

XO SHUTDOWN: OFF

4

LOW VOLTAGE LDOS
XO SHUTDOWN: ON

1

C5631_RF

20UF

20%

6.3V

2

CERM-X5R
0402

4

MDM MEMORY, MDM USB
XO SHUTDOWN: ON

1

C5632_RF

25UF

20%

6.3V

2

X5R
0402

4

HIGH VOLTAGE LDOS
XO SHUTDOWN: ON

1

C5633_RF

25UF

20%

6.3V

2

X5R
0402

4

CORE
XO SHUTDOWN: ON

1

C5634_RF

25UF

20%

6.3V

2

X5R
0402

4

XO SHUTDOWN: OFF

XO SHUTDOWN: BYP

XO SHUTDOWN: OFF

XO SHUTDOWN: BYP

XO SHUTDOWN: ON

XO SHUTDOWN: BYP

XO SHUTDOWN: OFF

XO SHUTDOWN: OFF

XO SHUTDOWN: ON

XO SHUTDOWN: OFF

XO SHUTDOWN: ON

XO SHUTDOWN: OFF

XO SHUTDOWN: OFF

XO SHUTDOWN: OFF

XO SHUTDOWN: BYP

1

C5611_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

1

C5628_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

1

C5613_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

1

C5612_RF

1UF

20%
10V

2

X5R
0201

RADIO_PMIC

BBPMU_TO_PMU_AMUX1

PP_1V225_SMPS2

BBPMU_TO_PMU_AMUX2

BBPMU_TO_PMU_AMUX3

PP_1V0_SMPS5

PP_1V5_LDO1

PP_1V2_LDO2

PP_0V9_LDO3

PP_0V95_LDO4

PP_1V7_LDO5

PP_1V8_LDO6

PP_1V8_LDO7

PP_1V8_LDO8

PP_1V0_LDO9

PP_3V075_LDO10

VDD_SIM1

PP_2V7_LDO12

VDD_SIM2

PP_1V8_LDO14

PP_1V8_LDO15

4

4

BBPMU_TO_PMU_AMUX1-53[I16] 65 66

OUT

BBPMU_TO_PMU_AMUX3-53[I16] 65 69

OUT

66

OUT

66

OUT

66

OUT

69

OUT

66

OUT

66

OUT

OUT

64 66

OUT

66

OUT

66

OUT

66

OUT

81
66

OUT

75
73

OUT

74

66

OUT

71

OUT

68

OUT

73 74 75 77 79 80

0.90V/2685MA

1.25V/693MA

1.16V/1951MA

1.85V/1241MA

C

1.01V/1059MA

1.23V/124MA

1.20V/569MA

1.00V/610MA

1.00V/88MA

1.80V/52MA

1.80V/366MA

1.80V/15MA

1.80V/133MA

1.11V/1253MA

3.20V/15MA

1.80V/60MA

2.70V/62MA

1.80V/60MA

2.70V/5MA

1.80V/245MA

B

A

1

XO_GND

1

RF_CLK_GND

PLACE XW CLOSE TO PMU
VIA XW DOWN TO THE GND PLANE

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

BBPMU_TO_PMU_AMUX1

4 5

BBPMU_TO_PMU_AMUX2

4

BBPMU_TO_PMU_AMUX3

4 8

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

BBPMU_TO_PMU_AMUX1

BBPMU_TO_PMU_AMUX2

BBPMU_TO_PMU_AMUX3

OUT

OUT

OUT

62

62

62

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

BASEBAND: POWER

34567 8

2 1

D

C

B

PP_1V0_SMPS5

5 4

PP_1V0_LDO9

5 4

V16
V17

F12
F13

F9
G11
G12
G16
G17

G8

G9
H15
H16

J18
J19

K15

L15
M15
M16
M17

P15
P16
R15
R16
U16

U7
U8

E19

F18

F19

G18

H10
H13
H14

H8

H9
J12
J13
J14
J15

J7
J8

K18

L17

L18
M12
M13

N12

N7

P6

P7
T12
T18

T6

U11
U12
U13
U18

U6

V18

VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE

VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM

BB_RF

MDM9645

BGA

SYM 6 OF 8

PWR1

VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM

F7

BBPMU_TO_PMU_AMUX1

F8
G7
J11
K10
K11
K14
K6
K7
L10
L13
L14
L6
L9
M8
M9
N11
N8
P10
P11
P14
R10
R13
R14
R8
R9
T13
T8
T9

5 4

4 5

1

C5755_RF

2.2UF

20%

6.3V

2

X5R-CERM

0201-1
RADIO_PMIC

20 17 7 6 5 4

20 17 7 6 5 4

20 4

20 17 7 6 5 4

5 4

PP_1V2_LDO2

1

C5729_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

PP_1V8_LDO6

PP_1V8_LDO6

1

C5730_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

VDD_SIM1

VDD_SIM2

4

PP_1V8_LDO6

PP_1V8_LDO8

4

PP_3V075_LDO10

4

PP_0V95_LDO4

(PP_UIM1_LDO11)

(PP_UIM2_LDO13)

1

C5731_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5733_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5734_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5732_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5736_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5737_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5735_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5739_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5740_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5738_RF

20%

6.3V

2

0201-1

RADIO_PMIC

1

C5742_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5704_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

NOSTUFF

1

C5741_RF

0.1UF

20%
4V

2

X5R

01005

RADIO_PMIC

NOSTUFF

1

C5743_RF

2.2UF2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

C22
D22

G22

H22

L22

M22

T22

U22

W2

Y2

R23

AA23
AB16

E2
K2
P2

AA21

AA15

AB11

M19

V9

AA10

AB3

NC

W3

NC

AA3

NC

Y5
Y6
Y7

1

C5744_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

VDD_P1
VDD_P1
VDD_P1
VDD_P1
VDD_P1
VDD_P1
VDD_P1
VDD_P1
VDD_P1
VDD_P1

VDD_P2

VDD_P3
VDD_P3
VDD_P3
VDD_P3
VDD_P3

VDD_P4

VDD_P5

VDD_P7
VDD_P7

VDD_USB_HS_1P8
VDD_USB_HS_3P3

VDD_USB_SS_0P9
VDD_USB_SS_0P9
VDD_USB_SS_1P8

VDD_PCIE_0P9
VDD_PCIE_0P9
VDD_PCIE_1P8

BB_RF

MDM9645

BGA

SYM 7 OF 8

PWR2

VDD_DDR_CORE_1P8
VDD_DDR_CORE_1P8
VDD_DDR_CORE_1P8
VDD_DDR_CORE_1P8

VDD_DDR_CORE_1P2
VDD_DDR_CORE_1P2
VDD_DDR_CORE_1P2
VDD_DDR_CORE_1P2
VDD_DDR_CORE_1P2

VREF_SDC

VREF_UIM

VDD_A3
VDD_A3

VDD_A2
VDD_A1
VDD_A2
VDD_A1
VDD_A2
VDD_A1

VDD_A2
VDD_A2

VDD_A1
VDD_A1

VDD_A2
VDD_A2
VDD_A2
VDD_A2

VDD_USB_HS_MX

VDD_ALWAYS_ON

VDD_PLL
VDD_PLL

VDD_QFPROM_PRG

B23
E1
K23
U1

AA1
C23
D1
J23
W1

U21
Y20

E7
E17

B12
B3
B15
B7
B18
B8

C12
C15

B10
E10

C18
C6
C7
E3

V11

U14

E13
P19

F10

NC

1

C5745_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5746_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5747_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5748_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5749_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC
NOSTUFF

1

C5750_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

RADIO_PMIC

1

C5751_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

1

C5753_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

PP_1V8_LDO6

PP_1V2_LDO2

5 4

VDDPX_BIAS_UIM2

PP_1V0_LDO9

1

C5754_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

PP_1V7_LDO5

PP_1V5_LDO1

PP_0V95_LDO4

PP_1V8_LDO7

PP_1V8_LDO7

A1

GND

A11

GND

A12

GND

A15

GND

A17

GND

A2

GND

A22

GND

A23

GND

A4

GND

A6

GND

A7

20 17 7 6 5 4

AB10
AB15
AB21
AB23

3

5 4

1

C5752_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_PMIC

4

4

5 4

5 4 3

5 4 3

A9
AA5
AB1

AB5
AB7
AB9

B13
B19
B20
B21
B22

B5

C1
C11
C16

C2
C20
C21

C4

C9

D2
D21
D23
E14
E15
E16
E18
E21
E22
E23

E6
E8

E9
F11
F14
F15
F16
F17
F23

G10
G13
G14
G15
G19
G23

H11
H12
H17
H18
H19
H23

H6

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

BB_RF

MDM9645

BGA

SYM 8 OF 8

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

H7
J10
J16
J17
J22
J6
J9
K1
K12
K13
K16
K17
K8
K9
L11
L12
L16
L23
L7
L8
M10
M11
M14
M18
M6
M7
N10
N13
N14
N15
N16
N17
N18
N6
N9
P1
P12
P13
P17
P18
P8
P9
R11
R12
R17
R18
R7
T10
T11
T14

T15
T16
T17
T23
T7
U10
U15
U17
U23
U9
V1
V6
Y4
Y8

D

C

B

A

PP_1V0_SMPS5

5 4

BBPMU_TO_PMU_AMUX1

4 5

PP_1V0_LDO9

5 4

(MSM CORE)

1

C5705_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5708_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

(MSM MODEM)

1

C5706_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5709_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

(MODEM SUB MEMORY)

1

C5707_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5710_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5711_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5712_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5713_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5714_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5715_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5716_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5717_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5718_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5719_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5720_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5721_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5722_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5723_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5724_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5725_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5726_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5727_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5728_RF

2.2UF

20%
4V

2

X5R-CERM
0201

RADIO_BB

1

C5701_RF

15UF

20%

6.3V

2

CERM
0402

RADIO_BB

1

C5702_RF

15UF

20%

6.3V

2

CERM
0402

RADIO_BB

1

C5703_RF

15UF

20%

6.3V

2

CERM
0402

RADIO_BB

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

D

BASEBAND: CONTROL AND INTERFACES

BB_RF

MDM9645

BGA

SYM 1 OF 8

64 78

IN

64 78

OUT

64

IN

78 81

IN

PP_1V8_LDO6 MDM_VREF_LPDDR2

6 5 4

20

1

R5807_RF

1.00K

5%
1/32W
MF
01005

2

17 6

64 78

IN

SWD_AP_TO_BB_CLK_BUFFER

SWD_AOP_BI_BB_SWDIO

1 20

SHIELD_SLEEP_CLK_32K

XO_OUT_D0_EN

SHIELD_MDM_19P2M_CLK

BB_JTAG_RST_L

PMIC_RESOUT_L

T2

SLEEP_CLK

U3

CXO_EN

F2

CXO

V19

SRST*

V3 U2

RESIN*

R6
T3

W23

U19

W22

V22
V21

MODE_0
MODE_1

TCK
TRST*
TMS
TDI
TDO

NC

NC

NC

NC

NC

CONTROL

RESOUT*

PS_HOLD

SDC1_CLK

SDC1_CMD
SDC1_DATA_0
SDC1_DATA_1
SDC1_DATA_2
SDC1_DATA_3

SPMI_CLK

SPMI_DATA

V2

R21
V23
T21
T19
R19
R22

Y17
AB18

NC

PS_HOLD

NC

NC
NC

NC

NC
NC

SPMI_CLK

SPMI_DATA

OUT

64

64 78

BI

64 78

BI

1

R5801_RF

240

1%
1/32W
MF
01005

2

RADIO_BB

1

R5802_RF

240

1%
1/32W
MF
01005

2

RADIO_BB

PLACEPLACE
CLOSECLOSE
TO T3TO E1

BDM_CAL

EBI1_CAL

4

1

C5804_RF

0.1UF

10%
10V

2

X5R-CERM

0201

RADIO_BB

34567 8

D3

BDM_ZQ

V5

EBI1_CAL

K22

VREF_DQ_BDM

G21

EBI1_VREF

K21

EBI1_VREF

U5

EBI1_VREF

2 1

D

BB_RF

MDM9645

BGA

SYM 4 OF 8

MEMORY

C

B

64

IN

20 17 7 6 5 4

VREF_DAC_BIAS

PP_1V8_LDO6

SWD_AP_TO_MANY_SWCLK

1 20

1

C5801_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

71

71

71

71

71

71

71

71

71

71

71

71

NOSTUFF AT CARRIER

NOSTUFF

C

U5801_RF

74AUP1G34GX

5

SOT1226

2

NC

3

1

NC

SHIELD_XCVR0_PRX_CA2_I

IN

SHIELD_XCVR0_PRX_CA2_Q

IN

SHIELD_XCVR0_DRX_CA2_I

IN

SHIELD_XCVR0_DRX_CA2_Q

IN

SHIELD_XCVR1_DRX_I

IN

IN

IN

IN

IN

IN

SHIELD_XCVR1_DRX_Q

IN

IN

SHIELD_XCVR1_PRX_I

SHIELD_XCVR1_PRX_Q

SHIELD_XCVR0_PRX_CA1_I

SHIELD_XCVR0_PRX_CA1_Q

SHIELD_XCVR0_DRX_CA1_I

SHIELD_XCVR0_DRX_CA1_Q

SWD_AP_TO_BB_CLK_BUFFER

4

NC

NC

NC

NC

B9

BBRX_IP_CH0

A10

BBRX_QP_CH0

A8

BBRX_IP_CH1

C8

BBRX_QP_CH1

C5

BBRX_IP_CH2

B6

BBRX_QP_CH2

B4

BBRX_IP_CH3

A5

BBRX_QP_CH3

C13

TX_DAC_VREF

C19

TX_DAC_VREF

A3

BBRX_IP_CH5

C3

BBRX_QP_CH5

B2

BBRX_IP_CH6

B1

BBRX_QP_CH6

F21

NC

F22

NC

H21

NC

J21

NC

17 6

BB_RF

MDM9645

BGA

SYM 2 OF 8

ANALOG_RF

BBRX_IP_FB

BBRX_QP_FB

GNSS_BB_IP

GNSS_BB_QP

TX_DAC0_IP

TX_DAC0_IM

TX_DAC0_QP

TX_DAC0_QM

TX_DAC1_IP

TX_DAC1_IM

TX_DAC1_QP

TX_DAC1_QM

ET_DAC0_P

ET_DAC0_M

ET_DAC1_P

ET_DAC1_M

DNC
DNC
DNC
DNC
DNC

C10

B11

E11

E12

C17
B17
A16
B16

C14
B14
A13
A14

A20
A21
A18
A19

F1
F6
G1
G6
Y3

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

SHIELD_XCVR0_TX_FB_RX_I

SHIELD_XCVR0_TX_FB_RX_Q

SHIELD_GPS_RX_I

SHIELD_GPS_RX_Q

SHIELD_XCVR0-1_TX_I_P

SHIELD_XCVR0-1_TX_I_N

SHIELD_XCVR0-1_TX_Q_P

SHIELD_XCVR0-1_TX_Q_N

SHIELD_ET_DAC_P

SHIELD_ET_DAC_N

OUT

OUT

OUT

OUT

OUT

OUT

70 71

IN

BB_RF

MDM9645

70 71

IN

71

IN

64 78

IN

50_MDM_PCIE_CLK

BB_USB_TRXTUNE

71

IN

90_USB_BB_DATA_P

BI

90_USB_BB_DATA_N

70

70

70

70

53 62 78

81

53 62 78

81

1

R5806_RF

4.02K

1%
1/32W
MF
01005

2

NC

NC

NC

NC

AA9

PCIE_USB_SYSCLK

Y9

USB_HS_REXT

V10

USB_HS_DP

Y10

USB_HS_DM

AB2

USB_SS_TX_P

AA2

USB_SS_TX_M

AA4

USB_SS_RX_P

AB4

USB_SS_RX_M

PLACE
CLOSE
TO U12

77

77

NC

Y1

USB_SS_REXT

BGA

SYM 5 OF 8

USB_PCIE

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_TX_P

PCIE_TX_M

PCIE_RX_P

PCIE_RX_M

PCIE_REXT

V8
V7

AB6
AA6

AA8
AB8

AA7

90_PCIE_AP_TO_BB_REFCLK_P

90_PCIE_AP_TO_BB_REFCLK_N

PCIE_CAL_RES

1

R5803_RF

1.43K

1%
1/32W
MF
01005

2

RADIO_BB

PLACE
CLOSE

53 62 78

IN

53 62 78

IN

90_PCIE_BB_TO_AP_RXD_P

90_PCIE_BB_TO_AP_RXD_N

90_PCIE_AP_TO_BB_TXD_P

90_PCIE_AP_TO_BB_TXD_N

OUT

OUT

53 62

53 62

53 62

IN

53 62

IN

B

TO AA10

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8 7 5 4 2 1

36

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

D

C

BASEBAND: GPIOS

PP_1V8_LDO6

4 5 6 7 17 20

R5912_RF

RADIO_BB

SKU

ROW

R5911_RF
NOSTUFF

JP 1.0 KOHM

R5912_RF
NOSTUFF

NOSTUFF

MAV13 = BB_LAT_0

RF_BB_LAT_1

RF_BB_LAT_2
RF_BB_LAT_3

NOSTUFF

78 79
80

73 80

53 62 78

73 78

73 78

1.00K

1/32W

01005

53 62

IN

53 62

IN

53 62

OUT

53 62

IN

53 62 78

OUT

53 62

IN

OUT

OUT

OUT

74 78

OUT

OUT

OUT

1%

MF

17

17 18 19

12 19

1

2

OMIT_TABLE

SKU_ID2

7

7

BB_EEPROM_I2C_SDA

BB_EEPROM_I2C_SCL
I2S_BB_TO_AP_LRCLK

I2S_AP_TO_BB_DOUT

I2S_BB_TO_AP_DIN
I2S_BB_TO_AP_BCLK

UART_BB_TO_AOP_RXD

UART_AOP_TO_BB_TXD

FAST_BOOT_SELECT0

75_RFFE6_SCLK

75_RFFE6_SDATA

75_RFFE7_SCLK

75_RFFE7_SDATA

BB_TO_STROBE_DRIVER_GSM_BURST_IND

RX-DSPDT_CTL2 SIM1_DETECT

FBRX-DSPDT_CTL1

FBRX-DSPDT_CTL2

R5911_RF

1.00K

1%

1/32W

MF

01005

RADIO_BB

MAV13 = WDOG DIS

1

2

SKU_ID

NC
NC

NC
NC

NC

NC

NC
NC

NC
NC

NC

NC
NC

NC

NC

NC

NC

NC

NC

NC

NC

V15
AA19
AB14

Y15

T1
R3
R2
R1

T5
P3
R5
P5

V13

AA12

Y13

AA13

V14

AA14

Y14
AB13
AB19

P21

P23

Y18

N19

P22

N3
N2
N1

N5
M3
M2
M1
M5

L5
L3
L2
L1

N22

F5

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39

BB_RF

MDM9645

BGA

SYM 3 OF 8

GPIO

GPIO_40
GPIO_41
GPIO_42
GPIO_43
GPIO_44
GPIO_45
GPIO_46
GPIO_47
GPIO_48
GPIO_49
GPIO_50
GPIO_51
GPIO_52
GPIO_53
GPIO_54
GPIO_55
GPIO_56
GPIO_57
GPIO_58
GPIO_59
GPIO_60
GPIO_61
GPIO_62
GPIO_63
GPIO_64
GPIO_65
GPIO_66
GPIO_67
GPIO_68
GPIO_69
GPIO_70
GPIO_71
GPIO_72
GPIO_73
GPIO_74
GPIO_75
GPIO_76
GPIO_77
GPIO_78
GPIO_79

F3
K3
K5
J3
J2
J1
J5
H3
H2
H1
Y16
N23
AA16
V12
K19
Y23
L19
AA22
M23
AB22
Y12
AB17
Y22
M21
Y11
AA11
L21
W21
AA17
AA18
N21
AB12
H5
G3
G2
G5
Y21
Y19
AB20
AA20

NC

NC
NC

NC

NC

NC
NC

NC

NC

NC

NC

NC

NC

SHIELD_GSM_TX_PHASE

75_RFFE3_SDATA

75_RFFE3_SCLK

75_RFFE4_SDATA

75_RFFE4_SCLK

BB_TO_LAT_ANT_DATA
BB_TO_LAT_ANT_SCLK

AP_TO_BB_TIME_MARK

UART_BB_TO_WLAN_COEX

UART_WLAN_TO_BB_COEX

BB_TO_AP_RESET_DETECT_L
AP_TO_BB_COREDUMP

AP_TO_BB_IPC_GPIO1

RFCAL_QCN

BB_TO_PMU_PCIE_HOST_WAKE_L

PCIE_BB_BI_AP_CLKREQ_L

AP_TO_BB_MESA_ON

FAST_BOOT_SELECT1

SIM1_REMOVAL_ALARM

75_RFFE2_SDATA

75_RFFE2_SCLK

75_RFFE1_SDATA

75_RFFE1_SCLK

SIM1_IO

SIM1_RST
SIM1_CLK

17

BI

OUT

BI

OUT

17 7 1

17 7 1

IN

OUT

IN

OUT

IN

BI

OUT

BI

BI

BI

BI

OUT

BI

BI

BI

IN

OUT

74 78

74 78

70 78

70 78

53 62 78

WDOG DIS CONFLICT

53 62
78 81

53 62 78 81

53 62 78

53 62 78

53 62

53 62 78

53 62 68

53 62

64 78

77 78

77 78

70 78

70 78

78 81

78 81

78 81

78 81

1

C5902_RF

22PF

2%
16V

2

CERM
01005

1

C5903_RF

100PF

5%
16V

2

NP0-C0G
01005

1

2

34567 8

70

OUT

PLACE CAP CLOSE TO MDM

IMPROVES RXBN BY 4DB

PP_1V8_LDO15

4 12 13 14 16 18 19

BB_TO_LAT_ANT_SCLK

17 7 1

BB_TO_LAT_ANT_DATA

17 7 1

PCIE_AP_TO_BB_RESET_L

1 20

PP1V8_SDRAM

1

C5906_RF

0.01UF

10%

6.3V
X5R
01005

C5907_RF

33PF

5%
16V

2

NP0-C0G-CERM
01005

IN

53 62 64

2 1

BUFFER ON RFFE5

SCLK/SDATA_A IS OUTPUT

RFBUF_RF

RF1352

4

17 7 1

17 7 1

WLCSP

VIO

SCLK

SDATA

GND

7

BB_TO_LAT_ANT_SCLK

BB_TO_LAT_ANT_DATA

SDATA_A

GPO1
GPO2

SCLK_A

1
8

52

63

BB_TO_UAT_SCLK

BB_TO_UAT_DATA

USID=0XF

R5909_RF

0.00

0%

1/32W

MF

01005

RADIO_BB

NOSTUFF

R5910_RF

0.00

0%

1/32W

MF

01005

RADIO_BB

NOSTUFF

BB_BUFFER_GPO1
BB_BUFFER_GPO2

21

21

BB_TO_UAT_SCLK

BB_TO_UAT_DATA

D

1

1

14 7 1

14 7 1

14 7 1

14 7 1

C

B

RFFE USAGE TABLE

RFFE1 WTR3925
RFFE2 QFE3100

RFFE3 DIV MODULES

RFFE4 WTR4905

RFFE5 TUNERS + ELNAS

RFFE6 2G PA,MLB PA,MB/HB TDD PA,MB/HB FDD PA

17 7 1

17 7 1

BB_TO_LAT_ANT_SCLK

BB_TO_LAT_ANT_DATA

A3

A1

A2

VIO

SCLK

SDATA

GPIO_RF

QM18064

WLCSP

GND

B3

GPO1

GPO2

GPO3
GPO4

A4
B1
B2
B4

NC

USID=0X8

BB_TO_LAT_GPO1

BB_TO_LAT_GPO2

BB_TO_LAT_GPO3

1

1

1

B

A

PP_1V8_LDO6

4 5 6 7 17 20

100K

1%

1/32W

MF

01005

1

2

PCIE_BB_BI_AP_CLKREQ_L

7 1

R5906_RF

RADIO_BB

NOSTUFF

PCIE PULL-UPS TO BB RAIL

RFFE7 LB PA, COUPLERS

BB EEPROM

PP_1V8_LDO6

1

1

R5907_RF

10K

1%
1/32W
MF
01005

2

RADIO_BB

VCC

EPROM_RF

CAT24C08C4A

BB_EEPROM_I2C_SCL

7 7

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

WLCSP

RADIO_BB

VSS

A2 A1

C5901_RF

1UF

20%
10V

2

X5R
0201

RADIO_BB

SDASCL

1

R5908_RF

10K

1%
1/32W
MF
01005

2

RADIO_BB

B2B1

BB_EEPROM_I2C_SDA

4 5 6 7 17 20

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

TRANSCEIVER: POWER

34567 8

2 1

D

C

STAR ROUTING

65 69

IN

PP_0V9_LDO3

DEFAULT_CAPACITOR_1e+06pF_2_1

1

C6001_RF

10UF

20%

6.3V

2

CERM-X5R
0402

RADIO_TRANSCEIVER

RADIO_TRANSCEIVER

DEFAULT_RESISTOR_0.001OHM_2_1

R6001_RF

0.00

0%

1/32W

MF

01005

21

PP_VDD_XCVR0_RF1_TX_VCO

DEFAULT_CAPACITOR_100000pF_2_1

1

C6018_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

R6005_RF

0.00

1/32W

01005

DEFAULT_RESISTOR_0.001OHM_2_1

21

0%

MF

PP_VDD_XCVR0_RF1_TX

DEFAULT_CAPACITOR_100000pF_2_1

1

C6019_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

R6006_RF

0.00

1/32W

01005

DEFAULT_RESISTOR_0.001OHM_2_1

21

0%

MF

PP_VDD_XCVR0_RF1_DIG

DEFAULT_CAPACITOR_100000pF_2_1

1

C6020_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

R6007_RF

0.00

1/32W

01005

DEFAULT_RESISTOR_0.001OHM_2_1

21

0%

MF

PP_VDD_XCVR0_RF1_RX1

DEFAULT_CAPACITOR_100000pF_2_1

1

C6021_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

R6008_RF

0.00

0%

1/32W

MF

01005

21

PP_VDD_XCVR0_RF1_RX2

DEFAULT_CAPACITOR_100000pF_2_1

1

C6022_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

35MA

DEFAULT_CAPACITOR_27.000000pF_2_1

1

C6010_RF

27PF

5%
16V

2

NP0-C0G
01005

RADIO_TRANSCEIVER

175MA

1

C6011_RF

27PF

5%
16V

2

NP0-C0G
01005

RADIO_TRANSCEIVER

25MA

DEFAULT_CAPACITOR_27.000000pF_2_1

1

C6012_RF

27PF

5%
16V

2

NP0-C0G
01005

RADIO_TRANSCEIVER

40MA

DEFAULT_CAPACITOR_27.000000pF_2_1

1

C6013_RF

27PF

5%
16V

2

NP0-C0G
01005

RADIO_TRANSCEIVER

250MA

DEFAULT_CAPACITOR_27.000000pF_2_1

1

C6014_RF

27PF

5%
16V

2

NP0-C0G
01005

RADIO_TRANSCEIVER

88

VDD_RF1_TVCO

67

VDD_RF1_TSIG

45

VDD_RF1_DIG

64

VDD_RF1_RX1

49

VDD_RF1_RX2

XCVR0_RF

WTR3925-2-TR-03-1

WLPSP

SYM 4 OF 5

PWR

RADIO_TRANSCEIVER

LDO_CAP

VDD_RF2

23

30

C6380_RF CAN BE 0201 (TBD)

VDD_XCVR0_RF2_LDO_BYPASS

1

C6024_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

250MA

DEFAULT_CAPACITOR_100000pF_2_1

1

C6003_RF

0.47UF

20%
4V

2

CERM-X5R-1
201

RADIO_TRANSCEIVER

BBPMU_TO_PMU_AMUX3

DEFAULT_CAPACITOR_4700pF_2_1

1

C6005_RF

4700PF

10%

6.3V

2

X5R
01005

RADIO_TRANSCEIVER

BBPMU_TO_PMU_AMUX3-53[I16] 65 69

IN

58
56
42
72

28
84
21
91
20
90
19
89

102

55

XCVR0_RF

WTR3925-2-TR-03-1

3

GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

RADIO_TRANSCEIVER

GNDGND

GND
GND
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND

94

87
81
17
52
37
36
61

53
54

57
82
83
26
27
71
63
41
48

38
25
31

C

D

B

A

XCVR1_RF

WTR4905

WLNSP

9

GND

13

GND

16

GND

21

GND

24

STAR ROUTING

65 69

IN

PP_0V9_LDO3

1

C6006_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

RADIO_TRANSCEIVER

RADIO_TRANSCEIVER

RADIO_TRANSCEIVER

DEFAULT_RESISTOR_0.001OHM_2_1

R6002_RF

0.00

1/32W

01005

0%

MF

21

PP_VDD_XCVR1_RF1_DIG

1

C6007_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

RADIO_TRANSCEIVER

R6003_RF

0.00

1/32W

01005

0%

MF

21

PP_VDD_XCVR1_RF1_RX

1

C6008_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

RADIO_TRANSCEIVER

25MA

1

C6015_RF

27PF

5%
16V

2

NP0-C0G
01005

RADIO_TRANSCEIVER

40MA

DEFAULT_CAPACITOR_27.000000pF_2_1

1

C6016_RF

27PF

5%
16V

2

NP0-C0G
01005

50

VDD_RF1_DIG

33

VDD_RF1_RX

23

VDD_RF1_TX

XCVR1_RF

WTR4905

WLNSP

SRM 4 OF 5

PWR

VDD_RF2

VDD_RF2_LDO

250MA

1

2

44

34

VDD_XCVR1_RF2_LDO_BYPASS

1

2

C6002_RF

0.47UF

20%
4V

CERM-X5R-1

201

RADIO_TRANSCEIVER

C6023_RF

2.2UF

20%

6.3V
X5R-CERM
0201-1

BBPMU_TO_PMU_AMUX3

DEFAULT_CAPACITOR_4700pF_2_1

1

C6004_RF

4700PF

10%

6.3V

2

X5R
01005

RADIO_TRANSCEIVER

IN

BBPMU_TO_PMU_AMUX3-53[I16] 65 69

25
26
27
29
30

GND
GND
GND
GND
GND
GND

R6004_RF

0.00

0%

1/32W

MF

01005

21

PP_VDD_XCVR1_RF1_TX

1

C6009_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

RADIO_TRANSCEIVER

1

C6017_RF

27PF

5%
16V

2

NP0-C0G
01005

RADIO_TRANSCEIVER

175MA

SYM 5 OF 5

GND

SYNC_MASTER=Sync

PAGE TITLE

GND
GND
GND
GND
GND
GND
GND
GND
GND

32
35
37
39
40
42
45
48
52

SYNC_DATE=05/17/2016

B

A

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8 7 5 4 2 1

36

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

TRANSCEIVER: TX PORTS

50_XCVR0_TX_HMB1_B11_B21

9

34567 8

OMIT_TABLE

C6106_RF

27PF

01005

RADIO_TRANSCEIVER

2%

16V

CERM

2 1

21

50_XCVR0_TX_B11_B21_PA_IN

OUT

80

D

C

DEFAULT_INDUCTOR_2.800000nH_2_1

L6110_RF

2.8NH-+/-0.1NH-0.36A

50_XCVR0_TX_HMB2_B38_B40_B41

9

XCVR0_RF

01005

WTR3925-2-TR-03-1

WLPSP

67 70

67 70

67 70

67 70

67 71

67 71

68 78

68 78

SHIELD_XCVR0-1_TX_I_P

IN

SHIELD_XCVR0-1_TX_I_N

IN

SHIELD_XCVR0-1_TX_Q_P

IN

SHIELD_XCVR0-1_TX_Q_N

IN

SHIELD_XCVR0_TX_FB_RX_I

OUT

SHIELD_XCVR0_TX_FB_RX_Q

OUT

75_RFFE1_SCLK

IN

75_RFFE1_SDATA

IN

DEFAULT_CAPACITOR_1000pF_2_1

76

TX_BB_IP

75

TX_BB_IM

68

TX_BB_QP

60

TX_BB_QM

9

TX_FBRX_BBI

1

TX_FBRX_BBQ

47

RFFE_CLK

62

RFFE_DATA

C6110_RF

1000PF

64 70

SHIELD_WTR_19P2M_CLK

IN

21

10%

6.3V

X5R-CERM

01005

SHIELD_XCVR0_19P2M_CLK_WTR_IN

1

C6112_RF

1.0PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

46

XO_IN

SYM 3 OF 5

TX

RADIO_TRANSCEIVER

TX_LB1
TX_LB2
TX_LB3
TX_LB4

TX_MHB1
TX_MHB2
TX_MHB3
TX_MHB4

TX_HMLB1
TX_HMLB2

TX_FBRX_P

TX_FBRX_M

66

NC

59

NC

51

NC

44

NC

50_XCVR0_TX_HMB1_B11_B21

101

50_XCVR0_TX_HMB2_B38_B40_B41

100

50_XCVR0_TX_HMB3_B1_B3_B4_B25

93

50_XCVR0_TX_HMB4_B7_B30

86

80

NC

50_XCVR0_TX_HMLB2_B34_B39

74

8
16

100_XCVR0_TX_FBRX_IN_WTR

NC

9

9

9

9

9

1

C6118_RF

1.5PF

+/-0.1PF
16V

2

NP0-C0G
01005-1

3.0NH+/-0.1NH-200MA

L6111_RF

01005

C6107_RF

27PF

50_XCVR0_TX_HMB3_B1_B3_B4_B25

9

C6105_RF

27PF

21

50_XCVR0_TX_FBRX_IN_UNBAL

1

C6117_RF

1.5PF

+/-0.1PF
16V

2

NP0-C0G
01005-1

RADIO_TRANSCEIVER

2%

16V

CERM

01005

21

50_XCVR0_TX_FBRX_IN

50_XCVR0_TX_HMB4_B7_B30

9

73

IN

RADIO_TRANSCEIVER

L6109_RF

2.8NH-+/-0.1NH-0.36A

21

2%

16V

CERM

01005

DEFAULT_INDUCTOR_2.800000nH_2_1

01005

21

50_XCVR0_TX_HMB2_B38_B40_B41_MATCH

DEFAULT_CAPACITOR_1.200000pF_2_1

1

C6113_RF

1.2PF

+/-0.05PF
16V

2

NP0-C0G-CERM
01005

1

L6102_RF

10NH-3%-140MA

2

21

50_XCVR0_TX_HMB4_B7_B30_MATCH

DEFAULT_CAPACITOR_1.200000pF_2_1

1

C6114_RF

1.2PF

+/-0.05PF
16V

2

NP0-C0G-CERM
01005

01005

NOSTUFF

RADIO_TRANSCEIVER

C6115_RF

DEFAULT_CAPACITOR_22.000000pF_2_1

C6116_RF

22PF

21

50_XCVR0_TX_B38_B40_B41_PA_IN

5%

16V

CERM

01005

50_XCVR0_TX_B1_B3_B4_B25_PA_IN

DEFAULT_CAPACITOR_22.000000pF_2_1

22PF

21

50_XCVR0_TX_B7_B30_PA_IN

5%

16V

CERM

01005

OUT

OUT

OUT

D

79

80

80

C

B

50_XCVR1_TX_HMLB1_G1800_G1900

9

C6101_RF

27PF

21

2%

16V

CERM

RADIO_TRANSCEIVER

01005

50_XCVR0_TX_HMLB2_B34_B39

9

50_XCVR1_TX_G1800_G1900_PA_IN

1

L6101_RF

10NH-3%-140MA

01005

NOSTUFF

RADIO_TRANSCEIVER

2

C6108_RF

27PF

21

2%

16V

CERM

RADIO_TRANSCEIVER

01005

OUT

79

50_XCVR0_TX_B34_B39_PA_IN

OUT

79

B

A

C6102_RF

27PF

2%

16V

CERM

01005

21

1

50_XCVR1_TX_B8_B20_B26_B27_PA_IN

OUT

80

L6103_RF

10NH-3%-140MA

01005

NOSTUFF

RADIO_TRANSCEIVER

2

67 70

67 70

67 70

67 70

68

SHIELD_XCVR0-1_TX_I_P

IN

SHIELD_XCVR0-1_TX_I_N

IN

SHIELD_XCVR0-1_TX_Q_P

IN

SHIELD_XCVR0-1_TX_Q_N

IN

SHIELD_GSM_TX_PHASE

IN

14

TX_BB_IP

19

TX_BB_IM

3

TX_BB_QP

8

TX_BB_QM

57

GP_DATA

XCVR1_RF

WTR4905

WLNSP

SYM 2 OF 5

TX

TX_DA1
TX_DA2
TX_DA3
TX_DA4
TX_DA5

TX_FBRX

1

50_XCVR1_TX_HMLB1_G1800_G1900

18

50_XCVR1_TX_HMLB2_B8_B20_B26_B27

12

NC

2

50_XCVR1_TX_HMLB4_B12_B13_B28

7

50_XCVR1_TX_HMLB5_G850_G900

31

50_XCVR1_TX_FBRX_IN

9

9

9

9

12

50_XCVR1_TX_HMLB2_B8_B20_B26_B27

9

RADIO_TRANSCEIVER

C6103_RF

68 78

68 78

75_RFFE4_SDATA

IN

75_RFFE4_SCLK

56

RFFE_DATA

51

RFFE_CLK

50_XCVR1_TX_HMLB4_B12_B13_B28

9

DEFAULT_CAPACITOR_1000pF_2_1

55

C6109_RF

XO_IN

100PF

64 70

SHIELD_WTR_19P2M_CLK SHIELD_XCVR1_19P2M_CLK_WTR_IN

IN

5%

6.3V
CERM

01005

21

1

C6111_RF

68PF

5%
25V

2

NP0-C0G-CERM
01005

NOSTUFF

50_XCVR1_TX_HMLB5_G850_G900

9

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

C6104_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

1

L6104_RF

10NH-3%-140MA

01005

NOSTUFF

RADIO_TRANSCEIVER

2

50_XCVR1_TX_B12_B13_B28_PA_IN

50_XCVR1_TX_G850_G900_PA_IN

OUT

OUT

80

79

OFFPAGE=TRUE

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

TRANSCEIVER: PRX, DRX, & GPS PORTS

34567 8

2 1

D

50_XCVR0_PRX_PMB1_B4

11

50_XCVR0_PRX_PMB2_B1_B4

11

50_XCVR0_PRX_PMB3_B3

11

50_XCVR0_PRX_PMB4_B34_B39

11

50_XCVR0_PRX_PMB5_B25

11

50_XCVR0_PRX_PMLB6_B11_B21

11

50_XCVR0_PRX_PHB1_B7

11

50_XCVR0_PRX_PHB2_B40_EXT

11

50_XCVR0_PRX_PHB3_B38_B40_B41

11

50_XCVR0_PRX_PHB4_B30

11

NC
NC

NC
NC

104

96

103

95

99
92

106

98

105

97

73
65
85
79

XCVR0_RF

WTR3925-2-TR-03-1

WLPSP

PRX_LB1
PRX_LB2
PRX_LB3
PRX_LB4

PRX_MB1
PRX_MB2
PRX_MB3
PRX_MB4
PRX_MB5
PRX_MLB6

PRX_HB1
PRX_HB2
PRX_HB3
PRX_HB4

SYM 1 OF 5

PRX

RADIO_TRANSCEIVER

PRX_CA1_BBI

PRX_CA1_BBQ

PRX_CA2_BBI

PRX_CA2_BBQ

69

77

39

33

SHIELD_XCVR0_PRX_CA1_I

SHIELD_XCVR0_PRX_CA1_Q

SHIELD_XCVR0_PRX_CA2_I

SHIELD_XCVR0_PRX_CA2_Q

OUT

OUT

OUT

OUT

67

67

67

67

72

72

72

72

72

72

72

XCVR0_RF

D

WTR3925-2-TR-03-1

WLPSP

5

NC

NC

NC
NC

IN

IN

IN

IN

IN

IN

IN

50_XCVR0_DRX_DMB2_B34

50_XCVR0_DRX_DMB3_B1_B4

50_XCVR0_DRX_DMB4_B39

50_XCVR0_DRX_DMB5_B3_B25

50_XCVR0_DRX_DMLB6_B11_B21

50_XCVR0_DRX_DHB2_B7_B38_B41

50_XCVR0_DRX_DHB4_B30_B40

50_GPS_RX

10

NC

NC

NC

NC

DRX_LB1

12

DRX_LB2

4

DRX_LB3

11

DRX_LB4

15

DRX_MB1

22

DRX_MB2

7

DRX_MB3

14

DRX_MB4

6

DRX_MB5

13

DRX_MLB6

43

DRX_HB1

50

DRX_HB2

29

DRX_HB3

35

DRX_HB4

2

DNC

10

GNSS_L1

SYM 2 OF 5

DRX_GPS

DRX_CA1_BBQ

RADIO_TRANSCEIVER

DRX_CA2_BBQ

DRX_CA1_BBI

DRX_CA2_BBI

GNSS_BBI

GNSS_BBQ

GP_DATA

78

70

34

40

18

32

24

NC

SHIELD_XCVR0_DRX_CA1_I

SHIELD_XCVR0_DRX_CA1_Q

SHIELD_XCVR0_DRX_CA2_I

SHIELD_XCVR0_DRX_CA2_Q

SHIELD_GPS_RX_I

SHIELD_GPS_RX_Q

OUT

OUT

OUT

OUT

OUT

OUT

67

67

67

67

67

67

C

50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29

11

50_XCVR1_PRX_PLB2_B8_B26_B27

11

50_XCVR1_PRX_PMB1_G1800

11

50_XCVR1_PRX_PMB2_G1900

11

NC

NC

NC

NC

17
11

6

4

10

5

28
22

PRX_LB1
PRX_LB2
PRX_LB3

PRX_MB1
PRX_MB2
PRX_MB3

PRX_HB1
PRX_HB2

XCVR1_RF

WTR4905

WLNSP

SYM 3 OF 5

PRX

PRX_BBI

PRX_BBQ

15

20

SHIELD_XCVR1_PRX_I

SHIELD_XCVR1_PRX_Q

OUT

OUT

67

67

11

72

72

C

XCVR1_RF

WTR4905

WLNSP

SYM 1 OF 5

IN

IN

50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29

50_XCVR1_DRX_DLB2_B8_B26_B27

50_XCVR1_DRX_DMB2_B3

NC

NC

49
54
60

59
53

DRX_LB1
DRX_LB2
DRX_LB3

DRX_MB1
DRX_MB2

DRX_GPS

DRX_BBI

DRX_BBQ

47

36

SHIELD_XCVR1_DRX_I

SHIELD_XCVR1_DRX_Q

OUT

OUT

67

67

B

A

PP_1V8_LDO14

4

76

38
43

58

DRX_HB1
DRX_HB2

GNSS_IN

GNSS_BBI

GNSS_BBQ

46

SHIELD_XCVR0_TX_FB_RX_I

41

SHIELD_XCVR0_TX_FB_RX_Q

SYNC_MASTER=Sync

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

Apple Inc.

R

67 70

OUT

67 70

OUT

spare

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

B

A

NC

NC

NC

L6200_RF

120NH-5%-40MA

21

0201

GNSS

IN

50_GNSS

1

C6201_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

GNSS

RFIN

3

LNA_EN

7

VDD

GLNA_RF

SKY65766-13

LGA

GND

8

6

5

4

2

RFOUT

GNSS

91

50_DRX_GPS_LNA_OUT

1

C6204_RF

2.0PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

DEFAULT_RESISTOR_0.001OHM_2_1

R6201_RF

0.00

0%

1/32W

MF

01005

21

50_DRX_GPS_LNA_MATCH

1

C6205_RF

2.0PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

GPS FILTER

PLACE NEAR U_WTR

GFILT_RF

GPS-GNSS

SAFGB1G56XA0F57

LGA

UNBAL_PRT UNBAL_PRT

GND

6

5

3

2

41

50_GPS_FILTER_OUT

1

C6203_RF

1.6PF

+/-0.1PF
16V

2

NP0-C0G
01005

L6201_RF

10NH-3%-0.170A

21

01005

50_GPS_RX

10

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8 7 5 4 2 1

36

34567 8

2 1

D

C

PRIMARY & DIVERSITY RECEIVE MATCHING

80

80

80

DC BLOCKING CAP VALUES CANNOT BE MORE THAN 33PF

80

50_LAT_MLB_G1800_G1900_PA_RX

IN

RADIO_TRANSCEIVER

20NH-3%-0.25A-0.8OHM

80

IN

C6314_RF

27PF

2%

16V

CERM

01005

21

50_XCVR0_PRX_PMB5_B25_MATCH

C6305_RF

3.1NH-+/-0.1NH-0.5A-0.17OHM

21

0201

RADIO_TRANSCEIVER

IN

50_XCVR0_B25_PA_PRX

RADIO_TRANSCEIVER

OMIT_TABLE

1.6NH-+/-0.1NH-1A-0.05OHM

L6305_RF

6.2NH-3%-0.4A

IN

50_XCVR0_B11_B21_PA_PRX

0201

C6316_RF

27PF

2%

16V

CERM

01005

21

IN

50_XCVR0_B3_PRX-DSPDT_OUT

RADIO_TRANSCEIVER

21

50_XCVR0_PRX_PMLB6_B11_B21_MATCH

C6306_RF

3.0PF

+/-0.05PF

25V

C0G-CERM

RADIO_TRANSCEIVER

50_XCVR0_PRX_PMB3_B3_MATCH

0201

OMIT_TABLE

21

C6307_RF

3.0NH+/-0.1NH-0.6A

21

RADIO_TRANSCEIVER

0201

1.9NH-+/-0.1NH-0.6A-0.12OHM

L6304_RF

0201

RADIO_TRANSCEIVER

OMIT_TABLE

C6315_RF

27PF

21

2%

16V

CERM

RADIO_TRANSCEIVER

01005

L6306_RF

0201

RADIO_TRANSCEIVER

21

21

50_XCVR0_PRX_PMB5_B25

10

50_XCVR0_PRX_PMLB6_B11_B21

10

50_XCVR0_PRX_PMB3_B3

10

80

IN

50_XCVR1_B12_B13_B20_B28_B29_PA_PRX

RADIO_TRANSCEIVER

15NH-3%-0.3A-0.7OHM

50_XCVR1_B8_B26_B27_PA_PRX

RADIO_TRANSCEIVER

NOSTUFF

R6301_RF

NP0-C0G

L6312_RF

0201

L6313_RF

0201

27PF

21

5%

6.3V

0201

50_XCVR1_G1800_G1900_DIPLEX_OUT

1

OMIT_TABLE

L6320_RF

3.6NH+/-0.1NH-0.5A

0201

RADIO_TRANSCEIVER

2

21

50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29_MATCH

1

2

50_XCVR1_PRX_PLB2_B8_B26_B27_MATCH

21

1

2

1

COMMON

NOSTUFF

C6351_RF

27PF

2%
16V
CERM
01005

NOSTUFF

RADIO_TRANSCEIVER

C6352_RF

27PF

2%
16V
CERM
01005

GSMRX_RF

GSM1800-1900

B8856

OMIT_TABLE

LGA

GND

6

5

2

C6328_RF

27PF

21

2%

16V

CERM

01005

C6329_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

L6318_RF

5.1NH-3%-0.4A

0201

RADIO_TRANSCEIVER

4

GSM1800

GSM1900

50_XCVR1_G1800_DIPLEX_IN

3

50_XCVR1_G1900_DIPLEX_IN

L6319_RF

5.1NH-3%-0.4A

RADIO_TRANSCEIVER

50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29

50_XCVR1_PRX_PLB2_B8_B26_B27

0201

OMIT_TABLE

OMIT_TABLE

50_XCVR0_PRX_PMB1_G1800_MATCH

21

C6332_RF

2.0PF

+/-0.1PF

25V

C0G-CERM

0201

RADIO_TRANSCEIVER

21

50_XCVR0_PRX_PMB2_G1900_MATCH

OMIT_TABLE

21

C6333_RF

10

10

2.0PF

+/-0.1PF

16V

NP0-C0G

01005

OMIT_TABLE

21

C6340_RF

27PF

2%

16V

CERM

01005

RADIO_TRANSCEIVER

OMIT_TABLE

21

C6341_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

OMIT_TABLE

50_XCVR1_PRX_PMB1_G1800

10

50_XCVR1_PRX_PMB2_G1900

10

D

C

B

A

L6307_RF

4.3NH+/-3%-0.5A

80

80

79

IN

50_XCVR0_B4_PA_PRX

0201

RADIO_TRANSCEIVER

L6308_RF

4.3NH+/-3%-0.5A

IN

50_XCVR0_B1_B4_PA_PRX

0201

RADIO_TRANSCEIVER

L6309_RF

1.9NH-+/-0.1NH-0.6A-0.12OHM

IN

50_XCVR0_B34_B39_PA_PRX

0201

21

50_XCVR0_PRX_PMB1_B4_MATCH

C6308_RF

1.2PF

21

+/-0.1PF

25V

C0G-CERM

0201

50_XCVR0_PRX_PMB2_B1_B4_MATCH

21

C6309_RF

1.2PF

21

+/-0.1PF

25V

C0G-CERM

0201

50_XCVR0_PRX_PMB4_B34_B39_MATCH

21

C6301_RF

RADIO_TRANSCEIVER

3.3NH+/-0.1NH-0.5A

21

0201

80

79

C6318_RF

27PF

2%

16V

CERM

01005

21

50_XCVR0_PRX_PHB1_B7_MATCH

IN

50_XCVR0_B7_PA_PRX

RADIO_TRANSCEIVER

C6310_RF

IN

50_XCVR0_B38_B40_B41_PA_PRX

0.00

1%

1/20W

MF

0201

21

50_XCVR0_PRX_PHB3_B38_B40_B41_MATCH

RADIO_TRANSCEIVER

C6302_RF

1.0PF

21

+/-0.1PF

25V
C0G
201

RADIO_TRANSCEIVER

L6301_RF

2.5NH+/-0.1NH-0.6A

21

0201

RADIO_TRANSCEIVER

3.9NH+/-0.1NH-0.5A

L6311_RF

80

50_XCVR0_B30_PA_PRX

RADIO_TRANSCEIVER

C6345_RF

27PF

80

IN

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

50_XCVR0_B11_B21_PA_DRX

2%

16V

CERM

01005

RADIO_TRANSCEIVER

OMIT_TABLE

0.00

1/20W

21

50_XCVR0_DRX_DMLB6_B11_B21_MATCH

1%

MF

0201

21

50_XCVR_PRX_PHB4_B30_MATCH

C6311_RF

2.1NH-+/-0.1NH-0.6A-0.12OHM

0201

RADIO_TRANSCEIVER

C6348_RF

3.0PF

+/-0.05PF

C0G-CERM

RADIO_TRANSCEIVER

OMIT_TABLE

21

25V

0201

21

RADIO_TRANSCEIVER

L6322_RF

6.2NH-3%-0.4A

21

0201

OMIT_TABLE

C6342_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

C6343_RF

27PF

21

2%

16V

CERM

01005

C6317_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

L6310_RF

21

0201

C6319_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

C6320_RF

27PF

21

2%

16V

CERM

01005

50_XCVR0_DRX_DMLB6_B11_B21

50_XCVR0_PRX_PMB1_B4

50_XCVR0_PRX_PMB2_B1_B4

50_XCVR0_PRX_PMB4_B34_B39

50_XCVR0_PRX_PHB1_B7

50_XCVR0_PRX_PHB3_B38_B40_B41

50_XCVR0_PRX_PHB4_B30

74

IN

10

80

IN

50_XCVR0_B40_PA_PRX_EXT_FIL

SHUNT COMPONENT WITH BAND 40 FILTER

10

10

DC BLOCKING CAP VALUES CANNOT BE MORE THAN 33PF

10

10

74

IN

50_XCVR0_B34_MBHB-DRX-ASM_OUT

C6323_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

C6324_RF

27PF

2%

16V

CERM

01005

21

10

74

IN

50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT

RADIO_TRANSCEIVER

C6325_RF

27PF

10

74

IN

50_XCVR0_B39_MBHB-DRX-ASM_OUT

L6323_RF

RADIO_TRANSCEIVER

2%

16V

CERM

01005

21

2.4NH+/-0.1NH-0.6A

50_XCVR0_B3_B25_DRX-DSPDT_OUT 50_XCVR0_DRX_DMB5_B3_B25_MATCH

0201

RADIO_TRANSCEIVER

21

C6349_RF

3.2NH+/-0.1NH-0.5A

21

0201

L6321_RF

4.3NH+/-3%-0.5A

21

0201

RADIO_TRANSCEIVER

50_XCVR0_PRX_PHB2_B40_EXT_MATCH

RADIO_TRANSCEIVER

RADIO_TRANSCEIVER

74

50_XCVR0_DRX_DMB2_B34

50_XCVR0_DRX_DMB3_B1_B4

50_XCVR0_DRX_DMB4_B39

10

10

10

C6344_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

C6346_RF

27PF

21

2%

16V

CERM

01005

50_XCVR0_DRX_DMB5_B3_B25

L6328_RF

3.0NH+/-0.1NH-0.6A

IN

50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT

C6350_RF

0201

2.2PF

25V

+/-0.1PF

21

C0G-CERM

0201

RADIO_TRANSCEIVER

74

IN

50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT

21

50_XCVR0_DRX_DHB2_B7_B38_B41_MATCH

C6335_RF

27PF

2%

16V

CERM

RADIO_TRANSCEIVER

01005

21

C6334_RF

27PF

21

2%

16V

CERM

01005

RADIO_TRANSCEIVER

50_XCVR0_DRX_DHB4_B30_B40

50_XCVR0_DRX_DHB2_B7_B38_B41

10

10

C6336_RF

74

27PF

2%

16V

CERM

01005

21

IN

50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT

RADIO_TRANSCEIVER

50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29

10

B

C6337_RF

74

IN

10

74

IN

50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT

RADIO_TRANSCEIVER

L6324_RF

2.4NH+/-0.1NH-0.6A

50_XCVR1_B3_DRX-DSPDT_OUT 50_XCVR1_DRX_DMB2_B3_MATCH

0201

RADIO_TRANSCEIVER

21

L6325_RF

3.2NH+/-0.1NH-0.5A

21

0201

RADIO_TRANSCEIVER

SYNC_MASTER=Sync

PAGE TITLE

27PF

21

2%

16V

CERM

01005

C6338_RF

NP0-C0G

27PF

5%

6.3V

0201

50_XCVR1_DRX_DLB2_B8_B26_B27

21

50_XCVR1_DRX_DMB2_B3

10

10

SYNC_DATE=05/17/2016

A

spare

DRAWING NUMBER SIZE

50_XCVR0_PRX_PHB2_B40_EXT

10

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36

D

80

80

34567 8

2 1

LOWER ANTENNA AND COUPLER

JLAT1_RF

MM7829-2700

14 13 12 4

PP_2V7_LDO12

R6402_RF

1.3NH+/-0.1NH-1.1A

1

C6407_RF

18PF
2%
16V

2

CERM

2
14

4
16

01005

NCNC

50_XCVR0_LAT_CPLD

50_XCVR1_LAT_CPLD

9

VDD

LATDI_RF

LFD21829MMY1E339

BI

BI

50_LAT_LB_COMBINER_IN

50_LAT_MB_HB_COMBINER_IN

6
4

LB
MB-HB

0805-LGA

GND

5

3

1

ANT

2

50_LAT_LB_MB_HB_COMBINER_OUT 50_LAT_LB_MB_HB_CPL_ANT

1

2

R6401_RF

2NH+/-0.1NH-0.6A

21

0201

C6403_RF

18PF

2%
25V
C0H-CERM
0201

NOSTUFF

1

C6402_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

LATCP_RF

50_LAT_LB_MB_HB_CPL_IN

FL6402_RF

10-OHM-1.1A

65 68 73 74 75 77 79 80

IN

68 73 80

BI

68 73 80

IN

PP_1V8_LDO15

75_RFFE7_SDATA

75_RFFE7_SCLK

01005

21

PP_1V8_LDO15_LATCP

1

13

6

5

12

8

RFIN1
RFIN2

USID

VIO
SDATA
SCLK

SKY16705-21

LGA

RFOUT1
RFOUT2

RF_CPL1
RF_CPL2

1

C6409_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

12

12

1

C6410_RF

18PF
2%
25V

2

C0H-CERM
0201

NOSTUFF

0201

21

1

C6411_RF

0.7PF

+/-0.05PF
25V

2

C0G-CERM
0201

NOSTUFF

50_LAT1_ANT

F-ST-SM

2

D

1

3

C

70

70

OUT

OUT

50_XCVR0_TX_FBRX_IN

50_XCVR1_TX_FBRX_IN

14 13 12 4

FBRX-DSPDT_CTL1

17 7

FBRX-DSPDT_CTL2

17 7

PP_2V7_LDO12

1

2

C6414_RF

18PF

2%
16V
CERM
01005

1

C6419_RF

2

8

VDD

SWLATCP_RF

CXA4439GC-E

RF1 RF1A

10 4

RF2 RF1B

7

VCTL1

9

VCTL2

LGA-1

RF2A
RF2B

GND

3

18PF

2%
16V
CERM
01005

56

2

1

1

C6420_RF

18PF

2%
16V

2

CERM
01005

50_XCVR0_LAT_CPLD

50_XCVR0_UAT_CPLD

50_XCVR1_UAT_CPLD

50_XCVR1_LAT_CPLD

1

C6401_RF

0.033UF
20%
4V

2

X5R-CERM
01005

12

12

12

12

GND

7

3

10

11

15

USID=0X6

C

B

80

80

UPPER ANTENNA COUPLER

14 13 12 4

UATDI_RF

LFD21829MMY1E339

50_UAT_LB_COMBINER_IN

BI

50_UAT_MLB_COMBINER_IN

6
4

LB
MB-HB

0805-LGA

OMIT_TABLE

GND

5

3

1

ANT

2

50_UAT_LB_MLB_COMBINE

1

C6405_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

R6400_RF

0.00

1/20W

0201

21

1%

MF

1

C6404_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

50_UAT_LB_MLB_CPL_IN

50_UAT_MB_HB_CPL_IN

19

FL6401_RF

10-OHM-1.1A

65 68 73 74 75 77

IN

79 80

68 73 80

BI

68 73 80

IN

PP_1V8_LDO15

75_RFFE7_SDATA

75_RFFE7_SCLK

1

C6400_RF

0.033UF
20%
4V

2

X5R-CERM
01005

01005

21

PP_1V8_LDO15_UATCP

PP_2V7_LDO12

1

RFIN1

13

RFIN2

6

USID

5

VIO

12

SDATA

8

SCLK

9

VDD

UATCP_RF

SKY16705-21

LGA

GND

7

3

10

RFOUT1
RFOUT2

RF_CPL1
RF_CPL2

15

11

1

C6406_RF

18PF
2%
16V

2

CERM
01005

2
14

4
16

50_UAT_LB_MLB_CPL_OUT

50_UAT_MB_HB_CPL_ANT

50_XCVR0_UAT_CPLD

50_XCVR1_UAT_CPLD

1

C6408_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

12

12

1

C6417_RF

18PF
2%
25V

2

C0H-CERM
0201

NOSTUFF

1.3NH+/-0.1NH-1.1A

1

C6415_RF

18PF

2%

25V

2

C0H-CERM
0201

NOSTUFF

USID=0X7

R6405_RF

0.00

1%

1/20W

MF

0201

R6404_RF

0201

OMIT_TABLE

21

1

2

50_UAT_LB_MLB_SOUTH

C6418_RF

18PF

5%
16V
CERM
01005

NOSTUFF

OUT

53 62

B

21

1

2

50_UAT_MB_HB_SOUTH

C6416_RF

0.3PF

+/-0.1PF
25V
C0G-CERM
201

OMIT_TABLE

OUT

53 62

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

DIVERSITY RECEIVE

LB DRX ASM

34567 8

2 1

D

14 13 12 4

PP_2V7_LDO12

11

11

1

C6501_RF

20%

6.3V

2

X5R-CERM
01005

50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT

50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT

65 68 73 74 75 77 79 80

IN

68 74 78

BI

68 74 78

IN

PP_1V8_LDO15

75_RFFE3_SDATA

75_RFFE3_SCLK

1

C6514_RF

18PF

2%
16V

2

CERM
01005

1

2

1

C6503_RF

0.033UF
20%
4V

2

X5R-CERM
01005

C6505_RF

18PF0.1UF
2%
16V
CERM
01005

2

12

NC

3

11

5
7
6

VLB_RX0
VLB_RX1
LB_RX0
LB_RX1

VIO
SDATA
SCLK

4

1

9

VDD

LBDSM_RF

HFQSWEWUA

LGA

8

10

13

14

15

16

ANT

EPADGND

21

20

19

18

17

USID=0X9

R6501_RF

3.9NH+/-0.1NH-0.5A

50_LAT-UAT_LB-DRX-ASM_ANT 50_LB_DRX

1

C6507_RF

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

NOSTUFF

0201

21

1

C6510_RF

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

NOSTUFF

D

80

IN

C

B

14 13 12 4

50_XCVR1_B3_DRX-DSPDT_OUT

11

50_XCVR0_B3_B25_DRX-DSPDT_OUT

11

PP_2V7_LDO12

1

2

C6504_RF

18PF

2%
16V
CERM
01005

SWDSM_RF

CXA4430GC-E

4

RF1

6

RF2

3

VDD

LGA

GND

5

RFIN

CTRL

C

MB HB DRX ASM

14 13 12 4

18PF
2%
16V
CERM
01005

11

17 7

2

1

RX-DSPDT_CTL2

1

C6513_RF

2

PP_2V7_LDO12

50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT

65 68 73 74 75 77 79 80

68 74 78

68 74 78

1

C6502_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

50_XCVR0-1_B3_B25_MBHB-DRX-ASM_OUT

50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT

11

50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT

11

50_XCVR0_B34_MBHB-DRX-ASM_OUT

11

11

IN

BI

IN

PP_1V8_LDO15

75_RFFE3_SDATA

75_RFFE3_SCLK

1

C6515_RF

18PF

2%
16V

2

CERM
01005

1

C6506_RF

18PF

2%
16V

2

CERM
01005

2

B3_B25_RX

3

B1_B4_RX

15

B30_B40_RX

16

B7_B38/B41B_B41_RX

13

B34_RX

14

B39_RX

22

MIPI_VIO

20

MIPI_SDATA

21

MIPI_SCLK

4

1

18

MIPI_VDD

MHBDSM_RF

D5315

LGA

R6502_RF

ANT1

ANT2

THRM_PADGND

9

7

6

5

11

12

17

19

23

24

25

26

10

8

USID=0XA

50_LAT_MB-HB-DRX-ASM_ANT150_XCVR0_B39_MBHB-DRX-ASM_OUT

1

C6508_RF

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

NOSTUFF

50_UAT_MB-HB-DRX-ASM_ANT2

1

C6509_RF

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

NOSTUFF

0

21

5%

1/20W

MF

201

R6503_RF

0

21

5%

1/20W

MF

201

50_LAT_MB_HB_DRX

1

C6511_RF

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

NOSTUFF

50_UAT_MB-HB-DRX-LNA_OUT_RX

1

C6512_RF

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

NOSTUFF

80

IN

B

75

IN

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=04/17/2015

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

D

DIVERSITY RECEIVE LNAS

PP_MHBLN_RF

14

34567 8

LB DRX LNA

10

VDD

2 1

D

C

53

R6601_RF

0.00

1%

MF

0201

21

1

C6602_RF

18PF
2%
25V

2

C0H-CERM
0201

NOSTUFF

50_UUAT_LB_MLB_NORTH 50_UAT_LB_MLB_SPLIT_IN

BI

1

C6601_RF

18PF

2

NOSTUFF

1/20W

2%
25V
C0H-CERM
0201

UPPDI_RF

LFD21829MMP5E222

2

ANT

LGA

OMIT_TABLE

GND

5

3

1

LB

MB-HB

50_UAT_LB-DRX-LNA_TX_RX 50_UAT_LB-DRX-LNA_ANT

14 15

3

TX_RX

LBLN_RF

ANT

14

SKY13702-17

LGA

65 68 73 74 75 77 79 80

BB_TO_UAT_DATA-53[I16] 62 68 75

BI

BB_TO_UAT_SCLK-53[I16] 62 68 75

IN

PP_1V8_LDO15

BB_TO_UAT_DATA

BB_TO_UAT_SCLK

1

C6617_RF

18PF

2%
16V

2

CERM
01005

1

C6619_RF

18PF

2%
16V

2

CERM
01005

9

7
8

1

C6620_RF

0.033UF
20%
4V

2

X5R-CERM
01005

VIO
SDATA
SCLK

1

GND EPAD

6

5

4

2

11

12

13

15

16

17

18

19

20

21

22

23

24

25

USID=0X2

MB/HB DRX LNA

R6606_RF

0.00

50_UAT_LB_SPLIT_OUT

1/20W

1

C6611_RF

4
6

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

21

1%

MF

0201

OMIT_TABLE

50_UAT_LB-DRX-LNA_TX_RX

1

C6614_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

14

14 13 12 4

150OHM-25%-200MA-0.7DCR

PP_2V7_LDO12

R6605_RF

2.7NH+/-0.1NH-0.6A

50_UAT_MLB_SPLIT_OUT

0201

OMIT_TABLE

1

C6610_RF

1.5PF

+/-0.05PF
25V

2

C0G-CERM
0201

OMIT_TABLE

21

50_UAT_MLB-DRX-LNA_TX_RX

1

14

C6613_RF

10NH-3%-250MA

0201

OMIT_TABLE

2

75

65 68 73 74 75 77 79 80

BB_TO_UAT_DATA-53[I16] 62 68 75

BB_TO_UAT_SCLK-53[I16] 62 68

FL6602_RF

21

01005

50_UAT1_WEST

1 15

50_UAT_MB-HB-DRX-LNA_OUT_RX

13

IN

BI

IN

PP_1V8_LDO15

BB_TO_UAT_DATA

BB_TO_UAT_SCLK

1

C6629_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

1

C6625_RF

18PF

2%
16V

2

CERM
01005

4
2

21
23
22

IN_TX
OUT_RX

VIO
SDATA
SCLK

3

1

6

5

PP_MHBLN_RF

14

9

8

7

20

VDD

MHBLN_RF

SKY13703-19

LGA

GND

14

13

12

11

10

15

17

18

19

24

25

EPAD

27

26

ANT

28

16

50_UAT_MB-HB-DRX-LNA_ANT

C

B

14 13 12 4

PP_2V7_LDO12

USID=0X3

MLB DRX LNA

FL6603_RF

150OHM-25%-200MA-0.7DCR

21

01005

14 15

50_UAT_MLB-DRX-LNA_TX_RX

1

C6627_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

1

C6622_RF

18PF

2%
16V

2

CERM
01005

6

OUT_RX

PP_MLBLN_RF

MLBLN_RF

LMRX2HJB-H68

OMIT_TABLE

1

VDD

LGA

ANT

13

50_UUAT_MLB

B

A

65 68 73 74 75 77 79 80

IN

BB_TO_UAT_DATA-53[I16] 62 68 75

BI

BB_TO_UAT_SCLK-53[I16] 62 68 75

IN

PP_1V8_LDO15

BB_TO_UAT_DATA

BB_TO_UAT_SCLK

2
4
3

VIO
SDATA
SCLK

5

GND

9

8

7

10

11

12

14

EPAD

16

15

USID=0X4

A

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

D

8 7 5 4 2 1

36

UPPER ANTENNA FEEDS

34567 8

2 1

D

C

75

75

75

D

OMIT_TABLE

R6708_RF

BI

BI

BI

53 62

50_UAT_LB-DRX-LNA_ANT

50_UAT_MB-HB-DRX-LNA_ANT 50_UUAT_HB_PLEXER

BI

0.00

1/20W

0201

UP_RFFE

OMIT_TABLE

R6710_RF

OMIT_TABLE

R6703_RF

21

1%

MF

0.00

1%

1/20W

MF

0201

UP_RFFE

0.00

1%

1/20W

MF

0201

UP_RFFE

50_UUAT_LB_PLEXER

1

C6726_RF

18PF

2%
25V

2

C0H-CERM
0201

UP_RFFE
NOSTUFF

21

21

50_UUAT_MLB_PLEXER50_UUAT_MLB

1

C6728_RF

18PF

2%
25V

2

C0H-CERM
0201

UP_RFFE
NOSTUFF

1

C6711_RF

18PF

2%
25V

2

C0H-CERM
0201

UP_RFFE
NOSTUFF

50_UAT_WLAN_2G_WEST_PLEXER

10

14

17

8

1

LB
MLB
MB-HB
WIFI
GNSS

2

PPLXR_RF

ACFM-W312-AP1

LGA

OMIT_TABLE

GND

9

7

6

4

3

11

12

13

15

16

18

UAT1

5

ANT

EPAD

19

50_UAT1

R6705_RF

0.00

1%

1/20W

MF

0201

UP_RFFE

21

50_UAT1_MATCH

1

2

C6713_RF

18PF

2%
25V
C0H-CERM
0201

NOSTUFF

R6715_RF

0.00

1%

1/20W

MF

0201

UP_RFFE

21

50_UAT1_TEST

JUAT1_RF

MM8830-2600B

F-RT-SM

C R

GND

3

1

L6700_RF

56NH-100MA-3.9OHM

0201

UP_RFFE
NOSTUFF

2

UP_RFFE

50_UAT1_TUNER

TO ANTENNA TUNER

21

53 62

BI

C

B

71

50_GNSS

R6709_RF

0.00

1%

1/20W

MF

0201

UP_RFFE

21

50_GNSS_PLEXER

1

C6727_RF

18PF

2%
25V

2

C0H-CERM
0201

UP_RFFE
NOSTUFF

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

PMU: ET MODULATOR

34567 8

2 1

D

D

C

67

67

SHIELD_ET_DAC_P

IN

SHIELD_ET_DAC_N

IN

75_RFFE2_SCLK

17 7

75_RFFE2_SDATA

17 7

PP_VPA_APT

18

PP_QPOET_VCC_PA

19 18

PP_PA_VBATT

19 18

17
16

2
3

AMP_IN+

AMP_IN-

SCLK
SDATA

PP_1V8_LDO15

13

12

25

24

21

20

10

5

PA_VBATT

VCC_PA_ET

7

6

VCC_PA_ET

VCC_PA_GSM

2103-601507-10

GND

4

11

18

27

28

29

30

15

8

VDD_1P8

VCC_PA_GSM

VDD_BUCK

VDD_BUCK

QPOET_RF

LGA

9

1

32

31

14

22

VDD_LDO

VDD_LDO

VDD_VBATT

VDD_VBATT

TRIM_14
TRIM_18

USID_LSB

65 68 73 74 75 79 80

IN

1

C6801_RF

2.2UF

20%

6.3V

2

X5R-CERM

26
23

NC

19

1

C6802_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-10201-1

1

C6803_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

1

C6804_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

PP_VDD_MAIN

1

C6805_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

C

53 62 64 65 77 81

B

DESENSE CAPS

53 62 64 65 77 81

IN

PP_VDD_MAIN

1

2

PLACE C6806 AND C6807 NEAR THE QPOET

C6806_RF

100PF

5%
16V
NP0-C0G
01005

1

C6807_RF

27PF

2%
16V

2

CERM
01005

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8 7 5 4 2 1

36

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

MLB TEST POINTS

BBPMU

34567 8

2 1

BOOT CONFIG

DEFAULT FAST_BOOT[2:0]

D

C

B

BASEBAND

PP7000_RF

P2MM-NSM

SM

1

PP

OMIT

PP6952_RF

P2MM-NSM

SM

PP

OMIT

PP6943_RF

P2MM-NSM

SM

PP

OMIT

PP6944_RF

P2MM-NSM

SM

PP

OMIT

PP6939_RF

P2MM-NSM

SM

PP

OMIT

PP6940_RF

P2MM-NSM

SM

PP

OMIT

PP6941_RF

P2MM-NSM

SM

PP

OMIT

PP6942_RF

P2MM-NSM

SM

PP

OMIT

PP6903_RF

P2MM-NSM

SM

PP

OMIT

PP6904_RF

P2MM-NSM

SM

PP

OMIT

PP6935_RF

P2MM-NSM

SM

PP

OMIT

PP6936_RF

P2MM-NSM

SM

PP

OMIT

PP6915_RF

P2MM-NSM

SM

PP

OMIT

PP6916_RF

P2MM-NSM

SM

PP

OMIT

75_RFFE1_SDATA

1

75_RFFE1_SCLK

1

75_RFFE2_SDATA

1

75_RFFE2_SCLK

1

75_RFFE3_SDATA

1

75_RFFE3_SCLK

1

75_RFFE4_SDATA

1

75_RFFE4_SCLK

1

BB_TO_LAT_ANT_DATA

1

BB_TO_LAT_ANT_SCLK

1

75_RFFE6_SCLK

1

75_RFFE6_SDATA

PCIE

1

90_PCIE_AP_TO_BB_REFCLK_P

1

90_PCIE_AP_TO_BB_REFCLK_N

9 7

9 7

16 7

16 7

13 7

13 7

9 7

9 7

1 7

1 7

1 6

1 6

USB = 0X2

PP6945_RF

PP6906_RF

P2MM-NSM

SM

1

PP

OMIT

PP6907_RF

P2MM-NSM

SM

PP

OMIT

PP6908_RF

P2MM-NSM

SM

PP

OMIT

PP6909_RF

P2MM-NSM

SM

PP

OMIT

PP6911_RF

P2MM-NSM

SM

PP

OMIT

SWD_AP_TO_BB_CLK_BUFFER

1

PMU_TO_BB_USB_VBUS_DETECT

1

NFC_TO_BB_CLK_REQ

1

SIM1_REMOVAL_ALARM

1

50_MDM_PCIE_CLK

6

1 3 20

1 3

7 3

6 3

PP6919_RF

P2MM-NSM

SM

1

PP

BB_JTAG_RST_L

OMIT

PP6920_RF

P2MM-NSM

SM

1

PP

FBRX-DSPDT_CTL1

OMIT

PP6921_RF

P2MM-NSM

SM

1

PP

FBRX-DSPDT_CTL2

OMIT

PP6923_RF

P2MM-NSM

SM

1

PP

BB_TO_PMU_PCIE_HOST_WAKE_L

OMIT

PP6924_RF

P2MM-NSM

SM

1

PP

SPMI_CLK

OMIT

PP6925_RF

P2MM-NSM

SM

1

PP

SPMI_DATA

20 6

12 7

12 7

1 7

6 3

6 3

OMIT

PP6912_RF

P2MM-NSM

SM

1

PP

XO_OUT_D0_EN

OMIT

PP6913_RF

P2MM-NSM

SM

1

PP

BB_TO_NFC_CLK

6 3

3 1

PP6926_RF

P2MM-NSM

SM

1

PP

UART_BB_TO_AOP_RXD

OMIT

7 1

OMIT

PP6914_RF

P2MM-NSM

SM

1

PP

SHIELD_SLEEP_CLK_32K

6 3

OMIT

PP6933_RF

P2MM-NSM

SM

1

PP

BB_TO_STROBE_DRIVER_GSM_BURST_IND

1 7

OMIT

19 18 7

PP6917_RF

P2MM-NSM

SM

1

PP

UART_BB_TO_WLAN_COEX

20 7 1

PP6929_RF

P2MM-NSM

SM

1

PP

AP_TO_BB_TIME_MARK

OMIT

PP6930_RF

P2MM-NSM

SM

1

PP

OMIT

PP6931_RF

P2MM-NSM

SM

1

PP

OMIT

BB_TO_AP_RESET_DETECT_L

AP_TO_BB_COREDUMP

7 1

7 1

1 7

OMIT

19 18 7

PP6918_RF

P2MM-NSM

SM

1

PP

OMIT

UART_WLAN_TO_BB_COEX

20 7 1

PP6938_RF

P2MM-NSM

SM

1

PP

RX-DSPDT_CTL2

13 7

OMIT

P2MM-NSM

SM

1

PP

PMIC_RESOUT_L

OMIT

PP6905_RF

P2MM-NSM

SM

1

PP

AP_TO_BBPMU_RADIO_ON_L

OMIT

PP6900_RF

P2MM-NSM

SM

1

PP

PMU_TO_BBPMU_RESET_L

OMIT

SIM

PP6953_RF

P2MM-NSM

SM

1

PP

OMIT

PP6969_RF

P2MM-NSM

SM

1

PP

OMIT

PP6972_RF

P2MM-NSM

SM

1

PP

OMIT

PP6973_RF

P2MM-NSM

SM

1

PP

OMIT

PP6974_RF

P2MM-NSM

SM

1

PP

OMIT

PP6977_RF

P2MM-NSM

SM

1

PP

OMIT

SIM1_IO

SIM1_DETECT

SIM1_RST

SIM1_CLK

90_USB_BB_DATA_P

90_USB_BB_DATA_N

6 3

20 3 1

3 1

1 6 20

1 6 20

20 7 6 5 4

PP_1V8_LDO6

D

NOSTUFF

1

R6921_RF

10K

1%
1/32W

MF

01005

RADIO_DEBUG

2

FAST_BOOT_SELECT1

7

FAST_BOOT_SELECT0

7

20 7

1

R6922_RF

10K

1%

1/32W

MF

01005

RADIO_DEBUG

2

C

20 7

20 7

20 7

ICEFALL

PP6978_RF

P2MM-NSM

SM

1

PP

AP_TO_ICEFALL_FW_DWLD_REQ

OMIT

PP6979_RF

P2MM-NSM

SM

1

PP

SIM1_SWP

OMIT

PP6980_RF

P2MM-NSM

SM

1

PP

SE2_SWP

OMIT

PP6981_RF

P2MM-NSM

SM

1

PP

ICEFALL_LDO_ENABLE

OMIT

1 20

20

20

PP7500_RF

P2MM-NSM

OMIT

PP7501_RF

P2MM-NSM

OMIT

PP7502_RF

P2MM-NSM

SM

PP

OMIT

20 1

SM

1

PP

SM

1

PP

1

SE2_PWR_REQ

SE2_READY

NFC_SWP_MUX

20 1

B

20 1

20 1

A

PCIE GND

PP6970_RF

P2MM-NSM

SM

1

OMIT

8 7 5 4 2 1

PP6971_RF

P2MM-NSM

SM

1

PPPP

OMIT

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

TDD TRANSMIT

34567 8

2 1

D

C

2G PA

FL7001_RF

600-OHM-25%-0.1A

19 16 16

PP_PA_VBATT

0201-1

21

1

C7004_RF

1.0UF

20%

6.3V

2

X5R
0201-1

2GPA_VBATT

1

C7005_RF

27PF

5%
16V

2

NP0-C0G
01005

1

C7006_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

3

8

VCCVBATT

1

C7007_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

1

C7008_RF

18PF
2%
16V

2

CERM
01005

GSMPA_RF

50_TX_G850_G900_PA_OUT

17

612

50_TX_G1800_G1900_PA_OUT

1

2

1

2

C7009_RF

18PF

2%
25V
C0H-CERM
0201

NOSTUFF

C7010_RF

18PF

2%
25V
C0H-CERM
0201

NOSTUFF

70

70

65 68 73 74 75 77 79 80

68 78 79 80

68 78 79 80

50_XCVR1_TX_G850_G900_PA_IN

IN

50_XCVR1_TX_G1800_G1900_PA_IN

IN

PP_1V8_LDO15

IN

BI

75_RFFE6_SDATA

75_RFFE6_SCLK

IN

1

2

C7017_RF

27PF

5%
16V
NP0-C0G
01005

SKY77363

LGA

11

9

10

LBRFIN

HBRFIN

VIO
SDATA
SCLK

2

GND

4

LBRFOUT

HBRFOUT

5

USID=0X5

EPAD

13

PP_VPA_APT

1

C7001_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

C7011_RF

27PF

5%

6.3V

NP0-C0G

0201

C7012_RF

27PF

5%

6.3V

NP0-C0G

0201

50_TX_G850_G900_PA_OUT_M

21

1

C7013_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

50_TX_G1800_G1900_PA_OUT_M

21

1

C7014_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

OUT

OUT

80

80

MB HB TDD PA

PP_1V8_LDO15

75_RFFE6_SDATA

65 68 73 74 75 77 79 80

IN

68 78 79 80

BI

D

C

B

70

70

19 16

PP_QPOET_VCC_PA

MF0%

21

75_RFFE6_SCLK

IN

68 78 79 80

1

C7016_RF

5.6PF

+/-0.1PF
16V

2

NP0-C0G
01005

R7002_RF

MLB_PA_VBATT

19

11

VBATT

IN

IN

50_XCVR0_TX_B34_B39_PA_IN

50_XCVR0_TX_B38_B40_B41_PA_IN

3

RFIN_MB

5

RFIN_HB

01005

0.00

1/32W

TDD_PAD_VCC1

9

8

VCC1

VCC2

TDDPA_RF

AFEM-8065-AP1

LGA-1

14

VIO

12

SDATA

13

SCLK

ANT

1

C7015_RF

5.6PF

+/-0.1PF
16V

2

NP0-C0G
01005

16

50_TDD_PA_ANT_M

OUT

B

80

A

72

72

OUT

OUT

50_XCVR0_B38_B40_B41_PA_PRX

50_XCVR0_B34_B39_PA_PRX

27

RX_B38_B40_B41

25

RX_B34_B39

2

1

GND

7

6

4

10

15

17

19

21

22

24

26

28

23

20

18

29

30

31

32

33

THRM_PAD

36

35

34

37

38

39

40

41

42

43

USID=0XF

A

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

D

8 7 5 4 2 1

36

34567 8

2 1

D

C

FDD TRANSMIT

PP_QPOET_VCC_PA

DEFAULT_RESISTOR_0.001OHM_2_1

R7107_RF

PP_PA_VBATT

50_XCVR1_TX_B8_B20_B26_B27_PA_IN

50_XCVR1_TX_B12_B13_B28_PA_IN

50_TX_G850_G900_PA_OUT_M

50_LB_DRX

50_XCVR1_B8_B26_B27_PA_PRX

50_XCVR1_B12_B13_B20_B28_B29_PA_PRX

0.00

1/32W

01005

21

0%

MF

DEFAULT_CAPACITOR_1e+06pF_2_1

LB_PA_VBATT

1

C7103_RF

1.0UF

20%

6.3V

2

X5R
0201-1

18

12

26

25

NC

24

23

NC

2

RFIN0

3

RFIN1

2G_TX

LB_DIV

LB_RX0

LB_RX1

VLB_RX0

VLB_RX1

1

C7104_RF

18PF

2%
16V

2

CERM
01005

6

5

4

1

11

13

LB_PAD_VCC1

7

VBATT

17

15

79

74

72

72

70

70

19 18 16

19 18 16

IN

IN

IN

OUT

OUT

OUT

DEFAULT_RESISTOR_0.001OHM_2_1

1

R7108_RF

0.00

0%
1/32W
MF
01005

2

40

41

VCC1

VCC2

1

C7105_RF

18PF

2%
16V

2

CERM
01005

LBPA_RF

SKY78100-14

LB PA

GND

32

31

30

29

28

27

22

21

20

19

33

LGA1

34

NOSTUFF

1

R7130_RF

1.00

1%
1/32W
MF
01005

2

LB_SNUBBER

1

C7130_RF

68PF

2%

6.3V

2

NP0-C0G
01005

NOSTUFF

42

39

38

37

36

35

USID=0XD

43

44

10

VIO

45

8

SDATA

46

47

PP_1V8_LDO15_PA

75_RFFE7_SDATA_PA

75_RFFE7_SCLK_PA

9

SCLK

THRM_PAD

53

52

51

50

49

48

54

55

57

56

19 18 16

ANT1

ANT2

19 18 16

1

C7126_RF

33PF

5%
16V

2

NP0-C0G-CERM
01005

NOSTUFF

50_LAT_LB_PA_ANT

16

14

50_UAT_LB_PA_ANT

PP_QPOET_VCC_PA

PP_PA_VBATT

1

C7127_RF

0.033UF
20%
4V

2

X5R-CERM
01005

1

C7101_RF

180PF

10%
10V

2

CERM
01005

NOSTUFF

R7101_RF

1

C7111_RF

22NH-3%-0.25A

0201

2

1

C7112_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

DEFAULT_RESISTOR_0.001OHM_2_1

R7113_RF

0.00

1/32W

01005

0%

MF

21

1

C7113_RF

1.0UF

20%

6.3V

2

X5R
0201-1

R7111_RF

0.00

1/32W

MF

01005

18PF

21

2%

25V

C0H-CERM

0201

R7102_RF

0.00

21

1%

1/20W

MF

0201

18

MLB_PA_VBATT

21

0%

1

C7114_RF

18PF

2%
16V

2

CERM
01005

R7112_RF

0.00

0%

1/32W

MF

01005

1

C7120_RF

1.0PF

+/-0.1PF
25V

2

C0G
201

OMIT_TABLE

1

C7121_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

R7114_RF

10-OHM-1.1A

21

01005

21

1

C7128_RF

33PF

5%
16V

2

NP0-C0G-CERM
01005

NOSTUFF NOSTUFF

50_LAT_LB_COMBINER_IN

50_UAT_LB_COMBINER_IN

1

C7129_RF

0.033UF
20%
4V

2

X5R-CERM
01005

1

2

BI

BI

C7117_RF

18PF

2%
16V
CERM
01005

PP_1V8_LDO15

75_RFFE7_SDATA

75_RFFE7_SCLK

1

C7133_RF

0.033UF
20%
4V

2

X5R-CERM
01005

73

824-915

824-915

73

NOSTUFF

1

R7131_RF

1.00

1%
1/32W
MF
01005

2

MLB_TDD_SNUBBER

1

C7131_RF

68PF

2%

6.3V

2

NP0-C0G
01005

NOSTUFF

IN

BI

IN

PP_1V8_LDO15

75_RFFE6_SDATA

75_RFFE6_SCLK

65 68 73 74 75 77 79 80

68 73

68 73

65 68 73 74 75 77 79 80

IN

68 78 79 80

BI

68 78 79 80

IN

D

C

B

RXFIL_RF

BAW-B40F-RX

QM21140

LGA

50_XCVR0_B40B_PA_PRX 50_XCVR0_B40_PA_PRX_EXT_FIL

19

1

L7122_RF

4.7NH-3%-0.270A

01005

2

1 4

B40RXOUT

GND

6

5

3

2

B40ANT

19 18 16

19 18 16

1

L7123_RF

1.0PF

+/-0.1PF
16V

2

NP0-C0G
01005

PP_QPOET_VCC_PA

PP_PA_VBATT

DEFAULT_RESISTOR_0.001OHM_2_1

R7109_RF

0.00

1/32W

01005

0%

MF

25

VBATT

28

VCC1

27

VCC2

22

VIO

24

SDATA

23

SCLK

MLBPA_RF

50_XCVR0_TX_B11_B21_PA_IN

50_XCVR0_B11_B21_PA_PRX

50_XCVR0_B11_B21_PA_DRX

OUT

72

72

72

70

IN

OUT

OUT

NOSTUFF

1

R7132_RF

1.00

1%
1/32W
MF
01005

2

MBHB_SNUBBER

1

21

MBHB_FDD_PA_VBATT

DEFAULT_CAPACITOR_1e+06pF_2_1

1

C7106_RF

1.0UF

20%

6.3V

2

X5R
0201-1

1

C7108_RF

18PF

2%
16V

2

CERM
01005

29

1

R7110_RF

0.00

0%
1/32W
MF
01005

2

MBHB_FDD_PAD_VCC1

38

37

C7110_RF

18PF

2%
16V

2

CERM
01005

1

C7132_RF

68PF

2%

6.3V

2

NP0-C0G
01005

NOSTUFF

26

28

2

RFIN_MLB

20

PRX

18

DRX

3

1

PP_1V8_LDO15

75_RFFE6_SDATA

75_RFFE6_SCLK

27

HRPDAF025

LGA

OMIT_TABLE

MLB PA

ANT1

ANT2

14

12

50_LAT_MLB_PA_ANT

50_UAT_MLB_PA_ANT

1

C7122_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

R7105_RF

0.00

1%

1/20W

MF

0201

50_LAT_MLB_G1800_G1900_PA_RX

21

OMIT_TABLE

R7106_RF

1428-1463

72

BI

80

1428-1463

1.8NH+/-0.1NH-0.8A

21

0201

OMIT_TABLE

GND

9

8

7

6

5

4

10

11

13

15

16

17

19

21

26

29

30

31

32

33

THRM_PAD

36

35

34

37

38

39

40

41

42

43

1

C7123_RF

0.6PF

+/-0.05PF
25V

2

CERM
0201

OMIT_TABLE

50_UAT_MLB_COMBINER_IN

73

BI

B

USID=0XB

65 68 73 74 75 77 79 80

IN

68 78 79 80

BI

68 78 79 80

IN

A

11

79

79

72 80

74

72

11

72

72

72

70

70

50_TX_G1800_G1900_PA_OUT_M

IN

50_XCVR0_TX_B1_B3_B4_B25_PA_IN

IN

50_XCVR0_TX_B7_B30_PA_IN

IN

IN

OUT

OUT

OUT

50_TDD_PA_ANT_M

50_LAT_MLB_G1800_G1900_PA_RX

50_LAT_MB_HB_DRX

50_XCVR0_B40B_PA_PRX

19

50_XCVR0_B1_B4_PA_PRX

50_XCVR0_B3_PRX-DSPDT_OUT

50_XCVR0_B7_PA_PRX

OUT

OUT

50_XCVR0_B4_PA_PRX

50_XCVR0_B25_PA_PRX

50_XCVR0_B30_PA_PRX

34

RFIN_GSM

31

RFIN_MB

32

RFIN_HB

7

TRX2

8

TRX3

10

MB_HB_DRX

11

DCS_PCS_RX

1

RX_B1

3

RX_B3

5

RX_B7

17

RX_B4

19

RX_B25

21

RX_B30

2

VIO

VBATT

VCC1

VCC2

MBHBPA_RF

AFEM-8055-AP1

LGA

MB/HB PA

GND

9

4

12

15

16

18

20

22

23

24

25

30

33

35

36

39

40

41

42

6

43

44

USID=0XE

SDATA

46

45

SCLK

47

48

EPAD

49

50

51

52

53

54

55

56

ANT1

ANT2

57

14

13

50_LAT_MB_HB_PA_ANT

50_UAT_MB_HB_PA_ANT

R7103_RF

1.8NH+/-0.1NH-0.8A

21

0201

NOSTUFF

1

C7118_RF

18PF

2%
25V

2

C0H-CERM
0201

2NH+/-0.1NH-0.6A

1

C7119_RF

0.1PF

+/-0.05PF
25V

2

C0G
0201

OMIT_TABLE

R7104_RF

21

0201

OMIT_TABLE

50_LAT_MB_HB_COMBINER_IN

1710-2690

1

C7124_RF

18PF
2%
25V

2

C0H-CERM
0201

NOSTUFF

50_UAT_MB_HB_CPL_IN

1

C7125_RF

18PF

2%
25V

2

C0H-CERM
0201

NOSTUFF

BI

BI

1710-2690

73

73

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

SYNC_DATE=04/17/2015

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

ICEFALL

SWP MUX

34567 8

2 1

D

C

53

OUT

20

NOSTUFF

SE2_PRESENT

53 62 68 81

IN

1

C7201_RF

1UF

20%
10V

2

X5R
0201

SE2

PP1V8_SDRAM

1

R7506_RF

4.99K
1%
1/32W
MF
01005

2

NFC
OMIT_TABLE

1

C7528_RF

2

OMIT_TABLE

20 7 1

53 62 78

R7511_RF

0.00

21

1%

1/20W

MF

0201

NOSTUFF

1UF

20%
10V
X5R
0201

SE2

1

R7512_RF

10K

1%
1/32W
MF
01005

2

1

2

SE2_READY

OMIT_TABLE

PP1V8_ICEFALL_LDOPP1V8_SDRAM

PP1V8_ICEFALL_LDO

C7501_RF

0.1UF
20%

6.3V
X5R-CERM
01005

SE2

OMIT_TABLE

B3

NC

NC

NC
NC

NC

NC

A3
B1
A1
A2

E4

D4

C1

SPI_CLK
SPI_CS
SPI_INT
SPI_MISO
SPI_MOSI

GPIO_0
GPIO_1

NC

C3

C2

VDD1P2

VDD1P8

SE2_RF

BCM20211CP

20

E5

C5

D2

VDDC

VDDC

VDD1P8_BYP

WLBGA

VSS

VSS

VSS

VSS

B5

D5

C4

D1

VDD_SE2_1V8

VOLTAGE=1.80V

VDD_SE2_1V2

VOLTAGE=1.20V

E1

A5

VDDO_NFC

VDDO_HOST_2

DB_RX

DB_TX

DWP
SWP

REG_PU

TCAL_CLK

SE2
OMIT_TABLE

B4
A4

E2
E3

D3

B2

1

1

C7523_RF

1UF

20%
10V

2

X5R
0201

SE2

C7524_RF

1UF
20%
10V

2

X5R
0201

SE2

OMIT_TABLE

OMIT_TABLE

AP_TO_ICEFALL_FW_DWLD_REQ

NC

NC

SE2_SWP

SE2_PWR_REQ

NC

IN

20 17

IN

20 7 1

53 62

53 62 78

53 62 78

PP1V8_SDRAM

1

C7525_RF

0.1UF
20%

6.3V

2

X5R-CERM
01005

SE2

NFC_SWP

IN

20 16 4 3 1

R7510_RF

0.00

0%

1/32W

MF

01005
NFC

1

C7530_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

SE2

OMIT_TABLE

78

21

D

53 62

IN

NFC_SWP_MUX

NFC_SWP_R

SWPMX_RF

NLAS3257CMX2TCG

6

5

S

VCC

DFN

VER 1

B1

GND

B0A

1

2

34

SE2_SWP

SIM1_SWP

20 17

20 17

ICEFALL LDO

OMIT_TABLE

SE2LDO_RF

LP5907UVX-1.825-S

ICEFALL_LDO_ENABLE

17 1

1

C7529_RF

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

SE2

OMIT_TABLE

PP_VDD_MAIN

1

C7531_RF

100PF

5%

6.3V

2

CERM
01005

OMIT_TABLE

B1

VIN

VEN

DSBGA

GND

B2

VOUT

A2A1

PP1V8_ICEFALL_LDO

20

C

B

20 5 4

VDD_SIM1

VDD_SIM1

20 5 4

1

R6900_RF

15.00K

1%
1/32W
MF
01005

2

SIM

SIM CARD CONNECTOR

9 8

IN

SIM1_CLK

68 78 81 68 78 81

3

CLK

J_SIM_RF

SIM_DETECTSIM_DETECT_GND

7

IO

RCPT-WIDE-HSG-THICK-PIVOT

68 78 81

IN

1

C6900_RF

2.2UF

20%

6.3V

2

X5R-CERM

0201-1

SIM

SIM1_RST

17 7 6 5 4

1

DZ6901_RF

12V-33PF

2

01005-1

SIM

2

RESET

1

VCC

PP_1V8_LDO6

5

10

F-RT-SM

SIM

GND

12

11

13

14

15

16

SWP

6

SIM1_DETECT

SIM1_IO

SIM1_SWP

2

DZ6900_RF

5.5V-6.2PF

0201

1

SIM

BI

20 17

OUT

1

C6901_RF

100PF

5%
16V

2

NP0-C0G
01005

SIM

68 78 81

20 17 7

SIM1_RST

20 17 20 17 7

1

DZ6905_RF

SG-WLL-2-2

ESD202-B1-CSP01005

SIM

2

20 17 7

1

DZ6903_RF

SG-WLL-2-2

SIM

2

SIM1_SWPSIM1_IO

SIM1_CLK

1

DZ6902_RF

SG-WLL-2-2

ESD202-B1-CSP01005

SIM

2

1

DZ6904_RF

SG-WLL-2-2

ESD202-B1-CSP01005ESD202-B1-CSP01005

SIM

2

DEBUG CONNECTOR

J_DEBUG

20-5857-036-001-829

F-ST-SM

41

20 16 4 3 1

1 3 17

53 62 67 78

BI

53 62 67 78

BI

53 62 64 78

OUT

53 62 64

OUT

53 62 67

OUT

53 62 67

OUT

4 1

PP_VDD_MAIN

PMU_TO_BB_USB_VBUS_DETECT

90_USB_BB_DATA_P

90_USB_BB_DATA_N

AP_TO_BBPMU_RADIO_ON_L

AP_TO_BB_RESET_L

SWD_AP_TO_MANY_SWCLK

SWD_AOP_BI_BB_SWDIO

PP_VDD_BOOST

3837

21

43

65

87

109

1211

1413

1615

1817

2019

2221

2423

2625

2827

3029

3231

3433

3635

VDD_SIM1

SIM1_RST

SIM1_CLK

SIM1_IO

SIM1_SWP

SIM1_DETECT

BB_JTAG_RST_L

UART_BB_TO_WLAN_COEX

UART_WLAN_TO_BB_COEX

20 5 4

IN

IN

BI

20 17

OUT

OUT

IN

IN

68 78 81

68 78 81

68 78 81

68 78 81

B

67 78

53 62 68 78

53 62 68 78

A

20 17 7

SIM1_IO

R6904_RF

100K

1%

1/32W

MF

01005

SIM

4039

42

NOSTUFF

1

2

SIM1_DETECT

20 17 7

A

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36