Apple iPhone 7 Schematic

PP6907_RF

PP6912_RF

C1710

C7130_RF

C6513_RF

R7110_RF

C6419_RF

FD0406

PP6900_RF

PP6903_RF

R5910_RF

R5501_RF

C5901_RF

C1719C1704C1705C1707

C1744

C1706

R1304

C1727

C1742

C1714

C1726

C7105_RF

R7108_RF

C7110_RF

C6420_RF

C6801_RF

C6806_RF

C6807_RF

C6802_RF

C6805_RF

C6803_RF

FD0400

PP7618_RF

PP1409

PP2002

PP5303

C5501_RF

C5502_RF

C7523_RF

C6501_RF

C7113_RF

SWDS M_RF

R6201_RF

C7132_RF

R7132_RF

C6021_RF

C1466

C1909

C5904_RF

R5511_RF

R5505_RF

R5503_RF

R5908_RF

PP6978_RF

C7501_RF

R7130_RF

C6506_RF

R7113_RF

C6324_RF

C6349_RF

C6348_RF

C6204_RF

R6007_RF

PP7614_RF

PP7615_RF

PP7616_RF

PP7612_RF

PP7613_RF

PP7609_RF

PP7619_RF

C0813

C0814

C0811

C0812

C2618

C7606_RF

C7602_RF

C7607_RF

C7603_RF

C1827

C1833

C1813

C1814

C1866

C1865

C1828

C1820

C1821

C1834

C1839

C1842

C1844C1807

C1838

C1843

C1832

C1826

C1845

C1825

C1831

C1819

C1837

C1818

C1801

C1803

C1501

C1840

C1864

C1436

C1829

C1822

C1835

C1841

C1836

C1802

C1874

C1830

C1823

C1816

PP6904_RF

C5905_RF

U3603

R5909_RF

R3605

C1850C1846

C5801_RF

C5636_RF

C5635_RF

PP6908_RF

C5607_RF

C5738_RF

C5609_RF

C5613_RF

C5602_RF

C5603_RF

Y5501_RF

R5907_RF

EPROM_RF

R5504_RF

C5601_RF

C6900_RF

C5610_RF

R5502_RF

R1118

R1707

C1734
C1731C1717

R1703

C1753

C1736

C1751

C7524_RF

C7103_RF

SE2_RF

C6336_RF

C6337_RF

C7201_RF

C6503_RF

C6514_RF

LBDS M_RF

C6505_RF

C6502_RF

C6515_RF

MHBDS M_RF

R6503_RF

C6512_RF

C6509_RF

C6504_RF

L7122_RF

RXFIL_RF

L6328_RF

C6344_RF

C6334_RF

C6350_RF

L6323_RF

C6345_RF

C6205_RF

L6322_RF

GFIL T_RF

L6201_RF

C6203_RF

R6008_RF

C6022_RF

C6024_RF
C6118_RF

L6111_RF

C6117_RF

C6105_RF

C6001_RF

C6414_RF

SWLATCP_RF

C3605

R5601_RF

C7104_RF

C7528_RF

C7114_RF

C7108_RF

C6002_RF

C7106_RF

C7013_RF

PP7611_RF

C1605

C5612_RF

C1511

R0413

C1506

C1414

R1506

R1504

R2010

R0801

C2011

R0806

C1514 C1612

C1859

C1510

C1848

R1502

C1849 C1847

R2700

C1507

R2000

R3601

C3601

R3604

R5206

RFBUF_ RF

C5615_RF

C5625_RFC5703_RF

C5611_RF

C1724

C6110_RF

C6112_RF

C6507_RF

R6501_RF

C7117_RF

R7002_RF

L6321_RF

L7123_RF

C6004_RF

C6012_RF

C6020_RF

R7109_RF

C6409_RF

C7006_RF

C7601_RF

L7600_RF

C1508

C1013

C1518

C1444

R0800

C0804

R5906_RF

C5631_RF

BBPMU_RF

C5629_RF

C1723

C1743

R7107_RF

R7112_RF

C7129_RF

C6109_RF

C6111_RF

C6510_RF

C6508_RF

R6502_RF

C6014_RF

XCVR0_RF

C7011_RF

C7007_RF

C7600_RF

C0803

C3602

C5608_RF

C7127_RF

R7111_RF

L6325_RF

C6338_RF

R7131_RF

C6318_RF

C6013_RF

R6005_RF

C7009_RF

C7014_RF

C1610

R0807

R0803

C5628_RF

C7126_RF

R6002_RF

L6324_RF

C6302_RF

C6346_RF

C1527

C1420

C2006

U3602

C5702_RF

C1725

C7133_RF

C7128_RF

L6310_RF

C6019_RF

C6011_RF

R6006_RF

C6407_RF

C7008_RF

C0906

C1002

C1001

C1440

C1857

R0804

C5630_RF

C5804_RF

C6007_RF

C6015_RF

C6005_RF

C6335_RF

C6325_RF

C6511_RF

C6320_RF

C6108_RF

C6107_RF

C6114_RF

C6804_RF

C6401_RF

C7001_RF

R0906

C1851

PP6930_RF

R6921_RF
R6922_RF

R5807_RF

C5604_RF

C5626_RF

R1702

C7530_RF

SE2LDO_RF

C7529_RF

C6003_RF

L6311_RF

L6109_RF

LATCP_RF

FL6402_RF

C1010

C1454

C1439

C1862

C0802

C2013

C3606

R3602

R3603

C5623_RF

PP6925_RF

C0807

R1101

DZ6901_RF

C1746

R7114_RF
R7511_RF

C7531_RF

C6023_RF

C7131_RF

C6016_RF

C6008_RF

C6323_RF

C6311_RF

C6319_RF

C6343_RF

C6106_RF

L6110_RF

C7012_RF
C7010_RF

C4709

TP0412

FD0410

PP7620_RF

SH0400

C1011

C7604_RF

C1870

XW1806

C1876

C3604

C5621_RF

C0808

R0802

C7101_RF

XCVR1_RF

R6301_RF

R7103_RF

C6410_RF

C4710

TP0410

C1004

C1457

C1425

L1802

C6017_RF

C6102_RF

C7122_RF

R7105_RF

L6301_RF

C6010_RF

L6102_RF

C6402_RF

GSMPA_RF

R3807

C0907

C1452

C1863

R2011

R5912_RF

C5902_RF

PP6924_RF

C5622_RF

C0809

C1750

C6351_RF

R6003_RF

C7119_RF

C6310_RF

C6317_RF

C6018_RF

C6115_RF

C7118_RF

R6402_RF

R3808

TP0408

PP7621_RF

R0907

C1922

U1801

C5734_RF

C5745_RF

C5735_RF

C5709_RF

C5718_RF

C5701_RF

R5801_RF

C0810

C1715

C6328_RF

L6312_RF

C7123_RF

R7106_RF

R7104_RF

C6309_RF

L6308_RF

C6342_RF

L6306_RF

L6304_RF

C6315_RF

C6113_RF

C6405_RF

R3801

FL3807

FL3811

C6400_RF

C3812

TP0409

C1006

L7502_RF

C1409

C1429

C1904

PP6909_RF

R4714

U1701

C6006_RF

L6320_RF

C6116_RF

R6400_RF

C7124_RF

R3809

WLAN_RF

PP7623_RF

R1001

R1601

FL0700

C0704

C5733_RF

C5731_RF

C5704_RF

C5737_RF

C5740_RF

R4713

C1735

C7016_RF

R7102_RF

R6004_RF

C6329_RF

GSMRX_RF

C6403_RF

R6401_RF

FL6401_RF

R3811

C7521_RF

C1604

C1918

C1932

C1854

C0703

C5605_RF

PP6911_RF

U3601

C3603

C1756

C7015_RF

C7112_RF

C7121_RF

C6009_RF

L6103_RF

C6103_RF

L6318_RF

C6340_RF

C6352_RF

L6313_RF

C7125_RF

L6307_RF

C6316_RF

L6309_RF
C6301_RF

C6314_RF

C6305_RF

C6306_RF

L6305_RF

R6001_RF

R2003

C2009

C6404_RF

C7120_RF

C6411_RF

C6101_RF

C7017_RF

C7005_RF

L6104_RF

R6404_RF

C3824

C1611

C7511_RF

C1459

C1432

C1426

C1902

R0701

C5744_RF

C5753_RF

C5732_RF

C5723_RF

C5627_RF

C1728

C1738

C6307_RF

C6415_RF

C1935

C0806

C1607

C1933

C5713_RF
R5803_RF

C5725_RF

C6332_RF

C6333_RF

C6308_RF

FL7001_RF

C6104_RF

C6406_RF

C6408_RF

NFBS T_RF

R0509

C1421

C1609C1613

C1401

C1858

Y0700

C5717_RF

C5729_RF

C5706_RF

C1709

L6319_RF

C6341_RF

SH0402

C7111_RF

L6101_RF

C7004_RF

C6416_RF

R6405_RF

C6417_RF

C3823

C1434

PP6926_RF

C5754_RF

C5722_RF
C5727_RF

R7101_RF

UATCP_RF

R5806_RF

C5715_RF

R3607

C3607

R4702

R4701

C6418_RF

C3929

PP7622_RF

C7522_RF

C1437

C1402

C1416

C1927

C1603

R0702

C0702

C5741_RF
C5750_RF

C5707_RF

R3611

C3204

C3203

C3211

C3224

PP2401

PP2402

C6704_RF

SUAT1_RF

C8008_RF

C6716_RF

L8008_RF

C6700_RF

L6707_RF

C6720_RF

R6706_RF

C6714_RF

C6721_RF

USPDT2_RF

FL6700_RF

SGND_RF

FL4407

FL4402

FL4401

R4402

C4418

C4401

R4406

C4420

R4405

C4731

C4405

C4404

C4403

C4406

C4419

C4408

DZ4402

DZ4401

DZ4404

DZ4403

FL4403

C0409

PP5302

C4402

C4409

C2611

C2612

C2613

MCEW_ RF

J4504

C4415

C4732

C4414

C4410

C4407

C4413

C4422

XW4501

FL4405

FD0404

C2610

C2614

C0411

FL4732

C4417

C4421

BS0402

FL4731

FL4406
C0410

R4401

FL4404

C4411

C4412

C0408

C4416

R6605_RF

C6610_RF

UPPDI_RF

C6611_RF

C6602_RF

C6601_RF

FD0405

C2609

C0407

R6601_RF

C0412

R2001

C2007

M2600

C6713_RF

R6715_RF

L6700_RF

R6705_RF

PPLXR_RF

C6728_RF

R6710_RF

C6622_RF

C6627_RF

C6726_RF

MLBLN_RF

R6708_RF

C6613_RF

R6606_RF

C6614_RF

FL6602_RF

C6625_RF

C6629_RF

C6620_RF

C6617_RF

LBLN_RF

C6619_RF

BS0403

C6729_RF

C6734_RF

C6732_RF

C6731_RF

C6733_RF

C6730_RF

R6711_RF

JUAT1_RF

C2422

C2414

R2403

R6709_RF

C6727_RF

C2423

R2422

C2413

FL6603_RF

GLNA_RF

C2405

C2421

C6201_RF

C6711_RF

R6703_RF

MHBL N_RF

U2403

L6200_RF

W5BPF_RF
C7711_RF

R7711_RF

C7729_RF

C6735_RF

C2408

R7702_RF

C7709_RF

FL2504

C2523

C2526

C2524

C2525

C2512

C2513

C2522

C2528

C2529

J4501

C2514

FL2501

R2008

C7525_RF

PP5301

L7709 _RF

C7731_RF

L6710_RF

C2420

JUAT2_RF

C771 0_ RF

R1306

C4108

C4127 C4133

FL4105

C4729

C4102

C6701_RF

C6702_RF

TUNFX_RF

FL6701_RF

C0413

TP0414

R2904

C3308

C3501

C3316

TP0421

TP0403 TP0402

C4118

C4131

FL4119

C4110

C4121

C4122

C4120

FL4108

C4119

FL4117

C4129

FL4118

C4130

C4116

R4102

C4101

C3529

C3542

C4136

C4135

C4103

C3434

XW2201

FL6702_RF

FL6703_RF

R2905

C6705_RF

FL2914

R4705

R4707

FL2904

FL2909

TP0423

TP7505_RF

FL2910

FL2903

C2927

R4706

C2909

FL2505

R4708

C3333

C3312

C3323

R3333

C3306

C3325

C3318

C3319

C3315

XW1401

XW1803

FL4815

R2915

C3331

U3301

XW1802

C6703_RF

XW3203

FL2911

R4815

C4803

C3332

R3332

R4604

XW1801

U0700

C4708

R4603

DZ2907

C2924

PP7603_RF

SH0401

R3301

XW2001

C2905

C2908

DZ2905

C2934

C2931

PP7604_RF

C3329

R7512_RF

C3313

XW1807

BB_RF

XW3202

PP6921_RF

PP6933_RF

PP6920_RF

PP6941_RF

PP6918_RF

PP6917_RF

PP6919_RF

PP6969_RF

PP6979_RF

PP6953_RF

PP6973_RF

PP6972_RF

PP6943_RF

C4105

C4109

TP0405TP0404

FL4115

FL4101

R4110

FL4112

R4104

C2117

C2118

C2204

C2202

TP0416

ZT0404

TP0407

R4710

C4106

TP0406

FL4102

R4709

C4111

C2620

C2619

R4109

M2800

no_refdes+3

TP0415

R2201

C2201

C1905

no_refdes+8

C2917

C2521

C2520

C2508

C2506

C2503

C2530

C2510

C1923

C1930

C3311

C1615

C3324

R7520_RF

NFCSW_ RF

C1512

PP7501_RF

R1305

R0901

SWPMX_RF

XW1402

C0909

C0905

C0908

C0904

C1910

L2301

C1911

C1907

C1901

C1914

C3531

PP6931_RF

C3532

R6900_RF

PP3602

PP3601

PP2003

XW2700

C4107

XW2707

C4104

C4132 C4128

C4117

J4101

FL4120

FL4116

C4730

C4134

C4126

J2201

XW2404

C2203

C2445

PP2440

R2404

C2449

R2441

C2448

C2442

U2404

C2443

R3901

R4711

FL3915

JLAT3_RF

C3927

JLAT1_RF

C4507

PP4501

TP0411

CL0401

C3916

no_refdes+7

FD0403

TP0420TP0422

BS0405

C3934

FL3922

R4712
FL3910
C3932

C3913

C3910

C3909

C3914

C3911

C3912

C3924

C3918

C3805

FL4741

C4741

C4742

FL4742
C4711

C4712

R4501

C3915

C3926

FL3919

R3908

C3923

C3928

FL3924

C3925

J4502

C3919

FL3916

C3930

C3936

L3903L3902 L3901

C3935

C3931

XW3801

U3801

D10
PCB: 820-00188-08

R2903

FL2913

FL2908

C2906

C3327

XW2004

PP6971_RF

PP6945_RF

PP7000_RF

PP6940_RF

PP6944_RF

UATDI_RF

FL3801

C3802

C3826

R4807

C4810

C4809

R4806

C3801

C3819

C3817

C3816

C3825

C3818

C3811

C4804

C2921

C2915

R4812

C2916

XW2002

PP6942_RF

LATD I_RF

C4707

J4503

C2903

C3326

C5730_RF

C2926

C1808

C1804

L1804

PP6916_RF

C5616_RF

PP7600_RF

PP7601_RF

PP6935_RF

PP6939_RF

SH0403

MLBPA_R F

J3801

C2933

FL2902

XW2003

C0816

C0817

PP6915_RF

L5601_RF

L5603_RF

PP6938_RF

PP1701

R4811

R4813

L7500_RF

C0818

C0815
PP6970_RF

C5903_RF

PP0801

PP0802

C5632_RF

PP1702

FL2907

C2910

C1869

C5614_RF

no_refdes+2

C2902

C2911

R4810

FL2901

R2002

C2008

FD0407

C7509_RF

C7507_RF

L7501_RF

C1810

C7508_RF

C1806

C1811

PP6923_RF

C0805

C0801

R5911_RF

PP6906_RF

C5624_RF

C5620_RF

L5602_RF

XW5616_RF

C3813

C3815

C3821

FL3803

C3804

C3822

FL3802

C3803

FL3804

C3807

C3806

C3902

FL3904

R4808

R3923

FL2906

DZ2906

C2935

C2932

C3328

XW2005

J_SIM_RF

PP6977_RF

PP6974_RF

C3922

FL3806

R3805

C3828

C4812

C4813

PP7608_RF

R4809

L3302

XW1403

XW1901
XW1902

XW1805

PP6905_RF

PP6952_RF

PP6936_RF

C3814

R3802

TP0413

C2904

C2901

C2914

no_refdes+10

TP7500_RF

C7515_RF

R7508_RF

BALUN_RF

C7516_RF

R7509_RF

C7510_RF

L1801

L1816

U5801_RF

C7518_RF

C7512_RF

C7514_RF

L1810

L1811

L1812

L1813

PP1410PP0902

C1872C1873

PP1411

L1809

L1808

L1807

L1806

L1803

C1867

C1871

L1814

C1861

L1815

L1818

PP6929_RF

C1860

L1817

PP7502_RF

L5604_RF

C5617_RF

C5633_RF

PP6914_RF

XW5614_RF

C5634_RF

C5618_RF

XW5615_RF

L5605_RF

no_refdes+5

no_refdes+5

PP6980_RF

LBPA_RF

TDDPA_RF

MBHBPA_RF

QPOET_RF

no_refdes+4

TP0400 TP0401

TP0419

FD04 08

BS0406

TP0424

no_refdes+1

PP3801

L800 9_RF

no_refdes+6

PP8000_RF

SUAT2_RF

C7730_RF

FD0409

FD0402

ZT0401

PP7606_RF

PP7607_RF

PP7605_RF

C7700_RF

R7700_RF

L7700_RF

C7702_RF

R7703_RF

C7705_RF

C7708_RF

C7707_RF

R7704_RF

PP7610_RF

PP7624_RF P P6981_RF

PP7506_RF

PP7507_RF

R3304

PP7508_RF

PP7505_RF

C1875

C0901

C0903 C0902

C7520_RF

C7517_RF

R0900

R0505

C1465

C1408

R1602

C1913

C1852

C1877

C1908

C0705

XW1804
C1601

C0910

PP2001

C5712_RF

C5721_RF
C5743_RF
C5728_RF

C5716_RF

C5705_RF

C3225

R4002

L2700

C3720

FL3918

FL3908

R3915

FL3909

C3940

C3725

NFC_RF

C1005

C7527_RF

C1448

C1456

C7503_RF

R7599_RF

PP7504_RF

C7526_RF

C7506_RF

C1410

C1413

PP1402PP1401

C1415

PP7509_RF

C1502

C1428

C1460

C1461

C1417

C1418

C1419

C1427

C1433

C1606

PP0701

Y2001

C2307

R2004

C2010

C2002

C1504

C4143

C0701

C1916

C1926

L1805

C5710_RF

C5719_RF

C3201

C3222

C3223

R0805

R1704

C1711

Q4001

C3710

C3403

C3432

C3404

C3526

C3539

C3524

C3538

C3407

U2700

C2703

C2701

R2705

Q2101

C3525

R2702

C3706

C3721

C3704

C3705

C3709C3708

L3704

C3921

FL3912

C3933

FL3902

C1411

C1424

C1431

C1430

C2004

C1412

PP1403

C1404

C1422

C2003

PP1408

C1503

C1442

C1438

C1523

C0800

R2012

FL1501

C1528

C1403

C0700

R2007

C1925

R1114

C1853

C1458

C2302

C2308

R0700

R1303

R1901

C2001

C1921

R2009

R2005

C5736_RF

C1809

C2303

C5755_RF

C2304

C2306

C3212

C1868

C5724_RF

C1805

C1912

C5708_RF

C5714_RF

R5802_RF

C3202

C3113

C2108

FL3901

C5749_RF

C5711_RF

C5742_RF

C5726_RF

C3209

C3208

C5720_RF

U3101

C3112

R3104

R3103

R1103

C3220

C3214

C3213

R3201

C3107

C3205

C3106

PP5304

R2710

C1732

C2710

C1712

C1747C1745

C4007

L4022

L4021

U4001

C4001

R4001

C3427

C4004

C3428

C4003

C2708

FL4106

C3429

U3402

C3430

C3535

C3537C3431

U3502

C3405

R2711

C3536

U2710

C2114

C2700

D2700

C3528

C2103C2112

C2702

C2101

U2101

R2102

C2102

C2110

R2104

C2106

PP4001

C4807

R2701

U4805

U2701

C5906_RF

C2706

R2706

R4803

R2704

R4804

U4802

R2703

R3701

R4805

U4806

FL3906

U3701

D3701D3702

C3424

C2113

C3703

C3719

C4601

U3702

L3703

C3702 C3724

C3711

FL3911

U3703

C3718

FL3920

C4701

C4702

C3920

C3714

FL3917
FL3913

C3901

C3917

C3904

C3903

C3905

C3939

FL3903

C7704_RF

C1407

C1101

U1101

C2111

R2101

C5907_RF

C3716

W25DI_RF

C7706_RF

C7703_RF

R7701_RF

PP7617_RF

R7600_RF

C1405

C1435

R4715

C2309

C1915

R3202

R6904_RF R1701

C1754

C1713

C1702

C1703C1708

C1730

C1729

C1722

C1720

C1733

C1752

C1718

C1749

Q2700

R3508

C5908_RF

C3530

C3722

C3715

C3717

R2006

PP7503_RF

C1423

C1406

C1529

C1602

C1513

R4716

U2301

C5739_RF

C5746_RF

C1721

C1701

C1737

C1739

C1740

C2109

C2105

C2115

R2103

C5909_RF

GPIO_RF

C3707

L7701_RF

PP7500_RF

R7510_RF

C7505_RF

C1509

R7502_RF

C7504_RF

C1515

R0504

R0508

R2020

R1505

R0501

R0503

C1522

R1113

R1210

R4703

C4703

C2301

C5748_RF

R1116

C3221

DZ6903_RF

DZ6905_RF

DZ6902_RF

DZ6904_RF

C1716

C1748

Q2701

C4608

C3422

C4002

C3527

C2104

R2105

Q2102

C3938

C3713 C3712

W2BPF_RF

C1519

C1449

C0900

C1614

C1608

R1501

R4704

C4704

R2301

C3217

C5752_RF
C3215

C5747_RF

C6901_RF

R3101

C4008

C2707 C3534

C4005

C4006

C3426

C2617

C3727 C3726

C0416

C2527

C0414

C0415

C7701_RF

L7702_RF

L7703_RF

C7502_RF

R1503

R7506_RF

C7500_RF

R4801

R4802

R2015

C1855

C1856

C1919

C2704

PP6913_RF

C5751_RF

C1741

MCNS_ RF

DZ6900_RF

C2705

FL4121

FL4107

FL4604

FL4729

FL4730

C3937

FL4103

FL4114

C3425

C2531

FL2502

C2507

U2501

FL2503

R4817

C2501

C2505

FL2500

C2519

C2504

FL2506

R4816

C2509

C4817

C4816

C2518

C2511

C2515

C2502

TP8000_RF

no_refdes+9

USPDT_RF

L8007_RF

C8005_RF

C8007_RF

U2402

PP2404

XW3333

C2401

PP2403

C2418

C0406

C0402

C0404

C0401

C0405
C0403

C0420

C0418

C0417

C0419

C0421

C0422

VIETMOBILE.VN

34567 8

2 1

D

C

B

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D10 MLB - DVT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

<CSA>

<CSA_PAGE1>

<CSA_PAGE2>

<CSA_PAGE3>

<CSA_PAGE4>

<CSA_PAGE5>

<CSA_PAGE6>

<CSA_PAGE7>

<CSA_PAGE8>

<CSA_PAGE9>

<CSA_PAGE10>

<CSA_PAGE11>

<CSA_PAGE12>

<CSA_PAGE13>

<CSA_PAGE14>

<CSA_PAGE15>

<CSA_PAGE16>

<CSA_PAGE17>

<CSA_PAGE18>

<CSA_PAGE19>

<CSA_PAGE20>

<CSA_PAGE21>

<CSA_PAGE22>

<CSA_PAGE23>

<CSA_PAGE24>

<CSA_PAGE25>

<CSA_PAGE26>

<CSA_PAGE27>

<CSA_PAGE28>

<CSA_PAGE29>

<CSA_PAGE30>

<CSA_PAGE31>

<CSA_PAGE32>

<CSA_PAGE33>

<CSA_PAGE34>

<CSA_PAGE35>

<CSA_PAGE36>

<CSA_PAGE37>

<CSA_PAGE38>

<CSA_PAGE39>

<CSA_PAGE40>

<CSA_PAGE41>

<CSA_PAGE42>

<CSA_PAGE43>

<CSA_PAGE44>

<CSA_PAGE45>

CONTENTSPAGE

TABLE OF CONTENTS

MLB SPECIFIC: BOM TABLE

SYSTEM:MECHANICAL, TESTPOINTS
SYSTEM:BOARDID

spare

SOC:JTAG,USB,XTAL

SOC:PCIE

SOC:MIPI AND ISP

SOC:LPDP

SOC:SERIAL

SOC:GPIO & UART

SOC:AOP

SOC:POWER (1/3)

SOC:POWER (2/3)

SOC:POWER (3/3)

NAND

SYSTEM POWER:PMU (1/3)

SYSTEM POWER:PMU (2/3)

SYSTEM POWER:PMU (3/3)

SYSTEM POWER:CHARGER

SYSTEM POWER:BATTERY CONN

SYSTEM POWER:BOOST

SENSORS

B2B FILTERS: UTAH

CAMERA:STROBE DRIVER

Accessory: Buck Circuit

TRINITY: FF SPECIFIC

B2B:FOREHEAD

spare

AUDIO:CALTRA CODEC (1/2)

AUDIO:CALTRA CODEC (2/2)

AUDIO:SPEAKER AMP 2

AUDIO:SPEAKER AMP 1

ARC:DRIVER

ARC:MAGGIE

DISPLAY & MESA:POWER

B2B:ORB & MESA

B2B FILTERS: DISPLAY & TOUCH

TRISTAR 2

B2B:DOCK FLEX

spare <SYNC_MASTER42>

spare

B2B: SMALL FF SPECIFIC

SYNC

<SYNC_MASTER1>

<SYNC_MASTER2>SYSTEM:BOM TABLES

<SYNC_MASTER3>

<SYNC_MASTER4>

<SYNC_MASTER6>

<SYNC_MASTER7>

<SYNC_MASTER8>

<SYNC_MASTER9>

<SYNC_MASTER10>

<SYNC_MASTER11>

<SYNC_MASTER12>

<SYNC_MASTER13>

<SYNC_MASTER14>

<SYNC_MASTER15>

<SYNC_MASTER16>

<SYNC_MASTER17>

<SYNC_MASTER18>

<SYNC_MASTER19>

<SYNC_MASTER20>

<SYNC_MASTER21>

<SYNC_MASTER22>

<SYNC_MASTER23>

<SYNC_MASTER24>

<SYNC_MASTER25>

<SYNC_MASTER26>

<SYNC_MASTER27>

<SYNC_MASTER28>

<SYNC_MASTER29>

<SYNC_MASTER30>

<SYNC_MASTER31>

<SYNC_MASTER32>

<SYNC_MASTER33>

<SYNC_MASTER34>

<SYNC_MASTER35>

<SYNC_MASTER36>

<SYNC_MASTER37>

<SYNC_MASTER38>

<SYNC_MASTER39>

<SYNC_MASTER40>

<SYNC_MASTER41>

<SYNC_MASTER43>

<SYNC_MASTER44>B2B FILTERS: RIGHT BUTTON FLEX

<SYNC_MASTER45>

LAST_MODIFICATION=Tue Jun 14 15:20:28 2016

<SYNC_DATE1>

<SYNC_DATE2>

<SYNC_DATE3>

<SYNC_DATE4>

<SYNC_DATE5>

<SYNC_DATE6>

<SYNC_DATE7>

<SYNC_DATE8>

<SYNC_DATE9>

<SYNC_DATE10>

<SYNC_DATE11>

<SYNC_DATE12>

<SYNC_DATE13>

<SYNC_DATE14>

<SYNC_DATE15>

<SYNC_DATE16>

<SYNC_DATE17>

<SYNC_DATE18>

<SYNC_DATE19>

<SYNC_DATE20>

<SYNC_DATE21>

<SYNC_DATE22>

<SYNC_DATE23>

<SYNC_DATE24>

<SYNC_DATE25>

<SYNC_DATE26>

<SYNC_DATE27>

<SYNC_DATE28>

<SYNC_DATE29>

<SYNC_DATE30>

<SYNC_DATE31>

<SYNC_DATE32>

<SYNC_DATE33>

<SYNC_DATE34>

<SYNC_DATE35>

<SYNC_DATE36>

<SYNC_DATE37>

<SYNC_DATE38>

<SYNC_DATE39>

<SYNC_DATE40>

<SYNC_DATE41>

<SYNC_DATE42>

<SYNC_DATE43>

<SYNC_DATE44>

<SYNC_DATE45>

<CSA>

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75 DIVERSITY RECEIVE LNA'S

76

77

78

79

80

81 ICEFALL, SIM, DEBUG_CONN

<CSA_PAGE46>

<CSA_PAGE47>

<CSA_PAGE48>

<CSA_PAGE49>

<CSA_PAGE50>

<CSA_PAGE51>

<CSA_PAGE52>

<CSA_PAGE53>

<CSA_PAGE54>

<CSA_PAGE55>

<CSA_PAGE56>

<CSA_PAGE57>

<CSA_PAGE58>

<CSA_PAGE59>

<CSA_PAGE60>

<CSA_PAGE61>

<CSA_PAGE62>

<CSA_PAGE63>

<CSA_PAGE64>

<CSA_PAGE65>

<CSA_PAGE66>

<CSA_PAGE67>

<CSA_PAGE68>

<CSA_PAGE69>

<CSA_PAGE70>

<CSA_PAGE71>

<CSA_PAGE72>

<CSA_PAGE73>

<CSA_PAGE74>

<CSA_PAGE75>

<CSA_PAGE76>

<CSA_PAGE77>

<CSA_PAGE78>

<CSA_PAGE79>

<CSA_PAGE80>

<CSA_PAGE81>

<CSA_PAGE82>

<CSA_PAGE83>

<CSA_PAGE84>

<CSA_PAGE85>

<CSA_PAGE86>

<CSA_PAGE87>

<CSA_PAGE88>

<CSA_PAGE89>

<CSA_PAGE90>

CONTENTSPAGEDATE

SMALL FORM FACTOR SPECIFIC

I2C MAP: AP, TOUCH, HOMER, I2C5

I2C MAP AOP

I2C TABLE

spare

spare

MLB UNIQUE

CELL,WIFI,NFC

WIFI_MLB SCHEMATIC

PERENNIAL

WIFI FRONT-END [77]

page1

NFC

page1 [1]

UAT MATCH AND TUNER CONNECTOR [2]

BOM LIST

page1

BOM_OMIT_TABLE

PMU: CONTROL AND CLOCKS

PMU: SWITCHERS AND LDOS

BASEBAND: POWER2

BASEBAND: CONTROL

BASEBAND GPIOS

TRANSCEIVER0/1: POWER

TRANSCEIVER0/1: TX PORTS

TRANSCEIVER0/1: PRX PORTS

RECEIVE MATCHING

LOWER ANTENNA & COUPLERS

DIVERSITY RECEIVE ASM'S

UPPER ANTENNA FEEDS

PMU: ET MODULATOR

TEST POINTS & BOOT CONFIG

TDD TRANSMIT

FDD TRANSMIT

<SYNC_MASTER46>

<SYNC_MASTER47>

<SYNC_MASTER48>

<SYNC_MASTER49>

<SYNC_MASTER50><SYNC_MASTER5>

<SYNC_MASTER51>

<SYNC_MASTER52>

<SYNC_MASTER53>

<SYNC_MASTER54>

<SYNC_MASTER55>

<SYNC_MASTER56>

<SYNC_MASTER57>

<SYNC_MASTER58>

<SYNC_MASTER59>

<SYNC_MASTER60>

<SYNC_MASTER61>

<SYNC_MASTER62>

<SYNC_MASTER63>

<SYNC_MASTER64>

<SYNC_MASTER65>

<SYNC_MASTER66>

<SYNC_MASTER67>

<SYNC_MASTER68>

<SYNC_MASTER69>

<SYNC_MASTER70>

<SYNC_MASTER71>

<SYNC_MASTER72>

<SYNC_MASTER73>

<SYNC_MASTER74>

<SYNC_MASTER75>

<SYNC_MASTER76>

<SYNC_MASTER77>

<SYNC_MASTER78>

<SYNC_MASTER79>

<SYNC_MASTER80>

<SYNC_MASTER81>

<SYNC_MASTER82>

<SYNC_MASTER83>

<SYNC_MASTER84>

<SYNC_MASTER85>

<SYNC_MASTER86>

<SYNC_MASTER87>

<SYNC_MASTER88>

<SYNC_MASTER89>

<SYNC_MASTER90>

ECNREV DESCRIPTION OF REVISION

DATESYNC

<SYNC_DATE46>

<SYNC_DATE47>

<SYNC_DATE48>

<SYNC_DATE49>

<SYNC_DATE50>

<SYNC_DATE51>

<SYNC_DATE52>

<SYNC_DATE53>

<SYNC_DATE54>

<SYNC_DATE55>

<SYNC_DATE56>

<SYNC_DATE57>

<SYNC_DATE58>

<SYNC_DATE59>

<SYNC_DATE60>

<SYNC_DATE61>

<SYNC_DATE62>

<SYNC_DATE63>

<SYNC_DATE64>

<SYNC_DATE65>

<SYNC_DATE66>

<SYNC_DATE67>

<SYNC_DATE68>

<SYNC_DATE69>

<SYNC_DATE70>

<SYNC_DATE71>

<SYNC_DATE72>

<SYNC_DATE73>

<SYNC_DATE74>

<SYNC_DATE75>

<SYNC_DATE76>

<SYNC_DATE77>

<SYNC_DATE78>

<SYNC_DATE79>

<SYNC_DATE80>

<SYNC_DATE81>

<SYNC_DATE82>

<SYNC_DATE83>

<SYNC_DATE84>

<SYNC_DATE85>

<SYNC_DATE86>

<SYNC_DATE87>

<SYNC_DATE88>

<SYNC_DATE89>

<SYNC_DATE90>

APPD

DATE

2016-06-1400064008778 ENGINEERING RELEASED

D

C

B

A

TABLE OF CONTENTS

Schematic & PCB Callouts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SCH1 SCH,MLB,D10051-00419

CRITICAL

CRITICALPCB1820-00188 PCBF,MLB,D10

8 7 5 4 2 1

BOM OPTIONCRITICAL

?

?

TABLE_5_HEAD

TABLE_5_ITEM

System Block Diagram:

<rdar://problem/16684269>

SCH 051-00419
BRD 820-00188

MCO 056-01342

36

TABLE OF CONTENTS

SYNC_MASTER=Sync

PAGE TITLE

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Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

NAND BOM Options

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NAND,H,32GB,16nm,MLC

1 CRITICALU1701335S00169

335S00182 1 U1701 CRITICAL

335S00156 1 U1701 CRITICAL

138S0867 5

138S00003 CRITICAL

138S00003 CRITICAL

335S00180 T,15nm,TLC,128GBALTERNATE U1701335S00182

#22686038:See Radar

NAND,H,128GB,16nm,TLC

NAND,H,256GB,3Dv3,TLC

CAP,X5R,10UF,20%,6.3V,0.65MM,HRZTL,0402 C1748,C1713,C1716,C1721,C1733

5

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402 C1748,C1713,C1716,C1721,C1733

5

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402

PART NUMBER

C1748,C1713,C1716,C1721,C1733

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

335S00169335S00201 U1701 T,15nm,MLC,32GBALTERNATE

335S00169 ALTERNATE U1701 S,16nm,MLC,32GB335S00209

335S00182335S00195 U1701ALTERNATE SS,1Ynm,TLC,128GB

U1701335S00182 ALTERNATE335S00179 SD,15nm,TLC,128GB

335S00183 U1701 SD,3Dv2,TLC,256GBALTERNATE335S00148

U1701ALTERNATE335S00183 SS,3Dv3,TLC,256GB335S00190

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

NAND_32G

NAND_128G

NAND_256G

NAND_32G

NAND_128G

NAND_256G

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

Active Diode Alternate

PART NUMBER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

DDR PLL Alternate

PART NUMBER

155S00068155S00095

ALTERNATE FL1501

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

FERR BD,100OHM,25%,100MA,2OHM,01005

Power Inductor Alternates

PART NUMBER

152S00118 152S00075

152S00077 ALL152S00397

152S00121 152S00081

152S00366152S00402 ALLALTERNATE

152S1843

ALTERNATE ALL

ALTERNATE

ALTERNATE ALL

ALTERNATE152S1936152S00123 ALL

ALTERNATE152S00297 ALL

ALTERNATE152S00297 ALL152S00365

ALTERNATE152S00398 152S00204 ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

IND,PWR,SHLD,1.2 UH,3.0A,0.080 OHM,2016

IND,PWR,SHLD,1.0 UH,2.25A,0.150 OHM,2016

IND,PWR,SHLD,0.47 UH,3.8A,0.048 OHM,2012

IND,PWR,SHLD,15 UH,0.72A,0.900 OHM,3225

IND,MULT,1UH,1.2A,0.320 OHM,0603

CYNTEC 2012 1UH

CYNTEC 2012 1UH

IND,PWR,0.22UH,20%,6.7a,23MOHM,2012

TABLE_ALT_HEAD

TABLE_ALT_ITEM

ACC BUCK CIRCUIT Alternates

376S00166

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

reverted 11/13

TABLE_ALT_ITEM

TABLE_ALT_ITEM

For Chestnut inductor; so it doesn't interfere with PMU inducotr Buck 7 alts

PART NUMBER

371S00064DIODES INC. ACT DIODEALTERNATE376S00047376S00106 Q2101

ALTERNATE371S00087 D2700

152S00557152S00558 ALTERNATE

376S00164 ALTERNATE

353S01039 ALTERNATE U2710353S01007

L2700

Q2700,Q2701

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

DIODE,SHOTTKY,30V,200MA,0201

TABLE_ALT_ITEM

IND,MLD,0.47UH,2.5A,80Mohm,1608

TABLE_ALT_ITEM

PFET,12V,CSP4

TABLE_ALT_ITEM

IC,LOAD SWITCH,WLCSP4

D

C

Magnesium Alternates

PART NUMBER

338S00203338S00173 U2402

ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

Larger Wafer (-29 flow) Magnesium

TABLE_ALT_HEAD

TABLE_ALT_ITEM

152S00120 152S00077 ALTERNATE

152S00117 152S00074

ALTERNATE

ALL

L1806,L1810,L1814,L1816,L1817

Global R/C Alternates

PART NUMBER

118S0764 ALTERNATE ALL

138S0702 ALTERNATE ALL

138S00006

138S0648

132S0436 132S0400

118S0717

138S0657

ALTERNATE138S0835 ALL

138S00003 ALTERNATE138S00005 ALL

ALTERNATE138S00003138S00048

ALL

138S0652 ALTERNATE ALL

132S0436132S0400 ALTERNATE ALL

138S0986 ALL138S00024

138S0739 ALTERNATE

ALTERNATE

ALL138S0706

ALL138S0945 ALTERNATE138S0739

ALTERNATE

ALL

For Chestnut inductor only

IND,PWR,SHLD,1.0 UH,3.0A,0.060 OHM,2016

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

RES, 3.92K, 0.1%, 0201

CAP, X5R, 4.3UF, 4V, 0610

CAP, 3-TERM, 4.3UF, 4V, 0402

CAP,X5R,15UF,6.3V,0.65MM,0402,TAIYO

CAP,X5R,15UF,6.3V,0.65MM,0402,KYOCERA

CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

CAP,X5R,0.22UF,6.3V,01005,TDK

CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK

CAP,CER,1UF,20%,10V,X5R,0201,MURATA

CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA

CAP,CER,X5R,0.22UF,20%,6.3V,20%

Except BUCK5 LX (BUCK5 LX is Taiyo only)

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

C

B

Carbon Alternates

PART NUMBER

ALTERNATE338S00087 338S00226

UT LDO Alternates

PART NUMBER

ALTERNATE U2501353S00015353S00889

U2401,U2404

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

Updated version of Carbon

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ST, LDO REG, 2.925V, CSP 0.65x0.65

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Global Ferrite Alternates

PART NUMBER

155S0581 ALTERNATE ALL155S00067

155S00012 ALLALTERNATE155S00168

155S0610

152S00489 ALLALTERNATE152S00456

ALTERNATE155S0581 ALL155S00067

ALLALTERNATE155S00194

ALLALTERNATE155S00200 155S0610

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

FERR, 240OHM, 0.38OHM DCR, 0201

FERR, 240OHM, 0.38OHM DCR, 0201

FLTR, 65 OHMS, 0605

FERR BD, 150OHM, TDK

FERR BD, 150OHM, TY

FERR BD, 0.47UH, TY

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

B

A

Mamba LDO Alternates

PART NUMBER

U3801353S00932 353S00576 ALTERNATE

I2C5 Alternate

PART NUMBER

ALTERNATE335S00234 335S00233 U1101

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ST, LDO REG, 2.75V

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

I2C5 ALTERNATE

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Global Varistor Alternates

PART NUMBER

377S0140 ALL377S0168 ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

VARISTOR, 6.8V, 100PF, 01005

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SYNC_MASTER=Sync

PAGE TITLE

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

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8 7 5 4 2 1

36

D

D10 EEEE CALLOUTS

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 EEEE CODE FOR 639-01754 EEEE_GXD5 CRITICAL825-6838

825-6838

1 CRITICALEEEE_H6TFEEEE CODE FOR 639-02372825-6838

1

EEEE CODE FOR 639-02374 EEEE_H6TH825-6838 CRITICAL1

EEEE_GXD7 CRITICAL1 EEEE CODE FOR 639-01756

EEEE_H6TGEEEE CODE FOR 639-02373825-6838

CRITICALEEEE_GXD6825-6838 1 EEEE CODE FOR 639-01755

CRITICAL

BOM OPTIONCRITICAL

EEEE_BEST

EEEE_SUPREME

EEEE_EXTREME

EEEE_BEST_ROW

EEEE_SUPREME_ROW

EEEE_EXTREME_ROW

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

34567 8

2 1

D

C

CAYMAN DDR Alternates

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TABLE_ALT_ITEM

339S00254

339S00255

PART NUMBER

339S00253

ALTERNATE ALL339S00253 DDR-H, 2G, B1

ALTERNATE ALL DDR-S, 2G, B1

Cap 2.2UF Alternates

PART NUMBER

138S00032

ALTERNATE138S00049

(C2507,C2531)

ALLALTERNATE138S00032138S0831

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CAP,CER,X5R,2,2UF,20%6.3V,20%, KYOCERA

CAP,CER,X5R,2,2UF,20%,6.3V,20%,MURATA

D10x Specific BOM Callouts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1152S00117 CRITICALL1803

TAIYO,IND,PWR,SHLD,1UH,3.6A,0.060OHM,2016

117S0156 2 CRITICAL

RES,MF,1K OHM, 5%, 1/32W, 01005

R4808,R4809

TABLE_ALT_HEAD

TABLE_ALT_ITEM

#25634778: Exclude Kyocera as 2.2UF alt at only C2507/C2531 REFDES (other refdes no impact)

TABLE_ALT_ITEM

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

B5LX_TAIYO

TABLE_5_ITEM

UTAH_C

#24681501

#24629229

C

B

B

A

SYNC_MASTER=Sync

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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

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34567 8

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D

Current as of D10 MCO 056-01342-78

NORTH_SCREW_EXPOSED

O

Contained in radio_mlb pages

1

C0413

100PF

5%
16V

2

NP0-C0G
01005

1

C0414

56PF

5%
25V

2

NP0-C0G-CERM
01005

O

O

ZT0401

2.70R1.80-NSP

1

CHASSIS_GND_BS401

1

C0401

220PF

5%
10V

2

C0G-CERM
01005

CHASSIS_GND_BS402

4

1

C0407

220PF

5%
10V

2

C0G-CERM
01005

1

C0402

220PF

5%
10V

2

C0G-CERM
01005

1

C0408

220PF

5%
10V

2

C0G-CERM
01005

44

1

2

1

2

BS0402

C0403

100PF

5%
16V
NP0-C0G
01005

C0409

100PF

5%
16V
NP0-C0G
01005

STDOFF-2.56OD1.4ID-1.10H-SM

1

CHASSIS_GND_BS402

1

C0404

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0410

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0405

18PF

2%
16V

2

CERM
01005

1

C0411

18PF

2%
16V

2

CERM
01005

4

1

2

1

2

BS0403

C0406

4PF

+/-0.1PF
16V
NP0-C0G
01005

C0412

4PF

+/-0.1PF
16V
NP0-C0G
01005

STDOFF-2.56OD1.4ID.99H-SM

CHASSIS_GND_BS403

1

4

1

C0415

18PF 4PF

2%
16V

2

CERM
01005

1

2

C0416

+/-0.1PF
16V
NP0-C0G
01005

41 40 21

22 21

28 27 26 25 23 21 19 18 10 9
52 46 41 40 39 37 35 34 33 31

53

DFU

TESTPOINTS

POWER

PP5V0_USB

PP_BATT_VCC

PP_VDD_MAIN

TP0419

1

TP-P55

ROOM=TEST

A

TP0420

ROOM=TEST

TP0421

ROOM=TEST

TP0415

ROOM=TEST

TP0422

ROOM=TEST

TP0408

ROOM=TEST

FD0408

0P5SM1P0SQ-NSP

ROOM=TEST

TP0424

ROOM=TEST

1

TP-P55

1

TP-P55

1

TP-P55

1

TP-P55

1

TP-P55

FID

1

1

TP-P55

A

POWER GROUND

A

VBUS

VBATT

A

A

A

A

VDD_MAIN

Note: Fiducial used as test point

FD0400

FID

0P5SQ-SMP3SQ-NSP

1

ROOM=TEST

GND TP

FIDUCIALS

FD0410

FID

0P5SM1P0SQ-NSP

1

FD0409

0P5SM1P0SQ-NSP

1

FD0405

0P5SM1P0SQ-NSP

1

FD0406

0P5SQ-SMP3SQ-NSP

1

FD0404

0P5SQ-SMP3SQ-NSP

1

FD0403

0P5SQ-SMP3SQ-NSP

1

FD0402

0P5SQ-SMP3SQ-NSP

1

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

FID

ROOM=ASSEMBLY

D

C

CHASSIS_GND_BS403

4

1

C0417

220PF

5%
10V

2

C0G-CERM
01005

1

C0418

220PF

5%
10V

2

C0G-CERM

01005

1

C0419

100PF

5%
16V

2

NP0-C0G
01005

1

C0420

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0421

18PF

2%
16V

2

CERM
01005

1

C0422

4PF

+/-0.1PF
16V

2

NP0-C0G
01005

Back Shields

1

SH0400

SM

SHLD-EMI-UPPER-BK-D10

1

SH0402

SM

Front Shields

1

SH0401

SM

SHLD-EMI-UPPER-FRT-D10

1

SH0403

SM

PMU_TO_AP_FORCE_DFU

20 12

E75

90_TRISTAR_DP1_CONN_P

41 40

90_TRISTAR_DP1_CONN_N

41 40

90_TRISTAR_DP2_CONN_P

41 40

90_TRISTAR_DP2_CONN_N

41 40

PP_TRISTAR_ACC1

41 40

PP_TRISTAR_ACC2

41 40

TP0414

1

TP-P55

ROOM=TEST

TP0402

1

TP-P55

ROOM=TEST

TP0403

1

TP-P55

ROOM=TEST

TP0404

1

TP-P55

ROOM=TEST

TP0405

1

TP-P55

ROOM=TEST

TP0406

1

TP-P55

ROOM=TEST

TP0407

1

TP-P55

ROOM=TEST

A

FORCE DFU

A

A

A

A

A

ACCESSORY ID AND POWER

A

C

FD0407

FID

0P5SM1P0SQ-NSP

1

ROOM=TEST

B

SHLD-EMI-LOWER-BK-D10

ZT0404

2.70R1.80-NSP

1

SHLD-EMI-LOWER-FRT-D10

TRISTAR_CON_DETECT_L

41 40

AMUX

PMU_AMUX_AY

20

PMU_AMUX_BY

20

TP0416

1

TP-P55

ROOM=TEST

TP0412

1

TP-P55

ROOM=TEST

TP0423

1

TP-P55

ROOM=TEST

A

A

TP IS TO HELP WITH USB SI
IN THE FACTORY FIXTURE.

A

FOR DIAGS

TP0413

1

TP-P55

ROOM=TEST

1

R0413

200K

1%
1/32W
MF
01005

2

ROOM=PMU

A

ANALOG MUX A OUTPUT

#25244799

100k to 200k

ANALOG MUX B OUTPUT

B

A

BS0405

STDOFF-2.56OD1.4ID.99H-SM

1

CLIP-MLB-COAX-RETENTION-D10

CL0401

SM-SP

1

TOP SIDE

BS0406

STDOFF-2.9OD1.9ID-0.85H-SM

1

MOJAVE

MESA_TO_BOOST_EN

38 37

PP16V0_MESA

38 37

LCM

PP_LCM_BL_CAT1_CONN

45 39

PP_LCM_BL_CAT2_CONN

45 39

PP_LCM_BL_ANODE_CONN

45 39

TP0400

1

TP-P55

ROOM=TEST

TP0401

1

TP-P55

ROOM=TEST

TP0409

ROOM=TEST

TP0410

ROOM=TEST

TP0411

A

A

1

TP-P55

1

TP-P55

1

TP-P55

ROOM=TEST

A

A

A

LCM BACKLIGHT SINK1

LCM BACKLIGHT SINK2

LCM BACKLIGHT SOURCE

SYNC_MASTER=Sync

PAGE TITLE

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Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

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PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

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34567 8

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C

BOOTSTRAPPING:BOARD REV

BOARD_REV3

12

BOARD_REV2

12

BOARD_REV1

12

BOARD_REV0

12

BOARD_ID4=No connect

PP1V8

11

NOSTUFF

R0509

010055%MF 1/32W

NOSTUFF

R0505

R0508

NOSTUFF

R0504

01005

ROOM=SOC

ROOM=SOC

MF

ROOM=SOC

MF01005

ROOM=SOC

MF 1/32W

5%

5%

21

21

1/32W01005

21

1/32W

21

5%

1.00K

1.00K

1.00K

1.00K

MAKE_BASE=TRUE

BOARD ID
BOOT CONFIG

PP1V8

SELECTED -->

52 48 47 46 39

BOARD_REV[3:0]

FLOAT=LOW, PULLUP=HIGH

1111 Pre-Proto w/D520 (non enclosure)

1110 PROTO1

1101 PROTO2

1100 PROTO2v5

1011 EVT1
1010 EVT2
xxxx SPARE

1000 CARRIER

xxxx SPARE

0010 DVT

xxxx SPARE

0000 PVT

29 25 18 17 16 13 12 11 9 8 7

D

C

B

NOSTUFF

BOARD_ID2

11

0=EUREKA, 1=KAROO

R0503

01005 MF

NOSTUFF

BOARD_ID1

11

0=FORM FACTOR A, 1=FORM FACTOR B

BOARD_ID0=No connect

PP1V8

12

BOOT_CONFIG1=No connect

BOOT_CONFIG0=No connect

R0501

ROOM=SOC

5%

ROOM=SOC

5%

1.00K

21

1/32W

1.00K

21

1/32W01005 MF

MAKE_BASE=TRUE

BOARD_ID[4:0]

FLOAT=LOW, PULLUP=HIGH

SELECTED --> 01000 D10 MLB

01001 D10 DEV

01010 D11 MLB

01011 D11 DEV

01100 D101 MLB

01101 D101 DEV

01110 D111 MLB

01111 D111 DEV

0=MLB, 1=DEV

0=FORM FACTOR A, 1=FORM FACTOR B

0=EUREKA, 1=KAROO

BOOT_CONFIG[2:0]

FLOAT=LOW, PULLUP=HIGH

000 SPI0

001 SPI0 TEST MODE

010 NVME0_X2

011 NVME0 X2 TEST

SELECTED -->

100 NVME0 X1

101 NVME0 X1 TEST

110 SLOW SPI0 TEST

111 FAST SPI0 TEST

B

A

SYNC_MASTER=Sync

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C

C

B

B

A

SYNC_MASTER=Sync

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SOC - USB, JTAG, XTAL

VDD18_AMUX: 1.62-1.98V @1mA MAX

PP1V1_XTAL

C0700

1

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

1

C0704

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP3V3_USB

VDD18_USB: 1.71-1.89V @20mA MAX

FL0700

VDD11_XTAL:1.06-1.17V @TBD mA MAX

240-OHM-25%-0.20A-0.9DCR

21

01005

ROOM=SOC

19

1

C0705

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

PP1V1

PP1V8

52 48 47 46 39

29 25 18 17 16 13 12 11 9 8 7 5

D

18 15

C

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

PP1V8

CKPLUS_WAIVE=PWRTERM2GND

CL20

VDD12_UH1_HSIC0

AJ60

VDD18_AMUX

CE25

VDD18_USB

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

CG50

VDD11_XTAL

CG26

1

C0701

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

CC25

VDD33_USB

VDD_FIXED_USB

PP0V9_SOC_FIXED

3.14-3.46V @20mA MAX

18 15 10 9 8

tbd - tbd V @5mA MAX

C

B

Dev ONLY

40 37 20 13

PP0701

P2MM-NSM

SM

1

PP

SWD_DOCK_BI_AP_SWDIO

40

SWD_DOCK_TO_AP_SWCLK

40

PMU_TO_SYSTEM_COLD_RESET_L

20 13

PMU_TO_AOP_TRISTAR_ACTIVE_READY

AP_TO_PMU_TEST_CLKOUT

20

AP_TO_NAND_RESET_L

17

NC

NC

NC

NC

NC

CM22
CM20

CL31

CL29

CG37

CJ35
CK33
CH37

CM14

BJ3

BJ2

BL65

UH1_HSIC0_DATA
UH1_HSIC0_STB

JTAG_SEL

JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

COLD_RESET*

CFSB

TST_CLKOUT

S3E_RESET*

SYM 1 OF 16

ANALOGMUX_OUT

USB_DP

USB_DM

USB_VBUS

USB_ID

USB_REXT

N64

CM26
CL26

CH26

CJ26

CK26

AP_TO_PMU_AMUX_OUT

90_USB_AP_DATA_P
90_USB_AP_DATA_N

USB_VBUS_DETECT

NC

AP_USB_REXT

20

40

40

21

1

R0700

200

1%
1/32W
MF

2

01005

ROOM=SOC

B

BJ4

HOLD_RESET

BL3

TESTMODE

WDOG

XI0

XO0

CK35

CM42
CL42

AP_TO_PMU_WDOG_RESET

XTAL_AP_24M_IN
XTAL_AP_24M_OUT

20

1

R0701

511K

1%
1/32W

MF

01005

2

ROOM=SOC

R0702

0.00

0%

1/32W

MF

01005

ROOM=SOC

CRITICAL
ROOM=SOC

Y0700

1.60X1.20MM-SM

24.000MHZ-30PPM-9.5PF-60OHM

21

SOC_24M_O

1

C0702

12PF

5%
16V
CERM

2

01005

ROOM=SOC

31

42

1

C0703

12PF

5%

2

16V
CERM
01005

ROOM=SOC

A

SYNC_MASTER=Sync

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

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A

SOC - PCIE INTERFACES

34567 8

2 1

D

19 16 10

PP1V2_SOC

1

C0805

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

R0804

0.00

1/32W

01005

ROOM=SOC

21

0%

MF

VDD12_PCIE: 1.14-1.26V @10mA MAX

1

C0801

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

VDD12_PCIE_REFBUF:1.08-1.26V @40mA MAX

PP1V2_SOC_PCIE_REFBUF

1

C0802

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

CE58

VDD12_PCIE

CE49

CC49

CA60

CA55

CC62

CC53

CE60

CE55

CC47

BW55

PP0V9_SOC_FIXED_PCIE_REFBUF

C0804

1

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

R0803

0.00

0%

1/32W

MF

01005

ROOM=SOC

VDD_FIXED_PCIE_xxx:0.855-0.990V @225mA MAX

PP0V9_SOC_FIXED

18 15 10 9 7

D

1

C0803

1

21

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

C0800

1

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=SOC

C0806

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

C

17

17

17

17

17

17

PCIE LINK 0

17

17

29 25 18 17 16 13 12 11 9 7 5

PCIE_NAND_BI_AP_CLKREQ_L

PP1V8

1

R0805

100K

5%
1/32W
MF
01005

2

ROOM=SOC

52 48 47 46 39

90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_AP_TO_NAND_REFCLK_N

#24557655:replace with 20% caps. SI no negative impact

GND_VOID=TRUE

21

C0807

ROOM=SOC

90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_NAND_TO_AP_RXD_N 90_PCIE_NAND_TO_AP_RXD_C_N

D10 NAND is now Gen3 (was Gen2). Caps intentionally 0.22uF

90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_NAND_TXD_N

PCIE_AP_TO_NAND_RESET_L

C0808

ROOM=SOC

C0809

ROOM=SOC

C0810

ROOM=SOC

20%
X5R 01005

20%
X5R

20%
X5R

20%
X5R

6.3V

GND_VOID=TRUE

21

6.3V
01005

GND_VOID=TRUE

21

6.3V
01005

21

GND_VOID=TRUE

6.3V
01005

0.22UF

0.22UF

0.22UF

0.22UF

90_PCIE_NAND_TO_AP_RXD_C_P

90_PCIE_AP_TO_NAND_TXD_C_P
90_PCIE_AP_TO_NAND_TXD_C_N

BC64

CJ48

CK48

CM46

CL46

CK44

CJ44

BJ65

PCIE_CLKREQ0*

PCIE_REF_CLK0_P
PCIE_REF_CLK0_N

PCIE_RX0_P
PCIE_RX0_N

PCIE_TX0_P
PCIE_TX0_N

PCIE_PERST0*

VDD12_PCIE_REFBUF

VDD_FIXED_PCIE_CLK

VDD_FIXED_PCIE_ANA

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 2 OF 16

VDD_FIXED_PCIE_REFBUF

PCIE_CLKREQ3*

PCIE_REF_CLK3_P

PCIE_REF_CLK3_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_TX3_P

PCIE_TX3_N

PCIE_PERST3*

BE66

CL64
CM64

CM61
CL61

CK63
CJ63

BJ66

PCIE_WLAN_BI_AP_CLKREQ_L

90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N

90_AP_PCIE3_RXD_C_P
90_AP_PCIE3_RXD_C_N

90_AP_PCIE3_TXD_C_P
90_AP_PCIE3_TXD_C_N

52

52

52

52

52

52

52

PCIE_AP_TO_WLAN_RESET_L

52

C

PCIE LINK 3PCIE LINK 2

B

PCIE LINK 1

1

R0802

100K

5%
1/32W
MF
01005

2

ROOM=SOC

LINK 1 USED ON AP_DEV ONLY

NC

NC

NC

NC

NC

NC

NC

NC

CL54

CM54

CK52

CJ52

CM50

CL50

CH57

CG57

PCIE_CLKREQ1*

PCIE_REF_CLK1_P
PCIE_REF_CLK1_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_PERST1*

PCIE_EXT_REF_CLK_P
PCIE_EXT_REF_CLK_N

LINK1

LINK3LINK0

LINK2

PCIE_CLKREQ2*

PCIE_REF_CLK2_P
PCIE_REF_CLK2_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_TX2_P

PCIE_TX2_N

PCIE_PERST2*

BE65BG66

CK59
CJ59

CK56
CJ56

CM57
CL57

BE64BG64

PCIE_BB_BI_AP_CLKREQ_L

90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N

WLAN RX PP's are now managed on Page 52

90_AP_PCIE2_RXD_C_P
90_AP_PCIE2_RXD_C_N

90_AP_PCIE2_TXD_C_P
90_AP_PCIE2_TXD_C_N

52

52

52

52

52

52

52

1

R0806

100K

5%
1/32W
MF
01005

2

ROOM=SOC

PCIE_AP_TO_BB_RESET_L

1

R0801

100K

5%
1/32W
MF
01005

ROOM=SOC

2

B

52

A

PCIE_REXT

CG63

AP_PCIE_RCAL

1

R0800

3.01K

1%
1/32W
MF
01005

2

ROOM=SOC

SYNC_MASTER=Sync

PAGE TITLE

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Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

SOC - MIPI & ISP INTERFACES

34567 8

2 1

D

0.825-0.94V @25mA MAX

18 15 10 8 7

90_MIPI_NH_TO_AP_DATA0_P

45

45

90_MIPI_NH_TO_AP_DATA0_N

PP0V9_SOC_FIXED

1

2

C0902

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=SOC

1

C0900

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

A18

MIPI0C_DPDATA0

B18

MIPI0C_DNDATA0

G6

G17

G13

VDD_FIXED_MIPI

G10

G15

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 3 OF 16

G21

G19

VDD18_MIPI

ISP_I2C0_SCL

ISP_I2C0_SDA

1.62-1.98V @7mA MAX

1

2

N65
N66

1

C0901

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

I2C_ISP_UT_SCL
I2C_ISP_UT_SDA

PP1V8

C0903

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=SOC

48

48

D

52 48 47 46 39

29 25 18 17 16 13 12 11 8 7 5

C

R0900

4.02K

1/32W

01005

ROOM=SOC

D11/111 ONLY

1%

MF

U64
R65

U65
U66

W64
W66

AA64

B50
A48
C48

A50
E50
AA65
AE64
AC65

I2C_ISP_NV_SCL
I2C_ISP_NV_SDA

I2C_ISP_NH_SCL
I2C_ISP_NH_SDA

NC
NC

NC

Dev ONLY

Spare

AP_TO_UT_CLK_R
NC_AP_TO_NV_CLK_R

AP_TO_NH_CLK_R

AP_TO_UT_SHUTDOWN_L
NC_AP_TO_NV_SHUTDOWN_L
AP_TO_NH_SHUTDOWN_L

TP_SENSOR3_RST

NC

46

46

48

48

25

29

D11/111 ONLY

D11/111 ONLY

1

PP

PP0902

SM

P2MM-NSM

ROOM=SOC

R0906

33.2

1/32W

01005

ROOM=SOC

1%

MF

21

NOSTUFF

1

C0906

100PF

5%
35V

2

NP0-C0G
01005

R0907

33.2

1/32W

01005

ROOM=SOC

Radar 20511449

<--- Needed for Cayman debug; this pin cannot be input

1%

MF

21

NOSTUFF

1

C0907

100PF

5%
35V

2

NP0-C0G
01005

AP_TO_UT_CLK

AP_TO_NH_CLK

C

25

29

NC
NC

NC
NC

B20

MIPI0C_DPDATA1

C20

MIPI0C_DNDATA1

C24

MIPI0C_DPDATA2

B24

MIPI0C_DNDATA2

A26

MIPI0C_DPDATA3

B26

MIPI0C_DNDATA3

B22

MIPI0C_DPCLK

A22

MIPI0C_DNCLK

E24

MIPI0C_REXT

B4

MIPID_DPDATA0

A4

MIPID_DNDATA0

B5

MIPID_DPDATA1

C5

MIPID_DNDATA1

C9

MIPID_DPDATA2

B9

MIPID_DNDATA2

A11

MIPID_DPDATA3

B11

MIPID_DNDATA3

45

90_MIPI_NH_TO_AP_DATA1_P

45

90_MIPI_NH_TO_AP_DATA1_N

45

90_MIPI_NH_TO_AP_CLK_P

45

90_MIPI_NH_TO_AP_CLK_N

MIPI0C_REXT

1

39

90_MIPI_AP_TO_LCM_DATA0_P

39

2

90_MIPI_AP_TO_LCM_DATA0_N

39

90_MIPI_AP_TO_LCM_DATA1_P

39

90_MIPI_AP_TO_LCM_DATA1_N

NC_MIPI_AP_TO_LCM_DATA2_P
NC_MIPI_AP_TO_LCM_DATA2_N

NC_MIPI_AP_TO_LCM_DATA3_P
NC_MIPI_AP_TO_LCM_DATA3_N

ISP_I2C1_SCL

ISP_I2C1_SDA

ISP_I2C2_SCL

ISP_I2C2_SDA

ISP_I2C3_SCL

ISP_I2C3_SDA

SENSOR_INT

SENSOR0_CLK
SENSOR1_CLK
SENSOR2_CLK

SENSOR0_RST
SENSOR1_RST
SENSOR2_RST
SENSOR3_RST
SENSOR4_RST

B

39

90_MIPI_AP_TO_LCM_CLK_P

39

90_MIPI_AP_TO_LCM_CLK_N

26

AP_TO_STROBE_DRIVER_HWEN

36

SPI_AP_TO_MAGGIE_CS_L

1%

1/32W

MF

01005

1

2

R0901

4.02K

ROOM=SOC

MIPID_REXT

NC

B7

MIPID_DPCLK

A7

MIPID_DNCLK

BN4

DISP_TOUCH_BSYNC0

BR2

DISP_TOUCH_BSYNC1

BR4

DISP_TOUCH_EB

E11

MIPID_REXT

SENSOR0_ISTRB
SENSOR1_ISTRB

SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN

MIPI1C_REXT

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK

MIPI1C_DNCLK

E52
D50

C50
B48

E16

B12
C12

B16
C16

B14
A14

NC_SENSOR0_ISTRB

NC

NC

AP_TO_MUON_BL_STROBE_EN

Per Radar 21221938

37

B

Dev only

A

28 27 26 25 23 21 19 18 10 4
52 46 41 40 39 37 35 34 33 31

53

8 7 5 4 2 1

PP_VDD_MAIN

1

C0904

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

AC return path for LCM MIPI which is referenced to GND and VDD_MAIN
Radar 21203307

1

C0905

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0908

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0909

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0910

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

A

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

36

D

34567 8

2 1

D

PP1V2_SOC

1

C1013

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

VDD12_PLL_LPDP:1.14-1.26V @3mA MAX
VDD12_LPDP:1.14-1.26V @60mA MAX

1

C1001

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1004

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1005

0.01UF

10%

6.3V

2

X5R
01005

ROOM=SOC

90_LPDP_UT_TO_AP_D0_P

25

90_LPDP_UT_TO_AP_D0_N

25

1

C1002

15PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

Desense for Wifi frequencies

CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND

CAYMAN-2GB-20NM-DDR-M

A54

LPDPRX_RX_D0_P

B54

LPDPRX_RX_D0_N

G30

G28

G25

G55

VDD12_LPDP_TX

U0700

SYM 4 OF 16

G23

G62

G60

G58

VDD12_LPDP_RX

CSP

VDD12_PLL_LPDP

LPDP_TX0P

LPDP_TX0N

B27
C27

NC

NC

D

Dev ONLY

C

LPDP Lanes swapped between D10 and D11

D11/111 ONLY

D11/111 ONLY

90_LPDP_UT_TO_AP_D1_P

25

90_LPDP_UT_TO_AP_D1_N

25

NC_90_LPDP_NV_TO_AP_D2_P

46

NC_90_LPDP_NV_TO_AP_D2_N

46

NC_90_LPDP_NV_TO_AP_D3_P

46

NC_90_LPDP_NV_TO_AP_D3_N

46

GND ON MLB; other on Dev

LPDP_UT_BI_AP_AUX

25

NC_AP_LPDP_AUX2

46

NC

NC

NC

B56

LPDPRX_RX_D1_P

C56

LPDPRX_RX_D1_N

A61

LPDPRX_RX_D2_P

B61

LPDPRX_RX_D2_N

B63

LPDPRX_RX_D3_P

C63

LPDPRX_RX_D3_N

A64

LPDPRX_RX_D4_P

B64

LPDPRX_RX_D4_N

D54

LPDPRX_AUX_D0_P

E56

LPDPRX_AUX_D1_P

D61

LPDPRX_AUX_D2_P

E63

LPDPRX_AUX_D3_P

D64

LPDPRX_AUX_D4_P

LPDP_TX1P

LPDP_TX1N

LPDP_TX2P

LPDP_TX2N

LPDP_TX3P

LPDP_TX3N

LPDP_AUX_P
LPDP_AUX_N

LPDP_CAL_DRV_OUT

LPDP_CAL_VSS_EXT

A29
B29

B31
C31

A33
B33

D33
E33

E35
E31

NC

NC

C

NC

NC

NC

NC

NC

NC

NC

B

18 15 9 8 7

R1001

300

1%

1/32W

MF

01005-1

ROOM=SOC

C1006

100PF

5%

16V

NP0-C0G

01005

ROOM=SOC

GND ON MLB; other on Dev

PP0V9_SOC_FIXED

1

2

AP_LPDPRX_RCAL_NEG

1

2

#24401637:Unconnect LPDPRX_EXT_C

NC

B59

LPDPRX_BYP_CLK_P

C59

LPDPRX_BYP_CLK_N

A57

LPDPRX_RCAL_P

B57

LPDPRX_RCAL_N

D57

LPDPRX_EXT_C

EDP_HPD

DP_WAKEUP

BN3
AP2

NC

NC

Reserved for PanelID[1:0] on ap_dev board
Reserved for PanelID[1:0] on ap_dev board

B

A

28 27 26 25 23 21 19 18 9 4

52 46 41 40 39 37 35 34 33 31

8 7 5 4 2 1

53

PP_VDD_MAIN

1

C1010

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

AC return path for LCM LPDP which is referenced to GND and VDD_MAIN

1

C1011

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

SYNC_MASTER=Sync

PAGE TITLE

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DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - SERIAL INTERFACES

34567 8

2 1

D

I2S_AP_TO_CODEC_MCLK

32

32

32

32

32

R1103

33.2

1%

1/32W

MF

MF

01005

ROOM=SOC

D

21

I2S_AP_TO_CODEC_MCLK_R
I2S_AP_TO_CODEC_MSP_BCLK

32

32

32

32

32

I2S_AP_TO_CODEC_MSP_LRCLK

32

32

32

32

32

I2S_CODEC_TO_AP_MSP_DIN

32

32

32

32

32

I2S_AP_TO_CODEC_MSP_DOUT

32

32

32

32

32

BV65

BY66
BU64
BR64
BU65

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

U0700

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CSP

CSP

CSP

CSP

CSP

SYM 6 OF 16

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

36 35 34 33 32

35 34 33 32

35 34 33 32

35 34 33 32

34 33 32

36 35 34 33 32

36 35 34 33 32

35 34 33 32

34 33 32

34 33 32

36

36

36

36

36

36

36

36

36

36

I2S1/2/3 MCLK NC #24559456

I2S_AP_TO_BT_BCLK
I2S_AP_TO_BT_LRCLK
I2S_BT_TO_AP_DIN
I2S_AP_TO_BT_DOUT

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
I2S_MAGGIE_TO_AP_DIN
I2S_AP_TO_MAGGIE_DOUT

NC

NC

D48
E48
A46
C46
E46

BU66
BR66
BN64
BN65

BJ64

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

I2C2_SDA

I2C3_SCL

I2C3_SDA

CK7
CG12

AG64
AG66

U3
U4

AE66
AE65

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

C

B

SPI_AP_TO_CODEC_MAGGIE_SCLK

36 32

36 32

36 32

36 32

36 32

Route as daisy-chain. No T's allowed.

SPI_AP_TO_TOUCH_SCLK

39

39

39

39

39

R1116

0.00

0.00

0.00

0.00

0.00

0%

0%

0%

0%

0%

1/32W

1/32W

1/32W

1/32W

1/32W

MF

MF

MF

MF

MF

01005

01005

01005

01005

01005

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

R1101

0.00

0.00

0.00

0.00

0.00

0%

0%

0%

0%

0%

1/32W

1/32W

1/32W

1/32W

1/32W

MF

MF

MF

MF

MF

01005

01005

01005

01005

01005

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

I2S_BB_TO_AP_BCLK

53

53

53

53

53

I2S_BB_TO_AP_LRCLK

53

53

53

53

53

I2S_BB_TO_AP_DIN

53

53

53

53

53

I2S_AP_TO_BB_DOUT

53

53

53

53

53

NC

CH11

CM7

CK9

CG18

CJ9

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

SPI4_SCLK

SPI4_MISO
SPI4_MOSI

I2C5_SCL

I2C5_SDA

CB2
BY4
BY3
CB4

N2
N3
N4
R3

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

BOARD_ID2

5

5

5

5

5

BOARD_ID1

5

5

5

5

5

BOARD_ID0

PP1V8

5

SPI_CODEC_MAGGIE_TO_AP_MISO

36 32

36 32

36 32

36 32

36 32

SPI_AP_TO_CODEC_MAGGIE_MOSI

36 32

36 32

36 32

36 32

36 32

21

SPI_AP_TO_CODEC_MAGGIE_SCLK_R
SPI_AP_TO_CODEC_CS_L

32

32

32

32

32

NC

GPIO_42
GPIO_43

PMU_SCLK
PMU_MISO
PMU_MOSI

DWI_CLK

C44
B44
A44
D44

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI_TOUCH_TO_AP_MISO

39

39

39

39

39

SPI_AP_TO_TOUCH_MOSI

39

39

39

39

39

21

SPI_AP_TO_TOUCH_SCLK_R
SPI_AP_TO_TOUCH_CS_L

39

39

39

39

39

DWI_DO

DROOP

GPU_TRIGGER

SOCHOT

B42
A42
E44
C42

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

CLK32K_OUT

NAND_SYS_CLK

SPI_MESA_TO_AP_MISO

38

38

38

38

38

SPI_AP_TO_MESA_MOSI

38

38

38

38

38

SPI_AP_TO_MESA_SCLK

38

38

38

38

38

MESA_TO_AP_INT

38

38

38

38

38

CJ12

NC

CG22

NC

CM9

NC

CH16
CJ14

CH20

NC

CH22

NC

AH65

SPI_PMGR_TO_PMU_SCLK

AH66

SPI_PMU_TO_PMGR_MISO

AK64

SPI_PMGR_TO_PMU_MOSI

AK65

DWI_PMGR_TO_BACKLIGHT_CLK

AM64

DWI_PMGR_TO_BACKLIGHT_DATA

I2C5_SCL
I2C5_SDA

AE3
BY2

AG4

AM66

AP_TO_CUMULUS_CLK32K

BN66

AP_TO_NAND_SYS_CLK_R

R1118

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

37

37

37

37

37

37

37

37

37

37

39

39

39

39

39

0.00

0.00

0.00

0.00

0.00

0%

0%

0%

0%

0%

1/32W

1/32W

1/32W

1/32W

1/32W

MF

MF

MF

MF

MF

01005

01005

01005

01005

01005

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

C

47 11

47 11

47 11

47 11

47 11

47 11

47 11

47 11

47 11

47 11

1

R1113

10K

10K

10K

10K

10K

5%

5%

5%

5%

5%
1/32W

1/32W

1/32W

1/32W

1/32W
MF

MF

MF

MF

MF
01005

01005

01005

01005

01005

2

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

PP1V8

1

R1114

10K

10K

10K

10K

10K

5%

5%

5%

5%

5%
1/32W

1/32W

1/32W

1/32W

1/32W
MF

MF

MF

MF

MF
01005

01005

01005

01005

01005

2

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

PMU_TO_AP_PRE_UVLO_L
PMU_TO_AP_THROTTLE_GPU_L

AP_TO_PMU_SOCHOT_L

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

29 25 18 17 16 13 12 11 9 8 7 5

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

B

21

AP_TO_NAND_SYS_CLK

17

17

17

17

17

A

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

52 48 47 46 39 29

52 48 47 46 39 29

52 48 47 46 39 29

52 48 47 46 39 29

PP1V8

I2C5

See Radar#25316444 for Details

1

C1101

1.0UF

1.0UF

1.0UF

1.0UF

1.0UF

20%

20%

6.3V

6.3V

2

X5R

X5R
0201-1

0201-1

0201-1

ROOM=SOC

ROOM=SOC

VCC

U1101

WLCSP

WLCSP

WLCSP

WLCSP

WLCSP

VSS

ROOM=SOC

CRITICAL

CRITICAL

CRITICAL

B2 A1

I2S_AP_TO_CODEC_MCLK

A2B1

SDASCL

I2C5_SDA
I2C5_SCL

I2S_AP_TO_CODEC_MCLK_R
I2S_AP_TO_CODEC_MSP_BCLK
I2S_AP_TO_CODEC_MSP_LRCLK
I2S_CODEC_TO_AP_MSP_DIN
I2S_AP_TO_CODEC_MSP_DOUT

47 11

47 11

47

47

I2S_AP_TO_BT_LRCLK
I2S_BT_TO_AP_DIN

I2S_AP_TO_BT_LRCLK

47 11

47 11

47 11

47 11

47 11
I2S_AP_TO_BT_LRCLK
I2S_BT_TO_AP_DIN
I2S_AP_TO_BT_DOUT
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_DIN
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
I2S_AP_TO_MAGGIE_DOUT

I2S_MAGGIE_TO_AP_DIN
I2S_AP_TO_MAGGIE_DOUT
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_DIN
I2S_AP_TO_BB_DOUT

BOARD_ID2
BOARD_ID2
BOARD_ID2
BOARD_ID2

To Cayman

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

I2C5_SCL
I2C5_SCL

I2C5_SDA
I2C5_SDA

I2C5_SCL
I2C5_SCL

I2C5_SDA
I2C5_SDA

SYNC_MASTER=Sync

PAGE TITLE

spare

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

34567 8

2 1

D

C

B

36

36

36

36

29 25 18 17 16 13 11 9 8 7 5

29 25 18 17 16 13 11 9 8 7 5

29 25 18 17 16 13 11 9 8 7 5

29 25 18 17 16 13 11 9 8 7 5

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

52 48 47 46 39

20

20

20

20

#24557547:Delete R1204

MAGGIE_TO_AP_CDONE

PP1V8

Nostuff per #24511702

PMU_TO_AP_THROTTLE_CPU_L

D101/D111 ONLY

D101/D111 ONLY

D101/D111 ONLY

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

1

R1210

10K

10K

10K

10K

5%

5%

5%

5%
1/32W

1/32W

1/32W

1/32W
MF

MF

MF

MF
01005

01005

01005

01005

2

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

D10/D11 ONLY

Dev only

SOC - GPIO INTERFACES

AP_TO_ACC_BUCK_VSEL

27

27

27

27

AP_TO_MAGGIE_CRESETB_L

36

36

36

36

BUTTON_VOL_UP_L

44 20

44 20

44 20

44 20

DEV ONLY

AP_TO_BB_RESET_L

53

53

53

53

RESERVERD FOR SSHB ID ON DEV BOARD

NC_AP_TO_BB_IPC_GPIO2

NC_AP_TO_BB_IPC_GPIO2

NC_AP_TO_BB_IPC_GPIO2

NC_AP_TO_BB_IPC_GPIO2
NC_AP_TO_GNSS_WAKE

NC_AP_TO_GNSS_WAKE

NC_AP_TO_GNSS_WAKE

NC_AP_TO_GNSS_WAKE

53

53

53

53

AP_TO_BB_TIME_MARK
NC_AP_TO_GNSS_TIME_MARK

BB_TO_AP_RESET_DETECT_L

53

53

53

53

AP_TO_SPKAMP2_RESET_L

33

33

33

33

ALS_TO_AP_INT_L

29

29

29

29

53

53

53

53

AP_TO_NFC_FW_DWLD_REQ

AP_TO_NAND_FW_STRAP

17

17

17

17

TOUCH_TO_AP_INT_L

39

39

39

39

AP_TO_BBPMU_RADIO_ON_L

53

53

53

53

53

AP_TO_ICEFALL_FW_DWLD_REQ

AP_TO_LCM_RESET_L

39

39

39

39

AP_BI_HOMER_BOOTLOADER_ALIVE

36

36

36

36

PMU_TO_AP_FORCE_DFU

20 4

20 4

20 4

20 4

NC_DFU_STATUS

5

PP1V8

53

53

53

53

AP_TO_NFC_DEV_WAKE

PMU_TO_AP_BUF_RINGER_A

20

20

20

20

AP_TO_BT_WAKE

53

53

53

53

AP_TO_WLAN_DEVICE_WAKE

53

53

53

53

BOARD_REV3

5

5

5

5

BOARD_REV2

5

5

5

5

BOARD_REV1

5

5

5

5

BOARD_REV0

5

5

5

5

AP_TO_TOUCH_MAMBA_RESET_L

39

39

39

39

AP_TO_BB_MESA_ON

53

53

53

53

AP_TO_BB_COREDUMP

53

53

53

53

53

53

53

53

AP_TO_BB_IPC_GPIO1

BOOT_CONFIG0

#24608280

BOOT_CONFIG1

BOARD_ID4

NC

NC

NC

NC

NC

NC

BB64
BC65
BB66
AY65
AY66
AV65
AV67

AT67
AT66

AT64
AP66
AP65
AH64

AE4
AC3
AE2
BB2
BB4
BC3
BC4
BE2
BE4
BE3
BG2

CJ11

CL9
CH14
CK11
CG20

AA2
AA3

D42

E42

A41

C41

E41

A39

AT4

AT2

AV3
AY2
AY3

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41

U0700

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CAYMAN-2GB-20NM-DDR-M

CSP

CSP

CSP

CSP

SYM 5 OF 16

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART0_RXD

UART0_TXD

UART1_CTS*
UART1_RTS*

UART1_RXD

UART1_TXD

UART2_CTS*
UART2_RTS*

UART2_RXD

UART2_TXD

UART3_CTS*
UART3_RTS*

UART3_RXD

UART3_TXD

UART4_CTS*
UART4_RTS*

UART4_RXD

UART4_TXD

UART5_RTXD

UART6_RXD

UART6_TXD

UART7_RXD

UART7_TXD

AG2
AH4
AH3

CL5
CJ7

E39
D39
C39
B39

AM4
AK3
AK4
AH2

AA4
W2
W4
U2

D37
C37
B37
A37

BG4

CG16
CG14

AP3
AM2

NC

PROX_BI_AP_AOP_INT_PWM_L
NC_BB_TO_AP_RESET_ACT_L

UART_AP_DEBUG_RXD
UART_AP_DEBUG_TXD

UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_RTS_L

UART_AP_TO_BT_RTS_L
UART_BT_TO_AP_RXD

UART_BT_TO_AP_RXD
UART_AP_TO_BT_TXD

NC_AP_UART2_CTS_L
NC_AP_UART2_RTS_L
NC_AP_UART2_RXD

NC_AP_UART2_RXD
NC_AP_UART2_TXD

NC_AP_UART2_TXD

NC_AP_UART2_TXD

NC_AP_UART2_TXD

UART_NFC_TO_AP_CTS_L

UART_NFC_TO_AP_CTS_L

UART_NFC_TO_AP_CTS_L

UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L

UART_AP_TO_NFC_RTS_L

UART_AP_TO_NFC_RTS_L

UART_AP_TO_NFC_RTS_L
UART_NFC_TO_AP_RXD

UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_TXD

UART_WLAN_TO_AP_CTS_L

UART_WLAN_TO_AP_CTS_L
UART_AP_TO_WLAN_RTS_L

UART_AP_TO_WLAN_RTS_L
UART_WLAN_TO_AP_RXD

UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD

UART_AP_TO_WLAN_TXD

SWI_AP_BI_TIGRIS

SWI_AP_BI_TIGRIS

UART_ACCESSORY_TO_AP_RXD

UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_ACCESSORY_TXD

UART_AP_TO_ACCESSORY_TXD

UART_HOMER_TO_AP_RXD

UART_HOMER_TO_AP_RXD
UART_AP_TO_HOMER_TXD

UART_AP_TO_HOMER_TXD

29 13

29 13

29 13

29 13

40

40

40

40

40

40

40

40

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53
UART_AP_TO_BT_RTS_L
53

53

53

53

53

53

53

53

53

53

53

53
NC_AP_UART2_RXD

NC_AP_UART2_RXD

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

21

21

21

21

40

40

40

40

40

40

40

40

36

36

36

36

36

36

36

36

D

D101/D111 ONLY

C

D101/D111 ONLY; for GNSS

B

A

PMU_TO_AP_BUF_POWER_KEY_L

20

20

20

20

PMU_TO_AP_BUF_VOL_DOWN_L

20

20

20

20

#25120460:REQUEST_DFU Assignment

BU2
BU3

REQUEST_DFU1
REQUEST_DFU2

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=05/17/2016

A

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SOC - AOP

34567 8

2 1

D

C

#24512059: Remove R1300 PU

Use internal pullup in SOC (AOP side).

Internal pullup in AOP. Radar 21210869

20

20 15

24

24

29 12

24

24

24

24

53 39 23 20

40

36

24

24

24

35 34 33 32

48

20

AOP_TO_PMU_SLEEP1_REQUEST

PMU_TO_AOP_SLEEP1_READY

SPI_AOP_TO_COMPASS_CS_L
COMPASS_TO_AOP_INT
PROX_BI_AP_AOP_INT_PWM_L
ACCEL_GYRO_TO_AOP_DATARDY
SPI_AOP_TO_ACCEL_GYRO_CS_L
ACCEL_GYRO_TO_AOP_INT
SPI_AOP_TO_PHOSPHORUS_CS_L
LCM_TO_MANY_BSYNC
TRISTAR_TO_AOP_INT
AOP_TO_MAGGIE_EN

PHOSPHORUS_TO_AOP_INT_L
SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L

BOT_ACCEL_GYRO_TO_AOP_DATARDY

AUDIO_TO_AOP_INT_L

AOP_TO_MESA_I2C_ISO_EN

PMU_TO_AOP_IRQ_L

CM16
CM29

CK12
CK16
CK18

CJ29

CG31

CH31
CK20

CJ31
CK27
CK24
CK29
CK22

CM12

CK31

CG33

CJ33

CAYMAN-2GB-20NM-DDR-M

AOP_DDR_REQ
AOP_DDR_RESET*

AOP_FUNC_0
AOP_FUNC_1
AOP_FUNC_2
AOP_FUNC_3
AOP_FUNC_4
AOP_FUNC_5
AOP_FUNC_6
AOP_FUNC_7
AOP_FUNC_8
AOP_FUNC_9
AOP_FUNC_10
AOP_FUNC_11
AOP_FUNC_12
AOP_FUNC_13
AOP_FUNC_14
AOP_FUNC_15

U0700

CSP

SYM 7 OF 16

CFSB_AOP

AWAKE_REQ

AWAKE_RESET*

AOP_PDM_CLK0
AOP_PDM_DATA0
AOP_PDM_DATA1

RT_CLK32768

AOP_SWD_TCK_OUT

AOP_SWD_TMS0
AOP_SWD_TMS1

SWD_TMS2
SWD_TMS3

CH35

CM31
CJ37

CM37
CH41
CK39

CM33

CL14

CL16
CG35
BU4
BV3

PP1V8

NOSTUFF

1

R1304

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

PMU_TO_SYSTEM_COLD_RESET_L

AOP_TO_PMU_ACTIVE_REQUEST
PMU_TO_AOP_TRISTAR_ACTIVE_READY

AOP_TO_MESA_BLANKING_EN

AOP_TO_WLAN_CONTEXT_B
AOP_TO_WLAN_CONTEXT_A

PMU_TO_AOP_CLK32K

SWD_AP_TO_MANY_SWCLK

HOMER_TO_AOP_WAKE_INT
SWD_AOP_BI_BB_SWDIO
SWD_AP_BI_NAND_SWDIO
SWD_AP_BI_HOMER_SWDIO

D

52 48 47 46

39 29 25 18 17 16 12 11 9 8 7 5

20 7

20

40 37 20 7

38

53

53

20

C

36

53

17

36

53 36 17

BB_SWDIO has pullup in Radio_MLB pages

B

#25756894:North Carbon R1 (+Mg,P)

#25756894:South Carbon R2

24

SPI_AOP_TO_IMU_SCLK_R1

24

SPI_AOP_TO_IMU_SCLK_R2

36 35 34 33

I2S_AOP_TO_MAGGIE_L26_MCLK

R1305

49.9

21

1%

1/32W

MF

01005

ROOM=SOC

R1306

49.9

21

1%

1/32W

MF

01005

ROOM=SOC

I2C_AOP_SCL

48

I2C_AOP_SDA

48

SPI_IMU_TO_AOP_MISO

24

SPI_AOP_TO_IMU_MOSI

24

SPI_AOP_TO_IMU_SCLK

UART_BB_TO_AOP_RXD

53

UART_AOP_TO_BB_TXD

53

MAGGIE_TO_AOP_INT

36

UART_AOP_TO_MAGGIE_TXD

36

UART_TOUCH_TO_AOP_RXD

39

39

UART_AOP_TO_TOUCH_TXD

I2S_CODEC_XSP_TO_AOP_BCLK

R1303

33.2

1%

1/32W

MF

01005

ROOM=SOC

21

32

32

I2S_CODEC_XSP_TO_AOP_DIN
I2S_AOP_TO_MAGGIE_L26_MCLK_R
I2S_CODEC_XSP_TO_AOP_LRCLK

32

I2S_AOP_TO_CODEC_XSP_DOUT

32

CM11

CJ24

CJ18
CJ27
CJ16

CK14

CJ20

CJ22

CL11

CG29
CH29

CL35
CJ39

CM35

CK37

CG39

AOP_I2C0_SCL
AOP_I2C0_SDA

AOP_SPI_MISO
AOP_SPI_MOSI
AOP_SPI_SCLK

AOP_UART0_RXD
AOP_UART0_TXD

AOP_UART1_RXD
AOP_UART1_TXD

AOP_UART2_RXD
AOP_UART2_TXD

AOP_I2S_BCLK
AOP_I2S_DIN
AOP_I2S_MCK
AOP_I2S_LRCK

AOP_I2S_DOUT

DOCK_ATTENTION

DOCK_CONNECT

CG41

CL37

AOP_TO_SPKAMP1_ARC_RESET_L

MESA_TO_AOP_FDINT

35 34

38

DOCK_CONNECT can be GPIO, but input only. Radar 21680759

B

A

SYNC_MASTER=Sync

PAGE TITLE

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DRAWING NUMBER SIZE

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - CPU, GPU & SOC RAILS

34567 8

2 1

D

C

B

PP_CPU_VAR

1.06V @17.4A MAX

0.9V @tbd A MAX

0.625V @tbd A MAX

1

C1401

15UF

20%

6.3V

2

X5R
0402-1

ROOM=SOC

C1404

7.5UF

20%

4V

CERM CERM

1

432

ROOM=SOC

C1405

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1406

0.47UF

20%

6.3V
CERM
0402

1

432

1

2

C1411

7.5UF

1

ROOM=SOC

C1412

4.3UF

1

C1413

1

1.06V @1.0A MAX

0.80V @TBDA MAX

PP_CPU_SRAM_VAR

18

ROOM=SOC

C1407

7.5UF

20%

4V
CERM
0402

1

1.03V @1.44A MAX

0.92V @1.50A MAX

0.80V @TBD A MAX

PP_GPU_SRAM_VAR

18

3

4

2

18 14

C1408

15UF

20%

6.3V
X5R

0402-1

ROOM=SOC

20%

4V

0402

432

20%

4V

CERM
0402

432

ROOM=SOC

0.47UF

20%

6.3V
CERM
0402

432

ROOM=SOC

C1435

7.5UF

20%

4V

CER

0402

1

2

ROOM=SOC

C1439

7.5UF

20%

4V

CER

0402

1

3

4

1

C1434

15UF

20%

6.3V

2

X5R
0402-1

ROOM=SOC

C1417

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1418

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1419

0.47UF

20%

6.3V
CERM
0402

1

432

ROOM=SOC

C1433

7.5UF

20%

4V
CERM
0402

1

ROOM=SOC

C1437

7.5UF

20%

4V
CERM
0402

1

ROOM=SOC

C1422

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1423

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1424

0.47UF

20%

6.3V
CERM
0402

1

432

BUCK0_PP_CPU_FB

18

1

C1458

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

432

1

C1459

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

1

C1449

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

ROOM=SOC

C1427

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1428

1UF 1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1460

7.5UF

20%

4V
CERM
0402

1

432

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

ROOM=SOC

C1430

4.3UF

1

ROOM=SOC

C1431

1

ROOM=SOC

C1461

7.5UF

1

XW1402

21

ROOM=SOC

20%

4V
CERM
04020402

20%

4V
CERM
0402

20%

4V
CERM
0402

OMIT

PP1401

P2MM-NSM

ROOM=SOC

SM

PP

1

PP_GPU_VAR

18 14

PP_SOC_VAR

18

0.80V @4.1A MAX

PP1402

P2MM-NSM

ROOM=SOC

XW1401

SHORT-20L-0.05MM-SM

AD10
AD15
AD19
AD23

AF13
AF17
AJ23
AL21

432

432

432

AL8
AN10
AN19
AN23
AR13
AR17
AR21
AU10
AU15

AW13
AW17
AW21

BA10
BA23
BD21

BD8
BF10
BF23

BH13
BH17
BH21
BK10
BK15

AJ10

AF8

AN15

AR8

AU19

AW8
BA15
BA19

BH8

AF43
AF47
AF51

P17
P21
P25
P30
P34
P38
P43
P47
P51
Y15
Y19
Y23
Y40
Y45
Y49
Y53

VDD_CPU

VDD_CPU_SRAM

VDD_GPU_SRAM

CAYMAN-2GB-20NM-DDR-M

U0700

CSP

SYM 8 OF 16

VDD_GPU

VDD_CPU_SENSE

VSS_CPU_SENSE

VDD_GPU_SENSE

VDD_SOC_SENSE

VSS_SENSE

AB13
AB17
AB21
AB25
AB43
AB47
AB51
AB55
AD40
AD45
AD49
AD53
AF55
AJ40
AJ49
AJ53
J25
J30
J38
J43
J47
J51
L15
L19
L23
L28
L32
L36
L40
L45
L49
L53
P13
T15
T36
T40
T53
V13
V25
V34
V38
V51
V55
Y28

BK23

BK21

TP_AP_VSS_CPU_SENSE

AJ45

AL47

TP_VDD_SOC_SENSE

AJ47

TP_VSS_SENSE

1

2

ROOM=SOC

C1402

4.3UF

20%

4V
CERM
0402

1

432

OMIT

NO_XNET_CONNECTION

C1414

15UF

20%

6.3V
X5R
0402-1

ROOM=SOC

ROOM=SOC

1

C1466

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

C1409

4.3UF

20%

4V
CERM
0402

1

432

SM

PP

21

1

1

1

1

1

1

1

C1448

2

ROOM=SOC

ROOM=SOC

C1452

4.3UF

20%

4V
CERM
0402

432

ROOM=SOC

C1410

1UF

20%

4V
CERM
0402

432

PP1403

SM

PP

PP

PP

P2MM-NSM

ROOM=SOC

PP1410

SM

P2MM-NSM

ROOM=SOC

PP1411

SM

P2MM-NSM

ROOM=SOC

PP_CPU_VAR

BUCK1_PP_GPU_FB

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

C1454

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

ROOM=SOC

C1416

7.5UF

1

C1415

1UF

20%

4V
CERM
0402

1

432

20%

4V
CERM
0402

432

ROOM=SOC

C1420

1UF

20%

4V
CERM
0402

1

432

AP_VDD_CPU_SENSE

SM

1

PP

AP_VDD_GPU_SENSE

SM

1

PP

18 14

18

ROOM=SOC

C1421

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC ROOM=SOC

C1425

0.47UF

20%

6.3V
CERM
0402

1

PP1408

P2MM-NSM

ROOM=SOC

PP1409

P2MM-NSM

ROOM=SOC

1

C1436

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

C1444

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

1.03V @12.9A MAX

0.92V @10.7A MAX

0.80V @TBD A MAX

0.67V @TBD A MAX

PP_GPU_VAR

ROOM=SOC

C1426

7.5UF

20%

4V
CERM
0402

1

432

C1429

0.47UF

20%

6.3V
CERM
0402

1

432

20

20

432

ROOM=SOC

C1432

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1456

0.47UF

6.3V
CERM
0402

1

20%

ROOM=SOC

C1457

0.47UF

20%

6.3V
CERM
0402

1

432

432

18 14

AD28
AD32
AF60

AJ28
AJ32
AJ36

AL6
AN28
AN32
AN36
AN40
AN45
AN49
AN53
AN58
AR25
AR30
AR34
AR38
AR43
AR47
AR51
AR55

AW30
AW34
AW38
AW43
AW47
AW51

|- - - |||||||- - |||==

AW55
AW60

BD25
BD30
BD34
BD38
BD43
BD47
BD51
BD55

BD6
BD60
BF28
BF32
BF36
BF45
BF49
BF53
BF58
BK28
BK32
BK36
BK40

CAYMAN-2GB-20NM-DDR-M

VDD_SOC

U0700

CSP

SYM 9 OF 16

C1403

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

ROOM=SOC

C1465

VDD_SOC

4.3UF

20%

4V
CERM
0402

1

432

BK45
BK49
BK53
BM55
BP15
BP19
BP23
BP28
BP32
BP36
BP40
BP45
BP49
BP53
BP58
BT13
BT17
BT21
BT25
BT30
BT34
BT38
BT43
BT47
BT51
BT55
BW10
CA13
CA17
CA21
CA25
CA30
CA34
CA38
CA43
CA47
CE13
CE17
CE45
J13
J21
J34
P55
T10
T60
V30
Y10
Y36
Y60
BF40
J60

AW25

OMIT

XW1403

SHORT-20L-0.05MM-SM

ROOM=SOC

NO_XNET_CONNECTION

0.67V @TBDA MAX

21

ROOM=SOC

C1438

1UF

CERM
0402

1

BUCK2_PP_SOC_FB

ROOM=SOC

C1440

20%

4V

432

7.5UF

20%

4V

CERM
0402

1

432

18

ROOM=SOC

C1442

0.47UF

20%

6.3V
CERM
0402

1

432

D

C

B

A

432

432

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - POWER SUPPLIES

34567 8

2 1

DDR IMPEDANCE CONTROL

D

C

B

18 10 9 8 7

TBD-TBDV @1.9A MAX

PP0V9_SOC_FIXED

ROOM=SOC

C1502

4.3UF

20%

4V
CERM
0402

1

432

C1501

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

ROOM=SOC

C1527

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1503

7.5UF

20%

CERM
0402

1

0.797-0.945V @9 mA MAX

0.765-0.840V @60mA MAX

PP0V8_AOP

19

1

2

4V

432

C1504

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

AB30
AB34
AB38

AD58

AF25
AF30
AF34
AF38
AF62

AJ58
AL25
AL30
AL34
AL38
AL43
AL51
AL55

AL60
AR60
AU28
AU32
AU36
AU40
AU45
AU49
AU53
AU58

AU6
BA28
BA32
BA36
BA40
BA45
BA49
BA53
BA58

BH25
BH30
BH34
BH38
BH43
BH47
BH51
BH55

BK58

AW23

CC36
CE30
CE40

1.06-1.17V @0.85A MAX

18 15 7

PP1V1

CAYMAN-2GB-20NM-DDR-M

VDD_FIXED

VDD_FIXED_CPU

VDD_LOW

1

C1506

10UF

20%

6.3V
CERM-X5R

2

0402-9

ROOM=SOC

U0700

CSP

SYM 10 OF 16

1

C1528

10UF

20%

6.3V
CERM-X5R

2

0402-9

ROOM=SOC

VDD_FIXED

BK6
BM13
BM17
BM21
BM25
BM30
BM34
BM38
BM43
BM47
BM51
BP10
BP60
BW15
BW19
BW23
BW28
BW32
BW36
BW40
BW45
BW49
BW53
BW58
BW8
CC10
CC15
CC19
CC23
CC28
CC32
CC45
G32
G36
J17
J23
J55
J62
L10
L58
L60
T32
T58
T8
Y58
Y8

1

C1518

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1519

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1514

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1522

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

BE1

BJ1

BL1

BM8

BP6

BT8

BW6

CA8
CC6
CD1
CH1

BE67

BH60

BJ67

BK62

BL67

BM60

BP62
BT60

BW62

CD67
CH67

AB8
AC1
AE1
AH1

E1
K1

L6
P8
T6
V8
Y6

AB60
AC67
AD62

AE67
AH67

E67
K67
P60
T62
V60
Y62

VDDIO11_DDR0

VDDIO11_DDR1

VDDIO11_DDR2

VDDIO11_DDR3

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 11 OF 16

VDDIO11_PLL_DDR0
VDDIO11_PLL_DDR1
VDDIO11_PLL_DDR2
VDDIO11_PLL_DDR3

VDDIO11_RET_DDR0
VDDIO11_RET_DDR1
VDDIO11_RET_DDR2
VDDIO11_RET_DDR3

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

VDD2

18 15 7

CD3
BY64
K3
K65

BN2
AA66

CF3
CB65
K4
K64

CE8
BW60
J8
P58

CG3
CD65
H4
H64

CF4
CB64
H3
H65

AM3
AM65
BB3
BB65
BR1
BR67
BV1
BV67
BY1
BY67
C2
C66
CJ2
CJ66
CK2
CK66
D2
D66
N1
N67
R1
R67
W1
W67

PP1V1

1

R1501

240

1%
1/32W
MF

2

01005

ROOM=SOC

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

PMU_TO_AOP_SLEEP1_READY

1.06 - 1.17V @4mA MAX

PP1V1_DDR_PLL

1

C1508

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

(CURRENT INCLUDED IN VDD2)

1

C1509

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

PP1V1_SDRAM

SYSTEM_ALIVE

1.06 - 1.17V @1.74A MAX

C1512

1

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

1

2

21 20 17

C1513

10UF

20%

6.3V
CERM-X5R
0402-9

ROOM=SOC

1

R1502

240

1%
1/32W
MF

2

01005

ROOM=SOC

1

C1523

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

C1507

1

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

19 18 15

1

R1503

240

1%
1/32W
MF

2

01005

ROOM=SOC

20 13

1

2

1

R1504

240

1%
1/32W
MF

2

01005

ROOM=SOC

FL1501

100OHM-25%-0.12A

01005

C1510

0.22UF

20%

6.3V
X5R
01005-1

ROOM=SOC

C1529

1

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

1

2

R1505

1

240

1%
1/32W
MF
01005

2

ROOM=SOC

21

1

2

PP1V1

PP1V1_SDRAM

C1511

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

1

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

R1506

240

1%
1/32W
MF
01005

ROOM=SOC

C1515

2.2UF

D

18 15 7

C

19 18 15

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

SOC - POWER SUPPLIES

34567 8

2 1

D

C

B

A12
A16

A2
A20
A24
A27
A31
A35

A5
A52
A56
A59
A63
A66

A9

AA1
AA67
AB10
AB15
AB19
AB23
AB28
AB32
AB36
AB40
AB45
AB49
AB53
AB58

AB6
AB62

AC2

AC4

AC64
AC66
AD13
AD17
AD21
AD25
AD30
AD34
AD43
AD47
AD51
AD55
AD60

AD8
AF10
AF15
AF19
AF23
AF28
AF32
AF36
AF40
AF45
AF49
AF53
AF58

AF6
AG1
AG3

AG65
AG67

AJ21
AJ25
AJ30
AJ34
AJ38
AJ43

AL10

AJ51
AJ55

AJ8
AK1
AK2

AK66
AK67

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 13 OF 16

VSS VSS

AL23
AL28
AL32
AL36
AL40
AL45
AL53
AL58
AL62
AN13
AN17
AN21
AN25
AN30
AN34
AN38
AN43
AN47
AN51
AN55
AN60
AN8
AP1
AP4
AP64
AP67
AR10
AR15
AR19
AR28
AR32
AR36
AR40
AR45
AR49
AR53
AR58
AR6
AR62
AT1
AT3
AT65
AU13
AU17
AU21
AU25
AU30
AU34
AU38
AU43
AU47
AU51
AU55
AU60
AU8
AV1
AV2
AV4
AV64
AV66
AW10
AW15
AW19
CH50
AW28
AW32
AW36

AW40

AW45
AW49
AW53
AW58
AW6
AW62
AY1
AY4
AY64
AY67

B1

B3
B35
B41
B46
B52
B65
B67

BA13
BA17
BA21
BA30
BA34
BA38
BA43
BA47
BA51
BA55
BA60

BA8
BC1
BC2

BC66
BC67
BD10
BD23
BD28
BD32
BD36
BD40
BD45
BD49
BD53
BD58
BD62

BF21
BF25
BF30
BF34
BF43
BF47
BF51
BF55

BF8
BG1
BG3

BG65
BG67
BH10
BH15
BH19
BH23
BH28
BH32
BH36
BH40
BH45
BH49
BH53
BH58

BH6

BH62

BK13
BK17

AL49
BK25
BK30
BK34
BK38
BK43
BK47
BK51
BK55
BK60

BK8

BL2
BL4

BL64

U0700

CSP

SYM 14 OF 16

VSS VSS

BL66
BM10
BM15
BM19
BM23
BM28
BM32
BM36
BM40
BM45
BM49
BM53
BM58
BM6
BM62
BN1
BN67
BP13
BP17
BP21
BP25
BP30
BP34
BP38
BP43
BP47
BP51
BP55
BP8
BR3
BR65
BT10
BT15
BT19
BT23
BT28
BT32
BT36
BT40
BT45
BT49
BT53
BT58
BT6
BT62
BU1
BU67
BV2
BV4
BV64
BV66
BW13
BW17
BW21
BW25
BW30
BW34
BW38
BW43
BW47
BW51
CE51
BY65
C11
C14
C18
C22
C26
C29
C33
C35
C4
C52
C54
C57
C61
C64
C7
CA10

CA15
CA19
CA23
CA28
CA32
CA36
CA40
CA45
CA49
CA53
CA58

CA6

CA62

CB1

CB3
CB66
CB67

CC13
CC17
CC21
CC30
CC34
CC38
CC43

CL22

T30
CC8
CD2
CD4

CD64
CD66

CE10
CE15
CE47
CE53

CE6

CE62

CF1
CF2

CF64
CF65
CF66
CF67

CG1

CG11

CG2
CG24
CG27

CG4
CG42
CG44
CG46
CG48

CG5
CG52
CG54
CG56
CG59
CG61
CG64
CG65
CG66
CG67
CH12
CH18

CH2
CH24
CH27

CH3
CH33
CH39

CH4
CH42
CH44
CH46
CH48

CH5

U0700

CAYMAN-2GB-20NM-DDR-MCAYMAN-2GB-20NM-DDR-M

SYM 15 OF 16

VSSVSS

CH52
CH54
CH56
CH59
CH61
CH63
CH64
CH65
CH66
CH7
CH9
CJ1
CJ3
CJ4
CJ41
CJ42
CJ46
CJ5
CJ50
CJ54
CJ57
CJ61
CJ64
CJ65
CJ67
CK4
CK41
CK42
CK46
CK5
CK50
CK54
CK57
CK61
CK64
CL1
CL12
CL18
CL24
CL27
CL3
CL33
CL39
CL4
CL41
CL44
CL48
CL52
CL56
CL59
CL63
CL65
CL67
CL7
CM18
CM2
CM24
CM27
CM39
CM4
CM41
CM44
CM48
CM5
CM52
CM56
CM59
CM63
CM66
D1
D11
D12
D14
D16
D18

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

=|- - - - - ||||- - ||- - |- |- - - - |-

|||- |||- ||||||||||- |- |- |||- ||- ||-

|- - - |||||||- - |||==

D20
D22
D24
D26
D27
D29

D3
D31
D35

D4
D41
D46

D5
D52
D56
D59
D63
D65
D67

D7

D9

E12
E14
E18

E2

E20
E22
E26
E27
E29

E3

E37

E4

E5

E54
E57
E59
E61
E64
E65
E66

E7

E9

F1
F2
F3

F4
F64
F65
F66
F67

G38
G43
G47
G51

G8

H1

H2
H66
H67

J10
J15
J19
J28
J32
J40
J45
J49
J53

J6

K2

K66

L13
L17
L21
L25
L30
L34

U0700

CAYMAN-2GB-20NM-DDR-M

CSPCSP

SYM 16 OF 16

VSSVSS

L38
L43
L47
L51
L55
L62
L8
M1
M2
M3
M4
M64
M65
M66
M67
P10
P15
P19
P23
P28
P32
P36
P40
P45
P49
P53
P6
P62
R2
R4
R64
R66
T13
T25
T34
T38
T51
T55
U1
U67
V10
V15
V28
V32
V36
V40
V53
V58
V6
V62
W3
W65
Y13
Y17
Y21
Y25
Y30
Y43
Y47
Y51
Y55
BF38
J58

47 41 40 37 36 32 21 20 18 16

29 25 18 17 13 12 11 9 8 7 5

47 41 40 37 36 32 21 20 18 16

19 10 8

PP1V2_SOC

53 52 48

52 48 47 46 39

53 52 48

19

C1604

2.2UF

X5R-CERM

ROOM=SOC

PP1V8_SDRAM

1.62-1.98V @43mA MAX

PP1V8

PP1V8_SDRAM

1

C1603

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

PP1V2_REF

R1602

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1601

0.00

0%

1/32W

MF

01005

ROOM=SOC

20%

6.3V

0201-1

1

2

1

C1615

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1602

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

1

C1605

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1607

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1.62-1.98V @10mA MAX

1

C1601

0.1UF

20%

6.3V
X5R-CERM

2

01005

ROOM=SOCROOM=SOC

1.62-1.98V @2mA MAX

1.62-1.98V @1mA MAX

1.62-1.98V @1mA MAX

TBD-TBDV @30mA MAX

C1611

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

VDD12_PLL_CPU:1.14-1.26V @13mA MAX

PP1V2_PLL_CPU

21

1

C1606

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

VDD12_PLL_SOC:1.14-1.26V @31mA MAX

PP1V2_PLL_SOC

21

1

C1609

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1608

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1610

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1612

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1614

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1613

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

AM1

AM67

BB1

BB67

C3

C65

CK3

CK65

AJ62
AN62
AU62
BA62

BF62

G40
G45
G49
G53

AD6

AJ6
AN6
BA6

BF6

CE19
CE23

CE28
CE32
CE34
CE36
CE43
CE38

AR23
BK19

AF21

J36

CE21

BF60

CG9

CC40

AU23

T28

Y38

BA25

Y32
AD36
AD38

Y34

CAYMAN-2GB-20NM-DDR-M

VDD1

VDDIO18_GRP1

VDDIO18_GRP2

VDDIO18_GRP3

VDDIO18_GRP4

VDDIO18_GRP10

VDD18_TSADC0
VDD18_TSADC1
VDD18_TSADC2
VDD18_TSADC3
VDD18_TSADC4
VDD18_TSADC5

VDD18_FMON

VDD18_LPOSC

VDD12_CPU_UVD
VDD12_GPU_UVD
VDD12_SOC_UVD

VDD12_PLL_CPU

VDD12_PLL_SOC

U0700

CSP

SYM 12 OF 16

CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND

VDD18_EFUSE1
VDD18_EFUSE2

D

CG7
G34

C

B

1.70-1.95V @134mA MAX

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

315mA MAX

PP1V8

1

C1701

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1739

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

R1703

24.9

1%

1/32W

MF

01005

ROOM=NAND

21

PP1V8_NAND_AVDD

17

1

C1741

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

NAND_AGND

1

C1707

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1743

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1726

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=NAND

1

C1729

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1745

1.0UF

20%

2

6.3V
X5R

0201-1

ROOM=NAND

1

C1710

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=NAND

1

C1730

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1747

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

17 8

17 8

PROBE POINTS

90_PCIE_AP_TO_NAND_REFCLK_P

90_PCIE_AP_TO_NAND_REFCLK_N

D

SM

1

1

PP1701

PP

P2MM-NSM

ROOM=NAND

SM

PP1702

PP

P2MM-NSM

ROOM=NAND

C

19

PP0V9_NAND

1007mA MAX

1

C1737

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1708

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1704

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1738

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1711

22PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C1702

15UF

20%

6.3V
X5R

2

0402-1

ROOM=NAND

1

C1740

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1717

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C1705

15UF

20%

6.3V
X5R

2

0402-1

ROOM=NAND

1

C1742

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1723

39PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

C1722

1

15UF

20%

6.3V

2

0402-1

ROOM=NAND

1

C1744

1.0UF

20%

6.3V

2

X5R
0201-1 0201-1

ROOM=NAND

1

C1712

2

C1727

1

15UF

20%

6.3V
X5RX5R

2

0402-1

ROOM=NAND

1

C1746

2

100PF

5%
16V
NP0-C0G
01005

ROOM=NAND

1.0UF

20%

6.3V
X5R

ROOM=NAND

#24543147:10uF for 32GB
#26326159:10uF for C1719

OMIT

1

C1748

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1713

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1716

15UF

20%

6.3V

2

X5R
0402-1

1

C1719

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=NANDROOM=NAND

1230mA MAX (1us peak power)

PP3V0_NAND

OMIT

1

C1721

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1733

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

C

B

C1703

1

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

C1706

1

22PF

5%
16V

2

CERM
01005

ROOM=NAND

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 29

1

R1704

3.01K

1%
1/32W
MF
01005

2

ROOM=NAND

C1709

1

100PF

5%

2

16V
NP0-C0G
01005

ROOM=NAND

PP1V8

C1714

1

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1724

0.01UF

10%

6.3V

2

X5R
01005

ROOM=NAND

C1725

1

0.01UF

10%

2

6.3V
X5R
01005

ROOM=NAND

11

17 8

17 8

C1720

1

100PF

5%

2

16V
NP0-C0G
01005

ROOM=NAND

C1728

1

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

AP_TO_NAND_SYS_CLK

90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_AP_TO_NAND_REFCLK_N

8

PCIE_NAND_BI_AP_CLKREQ_L

PCIE_NAND_RESREF

8

90_PCIE_AP_TO_NAND_TXD_P

8

90_PCIE_AP_TO_NAND_TXD_N

8

90_PCIE_NAND_TO_AP_RXD_P

8

90_PCIE_NAND_TO_AP_RXD_N

NAND_VREF

NC

NC

NC

NC

M4

PCI_AVDD_CLK1

D2

CLK_IN

H8

PCIE_REFCLK_P

H6

PCIE_REFCLK_M

G9

PCIE_CLKREQ*

M6

PCI_RESREF

M8

PCIE_RX0_P

K8

PCIE_RX0_M

N5

PCIE_RX1_P

N3

PCIE_RX1_M

P8

PCIE_TX0_P

N7

PCIE_TX0_M

M2

PCIE_TX1_P

K2

PCIE_TX1_M

K6

K4

J7

J5

PCI_VDD2

PCI_VDD1

PCI_AVDD_H

PCI_AVDD_CLK2

C3

AVDD1

E5

VREF

A5

R7

R3

J9

J1

F2

A7

A3

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDIO

U1701

THGBX6T1T82LFXF

VLGA

VER-1

ROOM=NAND

BOMOPTION=OMIT_TABLE

CRITICAL

OB10

OB0

VDDIO

VDDIO

OF10

OF0

VDDIO

VDDIO

R5

VDDIO

OA0

VCC

OD0

OA10

VCC

OD10

VCC

VCC

EXT_NWE

OG10

OG0

VCC

VCC

EXT_D0
EXT_D1
EXT_D2
EXT_D3
EXT_D4
EXT_D5
EXT_D6
EXT_D7

EXT_NCE

EXT_NRE

EXT_RNB

EXT_CLE

EXT_ALE

G3
J3
H2
E3
E7
F6
C7
B8

G1

F4

C5

G5

H4

D4

1

C1749

1.0UF 1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1715

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1750

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1718

22PF

5%
16V

2

CERM
01005

ROOM=NAND

PMU_TO_NAND_LOW_BATT_BOOT_L
AP_TO_NAND_FW_STRAP

NC

NC

NC

NC

NC

SYSTEM_ALIVE

PCIE_AP_TO_NAND_RESET_L

SWD_AP_BI_NAND_SWDIO_R

SWD_AP_NAND_SWCLK_R

NC

NC

1

C1751

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1731

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

2

ROOM=NAND

ROOM=NAND

1/32W 0%

1

C1752

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

C1732

39PF

5%
16V
NP0-C0G
01005

ROOM=NAND

20

12

21 20 15

8

0.00

0%

0.00

R1702

21

01005 MF1/32W

R1707

21

01005 MF

1

C1753

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1734

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C1754

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1735

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1736

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

SWD_AP_BI_NAND_SWDIO

SWD_AP_TO_MANY_SWCLK

B

13

53 36 13

A

F8

D8

D6

RESET*

TRST*

ZQ

SYNC_MASTER=Sync

PAGE TITLE

7

AP_TO_NAND_RESET_L

NC

NAND_ZQ

spare

1

R1701

34.8

0.5%
1/32W
MF
01005

ROOM=NAND

2

17

NAND_AGND

VSSA

B2

VSS

B4

VSS

B6

VSS

G7

OE10

VSS

L3

VSS

VSS

L5

VSS

L7

P2

VSS

P4

VSS

P6

VSS

OC0

8 7 5 4 2 1

VSS

OC10

VSS

OE0

VSS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

36

051-00419

8.0.0

6 OF 53

6 OF 81

D

SYNC_DATE=05/17/2016

A

34567 8

2 1

D

C

B

A

BUCK5

3.2A MAX

BUCK6

1.5A MAX

BUCK7

1.5A MAX

BUCK8

1.5A MAX

BUCK9

0.75A MAX

15 10 9 8 7

25

28 27 26 25 23 21 19 10 9 4

52 46 41 40 39 37 35 34 33 31

1

C1867

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

19

PP1V25_BUCK

14

PP_CPU_SRAM_VAR

0.80V - 1.06V

14

PP_GPU_SRAM_VAR

0.80V - 0.92V

PP2V8_UT_AF_VAR

53

1

C1840

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1811

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1868

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1869

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1870

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP_VDD_MAIN

1

C1875

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1876

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1801

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1846

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1847

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1848

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1803

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1804

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1805

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1806

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1862

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1850

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1851

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1852

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1877

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1807

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1808

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1809

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1810

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1863

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

19

VDD_MAIN_SNS

1

C1853

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1854

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1855

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1849

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

D10/D101:#24681501,TY ONLY, D11/D11: Both Vendor

CRITICAL

1

C1857

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1858

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1859

2.2UF

20%

6.3V

2

X5R-CERM

0201-1

ROOM=PMU

1

C1856

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

L1803

1.0UH-3.6A-0.06OHM

2 1

MEKK2016T-SM

NO_XNET_CONNECTION=1

ROOM=PMU

OMIT

BUCK5_LX0PP0V9_SOC_FIXED

XW1802

SHORT-20L-0.05MM-SM

CRITICAL

21

L1804

BUCK5_FB

NO_XNET_CONNECTION=1ROOM=SOC

1UH-20%-2.1A-0.12OHM

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

BUCK6_LX0

XW1807

SHORT-20L-0.05MM-SM

21

ROOM=SOC

CRITICAL

L1805

1.0UH-20%-2.25A-0.086OHM

2 1

MCFE2016T-SM

ROOM=PMU

OMIT

XW1803

SHORT-20L-0.05MM-SM

21

ROOM=SOC NO_XNET_CONNECTION=1

CRITICAL

L1801

1UH-20%-2.1A-0.12OHM

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

XW1801

SHORT-20L-0.05MM-SM

21

CRITICAL

ROOM=SOC

L1802

NO_XNET_CONNECTION=1

1.0UH-20%-1.5A-0.161OHM

21

0603

OMIT

XW1806

SHORT-20L-0.05MM-SM

21

ROOM=SOC NO_XNET_CONNECTION=1

BUCK6_FB

NO_XNET_CONNECTION=1

BUCK7_LX0

BUCK7_FB

BUCK8_LX0

BUCK8_FB

BUCK9_LX0

BUCK9_FB

VDD_MAIN_SNS

M8

VDD_MAIN

N7

VDD_MAIN_E

H6

VDD_MAIN_N

F11

VDD_MAIN_SW

R13

VDD_MAIN_W

H14

VDD_MAIN_W

H13

A5
B5

VDD_BUCK0_01

C5
D5

A9
B9

VDD_BUCK0_23

C9
D9

A17
B17

VDD_BUCK1_01

C17
D17

A13
B13

VDD_BUCK1_23

C13
D13

H1

VDD_BUCK2

H2
H3

T2

VDD_BUCK3

T3

M1

VDD_BUCK4

M2
M3

B1

VDD_BUCK5

C1
D1

K18

VDD_BUCK6

K19

U6

VDD_BUCK7

V6

F18

VDD_BUCK8

F19

L18

VDD_BUCK9

L19

B2
C2

BUCK5_LX0

D2
A2

BUCK5_FB

F5

J18

BUCK6_LX0

J19

BUCK6_FB

H16

U7

BUCK7_LX0

V7

BUCK7_FB

R8

G18

BUCK8_LX0

G19

BUCK8_FB

H15

M18

BUCK9_LX0

M19

BUCK9_FB

P16

U1801

D2333A1

WLCSP

SYM 2 OF 4

ROOM=PMU

BAT/USBBUCK INPUT

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

BUCK1_LX1

BUCK1_LX2

BUCK1_LX3

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

BUCK2_FB

BUCK3_LX0

BUCK3_FB

VBUCK3_SW

BUCK4_LX0

BUCK4_LX1

BUCK4_FB

VBUCK4_SW

BUCK3_SW1

BUCK3_SW2
BUCK3_SW3

SWITCH OUTPUTS

BUCK4_SW1

BUCK0_LX0

B4
C4
D4
A4

A6
B6
C6
D6

A8
B8
C8
D8

A10
B10
C10
D10

BUCK0_PP_CPU_FB

F10

B18
C18
D18
A18

A16
B16
C16
D16

A14
B14
C14
D14

A12
B12
C12
D12

BUCK1_PP_GPU_FB

F12

G1
G2
G3

J1
J2
J3

BUCK2_PP_SOC_FB

J5

R2
R3
R1
R7

U2
V2

N1
N2
N3

L1
L2
L3

K5

U5
V5

T1
U1

U3
V3

U4
V4

NO_XNET_CONNECTION=1

BUCK0_LX1

NO_XNET_CONNECTION=1

BUCK0_LX2

NO_XNET_CONNECTION=1

BUCK0_LX3

NO_XNET_CONNECTION=1

BUCK1_LX0

NO_XNET_CONNECTION=1

BUCK1_LX1

NO_XNET_CONNECTION=1

BUCK1_LX2

BUCK1_LX3

NO_XNET_CONNECTION=1

BUCK2_LX0

BUCK2_LX1

NO_XNET_CONNECTION=1

BUCK3_LX0

NO_XNET_CONNECTION=1

BUCK3_FB

NO_XNET_CONNECTION=1

BUCK4_LX0

NO_XNET_CONNECTION=1

BUCK4_LX1

NO_XNET_CONNECTION=1

BUCK4_FB

NO_XNET_CONNECTION=1 ROOM=SOC

L1806

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1807

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

CRITICAL

L1808

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

ROOM=PMU

CRITICAL

L1809

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

14

CRITICAL

L1810

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1811

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

CRITICAL

L1812

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

ROOM=PMUNO_XNET_CONNECTION=1

CRITICAL

L1813

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

14

CRITICAL

L1814

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1815

0.47UH-20%-3.8A-0.048OHM

2 1

PIQA20121T-SM

ROOM=PMU

14

L1816

CRITICAL

ROOM=PMU

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

OMIT

XW1804

SHORT-20L-0.05MM-SM

ROOM=SOC

CRITICAL

21

L1817

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1818

0.47UH-20%-3.8A-0.048OHM

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

XW1805

SHORT-20L-0.05MM-SM

21

PP1V8

PP1V8_TOUCH
PP1V8_MAGGIE_IMU

PP1V1

CRITICAL

36 24

15 7

Voltages per Cayman Power Spec, Sec. 2.2, rev 0.9.2, #24557869

PP_CPU_VAR

1

C1818

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1819

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1825

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1826

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1831

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1832

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1837

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1838

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1842

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1843

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1844

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1845

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

2

0.625V - 1.06V

C1872

220PF

5%
10V
C0G-CERM
01005

ROOM=PMU

PP_GPU_VAR

1

C1813

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1814

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1820

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1821

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1827

15UF

20%

6.3V

2

X5R

0402-1

ROOM=PMU

1

C1828

15UF

20%

6.3V

2

X5R

0402-1

ROOM=PMU

1

C1833

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1834

15UF

20% 20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1839

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1866

15UF

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1865

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1873

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

0.67V - 0.92V

1.03V for overdrive only

PP_SOC_VAR

0.67V/0.80V

1

C1822

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1829

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1835

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1841

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1864

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1871

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP1V8_SDRAM

1

C1816

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1823

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1860

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP1V1_SDRAM

1

C1830

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

52 48 47 46

39 29 25 17 16 13 12 11 9 8 7 5

1

C1836

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1802

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1874

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

SYNC_MASTER=Sync

PAGE TITLE

1

C1861

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

14

14

14

D

13.4A MAX

BUCK1

C

4.7A MAX13.4A MAX

BUCK2BUCK0

(pending vendor qual)

53 52 48 47

19 15

41 40 37 36 32 21 20 16

1.7A MAX

4.7A MAX

B

BUCK3 BUCK4

A

SYNC_DATE=05/17/2016

spare

DRAWING NUMBER SIZE

47 46 39 38

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

Apple Inc.

R

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

D

8 7 5 4 2 1

36

D

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

VDD_MAIN_SNS

18

PMU_PRE_UVLO_DET

20

53 52

PP_VDD_MAIN

OMIT

XW1901

SHORT-20L-0.05MM-SM

21

ROOM=PMU

NO_XNET_CONNECTION

OMIT

XW1902

SHORT-20L-0.05MM-SM

21

ROOM=PMU

1

2

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

53 52

C1901

15UF

20%

6.3V
X5R
0402-1

ROOM=PMU

1

C1910

10UF

20%

6.3V

2

0402-9

ROOM=PMU

PP_VDD_MAIN

1

C1914

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1911

10UF

20%

6.3V

2

CERM-X5RCERM-X5R
0402-9

1

C1907

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMUROOM=PMU

34567 8

ADELYN LDO SPECS

LDO#

LDO1 (Ca)

LDO2 (Ca)

LDO3 (Ca)

LDO4 (D)

LDO5 (F)

LDO6 (Cb)

ADJ.RANGE, LOW

1.2-2.475V

1.2-2.475V

1.2-2.475V

0.7-1.2V

2.5-3.6V(tbc)

1.2-2.475V

LDO7 (Cb) 1.2-2.475V 2.4-3.675V +/-30mV 250mA

LDO8 (Cb)

LDO9 (Cb)

1.2-2.475V

1.2-2.475V

ADJ.RANGE, HI

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

ACCURACY

+/-1.4%

+/-2.5%

+/-2.5%

+/-75mV

+/-2.5%

+/-30mV

+/-25mV

MAX.CURRENT

50mA

50mA

50mA

60mA+/-2.5%

1000mA

250mA

(500/100mA in bypass)

250mA

250mA

LDO#

LDO11 (Cb)

LDO12 (E)

LDO13 (Cb)

LDO14 (Gb)

LDO15 (Ca)

LDO16 (Cb)

LDO17 (Ca)

LDO18 (Gb)

LDO19 (Gb)

2 1

ADJ.RANGE, LOW

1.2-2.475V

1.8V

1.2-2.475V

0.7-1.4V

1.2-2.475V

1.2-2.475V

1.2-2.475V

0.7-1.4V

0.7-1.4V

ADJ.RANGE, HI

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

ACCURACY

+/-30mV

+/-5%

+/-30mV

+/-3.0%

+/-2.5%

+/-30mV

+/-2.5%

+/-3.0%

+/-3.0%

MAX.CURRENT

250mA

10mA

250mA

400mA

50mA

250mA

50mA

400mA

400mA

D

C

B

A

U1801

D2333A1

WLCSP

SYM 4 OF 4

A1
A11
A15

H8
A19
P13

A3

P14

A7
B11
B15
B19

B3

B7
C11
C15
C19

C3

C7
D11
D15
D19

D3

D7

VSS VSS

E1
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19

E2

E3

E4

E5

E6

E7

E8

E9

F1

F17

F2
F3
F4

PP1V1_SDRAM

18 15

53 38 37 32 25 23

G17
G4
H17
H18
H19
H4
J17
J4
J8
K1
K17
K2
K3
K4
K8
L17
L4
L8
M17
M4
N17
N18
N19
N4
P1
P2
P3
P4
P15
R17
R4
T5
T15
T4
T6
T7
T8
U15
T13
U8
V1
V12
V19
V8

U15 = PMU XTAL GND

PP_VDD_BOOST

1

C1915

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1908

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

PP1V25_BUCK

18

27 26 25 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 28

PMU_VSS_RTC

1

C1912

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1913

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

20

53 52

PP_VDD_MAIN

NC

R12

VDD_LDO1

V11

VDD_LDO2_15

R10

VDD_LDO3_17

R16

VDD_LDO4

V9

VDD_LDO5

V10
R14

VDD_LDO6_BYP
VDD_LDO7_8

P19
R19

VDD_LDO9
VDD_LDO10

R9

VDD_LDO11_13

V13

VDD_LDO14

V16

VDD_LDO16

T19

VDD_LDO18

V17

VDD_LDO19

V18

VDD_LDO19

U19

VPP_OTP

G15

TP_DET

VPUMP: 10nF min. @4.6V

1

C1905

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PMU

U1801

D2333A1

WLCSP

SYM 1 OF 4

LDO INPUT

LDO

1

2

1

C1909

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PMU_VPUMP

C1902

47NF

20%

6.3V
X5R-CERM
01005

ROOM=PMU

VLDO1
VLDO2
VLDO3

VLDO4
VLDO5_0
VLDO5_1

VLDO6

VBYPASS

VLDO7

VLDO8

VLDO9

VLDO9_FB

VLDO10
VLDO11
VLDO12
VLDO13
VLDO14
VLDO15
VLDO16
VLDO17
VLDO18
VLDO19

VBUF_1V2

VPUMP

T12
U11
T10
T16
U9
U10
T14

R15

T17
P18
R18

P17

T9
U13
P7
U14
U16
U12
T18
T11
U17
U18

P8J6

R5

NC

NC

1

C1916

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

LDO10 (Ga)

1

C1918

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1921

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1933

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1

C1922

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1923

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1925

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1

C1926

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

+/-4.5%

1

C1927

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1935

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1150mA0.7-1.2V

LDO_RTC

BUF_1V2

2.5V

1.2V

PP3V3_USB

PP1V8_VA
PP3V0_ALS_APS_CONVOY

PP0V8_AOP

PP3V0_NAND

PP_ACC_VAR

PP3V0_TRISTAR_ANT_PROX
PP2V9_NH_AVDD
PP1V8_HAWKING

PP0V9_NAND

7

29 25

15

52 17

29

44

17

+/-2.0%

+/-5.0%

35 34 33 32

53 41 40 29

46 40 27

10mA

10mA

LDO1
LDO2
LDO3
LDO4
LDO5

LDO6

LDO7
LDO8
LDO9

LDO10

C

LDO11

PP1V8_ALWAYS

PP3V0_MESA

PP1V2_SOC

PP1V8_MESA

#24989262

PP_LDO17

PP1V2_UT_DVDD

PP1V2_NH_NV_DVDD

PP1V2_REF

1/20W

1%

2 1

R1901

0.00

21 20

38

48 38

MF

NOSTUFF

0201

25

29

16

LDO12
LDO13

16 10 8

LDO14
LDO15
LDO16
LDO17
LDO18
LDO19

VBUF_1V2

New for ADELYN

1

C1930

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

2

1

C1904

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

C1932

0.22UF

20%

6.3V
X5R
01005-1

ROOM=PMU

1

C1919

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

B

#24989262:OTP-AO LDO17 default off,50mA Iout_max

A

SYNC_MASTER=Sync

PAGE TITLE

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

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SHEET

6 OF 81

D

8 7 5 4 2 1

36

34567 8

2 1

BUTTON PULL-UP RESISTORS

D

47 41 40 37 36 32 21 20 18 16

53 52 48

PP1V8_SDRAM

1

R2006

100K

5%
1/32W
MF
01005

2

ROOM=PMU

PP1V8_ALWAYS

1

R2005

100K

5%
1/32W
MF
01005

2

ROOM=PMU

D101/D111 ONLY: TCXO_RF Supplies 32K

1

R2012

10K

5%
1/32W
MF
01005

2

ROOM=PMU

NO_XNET_CONNECTION

1

C2001

1000PF

10%
10V

2

X5R
01005

ROOM=PMU

21 20 19

40

13 7

13

15 13

13

40 37 13 7

13

21 17 15

53 39 23 13

13

AP_TO_PMU_WDOG_RESET

7

TRISTAR_TO_PMU_HOST_RESET

AP_TO_PMU_SOCHOT_L

11

PMU_TO_SYSTEM_COLD_RESET_L

Active high with int 200k PD

AOP_TO_PMU_SLEEP1_REQUEST
PMU_TO_AOP_SLEEP1_READY
AOP_TO_PMU_ACTIVE_REQUEST
PMU_TO_AOP_TRISTAR_ACTIVE_READY

PMU_TO_AOP_CLK32K

SYSTEM_ALIVE
LCM_TO_MANY_BSYNC

HIGH=FORCE PWM MODE

PMU_TO_AOP_IRQ_L

NC

NC

NC

1

SM

PP

1

SM

PP

1

SM

PP

RESET_IN1

P9

RESET_IN2

P10

RESET_IN3

P11

RESET*

M5

SHDN

P12

SLEEP1_REQ

R11

SLEEP1_RDY

L11
L12

ACTIVE_REQ

J12

ACTIVE_RDY

SLEEP_32K

M9

OUT_32K

M10

SYS_ALIVE

H5

FORCE_SYNC

L13

CRASH*

L10

IRQ*

G5

PP2001

P2MM-NSM

ROOM=SOC

PP2002

P2MM-NSM

ROOM=SOC

PP2003

P2MM-NSM

ROOM=PMU

U1801

D2333A1

WLCSP

SYM 3 OF 4

REFS

RESETS

COMPARATORADC

IREF

VREF

PRE_UVLO*

VDROOP0*
VDROOP1*

VDROOP0_DET
VDROOP1_DET

PMU_IREF

K6

J7

PMU_VREF

1

C2006

0.22UF

20%

6.3V

2

X5R
0201

ROOM=PMU

PMU_TO_AP_PRE_UVLO_L

N10

G6

PMU_TO_AP_THROTTLE_CPU_L
PMU_TO_AP_THROTTLE_GPU_L

G7

F6

AP_VDD_CPU_SENSE

F7

AP_VDD_GPU_SENSE

1

R2011

200K

1%
1/20W
MF
201

2

ROOM=PMU

11

12

11

14

14

1

2

44 20

44 20

BUTTON_RINGER_A

BUTTON_POWER_KEY_L

PP1V8_SDRAM

NOSTUFF

1

R2015

220K

5%
1/32W
MF
01005

2

44 20

BUTTON_VOL_DOWN_L

NOTE:VDROOP_DET filtering is now inside Adelyn

ROOM=PMU

PP1V8_SDRAM

NOSTUFF

R2008

100K

5%
1/32W
MF
01005

ROOM=PMU

PP1V8_ALWAYS

NOSTUFF

1

R2007

220K

5%
1/32W
MF
01005

ROOM=PMU

2

53 52 48

47 41 40 37 36 32 21 20 18 16

D

21 20 19

53 52 48

47 41 40 37 36 32 21 20 18 16

C

B

C2007

100PF

NP0-C0G

ROOM=PMU

ROOM=PMU

ROOM=PMU

01005

C2008

100PF

NP0-C0G

01005

C2009

100PF

NP0-C0G

01005

5%

16V

5%

16V

5%

16V

FOREHEAD NTC

1

1

2

R2001

10KOHM-1%

01005

2

ROOM=PMU

REAR CAMERA NTC

1

1

R2002

10KOHM-1%

2

2

01005
ROOM=PMU

RADIO PA NTC

1

1

2

R2003

10KOHM-1%

01005
ROOM=PMU

2

FOREHEAD_NTC_RETURN

RCAM_NTC_RETURN

PA_NTC_RETURN

I2C1_AP_SDA

47

#24825674: Add R2020 to meet timing spec
#26169957: R2020 to 100ohm (D10x only)

OMIT

XW2002

SHORT-20L-0.05MM-SM

ROOM=SOC

XW2003

SHORT-20L-0.05MM-SM

ROOM=SOC

XW2004

SHORT-20L-0.05MM-SM

ROOM=SOC

XW2005

SHORT-20L-0.05MM-SM

ROOM=SOC

21

OMIT

21

OMIT

21

OMIT

21

R2020

100

5%

1/32W

MF

01005

ROOM=PMU

1

C2013

1000PF

10%
10V

2

X5R
01005

ROOM=PMU
PLACE_NEAR=U1801:2mm

21

TBD

47

11

11

11

20

44 12

39 37

40 20

36

53

53

27

53 20

53

I2C1_AP_SCL

I2C_PMU_SDA_R

SPI_PMGR_TO_PMU_SCLK
SPI_PMGR_TO_PMU_MOSI
SPI_PMU_TO_PMGR_MISO

AP_TO_PMU_AMUX_OUT

7

PMU_ADC_IN

BUTTON_VOL_UP_L

LCM_TO_CHESTNUT_PWR_EN
TRISTAR_TO_PMU_USB_BRICK_ID

PP1V2_MAGGIE
PMU_AMUX_AY

4

BBPMU_TO_PMU_AMUX1
BBPMU_TO_PMU_AMUX2

ACC_BUCK_TO_PMU_AMUX

PMUGPIO_TO_WLAN_CLK32K

CHESTNUT_TO_PMU_ADCMUX

37

AP_TO_PMU_TEST_CLKOUT

7

BBPMU_TO_PMU_AMUX3

PMU_AMUX_BY

4

FOREHEAD_NTC

REAR_CAMERA_NTC
RADIO_PA_NTC

AP_NTC

PMU_TCAL

PMU_XTAL1

PMU_XTAL2

PMU_VDD_RTC

1

C2002

0.22UF

20%

2

6.3V
X5R
0201

ROOM=PMU

NC

NC

NC

NC

N13
M13

N6
N5
P5

J14
J15

J16
K16
K15
K14

J13
K13
K12

L14
L15
L16

M16
M15
M14
N16
N15
N14

R6

M6

P6

L5
L6

G16

V14
V15

N9

SCL
SDA

SCLK
MOSI
MISO

AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_A4
AMUX_A5
AMUX_A6
AMUX_A7
AMUX_AY

AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_B4
AMUX_B5
AMUX_B6
AMUX_B7
AMUX_BY

TDEV1
TDEV2
TDEV3
TDEV4
TDEV5
TCAL

XTAL1
XTAL2

VDD_RTC

PRE_UVLO_DET

PMGR

AMUX

BUTTONS

NTCXTAL

GPIO

GPIO21 = I2C SCL is for Chestnut dark current mitigation RS = requires sequencer

IBAT

VBAT

BRICK_ID

ADC_IN

BUTTON1
BUTTON2
BUTTON3
BUTTON4

BUTTONO1
BUTTONO2
BUTTONO3

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

PMU_PRE_UVLO_DET

N8

L7

NC

M7

NC

H7

TRISTAR_TO_PMU_USB_BRICK_ID

PMU_ADC_IN

K7

M12

BUTTON_VOL_DOWN_L

N12

BUTTON_POWER_KEY_L

M11

BUTTON_RINGER_A

N11

H11
J11
K11

F16
F15
G14
F14
F13
G13
G12
H12
G11
G10
F9
G9
F8
G8
H9
H10
J9
J10
K9
K10
L9

Reserved for MENU key on dev board

NC

PMU_TO_AP_BUF_VOL_DOWN_L
PMU_TO_AP_BUF_POWER_KEY_L
PMU_TO_AP_BUF_RINGER_A

TIGRIS_TO_PMU_INT_L
BB_TO_PMU_PCIE_HOST_WAKE_L
PMU_TO_BBPMU_RESET_R_L
WLAN_TO_PMU_HOST_WAKE
NFC_TO_PMU_HOST_WAKE
PMU_TO_NAND_LOW_BATT_BOOT_L

NC_PMU_TO_GNSS_EN

PMUGPIO_TO_WLAN_CLK32K
PMU_TO_BT_REG_ON

NC_GNSS_TO_PMU_HOST_WAKE

PMU_TO_WLAN_REG_ON
BT_TO_PMU_HOST_WAKE
PMU_TO_CODEC_DIGLDO_PULLDN
PMU_TO_ACC_BUCK_SW_EN
PMU_TO_BB_USB_VBUS_DETECT
PMU_TO_NFC_EN

PMU_TO_BOOST_EN

PMU_TO_LCM_PANICB

PMU_TO_HOMER_RESET_L

I2C0_AP_SCL

19

20

12

12

12

40 20

44 20

44 20

44 20

21

53

53

53

17

53

53

53

32

27

53

53

23

39

36

37 47

Button for two-finger reset: 20711463 and 21196187

R2000

ROOM=PMU

53 20

#24511807: Stuff for Carrier

R2009

0.00

RS

RS

RS

Sequencer controllable

1/32W

01005

1.00K

1/32W

01005

0%

MF

5%

MF

C

21

PMU_TO_BBPMU_RESET_L

53

B

21

PMU_TO_AP_FORCE_DFUPMU_TO_AP_FORCE_DFU_R

12 4

A

AP NTC

1

C2010

100PF

NP0-C0G

ROOM=PMU

01005

5%

16V

1

2

R2004

10KOHM-1%

01005

ROOM=PMU

2

AP_NTC_RETURN

NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC

1

C2011

100PF 3.92K

5%
16V

2

NP0-C0G
01005

ROOM=PMU

1

R2010

0.1%
1/20W
MF
0201
ROOM=PMU

2

C2003

22PF

5%

16V

CERM

01005

ROOM=PMU

1

2

19

CRITICAL

32.768KHZ-20PPM-12.5PF

Y2001

21

1.60X1.00-SM

ROOM=PMU

PMU_VSS_RTC

1

C2004

22PF

5%
16V

2

CERM
01005

ROOM=PMU

XW2001

SHORT-20L-0.05MM-SM

ROOM=PMU

21

OMIT

SYNC_MASTER=Sync

PAGE TITLE

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Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00419

REVISION

D

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

SYNC_DATE=05/17/2016

A

8 7 5 4 2 1

36

TIGRIS CHARGER

34567 8

2 1

D

See Charger C2113 on Pg46

1

C2114

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=CHARGER

PP_VDD_MAIN

D

31 28 27 26 25 23 19 18 10 9 4

53 52 46 41 40 39 37 35 34 33

C

B

40 4

20 19

20

PP5V0_USB

PP1V8_ALWAYS

TIGRIS_TO_PMU_INT_L

USB_VBUS_DETECT

7

1

R2101

100K

5%
1/32W

MF

01005

2

ROOM=CHARGER

#24558610: Change to 100ohm

1

C2101

4.2UF

10%
16V

2

X5R-CERM
0402-1

ROOM=CHARGER

R2103

100

5%

1/32W

MF

01005

R2104

30.1K

1%

1/32W

MF

01005

TIGRIS_PMID

1

C2103

330PF

10%
16V

2

CER-X7R
01005

ROOM=CHARGER

1

C2110

330PF

10%
16V

2

CER-X7R
01005

F4: 100 kOhm pullup to VLDO (regulated output voltage)

21

ROOM=CHARGER

21

ROOM=CHARGER

1

2

ROOM=CHARGER

20 17 15

1

C2109

4.2UF

10%
16V
X5R-CERM
0402-1

ROOM=CHARGER

47

I2C1_AP_SDA
I2C1_AP_SCL

47

C2111

4.2UF

10%
16V

2

X5R-CERM
0402-1

ROOM=CHARGER

SYSTEM_ALIVE

TRISTAR_TO_TIGRIS_VBUS_OFF

40

TIGRIS_TO_PMU_INT_R_L

TIGRIS_VBUS_DETECT

1

C2112

330PF

10%
16V

2

CER-X7R
01005

ROOM=CHARGER

F5

PMID

A5

VBUS

B5

VBUS

D5

VBUS

C5

VBUS

E5

VBUS

G3

SDA

E4

SCL

E3

SYS_ALIVE

F4

VBUS_OVP_OFF

G2

INT

F1

VBUS_DET

F3

TEST

C2

D2

B2

A2

VDD_MAIN

VDD_MAIN

VDD_MAIN

VDD_MAIN

U2101

SN2400AB0

WCSP

ROOM=CHARGER

CRITICAL

PGND

PGND

PGND

PGND

B3

A3

D3

C3

LDO

BOOT

BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW

BAT
BAT
BAT
BAT

BAT_SNS

ACT_DIODE

HDQ_HOST

HDQ_GAUGE

G4

G5

A4
B4
D4
C4

A1
B1
D1
C1

E1

E2

G1
F2

TIGRIS_LDO

1

C2104

220PF

5%
10V

2

C0G-CERM
01005

ROOM=CHARGER

NO_XNET_CONNECTION

C2105

0.047UF

10%
16V
X5R

0201

21

TIGRIS_BOOT

ROOM=CHARGER

TIGRIS_BUCK_LX

VBATT_SENSE

TIGRIS_ACTIVE_DIODE

SWI_AP_BI_TIGRIS
TIGRIS_TO_BATTERY_SWI_1V8

1

C2115

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CHARGER

22

12

28

TO TRINITY

#25112685,Remove Snub

48 47 41 40 37 36 32 20 18 16

53 52

PP1V8_SDRAM

C2106

330PF

10%
16V

CER-X7R

ROOM=CHARGER

01005

1

2

ROOM=CHARGER

C2102

220PF

5%

10V

C0G-CERM

01005

NOSTUFF

R2102

100K

5%

1/32W

MF

ROOM=CHARGER

01005

C

B3

B2

B1

A3

A2

A1

G

1

D

2

1

2

1

2

C3

C2

C1

C2108

330PF

10%
16V
CER-X7R
01005

ROOM=CHARGER

CRITICAL

S

Q2101

CSD68827W

BGA

ROOM=CHARGER

PP_BATT_VCC

1

2

C2117

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=CHARGER

1

C2118

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CHARGER

22 4

B

1

R2105

40.2K

1%
1/32W
MF
01005

2

2

1

G

S

SYM_VER_1

Q2102

RV3C002UN

DFN

D

TIGRIS_TO_BATTERY_SWI

3

22

A

SYNC_MASTER=Sync

PAGE TITLE

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Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

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D

BATTERY CONNECTOR

516S00172 (matches d10 mlb MCO rev 27)THIS ONE ON MLB --->

C

TIGRIS_TO_BATTERY_SWI

21

R2201

100

21

5%

1/32W

MF

01005

ROOM=BATTERY_B2B

TIGRIS_BATTERY_SWI_CONN

1

C2201

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=BATTERY_B2B

RCPT-BATT-SHORT

J2201

F-ST-SM

1
3 2
4

ROOM=BATTERY_B2B

CRITICAL

ALLOW_APPLE_PREFIX

11
87

5

6

109
12

XW2201

SHORT-20L-0.05MM-SM

PLACE_NEAR=J2201:2mm

ROOM=BATTERY_B2B

NO_XNET_CONNECTION=1

21

VBATT_SENSE

1

C2202

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=BATTERY_B2B

21

1

C2203

100PF

5%
16V

2

NP0-C0G
01005

ROOM=BATTERY_B2B

PP_BATT_VCC

1

C2204

220PF

5%
10V

2

C0G-CERM
01005

ROOM=BATTERY_B2B

C

21 4

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

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DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

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C

28 27 26 25 21 19 18 10 9 4

52 46 41 40 39 37 35 34 33 31

53

PP_VDD_MAIN

1

C2309

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=BOOST

1

C2301

4.7UF

20%

6.3V

2

X5R-CERM1
402

ROOM=BOOST

PMU_TO_BOOST_EN

20

1

R2301

511K

1%
1/32W
MF
01005

2

L2301

ROOM=BOOST

0.47UH-20%-4.2A-0.048OHM

21

PIUA20121T-SM

47

I2C0_AP_SCL

I2C0_AP_SDA

47

SYS_BOOST_LX

BOOST

A3

VIN

A4

C3
C4

A1

B2

C2

B1

C1

VIN

SW
SW

EN

SCL

SDA

VSEL

BYP*

U2301

SN61280D

DSBGA

ROOM=BOOST

VOUT
VOUT

B3
B4

1

C2302

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2303

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2304

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2307

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2308

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2306

220PF

5%
10V

2

C0G-CERM
01005

ROOM=BOOST

When VDD_MAIN < 3.4, boosts to 3.4
Otherwise tracks VDD_MAIN

PP_VDD_BOOST

53 38 37 32 25 19

C

B

53 39 20 13

LCM_TO_MANY_BSYNC

HIGH=FORCE PWM MODE

Control details from Radar 19634006

A2

GPIO

PGND

D3

D2

D4

AGND

D1

B

A

SYNC_MASTER=Sync

PAGE TITLE

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DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

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REVISION

BRANCH

PAGE

SHEET

051-00419

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6 OF 53

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SYNC_DATE=05/17/2016

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36 24 18

36 24 18

PP1V8_MAGGIE_IMU

13

PP1V8_MAGGIE_IMU

1

2

BOMOPTION=CARBON_1

1

R2401

100K

5%
1/32W
MF
01005

2

ROOM=SOC

SPI_AOP_TO_ACCEL_GYRO_CS_L

GYRO_CHARGE_PUMP

ACCEL_GYRO_TO_AOP_INT

13

BOMOPTION=CARBON_1

1

C2403

0.1UF

10%

6.3V

2

X6S
0201

ROOM=CARBON

CARBON - ACCEL & GYRO

C2418

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=CARBON

INVENSENSE, MPU-6800: C2403=0.1UF

BOMOPTION=CARBON_1

1

C2402

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CARBON

BOMOPTION=CARBON_1

1

C2415

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CARBON

16

VDD

1

BOMOPTION=CARBON_1

VDDIO

U2401

MPU-6900-21

LGA

5
8

14

7

CS
FSYNC
REGOUT

INT

GND

9

ROOM=CARBON

CRITICAL

GND

GND

12

11

10

GND

GND

13

SPC

SDI

SDO

DRDY

GND

15

BOMOPTION: CARBON_1
#25765850:Update Carbon APN

2

SPI_AOP_TO_IMU_SCLK_R1

3

SPI_AOP_TO_IMU_MOSI

4

SPI_IMU_TO_AOP_MISO

6

ACCEL_GYRO_TO_AOP_DATARDY

13

MAGNESIUM - COMPASS

D

PP1V8_MAGGIE_IMU_FILT

24

1

C2401

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=MAGNESIUM

24 13

PP1V8_MAGGIE_IMU_FILT

24 13

24 13

BOMOPTION=CARBON_1

1

C2419

5PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=CARBON

24

1

C2408

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAGNESIUM

NC

NC
NC

NC

NC

C2

B1
B3
D1
D2

D4

C4

VDD

U2402

HSCDTD601A-19A

VPP

RSV
RSV
RSV
RSV

RST*

ROOM=MAGNESIUM

LGA

114K INT PU

114K INT PD1.09M INT PU

CRITICAL

VSS

C1

SDO

SDA/SDI

SCL/SCK

CSB

TRG/SE

DRDY

B4

A4

A3

A2

C3

A1

NC

SPI_IMU_TO_AOP_MISO

SPI_AOP_TO_IMU_MOSI

SPI_AOP_TO_IMU_SCLK_R1

SPI_AOP_TO_COMPASS_CS_L

COMPASS_TO_AOP_INT

PP2404

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

PP2401

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

24 13

24 13

24 13

13

13

C

B

36 24 18

PP1V8_MAGGIE_IMU

PP1V8_MAGGIE_IMU_R

24

13

#25782019:Add 0ohm

R2404

0.00

0%

1/32W

MF

ROOM=BOT_CARBON

01005

1

R2441

100K

5%
1/32W
MF
01005

2

ROOM=SOC

SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L

BOT_GYRO_CHARGE_PUMP

PP1V8_MAGGIE_IMU_R

24

21

1

C2448

2.2UF

20%

6.3V

2

X5R-CERM X5R-CERM
0201-1

ROOM=BOT_CARBON

XW2404

SHORT-20L-0.05MM-SM

NC

ROOM=BOT_CARBON

1

C2443

0.1UF

10%

6.3V

2

X6S
0201

ROOM=BOT_CARBON

NO_XNET_CONNECTION=1

XW2404 to balance Via/Cu at INT pin

OMIT

1

C2442

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=BOT_CARBON

21

BOT_ACCEL_GYRO_TO_XW_INT

1

C2445

0.1UF

20%

6.3V

2

01005

ROOM=BOT_CARBON

5
8

14

7

VDD

CS
FSYNC
REGOUT

INT

GND

9

16

1

VDDIO

U2404

MPU-6900-21

LGA

ROOM=BOT_CARBON

CRITICAL

GND

GND

GND

13

12

11

10

GND

SPC

SDI

SDO

DRDY

GND

15

#25740540:PP for South Carbon MOSI

2

SPI_AOP_TO_IMU_SCLK_R2

3

SPI_AOP_TO_IMU_MOSI

4

SPI_IMU_TO_AOP_MISO

6

BOT_ACCEL_GYRO_TO_AOP_DATARDY

PP2402

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

PP2403

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

1

PP

24 13

24 13

PP2440

SM

P2MM-NSM

ROOM=HOMER

13

NOSTUFF

1

C2449

5PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=BOT_CARBON

13

B

A

PP1V8_MAGGIE_IMU_FILT

24

BOSCH: Internal PU

13

NOSTUFF

1

R2403

100K

5%
1/32W
MF
01005

2

ROOM=SOC

SPI_AOP_TO_IMU_MOSI

24 13

SPI_AOP_TO_IMU_SCLK_R1

24 13

SPI_AOP_TO_PHOSPHORUS_CS_L

24

PP1V8_MAGGIE_IMU_FILT

8

VDD VDDIO

U2403

BMP284AA

SDI SDO

4

SCK

2

CS*

LGA

GND

PHOSPHORUS

#24593845, #25691124

BOSCH (APN:338S00188): nostuff C2420/C2421/C2422/C2423 and R2403 PU

R2422

0.00

NOSTUFF

13

1

C2420

4PF

+/-0.1PF
16V

2

NP0-C0G

01005

ROOM=PHOSPHORUS

24 13

1

C2413

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=PHOSPHORUS

6

53

7

IRQ

1

PHOSPHORUS_TO_AOP_INT_L

1

C2405

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=PHOSPHORUS

SPI_IMU_TO_AOP_MISO

NOSTUFF NOSTUFF

1

C2421

20PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

1/32W

01005

ROOM=PHOSPHORUS

0%

MF

21

1

C2422

20PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

NOSTUFF

1

C2423

5.6PF

+/-0.1PF
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

1

C2414

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PHOSPHORUS

PP1V8_MAGGIE_IMU

SYNC_MASTER=Sync

PAGE TITLE

36 24 18

A

SYNC_DATE=05/17/2016

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DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

051-00419

REVISION

8.0.0

BRANCH

PAGE

6 OF 53

SHEET

6 OF 81

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8 7 5 4 2 1

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