THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
NOTE: ACCEL, GYRO, COMPASS ALL USING SPI (VIA OSCAR) FOR AP COMMUNICATION.
0101001X 0X29 0X52
1010001X 0X51 0XA2
1100011X 0X63 0XC6
0010000X 0X10 0X20
0001100X 0X0C 0X18
0010000X 0X10 0X20
63
SYNC_MASTER=N56_MLB
PAGE TITLE
SOC:MAIN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=08/29/2013
DRAWING NUMBER
051-9903
REVISION
7.0.0
BRANCH
PAGE
2 OF 55
SHEET
2 OF 54
124578
SIZE
A
D
876543
12
FIJI: DIGITAL I/O,BOOTSTRAPPING
PP1V8
2 3 5 6 7
10 11 12 13 15 20 23
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
1
1
1
R0302
R0303
R0304
2.2K
2.2K
5%
1/32W
01005
PMU_TO_AP_PRE_UVLO_L_R
AP_TO_PMU_SOCHOT1_L_R
5%
1/32W
MF
MF
01005
2
AP_TO_EEPROM_I2C_SCL
AP_BI_EEPROM_I2C_SDA
NO CONNECTED ON MLB
USED FOR PCIE NAND
DWI_CLK
DWI_DO
SOCHOT0
SOCHOT1
2.2K
5%
1/32W
MF
01005
2
AM32
AM31
Y31
Y30
AH1
AH2
AN1
NC
AN2
NC
AL29
45_AP_TO_PMU_AND_BL_DWI_CLK
AL30
45_AP_TO_PMU_AND_BL_DWI_DO
AR31
AP31
AN30
NC
AN31
NC
AN33
NC
AN32
NC
AM30
NC
C32
OSCAR_TO_AP_ISP_UART_RXD
C33
AP_ISP_TO_OSCAR_UART_TXD
AJ31
AJ32
AL5
NC
AB1
45_AP_TO_TOUCH_CLK32K_RESET_L
AH30
NC
AB4
NC
D
ROOM=SOC
R0301
33.2
45_AP_TO_CODEC_I2S0_MCLK
PP1V8_SDRAM
3 4
10 12 13 14
15 17 26 29
PP1V8_ALWAYS
5
12 14 26
ROOM=SOC
1
ROOM=SOC
R0314
220K
5%
1/32W
MF
01005
R0313
392K
2
1/32W
01005
BOARD_ID3
BOOT_CONFIG0
C
BOOT_CONFIG1
AP_TO_HEADSET_HS3_CTRL
18
AP_TO_HEADSET_HS4_CTRL
18
BUTTON_TO_AP_VOL_UP_L
8
13
BUTTON_TO_AP_VOL_DOWN_L
8
13
SPKAMP_TO_AP_INT_L
16
AP_TO_SPKAMP_BEE_GEES
16
AP_TO_SPKAMP_RESET_L
16
1
AP_TO_BT_WAKE
29
AP_TO_BB_RST_L
29
1%
AP_TO_WLAN_JTAG_SWCLK
29
MF
2
AP_TO_WLAN_JTAG_SWDIO
29
13 21
BUTTON_TO_AP_MENU_KEY_L
8
13
BUTTON_TO_AP_HOLD_KEY_L
PMU_TO_AP_IRQ_L
13
BB_TO_AP_IPC_GPIO1
29
AP_TO_BB_WAKE_MODEM
29
AP_TO_STOCKHOLM_SIM_SEL
29
AP_TO_PMU_KEEPACT
13
BB_TO_AP_DEVICE_RDY
29
BB_TO_AP_GPS_SYNC
29
AP_TO_BB_HOST_RDY
29
BB_TO_AP_RESET_DET_L
29
BOOT_CONFIG1
27
FORCE_DFU
25
DFU STATUS
BOOT_CONFIG2
BOARD_ID4
BOARD_REV3
BOARD_REV2
BOARD_REV1
BOARD_REV0
CODEC_TO_AP_INT_L
10
AP_TO_RADIO_ON_L
29
BOARD_REV3
27
BOARD_REV2
27
BOARD_REV0
27
AP_TO_BB_COREDUMP
29
BUTTON_TO_AP_RINGER_A
8
13
BB_TO_AP_IPC_GPIO
29
AP_TO_VIBE_EN
14
AC1
GPIO0
AC2
GPIO1
AC3
GPIO2
AC4
GPIO3
AD1
GPIO4
AD2
GPIO5
AD3
GPIO6
AD4
GPIO7
AG30
GPIO8
AG31
GPIO9
AG32
GPIO10
Y3
GPIO11
Y4
GPIO12
AK31
GPIO13
AE1
GPIO14
AF30
GPIO15
AE2
GPIO16
NC
AE3
GPIO17
AE4
GPIO18
NC
AK32
GPIO19
AF3
GPIO20
NC
AF4
GPIO21
AH4
GPIO22
AJ1
GPIO23
AD29
GPIO24
AJ2
GPIO25
AK33
GPIO26
AJ30
GPIO27
NC
AJ3
GPIO28
NC
AJ4
GPIO29
NC
AD30
GPIO30
AC30
GPIO31
AC31
GPIO32
NC
AB29
GPIO33
NC
AK1
GPIO34
AK2
GPIO35
AK3
GPIO36
NC
AK4
GPIO37
AM29
GPIO38
AB30
GPIO40
AB31
GPIO41
AL3
GPIO42
U0201
POP-FIJI-1GB-DDR-B0
GRP2
BGA
SYM 2 OF 13
TMR32_PWM0
TMR32_PWM1
TMR32_PWM2
GRP2
UART0_RXD
UART0_TXD
UART1_CTSN
UART1_RTSN
UART1_RXD
UART1_TXD
UART2_CTSN
UART2_RTSN
GRP3
UART2_RXD
UART2_TXD
UART3_CTSN
UART3_RTSN
UART3_RXD
UART3_TXD
UART4_CTSN
UART4_RTSN
GRP3
UART4_RXD
UART4_TXD
UART5_RTXD
GRP2GRP4GRP4GRP4
UART6_RXD
UART6_TXD
UART7_RXD
UART7_TXD
UART8_RXD
GRP2
UART8_TXD
AM3
OSCAR_BI_AP_TIME_SYNC_HOST_INT
AM4
AN3
NC
AL2
TRISTAR_TO_AP_DEBUG_UART0_RXD
AL1
AP_TO_TRISTAR_DEBUG_UART0_TXD
H30
H31
H32
H33
AL31
AM33
AL32
AL33
F30
STOCKHOLM_TO_AP_UART3_CTS_L
G30
AP_TO_STOCKHOLM_UART3_RTS_L
G31
STOCKHOLM_TO_AP_UART3_RXD
G32
AP_TO_STOCKHOLM_UART3_TXD
AE31
AF31
AE32
AE33
AG4
AM2
TRISTAR_TO_AP_ACC_UART6_RXD
AM1
AP_TO_TRISTAR_ACC_UART6_TXD
B30
NC
A30
AF2
AF1
AP_TO_VIBE_TRIG
BT_TO_AP_UART1_CTS_L
AP_TO_BT_UART1_RTS_L
BT_TO_AP_UART1_RXD
AP_TO_BT_UART1_TXD
BB_TO_AP_UART2_CTS_L
AP_TO_BB_UART2_RTS_L
BB_TO_AP_UART2_RXD
AP_TO_BB_UART2_TXD
WLAN_TO_AP_UART4_CTS_L
AP_TO_WLAN_UART4_RTS_L
WLAN_TO_AP_UART4_RXD
AP_TO_WLAN_UART4_TXD
AP_TO_TIGRIS_SWI
AP_TO_WLAN_DEVICE_WAKE
OSCAR_TO_AP_UART_RXD
AP_TO_OSCAR_UART_TXD
22
14
17
17
29
29
29
29
29
29
17 29
17 29
29
29
29
29
29
29
29
29
14
17
17
29
22
22
10
45_AP_TO_SPKAMP_I2S2_MCLK
16
BLUETOOTH
BASEBAND
STOCKHOLM
WIFI UART
GAS GAUGE
CODEC XSP & SPKR AMP
B
AP_TO_MESA_SPI_CLK
21
12
1/32W
01005
CODEC ASP
BLUETOOTH
ROOM=SOC
R0311
33.2
12
1/32W
01005
PP0303
P2MM-NSM
ROOM=SOC
BASEBAND
CODEC VSP
BOARD_ID2
BOARD_ID1
BOARD_ID0
CODEC
GRAPE
ROOM=SOC
R0340
12
45_AP_TO_CODEC_I2S0_MCLK_R
1%
45_AP_TO_CODEC_ASP_I2S0_BCLK
10
MF
AP_TO_CODEC_ASP_I2S0_LRCLK
10
CODEC_TO_AP_ASP_I2S0_DIN
10
AP_TO_CODEC_ASP_I2S0_DOUT
10
45_AP_TO_BT_I2S1_BCLK
29
AP_TO_BT_I2S1_LRCLK
29
BT_TO_AP_I2S1_DIN
29
AP_TO_BT_I2S1_DOUT
29
45_AP_TO_SPKAMP_I2S2_MCLK_R
1%
45_AP_TO_CODEC_XSP_I2S2_BCLK
10 16
MF
AP_TO_CODEC_XSP_I2S2_LRCLK
10 16
CODEC_TO_AP_XSP_I2S2_DIN
10 16
AP_TO_CODEC_XSP_I2S2_DOUT
10 16
ALS_TO_AP_INT_L
11
SM
1
29
45_AP_TO_BB_I2S3_BCLK
PP
AP_TO_BB_I2S3_LRCLK
29
BB_TO_AP_I2S3_DIN
29
AP_TO_BB_I2S3_DOUT
29
TRISTAR_TO_AP_INT
13 17
45_AP_TO_CODEC_VSP_I2S4_BCLK
10
AP_TO_CODEC_VSP_I2S4_LRCLK
10
CODEC_TO_AP_VSP_I2S4_DIN
10
AP_TO_CODEC_VSP_I2S4_DOUT
10
BOARD_ID2
26 27
BOARD_ID1
27
CODEC_TO_AP_SPI_MISO
10
AP_TO_CODEC_SPI_MOSI
10
AP_TO_CODEC_SPI_CLK
10
AP_TO_CODEC_SPI_CS_L
10
TOUCH_TO_AP_SPI_MISO
24
AP_TO_TOUCH_SPI_MOSI
24
AP_TO_TOUCH_SPI_CLK
24
AP_TO_TOUCH_SPI_CS_L
24
MESA_TO_AP_SPI_MISO
21
AP_TO_MESA_SPI_MOSI
21
AP_TO_MESA_SPI_CLK_R
MESA_TO_AP_INT
21
01005
0.00
D26
I2S0_MCK
U30
I2S0_BCLK
U31
I2S0_LRCK
U32
I2S0_DIN
U33
I2S0_DOUT
R30
I2S1_MCK
NC
P30
I2S1_BCLK
T30
I2S1_LRCK
R31
I2S1_DIN
T31
I2S1_DOUT
D25
I2S2_MCK
N30
I2S2_BCLK
N31
I2S2_LRCK
P32
I2S2_DIN
P33
I2S2_DOUT
AA2
I2S3_MCK
AA4
I2S3_BCLK
AA3
I2S3_LRCK
Y1
I2S3_DIN
Y2
I2S3_DOUT
AB32
I2S4_MCK
AB33
I2S4_BCLK
AA30
I2S4_LRCK
AA32
I2S4_DIN
AA33
I2S4_DOUT
AG1
SPI0_MISO
AG2
SPI0_MOSI
AG3
SPI0_SCLK
NC
AH3
SPI0_SSIN
NC
J3
SPI1_MISO
J2
SPI1_MOSI
J1
SPI1_SCLK
J4
SPI1_SSIN
F33
SPI2_MISO
F32
SPI2_MOSI
E32
SPI2_SCLK
E31
SPI2_SSIN
AD33
SPI3_MISO
AD32
SPI3_MOSI
AD31
SPI3_SCLK
AE30
SPI3_SSIN
U0201
POP-FIJI-1GB-DDR-B0
SYM 3 OF 13
GRP4
GRP2
GRP3
GRP1
GRP4GRP2
GRP3
BGA
I2C0_SCL
I2C0_SDA
I2C1_SCL
GRP3
I2C1_SDA
I2C2_SCL
I2C2_SDA
GRP2
I2C3_SCL
I2C3_SDA
SEP_I2C_SCL
SEP_I2C_SDA
SEP_SPI_SCLK
SEP_SPI_SSIN
GRP3
SEP_SPI_MISO
SEP_SPI_MOSI
SEP_GPIO0
ISP_UART0_RXD
GRP4
ISP_UART0_TXD
GRP3
DISP_VSYNC
CLK32K_OUT
GRP2
CPU_SLEEP_STATUS
NAND_SYS_CLK
R0305
2
2.2K
1/32W
01005
1
5%
MF
2
13 15
13 15
3
3
22
22
R0306
1.33K
1%
1/32W
MF
01005
R0310
24
10K
1/32W
01005
ROOM=SOC
1/32W
R0312
ROOM=SOC
1
R0308
1.33K
1/32W
01005
2
PP1V8
1
5%
MF
2
1/32W
0.00
12
ROOM=SOC
24 25 26 27
1
1%
MF
2
2 3 5 6 7
24 25 26 27
R0315
0.00
12
0%
ROOM=SOC
MF
01005
PMU_TO_AP_PRE_UVLO_L
PP1V8_SDRAM
NOSTUFF
1
R0307
10K
5%
1/32W
MF
01005
2
ROOM=SOC
MF0%
01005
P2MM-NSM
1
PP
SM
PP0301
P2MM-NSM
1
PP
SM
PP0302
AP_TO_I2C0_SCL
AP_BI_I2C0_SDA
AP_TO_I2C1_SCL
AP_BI_I2C1_SDA
AP_TO_I2C2_SCL
AP_BI_I2C2_SDA
P2MM-NSM
PP
SM
PP0305
P2MM-NSM
PP
SM
PP0304
10 11 12 13 15 20 23
3 4
10 12 13 14 15
17 26 29
AP_TO_PMU_SOCHOT1_L
13 15 17
13 15 17
14 16 21
14 16 21
11 20
11 20
D
C
13
B
13
ANTI-ROLLBACK EEPROM
ONSEMI EEPROM
APN:335S0894
PP1V8
2 3 5 6 7
10 11 12 13 15 20 23
24 25 26 27
AP_BI_EEPROM_I2C_SDA
3
AP_TO_EEPROM_I2C_SCL
3
1
R0316
2.2K
5%
1/32W
MF
01005
2
ROOM=E_SE
VCC
U0301
CAT24C08C4A
WLCSP
B1B2
SCLSDA
1
C0301
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=E_SE
1
R0317
2.2K
5%
1/32W
MF
01005
2
ROOM=E_SE
A
VSS
ROOM=E_SE
A2A1
63
REMOVED HOLD + MENU KEY
BUFFERS SINCE NOT NEEDED FOR FIJI
SYNC_MASTER=N56_MLB
PAGE TITLE
SOC:I/OS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Apple Inc.
R
SYNC_DATE=08/29/2013
DRAWING NUMBER
051-9903
REVISION
7.0.0
BRANCH
PAGE
4 OF 55
SHEET
4 OF 54
124578
876543
FIJI: VDDIOD,VDDIO18,VDD_VAR_SOC
12
JUST A FEW GNDS
C22
C23
C24
C25
C26
C27
C28
D10
D12
D13
D18
D19
D20
D21
D22
D23
D24
D27
E11
E15
E17
E19
E21
E23
E24
E25
E26
E27
E28
F10
F12
F14
F16
F18
F20
F22
F24
F27
F29
F31
G11
G13
G15
G17
G19
G21
G23
G25
G27
G28
H10
H12
H14
H17
H18
H20
H22
H24
H26
H27
H29
J11
J13
J16
J19
J21
J23
J25
J27
J28
U0201
POP-FIJI-1GB-DDR-B0
C3
C4
C5
C6
C9
D4
D5
D6
D8
D9
E6
E7
E9
VSS
F6
F8
G6
G9
H2
H5
H6
H7
H8
BGA
SYM 12 OF 13
VSS
AJ15
AJ18
AJ20
AJ22
AJ26
AJ28
AJ5
AK10
AK14
AK16
AK24
AK27
AK28
AK29
AK6
AK8
AL11
AL13
AL15
AL17
AL19
AL21
AL23
AL25
AL27
AL6
AL7
AL9
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM26
AM28
AM5
AM6
AM7
AM8
AM9
AN25
AN26
AN27
AN28
AN29
AN5
AN6
AP1
AP10
AP12
AP14
AP17
AP19
AP2
AP21
AP24
AP3
AP32
AP33
AP5
AP7
AR1
AR2
AR3
AR32
AR33
AR5
B1
B18
B2
B20
B32
B33
C10
C11
C15
C16
C17
C18
C19
C20
A1
A2
A32
A33
AA11
D
AA15
AA20
AA24
AA26
AA27
AA28
AA31
AA5
AA7
AA9
AB12
AB14
AB17
AB19
AB21
AB27
AB28
AB6
AB7
AB8
AC11
AC13
AC15
AC20
AC22
AC24
C
AC26
AC28
AC32
AC5
AC6
AC9
VSS
AD10
AD12
AD17
AD23
AD27
AD28
AD5
AD7
AD8
AE13
AE18
AE20
AE24
AE26
AE27
AE28
AE29
AE6
AE7
AF10
AF12
AF14
AF16
AF19
AF21
AF28
AF32
AG11
AG13
AG15
AG20
AG22
AG24
AG26
AG28
AH12
AH14
AH17
AH19
AH21
AH23
AH25
AH27
AH28
AJ11
AJ13
AE9
AF5
AF6
AF8
AG5
AG7
AG9
AH6
AH8
B
A
U0201
POP-FIJI-1GB-DDR-B0
BGA
SYM 11 OF 13
VSS
J29
J30
J31
J32
J9
K10
K12
K14
K17
K18
K20
K22
K24
K26
K28
K29
K30
K31
K32
K6
K8
L1
L11
L13
L15
L17
L19
L2
L21
L23
L25
L27
L29
L30
L31
L32
L5
L7
L9
M10
M12
M14
M18
M2
M20
M22
M24
M26
M28
M29
M3
M30
M31
M32
M4
M5
M6
M8
N11
N13
N15
N17
N19
N2
N21
N23
N25
N27
N29
N3
N32
N7
N9
P10
P12
P14
P16
P18
P2
P20
P22
P24
P26
P28
P29
P3
P31
P4
P5
P6
P8
C21
PP_VAR_SOC
12 26
1
C0508
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=SOC
ROOM=SOC
C0503
4.3UF
20%
4V
CERM
0402
143
2
ROOM=SOC
C0507
1UF
20%
4V
CERM
0402
143
2
ROOM=SOC
C0509
1UF
20%
4V
CERM
0402
143
2
ROOM=SOC
C0510
0.47UF
20%
6.3V
CERM
0402
143
2
VDDIOD, VDDIO18
CAPS FOR VDDIOD ARE SHARED WITH VDDQ
PP1V2
2 4
11 12 26
E16
E18
F15
F17
AK11
AK19
AK21
AK23
AK7
AK9
AL10
AL12
AL18
AL20
AL22
AL8
K27
L28
M27
N28
P27
R28
T27
U28
V27
W28
K7
L6
M7
N6
P7
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDRCA
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR0DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
VDDIOD_DDR1DQ
POP-FIJI-1GB-DDR-B0
SYM 9 OF 13
1.2V
U0201
BGA
1.8V
VDDIO18_GRP1
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP3
VDDIO18_GRP3
VDDIO18_GRP3
VDDIO18_GRP3
VDDIO18_GRP4
VDDIO18_GRP4
VDDIO18_GRP4
VDDIO18_GRP7
VDDIO18_PPN
VDDIO18_PPN
VDDIO18_PPN
VDDIO18_PPN
VDDIO18_PPN
J6
ROOM=SOC
1
C0501
AB5
AE5
AH5
T6
W5
AA29
AC29
AF29
AJ29
F25
F28
H28
T5
AK13
AK15
AK17
AL14
AL16
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=SOC
1.0UF
20%
6.3V
X5R
0201-1
PP1V8_ALWAYS
1
2
1
C0520
0.1UF
20%
4V
2
X5R
01005
ROOM=SOC
C0511
GRP7 POWERS GPIO11,12 (BUTTONS)
3
12 14 26
ROOM=SOC
C0502
1UF
20%
4V
CERM
0402
143
2
ROOM=SOC
C0506
0.47UF
20%
6.3V
CERM
0402
143
2
PP1V8
2 3 6 7
10 11 12 13 15 20 23 24
25 26 27
12
45_BUCK2_FB
63
VDD_SRAM, VDD_SOC
U0201
POP-FIJI-1GB-DDR-B0
G24
G26
H16
H19
H21
H23
H25
J15
J17
J18
J20
J22
J24
K16
K19
K21
K23
K25
L18
L20
L22
VDD_VAR_SOC
L24
0.90V - 0.95V
1.8A @ 105C
M19
M21
M23
M25
N18
N20
N22
N24
P19
P21
P23
P25
R20
R22
R24
T21
T23
T25
U20
U22
U24
V21
V23
V25
W20
W22
W24
W26
VDD_VAR_SOC_SENSE
SYNC_MASTER=N56_MLB
PAGE TITLE
SOC:GND,VDDIO18,VDDIOD,VDD_VAR_SOC
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
BGA
SYM 8 OF 13
Apple Inc.
R
PP0501
P2MM-NSM
SM
PP
ROOM=SOC
V10
V12
V14
V16
V18
V2
V20
V22
V24
V26
V28
V29
V3
V30
V31
V32
V4
V5
V6
V8
W11
W13
W15
W19
W2
W23
W25
VSS
W27
W29
W3
W30
W31
W32
W33
W6
W7
W9
Y10
Y12
Y14
Y17
Y21
Y28
Y29
Y5
Y6
Y8
VSS_SENSE
CPU_VSS_SENSE
AA13
SYNC_DATE=08/29/2013
DRAWING NUMBER
051-9903
REVISION
BRANCH
PAGE
SHEET
124578
7.0.0
5 OF 55
5 OF 54
SIZE
D
C
B
A
D
876543
FIJI: NAND + 12X17 NAND PKG
SUPPORT FOR PPN1.5 (1.8V IO) ONLY
12
D
1
1000MA
VCC
VSS
F2M6B6
OMIT_TABLE
ROOM=NAND
U0604
L3F6B2
C0609
0.47UF
20%
4V
2
X7S
0204
ROOM=NAND
N7
N1
LGA
A7
M2
1
C0623
100PF
5%
16V
2
NP0-C0G
01005
ROOM=NAND
PP1V2_NAND_VDDI
26
PP1V8
PP1V8
10 11 12 13 15 20 23
2 3 5 6 7
24 25 26 27
C
AP_TO_NAND_ANC0_CEN0_L
6
AP_BI_NAND_ANC0_IO<0>
6
AP_BI_NAND_ANC0_IO<1>
6
AP_BI_NAND_ANC0_IO<2>
6
AP_BI_NAND_ANC0_IO<3>
6
AP_BI_NAND_ANC0_IO<4>
6
AP_BI_NAND_ANC0_IO<5>
6
AP_BI_NAND_ANC0_IO<6>
6
AP_BI_NAND_ANC0_IO<7>
6
AP_TO_NAND_ANC0_ALE
6
AP_TO_NAND_ANC0_CLE
6
AP_TO_NAND_ANC0_WE_L
6
45_AP_TO_NAND_ANC0_RE_L
240
1%
MF
6
45_AP_BI_NAND_ANC0_DQS
6
45_AP_PPN0_ZQ
AP_TO_NAND_ANC_DQVREF
6
R0601
1/32W
01005
ROOM=SOC
1
R0607
100K
5%
1/32W
MF
01005
2
ROOM=SOC
AN16
PPN0_CEN0
AP16
PPN0_CEN1
NC
AN22
PPN0_IO0
AP22
PPN0_IO1
AN21
PPN0_IO2
AN20
PPN0_IO3
AN19
PPN0_IO4
AN18
PPN0_IO5
AP18
PPN0_IO6
AN17
PPN0_IO7
AP23
PPN0_ALE
AN23
PPN0_CLE
AR23
PPN0_WEN
AP20
PPN0_REN
AR18
PPN0_DQS
AR20
PPN0_ZQ
AR21
PPN0_VREF
U0201
POP-FIJI-1GB-DDR-B0
BGA
SYM 4 OF 13
PPN1_CEN0
PPN1_CEN1
PPN1_IO0
PPN1_IO1
PPN1_IO2
PPN1_IO3
PPN1_IO4
PPN1_IO5
PPN1_IO6
PPN1_IO7
PPN1_ALE
PPN1_CLE
PPN1_WEN
PPN1_REN
PPN1_DQS
PPN1_ZQ
PPN1_VREF
AN8
AN7
AN9
AN10
AN11
AP11
AN12
AN14
AN15
AP15
AP9
AP8
AR9
AN13
AP13
AR12
AR10
1
R0608
100K
5%
1/32W
MF
01005
2
ROOM=SOC
NC
45_AP_TO_NAND_ANC1_RE_L
2 3 5 6 7
10 11 12 13 15 20 23
24 25 26 27
AP_TO_NAND_ANC1_CEN0_L
AP_TO_NAND_ANC1_ALE
AP_TO_NAND_ANC1_CLE
AP_TO_NAND_ANC1_WE_L
45_AP_BI_NAND_ANC1_DQS
45_AP_PPN1_ZQ
AP_TO_NAND_ANC_DQVREF
6
6
6
6
6
R0602
6
240
1212
1%
1/32W
MF
01005
ROOM=SOC
6
THE TOTAL INDUCTANCE SEEN BY THE NAND SHOULD BE <2NH
1
C0625
100PF
5%
16V
2
NP0-C0G
01005
ROOM=NAND
AP_BI_NAND_ANC1_IO<0>
AP_BI_NAND_ANC1_IO<1>
AP_BI_NAND_ANC1_IO<2>
AP_BI_NAND_ANC1_IO<3>
AP_BI_NAND_ANC1_IO<4>
AP_BI_NAND_ANC1_IO<5>
AP_BI_NAND_ANC1_IO<6>
AP_BI_NAND_ANC1_IO<7>
B
PP0604
P2MM-NSM
ROOM=NAND
PP0605
P2MM-NSM
ROOM=NAND
1
C0624
2
6
6
6
6
6
6
6
6
1
C0601
220PF
10%
10V
X7R-CERM
01005
ROOM=NAND
AP_BI_NAND_ANC0_IO<0>
AP_BI_NAND_ANC0_IO<1>
AP_BI_NAND_ANC0_IO<2>
AP_BI_NAND_ANC0_IO<3>
AP_BI_NAND_ANC0_IO<4>
AP_BI_NAND_ANC0_IO<5>
AP_BI_NAND_ANC0_IO<6>
AP_BI_NAND_ANC0_IO<7>
SM
PP
SM
PP
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=NAND
NAND_TO_PP_TCKC
NAND_TO_PP_TMSC
1
C0615
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=NAND
1
C0622
220PF
10%
10V
2
X7R-CERM
01005
ROOM=NAND
G3
H2
J3
K2
L5
K6
J5
H6
G1
J1
L1
N3
N5
L7
J7
G7
OA0
OB0
VDDI
IO0-0
IO1-0
IO2-0
IO3-0
IO4-0
IO5-0
IO6-0
IO7-0
IO0-1
IO1-1
IO2-1
IO3-1
IO4-1
IO5-1
IO6-1
IO7-1
TCKC
TMSC
OB8
1
C0602
1UF
20%
4V
2
X6S
0204
ROOM=NAND
OC8
OE0
OF8
G0
OA8
OD8
VCCQ
DQS0*
R/B0*
DQS1*
R/B1*
NAND-1YNM-128GX8-TLC-PPN1.5-128G
VSSQ
G8
OF0
OC0
OE8
OD0
1
2
500MA
1
C0603
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=NAND
A5
CE0*
A3
CLE0
C1
ALE0
E3
WE0*
B4
RE0
NC
C7
RE0*
H4
DQS0
F4
NC
E5
C5
CE1*
C3
CLE1
D2
ALE1
E1
WE1*
D4
RE1
NC
D6
45_AP_TO_NAND_ANC1_RE_L
RE1*
M4
DQS1
K4
NC
E7
NC
G5
VREF
A1
ZQ
C0604
1UF
20%
4V
X6S
0204
ROOM=NAND
AP_TO_NAND_ANC0_CEN0_L
AP_TO_NAND_ANC0_WE_L
45_AP_TO_NAND_ANC0_RE_L
45_AP_BI_NAND_ANC0_DQS
AP_TO_NAND_ANC1_CEN0_L
AP_TO_NAND_ANC1_CLE
AP_TO_NAND_ANC1_ALE
AP_TO_NAND_ANC1_WE_L
45_AP_BI_NAND_ANC1_DQS
AP_TO_NAND_ANC_DQVREF
6
OMIT_TABLE
1
C0610
15UF
20%
6.3V
2
X5R
0402-1
ROOM=NAND
1
C0605
15UF
20%
6.3V
2
X5R
0402-1
ROOM=NAND
AP_TO_NAND_ANC0_CLE
AP_TO_NAND_ANC0_ALE
NAND_TO_PP_RB
45_NAND_PPN_ZQ
1
2
C0606
15UF
20%
6.3V
X5R
0402-1
ROOM=NAND
6
6
6
6
6
6
6
6
6
6
6
6
ROOM=NAND
1
R0609
243
1%
1/32W
MF
01005
2
OMIT_TABLE
1
C0611
15UF
20%
6.3V
2
X5R
0402-1
ROOM=NAND
1
2
PP0600
SM
PP
OMIT_TABLE
1
C0613
15UF
20%
6.3V
2
X5R
0402-1
ROOM=NAND
C0612
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=NAND
P2MM-NSM
1
C0616
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=NAND
1
C0640
1.0UF
20%
6.3V
2
X5R
0201-1
NOTE:C0640,C0641 ADDED FOR UF NEEDS
ROOM=NAND
1
C0607
0.01UF
10%
6.3V
2
X5R
01005
ROOM=SOC
1
C0608
0.01UF
10%
6.3V
2
X5R
01005
ROOM=SOC
OMIT_TABLEOMIT_TABLE
1
C0614
15UF
20%
6.3V
2
X5R
0402-1
ROOM=NAND
1
2
1
C0641
1.0UF
20%
6.3V
2
X5R
0201-1
C0617
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=NAND
1
2
1
R0603
50K
1%
1/32W
MF
01005
2
ROOM=SOC
1
R0604
50K
1%
1/32W
MF
01005
2
ROOM=SOC
1
C0633
15UF
20%
6.3V
2
X5R
0402-1
ROOM=NAND
C0620
100PF
5%
16V
NP0-C0G
01005
ROOM=NAND
PP1V8
1
2
1
C0621
220PF
10%
10V
2
X7R-CERM
01005
ROOM=NAND
2 3 5 6 7
24 25 26 27
PP3V0_NAND
OMIT_TABLE
C0634
15UF
20%
6.3V
X5R
0402-1
ROOM=NAND
PP1V8
10 11 12 13 15 20 23
12 26
2 3 5 6 7
24 25 26 27
10 11 12 13 15 20 23
D
C
B
NOTE: IO<6> PREFERRED BY MATT BYOM (N51)
(IS A STATUS READY BIT)
AP_BI_NAND_ANC0_IO<6>
45_AP_TO_NAND_ANC0_RE_L
45_AP_BI_NAND_ANC0_DQS
6
6
6
ROOM=SOC
ROOM=SOC
ROOM=SOC
PP0601
P4MM
SM
1
PP
PP0602
P4MM
SM
1
PP
PP0603
P4MM
SM
1
PP
A
63
NOTE: NAND PADS SHOULD BE SHIELDED FROM TRACES WITH A GROUND PLANE
SYNC_MASTER=N56_MLB
PAGE TITLE
SOC:NAND
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=08/29/2013
DRAWING NUMBER
051-9903
REVISION
7.0.0
BRANCH
PAGE
6 OF 55
SHEET
6 OF 54
124578
SIZE
A
D
876543
FIJI: HIGH SPEED DIG (CAM,LCD,LPDP,PCIE)
12
20
22
22
16
24
13 22
20 24
24
29
29
D
C
B
D
PP0V95_FIXED_SOC
4
12 26
NOTE: NEED TO EVALUATE PI FOR PP1V0.
CONCERN OVER SHARING IT WITH MIPI AND
PCIE REFCLK WITHOUT A FILTER.
NOTE: IS A FERRITE NEEDED? THERE ARE DCR CONCERNS.
R0712
12
0.00
01005
ROOM=SOC
NOTE: PLACE NEAR THE PCIE PINS, NOT LPDP.
PP1V0
7
12 26
1
C0713
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=SOC
45_PCIE_RESREF
1
R0710
200
1%
1/32W
MF
01005
2
ROOM=SOC
1
2
AR30
NC
AP30
NC
AR26
NC
AP26
NC
AR27
NC
AP27
NC
AR28
NC
AP28
NC
AR29
NC
AP29
NC
AL28
NC
AK26
NC
B11
NC
A11
NC
B12
NC
A12
NC
A13
NC
B13
NC
AB2
NC
A10
B10
A9
B9
A14
B14
AB3
A8
C0708
0.1UF
20%
4V
X5R
01005
ROOM=SOC
LPDP_AUX_P
LPDP_AUX_N
LPDP_TX0P
LPDP_TX0N
LPDP_TX1P
LPDP_TX1N
LPDP_TX2P
LPDP_TX2N
LPDP_TX3P
LPDP_TX3N
LPDP_CAL_DRV_OUT
LPDP_CAL_VSS_EXT
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
PCIE_REF_CLK0_P
PCIE_REF_CLK0_M
PCIE_CLKREQ0_N
PCIE_RX1_P
PCIE_RX1_M
PCIE_TX1_P
PCIE_TX1_M
PCIE_REF_CLK1_P
PCIE_REF_CLK1_M
PCIE_CLKREQ1_N
PCIE_RESREF
26
PP0V95_FIXED_SOC_PCIE
1
C0712
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=SOC
1
C0711
0.1UF
20%
4V
2
X5R
01005
ROOM=SOC
PWRTERM2GND
PWRTERM2GND
PWRTERM2GND
AM27
AM25
AL26
AL24
PWRTERM2GND
POP-FIJI-1GB-DDR-B0
VDDA10_LPDP3
VDDA10_LPDP2
VDDA10_LPDP1
VDDA10_LPDP0
1.0V
24MA
BGA
SYM 6 OF 13
E13
D11
VDD095_VPTX0_PCIE
VDD095_VPTX1_PCIE
0.95V
U0201
RF TEAM: CONFIRMED PD NEEDED
F13
D14
E12
VDD18_VPH_PCIE
VDD095_VP_PCIE
VDDA10_REFCLK_PCIE
1.8V1.0V
PCIE_REF_PAD_CLK_P
PCIE_REF_PAD_CLK_M
GPIO39/PCIE_PERST0_N
GPIO43/PCIE_PERST1_N
R0719
PP1V8
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
ULPI_CLK
ULPI_DIR
ULPI_NXT
ULPI_STP
EDP_HPD
2 3 5 6 7
10 11 12 13 15 20 23
24 25 26 27
H4
AP_TO_OSCAR_SWDCLK_1V8
H3
AP_BI_OSCAR_SWDIO_1V8
G3
NC
G4
F2
NC
G2
NC
F3
NC
F4
G5
OSCAR_TO_PMU_HOST_WAKE
E3
LCM_TO_AP_HIFA_BSYNC
F1
AP_TO_TOUCH_RESET_L
E4
G29
AP_TO_STOCKHOLM_EN
C13
NC
C12
NC
AK5
NC
AL4
AP_TO_WLAN_PCIE1_RST_L
AP_TO_LEDDRV_EN
TOUCH_TO_AP_INT_L
AP_TO_LCM_RESET_L
1
R0719
100K
5%
1/32W
MF
01005
2
A
SYNC_MASTER=N56_MLB
PAGE TITLE
SOC:CAM,LCD,LPDP,PCIE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
63
SYNC_DATE=08/26/2013
DRAWING NUMBER
051-9903
REVISION
7.0.0
BRANCH
PAGE
8 OF 55
SHEET
8 OF 54
124578
SIZE
A
D
876543
L67 AUDIO CODEC
12
D
AUDIO I/O
D
(ANALOG MIC IN, DIG MIC IN, HPOUT, LINEOUT, RECEIVER OUT, MIKEYBUS)
C0922
0.1UF
12
X5R20%
01005
4V
LOWERMIC1_TO_CODEC_P
9
VOICE MIC
CODEC_TO_HPHONE_HS4
18
9
C
HEADPHONE MIC
CODEC_TO_HPHONE_HS3
9
18
ANC REF MIC
18
LOWERMIC1_TO_CODEC_N
9
18
ROOM=CODEC
R0915
1.33K
12
1%
1/32W
MF
01005
NO_XNET_CONNECTION=TRUE
C0904
NO_XNET_CONNECTION=TRUE
ROOM=CODEC
R0950
1.33K
12
1%
1/32W
MF
01005
NO_XNET_CONNECTION=TRUE
REARMIC2_TO_CODEC_P
8 9
REARMIC2_TO_CODEC_N
8 9
ROOM=CODEC
220PF
X7R-CERM
01005
NOSTUFF
1
C0927
56PF
5%
16V
2
NP0-C0G
01005
ROOM=CODEC
1
10%
10V
2
NOSTUFF
1
C0942
56PF
5%
16V
2
NP0-C0G
01005
ROOM=CODEC
NOSTUFF
1
C0930
56PF
5%
16V
2
NP0-C0G
01005
ROOM=CODEC
NOSTUFF
1
C0943
56PF
5%
16V
2
NP0-C0G
01005
ROOM=CODEC
EXTMIC_TO_CODEC_P
EXTMIC_TO_CODEC_N
B
FRONTMIC3_TO_CODEC_P
9
ANC ERROR MIC
11
FRONTMIC3_TO_CODEC_N
9
11
1
2
NOSTUFF
C0946
56PF
5%
16V
NP0-C0G
01005
ROOM=CODEC
NOSTUFF
1
C0947
56PF
5%
16V
2
NP0-C0G
ROOM=CODEC
01005
ROOM=CODEC
C0923
0.1UF
12
X5R20%
01005
4V
ROOM=CODEC
C0920
0.1UF
12
20%
X5R
01005
4V
ROOM=CODEC
C0921
0.1UF
12
20%X5R
01005
4V
ROOM=CODEC
C0940
0.1UF
12
X5R
20%
01005
4V
ROOM=CODEC
C0941
0.1UF
12
20%X5R
01005
4V
ROOM=CODEC
C0944
0.1UF
12
20%
X5R
01005
4V
ROOM=CODEC
C0945
0.1UF
12
20%
X5R
01005
4V
ROOM=CODEC
LOWERMIC1_TO_AIN1_P
LOWERMIC1_TO_AIN1_N
EXTMIC_TO_AIN2_P
EXTMIC_TO_AIN2_N
REARMIC2_TO_AIN5_P
REARMIC2_TO_AIN5_N
FRONTMIC3_TO_AIN6_P
FRONTMIC3_TO_AIN6_N
LOWERMIC1_TO_DIN1_SD
LOWERMIC1_TO_DIN1_SCLK
MIC2MIC3_TO_DIN2_SD
MIC2MIC3_TO_DIN2_SCLK
ROOM=CODEC
U0900
WLCSP
G2
AIN1+
G1
AIN1-
F4
AIN2+
F3
AIN2-
F2
AIN3+
NC
F1
AIN3-
NC
E4
AIN4+
NC
E3
AIN4-
NC
E1
AIN5+
E2
AIN5-
D1
AIN6+
D2
AIN6-
D3
AIN7+
NC
D4
AIN7-
NC
C1
AIN8+
NC
C2
AIN8-
NC
A6
DMIC1_SD
B6
DMIC1_SCLK
A3
DMIC2_SD
A2
DMIC2_SCLK
PRIMARY
(VOICE) MIC
HEADPHONE
MIC
ANALOG
MIC IN
ANC
REF MIC2
ANC
REF MIC1
ANC
ERROR MIC
ANALOG
LINEIN
ANALOG
LINEIN
SYM 1 OF 3
CS42L67-CWZR-A1
AOUT1+
AOUT1-
AOUT2+
AOUT2-
LINEOUT_REF
LINEOUTA
LINEOUTB
HPOUTA
HPOUTB
HS3_REF
HS4_REF
HPDETECT
MBUS_REF
HS3
HS4
K7
L7
L5
K5
K8
J8
H8
J9
K9
K1
L2
L9
L8
G8
G10
DN
F10
DP
F11
CODEC_TO_RCVR_P
CODEC_TO_RCVR_N
CODEC_TO_HAC_P
CODEC_TO_HAC_N
NC
NC
CODEC_TO_HPHONE_HS3
CODEC_TO_HPHONE_HS4
CODEC_TO_HPHONE_HS3_REF
CODEC_TO_HPHONE_HS4_REF
HPHONE_TO_CODEC_DET
90_CODEC_BI_TRISTAR_MIKEYBUS_L67_N
90_CODEC_BI_TRISTAR_MIKEYBUS_L67_P
CODEC_MBUS_REF
11
11
11
11
CODEC_TO_HPHONE_L
56PF
5%
16V
01005
20.0
ROOM=CODEC
20.0
ROOM=CODEC
CODEC_TO_HPHONE_R
1
2
MF
01005
MF
01005
ROOM=CODEC
C0952
100PF
12
NP0-C0G
01005
ROOM=CODEC
1
C0953
100PF
5%
10V
2
NP0-C0G
01005
C0954
100PF
12
NP0-C0G
01005
ROOM=CODEC
9
18
18
9
18
18
NOSTUFF
C0950
56PF
18
18
NP0-C0G
01005
ROOM=CODEC
NOSTUFF
1
C0951
5%
16V
2
NP0-C0G
ROOM=CODEC
R0902
12
5%
1/32W
R0903
12
5%
1/32W
18
18
5%
10V
NOSTUFF
5%
10V
90_CODEC_BI_TRISTAR_MIKEYBUS_N
90_CODEC_BI_TRISTAR_MIKEYBUS_P
NO_XNET_CONNECTION=TRUE
17
17
C
B
ROOM=SOC
LOWERMIC1_TO_CODEC_P
9
18
LOWERMIC1_TO_CODEC_N
9
18
REARMIC2_TO_CODEC_P
8 9
NO_XNET_CONNECTION=TRUE
NO_XNET_CONNECTION=TRUE
NO_XNET_CONNECTION=TRUE
A
FRONTMIC3_TO_CODEC_P
9
11
REARMIC2_TO_CODEC_N
8 9
FRONTMIC3_TO_CODEC_N
9
11
NO_XNET_CONNECTION=TRUE
NO_XNET_CONNECTION=TRUE
NO_XNET_CONNECTION=TRUE
R0941
NOSTUFF
12
0.00
01005
R0942
ROOM=SOC
NOSTUFF
12
0.00
01005
ROOM=SOC
R0943
NOSTUFF
12
0.00
01005
R0944
ROOM=SOC
ROOM=SOC
ROOM=SOC
01005
01005
01005
NOSTUFF
NOSTUFF
NOSTUFF
12
0.00
R0945
12
0.00
R0946
12
0.00
63
SYNC_MASTER=N61_MLB
PAGE TITLE
AUDIO:L67 CODEC (1/2)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=08/26/2013
DRAWING NUMBER
051-9903
REVISION
7.0.0
BRANCH
PAGE
9 OF 55
SHEET
9 OF 54
124578
SIZE
A
D
876543
L67 AUDIO CODEC
12
D
C
KEEP THESE CAPS AT CODEC PINS
ROOM=CODEC
1
R1000
2.21K
1%
1/32W
MF
01005
2
ROOM=CODEC
1
C1037
1.0UF
20%
6.3V
2
X5R
0201-1
1
C1038
4.7UF
20%
6.3V
2
B
X5R-CERM1
402
ROOM=CODEC
ROOM=BUTTON_B2B
XW1002
SHORT-10L-0.1MM-SM
21
PCB NOTE:
PLACE NEAR J1111 GND PIN
NOTE: C1022 WAS REDUCED TO 2.2UF BECAUSE OF
ADDITIONAL NEARBY VCC MAIN CAPS
12 14 15 16 17 23 26 31 39 48
51 52
2 3 5 6 7
11 12 13 15 20 23
24 25 26 27
3 4
10 12 13 14 15 17 26 29
12 16 26
18 26
6.3V
20%
402
1
2
1
2
18
CODEC_AGND
PP_CODEC_TO_MIC1_BIAS
MIC1_BIASFILT_RET
ROOM=CODEC
C1020
1.0UF
20%
6.3V
X5R
0201-1
26
PP_EXTMIC_BIAS_IN
26
PP_EXTMIC_BIAS
26
PP_EXTMIC_BIAS_FILT_IN
26
PP_EXTMIC_BIAS_FILT
ROOM=CODEC
1
C1015
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=CODECROOM=CODEC
C1018
4.7UF
X5R-CERM1
FRONTMIC3_BIAS_FILT_GND
PP_VCC_MAIN
PP1V8
PP1V8_SDRAM
PP1V8_VA_L19_L67
10
ROOM=CODEC
1
C1000
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=CODEC
1
C1074
2.2UF
20%
6.3V
2
X5R
0201-1
CODEC_AGND
10
C1021
4.7UF
ROOM=CODEC
X5R-CERM1
11 26
PP_CODEC_TO_FRONTMIC3_BIAS
FRONTMIC3_TO_CODEC_RET_FILT
8
26
PP_CODEC_TO_REARMIC2_BIAS
REARMIC2_TO_CODEC_RET_FILT
1
C1019
4.7UF
2
20%
6.3V
X5R-CERM1
402
REARMIC2_BIAS_FILT_GND
20%
6.3V
402
12
1
C1022
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=CODEC
1
C1013
2
1
C1014
2
1
C1012
2
ROOM=CODEC
MIC1_BIAS_FILT
POWER, MICBIAS
1
2
PCB: C1021 AT U0921.L6
0.1UF
20%
4V
X5R
01005
ROOM=CODEC
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=CODEC
2.2UF
20%
6.3V
X5R
0201-1
J5
J6
L4
L3
K4
K3
H7
G6
H6
H5
ROOM=BUTTON_B2B
XW1004
SHORT-10L-0.1MM-SM
C1031
0.1UF
20%
6.3V
X5R-CERM
01005
ROOM=CODEC
1
C1016
0.1UF
20%
4V
2
X5R
01005
ROOM=CODEC
MIC1_BIAS
MIC1_BIAS_FILT
MIC2_BIAS_IN
MIC2_BIAS
MIC2_BIAS_FILT_IN
MIC2_BIAS_FILT
MIC3_BIAS
MIC3_BIAS_FILT
MIC4_BIAS
MIC4_BIAS_FILT
21
1
C1075
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=CODEC
J1
VA
G11
VCP
B10
A11
VD
U0900
WLCSP
SYM 2 OF 3
GNDD
A10
H11B9L6
ROOM=CODEC
VP
VL
VPROG_CP
FLYP
FLYC
26
FLYN
+VCP_FILT
GNDCP0
GNDCP1
-VCP_FILT
SPEAKER_VQ
CS42L67-CWZR-A1
GNDP
26
FILT+
FILT-
GNDA
GNDHS0
GNDHS1
L1
K2
J11
26
PP_CODEC_VHP_FLYP
G9
26
PP_CODEC_VHP_FLYC
H10
J10
PP_CODEC_VHP_FLYN
H9
K11
26
K10
L11
L10
26
J7
26
PP_CODEC_SPKR_VQ
K6
H1
PP_CODEC_FILT+
H2
C1024
J2
CERM-X5R
ROOM=CODEC
PP_CODEC_VCPFILT+
PGND_CODEC_GNDCP
PP_CODEC_VCPFILT-
1
10UF
20%
6.3V
2
KEEP THIS CAP AT CODEC PINS
0402-9
2
ROOM=CODEC
XW1003
SHORT-10L-0.1MM-SM
1
KEEP THESE CAPS AT CODEC PINS
ROOM=CODEC
1
C1032
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=CODEC
1
C1033
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=CODEC
1
C1034
4.7UF
20%
6.3V
2
X5R-CERM1
402
KEEP THIS CAP AT CODEC PINS
CODEC_AGND
KEEP THESE CAPS AT CODEC PINS
XW1048
SM
12
ROOM=CODEC
10
ROOM=CODEC
1
C1025
4.7UF
20%
6.3V
2
X5R-CERM1
402
1
C1029
4.7UF
20%
6.3V
2
X5R-CERM1
402
ROOM=CODEC
10 12 13 14 15 17 26 29
3 4
PP1V8_SDRAM
ROOM=CODEC
1
R1045
1.00K
5%
1/32W
MF
01005
2
DIGITAL SYSTEM I/O
45_AP_TO_CODEC_I2S0_MCLK
3
45_AP_TO_CODEC_ASP_I2S0_BCLK
3
AP_TO_CODEC_ASP_I2S0_LRCLK
3
AP_TO_CODEC_ASP_I2S0_DOUT
3
CODEC_TO_AP_ASP_I2S0_DIN
3
45_AP_TO_CODEC_VSP_I2S4_BCLK
3
AP_TO_CODEC_VSP_I2S4_LRCLK
3
AP_TO_CODEC_VSP_I2S4_DOUT
3
CODEC_TO_AP_VSP_I2S4_DIN
3
45_AP_TO_CODEC_XSP_I2S2_BCLK
3
16
AP_TO_CODEC_XSP_I2S2_LRCLK
3
16
AP_TO_CODEC_XSP_I2S2_DOUT
3
16
CODEC_TO_AP_XSP_I2S2_DIN
3
16
AP_TO_CODEC_SPI_CS_L
3
AP_TO_CODEC_SPI_CLK
3
AP_TO_CODEC_SPI_MOSI
3
CODEC_TO_AP_SPI_MISO
3
CODEC_TO_AP_INT_L
3
CODEC_TO_PMU_MIKEY_INT_L
13
CODEC_RESET_L
TSTO MUST BE NC
A9
MCLK
WEAK INT PD
C10
ASP_SCLK
B11
ASP_LRCK
C9
ASP_SDIN
A8
ASP_SDOUT
ALL ASP PINS:WEAK INT PD
E9
VSP_SCLK
E8E7
VSP_LRCK/FSYNC
D10F5
VSP_SDIN
D11
VSP_SDOUT
ALL VSP PINS:WEAK INT PD
B8
XSP_SCLK
B7
XSP_LRCK/FSYNC
C7
XSP_SDIN/DAC2B_MUTE
A7
XSP_SDOUT
ALL XSP PINS:WEAK INT PD
B5
CS*
B4
CCLK
B3
CDIN
A4
CDOUT
WEAK INT PD
L67 WEAK INT PD = 550K - 2450K
G4
INT*
G5
WAKE*
G3
RESET*
E10
NC
E11
NC
A5
NC
C6
TSTO
NC
C8
NC
D6
NC
U0900
WLCSP
SYM 3 OF 3
CS42L67-CWZR-A1
GND
TSTI
ROOM=CODEC
A1
C5
B1
F9
D5
D7
E5
E6
F6
F7
F8
G7
H3
H4
J3
J4
D8
D9
B2
C3
C4
C11
D
C
B
A
SYNC_MASTER=N61_MLB
PAGE TITLE
AUDIO:L67 CODEC (2/2)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
C1271: WIFI MODULE
C1272: AP PMU MODULE
BB PMU MODULE:RF SIDE
QPOET MODULE:RF SIDE
1
2
1
2
1
2
1
2
C1220
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=PMU
C1251
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=PMU
C1285
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=PMU
C1271
100PF
NP0-C0G
01005
ROOM=WIFI
1
C1200
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=PMU
1
C1225
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=PMU
1
C1298
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=PMU
1
5%
16V
2
C1272
100PF
NP0-C0G
01005
ROOM=PMU
5%
16V
1
C1217
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=PMU
1
C1260
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=PMU
B
5%
1/32W
MF-LF
01005
ROOM=PMU
1
2
1
2
1
2
26
14 25
C1218
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=PMU
C1263
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=PMU
C1264
10UF
20%
6.3V
CERM-X5R
0402-9
ROOM=PMU
PP5V0_USB_TO_PMU
CHARGER_VBATT_SNS
C1250
2.2UF
20%
6.3V
X5R
0201-1
ROOM=PMU
1
C1267
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=PMU
1
C1266
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
2 4
12 23 26
PP1V2_SDRAM
1
C1278
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
NC
NC
NC
NC
NC
NC
NC
NC
NC
M20
M21
N20
N21
P20
P21
H20
H21
K10
VBAT
L16
ACT_DIO
L20
L21
J20
J21
K7
VCC_MAIN_S
A4
B4
C4
F1
F2
K1
K2
E20
E21
A17
B17
C17
N9
N8
A8
B8
C8
A13
B13
C13
N13
VDD_LDO6
P14
VDD_LDO2
H17
VDD_LDO1_3
J17
VDD_LDO4_13
N15
VDD_LDO5
L17
VDD_LDO7_8
L2
VDD_LDO10
N11
VDD_LDO9_11
P12
VDD_VIB
R12
VIB
N12
VIB_PWM_EN
C1
XTAL1
D1
XTAL2
G9
VSS_RTC
VCENTER
VBUS
IBAT
CHG_LX
VCC_MAIN
VDD_BUCK1
VDD_BUCK2
VDD_BUCK3
VDD_BUCK4
VDD_BUCK5
VDD_BUCK6
VDD_BYP_BUCK6
VDD_BUCK001
VDD_BUCK023
45_PMU_TO_XTAL_OSC32
ROOM=PMU
C1276
18PF
CERM
01005
32.768K-20PPM-12.5PF
1
5%
16V
2
2.0X1.2X0.60-SM1
ROOM=PMU
Y1200
21
45_XTAL_TO_PMU_OSC32
ROOM=PMU
1
C1283
18PF
5%
16V
2
CERM
01005
A
U1202
D2186AZE0FJAVAC
FCCSP-N56-N61
SYM 1 OF 3
BAT/USB
BUCK
BUCK INPUT
LDO INPUT
VIBE
XTAL
LDO
SPEC REQUIRES 10NF,
VPUMP RUNS AT 4.6V
ROOM=PMU
BUCK0_LX0
BUCK0_LX1
BUCK0_LX2
BUCK0_LX3
BUCK0_FB
BUCK1_LX0
BUCK1_LX1
BUCK1_FB
BUCK2_LX
BUCK2_FB
BUCK3_LX
BUCK3_FB
BUCK3_SW1
BUCK3_SW2
BUCK3_SW3
VBUCK3_SW
BUCK4_LX
BUCK4_FB
VBUCK4_SW
BUCK4_SW1
BUCK4_SW2
BUCK5_LX0
BUCK5_LX1
BUCK5_FB
BUCK6_LX
BUCK6_FB
BUCK6_BYP
(50MA)
(50MA)
(50MA)
(50MA)
(1000MA)
(150MA)
(250MA)
(250MA)
(250MA)
VLDO9_FB
(100MA)
(250MA)
(5MA)
(250MA)
VPUMP CAP:
30% DERATED.
VLDO1
VLDO2
VLDO3
VLDO4
VLDO5
VLDO6
VLDO7
VLDO8
VLDO9
VLDO10
VLDO11
VLDO12
VLDO13
VPUMP
26
B7
C7
A9
26
B9
C9
A12
26
B12
C12
A14
26
B14
C14
E7
A3
26
B3
C3
A5
26
B5
C5
E4
G1
G2
F4
J1
J2
K6
P5
N5
P6
R6
P7
R7
N6
N7
F20
F21
E18
N3
N4
M2
N2
L5
A16
B16
C16
A18
B18
C18
C21
R9
NC
L11
NC
R8
NC
2.5-3.3V +/-77.5MV
F18
1.2-1.9V +/-42.5MV
R14
2.5-3.3V +/-75MV
G18
2.5-3.6V +/-75MV
H18
2.5-3.6V +/-75MV
R15
1.2-3.6V +/-82.5MV
R13
2.5-3.6V +/-75MV
K18
2.5-3.6V +/-70MV
L18
NC
2.5-3.6V +/-71.25MV
R10
P10
PP2V9_LDO9
0.6-1.4V +/-25MV
L1
2.5-3.6V +/-82.5MV
R11
FIXED 1.8V, +/-5%
L6
2.5-3.6V +/-71.25MV
J18
R5
45_PMU_VPUMP
PP_BUCK0_LX0
DIDT=TRUE
PP_BUCK0_LX1
DIDT=TRUE
PP_BUCK0_LX2
DIDT=TRUE
PP_BUCK0_LX3
DIDT=TRUE
45_BUCK0_FB
PP_BUCK1_LX0
DIDT=TRUE
PP_BUCK1_LX1
DIDT=TRUE
45_BUCK1_FB
PP_BUCK2_LX
26
DIDT=TRUE
45_BUCK2_FB
26
PP_BUCK3_LX
DIDT=TRUE
45_BUCK3_FB
PP1V8_GRAPE
PP1V8_OSCAR
PP_BUCK4_LX
26
DIDT=TRUE
45_BUCK4_FB
PP1V2_OSCAR
26
PP_BUCK5_LX0
DIDT=TRUE
26
PP_BUCK5_LX1
DIDT=TRUE
45_BUCK5_FB
1
C1208
0.1UF
20%
6.3V
2
X5R-CERM
01005
ROOM=PMU
0.47UH-20%-3.3A-0.065OHM
0.47UH-20%-3.3A-0.065OHM
4
4
5
PP1V8
2 3 5 6 7
25 26 27
24 26
19 22 26
PP1V2
2 4 5
22 26
4
1
C1270
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
12
12
MCMK2012TR47M-SM
1UH-3.0A-0.059OHM
12
L1212
12
MCMK2012TR47M-SM
SAME POLARITY
1UH-3.0A-0.059OHM
12
0.47UH-20%-3.3A-0.065OHM
12
MCMK2012TR47M-SM
1.0UH-20%-2.4A-0.075HM
12
PIFE20161T-SM
10 11 13 15 20 23 24
11 26
1
C1229
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
L1209
PIFA20161B
L1210
L1211
PIFA20161B
L1213
PIFA20161B
L1214
L1215
1
C1212
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
ROOM=PMU
ROOM=PMU
ROOM=PMU
ROOM=PMU
ROOM=PMU
ROOM=PMU
ROOM=PMU
1
C1284
1.0UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
1
C1290
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1222
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1203
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
2
C1299
2.2UF
20%
6.3V
X5R
0201-1
ROOM=PMU
1
C1292
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1245
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
0V9/0V95
1
C1227
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
0V9/0V95
1
C1223
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1207
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
0V775/0V95/1V0
1
C1294
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1262
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1210
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1275
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1235
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1228
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
1
C1226
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
PP_VAR_SOC
1
C1289
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
PP_CPU
PP_GPU
4
26
4
26
5
26
1
2
C1242
1.0UF
20%
6.3V
X5R
0201-1
7.6A MAX
3.45A MAX
1.8A MAX
ROOM=PMU
1.0UH-20%-2.4A-0.075HM
H7 VDD_CPU
SHORT-10L-0.1MM-SM
H7 VDD_GPU
H7 VAR
PP1V8_VA_L19_L67
PP3V0_PROX_IRLED
1
C1232
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=PMU
L1216
12
PIFE20161T-SM
ROOM=PMU
XW1218
21
ROOM=PMU
1.0UH-20%-2.4A-0.075HM
ROOM=PMU
1.0UH-20%-2.4A-0.075HM
0.47UH-30%-2.7A-0.065OHM
PP3V3_USB
PP3V0_TRISTAR
PP3V0_IMU
PP3V0_NAND
PP3V3_ACC
PP3V0_PROX_ALS
PP1V0
PP1V8_ALWAYS
PP3V0_MESA
1
C1291
0.1UF
20%
4V
2
X5R
01005
ROOM=PMU
PCB:PLACE C1297 NEAR C1263
100PF
NP0-C0G
01005
ROOM=PMU
1
C1296C1297
100PF
5%
16V
2
ROOM=PMU
1
2
PCB:PLACE C1296 NEAR L1216
L1217
12
PIFE20161T-SM
XW1220
SHORT-10L-0.1MM-SM
ROOM=PMU
21
L1218
12
PIFE20161T-SM
L1219
12
MCKK2012-SM
2
26
10 16 26
15 17 26 29
19 26
6
26
17 26
11 26
SYNC_MASTER=N56_MLB
7
26
PAGE TITLE
11 26
3 5
14 26
21 26
1
2
NOTICE OF PROPRIETARY PROPERTY:
C1219
THE INFORMATION CONTAINED HEREIN IS THE
2.2UF
PROPRIETARY PROPERTY OF APPLE INC.
20%
6.3V
THE POSESSOR AGREES TO THE FOLLOWING:
X5R
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
0201-1
ROOM=PMU
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
1
C1214
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
ROOM=PMU
ROOM=PMU
SOC USB PHY (25 MA)
SPEAKER AMP, CODEC VA (2.5 MA L1419, 3MA L67)
TRISTAR VDH, WIFI_FLEX PAC (? MA)
GYRO, ACCEL, COMPASS (? MA)
NAND (? MA)
ACCESSORY POWER (? MA)
PROX/ALS VDD (PROX: 0.75/1.2 MA ALS: 0.175/0.25 MA [TYP/MAX])
REAR CAM AUTO FOCUS (120MA PEAK, PROBABLY CAP AT 80MA)
REAR/FRONT CAM AVDD (? MA)
SOC 1V0 MIPI, USB_DVDD, DP (71 MA TOTAL)
PROX LED (102 MA TYP)
ALWAYS ON 1V8 (? MA)
1
2
POWER:ADI(1/2)
R
1
C1293
15UF
5%
20%
16V
01005
1
C1216
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
6.3V
2
X5R
0402-1
ROOM=PMU
NP0-C0G
PCB:PLACE C1270 NEAR L1217
PP0V95_FIXED_SOC
1
C1240
15UF
20%
6.3V
X5R
0402-1
ROOM=PMU
C1202
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
TO DO: REVIEW ALL LDO ASSIGNMENTS
(CHECK VDD_LDO INPUT SOURCE,
CHECK CURRENT RATING FOR LDO OUT
VS. LOAD REQUIREMENT AT DESTINATION, ETC)
NOTE: 3V +/- 5% PER EUGENE
Apple Inc.
63
12
PP1V8_SDRAM
1
2
ROOM=PMU
PP1V2_SDRAM
1
2
1
2
3 4
26 29
C1243
15UF
20%
6.3V
X5R
0402-1
2 4
C1288
100PF
5%
16V
NP0-C0G
01005
ROOM=PMU
4 7
1
C1209
15UF
20%
6.3V
2
X5R
0402-1
ROOM=PMU
SYNC_DATE=08/29/2013
DRAWING NUMBER
051-9903
REVISION
BRANCH
PAGE
SHEET
124578
10 13 14 15 17
12 23 26
TOTAL=1.600A MAX
26
C1241
15UF
20%
6.3V
X5R
0402-1
ROOM=PMU
7.0.0
12 OF 55
12 OF 54
H7 VDD1(BUCK3)=0.045A MAX
BUCK3_SW1=0.500A MAX
+
BUCK3_SW2=0.?A MAX
BUCK3_SW3=0.?A MAX
TOTAL=0.545A MAX
D
+
BUCK4_SW2=0.100A MAX
BUCK4_SW1=1.000A MAX
(BUCK4)=0.500A MAX
H7 VDDCA,VDD2
C
VDD_SRAM_SOC
H7 VDD_SRAM,
3.3A MAX
B
A
SIZE
D
876543
ADI PMU
(AMUX, GPIO, BUTTONS, ADC, THERMISTORS, SYSTEM I/F, GND)
12
D
C
FOREHEAD NTC
NO_XNET_CONNECTION=TRUE
ROOM=PMU_
C1359
NO_XNET_CONNECTION=TRUE
C1367
100PF IS NEEDED FOR SAMPLING CAP IN ADC IN PMU
B
NO_XNET_CONNECTION=TRUE
C1322
100PF IS NEEDED FOR SAMPLING CAP IN ADC IN PMU
NO_XNET_CONNECTION=TRUE
C1368
A
1
100PF
5%
6.3V
2
CERM
01005
100PF IS NEEDED FOR SAMPLING CAP IN ADC IN PMU
ROOM=PMU_
1
100PF
5%
6.3V
2
CERM
01005
ROOM=PMU_
1
100PF
5%
6.3V
2
CERM
01005
ROOM=PMU_
1
100PF
5%
6.3V
2
CERM
01005
100PF IS NEEDED FOR SAMPLING CAP IN ADC IN PMU
NO_XNET_CONNECTION=TRUE
1
ROOM=PMU_
R1308
10KOHM-1%
01005
2
CAMERA NTC
NO_XNET_CONNECTION=TRUE
1
ROOM=PMU_
R1310
10KOHM-1%
01005
2
RADIO PA NTC
NO_XNET_CONNECTION=TRUE
1
ROOM=PMU_
R1390
10KOHM-1%
01005
2
H7P NTC
NO_XNET_CONNECTION=TRUE
1
ROOM=PMU_
R1357
10KOHM-1%
01005
2
FOREHEAD_NTC_P
FOREHEAD_NTC_N
CAM_NTC_P
CAM_NTC_N
PA_NTC_P
PA_NTC_N
SOC_NTC_P
SOC_NTC_N
PCB: MAKE XW1328, XW1329 ACCESSIBLE!
ROOM=PMU
PP1300
ROOM=PMU
PP1301
2 3 5 6 7
10 11 12 15 20 23 24
25 26 27
NO_XNET_CONNECTION=TRUE
XW1304
NO_XNET_CONNECTION=TRUE
XW1309
NO_XNET_CONNECTION=TRUE
XW1306
NO_XNET_CONNECTION=TRUE
XW1311
NO_XNET_CONNECTION=TRUE
XW1308
NO_XNET_CONNECTION=TRUE
XW1333
NO_XNET_CONNECTION=TRUE
XW1314
NO_XNET_CONNECTION=TRUE
XW1315
PLACE THESE XWS AT PMU
ROOM=PMU
21
SHORT-10L-0.1MM-SM
ROOM=PMU
21
SHORT-10L-0.1MM-SM
ROOM=PMU
21
SHORT-10L-0.1MM-SM
ROOM=PMU
21
SHORT-10L-0.1MM-SM
ROOM=PMU
21
SHORT-10L-0.1MM-SM
ROOM=PMU
21
SHORT-10L-0.1MM-SM
ROOM=PMU
21
SHORT-10L-0.1MM-SM
ROOM=PMU
21
SHORT-10L-0.1MM-SM
AMUX VOLTAGE LIMIT IS APPROX. = VDD_REF = PP_VCC_MAIN
1.8V --->
1.8V --->
PP1V8
1.8V --->
1.8V --->
1.8V --->
3.33V --->
BASEBAND --->
1.8V --->
1.8V --->
BASEBAND --->
SM
P2MM-NSM
1
PP
P2MM-NSM
1
PP
SM
ROOM=PMU
R1301
100K
5%
1/32W
MF
01005
PMU_TO_PHOTON_ALIVE
20
1
2
C1365
ROOM=PMU
BUTTON_TO_AP_RINGER_A
3 8
13
BUTTON_TO_AP_VOL_UP_L
3 8
BUTTON_TO_AP_VOL_DOWN_L
3 8
LCM_TO_CHESTNUT_PWR_EN
15 20
TRISTAR_TO_PMU_USB_BRICKID_R
13
CHESTNUT_TO_PMU_ADCIN7
13 15
PMU_TO_TP_AMUX_AY
25
RADIO_TO_PMU_ADC_SMPS1
29
RADIO_TO_PMU_ADC_PP_LDO11_VDDIO
29
45_PMU_TO_WLAN_CLK32K
13 29
RADIO_TO_PMU_ADC_PP_LDO5_SIM
29
AP_TO_PMU_TEST_CLKOUT
2
RADIO_TO_PMU_ADC_SMPS4
29
PMU_TO_TP_AMUX_BY
25
AP_TO_I2C0_SCL
3
13 15 17
AP_BI_I2C0_SDA
3
15 17
3
15
45_AP_TO_PMU_AND_BL_DWI_CLK
3
15
45_AP_TO_PMU_AND_BL_DWI_DO
PMU_TO_AP_PRE_UVLO_L
3
AP_TO_PMU_RESET_IN
2
TRISTAR_TO_PMU_HOST_RESET
17
AP_TO_PMU_SOCHOT1_L
3
RESET_1V8_L
15 17 25
2 4
PMU_TO_AP_IRQ_L
3
FOREHEAD_TO_PMU_NTC
CAM_TO_PMU_NTC
PA_TO_PMU_NTC
SOC_TO_PMU_NTC
45_PMU_TCAL
1
100PF
5%
6.3V
2
CERM
01005
1
R1309
3.92K
0.1%
1/20W
MF
0201
2
ROOM=PMU
63
APN: 338S1251 (ADI AZ)
ROOM=PMU
U1202
D2186AZE0FJAVAC
A1
AMUX_A0
NC
B1
AMUX_A1
NC
D2
AMUX_A2
E2
AMUX_A3
E1
AMUX_A4
H6
AMUX_A5
H5
AMUX_A6
H4
AMUX_A7
G4
AMUX_AY
J5
AMUX_B0
J6
AMUX_B1
K5
AMUX_B2
NC
K8
AMUX_B3
NC
L8
AMUX_B4
K9
AMUX_B5
L9
AMUX_B6
L10
AMUX_B7
L4
AMUX_BY
J4
SCL
K4
SDA
K15
DWI_CK
J16
DWI_DI
K16
DWI_DO
NC
F8
PRE_UVLO
P3
RESET_IN1
R3
RESET_IN2
P4
RESET_IN3
R4
RESET*
P2
IRQ*
N1
SYS_ALIVE
L15
TDEV1
R17
TDEV2
P17
TDEV3
R19
TDEV4
P18
TCAL
P19
TBAT
NC
FCCSP-N56-N61
100-300K INT PD
100-300K INT PD
100-300K INT PD
100-300K INT PD
100-300K INT PU TO LDO12
NO INT PULL
NO INT PULL
SYM 2 OF 3
AP<->PMUAMUX
NTC
ADI OTP:
SEE RADAR 14032884
VDD_REF
VDD_RTC
FIXED 2.5V, +/-2%
BRICK_ID
ADC/REFS
ADC_IN7
ADC_REF
ACC_ID
TMPR_DET
ACC_DET
BUTTON1
100-300K INT PU
BUTTON2
100-300K INT PU
BUTTON3
100-300K INT PU
BUTTON4
100-300K INT PU
KEEPACT
NO INT PULL
BUTTONS/DETECT
OUT_32K
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
IREF
VREF
SHDN
F6
45_PMU_IREF
G5
26
PP_PMU_VREF
E5
26
PP_PMU_VDD_REF
F7
26
PP_PMU_VDD_RTC
N17
13
TRISTAR_TO_PMU_USB_BRICKID_R
N18
E6
NC
N19
NC
F5
NC
R18
D21
D20
B20
C20
L7
N10
E8
F17
F16
E15
F15
G17
E17
E16
E14
H16
G16
F14
F13
E13
E12
E11
F12
E10
E9
F11
F9
F10
BUTTON_TO_AP_MENU_KEY_L
BUTTON_TO_AP_HOLD_KEY_L
NC
NC
45_PMU_TO_WLAN_CLK32K
BB_TO_PMU_HOST_WAKE_L
STOCKHOLM_TO_PMU_HOST_WAKE
PMU_TO_OSCAR_RESET_CLK32K_L
WLAN_TO_PMU_HOST_WAKE
CODEC_TO_PMU_MIKEY_INT_L
BT_TO_PMU_HOST_WAKE
PMU_TO_WLAN_REG_ON
OSCAR_TO_PMU_HOST_WAKE
NC
NC
NC
NC
NC
WLAN_TO_PMU_PCIE_WAKE_L
ROOM=PMU
R1316
200K
12
1%
1/20W
ROOM=PMU
C1317
0.1UF
12
0201 6.3V
10%
CERM-X5R
ROOM=PMU
C1318
1.0UF
12
6.3V
ROOM=PMU
C1319
0.1UF
12
10%
6.3V
CERM-X5R
0201
AP_TO_PMU_KEEPACT
CHG_TO_PMU_INT_L
PMU_TO_BB_RST_R_L
TRISTAR_TO_AP_INT
PMU_TO_BT_REG_ON
AP_TO_I2C0_SCL
PMU_TO_BB_VBUS_DET
PMU_TO_ACC_SW_ON
X5R20%
0201-1
MF
201
3
21
3 8
13 29
14
29
3
17
29
22
29
10
29
29
29
3
13 15 17
7
22
29
29
17
ROOM=PMU
1
R1330
100K
5%
1/32W
MF
01005
2
1
C1326
0.01UF
10%
6.3V
2
X5R
01005
ROOM=PMU
1
C1323
1000PF
10%
6.3V
2
X5R-CERM
01005
ROOM=PMU
ROOM=PMU
R1312
1.00K
12
5%
1/32W
MF
01005
ROOM=PMU
R1331
6.34K
12
MF1%
PP1V8_SDRAM
PMU_TO_BB_RST_L
TRISTAR_TO_PMU_USB_BRICKID
1/32W01005
CHESTNUT_TO_PMU_ADCIN7
3 4
10 12 14 15 17 26 29
BUTTON_TO_AP_RINGER_A
ROOM=PMU
1
R1387
1.00M
5%
1/32W
MF
01005
29
2
D
17
ROOM=PMU
13 15
A15
B15
VSS_BUCK0_5
C15
A2
B2
VSS_BUCK1
C2
A6
B6
VSS_BUCK01
C6
G20
VSS_BUCK4
G21
A19
B19
VSS_BUCK5
3 8
13
3
SYNC_MASTER=N56_MLB
PAGE TITLE
C19
A10
A11
B10
B11
C10
C11
H15
G15
K20
K21
A20
A21
B21
G10
G11
G12
P9
H1
H2
G8
G6
H7
J7
P8
G7
VSS_BUCK6
VSS_BUCK012
VSS_BUCK23
VSSA_BUCK0
VSSA_BUCK1
VSSA_BUCK2
VSSA_BUCK3
VSSA_BUCK4
VSSA_BUCK5
VSSA_BUCK6
VSS_SW_CHG
VSS
POWER:ADI(2/2)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
U1202
D2186AZE0FJAVAC
FCCSP-N56-N61
SYM 3 OF 3
G13
G14
H8
H9
H10
H11
H12
H13
H14
J8
J9
J10
J11
J12
J13
J14
J15
K11
K12
K13
K14
K17
VSS
L12
L13
L14
M1
N14
P1
P11
P13
P15
P16
R1
R2
R16
R20
R21
SYNC_DATE=08/29/2013
DRAWING NUMBER
051-9903
REVISION
7.0.0
BRANCH
PAGE
13 OF 55
SHEET
13 OF 54
SIZE
C
B
A
D
124578
876543
TIGRIS CHARGER & VIBE DRIVER
12
D
C
PP1V8_ALWAYS
3 5
12 26
ROOM=CHARGER
R1403
CHG_TO_PMU_INT_L
13
100K
1/32W
01005
D
PP_VCC_MAIN
CHARGER CAPS
1
C1417
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=CHARGER
ROOM=CHARGER
1
C1416
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=CHARGER
1
C1410
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=CHARGER
C1402
0.033UF
12 25
3
25
26
12
16V
402
ROOM=CHARGER
1
C1412
2.2UF
20%
6.3V
2
X5R
0201-1
ROOM=CHARGER
1
C1415
2.2UF
20%
6.3V
2
X5R
0201-1
1
C1450
220PF
10%
10V
2
X7R-CERM
01005
ROOM=CHARGER
CHARGER DESENSE CAPS
PLACE BY L1401
10%
X5R
1.0UH-20%-3.2A-0.065OHM
C1451
1
100PF
5%
16V
NP0-C0G
2
01005
ROOM=CHARGER
L1401
12
PIFE25201T-SM
ROOM=CHARGER
1
C1411
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=CHARGER
CHARGER_LDO
ROOM=CHARGER
C1403
1
100PF
5%
16V
NP0-C0G
2
26
26
CHARGER_VBATT_SNS
CHG_ACT_DIO
AP_TO_TIGRIS_SWI
01005
CHG_BOOT
CHG_LX
BATTERY_SWI
A2B2D2
C2
PMID_CAP
26
1
1
C1407
4.2UF
10%
16V
2
X5R-CERM
0402-1
PP5V0_USB
12 17 18 25 26
1
C1408
4.2UF
10%
16V
2
1
1
C1440
220PF
5%
10%
10V
MF
2
X7R-CERM
01005
2
ROOM=CHARGER
X5R-CERM
0402-1
ROOM=CHARGER
USB_VBUS_DETECT
2
ROOM=CHARGER
C1470
100PF
5%
25V
NP0-C0G
01005
ROOM=CHARGER
10 12 13 15 17 26 29
1
C1409
4.2UF
10%
16V
2
X5R-CERM
0402-1
ROOM=CHARGER
NOSTUFF
C1471
100PF
5%
25V
NP0-C0G
01005
ROOM=CHARGER
PP1V8_SDRAM
3 4
R1454
68.1K
12
1/32W
01005
1%
MF
C1453
100PF
5%
25V
2
NP0-C0G
01005
ROOM=CHARGER
SM
XW1401
12
ROOM=CHARGER
TRISTAR_TO_PMU_OVP_SW_EN_L
17
PP_TIGRIS_VBUS_DET
26
1
2
AP_BI_I2C1_SDA
3
14 16 21
AP_TO_I2C1_SCL
3
14 16 21
SYS_ALIVE_TIGRIS
NOSTUFF
C1452
100PF
5%
25V
NP0-C0G
01005
ROOM=CHARGER
F5
PMID
A5
VBUS
B5
VBUS
D5
VBUS
C5
VBUS
E5
VBUS
G3
SDA
E4
SCL
E3
SYS_ALIVE
F4
VBUS_OVP_OFF
G2
INT
F1
VBUS_DET
F3
TEST
VDD_MAIN
VDD_MAIN
VDD_MAIN
U1401
SN2400B0YFF
WCSP
PGND
PGND
PGND
A3
VDD_MAIN
ACT_DIODE
HDQ_GAUGE
PGND
C3B3D3
BOOT
BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW
BAT_SNS
HDQ_HOST
LDO
BAT
BAT
BAT
BAT
G4
G5
A4
B4
D4
C4
A1
B1
D1
C1
E1
E2
G1
F2
ROOM=CHARGER
1
C1418
2.2UF
20%
6.3V
2
X5R
0201-1
NOSTUFF
ROOM=CHARGER
1
R1401
100K
5%
1/32W
MF
01005
2
C1480
1
100PF
16V
NP0-C0G
2
01005
ROOM=CHARGER
DESENSE CAP
PCB: PLACE CLOSE BY TIGRIS
B3B2B1A3A2
S
Q1403
A1
G
C1C2C3
5%
CSD68815W15
BGA
D
ROOM=CHARGER
PP_BATT_VCC
10 12 15 16 17 23 26 31 39 48
51 52
14 16 25 26 40 45 46
C
PP_BATT_VCC
1
A3
C3
A2
VIBE_C_VREG
C1433
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=VIBE_DRIVER
B
AP_BI_I2C1_SDA
14 16 21
3
AP_TO_I2C1_SCL
3
14 16 21
AP_TO_VIBE_EN
3
AP_TO_VIBE_TRIG
3
NOSTUFF
1
R1411
100K
5%
1/32W
MF
01005
2
ROOM=VIBE_DRIVER
ROOM=VIBE_DRIVER
B2
C1
A1
B1
1
R1412
100K
5%
1/32W
MF
01005
2
ROOM=VIBE_DRIVER
U1400
DRV2604YZF
SDA
SCL
EN
IN/TRIG
BGA
C2
VDD
OUT+
OUT-
VREG
GND
B3
A
63
ROOM=VIBE_DRIVER
1
C1401
2.2UF
20%
6.3V
2
X5R
0201-1
14 16 25 26 40 45 46
C1405
1
100PF
NP0-C0G
2
ROOM=VIBE_DRIVER
01005
B
VIBE_DRIVE_P
VIBE_DRIVE_N
C1406
1
2
ROOM=VIBE_DRIVER
100PF
NP0-C0G
01005
5%
16V
18 26
18 26
5%
16V
SIZE
A
D
PAGE TITLE
POWER:TIGRISR,VIBE DRIVER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-9903
REVISION
7.0.0
BRANCH
PAGE
14 OF 55
SHEET
14 OF 54
124578
876543
CHESTNUT, BACKLIGHT DRIVER, MESA BOOST
12
D500 DISPLAY PMU (TI CHESTNUT, 338S1149)
D
PP_VCC_MAIN
10 12 14 15 16 17 23 26 31 39
48 51 52
1.5UH-20%-1.8A-0.118OHM
L1519
LQE2MRT1R5MG0-SM
ROOM=CHESTNUT
C
1
2
C1547
ROOM=CHESTNUT
PP_CHESTNUT_LXP
AP_TO_I2C0_SCL
3
13 15 17
AP_BI_I2C0_SDA
3
13 15 17
LCM_TO_CHESTNUT_PWR_EN
13 20
RESET_1V8_L
2 4
13 17 25
CHESTNUT_TO_PMU_ADCIN7
13
10UF
CERM-X5R
0402-9
6.3V
1
20%
2
D1
B2
A2
D3
D2
C3
C2
E1
U1501
TPS65730A0PYFF
BGA
ROOM=CHESTNUT
VIN
SW
SYNC
NO INT PULL
SCL
SDA
LCM_EN
200K INT PD
RESET*
NO INT PULL
ADCMUX
AGND
B1D4C1
LCMBST
VNEG(SUB)
HVLDO1
HVLDO2
HVLDO3
PGND1
PGND2
CPUMP
VNEG
CF1
CF2
C4
E4
26 26
B3
B4
E3
E2
A4
A3
A1
26
PP_CHESTNUT_CP
PP_CHESTNUT_CN
1
C1541
1UF
20%
6.3V
2
X5R
0201
ROOM=CHESTNUT
1
C1554
10UF
20%
10V
2
X5R-CERM
0402-8
ROOM=CHESTNUT
1
C1569
10UF
20%
10V
2
X5R-CERM
0402-8
ROOM=CHESTNUT
26
PP6V0_LCM_BOOST
1
C1577
10UF
20%
10V
2
X5R-CERM
0402-8
ROOM=CHESTNUT
PN5V7_SAGE_AVDDN
PP5V7_SAGE_AVDDH
PP5V7_LCM_AVDDH
PP5V1_GRAPE_VDDH
24 26
20 26
24 26
1
C1504
10UF
20%
10V
2
X5R-CERM
0402-8
ROOM=CHESTNUT
20 24 26
1
C1502
10UF
20%
10V
2
X5R-CERM
0402-8
ROOM=CHESTNUT
1
C1529
10UF
20%
10V
2
X5R-CERM
0402-8
ROOM=CHESTNUT
D
C
D500 BACKLIGHT DRIVER
15UH-20%-0.72A-0.9OHM
B
PP_VCC_MAIN
10 12 14 15 16 17 23 26 31 39
48 51 52
ROOM=BACKLIGHT
10UF
6.3V
CERM-X5R
0402-9
1
20%
2
L1503
12
PITA32251T-SM
ROOM=BACKLIGHT
1
C1597C1552
10UF
20%
6.3V
2
CERM-X5R
0402-9
ROOM=BACKLIGHT
13 15 17
13 15 17
10 11 12 13 20 23 24
10 12 13 14 17 26 29
AP_BI_I2C0_SDA
3
AP_TO_I2C0_SCL
3
PP1V8
2 3 5 6 7
25 26 27
PP1V8_SDRAM
3 4
NOTE: D1501 IS 30V DIODE FOR N61 AND 20V FOR N56.
26
PP_WLED_LX
A3
C3
A1
A2
C1
B1
NSR0530P2T5G
U1502
LM3534TMX-A1
BGA
SW
IN
SDA
SCL
VIO_SPI
HWEN
ROOM=BACKLIGHT
D1501
SOD-923-1
ROOM=BACKLIGHT
ILED1
ILED2
GND
B3
D1
OVP
PP_LCM_BL_CAT1
D3
D2
PP_LCM_BL_CAT2
B2
45_AP_TO_PMU_AND_BL_DWI_CLK
SCK
C2
45_AP_TO_PMU_AND_BL_DWI_DO
SDI
1
C1505
2.2UF
20%
25V25V
2
X5R-CERM
0402-1
ROOM=BACKLIGHT
20 26
20 26
1
C1530
2.2UF
20%
2
X5R-CERM
0402-1
ROOM=BACKLIGHT
ROOM=BACKLIGHT
1
C1513
100PF
5%
25V
2
NP0-C0G
01005
3
13
3
13
1AK
C1531
2.2UF
20%
25V
2
X5R-CERM
0402-1
ROOM=BACKLIGHT
PP_LCM_BL_ANODE
20 26
52
PP_VCC_MAIN
10 12 14 15 16 17
23 26 31 39 48 51
C1508
10UF
6.3V
CERM-X5R
0402-9
ROOM=MESA
ROOM=MESA
1.0UH-20%-0.4A-0.53OHM
1
20%
2
L1500
0403
PP3V0_TRISTAR
12 17 26 29
MESA_TO_BOOST_EN
21 25
21
PP18V0_MESA_SW
26
A
63
MESA BOOST A0
APN: 353S3978
ROOM=MESA
U1503
LM3638
SW
VIN
EN_M
EN_S
LDOIN
A1
BGA
PGND
B3
AGND
VOUT
PMID
C3
VOLTAGE=17.0V
C1
B1
A2
B2
A3
C2
26
P17V0_MOJAVE_LDOIN
SYNC_MASTER=N61_MLB
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
PP16V5_MESA
1
C1500
2.2UF
20%
25V
2
X5R
0402-3
ROOM=MESA
1
C1501
2.2UF
20%
25V
2
X5R
0402-3
ROOM=MESA
ROOM=MESA
1
C1503
100PF
5%
25V
2
NP0-C0G
01005
SYNC_DATE=08/26/2013
DISPLAY:CHESTNUT,BACKLIGHT DRIVER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING NUMBER
051-9903
REVISION
BRANCH
PAGE
15 OF 55
SHEET
15 OF 54
124578
21 25 26
7.0.0
SIZE
B
A
D
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