Apple iPad Mini Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

65

43

21

CK

REV ECN

0001520462

13

DESCRIPTION OF REVISION

ENGINEERING RELEASED

APPD

DATE

2012-07-02

MAIN LOGIC BOARD

DVT

X123

LAST_MODIFIED=Wed Jun 27 16:39:53 2012

D

SCH AND BOARD PART NUMBERS

QTY

PART#

CSAPDF

TABLE_TABLEOFCONTENTS_HEAD

1

TABLE_TABLEOFCONTENTS_ITEM

2

TABLE_TABLEOFCONTENTS_ITEM

3

TABLE_TABLEOFCONTENTS_ITEM

C

B

4

TABLE_TABLEOFCONTENTS_ITEM

5

TABLE_TABLEOFCONTENTS_ITEM

6

TABLE_TABLEOFCONTENTS_ITEM

7

TABLE_TABLEOFCONTENTS_ITEM

8

TABLE_TABLEOFCONTENTS_ITEM

9

TABLE_TABLEOFCONTENTS_ITEM

10

TABLE_TABLEOFCONTENTS_ITEM

11

TABLE_TABLEOFCONTENTS_ITEM

12

TABLE_TABLEOFCONTENTS_ITEM

13

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

15

TABLE_TABLEOFCONTENTS_ITEM

16

TABLE_TABLEOFCONTENTS_ITEM

17

TABLE_TABLEOFCONTENTS_ITEM

18

TABLE_TABLEOFCONTENTS_ITEM

19

TABLE_TABLEOFCONTENTS_ITEM

20

TABLE_TABLEOFCONTENTS_ITEM

CONTENTS

TABLE OF CONTENTS

1

BLOCK DIAGRAM: SYSTEM

2

6

AP: MAIN

7

AP: I/Os

8

AP: FLASH MEMORY INTERFACE

AP: TV/DP/MIPI/CAMERA

9

10

AP: PWR

11

AP: PWR

12

AP: MISC & ALIASES

13

E75 SUPPORT

NAND STORAGE

14

17

TOUCH: FLEX CONNECTOR

18

AUDIO JACK FLEX CONN

19

AUDIO: L81 CODEC

AUDIO: CS35L19A AMPS

20

22

VIDEO: MIPI CONNECTOR

FF CAM & MIC CONNECTORS

26

27

INERTIAL SENSORS

PROX SENSOR

28

29

BUTTON & REAR CAMERA CONN

SYNC MASTER

DESCRIPTION

1

SCH,MLB,X123

1

PCB,MLB,X123

DATE

N/A

N/A

N/A

N/A

N/A

MLB

N/A

N/A

N/A

N/A

MLB

N/A

N/A

KAVITHA1401/18/2012

KAVITHA

N/A

N/A

N/A

N/A

N/A

N/A

N/A

04/18/2011

05/05/2011

04/18/2011

05/04/2012

04/18/2011

04/18/2011

04/11/2011

N/A

05/04/2012

06/21/2010

03/31/2011

01/18/2012

N/A

N/A

N/A

N/A

N/A

REFERENCE DESIGNATOR(S)

SCH1051-9374

PCB1820-3243

BOM OPTION

CSAPDF

TABLE_TABLEOFCONTENTS_HEAD

21

TABLE_TABLEOFCONTENTS_ITEM

22

TABLE_TABLEOFCONTENTS_ITEM

23

TABLE_TABLEOFCONTENTS_ITEM

24

TABLE_TABLEOFCONTENTS_ITEM

25

TABLE_TABLEOFCONTENTS_ITEM

26

TABLE_TABLEOFCONTENTS_ITEM

27

TABLE_TABLEOFCONTENTS_ITEM

28

TABLE_TABLEOFCONTENTS_ITEM

29

TABLE_TABLEOFCONTENTS_ITEM

30

TABLE_TABLEOFCONTENTS_ITEM

31

TABLE_TABLEOFCONTENTS_ITEM

32

TABLE_TABLEOFCONTENTS_ITEM

33

TABLE_TABLEOFCONTENTS_ITEM

34

TABLE_TABLEOFCONTENTS_ITEM

35

TABLE_TABLEOFCONTENTS_ITEM

36 GPS

TABLE_TABLEOFCONTENTS_ITEM

37

TABLE_TABLEOFCONTENTS_ITEM

38

TABLE_TABLEOFCONTENTS_ITEM

39

TABLE_TABLEOFCONTENTS_ITEM

40

TABLE_TABLEOFCONTENTS_ITEM

41

TABLE_TABLEOFCONTENTS_ITEM

42

TABLE_TABLEOFCONTENTS_ITEM

43

TABLE_TABLEOFCONTENTS_ITEM

44

TABLE_TABLEOFCONTENTS_ITEM

45

TABLE_TABLEOFCONTENTS_ITEM

46

TABLE_TABLEOFCONTENTS_ITEM

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

57

73

75

81

82

93

100

101

102

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

CONTENTS
SYSTEM & DEBUG CONNECTORS
BASEBAND PMU (1 0F 2)
BASEBAND PMU (2 OF 2)
BASEBAND (1 OF 2)
MOBILE DATA MODEM (2 OF 2)
RF TRANSCEIVER (1 0F 3)
RF TRANSCEIVER (2 OF 3)
RF TRANSCEIVER (3 OF 3)
BAND 5/8 PAD
BAND 13 PA
2G PA, DCDC CONVERTER
DCS RX, ASM
BAND 1/4 PAD
BAND2 PAD
RX DIVERSITY

WIFI/BT
IO FLEX: DOCK COMPONENTS
Power: Aliases
POWER: BATTERY CONNECTOR
Power: PMU
POWER: PMU
MECHANCIAL PARTS
CONSTRAINTS: ASSIGNMENTS
CONSTRAINTS: ASSIGNMENTS
CONSTRAINTS: MLB RULES

SYNC MASTER

N/A

N/A

DATE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

06/27/2012JORGE

04/18/2011

N/AN/A

N/AN/A

N/AN/A

05/09/2011

N/AN/A

N/AN/A

N/AN/A

N/AN/A

D

C

B

A

DRAWING

3

DRAWING TITLE

SCH,MLB,X123

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

1 OF 102

SHEET

1 OF 46

1245678

SIZE

A

D

87

6 5

4 3

12

ISP_I2C1

CUMULUS

MASTER

CABERNET BRD

SPI1

H4A

MIPI1C

ISP_I2C0

MIPI0C

D

CUMULUS

SLAVE

CABERNET BRD

DUAL-CORE ARM

CORTEX-A9 W/ SMP

1GHZ

LPDDR2

HSIC1

UART4

FF CAMERA

CANADA FLEX

REAR CAMERA

SENSOR PANEL

RF/GPS

D

RF ANT

2X32-BIT

400MHZ/800MB/S

DISPLAY/

TOUCH PANEL

C

LVDS

MLC

(POR)

CSA 21

MIPI0D

DUAL-CORE IMG

GPU

SGX543-MP

AUDIO

AE2

ARM A5 CPU

HSIC2

UART3

UART1

I2S3

BT_I2S

CSA 32-46

WIFI/BT

CSA 47

WIFI/BT ANT

C

BACKLIGHT

UART5_RTXD

NAND FLASH

PMU

BATTERY

FMI0

ALISON

FMI1

CSA 75

DWI
I2C0

CSA 81-82

B

AUDIO CODEC

SPI

ASP

XSP

E75

IO FLEX

TRISTAR

CSA 13

MIKEY

BB USB

UART4

JTAG

USB2.0
UART0

UART2

I2C2

I2C1

SPI2

I2S0

I2S2

I2S1

CSA 14

B

L81

HS JACK

AUDIO JACK FLEX

CSA 19

A

GYRO

AP3GDL20 (NEW) (SAME AS K93A)

CSA 27

ACCELEROMETER

AP3DSH (NEW)

CSA 27

ALS

(SAME AS K93A)

VGA FLEX

PROX

(SAME AS J2)

CSA 28

COMPASS

CSA 27

AMP

CSA 20

AMP

CSA 20

SPEAKER

CSA 20

SYNC_MASTER=N/A

PAGE TITLE

BLOCK DIAGRAM: SYSTEM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

2 OF 102

SHEET

2 OF 46

124578

SIZE

A

D

87

R0620

0.00

=PP1V0_PLL_H4

39

D

12

0%

1/32W

MF

01005

R0621

0.00

12

0%

1/32W

MF

01005

R0622

0.00

12

0%

1/32W

MF

01005

R0624

0.00

12

0%

1/32W

MF

01005

1

C0651

0.01UF

10%

6.3V

2

X5R
01005

1

C0648

0.01UF

10%

6.3V

2

X5R
01005

1

C0646

0.01UF

10%

6.3V

2

X5R
01005

1

C0608

0.01UF

10%

6.3V

2

X5R
01005

1

2

1

2

1

2

1

2

6 5

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V0_PLL4_F

C0680

27PF

5%
16V
NP0-C0G
01005

PP1V0_PLL3_F

C0681

27PF

5%
16V
NP0-C0G
01005

PP1V0_PLL2_F

C0682

27PF

5%
16V
NP0-C0G
01005

PP1V0_PLL01_F

C0683

27PF

5%
16V
NP0-C0G
01005

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

39

=PP1V0_USB_H4

3

1

C0643

0.22UF

20%

6.3V

2

X5R
0201

4 3

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V0_PLL_USB_F

1

2

C0684

27PF

5%
16V
NP0-C0G
01005

1

C0652

0.01UF

10%

6.3V

2

X5R
01005

1

C0627

0.01UF

10%

6.3V

2

X5R
01005

1

2

C0640

1UF

20%

6.3V
X5R
0201

R0625

0.00

12

0%

1/32W

MF

01005

1

C0630

0.01UF

10%

6.3V

2

X5R
01005

=PP1V0_USB_H4

=PP3V3_USB_H4

12

D

3

39

8

39

=PP1V2_HSIC_H4

C

HSIC1_BB_DATA

21 44

BI

HSIC1_BB_STB

21 44

BI

HSIC2_WLAN_DATA

21 44

BI

HSIC2_WLAN_STB

21 44

=PP1V8_H4

3 4 6 9

39

1

R0647

100K

1%
1/32W
MF
01005

NOSTUFF

C0618

1000PF

10%

6.3V
X5R
01005

2

COMMON339S0179

JTAG_SOC_TDI

44

1%
1/32W
MF
01005

IN

JTAG_SOC_TMS

10 44

OUT

JTAG_SOC_TCK

10 44

OUT

CRITICAL BOM OPTION

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

1

2

ELPIDA

HYNIX

=PP1V8_H4

3 4 6 9

39

1

R0617

B

RST_SYSTEM_L

10 21 42

IN

A

PART#

PART NUMBER

339S0187

339S0188 339S0179

DESCRIPTION

QTY

1

H4A B0,35NM,1.15MM HEIGHT

ALTERNATE FOR
PART NUMBER

339S0179

BOM OPTION

REF DES

U0652

U0652

10K

2

REFERENCE DESIGNATOR(S)

U0652

COMMENTS:

1

R0646

100K

1%
1/32W
MF
01005

2

R0688

100K

1/32W

01005

R0689

221K

1/32W

01005

TABLE_5_HEAD

TABLE_5_ITEM

1%

MF

1%

MF

1

2

1

2

SAMSUNG

1

R0645

100K

1%
1/32W
MF
01005

2

BI

9

IN

9

44

OUT

9

44

OUT

SOC_DDR_CKEIN

SOC_TST_STPCLK

9

SOC_TESTMODE

9

SOC_FAST_SCAN_CLK

9

SOC_HOLD_RESET

9

39

JTAG_SOC_SEL

JTAG_SOC_TRST_L
JTAG_SOC_TDO

1

2

NC_JTAG_SOC_TRTCK

TP_SOC_TST_CLKOUT

C0642

0.22UF

20%

6.3V
X5R
0201

W30

HSIC1_DATA

W31

HSIC1_STB

R31

HSIC2_DATA

U31

HSIC2_STB

A25

JTAG_SEL

E26

JTAG_TRTCK

E25

JTAG_TRST*

D26

JTAG_TDO

D25

JTAG_TDI

B25

JTAG_TMS

C26

JTAG_TCK

G23

RESET*

J23

CFSB

K12

DDR0_CKEIN

T9

DDR1_CKEIN

A29

TST_CLKOUT

A26

TST_STPCLK

G20

TESTMODE

H26

FUSE1_FSRC

F22

FAST_SCAN_CLK

H23

HOLD_RESET

W26

HSIC_VDD121

25MA

HSIC_VSS121

W28

V24

V27

V25

HSIC_VDD122

25MA

HSIC1_DVDD101

10MA

10MA

HSIC1_DVSS

HSIC_VSS122

W25

W29

V26

E21

E20

E18

E17

E16

4MA

4MA

4MA

HSIC2_DVDD102

4MA

4MA

4MA

OMIT

U0652

H4A

BGA

(1 OF 12)

POP-512MB-DDR

CRITICAL

USB_BRICKID_DM_MON

PLL4_AVSS11 PLL4_AVDD11

PLL3_AVSS11 PLL3_AVDD11

PLL2_AVSS11 PLL2_AVDD11

PLL1_AVSS11 PLL1_AVDD11

PLL0_AVSS11 PLL0_AVDD11

HSIC2_DVSS

D21

D20

D18

D17

D16

T27

R25

E19

USB_DVDD

10MA

35MA

USB11_DP

USB11_DM

USB_ANALOGTEST

USB_VBUS

USB_BRICKID

USB_REXT

2MA

PVDDP_CFSB

17MA

PVDDP_FMI0

6MA

PVDDP_TESTS

4MA

PVDDP_UART4

VSEL30_FMI

VSEL30_TST

VSEL30_UART4

USB_VSSA0

PLL_USB_AVSS11 PLL_USB_AVDD11

R27

R26

D19

P27

USB_VDD330

USB_ASW_VDD18

1MA

WDOG

XI0

XO0

USB_DP
USB_DM

USB_ID

USB_ASW_VSS18

P28

C27

A15

A16

T29
U29

M31

N31

U26

N28

M28

U27

T26

T25

J18
AC27

F27

AH25

G21

J21

H21

45

XTAL_SOC_24M_I

XTAL_SOC_24M_O

45

NC_USB_FS_D_P

NC_USB_FS_D_N

NC_USB_ANALOGTEST

USB_SOC_VBUS

NC_USB_ID

NC_USB_BRICKID_DP_MON

NC_USB_BRICKID_DM_MON

USB_REXT

SOC_WDOG

1.00M

1%

01005

12

9

9

SOC_USB_D_P
SOC_USB_D_N

1

C0610

0.01UF

10%

6.3V

2

X5R
01005

R0655

MF

1/32W

1

2

R0642

43.2

1%
1/20W
MF
201

1

C0611

0.01UF

10%

6.3V

2

X5R
01005

BI

BI

10

OUT

10 44

10 44

GDZT2R5.1B

=PP1V8_PVDDP_H4

1

2

R0640

1.00K

12

1%

1/32W

MF

01005

NOSTUFF

DZ0600

GDZ-0201

NOTE FOR VSEL...
0 - 1.8V IO

1.8V - 3V IO

=PP1V8_USB_H4

C0641

0.01UF

10%

6.3V
X5R
01005

XTAL_SOC_24M_O_R

1

2

R0651

68.1K

12

K

A

39

24.000MHZ-16PF-60PPM

C0613

15PF

5%
16V
NP0-C0G-CERM
01005

1%

1/32W

MF

01005

6 3

39

CRITICAL

Y0602

SM-2

31

24

PPVBUS_USB

SYNC_MASTER=N/A

PAGE TITLE

1

C0607

15PF

5%
16V

2

NP0-C0G-CERM
01005

41

AP: MAIN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

6 OF 102

SHEET

3 OF 46

124578

SIZE

C

B

A

D

87

6 5

4 3

12

H4A I/OS

R0720

33.2

1%

1/32W

MF

01005

I2S0_CODEC_ASP_MCK

14 44

OUT

D

I2S1_SPKAMP_MCK

15 44

OUT

C

12

R0721

33.2

1%

1/32W

MF

01005

12

44

44

I2S0_CODEC_ASP_MCK_R

44

I2S0_CODEC_ASP_BCLK

14 44

OUT

I2S0_CODEC_ASP_LRCK

14 44

OUT

I2S0_CODEC_ASP_DIN

14 44

IN

I2S0_CODEC_ASP_DOUT

14 44

OUT

I2S1_SPKAMP_MCK_R

44

I2S1_SPKAMP_BCLK

15 44

OUT

I2S1_SPKAMP_LRCK

15 44

OUT

I2S1_SPKAMP_DIN

15

IN

I2S1_SPKAMP_DOUT

15 44

OUT

PMU_GPIO_TRISTAR_IRQ

10 42

IN

I2S2_CODEC_XSP_BCLK

14 44

OUT

I2S2_CODEC_XSP_LRCK

14 44

OUT

I2S2_CODEC_XSP_DIN

14 44

IN

I2S2_CODEC_XSP_DOUT

14 44

OUT

GPIO_ACC_SW_POK_L

10

IN

I2S3_BT_BCLK

21 44

OUT

I2S3_BT_LRCK

21 44

OUT

I2S3_BT_DIN

21 44

IN

I2S3_BT_DOUT

21 44

OUT

GPIO_BOARD_ID2

9

IN

GPIO_BOARD_ID1

9

IN

GPIO_BOARD_ID0

9

IN

SPI1_GRAPE_MISO

12 44

IN

SPI1_GRAPE_MOSI

12 44

OUT

SPI1_GRAPE_SCLK

12

OUT

SPI1_GRAPE_CS_L

12 44

OUT

SPI2_CODEC_MISO

14 44

IN

SPI2_CODEC_MOSI

14 44

OUT

SPI2_CODEC_SCLK

14 44

OUT

SPI2_CODEC_CS_L

14 44

OUT

NC_SPI0_SSIN

AM18

AM19
AP14

AP17

AM22

AM13

AK3

AP8

AL14
AM20

AM9

AM16

AK2

AN17

AM2

AM1
AL16

AN20

AH1

AK5

AP21

AB1
AM15

AM4

AP23

AM3
AP13

AH4

AN13
AM12

AN22

AM21

I2S0_MCK
I2S0_BCLK

I2S0_LRCK

I2S0_DIN
I2S0_DOUT

I2S1_MCK

I2S1_BCLK

I2S1_LRCK
I2S1_DIN

I2S1_DOUT

I2S2_MCK
I2S2_BCLK

I2S2_LRCK

I2S2_DIN
I2S2_DOUT

I2S3_MCK

I2S3_BCLK

I2S3_LRCK
I2S3_DIN

I2S3_DOUT

SPI0_MISO
SPI0_MOSI

SPI0_SCLK

SPI0_SSIN

SPI1_MISO
SPI1_MOSI

SPI1_SCLK
SPI1_SSIN

SPI2_MISO

SPI2_MOSI

SPI2_SCLK
SPI2_SSIN

OMIT

U0652

H4A

BGA

POP-512MB-DDR

(3 OF 12)

I2C0_SCL
I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL
I2C2_SDA

SWI_DATA

DWI_DI

DWI_DO

DWI_CLK

SDIO0_CLK
SDIO0_CMD

SDIO0_DATA0

SDIO0_DATA1
SDIO0_DATA2

SDIO0_DATA3

AL4
AM6

AM7

AG3

D29
E29

AN6

U1

AN18
AM11

AH28
AJ24

AK25
AH24

AJ27

AK24

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

I2C2_SCL
I2C2_SDA

NC_SWI_AP

DWI_DI
DWI_DO
DWI_CLK

BB_JTAG_TCK

BB_JTAG_TMS

BB_JTAG_TDI

BB_JTAG_TDO

BB_JTAG_TRST_L

GPIO_ACC_SW_EN

AB5

AB4

AD5

AC4

AA3

AE5
AD3

AF5

AF4

AB3

AE4

AH3

K4

GPIO0

H1

GPIO1

F2

GPIO2

G4

GPIO3

G3

GPIO4

G2

GPIO5

K3

GPIO6

L4

GPIO7

G1

GPIO8

H2

GPIO9

N3

GPIO10

J2

GPIO11

J3

GPIO12

J1

GPIO13

W3

GPIO14

W4

GPIO15

M3

GPIO16

GPIO17

N2

GPIO18
GPIO19

Y4

GPIO20
GPIO21

H4

GPIO22

L2

GPIO23
GPIO24

V3

GPIO25

GPIO26
GPIO27

GPIO28

GPIO29

T2

GPIO30

GPIO31
GPIO32

GPIO33

P2

GPIO34

R3

GPIO35

GPIO36

GPIO_BTN_HOME_L

4

12 42

IN

GPIO_BTN_POWER_L

4

20 42

IN

GPIO_BTN_VOL_UP_L

20

IN

GPIO_BTN_VOL_DOWN_L

20

IN

4

10 15 42

4

10 15 42 44

4

4

18 19 44

4

4

17 18 44

42 44

42 44

42 44

21 24 44

21 24 44

21 24 44

21 24 44

21 24

10

44

18 19 44

17 18 44

44

BI

OUT

BI

OUT

BI

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

GPIO_BTN_SRL_L

4

20 42

IN

GPIO_SPKAMP_RST_L

4

15

OUT

GPIO_SPKAMP_KEEPALIVE

15

OUT

GPIO_SPKAMP_RIGHT_IRQ_L

15

IN

GPIO_CODEC_IRQ_L

14

IN

GPIO_BT_WAKE

21

OUT

GPIO_BB_RST_L

21

OUT

GPIO_BB_GSM_TXBURST

21

IN

GPIO_BB_IPC_GPIO

21

IN

GPIO_BB_DIAGS_RDY

21

IN

GPIO_BB_GPS_SYNC

21

IN

GPIO_BB_RST_DET_L

21

IN

GPIO_BOARD_ID3

9

IN

GPIO_BB_HSIC_HOST_RDY

21

OUT

GPIO_BOOT_CONFIG0

9

IN

GPIO_PMU_IRQ_L

42

IN

GPIO_PMU_KEEPACT

4

42

OUT

GPIO_GRAPE_RST_L

12

OUT

GPIO_GRAPE_IRQ_L

12

IN

GPIO_BB_RADIO_ON_L

21

IN

GPIO_BB_HSIC_DEV_RDY

21

OUT

GPIO_BOOT_CONFIG1

9

IN

GPIO_FORCE_DFU

4 9

IN

GPIO_DFU_STATUS

4

IN

GPIO_BOOT_CONFIG2

9

IN

GPIO_BOOT_CONFIG3

9

IN

GPIO_PROX_IRQ_L

19

IN

NC_GPIO31

GPIO_ACCEL_IRQ2_L

18

IN

GPIO_GYRO_IRQ1

18

IN

GPIO_WLAN_HSIC_RESUME

21

IN

GPIO_MLC_PWR_EN

16

OUT

GPIO_MLC_RST_1V8_L

4

OUT

VSS

B1

A31

A30

A27

A14

A13

A12

A11

A17

A24

OMIT

U0652

H4A

BGA

POP-512MB-DDR

(2 OF 12)

VSS

EHCI_PORT_PWR0

EHCI_PORT_PWR1
EHCI_PORT_PWR2

TMR32_PWM0

TMR32_PWM1
TMR32_PWM2

UART0_RXD
UART0_TXD

UART1_CTSN

UART1_RTSN

UART1_RXD
UART1_TXD

UART2_CTSN

UART2_RTSN

UART2_RXD

UART2_TXD

UART3_CTSN

UART3_RTSN

UART3_RXD

UART3_TXD

UART4_CTSN
UART4_RTSN

UART4_RXD

UART4_TXD

UART5_RTXD

T3
V2

U2

AP5

AP4
AN5

B29
C29

AG5

AH5
AL1

AK1

N1

T1
M1

R1

AF2
AG2

AE1

AF1

AJ26
AJ25

AK26

AK27

D28

GPIO_BOARD_REV0
GPIO_BOARD_REV1
GPIO_BOARD_REV2

GPIO_GYRO_IRQ2
GPIO_ACCEL_IRQ1_L

AP_CLK_32K_CUMULUS

UART0_DEBUG_RXD
UART0_DEBUG_TXD

UART1_BT_CTS_L
UART1_BT_RTS_L
UART1_BT_RXD
UART1_BT_TXD

GPIO_ALS_IRQ_L

GPIO_SPKAMP_LEFT_IRQ_L

UART2_ACC_RXD
UART2_ACC_TXD

GPIO_WLAN_HSIC_DEV_RDY
GPIO_WLAN_HSIC_HOST_RDY
UART3_WLAN_RXD
UART3_WLAN_TXD

UART4_BB_CTS_L
UART4_BB_RTS_L
UART4_BB_RXD
UART4_BB_TXD

UART5_BATT_RTXD

9

IN

9

IN

9

IN

18

IN

18

IN

12 44

OUT

10 44

IN

10 44

OUT

21

44

IN

21 44

OUT

21 44

IN

21

44

OUT

17

OUT

15

OUT

10 44

IN

10 44

OUT

21

IN

21

OUT

21

44

IN

21 44

OUT

21 44

IN

21 44

OUT

10 21 44

IN

10 21 44

OUT

40 42 44

BI

D

C

A1

=PP1V8_IO_H4

6 8

39

=PP1V8_S2R_MISC

4 9

10 15 42 44

10 15 42 44

18 19 44

18 19 44

17 18 44

17 18 44

39

I2C0_SDA

4

I2C0_SCL

4

I2C1_SDA

4

I2C1_SCL

4

I2C2_SDA

4

I2C2_SCL

4

10 39

10 39

=PP1V8_ALWAYS

39

=PP1V8_S2R_MISC

4 9

=PP1V8_H4

3 6 9

1

R0700

2.2K

5%
1/32W
MF
01005

2

R0771

220K

12

5%

1/32W

MF

01005

R0770

220K

12

5%

1/32W

MF

01005

R0765

220K

12

5%

1/32W

MF

01005

1

2

R0701

2.2K

5%
1/32W
MF
01005

1

2

GPIO_BTN_HOME_L

GPIO_BTN_POWER_L

GPIO_BTN_SRL_L

(SCREEN ROTATION LOCK)

1

R0702

1.8K

5%
1/32W
MF
01005

R0703

1.8K

5%
1/32W
MF
01005

2

4

12 42

GPIO_MLC_RST_1V8_L

4

IN

4

20 42

4

20 42

1

R0704

2.2K

5%
1/32W
MF
01005

2

1

R0705

2.2K

5%
1/32W
MF
01005

2

1

R0739

100K

1%
1/32W
MF
01005

2

1

R0735

100K

1%
1/32W
MF
01005

2

1

R0736

100K

1%
1/32W
MF
01005

2

1

R0737

100K

1%
1/32W
MF
01005

2

1

R0738

100K

1%
1/32W
MF
01005

2

GPIO_SPKAMP_RST_L
GPIO_PMU_KEEPACT
GPIO_MLC_RST_1V8_L
GPIO_FORCE_DFU
GPIO_DFU_STATUS

C1

B2

B

A

6 3

A6

A1

VCCA

U0701

SN74LVC1T45YZPR

BGA

A

NOSTUFF

DIR

GND

B1

R0750

0.00

12

0%

1/32W

MF

01005

4

15

4

42

4

4 9

4

A7

A2

VCCB

A10

=PP3V0_MLC_RST_LEVELSHIFTER

NOSTUFF

1

C0701

0.1UF

20%

6.3V

2

X5R-CERM
01005

C2

B

GPIO_MLC_RST_L

SYNC_MASTER=N/A

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

OUT

Apple Inc.

R

39

16

AP: I/Os

SYNC_DATE=05/05/2011

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

7 OF 102

SHEET

4 OF 46

SIZE

B

A

D

124578

A9

A8

A5

A4A3A2

87

39

D

6 5

=PP1V8_NAND_H4

5 8

R0831

1

100K

1%
1/32W
MF
01005

2

FMI0_CE0_L

11 44

OUT

NC_FMI0_CEN1
NC_FMI0_CEN2
NC_FMI0_CEN3

AF28

AE26

AF25
AF26

FMI0_CEN0

FMI0_CEN1
FMI0_CEN2

FMI0_CEN3

4 3

OMIT

U0652

H4A

BGA

POP-512MB-DDR

(4 OF 12)

12

D

FMI0_AD<0>

11 44

BI

FMI0_AD<1>

11 44

BI

FMI0_AD<2>

11 44

BI

FMI0_AD<3>

11 44

BI

FMI0_AD<4>

11 44

BI

FMI0_AD<5>

11 44

BI

FMI0_AD<6>

11 44

=PP1V8_NAND_H4

5 8

39

C

11 44

OUT

FMI1_CE0_L

R0832

1

100K

1%
1/32W
MF
01005

2

BI

FMI0_AD<7>

11 44

BI

FMI0_ALE

11 44

OUT

FMI0_CLE

11 44

OUT

FMI0_WE_L

11 44

OUT

FMI0_RE_N

11 44

OUT

FMI1_AD<0>

11 44

BI

FMI1_AD<1>

11 44

BI

FMI1_AD<2>

11 44

BI

FMI1_AD<3>

11 44

BI

FMI1_AD<4>

11 44

BI

FMI1_AD<5>

11 44

BI

FMI1_AD<6>

11 44

BI

FMI1_AD<7>

11 44

BI

FMI1_ALE

11 44

OUT

FMI1_CLE

11 44

OUT

FMI1_WE_L

11 44

OUT

FMI1_RE_N

11 44

OUT

FMI0_DQS_P

11 44

NC_FMI1_CEN1
NC_FMI1_CEN2
NC_FMI1_CEN3

FMI1_DQS_P

11 44

B

AC28
AC26

AD29

AD26
AE25

AG28

AG26
AG27

AD25

AE28

AC25
AD28

AE27

AB30
AB26

AA25

AB25

W27

Y28

Y26

AA31

AA28
AB28

AA29

AB29

AB31
AA26

Y25

Y29

AA27

FMI0_IO0

FMI0_IO1

FMI0_IO2
FMI0_IO3

FMI0_IO4

FMI0_IO5
FMI0_IO6

FMI0_IO7

FMI0_ALE
FMI0_CLE

FMI0_WEN

FMI0_REN
FMI0_DQS

FMI1_CEN0

FMI1_CEN1

FMI1_CEN2
FMI1_CEN3

FMI1_IO0
FMI1_IO1

FMI1_IO2

FMI1_IO3
FMI1_IO4

FMI1_IO5

FMI1_IO6
FMI1_IO7

FMI1_ALE

FMI1_CLE
FMI1_WEN

FMI1_REN

FMI1_DQS

C

VSS

B6B5B3

B9

B8

B2

B11

B12

B13

B15

B16

B17

B

A

SYNC_MASTER=N/A

PAGE TITLE

AP: FLASH MEMORY INTERFACE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

8 OF 102

SHEET

5 OF 46

124578

SIZE

A

D

87

6 5

4 3

12

PART NUMBER

VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

D

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP_AP_MIPI0D_0P4V

TV/DISPLAYPORT

VOLTAGE=0.4V

MIN_NECK_MIDTH SHOULD BE 0.2MM

MIPI

=PP1V8_MIPI_H4

=PP1V8_DPORT_H4

=PP1V8_IO_H4

4 8

39

=PP1V0_DPORT_H4

C

NC_DAC_COMP

NC_DAC_VREF

NC_DAC_IREF

NC_DP_PAD_DC_TP

NC_DP_PAD_R_BIAS

C23

DAC_COMP

H24

DAC_VREF

C24

DAC_IREF

P24

DP_PAD_DC_TP

N27

DP_PAD_R_BIAS

B

E23

E22

DAC_AVDD18A

DAC_AVDD18D

12MA

DAC_AVSS18A

DAC_AVSS18D

D23

D22

M27

L24

K26

DP_PAD_AVDD0

DP_PAD_AVDD1

77MA 77MA

OMIT

DP_PAD_AVDD_AUX

8MA

U0652

H4A

BGA

POP-512MB-DDR

(6 OF 12)

DP_PAD_AVSS0

DP_PAD_AVSS1

DP_PAD_AVSS_AUX

N24

M24

L25

M25

N25

DP_PAD_AVDDX

15MA

DP_PAD_AVDDP0

11MA

5MA

DAC_OUT3

DAC_OUT2
DAC_OUT1

DP_HPD

DP_PAD_AUXP

DP_PAD_AUXN

DP_PAD_TX0P

DP_PAD_TX0N

DP_PAD_TX1P
DP_PAD_TX1N

DP_PAD_AVSSX

DP_PAD_AVSSP0

M26

N26

P26

P25

DP_PAD_DVDD

A21

A22

A23

E27

K31
J31

G31

F31

D31

C31

DP_PAD_DVSS

NC_DAC_OUT3

NC_DAC_OUT2
NC_DAC_OUT1

NC_DP_HPD

NC_DP_PAD_AUXP
NC_DP_PAD_AUXN

NC_DP_PAD_TX0P

NC_DP_PAD_TX0N

NC_DP_PAD_TX1P
NC_DP_PAD_TX1N

39

39

39

39

12

OUT

20 45

IN

20 45

IN

20 45

IN

20 45

IN

20 45

OUT

20

45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

16 45

OUT

1

C0907

0.1UF

20%

6.3V

2

X5R-CERM
01005

=PP1V0_MIPI_H4

1

C0930

1UF

20%

6.3V

2

X5R
0201

DISPLAY_SYNC

MIPI0C_CAM_REAR_DATA_P<0>
MIPI0C_CAM_REAR_DATA_N<0>

MIPI0C_CAM_REAR_DATA_P<1>
MIPI0C_CAM_REAR_DATA_N<1>

NC_MIPI0C_CAM_REAR_DATA_P<2>

9

NC_MIPI0C_CAM_REAR_DATA_N<2>

9

NC_MIPI0C_CAM_REAR_DATA_P<3>

9

NC_MIPI0C_CAM_REAR_DATA_N<3>

9

MIPI0C_CAM_REAR_CLK_P
MIPI0C_CAM_REAR_CLK_N

MIPI0D_DATA_P<0>
MIPI0D_DATA_N<0>

MIPI0D_DATA_P<1>
MIPI0D_DATA_N<1>

MIPI0D_DATA_P<2>
MIPI0D_DATA_N<2>

MIPI0D_DATA_P<3>
MIPI0D_DATA_N<3>

MIPI0D_CLK_P
MIPI0D_CLK_N

1

2

C0908

0.1UF

20%

6.3V
X5R-CERM
01005

1

2

C0903

0.1UF

20%

6.3V
X5R-CERM
01005

AM10

AM30

AM31

AL30

AL31

AJ30

AJ31

AH30

AH31

AK30

AK31

AN25

AP25

AN26

AP26

AN28

AP28

AN29

AP29

AN27
AP27

MIPI_VSYNC

MIPI0C_DPDATA0

MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI0C_DPDATA2

MIPI0C_DNDATA2

MIPI0C_DPDATA3

MIPI0C_DNDATA3

MIPI0C_DPCLK

MIPI0C_DNCLK

MIPI0D_DPDATA0

MIPI0D_DNDATA0

MIPI0D_DPDATA1
MIPI0D_DNDATA1

MIPI0D_DPDATA2

MIPI0D_DNDATA2

MIPI0D_DPDATA3
MIPI0D_DNDATA3

MIPI0D_DPCLK

MIPI0D_DNCLK

AG17

AG18

AG19

AG20

45MA

POP-512MB-DDR

AG21

AG22

AG23

MIPI_VDD10

OMIT

U0652

H4A

BGA

(5 OF 12)

MIPI_VSS

AJ19

AJ23

MIPI0D_VDD

4MA

AJ18

ISP0_PRE_FLASH

ISP1_PRE_FLASH

MIPI1C_DPDATA0

MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1D_DPDATA0
MIPI1D_DNDATA0

MIPI1D_DPDATA1

MIPI1D_DNDATA1

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP_AP_MIPI1D_0P4V

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V0_MIPID_PLL_F

AJ22

AJ17

AJ21

MIPI0D_VDD10_PLL

MIPI0D_VREG_0P4V

MIPI1D_VDD10_PLL

MIPI1D_VREG_0P4V

6.6MA

ISP0_SDA

ISP0_SCL

ISP1_SDA

ISP1_SCL

ISP0_FLASH

SENSOR0_CLK

SENSOR0_RST

ISP1_FLASH

SENSOR1_CLK

SENSOR1_RST

MIPI1C_DPCLK

MIPI1C_DNCLK

MIPI1D_DPCLK

MIPI1D_DNCLK

1

2

AC1

AP7

AL20

AN3

AL17

AL13

AP19
AN8

AL19

AL10

AP11
AP18

AG30

AG31

AE30

AE31

AF30

AF31

AL28

AL29

AJ28
AJ29

AK28

AK29

C0961

27PF

5%
16V
NP0-C0G
01005

1

2

44

80-OHM-0.2A-0.4-OHM

R0931

2.2K

5%
1/32W
MF
01005

1

2

1

R0932

2.2K

5%
1/32W
MF
01005

2

C0963

1

C0962

0.1UF

20%

6.3V

2

X5R-CERM
01005

1

R0930

2.2K

5%
1/32W
MF
01005

2

NC_ISP0_FLASH

NC_ISP0_PRE_FLASH

ISP0_CAM_REAR_CLK_R

44

NC_ISP1_FLASH

NC_ISP1_PRE_FLASH

ISP1_CAM_FRONT_CLK_R

NC_MIPI1C_CAM_FRONT_DATA_P<1>

NC_MIPI1C_CAM_FRONT_DATA_N<1>

NC_MIPI1D_AP_DATA_P<0>

NC_MIPI1D_AP_DATA_N<0>

NC_MIPI1D_AP_DATA_P<1>

NC_MIPI1D_AP_DATA_N<1>

NC_MIPI1D_AP_CLK_P

NC_MIPI1D_AP_CLK_N

1UF

20%

6.3V
X5R
0201

49.9

100

01005

01005

FL0911

0201-1

1

R0933

2.2K

5%
1/32W
MF
01005

2

ALTERNATE FOR
PART NUMBER

155S0359155S0725

1

C0902

2.2NF

10%
10V

2

X5R-CERM
0201

1

C0920

2.2NF

10%
10V

2

X5R-CERM
0201

21

12

12

R0941

R0940

9

9

9

9

9

9

9

9

BOM OPTION

REF DES

FL0911

=PP1V0_MIPI_PLL_H4

=PP1V8_H4

ISP0_CAM_REAR_SDA
ISP0_CAM_REAR_SCL

ISP1_CAM_FRONT_SDA
ISP1_CAM_FRONT_SCL

ISP0_CAM_REAR_CLK

ISP0_CAM_REAR_SHUTDOWN

ISP1_CAM_FRONT_CLK

ISP1_CAM_FRONT_SHUTDOWN

MIPI1C_CAM_FRONT_DATA_P<0>
MIPI1C_CAM_FRONT_DATA_N<0>

MIPI1C_CAM_FRONT_CLK_P
MIPI1C_CAM_FRONT_CLK_N

COMMENTS:

RADAR: 11363497

39

3 4 9

39

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

20 44

20 44

17

17 44

20 44

20

17

17

17 45

17 45

17 45

17 45

44

44

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

AH22

AH23

AH21

AH20

AH19

AH18

AH17

A

6 3

SYNC_MASTER=MLB

PAGE TITLE

AP: TV/DP/MIPI/CAMERA

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/04/2012

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

9 OF 102

SHEET

6 OF 46

124578

SIZE

A

D

87

=PP1V2_S2R_H4

7

39

1

R1005

2.21K

1%
1/32W
MF
01005

2

PPVREF_DDR0_CA

1

R1006

2.21K

1%

D

=PP1V2_VDDQ_H4

7

39

1/32W
MF
01005

2

1

R1053

1.00K

1%
1/32W
MF
01005

2

1

R1054

1.00K

1%
1/32W
MF
01005

2

NOSTUFF

1

C1002

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR0_DQ

NOSTUFF

1

C1054

0.01UF

10%

6.3V

2

X5R

01005

7

44

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

7

44

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

=PP1V2_S2R_H4

7

39

CRITICAL

0.22UF

C

=PP1V2_S2R_H4

7

39

1

R1051

2.21K

1%
1/32W
MF
01005

2

PPVREF_DDR1_CA

1

R1052

2.21K

1%
1/32W
MF
01005

2

=PP1V2_VDDQ_H4

7

39

1

R1055

1.00K

1%
1/32W
MF
01005

B

2

1

R1056

1.00K

1%
1/32W
MF
01005

2

NOSTUFF

1

C1052

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR1_DQ

NOSTUFF

1

C1056

0.01UF

10%

6.3V

2

X5R

01005

7

44

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

7

44

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

CRITICAL

C1027

0.22UF

6.3V

0201

=PP1V2_VDDQ_H4

7

39

6.3V

0201

CRITICAL

1

C1029

0.22UF

20%

2

X5R

CRITICAL

1

C1028

0.22UF

20%

2

X5R

6 5

=PP1V2_S2R_H4

7

39

C1001

0.01UF

6.3V

01005

1

10%

2

X5R

L12

DDR0_VDDQ_CKE

T10

DDR1_VDDQ_CKE

AP15

DDR0_VREF_CA

Y31

DDR1_VREF_CA

B19

DDR0_VREF_DQ

Y2

DDR1_VREF_DQ

AP10

DDR0_ZQ

AD31

DDR1_ZQ

P30

Y30

AC30
AN12

VDDCA
AN16

AN21

A18
A19

A28

C2

L30

W1

Y1
AA30

AD30

AJ1
AN14

AN23

AP9

A20

B28

C1

M30

AA2
AE29

AJ2
AN10

AN24

B4
B7

B10

B14

B18

B20

B24

B27

C30

E2

F30

J30

K2

M2

R2
W2

AE2

AH2

AL2

AN4

AN7

C1004

6.3V

0201

20%

6.3V
X5R

0201

20%

X5R

1

2

CRITICAL

1

0.22UF

2

CRITICAL

C1030

0.22UF

C1005

20%

6.3V
X5R

0201

6.3V

0201

20%

X5R

39

1

2

R1001

240

12

12

240

R1000

CRITICAL

1

C1006

0.22UF

2

=PP1V8_S2R_H4

CRITICAL

C1015

4.7UF

X5R-CERM1

CRITICAL

1

C1024

4.7UF

20%

6.3V
2

X5R-CERM1

402

CRITICAL

C1031

0.22UF

20%

6.3V
X5R

0201

1%

1/20W

1/20W1%201

(DDR IMPEDANCE CONTROL)

CRITICAL

1

C1007

0.22UF

20%

6.3V
2

X5R

0201

CRITICAL

C1009

4.7UF

X5R-CERM1

CRITICAL

1

C1019

0.22UF

20%

6.3V
2

402

C1026

0.01UF

6.3V

01005

CRITICAL

1

C1032

0.22UF

6.3V

2

0201

C1000

0.01UF

10%

6.3V
X5R

01005

PPVREF_DDR0_CA

7

44

PPVREF_DDR1_CA

7

44

PPVREF_DDR1_DQ

7

44

PPVREF_DDR0_DQ

7

44

DDR0_ZQ

201

MF

DDR1_ZQ

MF

1

20%

6.3V

2

X5R

0201

1

20%

6.3V
2

402

1

20%

6.3V
2

X5R

0201

1

10%

2

X5R

1

20%

2

X5R

1

2

<1MA

<1MA

POP-512MB-DDR

80MA

VDD2

320MA (DRAM CORE)

20MA

VDD1

(DRAM CORE - CHARGE PUMP)

VDDQ

500MA

4 3

=PP1V2_VDDIOD_H4

OMIT

U0652

H4A

BGA

(7 OF 12)

VSS

B21

B22

B23
B26

B30

B31

C3
C4

C5

C6

C7
C8

C9

C10

C11
C12

C13
C14

C15

C16
C17

C18

C19
C20

C21

C22
C25

C28

D1
D2

D3

D4
D5

D6

D7
D8

D9

D10
D11

D12

D13
D14

D15

D24
D27

D30

E1
E3

E4
E5

E6

E7
E8

E9

E10
E11

E12

E13
E14

E15
E24

E28

E30
E31

F1

F3

39

=PP1V8_VDDIO18_H4

39

CRITICAL

C1039

0.22UF

6.3V

0201

CRITICAL

C1036

0.22UF

6.3V

0201

CRITICAL

C1042

4.7UF

6.3V

X5R-CERM1

20%

X5R

20%

X5R

20%

402

CRITICAL

C1034

4.7UF

6.3V

X5R-CERM1

CRITICAL

1

0.22UF

2

CRITICAL

1

0.22UF

2

CRITICAL

1

0.22UF

2

20%

402

C1040

C1037

C1043

6.3V

0201

6.3V

0201

6.3V

0201

1

2

1

20%

2

X5R

1

20%

2

X5R

1

20%

2

X5R

C1035

0.01UF

6.3V

01005

CRITICAL

C1041

0.22UF

6.3V

0201

CRITICAL

C1038

0.22UF

6.3V

0201

12

G7
G9

AE16

AE15

AE14

AE13

AE12

AE11

AE10

G11

G13
G15

H10

H12
H14

H16

J10
J11

J12

J13
J14

J15
J16

AA7

AA8

AB9

AC9

AD9

AE9

H20

H19

H6

H8

J7
J8

J9

K6

K8
L7

L8

M6
M8

N7

N8
P6

P8
R7

R8

T6
T8

U7

U8
V6

V8

W7
W8

Y6
Y8

VDDIOD

VDDIO18_GRP1

VDDIO18_GRP2

VDDIO18_GRP3

1

10%

2

X5R

1

20%

2

X5R

1

20%

2

X5R

OMIT

U0652

H4A

BGA

POP-512MB-DDR

(9 OF 12)

500MA

(VDDQ = VDDIOD)

(DON’T DOUBLE COUNT)

75MA

GPIO
EHCI (UNUSED)
UART[1-3] (1-2 UNUSED)
I2C[0-1]
ISP[0-1]
DWI
SENSOR[0-1]
ISP FLASH (UNUSED)
I2S[0-3] (1 UNUSED)
SPI[0-2] (0,2 UNUSED)

11MA - VSEL30_X,CFSB,TEST

2MA - XI/0

VSS

K7
K9

K10

K11
K13

K15

K17
K19

K21
K23

K24

K27
K28

K29

K30
L1

L3

L5
L6

L10
L14

L16

L18
L20

L22

L26
L27

L28

L29
L31

M4
M5

M7

M9
M11

M13

M15
M17

M19

M21
M23

M29
N4

N5

N6
N10

N12

N14
N16

N18

N20
N22

N29
N30

P1

P3

P4
P5

P7

P9
P11

P13

P15
P17

P19
P21

P23

P29
P31

R4

R5
R6

D

C

B

A

SYNC_MASTER=N/A

PAGE TITLE

AP: PWR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

10 OF 102

SHEET

7 OF 46

124578

SIZE

A

D

87

=PPVDD_SOC_H4

X5R-CERM1

CRITICAL

C1110

0.22UF

6.3V

0201

CRITICAL

C1116

0.22UF

6.3V

0201

CRITICAL

C1122

0.22UF

6.3V

0201

39

CRITICAL

C1104

4.7UF

6.3V

20%

X5R

20%

X5R

20%

X5R

20%

402

1

2

1

2

1

2

1

2

X5R-CERM1

CRITICAL

C1111

0.22UF

CRITICAL

C1117

0.22UF

CRITICAL

C1123

0.22UF

CRITICAL

C1105

4.7UF

6.3V

20%

6.3V
X5R

0201

20%

6.3V
X5R

0201

20%

6.3V
X5R

0201

CRITICAL

1

20%

2

402

1

0.22UF

2

1

0.22UF

2

1

0.22UF

2

AJ3

AJ4
AJ5

AJ6

AJ7
AJ8

AJ9
AJ10

AJ11

AJ12
AJ13

AJ14

AJ15
AJ16

AJ20

AK4

K1

AK6

AK7

AK8

AK9
AK10

AK11

AK12
AK13

AK14

AK15
AK16

AK17
AK18

AK19

AK20
AK21

AK22

AK23

T31

AL5

AL6

AL7

AL8

C1106

10UF

CRITICAL

C1112

6.3V

0201

CRITICAL

C1118

6.3V

0201

CRITICAL

C1124

6.3V

0201

1

20%

6.3V
2

X5R
603

1

20%

2

X5R

1

20%

2

X5R

1

20%

2

X5R

POP-512MB-DDR

R10

R12
R14

R16
R18

R20

R22

AA10
AA12

AA14

AA16
AA18

AA20

AA22

AB11

R24

R28

R29
R30

T11
T13

T15

T17
T19

T21

T23
T28

G19

T30

U10
U12

U14

U16
U18

U20

U22
U24

U28
H17

U30

J17

V11
V13

V15
V17

V19

V21
V23

V28

V29

W10
W12

W14
W16

W18

W20
W22

W24

Y11

Y13
Y15

Y17

Y19
Y21

Y23

Y27
AA1

AA4

AA5
AA6

AB2

AB6

AB7
AB8

T4

T5
T7

U3

U4
U5

U6

V1

V4

V5
V7

V9

W5

W6

Y3
Y5

Y7

Y9

D

C

B

A

OMIT

U0652

H4A

BGA

POP-512MB-DDR

(11 OF 12)

AB13

AB15
AB17

AB19
AB21

AB23

AB27
AC2

AC3

AC5
AC6

AC7

AC8
AC10

AC12
AC14

AC16

AC18
AC20

AC22

AC29
AC31

AD1

AD2
AD4

AD6
AD7

AD8

AD11
AD13

AD15

AD17
AD19

AD21

AD23
AD27

AE3
AE6

AE7

AE8
AE18

AE20

AE22

VSSVSS

AF3

J22

AF6
AF7

AF8
AF9

AF10

AF11
AF12

AF13

AF14
AF15

AF16

AF17
AF19

AF21
AF23

AF24

AF27
AF29

AG1

AG4
AG6

AG7

AG8
AG9

AG10
AG11

AG12

AG13
AG14

AG15

AG16
AG24

AG25

AG29
AH6

AH7
AH8

AH9

AH10
AH11

AH12

AH13
AH14

AH15

AH16
AH26

AH29

6 5

OMIT

U0652

H4A

BGA

POP-512MB-DDR

(10 OF 12)

4.2A

GRAPHICS
LOWPERF
APPLE MC
HPERF NRT
HPERF RT
CDIO
DISP_OUT
AUDIO COMPLEX
AUDIENCE DSP
USB
PMGR

CRITICAL

C1107

4.7UF

20%

6.3V

X5R-CERM1

402

CRITICAL

C1113

0.22UF

20%

6.3V
X5R

0201

CRITICAL

C1119

0.22UF

20%

6.3V
X5R

0201

CRITICAL

C1125

0.22UF

20%

6.3V
X5R

0201

C1128

0.01UF

10%

6.3V
X5R

01005

OMIT

U0652

H4A

BGA

(12 OF 12)

1

2

1

2

1

2

1

2

1

2

CRITICAL

C1108

4.7UF

X5R-CERM1

CRITICAL

C1114

0.22UF

CRITICAL

C1120

0.22UF

CRITICAL

C1126

0.22UF

C1129

0.01UF

6.3V

20%

402

6.3V

0201

6.3V

0201

6.3V

0201

6.3V

01005

VSSVSS

K14

K16
K18

K20
K22

L17

CRITICAL

C1109

4.7UF

X5R-CERM1

0.01UF

AL9

AL11
AL12

AL15

AL18
AL21

AL22
AL23

AL24

AL25
AL26

AL27

AM5
AM8

V30

AM14
AM17

V31
AM23

AM24

AM25
AM26

AM27

AM28
AM29

AN1

AN2
AN9

AN15
AN30

AN31

AP1
AP2

AP3

AP6
AP12

AP16

AP22
AP24

AP30

AP31

20%

6.3V

402

CRITICAL

C1115

0.22UF

6.3V

0201

CRITICAL

C1121

0.22UF

6.3V

0201

CRITICAL

C1127

0.22UF

6.3V

0201

C1130

10%

6.3V
X5R

01005

1

2

1

20%

2

X5R

1

20%

2

X5R

1

20%

2

X5R

1

2

1

2

1

20%

2

X5R

1

20%

2

X5R

1

20%

2

X5R

1

10%

2

X5R

L19
L21

L23

M18
M20

M22

N17
N19

N21
N23

P18

P20
P22

R17

R19
R21

R23

T18
T20

T22
T24

U17

U19
U21

U23

V18
V20

V22

W11

W13
W15

W17

W19
W21

W23

Y10

VDD

W9

VDD

6 3

4 3

=PPVDD_CPU_H4

1

2

39

CRITICAL

C1137

0.22UF

6.3V

0201

6.3V

6.3V

0201

6.3V

0201

CRITICAL

C1132

4.7UF

20%

6.3V

X5R-CERM1

402

CRITICAL

C1134

4.7UF

20%

6.3V

402

CRITICAL

C1140

0.22UF

20%

6.3V
X5R

0201

CRITICAL

C1143

0.22UF

20%

6.3V
X5R

0201

C1145

0.01UF

10%

6.3V
X5R

01005

=PP3V3_USB_H4

3

39

1

2

1

2

1

2

1

2

1

2

1

20%

2

402

1

20%

2

X5R

1

20%

2

X5R

CRITICAL

C1131

4.7UF

X5R-CERM1

CRITICAL

1

C1138

0.22UF

20%

X5R

6.3V

2

0201

CRITICAL

1

C1139

0.22UF

20%

2

X5R

CRITICAL

C1142

0.22UF

0.01UF

=PP1V8_IO_H4

4 6

39

0.01UF

=PP1V8_NAND_H4

5

39

CRITICAL

C1149

4.7UF

X5R-CERM1

=PP1V8_VDDIOD3_H4

39

CRITICAL

C1151

4.7UF

X5R-CERM1

Y12

Y14
Y16

Y18
Y20

Y22

AA9
AA11

AA13

AA15
AA17

AA19

AA21
AA23

AB10
AB12

AB14

AB16
AB18

AB20

AB22
AC11

AC13

AC15
AC17

AC19
AC21

AC23

AD10
AD12

AD14

AD16
AD18

AD20

AD22
AE17

AE19
AE21

AE23

AF18
AF20

AF22

CRITICAL

C1136

0.22UF

6.3V

0201

20%

X5R

CRITICAL

C1133

4.7UF

X5R-CERM1

CRITICAL

C1135

4.7UF

X5R-CERM1X5R-CERM1

0.22UF

0.22UF

0.01UF

C1147

6.3V

01005

C1148

6.3V

01005

20%

6.3V

402

20%

6.3V

402

20%

6.3V

402

20%

6.3V

402

CRITICAL

C1141

6.3V

0201

CRITICAL

C1144

6.3V

0201

C1146

6.3V

01005

10%

X5R

10%

X5R

1

2

1

2

12

OMIT

L9

1

2

1

2

1

20%

2

X5R

1

20%

2

X5R

1

10%

2

X5R

1

2

1

2

L11

L13
L15

M10

M12
M14

M16

N9
N11

N13

N15
P10

P12
P14

VDD_CPU

P16

R9
R11

R13

R15
T12

T14

T16

U9

U11
U13

U15

V10
V12

V14

V16

U25

VDDIO30_USB11_DM

AH27

VDDIOD1

AA24

AB24

AC24
AD24

VDDIOD2

AE24

Y24
J25

K25

VDDIOD3

SYNC_MASTER=N/A

PAGE TITLE

U0652

H4A

BGA

POP-512MB-DDR

(8 OF 12)

2.4A

A9 CORES
L2 CACHE
BIU

UNUSED

(UART4 <= GPIOS)

10MA

(SDIO <= WIFI)

35MA (NAND)

VDDIOD3

35MA

I2C2
UART0
UART5_RTXD
DP_HPD
TST_CLKOUT
TST_STPCLK
WDOG
JTAG

5MA

AP: PWR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

F4
F5

F6
F7

F8

F9
F10

F11

F12
F13

F14

F15
F16

F17
F18

F21

F23
F24

F25

F26
F28

F29

G5
G6

G8
G10

G12

G14
G16

G18

AL3
G22

AN11

G24

VSS

G25

G26
G27

G28

G29
G30

H3

H5
H7

H9

H11
H13

H15
H18

AN19

AP20

H22

F19

H25

H27

H28

H29

H30

H31

J4
J5

J6

J19
J20

F20

G17

J24
J26

J27

J28

J29

K5

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

11 OF 102

SHEET

8 OF 46

SIZE

D

C

B

A

D

124578

87

6 5

4 3

12

BOOT CONFIG ID

D

BOARD ID

C

BOARD REVISION

B

BOOT_CONFIG[3] (GPIO29)

BOOT_CONFIG[2] (GPIO28)

BOOT_CONFIG[1] (GPIO25)

BOOT_CONFIG[0] (GPIO18)

FOR REFERENCE

CURRENT SETTING ->

39

BOARD_ID[3]

BOARD_ID[2]

BOARD_ID[1]

BOARD_ID[0]

X123A

X123B

GPIO_BOARD_REV2

4

GPIO_BOARD_REV1

4

GPIO_BOARD_REV0

4

BRD_REV[2-0]

PROTO 0

000

PROTO 1

001

PROTO 2

010

EVT

011

DVT

100

=PP1V8_H4

3 4 6 9

39

4

4

4

4

BOOT_CONFIG[3:0]

0000 SPI0
0001 SPI3
0010 SPI0 W/TEST
0011 SPI3 W/TEST
0100 FMI0 2CS
0101 FMI0 4CS
0110 FMI0 4CS W/TEST
0111 RESERVED
1000 FMI1 2 CS
1001 FMI1 4 CS
1010 FMI1 4CS W/TEST

1011 RESERVED
1100 FMI0/1 2/2 CS
1101 FMI0/1 4/4 CS

1110 FMI0/1 4/4 CS W/TEST

1111 RESERVED

=PP1V8_H4

3 4 6 9

GPIO_BOARD_ID3

4

GPIO_BOARD_ID2

4

GPIO_BOARD_ID1

4

GPIO_BOARD_ID0

4

ID[3-0] SYSTEM

1010 P105 AP
1011 P105 DEV

1100 P106 AP
1101 P106 DEV

1110 P107 AP
1111 P107 DEV

NOSTUFF

1

R1207

2.2K

5%
1/32W
MF
01005

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. ENABLE PU AND DISABLE PD

3. READ

GPIO_BOOT_CONFIG3

GPIO_BOOT_CONFIG2

GPIO_BOOT_CONFIG1

GPIO_BOOT_CONFIG0

1100

BOARD_ID_P106_P107

1

R1204

2.2K

5%

5%

1/32W

1/32W

MF

MF

01005

01005

2

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

NOSTUFF

1

R1208

2.2K

5%
1/32W
MF
01005

2

1

R1213

2.2K

2

BOOT_CONFIG[3-0]

FMI0/1 2/2 CS

S/W READ FLOW

1

R1209

2.2K

5%
1/32W
MF
01005

2

1

R1200

2.2K

5%
1/32W
MF
01005

2

1

R1201

2.2K

5%
1/32W
MF
01005

2

BOARD_ID_P105_P107

1

R1205

2.2K

5%
1/32W
MF
01005

2

FMI_4CS_TEST

1

R1202

2.2K

5%
1/32W
MF
01005

2

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

FMI_4CS_NOTEST

1

R1203

2.2K

5%
1/32W
MF
01005

2

S/W READ FLOW

BOARD_ID_DEV

1

R1206

2.2K

5%
1/32W
MF
01005

2

=PP1V8_S2R_MISC

4

10 39

GPIO_FORCE_DFU

4

NOTE: PADS USED FOR DEBUG

NOSTUFF

1

R1270

1K

5%
1/20W
MF
201

2

JTAG

XW0601

XW0602

XW0603

JTAG_SOC_TRST_L

1

R1211

100

5%
1/32W
MF
01005

2

JTAG_SOC_SEL

1

R1210

100

5%
1/32W
MF
01005

2

R1260

100

12

1/32W

01005

SHORT-01005

12

SHORT-01005

12

SHORT-01005

12

3

44

OUT

D

3

OUT

5%

MF

SOC_TESTMODE

SOC_TST_STPCLK

SOC_FAST_SCAN_CLK

SOC_HOLD_RESET

3

3

3

3

NC_AP_MIPI0C_DPDATA2

NC_AP_MIPI0C_DNDATA2

NC_AP_MIPI0C_DPDATA3

NC_AP_MIPI0C_DNDATA3

NC_AP_MIPI1D_DPDATA1

NC_AP_MIPI1D_DNDATA1

NC_AP_MIPI1C_DPDATA1

NC_AP_MIPI1C_DNDATA1

SINGLE-PIN NETS

NC_FMI0_DQS_NEG

NC_FMI0_RE_POS

NC_FMI1_DQS_NEG

NC_FMI1_RE_POS

NC_PMU_SHDWN

NC_JTAG_SOC_TDO

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FMI0_DQS_N

FMI0_RE_P

FMI1_DQS_N

FMI1_RE_P

PMU_SHDWN

JTAG_SOC_TDO

NC_MIPI0C_CAM_REAR_DATA_P<2>

NC_MIPI0C_CAM_REAR_DATA_N<2>

NC_MIPI0C_CAM_REAR_DATA_P<3>

NC_MIPI0C_CAM_REAR_DATA_N<3>

NC_MIPI1D_AP_CLK_PNC_AP_MIPI1D_DPCLK

NC_MIPI1D_AP_CLK_NNC_AP_MIPI1D_DNCLK

NC_MIPI1D_AP_DATA_P<0>NC_AP_MIPI1D_DPDATA0

NC_MIPI1D_AP_DATA_N<0>NC_AP_MIPI1D_DNDATA0

NC_MIPI1D_AP_DATA_P<1>

NC_MIPI1D_AP_DATA_N<1>

NC_MIPI1C_CAM_FRONT_DATA_P<1>

NC_MIPI1C_CAM_FRONT_DATA_N<1>

NC_USB_FS_D_PNC_AP_USB11_DPD

NC_USB_FS_D_NNC_AP_USB11_DND

C

11

11

11

11

42

3

44

6

6

6

6

6

6

6

6

6

6

6

6

3

3

B

A

SYNC_MASTER=N/A

PAGE TITLE

AP: MISC & ALIASES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=04/11/2011

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

12 OF 102

SHEET

9 OF 46

124578

SIZE

A

D

6 5

TABLE_5_HEAD

TABLE_5_ITEM

NXP

87

CRITICAL BOM OPTION

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TI

PART#

343S0614

PART NUMBER

343S0620

DESCRIPTION

QTY

1

IC,ASIC,TRISTAR,CBTL1608,A1,WLCSP36

ALTERNATE FOR
PART NUMBER

BOM OPTION

COMMON343S0614

REFERENCE DESIGNATOR(S)

U1300

REF DES

COMMENTS:

IC,ASIC,TRISTAR,THS7383,A1,WLCSP36

U1300

COMMON

D

TRISTAR

=PP3V0_S2R_TRISTAR

39

C

TO USB BB MUX

AP USB

ACCESSORY UART

AP DEBUG UART

BB DEBUG UART

(T’S OFF TO H4A UART4)

1

C1320

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

=PP1V8_S2R_TRISTAR

10 39

MIKEY_TS_P

14 45

MIKEY_TS_N

14 45

USB_BB_D_P

21

44

USB_BB_D_N

44

21

USB_BRICKID

42

SOC_USB_D_P

3

44

SOC_USB_D_N

3

44

UART2_ACC_TXD

4

44

UART2_ACC_RXD

4

44

UART0_DEBUG_TXD

4

44

UART0_DEBUG_RXD

4

44

UART4_BB_RXD

4

21 44

UART4_BB_TXD

4

21 44

JTAG_SOC_TCK

3

44

JTAG_SOC_TMS

3

44

CRITICAL

1

C1300

2

1

C1321

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

0.1UF

20%

6.3V
X5R-CERM
01005

CRITICAL

1

C1360

1.0UF

20%
10V

2

X5R-CERM
0201-1

CRITICAL

1

C1301

0.1UF

20%

6.3V

2

X5R-CERM
01005

THS7383IYKAR

C3

DIG_DP

C4

DIG_DN

A1

USB1_DP

B1

USB1_DN

C2

BRICK_ID

A3

USB0_DP

B3

USB0_DN

E2

UART0_TX

E1

UART0_RX

F2

UART1_TX

F1

UART1_RX

D2

UART2_TX

D1

UART2_RX

A5

JTAG_CLK

B5

JTAG_DIO

F3F4D5

VDD_1V8

VDD_3V0

U1300

WCSP

CON_DET_L

OVP_SW_EN*

SWITCH_EN

HOST_RESET

DVSS

DVSS

CRITICAL

OMIT

ACC_PWR

BYPASS

DVSS

A6C1F5

P_IN
ACC1

ACC2

DP1
DN1

DP2

DN2

SDA
SCL

INT

CRITICAL

1

C1302

4.7UF

10%
25V

2

X5R-CERM
0603

F6

C5

TS_ACC1

E5

TS_ACC2

A2

TS_E75_DPAIR1_P

B2

TS_E75_DPAIR1_N

A4

TS_E75_DPAIR2_P

B4

TS_E75_DPAIR2_N

E3

TS_CON_DET_L

D6

OVP_SW_EN_L

E4

RST_SYSTEM_L

B6

TS_HOST_RESET

D3

I2C0_SDA

D4

I2C0_SCL

C6

PMU_GPIO_TRISTAR_IRQ

E6

TRISTAR_ADD0

CRITICAL

1

C1303

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C1322

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

38

38

38 44

38 44

38 44

38 44

10

OUT

IN

OUT

4

15 42 44

4

15 42 44

VOLTAGE=3V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5MM

TRISTAR BYPASS FOR 3V LDO

10

PP3V3_ACC_FET

38

38

3

21 42

10

OUT

4

42

10

PPVBUS_PROT

1

2

4 3

=PPVCC_MAIN_ACC_SW

=PP1V8_S2R_MISC

4 9

39

GPIO_ACC_SW_POK_L

4

OUT

38

CRITICAL

C1361

1UF

10%

25V
X5R
402

39

=PP3V3_ACC

1

R1321

100K

1%
1/32W
MF
01005

2

LAYOUT NOTE:
ADD THERMAL GND VIAS TO U1350

A2

C1

CRITICAL

1

2

C1350

0.1UF

10%

6.3V
X5R
201

VCC

U1350

LM34904

USMD

ACC_PWR

POK*

GND

CSD68803W15

C1

B2
B1

A2

A1

CRITICAL

ENABLE

ACC_DET*

B1

NOSTUFF

R1350

0.00

12

1%

1/20W

MF

0201

Q1301

BGA

D

G

A1

B2

C2

CRITICAL

S

C3

C2
B3

A3

CRITICAL

1

R1322

220K

5%
1/32W
MF
01005

2

GPIO_ACC_SW_EN

TS_CON_DET_L

1

R1320

1.00M

1%
1/32W
MF
01005

2

PP3V3_ACC_FET

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

12

D

4

IN

10 38

IN

C

10 39

GPIO_ACC_SW_POK

B

L81_MBUS_REF

14

OUT

R1370

0.00

12

0%

1/32W

MF

01005

GPIO_ACC_SW_POK_L

4

10

1

C1362

470PF

2

10%
10V
X5R
01005

3

D

CRITICAL

G

1

Q1300

DMN26D0UFB4

S

DFN

SYM_VER_1

2

B

EITHER TRISTAR OR AP CAN RESET PMU

=PP1V8_S2R_TRISTAR

10 39

1

C1310

0.1UF

20%

6.3V

2

X5R-CERM
01005

SOC_WDOG

3

A

IN

10

IN

TS_HOST_RESET

1

R1310

220K

5%
1/32W
MF
01005

2

1

R1311

220K

5%
1/32W
MF
01005

2

2

1

6 3

6

U1310

NC

CRITICAL

74LVC1G32

SOT891

4

35

NC_U1310_5

PMU_RESET_IN

SIZE

A

D

42

OUT

SYNC_MASTER=N/A

PAGE TITLE

E75 SUPPORT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

13 OF 102

SHEET

10 OF 46

124578

87

6 5

4 3

12

FLASH CONFIGURATIONS

QTY

PART NUMBER

335S0889

335S0871

335S0872

335S0873

D

=PP3V3_NAND

39

1

2

C1490

27PF

5%
16V
NP0-C0G
01005

1

2

C1491

27PF

5%
16V
NP0-C0G
01005

1

C1405

0.22UF

20%

6.3V

2

X5R
0201

C

1

2

1

2

C1492

C1406

0.22UF

20%

6.3V
X5R
0201

27PF

5%
16V
NP0-C0G
01005

1

2

CRITICAL

1

C1451

1UF

20%

6.3V

2

X5R
0201

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

CRITICAL

C1400

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

10UF

20%

6.3V
CERM-X5R
0402-2

CRITICAL

1

C1450

1UF

20%

6.3V

2

X5R
0201

FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>

FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>

CRITICAL

1

2

PPVDDI_NAND_U1400

B

TP_TCKC_U1400
TP_TMSC_U1400

C1401

10UF

20%

6.3V
CERM-X5R
0402-2

CRITICAL

1

2

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM

C1402

10UF

20%

6.3V
CERM-X5R
0402-2

OA0

OB0

1

2

C1404

0.1UF

20%

6.3V
X5R-CERM
01005

G3
H2

J3

K2
L5

K6

J5
H6

G1
J1

L1
N3

N5

L7
J7

G7

IO0-0
IO1-0

IO2-0
IO3-0

IO4-0

IO5-0
IO6-0

IO7-0

IO0-1

IO1-1

IO2-1
IO3-1

IO4-1
IO5-1

IO6-1

IO7-1

TCKC
TMSC

VDDI

OB8

F2M6B6

VCC

VSS

1

C1410

0.1UF

20%

6.3V

2

X5R-CERM
01005

OA8

OF8G0OE0

OD8

OC8

N7

N1

VCCQ

CRITICAL

OMIT

U1400

LGA-12X17

XXNM-XGBX8-MLC-PPN1.5-ODP

CE0*

CLE0
ALE0

WE0*

RE0

RE0*

DQS0

DQS0*

R/B0*

CE1*

CLE1
ALE1

WE1*

RE1

RE1*

DQS1

DQS1*

R/B1*

VREF

A5

A3
C1

E3

B4

C7

H4

F4

E5

C5

C3

D2
E1

D4

D6

M4

K4

E7

G5

A1

ZQ

VSSQ

A7M2L3F6B2

OC0

OD0

OE8

OF0

G8

CRITICAL

1

C1411

10UF

20%

6.3V

2

CERM-X5R
0402-1

FMI0_CE0_L
FMI0_CLE
FMI0_ALE
FMI0_WE_L

FMI0_RE_P
FMI0_RE_N

FMI0_DQS_P
FMI0_DQS_N

FMI1_CE0_L
FMI1_CLE
FMI1_ALE
FMI1_WE_L

FMI1_RE_P
FMI1_RE_N

FMI1_DQS_P
FMI1_DQS_N

FMI_ZQ_U1400

CRITICAL

1

C1412

10UF

20%

6.3V

2

CERM-X5R
0402-2

1

2

IN

IN

IN

IN

9

IN

IN

9

IN

IN

IN

IN

9

IN

IN

9

R1454

243

1%
1/20W
MF
201

CRITICAL

1

C1413

0.22UF

20%

6.3V

2

X5R
0201

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

5

44

VREF_NAND_U1400

335S0900

335S0883

CRITICAL

1

C1414

0.22UF

20%

6.3V

2

X5R
0201

ALTERNATE FOR
PART NUMBER

335S0890

335S0878 16GB

335S0879 32GB

335S0880 64GB

335S0880

335S0880

335S0880

335S0880

C1493

27PF

5%
16V
NP0-C0G
01005

1

2

C1494

27PF

5%
16V
NP0-C0G
01005

1

2

NAND_RDYBSY_L

BOM OPTION

8GB

16GB

16GB335S0881

32GB335S0882

64GB

=PP1V8_NAND

R1455

1

100K

1%
1/32W
MF
01005

2

REF DES

U1400

U1400

U1400

U1400

U1400

U1400

U1400

U1400

11 39

1

R1460

50K

1%
1/32W
MF
01005

2

1

R1461

50K

1%
1/32W
MF
01005

2

COMMENTS:

HYNIX 20NM PPN1.5 8GB

HYNIX 20NM PPN1.5 16GB

HYNIX 20NM PPN1.5 32GB

HYNIX 20NM PPN1.5 64GB

SANDISK 19NM PPN1.5 16GB

SAMSUNG 21NM PPN1.5 16GB

SAMSUNG 21NM PPN1.5 32GB

SAMSUNG 21NM PPN1.5 64GB

=PP1V8_NAND

1

C1460

0.01UF

10%

6.3V

2

X5R
01005

1

C1461

0.01UF

10%

6.3V

2

X5R
01005

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

11 39

PART#

335S0890

335S0878

335S0879

335S0880

DESCRIPTION

1

TOSHIBA 19NM PPN1.5 8GB

1

TOSHIBA 19NM PPN1.5 16GB

1

TOSHIBA 19NM PPN1.5 32GB

1

TOSHIBA 19NM PPN1.5 64GB

REFERENCE DESIGNATOR(S)

U1400

U1400

U1400

U1400

BOM OPTION

8GB

16GB

32GB

64GB

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

D

C

B

A

6 3

SYNC_MASTER=MLB

PAGE TITLE

NAND STORAGE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/04/2012

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

14 OF 102

SHEET

11 OF 46

124578

SIZE

A

D

87

6 5

4 3

12

TOUCH SUBSYSTEM

L1700

=PP5V25_GRAPE

D

=PPVCC_MAIN_GRAPE

39

NOSTUFF

R1750

=PP5V25_GRAPE

12 39

C

=PP1V8_GRAPE

12 39

169K

12

1%

1/20W

MF

201

R1780

0.00

12

0%

1/32W

MF

01005

MAIN2GRAPE_ON

1

R1751

100K

1%
1/32W
MF
01005

2

240OHM-350MA

CRITICAL

1

C1750

0.1UF

10%
16V

2

X5R-CERM
0201

VCC_MAIN_GRAPE_RAMP

CRITICAL

1

C1751

4700PF

10%
10V

2

X7R
201

21

0201

LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION

1

C1700

27PF

5%
16V

2

NP0-C0G
01005

1

C1701

1UF

10%
10V

2

X5R

402

=PP1V8_S2R_GRAPE

39

18

VDD

U1700

SLG5AP302

TDFN

7

CAP

25

ON S

GND

CRITICAL

D

1

C1702

1000PF

10%
16V

2

X7R
201

3

PP5V25_GRAPE_FILT

VOLTAGE=5.25V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

CRITICAL

1

C1752

1UF

20%

6.3V

2

X5R

0201

CRITICAL

1

C1753

10UF

20%
10V

2

X5R-CERM
0402-2

12 12 39

PP1V8_S2R2GRAPE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

SPI1_GRAPE_SCLK

4

44

DISPLAY_SYNC

6

12

R1753

0.00

1/32W

01005

D

RCPT - MLB 998-4526 -> 516S1054

(PLUG - FLEX 998-4527)

CRITICAL

J1700

503304-2010

F-ST-SM-1

R1752

0.00

0%

1/32W

MF

01005

12

0%

MF

NOSTUFF

1

C1761

27PF

5%
16V

2

NP0-C0G
01005

PP3V0_S2R_HALL_FILT

12

44

SPI1_GRAPE_SCLK_R
SPI1_GRAPE_MISO

4

44

SPI1_GRAPE_MOSI

4

44

SPI1_GRAPE_CS_L

4

44

AP_CLK_32K_CUMULUS

44

4

GPIO_GRAPE_IRQ_L

4

GPIO_GRAPE_RST_L

4

PP1V8_GRAPE_FILT

12

DISPLAY_SYNC_R

22

21

1

2

3

4

5

6

8

7

9

10

11

12

14

13

15

16

18

17

19

20

23

24

GPIO_BTN_HOME_FILT_L

PMU_GPIO_HALL_IRQ_4
PMU_GPIO_HALL_IRQ_3
PMU_GPIO_HALL_IRQ_2

PMU_GPIO_HALL_IRQ_1

PP5V25_GRAPE_FILT

12

42

42

42

42

12

C

L1760

GPIO_BTN_HOME_L

4

42

L1701

240OHM-350MA

=PP1V8_GRAPE

B

12 39

=PP3V0_S2R_HALL

240-OHM-0.2A-0.8-OHM

240-OHM-0.2A-0.8-OHM

A

0201

NOSTUFF

L1750

0201

L1702

0201

21

21

1

C1703

27PF

5%
16V

2

NP0-C0G
01005

21

1

C1706

27PF

5%
16V

2

NP0-C0G
01005

1

C1704

2

1

C1707

1UF

20%

6.3V

2

X5R
0201

1UF

20%

6.3V
X5R

0201

1

2

1

C1708

1000PF

10%
16V

2

X7R
201

C1705

1000PF

10%
16V
X7R
201

PP1V8_GRAPE_FILT

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_S2R_HALL_FILT

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

12

12 39

150OHM-25%-200MA-0.7DCR

01005

21

GPIO_BTN_HOME_R_L

1

C1760

27PF

5%
16V

2

NP0-C0G
01005

6 3

R1790

1.00K

12

1%

1/32W

MF

01005

SYNC_MASTER=N/A

PAGE TITLE

GPIO_BTN_HOME_FILT_L

TOUCH: FLEX CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

SYNC_DATE=06/21/2010

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

17 OF 102

SHEET

12 OF 46

124578

SIZE

B

A

D

87

6 5

4 3

12

D

R1850

0.00

DMIC1_FF_SCLK

14 45

L1800

=PP1V8_DMIC

39

0201

240-OHM-0.2A-0.8-OHM

21

1

2

C1800

27PF

5%
16V
NP0-C0G
01005

PP1V8_DMIC_CONN

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

C

12

0%

1/32W

MF

01005

DMIC1_FF_SD

14 45

ANT_PORTB_3

21 25

ANT_PORTB_2

21 25

PP_LDO14_2P65

21 22 27 32 35

ANT_PORTB_1

21 25

DMIC1_FF_SCLK_CONN

45

NOSTUFF

1

C1850

27PF

5%
16V

2

NP0-C0G
01005

1

C1820

56PF

5%
16V

2

NP0-C0G

1

C1821

56PF

5%
16V

2

NP0-C0G
0100501005

1

C1822

56PF

5%
16V

2

NP0-C0G
01005

VOLTAGE=2.65V

MIN_NECK_WIDTH=0.06 MM

1

C1801

0.1UF

10%

6.3V

2

X5R
201

1

C1802

27PF

5%
16V

2

NP0-C0G
01005

P/N 510S0760 - MLB

(P/N 510S0761 - FLEX)

CRITICAL

J1800

AA07-S016VA1

F-ST-SM-COMBO

18

17

1

2

4

3

6

5

7

8

9

10

11

12

13

14

15

16

19

20

CONN_HP_HS4_FILT
CONN_HP_HS4_REF_FILT
CONN_HP_HS3_REF_FILT

CONN_HP_HS3_FILT

CONN_HP_RIGHT_FILT

CONN_HP_LEFT_FILT

CONN_HP_HEADSET_DET

14

14

14

14

14

14

14

AUDIO_JACK_FLEX RET2
AUDIO_JACK_FLEX MIC1

AUDIO_JACK_FLEX MIC2

AUDIO_JACK_FLEX RET1

PER DAVE BREECE

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

AUDIO JACK FLEX CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=03/31/2011

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

13 OF 46

PAGE

18 OF 102

SHEET

124578

87

=PPVCC_MAIN_AUDIO

15 39

=PP1V8_AUDIO

14 39

R1950

1.00

D

=PP1V7_VA_VCP

15 39

CRITICAL

1

C1901

4.7UF

20%

6.3V

2

X5R

GND_AUDIO_CODEC

14

R1901

2.21K

12

MF

1%

1/20W

C

C1911

1.0UF

0201-MUR

6.3V

1

20%

2

X5R

L81_MIC2_BIAS_FILT_IN

XW1902

SHORT-8L-0.25MM-SM

CODEC_HP_HS4_REF

14

CODEC_HP_HS3_REF

14

21

NOSTUFF

XW1903

SHORT-8L-0.25MM-SM

21

NOSTUFF

402

L81_MIC2_BIAS_IN

201

L81_MIC2_BIAS

C1912

4.7UF

12

20%

6.3V
X5R
402

HP_MIC_P

45

HP_MIC_N

45

CRITICAL

1

C1903

1.0UF

20%

6.3V

2

X5R
0201-MUR

L82_MIC2_BIAS_FILT

C1916

0.01UF

12

10%

10V
201 X5R

C1917

0.01UF

12

10V

10%

201

X5R

B

MF

GND_AUDIO_CODEC

14

C1905

4.7UF

6.3V

20%

402

X5R

C1906

4.7UF

6.3V

20%
X5R402

NC_MIC1_BIAS

AIN1P

14

AIN1N

14

MIC1_BIAS_FILT

14

NC_MIC3_BIAS

AIN3P

14

AIN3N

14

MIC3_BIAS_FILT

14

NC_MIC4_BIAS

AIN4P

14

AIN4N

14

MIC4_BIAS_FILT

14

NOSTUFF

CRITICAL

C1918

2.2UF

10%

6.3V
X5R
402

12

1%

1/20W

L81_FLYP

12

L81_FLYC

L81_FLYN

12

45

45

L81_SPEAKER_VQ

1

2

GND_AUDIO_CODEC

MIC1_BIAS_FILT

CODEC_MIC_BIAS_FILT

MAKE_BASE=TRUE

1

C1990

100PF

5%
16V

2

NP0-C0G
01005

MIC3_BIAS_FILT

MIC4_BIAS_FILT

AIN1P

CODEC_AIN

MAKE_BASE=TRUE

1

C1991

100PF

5%
16V

2

NP0-C0G

A

01005

AIN1N

AIN3P

AIN3N

AIN4P

AIN4N

14

14

14

14

14

14

14

14

14

201

1

2

0.3MM

0.15MM

0.3MM

0.15MM

0.3MM

0.15MM

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

L81_AIN2_P
L81_AIN2_N

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

=PP1V8_AUDIO

39

14

42

IN

PP1V7_VCP

CRITICAL

C1950

4.7UF

20%

6.3V
X5R
402

6 5

CRITICAL

1

1

C1909

4.7UF

20%
10V

2

2

X5R-CERM
0402

1

C1914

0.1UF

10%
10V

2

X5R-CERM
0201

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

PPVCC_VPROG_MB_F

1

C1913

0.1UF

10%
10V

2

X5R-CERM
0201

H1

VPROG_MB

H9

L81_PVCP

J9

GNDCP

K9

L81_NVCP

F10

DP
DN

NC_LEFT_CH_OUT_P

F9

NC_LEFT_CH_OUT_N

NO_TEST=TRUE

D10

NO_TEST=TRUE

D9

J4

L81_MBUS_P

K4

L81_MBUS_N

J8

CODEC_HP_LEFT

K8

CODEC_HP_RIGHT

J1

CODEC_HP_HS3

K1

CODEC_HP_HS4

K7

J7
H8

CODEC_HP_DET

NO_TEST=TRUE

K6

NO_TEST=TRUE

J6

H6

E1

L81_FILT

F1

AOUT1+

AOUT2+
AOUT2-

HPOUTA
HPOUTB

FILT+

FILT-

HS3

HS4

GND_AUDIO_CODEC

L81_MBUS_REF

DIGITAL MIC

DMIC1_FF_SD

13 45

IN

DMIC1_FF_SCLK

13 45

IN

I2S0_CODEC_ASP_MCK

I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_DIN

I2S2_CODEC_XSP_BCLK
I2S2_CODEC_XSP_LRCK
I2S2_CODEC_XSP_DOUT
I2S2_CODEC_XSP_DIN
L81_MBUS_REF

R1951

1.00

12

1%

1/20W

201

MF

R1952

255K

12

1%

1/20W

201

MF

0.15MM

0.30MM

0.15MM

0.30MM

NC_RIGHT_CH_OUT_P

NC_RIGHT_CH_OUT_N

NC_CODEC_LINE_OUT_L
NC_CODEC_LINE_OUT_R

CRITICAL

1

C1910

4.7UF

20%

6.3V

2

X5R
402

VOLTAGE=0V

0.15MM

0.20MM

R1912

1/32W

R1913

1/32W

12

R1910

1/32W

5% MF

12

R1911

1/32W

5%

NOTE:

U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846

1

R1953

0

5%
1/20W
MF
201

2

PPVCC_VPROG_MB

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

NO_TEST=TRUE

NO_TEST=TRUE

14 45

14 45

MIN_LINE_WIDTH=0.20MM

14

OUT

12

5%

12

5%

MF

C1902

0.1UF

20%

6.3V
X5R-CERM
01005

CRITICAL

1

C1951

1.0UF

20%

6.3V

2

X5R
0201-MUR

1

2

1

2

VOLTAGE=1.7V
MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.15MM

G1

VA

H10

FLYP

J10

FLYC

K10

FLYN

H2

MIC1_BIAS

E3

AIN1+

E4

AIN1-

H3

MIC1_BIAS_FILT

J3

MIC2_BIAS_IN

G4

MIC2_BIAS

K3

MIC2_BIAS_FILT_IN

F3

MIC2_BIAS_FILT

C1

AIN2+

D1

AIN2M

H4

MIC3_BIAS

C3

AIN3+

C2

AIN3-

G3

MIC3_BIAS_FILT

F4

MIC4_BIAS

D2

AIN4+

E2

AIN4-

F2

MIC4_BIAS_FILT

C10

SPEAKER_VQ

14

NOSTUFF

1

R1940

1.00K

5%
1/32W
MF
01005

2

C1915

0.1UF

20%

6.3V
X5R-CERM
01005

G9

A9E8A8

G8

VD

VCP1

VCP0

CRITICAL

U1900

CS42L81-CWZR-A1

WLCSP

SYM 1 OF 2

GNDP

GNDD

GNDHS

GNDHS

J2

K2

E10

A10

SHORT-8L-0.25MM-SM

44

44

44

44

C1904

0.1UF

10%
10V

X5R-CERM

0201

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

PPVCC_VPROG_CP

E9

G10

VP0VLVP1

VPROG_CP

+VCP_FILT

-VCP_FILT

AOUT1_M

HS3_REF

HS4_REF

HPDETECT

LINEOUTA
LINEOUTB

LINEOUT_REF

GNDA

G2

NOSTUFF
XW1900

21

NOSTUFF

R1914

0

12

5%

1/20W

MF

201

4

44

IN

4

44

IN

4

44

IN

4

44

IN

4

44

IN

4

44

IN

4

44

IN

4

44

IN

4

44

IN

10 14

IN

SPI2_CODEC_CS_L

4

OUT

SPI2_CODEC_SCLK

4

OUT

SPI2_CODEC_MOSI

4

IN

SPI2_CODEC_MISO

4

OUT

GPIO_CODEC_IRQ_L

4

OUT

PMU_GPIO_CODEC_HS_IRQ_L

42

OUT

PMU_GPIO_CODEC_RST_L

CRITICAL

C1907

4.7UF

12

20%

6.3V
402

X5R

CRITICAL

C1908

4.7UF

12

20%
X5R

14

10 14

45

L81_DMIC1_FF_SD

22

MF

01005

L81_DMIC1_FF_SCLK

45

22

01005

MF

NC_DMIC2_SCLK

44

I2S0_CODEC_ASP_SDOUT

22

01005

44

I2S2_CODEC_XSP_SDOUT

22

01005

6.3V
402

MIN_NECK_WIDTH=0.15MM

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

6 3

4 3

PLACE R1930 & R1931 CLOSE TO U3600

14 45

NOSTUFF

R1954

0

12

5%

1/20W

MF

201

GND_AUDIO_CODEC

NO_TEST=TRUE

=PP3V0_SPARE1

14

CODEC_HP_HS3_REF

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

CODEC_HP_HS4_REF

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

B1

DMIC1_SD

B2

DMIC1_SCLK

B7

DMIC2_SD

B6

DMIC2_SCLK

C8

MCLK

A3

ASP_SCLK

B3

ASP_LRCK

A2

ASP_SDIN

A1

ASP_SDOUT

B4

XSP_SCLK

B5

XSP_LRCK_FSYNC

A5

XSP_SDIN_DAC2_MUTE

A4

XSP_SDOUT

K5

MBUS_REF

C5

CS*

A6

CCLK

B8

CDIN

A7

CDOUT

B9

INT*

B10

WAKE*

C9

RESET*

39

CODEC_HP_DET

14

U1900

CS42L81-CWZR-A1

WLCSP

SYM 2 OF 2

R1920

3.3K

12

5%

1/32W

MF

01005

14

14

C6

GND0

D3

GND1

D5

GND2

D6

GND3

D7

GND4

D8

GND5

E5

GND6

E6

GND7

E7

GND8

F5

GND9

F6

GND10

F7

GND11

F8

GND12

G5

GND13

G6

GND14

G7

GND15

H5

GND16

H7

GND17

J5

GND18

C4

TSTI0

C7

TSTI1

D4

TSTI2

14 45

CODEC_HP_DET_R

NOSTUFF

1

C1920

4700PF

10%
10V

2

X7R
201

FERR-33-OHM-0.8A-0.09-OHM

FERR-33-OHM-0.8A-0.09-OHM

FERR-33-OHM-0.8A-0.09-OHM

FERR-33-OHM-0.8A-0.09-OHM

R1930

L81_MBUS_N

240-OHM-0.2A-0.8-OHM

PLACE L1900 TO 1905 CLOSE
TO THE HP CONNECTOR

L1904

120-OHM-210MA

L1905

120-OHM-210MA

PART NUMBER

L1900

0201

L1901

0201

L1902

0201

L1903

0201

01005

01005

R1931

L1920

0201

21

21

21

21

ALTERNATE FOR
PART NUMBER

155S0453155S0773

MIKEY BUS FILTER

SIGNAL_MODEL=EMPTY

1

C1930

100PF

5%
25V

2

NP0-CERM

12

12

5%

1/20W

MF

201

12

12

5%

1/20W

MF

201

21

21

CONN_HP_LEFT_FILT

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

21

CONN_HP_RIGHT_FILT

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CONN_HP_HS3_FILT

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

CONN_HP_HS4_FILT

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

CONN_HP_HS3_REF_FILT

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

CONN_HP_HS4_REF_FILT

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

0201

NOSTUFF

1

C1931

100PF

5%
25V

2

NP0-CERM
0201

SIGNAL_MODEL=EMPTY

1

C1932

100PF

5%
25V

2

NP0-CERM
0201

CONN_HP_HEADSET_DET

BOM OPTION

SYNC_MASTER=KAVITHA

PAGE TITLE

REF DES

L1904,L1905

AUDIO: L81 CODEC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MIKEY_TS_PL81_MBUS_P
MIKEY_TS_N

13

IN

13

OUT

13

OUT

13

IN

13

IN

13

IN

13

IN

COMMENTS:

RADAR:11100717

12

10 45

BI

10 45

BI

TO HEADPHONE JACK

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SYNC_DATE=01/18/2012

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

14 OF 46

PAGE

19 OF 102

SHEET

124578

SIZE

D

C

B

A

D

8 7

6 5 4 3

12

RIGHT SPEAKER AMP

=PPVCC_MAIN_AUDIO

93 51 41

D

CRITICAL

1

C2041

4.7UF

20%
10V

2

X5R-CERM

0402

PP1V7_VA_VCP

14 93

CRITICAL

1

2

44 24 51 01

44 24 51 01

1

C2043

C2044

4.7UF

20%
10V

X5R-CERM

0402

0.1UF

10%
10V

2

X5R-CERM

0201

TBD: PLACEHOLDER FOR SPM3010T-XXX

2.2UH-20%-3.3A-0.11OHM

I2C0_SDA

4

I2C0_SCL

4

GPIO_SPKAMP_RIGHT_IRQ_L

4

GPIO_SPKAMP_RST_L

15

4

GPIO_SPKAMP_KEEPALIVE

4

15

I2S1_SPKAMP_MCK

44 51

4

I2S1_SPKAMP_BCLK

4

44 51

I2S1_SPKAMP_LRCK

4

44 51

I2S1_SPKAMP_DOUT

4

44 51

I2S1_SPKAMP_DIN

4

44 51

CRITICAL

L2040

TFA302610A-SM

1

2

C2092

0.1UF
10%
10V

X5R-CERM

0201

21

L19_R_VBOOST

CRITICAL

CRITICAL

1

1

C2045

10UF

20%
10V

2

2

X5R
603

L19_R_SWITCH

I2C ADDRESS: 1000001X

CRITICAL

1

C2094

C2091

10UF

10UF

20%

20%

10V

10V

2

X5R-CERM

X5R-CERM

0402-1

0402-1

A2

B2

D5

D6

A7

A6

D7

C7

E7

E6

F6

F7

E5

B1

A1

VBST

CS35L19B-CWZR

SW

SDA

SCL

INT*

RESET*

ALIVE

ADO

MCLK

SCLK

LRCK/FSYNC

SDIN

SDOUT

GNDP

B4

B3

A3

C3

C1

C4

A4

D1

U2040

WLCSP

VER1

D4

D3

F5

A5

VA

VP

F2

FILT+

C5

LDO_FILT

E3

VSENSE-

E2

VSENSE+

F1

ISENSE-

E1

ISENSE+

D2

OUT+

C2

OUT-

B7

IREF+

GNDA

B5

B6

F4

F3

C6

E4

C

LEFT SPEAKER AMP

=PPVCC_MAIN_AUDIO

93 51 41

B

CRITICAL

1

C2051

4.7UF

20%
10V

2

X5R-CERM

0402

CRITICAL

1

C2052

4.7UF

20%
10V

2

X5R-CERM

0402

CRITICAL

1

1

C2053

4.7UF

20%
10V

2

X5R-CERM

2

0402

TBD: PLACEHOLDER FOR SPM3010T-XXX

2.2UH-20%-3.3A-0.11OHM

I2C0_SDA

4

44 24 51 01

I2C0_SCL

44 24 51 01

4

GPIO_SPKAMP_LEFT_IRQ_L

4

GPIO_SPKAMP_RST_L

4

15

GPIO_SPKAMP_KEEPALIVE

4

15

I2S1_SPKAMP_MCK

4

44 51

I2S1_SPKAMP_BCLK

44 51

4

I2S1_SPKAMP_LRCK

4

44 51

I2S1_SPKAMP_DOUT

4

44 51

I2S1_SPKAMP_DIN

44 51

4

C2054

0.1UF

10%
10V

X5R-CERM

0201

1

2

L2050

TFA302610A-SM

C2093

0.1UF
10%
10V

X5R-CERM

0201

CRITICAL

1

C2055

10UF

20%
10V

2

X5R
603

21

L19_L_SWITCH

CRITICAL

1

C2090

10UF

20%
10V

2

X5R-CERM

0402-1

A

I2C ADDRESS: 1000000X

L19_L_VBOOST

CRITICAL

1

C2095

10UF

20%
10V

2

X5R-CERM

0402-1

A2
B2

D5

D6

A7

A6

D7

C7

E7

E6

F6

F7

E5

B1

A1

VBST

CS35L19B-CWZR

SW

SDA

SCL

INT*

RESET*

ALIVE

ADO

MCLK

SCLK

LRCK/FSYNC

SDIN

SDOUT

GNDP

B4

B3

A3

C3

C1

C4

D1

A4

U2050

WLCSP

VER1

D4

D3

F5

A5

VA

VP

F2

FILT+

C5

LDO_FILT

E3

VSENSE-

E2

VSENSE+

F1

ISENSE-

E1

ISENSE+

D2

OUT+

C2

OUT-

B7

IREF+

GNDA

B5

B6

F4

F3

C6

E4

6 3

=PP1V7_VA_VCP

1

C2046

0.1UF

10%

6.3V

2

X5R
201

L19_R_FILT
L19_R_LDO_FILT

SPKR_R_VSENSE_N_FILT
SPKR_R_VSENSE_P_FILT

SPKR_R_SES_N
SPKR_R_SES_P

SPKR_R_P

SPKR_R_N

L19_R_IREF

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

1

R2041

44.2K

1%
1/20W
MF
201

2

=PP1V7_VA_VCP

C2056

1

0.1UF

10%

6.3V
X5R

2

201

L19_L_FILT
L19_L_LDO_FILT

SPKR_L_VSENSE_N_FILT
SPKR_L_VSENSE_P_FILT

SPKR_L_SES_N
SPKR_L_SES_P

SPKR_L_P

SPKR_L_N

L19_L_IREF

MIN_LINE_WIDTH=0.5 MM

1

MIN_NECK_WIDTH=0.2 MM

R2051

44.2K

1%
1/20W
MF
201

2

1

2

14 15 39

CRITICAL

C2047

4.7UF

1 2

20%

X5R-CERM1

6.3V

402

CRITICAL

C2048

4.7UF

1 2

X5R-CERM1

20%

402

6.3V

NOSTUFF

C2060

0.01UF

1 2

10%

6.3V

1

R2043

0.00

0%
1/32W
MF

CRITICAL

01005

2

R2040

0.100

1 2

1/4W

0805

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

NOSTUFF

1

C2064

18PF

5%
16V

2

CERM
01005

14 15 39

CRITICAL

C2057

4.7UF

1 2

20%

X5R-CERM1

402

6.3V

CRITICAL

C2058

4.7UF

1 2

X5R-CERM1

20%

6.3V

402

NOSTUFF

C2080

0.01UF

1 2

10%

6.3V

1

R2053

0.00

0%
1/32W
MF
01005

CRITICAL

2

R2050

0.100

1 2

1%

1/4W

MF

0805

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

NOSTUFF

C2084

18PF

5%
16V
CERM
01005

01005

1%

MF

01005

X5R

1

R2042

0.00

0%
1/32W
MF
01005

2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

SPKR_R_FLR

NOSTUFF

1

C2061

18PF

5%
16V

2

CERM
01005

X5R

1

R2052

0.00

0%
1/32W
MF
01005

2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

SPKR_L_FLR

NOSTUFF

1

C2081

18PF

5%
16V

2

CERM
01005

OMIT

FL2041

220-OHM-2.0A

0603

OMIT

FL2040

220-OHM-2.0A

0603

NOSTUFF

C2049

18PF

OMIT

FL2051

220-OHM-2.0A

0603

OMIT

FL2050

220-OHM-2.0A

0603

NOSTUFF

C2059

18PF

01005

CERM

01005

CERM

21

16V

21

21

5%

16V

21

5%

1

2

1

2

NOSTUFF

1

2

NOSTUFF

1

C2050

18PF

5%
16V

2

CERM
01005

C2040

18PF

5%
16V
CERM
01005

PART#

113S0022

SPKR_R_CONN_P

1

2

SPKR_R_CONN_N

NOSTUFF

1

C2066

3.9PF

+/-0.1PF
16V

2

NP0-C0G
01005

SPKR_L_CONN_P

1

2

SPKR_L_CONN_N

NOSTUFF

1

C2086

3.9PF

+/-0.1PF
16V

2

NP0-C0G
01005

DESCRIPTION

QTY

4

RES,MF,1/10W,0 OHM,5%,0603,SMD,LF FL2040,FL2041,FL2050,FL2051

NOSTUFF

1

C2067

100PF

5%

16V

2

NP0-C0G

01005

NOSTUFF

1

C2068

100PF

5%

16V

2

NP0-C0G

01005

38 45

15

NOSTUFF

C2063

3.9PF

+/-0.1PF
16V
NP0-C0G
01005

15 38 45

15 38 45

NOSTUFF

C2083

3.9PF

+/-0.1PF
16V
NP0-C0G
01005

15 38 45

R2045

10K

1 2

1/32W

01005

R2044

1 2

1/32W

01005

NOSTUFF

C2087

100PF

NP0-C0G

01005

NOSTUFF

C2088

100PF

NP0-C0G

01005

5%

MF

10K

54 83 51

54 83 51

54 83 51

54 83 51

16V

16V

5%

MF

5%

5%

REFERENCE DESIGNATOR(S)

SPKR_R_VSENSE_N

SPKR_R_VSENSE_P

SPKR_R_CONN_P

SPKR_R_VSENSE_P

15

SPKR_R_CONN_N

SPKR_R_VSENSE_N

15

SPKR_L_CONN_P

SPKR_L_VSENSE_P

15

SPKR_L_CONN_N

SPKR_L_VSENSE_N

15

1

2

1

2

CRITICAL BOM OPTION

15

15

TABLE_5_HEAD

TABLE_5_ITEM

SPEAKER CONNECTOR

XW2074

SM

SIGNAL_MODEL=EMPTY

1 2

XW2075

SM

SIGNAL_MODEL=EMPTY

1 2

XW2076

SM

SIGNAL_MODEL=EMPTY

1 2

XW2077

R2055

10K

1 2

5%

1/32W

MF

01005

R2054

10K

1 2

5%

1/32W

MF

01005

SM

SIGNAL_MODEL=EMPTY

1 2

PLACE XWS CLOSE TO CONNECTOR

SPKR_L_VSENSE_N

SPKR_L_VSENSE_P

15

15

SYNC_MASTER=KAVITHA

PAGE TITLE

AUDIO: CS35L19A AMPS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

1

C2070

2

Apple Inc.

R

NOSTUFF

100PF

5%

16V

NP0-C0G
01005

NOSTUFF

CRITICAL

C2071

100PF

NP0-C0G

01005

D

C

NOSTUFF

CRITICAL

1

C2072

100PF

5%

16V

2

NP0-C0G
01005

NOSTUFF

CRITICAL

1

5%

16V

2

C2073

100PF

NP0-C0G

01005

1

5%

16V

2

B

SIZE

A

D

SYNC_DATE=01/18/2012

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

4 OF 4

PAGE

20 OF 102

SHEET

15 OF 46

124578

87

6 5

MIPI CONNECTOR

4 3

12

D

=PPVCC_MAIN_LCD

39

VCC_MAIN_LCD_RAMP

GPIO_MLC_PWR_EN

4

IN

1

R2205

100K

1%
1/20W
MF
201

2

CRITICAL

1

C2241

3900PF

10%
50V

2

X7R
0402

LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION

C

B

CRITICAL

1

C2240

0.1UF

10%
16V

2

X5R-CERM
0201

7

CAP

CRITICAL

VDD

U2200

SLG5AP304V

TDFN

GND

81

3

D

52

SON

CRITICAL

1

C2203

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2242

27PF

5%
16V

2

NP0-C0G
01005

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

PPVCC_MAIN_LCD_SW

CRITICAL

1

C2202

10UF

20%
10V

2

X5R-CERM
0402-2

VOLTAGE=4.5V

1

C2230

2

27PF

5%
16V
NP0-C0G
01005

39

FERR-120-OHM-1.5A

1

R2260

2.7K

5%
1/20W
MF
201

2

FERR-240-OHM-25%-300MA

=PPLED_REG

L2201

0402

L2200

0402

21

21

VOLTAGE=4.5V
MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

PPVCC_MAIN_LCD_SW_CONN

1

2

PPLED_BACK_REG

1

C2232

27PF

5%
16V

2

NP0-C0G
01005

GPIO_MLC_RST_L

4

WLED_STRING4

42

IN

WLED_STRING3

42

IN

WLED_STRING2

42

IN

WLED_STRING1

42

IN

WLED_STRING5

42

IN

WLED_STRING6

42

IN

VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

C2206

1000PF

10%
16V
X7R
201

P/N 998-4669 -> 516S1056

CRITICAL

J2201

AA07A-S032-VA1

F-ST-SM-1

3334

2

1

4

3

6

5

8

7

10

12

14

16

18

20

22

24

26

28

30

32

9

11

13

15

17

19

21

23

25

27

29

31

3536

45

MIPI_DATA_CONN_N<3>

45

MIPI_DATA_CONN_P<3>

MIPI_DATA_CONN_N<2>

45

MIPI_DATA_CONN_P<2>

45

MIPI_DATA_CONN_N<1>

45

MIPI_DATA_CONN_P<1>

45

MIPI_DATA_CONN_N<0>

45

MIPI_DATA_CONN_P<0>

45

MIPI_CLK_CONN_N
MIPI_CLK_CONN_P

PART NUMBER

155S0667 155S0583

ALTERNATE FOR
PART NUMBER

BOM OPTION

L2202,L2212,L2222,L2232,L2233,L2610,L2611,L2910,L2911,L2912,L5703,L5704

CRITICAL

L2233

32

4

SYM_VER-2

TCM0605-1

90-OHM-50MA

CRITICAL

L2232

32

4

SYM_VER-2

TCM0605-1

90-OHM-50MA

CRITICAL

L2222

32

4

SYM_VER-2

TCM0605-1

90-OHM-50MA

CRITICAL

L2212

32

4

32

4

TCM0605-1

90-OHM-50MA

CRITICAL

L2202

TCM0605-1

90-OHM-50MA

SYM_VER-2

SYM_VER-2

MIPI0D_DATA_N<3>

1

MIPI0D_DATA_P<3>

MIPI0D_DATA_N<2>

1

MIPI0D_DATA_P<2>

MIPI0D_DATA_N<1>

1

MIPI0D_DATA_P<1>

MIPI0D_DATA_N<0>

1

MIPI0D_DATA_P<0>

1

REF DES

MIPI0D_CLK_N

MIPI0D_CLK_P

COMMENTS:

RADAR:11100629

IN

IN

TABLE_ALT_HEAD

TABLE_ALT_ITEM

6

45

6

45

6

45

IN

6

45

IN

6

45

IN

6

45

IN

6

45

IN

6

45

IN

6

45

IN

6

45

IN

D

C

B

1

C2250

1

C2233

1

27PF

5%
25V

2

NP0-C0G
0201

100PF

5%
25V

2

NP0-CERM
0201

A

6 3

C2220

820PF

10%
25V

2

X7R-CERM
0201

SYNC_MASTER=N/A

PAGE TITLE

VIDEO: MIPI CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

22 OF 102

SHEET

16 OF 46

124578

SIZE

A

D

87

6 5

VGA FRONT CAMERA CONNECTOR

4 3

12

L2600

L2601

0201

240OHM-350MA

0201

XW2600

SM

12

21

1

C2603

27PF

5%
16V

2

NP0-C0G
01005

21

C2604

1UF

20%

6.3V
X5R
0201

1

C2601

1UF

20%

6.3V

2

X5R
0201

1

2

C2605

1000PF

10%

6.3V
X5R-CERM
01005

1

C2600

27PF

5%
16V

2

NP0-C0G
01005

1

2

PP2V8_CAM_FRONT_FILT

1

C2602

1000PF

10%

6.3V

2

X5R-CERM
01005

VOLTAGE=2.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

GND_AVDD_CAM_FRONT

VOLTAGE=0V
MIN_LINE_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=GND

PP1V8_CAM_FRONT_FILT

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

1

R2601

100K

1%
1/32W
MF
01005

2

17

17

17

ISP1_CAM_FRONT_SHUTDOWN

LOW = ENABLES CAMERA TO TURN ON
HIGH = DISABLES / TURNS OFF CAMERA

MIPI1C_CAM_FRONT_CLK_FILT_P

17 45

MIPI1C_CAM_FRONT_CLK_FILT_N

17 45

MIPI1C_CAM_FRONT_DATA_FILT_P<0>

17 45

MIPI1C_CAM_FRONT_DATA_FILT_N<0>

17 45

ISP1_CAM_FRONT_CLK_F_R

17 17 44

L2610

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

L2611

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

L2660

120-OHM-210MA

01005

32

4

32

4

21

ISP1_CAM_FRONT_CLK_F

MIPI1C_CAM_FRONT_CLK_P

MIPI1C_CAM_FRONT_CLK_N

MIPI1C_CAM_FRONT_DATA_P<0>

MIPI1C_CAM_FRONT_DATA_N<0>

6

45

OUT

6

45

OUT

6

45

OUT

6

45

OUT

D

=PP2V8_CAM_FRONT

39

=PP1V8_CAM_FRONT

39

240OHM-350MA

C

ISP1_CAM_FRONT_SHUTDOWN_F

17

L2602

=PP3V0_ALS

39

B

240-OHM-0.2A-0.8-OHM

ISP1_CAM_FRONT_SDA

6

44

BI

ISP1_CAM_FRONT_SCL

6

44

IN

4

18 44

BI

ISP1_CAM_FRONT_CLK

6

44

IN

I2C2_SDA

0201

21

U2600

1208

1

C2608

1000PF

10%

6.3V

2

X5R-CERM
01005

OUT1

OUT2

OUT3

OUT4

1

C2606

27PF

5%
16V

2

NP0-C0G
01005

1

C2607

1UF

20%

6.3V

2

X5R
0201

400MHZ-0.1A-27PF

IN1

IN2

IN3

IN4

PP3V0_ALS_FILT

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

ISP1_CAM_FRONT_SDA_F

ISP1_CAM_FRONT_SCL_F

ISP1_CAM_FRONT_CLK_F

I2C2_SDA_F

17 44

17 44

17 44

17 44

17

I2C2_SCL_F

17 44

GPIO_ALS_IRQ_L_F

17

PP3V0_ALS_FILT

17

MIPI1C_CAM_FRONT_DATA_FILT_P<0>

17 45

MIPI1C_CAM_FRONT_DATA_FILT_N<0>

17

45

MIPI1C_CAM_FRONT_CLK_FILT_P

17 45

MIPI1C_CAM_FRONT_CLK_FILT_N

17 45

GND

516S0869 PLUG FLEX

516S0876 RCPT MLB

CRITICAL

J2601

503548-1820

F-ST-SM

1920

12

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

22

21

ISP1_CAM_FRONT_CLK_F_R

ISP1_CAM_FRONT_SHUTDOWN_F

ISP1_CAM_FRONT_SDA_F
ISP1_CAM_FRONT_SCL_F

PP2V8_CAM_FRONT_FILT

GND_AVDD_CAM_FRONT

PP1V8_CAM_FRONT_FILT

I2C2_SDA_F

17 44

17

17

17 44

17

17

17

17

44

D

C

B

U2601

400MHZ-0.1A-27PF

I2C2_SCL

4

18 44

IN

GPIO_ALS_IRQ_L

4

OUT

ISP1_CAM_FRONT_SHUTDOWN

6

IN

NC_U2601_1

IN1

IN2

IN3

IN4

1208

GND

OUT1

OUT2

OUT3

OUT4

A

NC_U2601_5

ISP1_CAM_FRONT_SHUTDOWN_F

I2C2_SCL_F

GPIO_ALS_IRQ_L_F

17 44

17

17

6 3

SYNC_MASTER=N/A

PAGE TITLE

FF CAM & MIC CONNECTORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=N/A

051-9374

13.0.0

26 OF 102

17 OF 46

SIZE

A

D

87

6 5

4 3

12

GYRO

(WRITE: 0XD4 READ: 0XD5)

VOLTAGE=3.0V
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

D

240-OHM-0.2A-0.8-OHM

=PP3V0_SENSOR_ACCEL

39

=PP1V8_ACCEL

39

21

C

ACCELEROMETER

(WRITE: 0X3A READ: 0X3B)

L2700

0201

17 18 44

17 18 44

4

4

PP3V0_SENSOR_ACCEL_FILT

1

C2700

10UF

20%

6.3V
2

CERM-X5R

0402-2

I2C2_SDA

BI

I2C2_SCL

IN

C2702

0.1UF

6.3V

C2701

0.1UF

10%

X5R
201

6.3V

1

2

10%

X5R
201

12-BIT PART

1

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MAX_NECK_LENGTH=3MM

2

VOLTAGE=3.0V

1

VDD_IO

U2700

AP3DSHAD

7

SEL/SDO

6

SDA/SDI/SDO

4

SCL/SPC

LGA

INT1/DRDY

GND

5

121316

VDD

14

CRITICAL

2

NC

3

108

RESCS

15

RES

11
9

INT2

=PP3V0_SENSOR_GYRO

39

=PP1V8_GYRO

39

NC
NC

DATASHEET SAYS TO CONNECT

GPIO_ACCEL_IRQ1_L
GPIO_ACCEL_IRQ2_L

PIN 15 TO VDD

PIN 10 TO GND

OUT

OUT

4

4

240-OHM-0.2A-0.8-OHM

4

17 18 44

4

17 18 44

L2702

21

0201

I2C2_SCL

IN

I2C2_SDA

BI

MAX_NECK_LENGTH=3MM

PP3V0_SENSOR_GYRO_FILT

1

6.3V

C2721

0.1UF

20%

1

2

10%

6.3V

2

X5R
201

VDD_IO

C2723

10UF

CERM-X5R

0402-2

C2725

0.1UF

6.3V

10%

X5R
201

AP3GDL20BCTR

2

SCL/SPC

3

SDA/SDI/SDO

4

SDO/SA0

9

RES0

10

RES1

11

RES2

12

RES3

RES/GND

1

2

1

U2720

14

LGA

GND

RES/VDD
VDD

13

1516

DRDY/

INT2

INT1

CRITICAL

5

CS

6

8

DEN

7

R2724

10K

1/32W

01005

GYRO_CS

1

1%

MF

2

GPIO_GYRO_IRQ2
CAM_REAR_VSYNC

GPIO_GYRO_IRQ1

4

OUT

20

IN

4

OUT

GYRO_PUMP

D

C

1

C2726

0.01UF

10%
25V

2

X5R-CERM

0201

B

COMPASS

B

WRITE: 0X18 READ: 0X19

NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3MM

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

PP3V0_SENSOR_COMPASS_FILT

=PP1V8_COMPASS

39

1

C2711

0.1UF

20%

6.3V
2

X5R-CERM

AGND_COMPASS

18

I2C1_SCL

4

19 44

IN

I2C1_SDA

4

19 44

BI

CS* TIES TO VID FOR I2C MODE

A

01005

NC_U2710_SO

NC_U2710_DRDY

A3

A4

A2

A1

XW2700

SM

SCL/SK

SDA/SI

CSB*

DRDY

12

C4

VDD

VID

U2710

AK8963C

CSP

CRITICAL

VSS

C1

B1

D1

CAD0

D2

CAD1

TST1

RST*

RSVSO

TRG

C2

B3B4

C3

D4

NC_U2710_TST1

NC_U2710_RSV

NC_U2710_TRG

240-OHM-0.2A-0.8-OHM

1

C2710

1.0UF

20%
10V

2

X5R-CERM

0201-1

6 3

L2701

21

0201

AGND_COMPASS

=PP3V0_SENSOR_COMPASS

18

39

SIZE

A

D

SYNC_MASTER=N/A

PAGE TITLE

INERTIAL SENSORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

27 OF 102

SHEET

18 OF 46

124578

87

6 5

PROX SENSOR

4 3

12

D

=PP1V8_PROX

19 39

=PP3V0_SENSOR_PROX

39

240-OHM-0.2A-0.8-OHM

C

I2C1_SDA

4

18 44

BI

I2C1_SCL

4

18 44

IN

GPIO_PROX_IRQ_L

4

OUT

INT* IS OPEN DRAIN PU RAIL MATCH VDRIVE

INT IS 1.8V LEVEL.

PROX GPIO WILL NOT BE USED.

THEREFORE,PROX GPIO IS NOT

CONNECTED TO MLB INTERCONNECT.

L2800

21

0201

=PP1V8_PROX

19 39

P106_P107

C2802

0.01UF

P106_P107

C2800

2.2UF

P106_P107

1

10%
10V

2

X5R
201

10%

6.3V
X5R
402

R2800

2.0K

P106_P107

C2804

0.1UF

20%

6.3V

X5R-CERM

01005

PP3V0_SENSOR_PROX_FILT

P106_P107

1

C2801

0.1UF

20%

2

1%

1/32W

MF

01005

P106_P107

C2807

27PF

NP0-C0G

6.3V

X5R-CERM

01005

1

2

P106_P107

1

1%

25V

2

201

P106_P107

1

C2805

68PF

2

NP0-C0G

P106_P107

1

C2806

68PF

2

NP0-C0G

PROX_BIAS

PROX_GPIO PROX_CIN9

1

R2801

100K

1%

1/32W

MF

01005

2

VDRIVE FOR: I2C AND GPIO

1

5%

6.3V
2

01005

1

5%

6.3V
2

01005

VOLTAGE=3.0V

MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=PWR

1.8 MA MAX

E3

BIAS

E1

SDA

C1

SCLK

D1

ADD0

B1

ADD1

A1

INT*

A2

GPIO

B2

TP

NC

D2

VDRIVE

VCC

U2800

AD7149

WLCSP

353S2964

CRITICAL

P106_P107

VDRIVE RAIL

ACSHIELD

E4

I2C ADDRESS: 0101100+R/W

READ: 0X59, WRITE: 0X58

C2

D3

CIN0

NC

A3

CIN1

B3

CIN2

A4

CIN3

NC

C3

CIN4

NC

A5

CIN5

NC

B4

CIN6

NC

B5

CIN7

C4

CIN8

NC

C5

CIN9

D4

GND

CIN10

CIN11
CIN12

E2

NC

D5

NC

E5

NC

PROX_CIN1

TP_PROX_CIN2

PROX_CIN7

P106_P107

C2803

0.5PF

+/-0.05PF

CERM

1

25V

2

201

0.5 PF

JUST IN CASE

NEED EXTERNAL

REF CAP TO MEASURE

P106_P107
CRITICAL

390NH-2%-170MA-4.0OHM

390NH-2%-170MA-4.0OHM

L2802

21

0603

P106_P107

CRITICAL

L2804

0603

P106_P107
CRITICAL

68NH-2%-320MA-1.0OHM

CIN9

68NH-2%-320MA-1.0OHM

CIN7

L2801

21

0402

P106_P107

CRITICAL

L2803

2121

0402

CIN9 SENSOR ELECTRODE

CIN7 DUMMY

A PLANE UNDER PROX_CIN NETS

AND ALSO TIE TO CONNECTOR.

PROX_CIN9_CONN
PROX_CIN7_CONN
PROX_ACSHIELD_CONN

PCB: ACSHIELD NEEDS TO BE

P106_P107

516S0872

CRITICAL

J2800

503548-0620

F-ST-SM

7

34

56

9

8

21

NC_J2800_2
NC_J2800_4
NC_J2800_6

10

D

C

B

CRITICAL

P106_P107

L2807

2121

0402

ACSHIELD_SB

CRITICAL

P106_P107

390NH-2%-170MA-4.0OHM

L2808

0603

68NH-2%-320MA-1.0OHM

ACSH_SB

CHOSE CIN NUMBERS FOR LAYOUT EASE

B

PCB: ENSURE ACSHIELD PLANE UNDER

U3200, NO GND PLANE NEAR PROX_CIN NETS..

A

SYNC_MASTER=N/A

PAGE TITLE

PROX SENSOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

28 OF 102

SHEET

19 OF 46

124578

SIZE

A

D

8 7

6 5 4 3

REAR CAMERA CONNECTOR

12

D

=PP1V8_CAM_REAR

93 02

1

C2972

27PF

5%
16V

2

NP0-C0G
01005

=PP1V2_CAM_REAR

39

1

C2973

27PF

5%
16V

2

NP0-C0G
01005

=PP2V8_CAM_REAR

C

39

=PP2V8_CAM_REAR_AF

39

1

C2970

27PF

5%
16V

2

NP0-C0G
01005

1

C2971

27PF

5%
16V

2

NP0-C0G
01005

L2902

240OHM-350MA

0201

L2903

240OHM-350MA

0201

L2900

240OHM-350MA

0201

XW2950

SM

1 2

L2901

240OHM-350MA

0201

XW2951

SM

1 2

21

1

27PF

5%
16V

2

NP0-C0G
01005

21

1

C2909

27PF

5%
16V

2

NP0-C0G
01005

21

1

C2900

27PF

5%
16V

2

NP0-C0G
01005

21

1

C2903

27PF

5%
16V

2

NP0-C0G
01005

1

C2907C2906

1UF

10%
10V

2

X5R
402

1

1UF

10%
10V

2

X5R
402

1

C2901

1UF

10%
10V

2

X5R
402

1

C2904

1UF

10%
10V

2

X5R
402

1

C2908

1000PF

10%

6.3V

2

X5R-CERM
01005

1

C2911C2910

1000PF

10%

6.3V

2

X5R-CERM
01005

1

C2902

1000PF

10%

6.3V

2

X5R-CERM
01005

1

C2905

1000PF

10%

6.3V

2

X5R-CERM
01005

PP1V8_CAM_REAR_FILT

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V2_CAM_REAR_FILT

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP2V8_CAM_REAR_FILT

VOLTAGE=2.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=GND

MAX_NECK_LENGTH=5 MM

PP2V8_CAM_REAR_AF_FILT

VOLTAGE=2.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=GND

MAX_NECK_LENGTH=5 MM

18

IN

44

6

IN

6

44

BI

CAM_REAR_VSYNC

=PP1V8_CAM_REAR

93 02

ISP0_CAM_REAR_SCL
ISP0_CAM_REAR_SDA
ISP0_CAM_REAR_SHUTDOWN

6

GND_CAM_AVDD

GND_AF_AVDD

APN: 516S0973

PLUG: 516S0974

1

R2950

100K

1%
1/32W
MF
01005

2

CRITICAL

J2950

AA07-S022VA1

F-ST-SM

24

23

1

2

3

4

5

6

8

7

10

9

12

11

14

13

15

16

17

18

19

20

21

22

25

26

ISP0_CAM_REAR_CLK_FILT

45

MIPI0C_CAM_REAR_DATA_FILT_P<0>

MIPI0C_CAM_REAR_DATA_FILT_N<0>

45

MIPI0C_CAM_REAR_CLK_FILT_P

45

MIPI0C_CAM_REAR_CLK_FILT_N

45

MIPI0C_CAM_REAR_DATA_FILT_P<1>

45

MIPI0C_CAM_REAR_DATA_FILT_N<1>

45

L2950

120-OHM-210MA

01005

L2911

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

L2910

2

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

L2912

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

21

32

4

3

4

32

4

ISP0_CAM_REAR_CLK

MIPI0C_CAM_REAR_DATA_P<0>

MIPI0C_CAM_REAR_DATA_N<0>

MIPI0C_CAM_REAR_CLK_P

MIPI0C_CAM_REAR_CLK_N

MIPI0C_CAM_REAR_DATA_P<1>

MIPI0C_CAM_REAR_DATA_N<1>

6

44

IN

45

6

OUT

45

6

OUT

6

45

OUT

45

6

OUT

6

45

OUT

6

45

OUT

D

C

B

B

CRITICAL

L2960

BUTTON CONNECTOR

GPIO_BTN_VOL_DOWN_L

4

GPIO_BTN_VOL_UP_L

4

GPIO_BTN_SRL_L

4

42

A

GPIO_BTN_POWER_L

42

4

240-OHM-0.2A-0.8-OHM

240-OHM-0.2A-0.8-OHM

240-OHM-0.2A-0.8-OHM

240-OHM-0.2A-0.8-OHM

0201

L2961

0201

L2962

0201

L2963

0201

21

21

21

21

GPIO_BTN_VOL_DOWN_R_L

GPIO_BTN_VOL_UP_R_L

GPIO_BTN_SRL_R_L

GPIO_BTN_POWER_R_L

R2900

1.00K

1

2

1 2

C2960

82PF

5%
25V
CERM
0201

1%

1/32W

MF

01005

1

2

C2961

82PF

5%
25V
CERM
0201

R2901

1.00K

1 2

1%

1/32W

MF

01005

1

2

C2962

82PF

5%
25V
CERM
0201

R2902

1.00K

1 2

1%

1/32W

MF

01005

1

2

C2963

82PF

5%
25V
CERM
0201

R2903

1.00K

1 2

1%

1/32W

MF

01005

DZ2960

201-1

12.8V-100PF

2

12.8V-100PF

1

DZ2961

201-1

12.8V-100PF

2

1

DZ2962

201-1

2

1

DZ2963

201-1

12.8V-100PF

2

1

GPIO_BTN_VOL_DOWN_L_FILT
GPIO_BTN_VOL_UP_L_FILT
GPIO_BTN_SRL_L_FILT
GPIO_BTN_POWER_L_FILT

6 3

J2960

FF18-6A-R11AD-B-3H

F-RT-SM

1

2

3

4

5

6

518S0692

SYNC_MASTER=N/A

PAGE TITLE

BUTTON & REAR CAMERA CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

29 OF 102

SHEET

20 OF 46

124578

SIZE

A

D

87

6 5

4 3

AP INTERFACE & DEBUG CONNECTOR

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

12

PP_BATT_VCC_CONN

D

C

B

A

AP CONNECTIONS

PP_BATT_VCC_CONN

21 22 23 29 30 31 33 34

TX_GTR_THRESH

25

BB_RST_L

21 23 24

RESET_DET_L

21 25

RADIO_ON_L

21 23

RESET_PMU_L

21 23

BB_WAKE_HOST

21 25

RF_RESET_L

21

PBL_RUN_BB_HSIC1_RDY

21 25

AP_WAKE_MODEM

25

AP_HSIC1_RDY

21 25

50_HSIC_BB_DATA

21 24

50_HSIC_BB_STROBE

21 24

BB_HSIC1_REMOTE_WAKE

25

BB_UART_TXD

21

25

BB_UART_RXD

21 25

BB_UART_RTS_L

21 25

BB_UART_CTS_L

BB_USB_VBUS

21 24

90_BB_USB_D_P

21 24

90_BB_USB_D_N

21 24

PP_WLAN_MAIN_VCC

37

PP_SYNC

25

PP_WL_BT_VDDIO_AP

37

CLK32K_AP

37

WLAN_REG_ON

21 37

WLAN_UART_TXD

37

WLAN_UART_RXD

37

WLAN_HOST_WAKE

37

WLAN_HSIC3_RESUME

37

DEV_HSIC3_RDY

37

AP_HSIC3_RDY

37

50_HSIC_WLAN_DATA

37

50_HSIC_WLAN_STROBE

37

BT_HOST_WAKE

37

BT_WAKE

21 37

BT_UART_TXD

21 37

BT_UART_RXD

21 37

BT_UART_RTS_L

37

BT_UART_CTS_L

37

BT_REG_ON

21 37

BT_PCM_CLK

37

BT_PCM_SYNC

37

BT_PCM_OUT

37

BT_PCM_IN

37

ANT_PORTB_1

13 21 25

ANT_PORTB_2

13 21 25

ANT_PORTB_3

13

21 25

LAT_SW1_CTL

21 25

PP_LDO14_2P65

13 21 22 27 32 35

PARTS TABLE FOR P105 SIM CARD, WHILE PINOUT IS BEING FIXED

QTY

PART#

512S0088

DESCRIPTION

P105 SIM TRAY

1

=PPBATT_VCC_RF

GPIO_BB_GSM_TXBURST
GPIO_BB_RST_L
GPIO_BB_RST_DET_L
GPIO_BB_RADIO_ON_L
PMU_GPIO_BB_RST_L
PMU_GPIO_BB_WAKE
RST_SYSTEM_L
GPIO_BB_HSIC_DEV_RDY

GPIO_BB_IPC_GPIO
GPIO_BB_HSIC_HOST_RDY
HSIC1_BB_DATA
HSIC1_BB_STB

GPIO_BB_DIAGS_RDY
UART4_BB_RXD
UART4_BB_TXD
UART4_BB_CTS_L
UART4_BB_RTS_L

BB_VBUS_DET
USB_BB_D_P
USB_BB_D_N

=PPBATT_VCC_WL

GPIO_BB_GPS_SYNC

=PP1V8_S2R_WL

PMU_CLK_32K_WLAN

PMU_GPIO_WLAN_REG_ON

UART3_WLAN_RXD
UART3_WLAN_TXD
PMU_GPIO_WLAN_HOST_WAKE

GPIO_WLAN_HSIC_RESUME
GPIO_WLAN_HSIC_DEV_RDY
GPIO_WLAN_HSIC_HOST_RDY
HSIC2_WLAN_DATA
HSIC2_WLAN_STB

PMU_GPIO_BT_HOST_WAKE

GPIO_BT_WAKE
UART1_BT_RXD
UART1_BT_TXD
UART1_BT_CTS_L
UART1_BT_RTS_L
PMU_GPIO_BT_REG_ON
I2S3_BT_BCLK
I2S3_BT_LRCK
I2S3_BT_DIN
I2S3_BT_DOUT

ANT_PORTB_1
ANT_PORTB_2
ANT_PORTB_3
ANT_PORTA_1

PP_LDO14_2P65

REFERENCE DESIGNATOR(S)

J31001_RF

BOM OPTION

CELL

39

4

4

4

4

42

42

3

10 42

4

4

4

3

44

3

44

4

4

10 44

4

10 44

4

44

44 21 25

4

42

10 44

10 44

39

4

39

44

42

42

4

44

4

44

4

4

3

44

3

44

42

4

4

44

4

44

4

44

4

44

42

4

44

4

44

4

44

4

44

13 21 25

13 21 25

13 21 25

13

21 22 27 32 35

J31010_RF

DEBUG CONNECTOR

DEBUG_RST_L

24

OUT

RESET_PMU_L

21 23

OUT

RADIO_ON_L

21 23

OUT

BB_USB_VBUS

21 24

OUT

90_BB_USB_D_N

21 24

BI

90_BB_USB_D_P

21 24

BI

RF_RESET_L

21

OUT

PP31007_RF

P4MM

SM
PP

PP31001_RF

P4MM

SM
PP

PP31006_RF

P4MM

SM
PP

PP31005_RF

P4MM

SM
PP

PP31003_RF

P4MM

SM
PP

PP31004_RF

P4MM

SM

PP

PP31013_RF

P4MM

SM

PP

42

4

PP31014_RF

P4MM

SM

PP

PP31015_RF

P4MM

SM
PP

PP31016_RF

P4MM

SM
PP

PP31017_RF

P4MM

SM
PP

PP31018_RF

P4MM

SM
PP

BB_ERROR_FLAG

1

NOSTUFF

SLEEP_CLK_32K

1

NOSTUFF

PMIC_SSBI

1

NOSTUFF

RADIO_ON_L

1

NOSTUFF

PBL_RUN_BB_HSIC1_RDY

1

NOSTUFF

AP_HSIC1_RDY

1

NOSTUFF

BT UART

BT_UART_TXD

1

NOSTUFF

BT_UART_RXD

1

NOSTUFF

BB NOR SPI

1

SPI_DATA_MOSI

NOSTUFF

1

SPI_DATA_MISO

NOSTUFF

1

SPI_CS_L

NOSTUFF

1

SPI_CLK

NOSTUFF

25

23

23 24

21 23

21 25

21 25

21 37

21

25

25

25

25

J31002_RF

24

37

MM4829-2702

F-ST-SM

J31003_RF

MM4829-2702

F-ST-SM

GPIO_51

21 25

ANT_SEL_1

21 25 32

ANT_SEL_2

21 25 32

LAT_SW1_CTL

21 25

423

NOSTUFF

423

NOSTUFF

1

1

50_HSIC_BB_DATA

50_HSIC_BB_STROBE

PP_SMPS3_MSME_1V8

21 22 24 25 28

CELL

1

R31101_RF

10K

1%
1/32W
MF
01005

2

CELL

R31102_RF

1

10K

1%
1/32W
MF
01005

2

21 24

21 24

CELL

1

R31103_RF

10K

1%
1/32W
MF
01005

2

CELL

R31104_RF

1

10K

1%
1/32W
MF
01005

2

24 44

24 44

24 44

24 44

24 44

BB_JTAG_TCK

4

OUT

BB_JTAG_TMS

4

OUT

BB_JTAG_TDO

4

IN

BB_JTAG_TDI

4

OUT

BB_JTAG_TRST_L

4

OUT

BB_JTAG_RTCLK

24

OUT

PS_HOLD

23 25

OUT

BB_UART_TXD

21 25

IN

BB_UART_RXD

21 25

OUT

BB_UART_RTS_L

21 25

IN

BB_UART_CTS_L

21 25

OUT

GPIO_DEBUG_LED

25

IN

GPIO_51

21 25

OUT

ANT_SEL_1

21 25 32 21 25

OUT OUT

GPIO51/BOOT_CONFIG_3

GPIO53/BOOT_CONFIG_1 GPIO48/BOOT_CONFIG_6

AXE654124

M-ST-SM

56

10
12

14
16

18

20
22

24

26
28

30

32
34

36
38

40

42
44

46

48
50

52

54

55

2

1

4

3

6

5

8

7

9
11

13
15

17

19

HSIC_BB_DATA

21

HSIC_BB_STROBE

23

25

NC

27

29

31
33

35

NC

37

39

41
43

45

47
49

GPIO54/BOOT_CONFIG_0

51

53

58 57

NOSTUFF

BOOT OPTIONS

BOOT_DEFAULT_OPTION

BOOT_NAND_OPTION

BOOT_HSIC_OPTION

BOOT_USB_OPTION

ENABLE SAHARA PROTOCOL

BOOT_CONFIG
SW REGISTER

VALUE

0X00

0X01

0X02

0X03

0X08

47

X

X

X

X

X

SIM CARD CONNECTOR

PP_LDO6_RUIM_1V8

21 22 24

1

1

2

SIM_SWP

R31004_RF

15.00K
1%
1/32W
MF
01005

2

CELL

SIMCRD_IO_CONN

SIM_DETECT

21 25

21 25

SIMCRD_IO_CONN

21 25 21 25

SIMCRD_RST_CONN

21

25

R31005_RF

0.00

0%

1/32W

MF

5

DETECT

OMIT

01005

NOSTUFF

I/O

SWP

7

12

6

1

VCC

J31001_RF

SIM-CARD-N41

SIMCRD_RST_CONN

21

25

SIMCRD_CLK_CONN

21 25

TABLE_5_HEAD

TABLE_5_ITEM

2

RST

F-ST-SM

3

CLK

GND

8

9

101113

PP_LDO6_RUIM_1V8

1

DZ31002_RF

12V-33PF
01005

2

CELL

DZ31001_RF

TPD4E101DPW

SON4

5

GND

CELL

41

32

SIMCRD_CLK_CONN

21 22 24

SIM_DETECT

21 25

PAGE TITLE

SYSTEM & DEBUG CONNECTORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

23 29 30 31 33 34

21 22

IN

PP_SMPS3_MSME_1V8

BT_WAKE

PP_LDO6_RUIM_1V8

WLAN_REG_ON

PMIC_RESOUT_L

AP_HSIC1_RDY
BT_REG_ON
BB_WAKE_HOST

RESET_DET_L
SIMCRD_CLK_CONN

SIMCRD_IO_CONN
SIM_DETECT
BB_RST_L
SIMCRD_RST_CONN

PBL_RUN_BB_HSIC1_RDY
ANT_SEL_2
LAT_SW1_CTL

GPIO/BOOT_CONFIG CONFIGURATION

301456

2

52 55X5453

51

5004948

00

0

0

0

0

1000001X

1

1

1

R
C
XW
DZ
U

0

0

0

R104
CXXX

0

0

100

XW206
DZ101
U101

0

1X110000

X

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

21 22 24 25 28

IN

21 37

OUT

21 22 24

IN

21 37

OUT

23 24

IN

21 25

IN

21 37

IN

25

21

IN

21 25

IN

21

25

IN

21 25

BI

21 25

OUT

21 23

OUT

21 25

IN

21 25

IN

21 25 32

OUT

X

X

X

051-9374

13.0.0

31 OF 102

21 OF 46

D

24

C

B

A

SIZE

D

87

6 5

BASEBAND PMU (1 OF 2)

4 3

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

12

PP_LVS1

D

24

OUT

D

PP_VREG

1

C32031_RF

1.0UF

20%

6.3V

2

X5R

1

2

22 23

S1_GND

1

2

1

2

22 23

S3_GND

1

2

1

2

22 23

S5_GND

C32030_RF

10UF

CERM-X5R

0402-1

CELL

1

C32029_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

0201-MUR

CELL

C32007_RF

22UF

20%

6.3V
X5R-CERM-1
603

CELL

C32008_RF

22UF

20%

6.3V
X5R-CERM-1
603

CELL

C32009_RF

22UF

20%

6.3V
X5R-CERM-1
603

CELL

C32010_RF

22UF

20%

6.3V
X5R-CERM-1
603

CELL

C32011_RF

22UF

20%

6.3V
X5R-CERM-1
603

CELL

1

20%

6.3V
2

XW32007_RF

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

21

NOSTUFF

XW32009_RF

21

NOSTUFF

XW32011_RF

SHORT-10L-0.25MM-SM

NOSTUFF

24 28

OUT

23 24

OUT

24

OUT

36

OUT

21 24

OUT

24

OUT

13 21 27

OUT

24 25

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

1

C32040_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

PP_SMPS1_MSMC_1V05

PP_SMPS2_RF1_1V3

PP_SMPS3_MSME_1V8

1

C32033_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

PP_SMPS4_RF2_2V0

PP_SMPS5_DSP_1V05

21

32 35

PAGE TITLE

BASEBAND PMU (1 0F 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CREATE A PLANE

24

OUT

24 28

OUT

CREATE A PLANE

21 22 24

OUT

22 28

OUT

22

OUT

25 28

R

R207
C237

L211

L
UCU201

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

32 OF 102

SHEET

22 OF 46

124578

SIZE

C

B

A

D

L32007_RF

2.2UH-20%-1.2A-0.15OHM

PP_VSW_S1

2.2UH-20%-1.2A-0.15OHM

PP_VSW_S2

L32008_RF

0806

CELL

0806

CELL

21

21

C

L32009_RF

2.2UH-20%-1.2A-0.15OHM

S1_GND

C32003_RF

4.7UF

20%
10V
X5R-CERM
0402

CELL

23

22

1

C32004_RF

4.7UF

20%
10V

2

X5R-CERM
0402

CELL

REF_BYP_8014_F2

1

C32006_RF

0.1UF

20%
4V

2

X5R
01005

CELL

28

REF_BYP

34

REF_GND

104

VDD_S1

95

VDD_S2

6

18

VDD_S3

24

98

VDD_S4

89

VDD_S5

101

8

VDD_XO

44

VDD_L2_L3

78

VDD_L4

5

VDD_L5_L6_L13_L14

75

VDD_L7

58

VDD_L8

70

VDD_L9

59

VDD_L10_L11

64

VDD_L12

U32001_RF

PM8018

BGA

VREG

(SYM 5 OF 5)

VOUT_LVS1

VREG_RFCLK

VSW_S1

VREG_S1

VSW_S2

VREG_S2

VSW_S3

VSW_S5_2

VREG_S3

VSW_S4

VREG_S4

VSW_S5

VREG_S5

VREG_XO

VREG_L2

VREG_L3
VREG_L4

VREG_L5

VREG_L6
VREG_L13

VREG_L14

VREG_L7

VREG_L8

VREG_L9
VREG_L10

VREG_L11

VREG_L12

CELL

53

13

92

97

79
90

102
83

42

48
100

12

81
87

105

82
88

76

20
31

32

84
11

17

23
29

63
54

77

65
55

43

PP_LDO1

1

C32034_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C32012_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C32013_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C32014_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C32015_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C32016_RF

1.0UF

20%

6.3V

2

X5R

0201-MUR

CELL

1

C32017_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C32018_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

23

S2_GND

20%
10V
X5R-CERM
0402

1

2

PP_SMPS4_RF2_2V0

PP_SMPS3_MSME_1V8

PP_SMPS5_DSP_1V05

22 28

21 22 24 25 28

22

22 23

S3_GND

1

2

IN

IN

IN

C32002_RF

4.7UF

CELL

22 23

S5_GND

1

C32026_RF

4.7UF

20%
10V

2

X5R-CERM
0402

CELL

34
31
29

PP_BATT_VCC_CONN

21

IN

23
30

B

33

1

C32035_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

1

2

1

C32036_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

C32037_RF

10UF

20%

6.3V
CERM-X5R
0402-1

CELL

1

C32023_RF

0.1UF

20%

6.3V

2

X5R-CERM
01005

NOSTUFF

23

S4_GND

1

2

C32001_RF

4.7UF

20%
10V
X5R-CERM
0402

CELL

A

PP_VSW_S3

PP_VSW_S4

1

C32019_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

L32010_RF

2.2UH-20%-1.2A-0.15OHM

2.2UH-20%-2.3A-0.115OHM

PP_VSW_S5

1

C32020_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

1

C32021_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

21

0806

CELL

21

0806

CELL

L32011_RF

TFA252010-SM

21

CELL

PP_LDO2_XO_HS_1V8
PP_LDO3_AMUX_1V8
PP_LDO4_VDDA_3V3
PP_LDO5_GPS_LNA_2V5
PP_LDO6_RUIM_1V8
PP_LDO13_VDDPX_2V95
PP_LDO14_2P65
PP_LDO7_DAC_1V8
PP_LDO8_VDDPX_1V2
PP_LDO9_PLL_1V05
PP_LDO10_ADSP_1V05
PP_LDO11_MDSP_FW_1V05
PP_LDO12_MDSP_SW_1V05

1

C32022_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

CELL

6 3

87

6 5

BASEBAND PMU (2 OF 2)

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

REVISIONBOARD_ID

D

0.25V

0.50V

0.70V

0.90V

1.10V

1.30V

R33019_RF

0.00

BB_RST_L

21 24

IN

PS_HOLD

21 25

IN

C

B

12

0%

1/32W

MF

01005

CELL

R33018_RF

20.0K

12

5%

CELL

1/32W

MF

01005

RADIO_ON_L

21 21 24

IN

RESET_PMU_L

21

IN

PP_BATT_VCC_CONN

21 22 29 30 31 33 34

PMIC_SSBI

21 24

BI

PS_HOLD_PMIC

R33017_RF

0.00

12

0%

1/32W

MF

01005

NOSTUFF

57

VCOIN

NC

NC

OPT_2

U32001_RF

PM8018

BGA

INPUT PWR

(SYM 3 OF 5)

47

PS_HOLD

69

KPD_PWR*

16

PM_RESIN_N

62

OPT_1

74

OPT_2

68

SSBI

GND_S1

GND_S3

GND_S4

U32001_RF

PM8018

BGA

CONTROL

(SYM 1 OF 5)

91
103

96

GND_S2

30
36

93

99
94

GND_S5

39
51

61 NEEDS TO BE MADE 45

61
56

GND

46

52
40

CELL

LED_DRV_N

PON_RESET*

PM_USR_INT_N
PM_MDM_INT_N

PON_TRIG

BAT_ID

S1_GND

22

S2_GND

S3_GND

22

S4_GND

S5_GND

86

4

PMIC_RESOUT_L

21

PM_USR_IRQ_L

14

PM_MDM_IRQ_L

41

35

CELL

XW33008_RF

SHORT-10L-0.25MM-SM

XW33010_RF

SHORT-10L-0.25MM-SM

22

NC

22

21

NOSTUFF

21

NOSTUFF

OUT

25

OUT

25

OUT

ALTERNATES

A

PART NUMBER

197S0437 CELL

ALTERNATE FOR
PART NUMBER

197S0410

BOM OPTION

CELL197S0410197S0409

6 3

N41 PROTO 1
N41 PROTO 2, X122 RF DEV 1
N41 PROTO 3, X122 PROTO 0
N41 EVT 1, X122 PROTO 1
N41 EVT 2, X122 EVT
N41 EVT 3, X122 DVT

PP_LDO3_AMUX_1V8

22 23 24

IN

REF DES

Y33001_RF

Y33001_RF

COMMENTS:

KYOCERA CRYSTAL

RAKON CRYSTAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

NDK - 197S0410
KYOCERA - 197S0437
RAKON - 197S0409

Y33001_RF

2.5X2.0MM-SM1

19.2MHZ-90PPM-10PF

13

CELL

1%

MF

CELL

42

XO_GND

23

XO_THERM_Y1

R33007_RF

100K

12

1/32W

01005

BOM OPTIONS

PART#

118S0685

118S0656

118S0729

118S0685

4 3

PA_ID

24

XTAL19M_IN

XTAL19M_OUT

GND1 PIN NO NEEDS TO BE 61

1

C33006_RF

1000PF

10%

6.3V

2

X5R-CERM
01005

CELL

23

XO_GND

DESCRIPTION

QTY

1

PA_ID RES DIVIDER 102K

1 Y

PA_ID RES DIVIDER 61.9K

PA_ID RES DIVIDER 39K

1

1 Y

PA_ID RES DIVIDER 102K

PP_LDO3_AMUX_1V8

22 23

IN

1

R33003_RF

143K

1%
1/32W
MF
01005

2

CELL

1

R33001_RF

392K

1%
1/32W
MF
01005

2

CELL

VREF_DAC_BIAS

25

IN

42 45

42 45

R33008_RF

100K

12

1%

1/32W

MF

01005

NOSTUFF

NC

XW33003_RF

SHORT-10L-0.1MM-SM

21

BOARD_ID

IN

IN

XO_GND

1

XTAL_19M_IN

2

XTAL_19M_OUT

3

XTAL_32K_IN

15

XTAL_32K_OUT

45

GND1

27

GND0

10

XO_THERM

22

XOADC_GND

24

OUT

BOARD_TEMP4_P

BOARD_TEMP4_N

23

U32001_RF

PM8018

CLOCKS

(SYM 2 OF 5)

REFERENCE DESIGNATOR(S)

VDDPX_BIAS

BGA

XO_OUT_D0_EN

R33004_RF

R33004_RF

R33002_RF

R33002_RF

1

R33004_RF

102K

1%
1/32W
MF
01005

2

PA_ID

OMIT

1

R33002_RF

15.8K

1%
1/32W
MF
01005

2

OMIT

1

RT33001_RF

10KOHM-1%-0.31MA

0201

2

CELL

XO_OUT_A0

XO_OUT_D0

XO_OUT_A1

SLEEP_CLK

RSVD

PLACE CLOSE TO PA

CELL

1

1

19
25

37

NC

9

26

7

RSVD

CRITICAL BOM OPTION

Y

Y

0.25V

0.50V

1.10V

85

MPP_01

67

MPP_02

66

MPP_03

72

MPP_04

73

MPP_05

NC

80

MPP_06

PP33001_RF

PP

SM

P4MM

PP33002_RF

PP

SM

P4MM

A0_PMCLK

MDM_CLK

D0_EN

SLEEP_CLK_32K

1

XW33004_RF

SHORT-10L-0.1MM-SM

NOSTUFF

2

B4_17

B3_13

B4_17

B3_13

PA CONFIG
B4/17 CONFIG 0
B4_17 CONFIG 1
B3/13 CONFIG 0

U32001_RF

PM8018

BGA

MPP MISC

(SYM 4 OF 5)

R33010_RF

24

OUT

24

IN

21 24

OUT

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

33

GPIO_01

GPIO_02
GPIO_03

GPIO_04

GPIO_05
GPIO_06

12

CELL

100

1%

1/32W

MF

01005

CELL

PAGE TITLE

NC

38

NC

50

NC

60

NC

71

NC

49

NC

RF_CLK

1

C33008_RF

8.2PF

+/-0.1PF%
16V

2

NP0-C0G
01005

CELL

26

OUT

BASEBAND PMU (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R
C
L
U

XW

12

R317
C309

LXXX
U301

XW305

DRAWING NUMBER

051-9374

REVISION

BRANCH

PAGE

33 OF 102

SHEET

23 OF 46

124578

13.0.0

SIZE

D

C

B

A

D

87

6 5

BASEBAND (1 OF 2)

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

D

C

B

A

PP_SMPS1_MSMC_1V05

22 24

IN

PP_LDO9_PLL_1V05

22 24

IN

PP_SMPS3_MSME_1V8

21 22 24 25 28 21 22 24 25 28 22 24

IN IN IN

1

2

PP_SMPS1_MSMC_1V05

22 24 21

IN IN

PP_SMPS1_MSMC_1V05

22 24

IN

1

C34022_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

PP_LDO9_PLL_1V05

22 24

IN

PP_SMPS3_MSME_1V8

21 22 24 25 28

IN

PP_LDO13_VDDPX_2V95

22

IN

C34015_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

1

C34001_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C34006_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C34016_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C34002_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C34007_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

F8
F9

F12
F13

F14

G9

G12

H9

H12

J8

J9

J12 T15
J13

K8
K9

K12

K13

L8

L9

L12
L13

M8

M9
M12

M13

N8

N9

N12
N13

P9

P12

R9

R12

T8

T9

C17

C18

E17
F17

G7

G13

G14

H7

H8

H13
H14

P7

P8
P13

P14

R7

R8

R13

R14

A14
A19

F21

M1
M21

K21

VDD_P2

1

2

1

C34008_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

PP_SMPS3_MSME_1V8

1

C34017_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

U34001_RF

MDM9615M

(5 OF 6)

VDD_CORE

VDD_MEM

VDD_P1

C34003_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

1

C34009_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

2

BGA

PWR

VDD_DDR

VDD_ADSP

VDD_MDSP_FW

VDD_MDSP_SW

VDD_QFUSE_PRG

VDD_USB_1P8
VDD_USB_3P3

VDD_HVPAD_BIAS

VDD_PLL1

VDD_PLL2

VDD_A2

VDD_A1

VDD_P3

1

C34004_RF

2

CELL

C34018_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

GND

GND

VDD_P4
VDD_P5

VDD_P6
VDD_P7

CELL

1.0UF

20%

6.3V
X5R
0201-MUR

AA20
B19

F20
M20

C5
C6

E6

E7
F5

T16

T17
U14

U15

U16
U17

U19

T19

N15

N16
N17

N19
P15

P16

P17
P19

B13

E12

E10

E16

K17

L17
W12

U6G8
U7

AA11

AA18

W9
AA7

AA15

A15

G1

G21
L1

U1

W19

A2
A3

A7

A11

1

C34005_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

PP_LDO10_ADSP_1V05

PP_LDO12_MDSP_SW_1V05

PP_SMPS3_MSME_1V8

PP_LDO10_ADSP_1V05

PP_LDO11_MDSP_FW_1V05

PP_LDO12_MDSP_SW_1V05

PP_LDO4_VDDA_3V3

PP_LDO9_PLL_1V05

PP_LDO3_AMUX_1V8

PP_LDO7_DAC_1V8

PP_SMPS3_MSME_1V8

1

2

PP_LDO6_RUIM_1V8
PP_SMPS3_MSME_1V8
PP_LDO8_VDDPX_1V2

PP_SMPS3_MSME_1V8

1

C34011_RF

1.0UF

20%

6.3V

2

X5R

0201-MUR

CELL

1

C34019_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

VDDPX_BIAS

C34024_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

IN

IN

IN

IN

1

2

1

2

IN

IN

IN

22

22 24

23

22

22 25

21 22

IN

21 22

IN

21 22 24 25 28

IN

22

IN

21 22 24 25

IN

C34012_RF

CELL

C34020_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

PP_LDO11_MDSP_FW_1V05

22 24 22 24

ININ

1.0UF

20%

6.3V
X5R
0201-MUR

1

2

22 24 25

28

22 24

22 24

22 24

PP_LVS1

MF

5%

1/32W

01005

470K

12

R34005_RF

CELL

PP_LDO2_XO_HS_1V8

23

IN

1

C34021_RF

0.1UF

20%
4V

2

X5R
01005

NOSTUFF

PP_SMPS2_RF1_1V3

1

C34023_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

24 25 28

28

C34027_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

IN

1

C34025_RF

1.0UF

2

CELL

1

2

22

20%

6.3V
X5R
0201-MUR

1

C34026_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

C34013_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

IN

22 28

IN

22 28

1

C34014_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

1

C34028_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

21 44

21 44

21 44

21 44

23

23

21 23

21

21

21 23

IN

21 23

IN

21

IN

21 23

IN

4

IN

4

IN

4

IN

4

IN

IN

OUT

BI

BI

BI

24

24

MDM_CLK

D0_EN
PMIC_SSBI

90_BB_USB_D_P
90_BB_USB_D_N

200

12

R34001_RF

6 3

BB_RST_L

PMIC_RESOUT_L

DEBUG_RST_L

SLEEP_CLK_32K

BB_JTAG_TDI
BB_JTAG_TMS

BB_JTAG_TRST_L

BB_MODE_0

BB_MODE_1

RREFEXT

21

IN

1%

MF

1/32W

01005

CELL

R34004_RF

0.00

12

1/32W

0%

01005

MF

NOSTUFF

BB_USB_VBUS

ID IS NC

4 3

U34001_RF

MDM9615M

BGA

(6 OF 6)

GND

U34001_RF

MDM9615M

BGA

(1 OF 6)

DIGITAL

SDC1_DATA0

SDC1_DATA1

SDC1_DATA2
SDC1_DATA3

GND

GND_ANA

RESOUT*

RTCK

HSIC_CAL

HSIC_DATA

HSIC_STB

SDC1_CMD

SDC1_CLK

CELL

TDOTCK

DNC
DNC

DNC

DNC

DNC

DNC

DNC
DNC

CELL

M14

M15

M16
M17

M19

N6
N7

N10
N11

N14

P6
P10

P11

R6
R10

R11

R15
R16

R17
R19

T10

T12
T13

T14

U2
V19

F11
J16

K16
L16

T6

T7
T11

U9

U12
W7

W14

Y7
Y11

Y15
Y18L2

U13

W13

U20

NC

AA3Y3

Y2

A8

C7

50_HSIC_BB_DATA

B8

50_HSIC_BB_STROBE

E8

NC

C8

NC

B9

NC

A9

NC

E9

NC

C9

NC

B10

NC

A10

NC

K19

NC

L21

NC

L19

NC

L20

NC

N20

NC

N21

NC

BB_JTAG_TDOBB_JTAG_TCK

BB_JTAG_RTCLK

50_HSIC_CAL

24

24

4

OUT

21

OUT

21

BI

21

BI

BB_MODE_0

BB_MODE_1

21 44

NC NC

NC
NC

NC

NC
NC

R34002_RF

240

12

1/32W

01005

CELL

PP_SMPS3_MSME_1V8

MF

1%

10K

01005

1/32W

NOSTUFF

12

R34006_RF

AA21

AA19

A21

AA1

B11
B14

B15
C19

F10

F15

F16
F19

G10

G11
G15

G16

G17
G20

H10
H11

H15

H16

J10

J11

J14
J15

K10

K11

K14
K15

K20

L10

L11

L14
L15

M10

M11

Y20

AA2

AA4

W20

Y19

V20

U21
Y21

C11
E11

A12

C12
B12

C10

B2

B7

F6

F7

G2

G6

H6

J6

J7

K6

K7

L6

L7

M6

M7

Y4

W4

GND

RESIN*

SRST*

SLEEP_CLK

TDI

TMS

TRST*

MODE_0

MODE_1

CXO

CXO_EN
SSBI_PMIC

USB_HS_DP

USB_HS_DM

USB_HS_REXT
USB_HS_ID

USB_HS_SYSCLK

USB_HS_VBUS

D21

EBI2_NAND_CS*

E19

EBI2_OE*
EBI2_WE*

D19

EBI2_BUSY*

C20

EBI2_CLE*

E20

EBI2_ALE*

1%

MF

U34001_RF

MDM9615M

BGA

(2 OF 6)

1%

MF

10K

1/32W

01005

12

R34007_RF

PAGE TITLE

EBI1_EBI2

21

22 24 25

NOSTUFF

EBI1_CAL

EBI2_AD_0

EBI2_AD_1
EBI2_AD_2

EBI2_AD_3

EBI2_AD_4
EBI2_AD_5

EBI2_AD_6
EBI2_AD_7

28

CELL

BASEBAND (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C21

J20

J19

G19D20
H20

J21
H19

H21

E21

EBI1_CAL

NC
NC

NC

NC
NC

NC
NC

R
C
L
U

R34008_RF

240

12

1%

1/32W

MF

01005

CELL

R502
C528

LXXX
U501

12

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

34 OF 102

SHEET

24 OF 46

124578

SIZE

D

C

B

A

D

87

6 5

BASEBAND (2 OF 2)

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

4 3

12

SIZE

D

C

B

A

D

D

U34001_RF

MDM9615M

BGA

(4 OF 6)

ANALOG

DAC0_VREF

26

IN

26

IN

26

IN

26

IN

26

IN

26

IN

26

IN

26

IN

PRX_BB_I_P
PRX_BB_I_N

PRX_BB_Q_P

PRX_BB_Q_N

DRX_BB_I_P

DRX_BB_I_N
DRX_BB_Q_P

DRX_BB_Q_N

C

26

IN

26

IN

26

IN

26

IN

GPS_BB_I_P
GPS_BB_I_N

GPS_BB_Q_P

GPS_BB_Q_N

U8

BBRX_IP_CH0

W8

BBRX_IM_CH0

Y8

BBRX_QP_CH0

AA8

BBRX_QM_CH0

Y10

BBRX_IP_CH1

AA10

BBRX_IM_CH1

Y9

BBRX_QP_CH1

AA9

BBRX_QM_CH1

W17

DNC

NC

W18

DNC

NC

W15

DNC DNC

NC

W16

DNC

NC

W10

GNSS_BB_IP

U10

GNSS_BB_IM

W11

GNSS_BB_QP

U11

GNSS_BB_QM

TX_DAC0_IP

TX_DAC0_IM
TX_DAC0_QP

TX_DAC0_QM

TX_DAC0_IREF

DNC

DNC

DNC

DNC

W5

Y13

AA13

Y6

AA6
Y5

AA5

W6

Y14

AA14

H17
J17

V21

W21

Y12
Y16

Y17

AA12
AA16

AA17

NC

NC

NC
NC

NC

NC

NC

NC
NC

NC

NC
NC

NC

NC

CELL

B

PP_SMPS3_MSME_1V8

21 22 24 25 28

IN

1

C35001_RF

0.1UF

20%
4V

2

X5R
01005

CELL

VCC

U35001_RF

SERIAL-SPI-2MX8-1.8V

D3

WP*/SIO2

21 25

21 25

SPI_DATA_MOSI

IN

SPI_CLK

IN

E2

D2

C2

SI/SIO0

SCLK

NC/SIO3

A

ALTERNATES

PART NUMBER

ALTERNATE FOR
PART NUMBER

335S0874335S0895

335S0874335S0899

BOM OPTION

CELL

CELL

REF DES

U35001_RF

U35001_RF

COMMENTS:

WINBOND SPI NOR

MICRON SPI NOR

WLCSP

MX25U1635EBAI-10G

CELL

GND

E3 B2

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

SO/SIO1

VREF_DAC_BIAS

1

C35008_RF

0.1UF

10%

6.3V

2

X7R
0201

CELL

1

C35009_RF

0.1UF

20%
4V

2

X5R
01005

PP_LDO7_DAC_1V8

B3

CS*

C3

A4

F1

NC

F4

23

OUT

PP_SMPS3_MSME_1V8

21 22 24 25 28

1

R35001_RF

1.00M

1%
1/32W

IN

OUT

OUT

BI

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

25

MF
01005

2

CELL

SIM_DETECT

SIMCRD_RST_CONN

SIMCRD_CLK_CONN
SIMCRD_IO_CONN

SPI_CLK

SPI_CS_L

SPI_DATA_MISO
SPI_DATA_MOSI

BB_UART_RTS_L

BB_UART_CTS_L
BB_UART_RXD

BB_UART_TXD
BB_ERROR_FLAG

GPIO_DEBUG_LED

AP_WAKE_MODEM

RESET_DET_L

GSM_PA_LB_EN

GSM_PA_HB_EN

B1B4_SELECT

PA_ON_B1B4
PA_ON_B2

PA_ON_B5
PA_ON_B13

PA_ON_B8

WAN_DIO_RX_ON

WAN_DIO

PA_R0

BB_PDM

B6

A6

A5
B5

A16
A13

E14
E13

C14

C13
E15

A18

C15
B16

B18

C16

NC

A17

NC

B21

NC

B20

NC

A20

NC

B17

NC

P21

NC

R21

NC

P20

NC

R20

NC

T20

NC

T21

BB_PDM_FILT

1

C35006_RF

2

C4

B4

A4

U5

V2
V1

U3

T3
T1

T5

R5
R3

T2

R2
P5

P1

0.01UF

10%

6.3V
X5R
01005

CELL

SPI2 CLK
SPI2 CS_L

SPI2 MOSI

SPI2 MISO

SPARE PA ON

SPARE PA ON

R35004_RF

1.00K

12 12

1%

1/32W

MF

01005

CELL

TX_BB_I_P

TX_BB_I_N
TX_BB_Q_P

TX_BB_Q_N

NOSTUFF

SPI_CS_L

SPI_DATA_MISO

NC

NC

NC

IREF

26

BI

26

OUT

26

OUT

26

OUT

26

OUT

24

22

IN

21 25

IN

21

25

OUT

PP_SMPS3_MSME_1V8

21 22 24 25 28

IN

1%

MF

10K

1/32W

12

CELL

WDOG_DISABLE

25

R35002_RF

01005

21

21

21

21

21 25

21 25

21 25

21 25

21

21

21

21

21

21

21

21

31

31

33

33

34

29

30

29

26

26

29 30 31 33 34

6 3

U34001_RF

MDM9615M

GPIO_0

GPIO_1
GPIO_2

GPIO_3

GPIO_4
GPIO_5

GPIO_6

GPIO_7
GPIO_8

GPIO_9

GPIO_10
GPIO_11

GPIO_12
GPIO_13

GPIO_14

GPIO_15
GPIO_16

GPIO_17

GPIO_18
GPIO_19

GPIO_20

GPIO_21
GPIO_22

GPIO_23
GPIO_24

GPIO_25

GPIO_26
GPIO_27

GPIO_28

GPIO_29
GPIO_30

GPIO_31

GPIO_32
GPIO_33

GPIO_34
GPIO_35

GPIO_36

GPIO_37
GPIO_38

GPIO_39

GPIO_40
GPIO_41

GPIO_42

GPIO_43

CELL

R35005_RF

1.00K

1%

1/32W

MF

01005

BGA

(3 OF 6)

GPIO

GPIO_44

GPIO_45
GPIO_46

GPIO_47

GPIO_48
GPIO_49

GPIO_50

GPIO_51
GPIO_52

GPIO_53

GPIO_54
GPIO_55

GPIO_56
GPIO_57

GPIO_58

GPIO_59
GPIO_60

GPIO_61

GPIO_62
GPIO_63

GPIO_64

GPIO_65
GPIO_66

GPIO_67
GPIO_68

GPIO_69

GPIO_70
GPIO_71

GPIO_72

GPIO_73
GPIO_74

GPIO_75

GPIO_76
GPIO_77

GPIO_78
GPIO_79

GPIO_80

GPIO_81
GPIO_82

GPIO_83

GPIO_84
GPIO_85

GPIO_86

GPIO_87

CELL

DCDC_ADJ

1

C35007_RF

4700PF

10%

6.3V

2

X5R
01005

CELL

P3

PA_R1

R1

ANT_PORTB_1

N5

SPARE ANT_SEL_4

N3

WDOG_DISABLE

P2

LAT_SW1_CTL

M2B3

TX_GTR_THRESH

N1

ANT_PORTB_2

N2

GPIO_51
ANT_SEL_0

M3
L3

ANT_SEL_1

M5

ANT_SEL_2

L5

ANT_SEL_3

K1

DRX_MODE_SEL_A

K5

DRX_MODE_SEL_B

K3

DRX_MODE_SEL_C

K2

ANT_PORTB_3

J2

DCDC_EN

J5

DCDC_MODE

J1

SPARE GRFC[34]

J3

PRX_B5_B8_1

H3

BB_PDM
H5
G5

DO NOT ASSIGN ANY SIGNALS TO GPIO[65..67]

H1

H2

BB_HSIC1_REMOTE_WAKE
F3

SPARE

F1

RTR_SSBI_PRX_DRX
G3

RTR_SSBI_TX_GPS
V3

NC

W3

WAN_GPRSYNC
W2

WAN_GP_DATA0
W1

WAN_GP_DATA1
Y1

WAN_GP_DATA2
F2

WLAN_TX_BLANK
E2

NC

E3

PBL_RUN_BB_HSIC1_RDY
D1

AP_HSIC1_RDY
E1

PM_MDM_IRQ_L
D2

SPARE SSBI

D3

PS_HOLD
C1

NC

B1

PP_SYNC
C2

BB_WAKE_HOST
C3

PM_USR_IRQ_L

31

OUT

SPARE PA ON

BOOT_CONFIG_6
BOOT_CONFIG_5

BOOT_CONFIG_4
BOOT_CONFIG_3

BOOT_CONFIG_2

BOOT_CONFIG_1
BOOT_CONFIG_0

LAT_SW2_CTL

PAGE TITLE

MOBILE DATA MODEM (2 OF 2)

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

30 33

29

OUT

13 21

OUT

25

21

OUT

21

OUT

13 21

OUT

21

IN

32

OUT

21

32

OUT

21 32

OUT

32

OUT

35

OUT

35

OUT

35

OUT

13

21

OUT

31

OUT

31

OUT

27

OUT

25

OUT

21

OUT

26

BI

26

BI

26

OUT

26

OUT

26

OUT

26

OUT

37

IN

21

"BB_DIAGS_READY"

OUT

21

IN

23

OUT

21 23

OUT

21

OUT

21

OUT

23

OUT

Apple Inc.

R

R
C

L

R608

C609
L601

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9374

13.0.0

35 OF 102

25 OF 46

87

6 5

4 3

RF TRANSCEIVER (1 OF 3)

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

C36005_RF

220PF

12

10%

RF_CLK

IN

IREF

IN

50_CPL_PDET

IN

10V

X7R-CERM

01005

NOSTUFF

CELL

C36001_RF

100PF

12

5%

16V

NP0-C0G

01005

R36004_RF

49.9

12

1%

1/32W

MF

01005

1

R36003_RF

130

1%
1/32W
MF
01005

2

CELL

31

33

34

33

29

30

29

31

25

25

25

25

27

27

30

30

33

33

34

34

33

33

25

25

25

25

35

35

35

35

32

32

35

35

35

35

XO_REF

C36004_RF

50_PDET_PAD

CELL

1

R36005_RF
130

1%
1/32W
MF
01005

2 21

CELL

50_XCVR_2G_PA_HB_TX

OUT

50_XCVR_3G_B4_TX

OUT

50_XCVR_3G_B2_TX

OUT

50_XCVR_3G_B1_TX

OUT

50_XCVR_3G_B5_TX

OUT

50_XCVR_3G_B13_TX

OUT

50_XCVR_3G_B8_TX

OUT

50_XCVR_2G_PA_LB_TX

OUT

PRX_BB_Q_P

OUT

PRX_BB_Q_N

OUT

PRX_BB_I_P

OUT

PRX_BB_I_N

OUT

100_BAND5_BAND8_RX_N

IN

100_BAND5_BAND8_RX_P

IN

100_BAND13_RX_P

IN

100_BAND13_RX_N

IN

100_BAND4_RX_P

IN

100_BAND4_RX_N

IN

100_BAND2_RX_P

IN

100_BAND2_RX_N

IN

100_BAND1_RX_P

IN

100_BAND1_RX_N

IN

DRX_BB_Q_P

OUT

DRX_BB_Q_N

OUT

DRX_BB_I_P

OUT

DRX_BB_I_N

OUT

100_DRX_BAND13_BAND17_P

IN

100_DRX_BAND13_BAND17_N

IN

100_DRX_BAND5_BAND8_P

IN

100_DRX_BAND5_BAND8_N

IN

100_XCVR_DCS1800_RX_P

IN

100_XCVR_DCS1800_RX_N

IN

100_DRX_BAND2_RX_P

IN

100_DRX_BAND2_RX_N

IN

100_DRX_BAND1_BAND4_P

IN

100_DRX_BAND1_BAND4_N

IN

D

23

25

34

7DB ATTENUATOR

C

B

27PF

12

5%

16V

NP0-C0G

01005

C36003_RF

15PF

5%

2

1

16V

01005

NP0-C0G-CERM

NOSTUFF

CELL

RF_RBIAS

1

R36001_RF

4.7K

1%
1/32W
MF
01005

2

CELL

50_PDET_IN

TRANSCEIVER RF AND IQ PORTS

U36001_RF

TRANSCEIVER

C14

RBIAS

N5

XO_REF

P1

DAC_REF

U10

PDET_IN

M14

NC

RSVD

T14

TX_MB1

R14

TX_MB2

P14

TX_MB3

N14

TX_MB4

U13

TX_LB1

V12

TX_LB2

V13

TX_LB3

U14

TX_LB4

F1

PRX_BB_QP

E1

PRX_BB_QM

G2

PRX_BB_IP

F2

PRX_BB_IM

A7

PRX_LB1_INP

A8

PRX_LB1_INM

B9

PRX_LB2_INP

B8

PRS_LB2_INM

A11

PRX_MB1_INP

A12

PRX_MB1_INM

B12

PRX_MB2_INP

B11

PRX_MB2_INM

A9

PRX_HB_INP

A10

PRX_HB_INM

J1

DRX_BB_QP

H1

DRX_BB_QM

J2

DRX_BB_IP

H2

DRX_BB_IM

H14

DRX_LB1_INP

J14

DRX_LB1_INM

J13

DRX_LB2_INP

H13

DRX_LB2_INM

F14

DRX_MB1_INP

G14

DRX_MB1_INM

F13

DRX_MB2_INP

E13

DRX_MB2_INM

D14

DRX_HB_INP

E14

DRX_HB_INM

BGA196

(3 OF 4)

GNSS_INP

GNSS_INM

GNSS_BB_I1

GNSS_BB_I2

GNSS_BB_Q1

GNSS_BB_Q2

TX_BB_IP

TX_BB_IM

TX_BB_QP

TX_BB_QM

GND20

GND21

GND22

GND23

GND24

GND25

GND26

GND27

GND28

GND29

GND30

GND31

GND32

GND33

GND34

GND35

GND36

GND37

GND38

GND39

GND40

GND41

GND42

GND43

GND44

GND45

GND46

GND47

GND48

GND49

CELL

A4

100_GPS_IN_P

A5

100_GPS_IN_N

C2

GPS_BB_I_P

B2

GPS_BB_I_N

D2

GPS_BB_Q_P

D1

GPS_BB_Q_N

T2

TX_BB_I_P

R2

TX_BB_I_N

R1

TX_BB_Q_P

T1

TX_BB_Q_N

M11

K11

K13

K14

V11

R10

G6

G7

B7

B10

D10

D11

C13

D7

E10

F10

G10

H10

J10

H8

J8

D13

H11

G13

J11

M13

N13

N11

T13

T11

36

IN

36

IN

25

OUT

25

OUT

25

OUT

25

OUT

25

IN

25

IN

25

IN

25

IN

25

IN

25

IN

25

IN

1

C36002_RF

5600PF

10%
10V

2

CERM-X5R
01005

CELL

22-OHM-25%-0.18A-0.9DCR

WAN_GPRSYNC

WAN_GP_DATA2

25

IN

WAN_GP_DATA1

25

IN

WAN_GP_DATA0

IN

NEED TO LENGTH MATCH:
GSM_TX_LB_CLK
GP_DATA[2:0]

L36001_RF

01005

CELL

GPRSYNC

WAN_DIO_RX_ON

WAN_DIO

VTUNE_SHDR

TRANSCEIVER PHASE CONTROL PORTS

U36001_RF

TRANSCEIVER

BGA196

C1

NC

GNSS_CLK

L2

PRX_CLK

NC

V2

GSM_PH_CLK

NC

V3

GPRS_SYNC

N2

RX_ON

N1

RF_ON

E5

VTUNE_SHDR

V6

GP_DATA2

V5

GP_DATA1

V4

GP_DATA0

N7

DNC16

NC

P7

DNC17

NC

P8

DNC18

NC

N8

DNC19

NC

L10

DNC20

NC

D4

DNC0

NC

K8

DNC1

NC

B13

GND55

(1 OF 4)

SSBI_1

SSBI_2

GND79

GND78

JAM_DET

GND56

GND57

GND58

GND59

GND60

GND61

GND62

GND63

CELL

M2

RTR_SSBI_TX_GPS

M1

RTR_SSBI_PRX_DRX

V8

CORRECT SYMBOL

V9

PA_R1 AND PA_R0 SHOULD BE GND PINS

L1

NC

R4

P4

A6

B4

E6

D5

G4

E4

12

D

25

BI

25

BI

C

B

R

R705
C705

C
L

LXXX

U

U701

A

6 3

PAGE TITLE

RF TRANSCEIVER (1 0F 3)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9374

13.0.0

36 OF 102

26 OF 46

SIZE

A

D

87

6 5

4 3

RF TRANSCEIVER SWITCHING NETWORKS (2 OF 3)

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

12

D

D

BAND 5/BAND 8 PRX TRANSCEIVER SWITCH

PP_LDO14_2P65

13 21 22 27 32 35

C

01005-1

CELL

70-OHM-300MA

L37006_RF

XM0830SZ SWITCH LOGIC

PRX_B5_B8 ACTIVE BAND PORT
===========================================

HIGH 5 PORT 1 TO PORT 3

LOW 8 PORT 1 TO PORT 2

SWAPPED BAND5 AND BAND8 INPUTS FROM DEV0

29

IN

29

IN

29

IN

29

IN

100_BAND8_RX_N
100_BAND5_RX_N

100_BAND8_RX_P
100_BAND5_RX_P

B

PP_LDO14_2P65_FILT

21

1

C37001_RF

0.1UF

20%
4V

2

X5R
01005

CELL

1

C37002_RF

56PF

5%
16V

2

NP0-C0G
01005

CELL

U37001_RF

XM0831SZ-AL1067

5

PORT2+

4

PORT2-

10

PORT3-

VDD

LLP

GND

C37004_RF

27PF

12

100_PRX_B5_B8_SW_N

9

71

PORT1+PORT3+

C37005_RF

8

PORT1-

6

CTL

2

3

CELL

100_PRX_B5_B8_SW_P

100_B5_B8_RX_MTCH_N

5%

16V

NP0-C0G

01005

CELL

27PF

12

100_B5_B8_RX_MTCH_P

5%

16V

NP0-C0G

01005

CELL

U37002_RF

74LVC1G04S500

PRX_B5_B8_0 PRX_B5_B8_1

SOT891

NC NC

6

NC

3

L37002_RF

7.5NH-5NH%-140MA

L37004_RF

5.6NH-3%-140MA

L37005_RF

5.6NH-3%-140MA

L37003_RF

7.5NH-5NH%-140MA

24

51

NC

CELL

21

01005

CELL

21

01005

CELL

21

01005

CELL

21

01005

CELL

PP_LDO14_2P65

1

C37007_RF

2.2UF

10%

6.3V

2

X5R
402

CELL

100_BAND5_BAND8_RX_N

C37006_RF

50_CM_TRAP_B5

100_BAND5_BAND8_RX_P

13 21 22 27

32 35

OUT

10PF

12

5%

16V

CERM

01005

CELL

OUT

25

IN

26

26

C

B

1

C37003_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

A

6 3

INVERTER ONLY IN P106/P107

R

RXXX
C37007

C
L

L803

U

U801

PAGE TITLE

RF TRANSCEIVER (2 OF 3)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9374

13.0.0

37 OF 102

27 OF 46

SIZE

A

D

87

6 5

4 3

12

RF TRANSCEIVER DECOUPLING (3 OF 3)

PP_RF1_14_15

PP_SMPS2_RF1_1V3

22 24 28

D

C

B

A

FERR-33-OHM-0.8A-0.09-OHM

L38001_RF

0201

CELL

XW38007_RF

SHORT-10L-0.1MM-SM

XW38008_RF

XW38009_RF

SHORT-10L-0.1MM-SM

21

SHORT-10L-0.1MM-SM

CLOSE TO
U6.R5

21

21

21

PP_RF1_2_4

1

C38079_RF

10UF

20%
10V

2

X5R-CERM
0402-1

CELL

PP_RF1_5_8_9

1

C38041_RF

10UF

20%
10V

2

X5R-CERM
0402-1

CELL

PP_RF1_3_20_23

L38017_RF

12NH+/-3%-0.25A-0.7OHM

L38022_RF

4.7NH-3%-0.35A

XW38001_RF

SHORT-10L-0.1MM-SM

XW38002_RF

SHORT-10L-0.1MM-SM

1

C38003_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CLOSE TO R95

CELL

XW38003_RF

SHORT-10L-0.1MM-SM

L38018_RF

120-OHM-25%-450MA

0201

CELL

CLOSE TO
U6.M10 AND P10

L38019_RF

47-OHM-0.2A

0201

CELL

CLOSE TO

U6.U5

L38020_RF

4.7NH-3%-0.35A

0201

CELL

CLOSE TO

U6.P13

L38026_RF

10NH-3500MA-0.17OHM

0402

CELL

CLOSE TO
U6.P11

L38025_RF

70-OHM-300MA

01005-1

CELL

L38021_RF

4.7NH-3%-0.35A

0201

CELL

0201

CELL

21

0201

CELL

PP_RF1_3_20_23_GPS_PLL

21

PP_RF1_3_20_23_TX_PLL

21

PP_RF1_14_PRX_LNA

21

PP_RF1_15_DRX_LNA

21

PP_RF1_13_GPS_LNA

21

21

PP_RF1_4_TX_LO

1

C38021_RF

0.22UF

20%

6.3V

2

X5R

CELL

0201

CLOSE TO
U6.M10 AND P10

21

PP_RF1_2_TX_VCO

1

C38022_RF

0.1UF

10%

6.3V

2

X5R
201

CELL

PP_RF1_9_HB_DA

21

CELL

1

C38024_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CLOSE TO

U6.P13

PP_RF1_8_TX_MIXER_LB_DA

21

1

C38025_RF

0.22UF

20%

6.3V

2

X5R
0201

CLOSE TO
U6.P11 AND R13

CELL

PP_RF1_5_PRE_DRIVER

21

PP_RF1_3_20_23_RX_PLL

CELL

1

C38036_RF

220PF

10%
10V

2

X7R-CERM
01005

CLOSE TO
U6.K4

CELL

1

C38037_RF

220PF

10%
10V

2

X7R-CERM
01005

CLOSE TO
U6.R5

1

C38038_RF

0.1UF

20%
4V

2

X5R
01005

CELL
CLOSE TO
U6.G5

CLOSE TO

U6.U5

1

C38043_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

1

2

28

28

28

28

28

28

28

C38027_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

CLOSE TO
U6.R11

28

28

28

28

PP_SMPS2_RF1_1V3

22 24 28

PP_SMPS4_RF2_2V0

22

1

C38090_RF

4.7UF

20%
10V

2

X5R-CERM
0402

STAR ROUTE

FERR-33-OHM-0.8A-0.09-OHM

FERR-33-OHM-0.8A-0.09-OHM

CELL

L38003_RF

0201

CELL

L38004_RF

0201

CELL

L38006_RF

70-OHM-300MA

L38008_RF

70-OHM-300MA

L38009_RF

70-OHM-300MA

L38010_RF

70-OHM-300MA

L38011_RF

70-OHM-300MA

240-OHM-0.2A-0.8-OHM

PP_LDO2_XO_HS_1V8

22 24

01005-1

CLOSE TO
U6.V10

L38014_RF

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

6 3

21

PP_RF1_11_12_RX_TX_DIG

1

2

21

CELL

1

C38016_RF

10UF

20%
10V

2

X5R-CERM
0402-1

CLOSE TO
L102

21

CELL

21

01005-1

CLOSE TO
U6.L13

CELL

21

01005-1

CELL

21

01005-1

CLOSE TO
U6.K7

CELL

21

01005-1

CLOSE TO
U6.T5

CELL

21

0201

CELL

XW38004_RF

SHORT-10L-0.1MM-SM

C38010_RF

1.0UF

20%

6.3V
X5R
0201-MUR

CELL

4.7NH-3%-0.35A

L38015_RF

4.7NH-3%-0.35A

1

C38023_RF

0.1UF

20%
4V

2

X5R
01005

CLOSE TO
U6.V10
CELL

1

C38029_RF

0.1UF

20%
4V

2

X5R
01005

CELL

PP_RF2_1_5_6_MASTER_BIAS_RX_BB

1

C38031_RF

0.1UF

20%
4V

2

X5R
01005

CELL

1

C38032_RF

2.2UF

20%

6.3V

2

CERM
402-LF

CELL

CELL

1

C38034_RF

10UF

20%

6.3V

2

CERM-X5R
0402

21

XW38006_RF

SHORT-10L-0.1MM-SM

L38024_RF

4.7NH-3%-0.35A

XW38005_RF

SHORT-10L-0.1MM-SM

L38023_RF

FERR-33-OHM-0.8A-0.09-OHM

L38016_RF

0201

CELL

0201

CELL

CLOSE TO
U6.E11 AND G8

PP_RF2_2_PDET

PP_RF2_7_TX_BB

CLOSE TO
U6.L13

CLOSE TO
U6.K10

PP_RF2_3_RX_VCO

CLOSE TO
U6.K7

PP_RF2_4_TX_VCO

CLOSE TO
U6.T5

PP_SMPS3_MSME_1V8

21 22 24 25

28

PP_XO_1P8_FILT

ROUTE FROM C265 TO U6.T10 AND C269 TO U6.E7

IN A STAR CONFIGURATION FOR ISOLATION BETWEEN E7 AND T10

28

PP_RF1_11_PDET_TX

CLOSE TO
U6.H5

CLOSE TO

U6.D6

PP_RF1_12_DIG

28

28

28

28

28

1

C38020_RF

27PF

5%
16V

2

NP0-C0G
01005

CELL

28

21

CELL

1

C38039_RF

0.1UF

20%
4V

2

X5R
01005

CLOSE TO
U6.M4

21

21

0201

CELL

CLOSE TO
U6.H5

PP_RF1_11_12_RX_TX_DIG_E7

21

PP_RF1_21_GPS_VCO

21

0201

CELL

CLOSE TO

U6.D6

PP_RF1_1_PRX_VCO

1

2

21

1

2

21

1

2

28

28

1

C38040_RF

0.1UF

10%
16V

2

X5R-CERM
0201

CELL

PP_RF1_22_GPS_DIG

1

C38013_RF

0.047UF

20%
4V

2

CERM-X5R
01005

CELL

1

C38015_RF

0.1UF

20%
4V

2

X5R
01005

CELL

C38017_RF

CLOSE TO

0.1UF

20%

U6.M8

4V
X5R
01005

CELL

PP_RF1_18_DRX_LO

C38018_RF

1.0UF

20%

6.3V

CLOSE TO

X5R

U6.H7

0201-MUR

CELL

PP_RF1_17_PRX_LO

C38019_RF

0.1UF

CLOSE TO

20%

U6.G8

4V
X5R
01005

CELL

28

28

28

L38013_RF

70-OHM-300MA

01005-1

CELL

CLOSE TO
U6.M4 AND H4

CLOSE TO
U6.P5

28

1

C38042_RF

0.1UF

20%
4V

2

X5R
01005

CELL

PP_RF1_1_PRX_VCO

28

PP_RF1_2_TX_VCO

28

PP_RF1_3_20_23_RX_PLL

28

PP_RF1_3_20_23_TX_PLL

28

PP_RF1_4_TX_LO

28

PP_RF1_5_PRE_DRIVER

28

PP_RF1_8_TX_MIXER_LB_DA

28

PP_RF1_9_HB_DA

28

PP_RF1_11_PDET_TX

28

PP_RF1_12_DIG

28

PP_RF1_13_GPS_LNA

28

PP_RF1_14_PRX_LNA

28

PP_RF1_15_DRX_LNA

28

PP_RF1_11_12_RX_TX_DIG_E7

28

PP_RF1_17_PRX_LO

28

PP_RF1_18_DRX_LO

28

PP_RF1_3_20_23_GPS_PLL

28

PP_RF1_21_GPS_VCO

28

PP_RF1_22_GPS_DIG

28

PP_XO_1P8_FILT

28

PP_DIG

28

STAR ROUTE

PP_RF2_1_5_6_MASTER_BIAS_RX_BB

28

PP_RF2_2_PDET

28

PP_RF2_3_RX_VCO

28

PP_RF2_4_TX_VCO

28

PP_RF2_7_TX_BB

28

PP_DIG

28

1

C38044_RF

0.22UF

20%

6.3V

2

X5R
0201

CELL
PLACE CLOSE TO PIN T10

STAR ROUTE

U36001_RF

TRANSCEIVER

M8

M10

R11

L14

P10

P11

P13

R13

T10

G11

F11

E11

V10

K10

L13

U5

K4

R5

M5

B6

D8

D9

E7

G8

H7

B5

G5

D6

H5

P5

M4

H4

E9

K7

T5

E8

VDD_RF1_1

VDD_RF1_2

VDD_RF1_3

VDD_RF1_23

VDD_RF1_4

VDD_RF1_5

VDD_RF1_6

VDD_RF1_7

VDD_RF1_8

VDD_RF1_9

VDD_RF1_10

VDD_RF1_11

VDD_RF1_12

VDD_RF1_13

VDD_RF1_14

VDD_RF1_141

VDD_RF1_15

VDD_RF1_151

VDD_RF1_16

VDD_RF1_17

VDD_RF1_171

VDD_RF1_18

VDD_RF1_19

VDD_RF1_20

VDD_RF1_21

VDD_RF1_22

VDD_XO

VDD_DIG

VDD_DIG_IO

VDD_RF2_1

VDD_RF2_2

VDD_RF2_3

VDD_RF2_4

VDD_RF2_5

VDD_RF2_6

VDD_RF2_7

NC

NC

NC
NC

NC
NC

RX OSCILLATOR 1
TX OSCILLATOR 1

RX PLL

TX PLL
TX LO HIGH/MID BAND

LB/HB PRE DRIVER AMP
HB PRE DRIVER AMP

TX LB

TX MIXER
HIGH BAND DRIVER AMP

LB DRIVER AMP

TX DIGITAL
RX/TX/SBI DIGITAL

GPS LNA

PRX LNA
PRX LNA

DRX LNA

DRX LNA

RX BB
PRX LO

PRX LO

DRX LO

GPS RX
GPS/SHDR PLL

GPS/SHDR OSCILLATOR AND LO

GPS/SHDR DIGITAL

XO SUPPLY
RF DIGITAL

RF DIGITAL IO

MASTER BIAS

PDET

RX OSCILLATOR 2
TX OSCILLATOR 2

PRX BB

DRX BB
TX BB

TRANSCEIVER

A1

GND64

A2

GND65

A3

GND66

A13

GND67

A14

GND68

B1

GND69

B3

GND70

B14

GND71

D3

DNC2

E2

DNC3

E3

DNC4

G1

DNC5

G3

DNC6

H3

DNC7

PAGE TITLE

U36001_RF

BGA196

(4 OF 4)

RF TRANSCEIVER (3 OF 3)

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BGA196

(2 OF 4)

DNC10

DNC11

DNC12

GND72

GND73

GND74

DNC13

DNC14

GND75

GND76

DNC15

GND77

Apple Inc.

DNC8

DNC9

CELL

K1

K2

K3

L3

P2

U1

U2

U3

U6

U9

U12

V1

V7

V14

NC
NC

NC

NC
NC

NC
NC

NC

L7

GND0

L8

GND1

M7

GND2

R7

GND3

T7

GND4

U7

GND5

L11

GND6

U11

GND7

N10

GND8

N4

GND9

L5

GND10

H6

GND11

J7

GND12

K5

GND13

L4

GND14

T8

GND15

R8

GND16

U8

GND17

U4

GND18

T4

GND19

CELL

R
C

L

XW

DRAWING NUMBER

051-9374

REVISION

BRANCH

PAGE

38 OF 102

SHEET

28 OF 46

124578

R912

C942
L924

XW906

13.0.0

SIZE

D

C

B

A

D

87

6 5

BAND 5/8 PAD

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

HIGH ATTENUATION

FL39002_RF

UMTS-BAND8TX-2.6DB

1

INPUT

SAFFB897MAM0F57

LLP

GND

543

2

OUTPUT

CELL

50_BAND8_TX_INT_OUT

C39003_RF

82PF

6.3V

NP0-C0G

01005

NOSTUFF

L39002_RF

6.8NH-3%-140MA

01005

1

5%

2

CELL

D

50_XCVR_3G_B8_TX

26

IN

C39001_RF

10PF

12 21

50_3G_TX_B8_T

5%

16V

CERM

01005

CELL
PLACE MATCHING
CLOSE TO XCVR

L39011_RF

6.2NH-5NH%-140MA

1

L39001_RF

5.1NH-3%-0.16A

01005

CELL

2

01005

21

50_TX_3G_B8_FILT

CELL

50_BAND8_TX_PA_IN

1

C39024_RF

0.4PF

+/-0.1PF
16V

2

NP0-C0G
01005

CELL

4 3

12

D

PA_ON_B5

PP_PA

30 31 33 34

IN

1

C39021_RF

220PF

10%
10V

2

X7R-CERM
01005

CELL

HIGH ATTN

FL39001_RF

C

26

IN

50_XCVR_3G_B5_TX

C39005_RF

12PF

12

5%

16V

CERM

01005

CELL

C39004_RF

50_3G_TX_B5_T

1

L39006_RF

4.7NH-3%-160MA

01005

CELL

2

33PF

12

5%

16V

NP0-C0G

01005

CELL

32

50_BAND5_TX_INT_IN

50_TXRX_B5_ASM

BI

SAFFB836MAL0F57

1

L39012_RF

6.8NH-3%-0.3A

0201

CELL

0201

CELL

C39006_RF

10PF

12

5%

16V

CERM

01005

CELL

50_BAND5_TX_PA_IN

1

L39010_RF

12NH-3%-140MA

01005

NOSTUFF

2

LGA

GND

532

21 21

50_TXRX_B5_PAD_MCH 50_TXRX_B5_PAD_ANT

4

OUTIN

OMIT

1

C39012_RF

2.1PF

+/-0.1PF
25V

2

C0G-CERM
0201

CELL

50_BAND5_TX_INT_OUT

1

L39003_RF

18NH-3%-140MA

01005

CELL

2

L39013_RF

7.5NH-150MA

21 22 23 30 31 33 34

IN

PP_BATT_VCC_CONN

23

RFIN_5

13

ANT_5

16

RX_5

17

RX_5Q

1

3

5

1

2

CELL

9

8

1

C39022_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

C39020_RF

0.01UF

10%

6.3V
X5R
01005

GND

121415

11

25

VBATT

20

18

2

VCC

U39001_RF

SKY77487

LGA

24

26

29

27

VEN_5

28

VEN_8

21

22

VMODE0

VMODE1

THRM_PAD

37363534333231

1

C39007_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

CPL_IN

CPL_OUT

RFIN_8

383940

ANT_8

RX_8

RX_8Q

41

42

OMIT

1

C39008_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

4

19

30

10

6

7

1

C39009_RF

100PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

50_CPL_B13_B17_OUT

50_CPL_B5_B8_OUT

1

2

B

100_BAND8_DUPLX_RX_N

1

L39007_RF

1.0NH+/-0.1NH-0.22A-0.9OHM

01005

NOSTUFF

BOM OPTIONS

PART#

353S3415

353S3568

DESCRIPTION

QTY

1

SKY77487 BAND 5/8 PAD

1

SKY77491 BAND5_E/8 PAD

BAND5 TX SAW

BAND5/BC10 TX SAW

REFERENCE DESIGNATOR(S)

U39001_RF

U39001_RF

FL39001_RF155S0552

FL39001_RF155S0742

A

CRITICAL BOM OPTION

Y

Y

Y1

Y1

B4_17

B3_13

B4_17

B3_13

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

100_BAND5_DUPLX_RX_N

1

2

100_BAND5_DUPLX_RX_P

C39018_RF

39PF

12

NP0-C0G

01005

L39009_RF

15NH-5%-140MA

01005

NOSTUFF

C39019_RF

39PF

12

NP0-C0G

01005

5%

16V

CELL

5%

16V

CELL

100_BAND5_RX_N

100_BAND5_RX_P

27

OUT

27

OUT

100_BAND8_DUPLX_RX_P

2

PA_ON_B8

PA_R0

PA_R1

C39011_RF

100PF

5%
16V
NP0-C0G
01005

NOSTUFF

30

IN

33

OUT

R39002_RF

C39014_RF

15PF

12

CELL

5%

16V

NP0-C0G-CERM

01005

C39016_RF

15PF

12

CELL

5%

16V

NP0-C0G-CERM

01005

12

1/20W

100_BAND8_RX_N

100_BAND8_RX_P

6 3

0

5%

MF

201

CELL

25

IN

25

IN

25

30 31 33 34

IN

25 30 33

IN

L39005_RF

50_TXRX_B8_PAD_MCH50_TXRX_B8_PAD_ANT

1

C39013_RF

1.2PF

+/-0.1PF
25V

2

C0G-CERM
0201

CELL

27

OUT

27

OUT

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

4.7NH-3%-0.35A

BAND 5/8 PAD

Apple Inc.

R

0201

CELL

21

R1003

R

C39023

C
L

L39010

U

U1001

50_TXRX_B8_ASM

DRAWING NUMBER

051-9374

REVISION

BRANCH

PAGE

39 OF 102

SHEET

29 OF 46

124578

BI

13.0.0

C

32

B

A

SIZE

D

87

6 5

4 3

B13/17 INTERSTAGE, PA, AND DUPLEXER

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

12

D

C

26

4.7NH-3%-160MA

IN

50_XCVR_3G_B13_TX

L40009_RF

01005

CELL

C40001_RF

5.0PF

+/-0.1PF

16V

NP0-C0G

01005

CELL

C40002_RF

21

50_3G_TX_B13_T

1

2

PLACE MATCHING

CLOSE TO XCVR

18PF

12

50_BAND13_TX_INT_IN

2%

16V

CERM

01005

CELL

D

L40006_RF

R40004_RF

0.00

100_BAND13_DUPLX_RX_P

PP_PA

29 31 33 34

IN

10

RFOUT

THRM

PAD

11

ISOVBP

CPL

1

C40007_RF

220PF

10%
10V

2

X7R-CERM
01005

CELL

50_BAND13_PA_OUT

83

PP_BATT_VCC_CONN

21 22 23 29 31 33 34

IN

1

C40005_RF

0.01UF

10%

6.3V

2

X5R
01005

LOW INSERTION LOSS

FL40001_RF

UMTS-BAND17TX-1DB

SAFFB710MAA0F57

LLP

1

INPUT

PA_R1

25 29 33

IN

PA_R0

25 29 31 33 34

IN

PA_ON_B13

25

IN

OMIT

GND

543

2

R40001_RF

0.00

12

0%

1/32W

MF

01005

CELL

OUTPUT

50_BAND13_TX_INT_OUT

PA_R1_VBP

C40003_RF

6.8PF

12

+/-0.1PF

16V

NP0-C0G

01005

CELL

50_3G_TX_B13_PA_T

1

2

CELL

C40004_RF

18PF

12

2%

16V

CERM

01005

L40002_RF

15NH-3%-140MA

01005

CELL

CELL

50_BAND13_TX_PA_IN

1

VCC1 VCC2

U40001_RF

ACPM-5617

LGA

OMIT

29

RFIN

46

VMODE

5

VEN

GND

7

1

C40008_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

C40011_RF

22PF

12

5%

25V

NP0-C0G

0201

OMIT

L40010_RF

3.3NH+/-0.1NH-0.45A

50_BAND13_PA_MATCH

1

L40003_RF

27NH-3%-0.140A-2.3OHM

0201

OMIT

2

0201

OMIT

50_BAND13_DUPLX_TX

21

3

TX

100_BAND13_DUPLX_RX_N

U40002_RF

BAND17-UMTS

AI45A

LLP

OMIT

GND

542

7

RX

ANT

12

1

SIGNAL_MODEL=EMPTY

L40012_RF

15NH-3%-140MA

01005

CELL

2

R40005_RF

12

1

8

6

50_BAND13_DUPLX_ANT

1

2

100_BAND13_DUPLX_MATCH_RX_P

0%

1/32W

MF

01005

CELL

0.00

1/32W

01005

CELL

100_BAND13_DUPLX_MATCH_RX_N

0%

MF

L40005_RF

3.0NH+/-0.1NH-0.45A

0201

OMIT

L40004_RF

15NH+/-3%-0.25A-0.7OHM

0201

OMIT

7.5NH-5NH%-140MA

1

SIGNAL_MODEL=EMPTY

L40007_RF

15NH-3%-140MA

01005

NOSTUFF

2

7.5NH-5NH%-140MA

21

50_BAND13_TRX_MATCH

01005

CELL

L40008_RF

01005

CELL

L40011_RF

6.8NH-3%-0.3A

1

C40017_RF

2.7PF

+/-0.1PF
25V

2

C0G-CERM
0201

CELL

21

100_BAND13_RX_P

21

100_BAND13_RX_N

0201

CELL

PLACE MATCHING
CLOSE TO XCVR

50_BAND13_TRX

21

26

OUT

26

OUT

C

32

BI

1

C40018_RF

100PF

5%
16V

2

NP0-C0G
01005

B

A

PA POWER MODES

MODE

==================================

LOW

MEDIUM
HIGH

PA_R0

HIGH

LOW
LOW

PA_R1

HIGH

HIGH
LOW

CELL

1

C40009_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

6 3

1

C40010_RF

100PF

5%
16V

2

NP0-C0G
01005

29

CELL

50_CPL_B13_B17_OUT

OUT

50_CPL_B13_B17_TERM

1

R40003_RF

49.9

1%
1/32W
MF
01005

2

CELL

BOM OPTIONS

PART#

353S3567

353S3441

155S0709

155S0738

152S1280

131S0129

131S0198

117S0002

152S1284

152S1336

152S1342

152S1063

152S1222

DESCRIPTION

QTY

BAND17 TX SAW

1

1 Y

BAND13 TX SAW

BAND17 PAM - SKY77729

1

BAND13 PAM - AVAGO ACPM-5613

BAND17 DUPLEXER

1

BAND13 DUPLEXER

1 Y

5.1 NH INDUCTOR, 0201

1

22 PF CAPACITOR, 0201

1 Y

1.8 PF CAPACITOR, 0201

1

0 OHMS RESISTOR, 0201

1

1

3.3 NH INDUCTOR, 0201

8.2 NH INDUCTOR, 0201

1

15 NH INDUCTOR, 0201

1

2.2 NH INDUCTOR, 0201

1

3.0 NH INDUCTOR, 0201

REFERENCE DESIGNATOR(S)

FL40001_RF155S0620

FL40001_RF155S0619

U40001_RF

U40001_RF

U40002_RF

U40002_RF

C40011_RF

C40011_RF

L40003_RF

L40010_RF

L40010_RF

L40004_RF

L40004_RF

L40005_RF

L40005_RF

CRITICAL BOM OPTION

Y

Y

Y1

Y

Y

Y

Y

Y

Y

Y

Y

Y1

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

B

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

FL

FL1101
R1102

R

C1118

C

L1108

L

U1102

U

BAND 13 PA

Apple Inc.

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

40 OF 102

SHEET

30 OF 46

SIZE

A

D

124578

87

6 5

4 3

12

2G PA, PA DC/DC CONVERTER

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

PP_BATT_VCC_CONN

21 22 23 29 30 31 33 34

IN

1

2

IN

IN

IN

1

2

DCDC_ADJ

DCDC_EN

DCDC_MODE

C41018_RF

0.01UF

10%

6.3V
X5R
01005

CELL

DCDC_PGND

31

D

C41001_RF

56PF

6.3V

NP0-C0G

01005

CELL

5%

25

25

25

C

C41009_RF

12PF

50_XCVR_2G_PA_HB_TX

26

IN

50_XCVR_2G_PA_LB_TX

26

IN

0.8NH+/-0.1NH-0.32A-0.6OHM

12

5%

16V

CERM

01005

CELL

L41005_RF

01005

CELL

B

1

2

50_TX_G_HB_MCH

1

C41016_RF

2.4PF

+/-0.1PF
16V

2

NP0-C0G
01005-1

CELL

21

50_TX_G_LB_MCH

C41019_RF

4.7UF

20%

6.3V
X5R
402

CELL

A2

REFIN

U41001_RF

B1

EN

C1

MODE

L41003_RF

4.7NH-3%-160MA

01005

CELL

C41017_RF

1

C41011_RF

6PF

+/-0.5PF
16V

2

NP0-C0G
01005

CELL

B2

IN1

CELL

MAX77100

WLP

AGND

A1

31

21

33PF

12

5%

16V

NP0-C0G

01005

CELL

C2

IN2

OUT

LX

PGND

A3

XW41002_RF

SHORT-10L-0.25MM-SM

DCDC_PGND

XW41003_RF

SHORT-10L-0.25MM-SM

50_TX_G_HB_PAIN

50_TX_G_LB_PAIN

1

C41020_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

DCDC_PGND

C3

2.2UH-20%-1.7A-200MOHM

B3

DCDC_OUT

12

L41001_RF

21

NOSTUFF

21

NOSTUFF

21 22 23 29 30 31 33 34

IN

1

2

31

TFA201610G-SM

CELL

PP_BATT_VCC_CONN

C41021_RF

0.01UF

10%

6.3V
X5R
01005

CELL

240-OHM-25%-0.20A-1.0DCR

1

C41003_RF

56PF

5%
16V

2

NP0-C0G
01005

CELL

PLACE CLOSE TO L41001_RF

CELL

1

C41002_RF

4.7UF

20%

6.3V

2

X5R
402

DCDC_PGND

1

2

31

PP_PA

1000PF

10%

6.3V
X5R-CERM
01005

OUT

CELL

C41015_RF

29 30 31 33

L41007_RF

21

01005

CELL

PA_R0

25 29 30 33 34

IN

GSM_PA_LB_EN

25

IN

GSM_PA_HB_EN

25

IN

34

29 30 31 33 34

IN

1

C41022_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

1

C41007_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

CELL

PP_PA

1

C41005_RF

4.7UF

20%

6.3V

2

X5R-CERM1
402

CELL

1

C41008_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

1

2

PP_BATT_VCC_FB

1

C41004_RF

0.01UF

10%

6.3V

2

X5R
01005

CELL

1

HB_GSM_RF_IN

3

LB_GSM_RF_IN

6

VMODE0

4

PA_ON2

5

PA_ON3

GND

GND

9

2

C41006_RF

0.1UF

20%
4V
X5R
01005

CELL

7

14

V2G

VBATT

U41002_RF

SKY77352

LGA

THRM_PAD

THRM_PAD

THRM_PAD

GND

GND

GND

131210

HB_GSM_RF_OUT

LB_GSM_RF_OUT

THRM_PAD

THRM_PAD

THRM_PAD

THRM_PAD

THRM_PAD

11

8

THRM_PAD

CELL

232221201918171615

50_TX_G_HB_PAOUT

50_TX_G_LB_PAOUT

R41002_RF

0

12

5%

1/20W

MF

201

CELL

L41008_RF

2.2NH+/-0.1NH-0.6A

0201

CELL

21

2G PA GAIN MODES

BAND

=======================================================

LOW BAND
LOW BAND
LOW BAND
LOW BAND
HIGH BAND
HIGH BAND
HIGH BAND
LOW BAND
LOW BAND
LOW BAND
HIGH BAND
HIGH BAND

50_TX_G_HB_PAMCH

1

2

50_TX_G_LB_PAMCH

MODE

GSM
GSM
GSM
GSM
GSM
GSM
GSM
EDGE
EDGE
EDGE
EDGE
EDGE

L41004_RF

1.5NH+/-0.1NH-600MA

C41010_RF

0.5PF

+/-0.05PF
25V
COG-CERM
0201

CELL

L41006_RF

4.7NH-3%-0.35A

0201

CELL

CELL

0201

GAIN MODE

ULTRA LOW

LOW

MEDIUM

HIGH

ULTRA LOW

LOW

HIGH

LOW

MEDIUM

HIGH

LOW

HIGH

21

50_TX_G_HB_ASM

21

50_TX_G_LB_ASM

PA_R1

HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW

OUT

OUT

32

32

PCL RANGE

16 TO 19
14 TO 15
7 TO 13
5 TO 6
10 TO 15
7 TO 9
0 TO 6
15 TO 19
10 TO 14
8 TO 9
9 TO 15
2 TO 8

D

C

B

1

C41012_RF

1.5PF

+/-0.1PF
25V

2

C0G-CERM
0201

CELL

R

R1209

C

C1215

L

L41007

U

U1202

A

6 3

PAGE TITLE

2G PA, DCDC CONVERTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

41 OF 102

SHEET

31 OF 46

124578

SIZE

A

D

87

6 5

ASM,DCS RX

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

4 3

12

D

13 21 22 27 35

C

CELL

C42001_RF

27PF

100_XCVR_DCS1800_RX_N

26

OUT

100_XCVR_DCS1800_RX_P

26

OUT

12

5%

16V

NP0-C0G

01005

SIGNAL_MODEL=EMPTY

L42001_RF

10NH-3%-140MA

01005

C42002_RF

27PF

12

5%

16V

NP0-C0G

01005

CELL

100_DCS1800_RX_MATCH_N

1

CELL

2

100_DCS1800_RX_MATCH_P

B

L42004_RF

1.2NH+/-0.1NH-220MA

01005

CELL

01005

CELL

L42002_RF

5.6NH-3%-140MA

L42005_RF

1.2NH+/-0.1NH-220MA

21

01005

CELL

21

1

2

100_PRX_DCS_G_1_P

100_PRX_DCS_G_1_N

FL42001_RF

DCS1800-RX-2.0DB

SAFFB1G84FB0F57

LLP

3

OUT1

OMIT

4

OUT2

50_DRX_B3_ZERO_OHM

35

IN

IN

GND

5

2

50_DRX_B3_OUT

PLACE R42002 CLOSE TO FL42001

50_RX_DCS_FIL

1

1

R42007_RF

0.00

0%
1/32W
MF
01005

2

OMIT

PLACE R42007 CLOSE TO FL42001

1

R42001_RF

0.00

0%
1/32W
MF
01005

2

OMIT

PLACE R42001 CLOSE TO R42005

1

R42005_RF

49.9

1%
1/32W
MF
01005

2

OMIT

50_BAND13_TRX

30

IN

R42002_RF

0.00

12

0%

1/32W

MF

01005

OMIT

FL42002_RF

BAND13-0.3DB

LFL18766MTH1D393

1

IN

OMIT

GND

PIN DEFINITION UPDATED FOR LAYOUT/ISOLATION COMPROMISE
5/30/2011

50_TXRX_B8_ASM

29

BI

50_TXRX_B4_ASM

33

BI

50_TXRX_B5_ASM

29

BI

50_TXRX_B1_ASM

33

1

R42003_RF

0.00

0%
1/32W
MF
01005

2

OMIT

3

OUT

2

BI

50_RX_DCS

50_TXRX_B13_ASM

50_TXRX_B2_ASM

34

BI

IN

IN

50_TX_G_HB_ASM
50_TX_G_LB_ASM

31

31

PP_LDO14_2P65

IN

50_OHM_TERM_2

1

R42006_RF

49.9

1%
1/32W
MF
01005

2

CELL

6

TRX1

7

TRX2

8

TRX3

9

TRX4

10

TRX5

17

TRX6

18

TRX7

19

TRX8

4

TXHB

5

TXLB

USE MURATA PART DUE TO LARGEST PACKAGE OUTLINE

16

VDD

U42001_RF

SKY13420

LGA

THRM

GND

PAD

3

21

R42008_RF

1

C42005_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

VC1

VC2
VC3

VC4
VC5

ANT1

ANT2
ANT3

OMIT

50_ANT2_TERM

49.9

1/32W

01005

CELL

11

12
13

14

15

ANT_SEL_4_LOW

20

1

2

1%

MF

1

2

1

C42006_RF

0.1UF

20%
4V

2

X5R
01005

CELL

1

R42010_RF

10K

5%
1/32W
MF
01005

2

CELL

50_ASM_ANT

1

2

1

100PF

5%
16V

2

NP0-C0G
01005

C42007_RF

CELL

R42011_RF

0.00

12

1%

1/20W

MF

0201

CELL

50_ANT1_TERM

R42009_RF

49.9

1%
1/32W
MF
01005

CELL

1

C42008_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

50_ASM_ANT_MCH

1

CELL

100PF

5%
16V

2

NP0-C0G
01005

C42009_RF

L42006_RF

1.5NH+/-0.1NH-600MA

1

C42013_RF

0.5PF

+/-0.05PF
25V

2

COG-CERM
0201

CELL

0201

CELL

1

2

ANT_SEL_0

ANT_SEL_1
ANT_SEL_2

ANT_SEL_3

C42010_RF

100PF

5%
16V
NP0-C0G
01005

CELL

21

50_PRI_ANT

IN

IN

IN

IN

D

C

25

21 25

21 25

25

36

IN

B

BOM OPTIONS

PART#

155S0596 FL42001_RF

155S0729

155S0695 FL42002_RF

155S0722

A

118S0652

118S0652

117S0161 0OHM RES

353S3573

353S3573

DESCRIPTION

QTY

1

DCS1800 RX FIL

BAND3 RX FIL

1

1 Y

THRU LINE

BAND13 TX LPF

1

1

0OHM RES117S0161

1 Y

0OHM RES117S0161

49.9OHM RES

1

49.9OHM RES

1

ASM, SKYWORKS

ASM, SKYWORKS

REFERENCE DESIGNATOR(S)

FL42001_RF

FL42002_RF

R42001_RF

R42002_RF

R42003_RF

R42005_RF

R42007_RF

U42001_RF

U42001_RF

6 3

CRITICAL BOM OPTION

Y

Y

Y

Y

Y

Y

Y1

Y1

Y1

B4_17

B3_13

B4_17

B3_13

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PAGE TITLE

DCS RX, ASM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R
C
L
U

FL

R42011
C42013

42006
U1301
FL1302

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

42 OF 102

SHEET

32 OF 46

SIZE

A

D

124578

87

6 5

BAND 1/4 PAD

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

4 3

12

SIZE

D

C

B

A

D

D

29 30 31 34

LOW INSERTION LOSS

FL43001_RF

C43001_RF

4.7PF

50_XCVR_3G_B1_TX

26

IN

C

50_XCVR_3G_B4_TX

26

IN

12 12

+/-0.1PF

16V
NP0-C0G
01005-1

CELL

PLACE MATCHING
CLOSE TO XCVR

C43009_RF

7.0PF

12 12

+/-0.1PF

16V

NP0-C0G

01005

CELL

B

C43002_RF

50_3G_TX_B1_T

1

L43001_RF

2.2NH+/-0.1NH-200MA

01005

CELL

2

50_TX_B4_MCH

1

L43007_RF

1.7NH+/-0.1NH-0.200A

01005

CELL

2

10PF

50_BAND1_TX_IN_IN

5%

16V

CERM

01005

CELL

C43010_RF

18PF

50_BAND4_TX_IN

2%

16V

CERM

01005

CELL

SAFFB1G95AA0F57

1

IN OUT

LOW INSERTION LOSS

FL43002_RF

BAND4-TX-1.6DB

SAFFB1G73KA0F57

14

IN OUT

LLP

OMIT

GND

LGA

GND

235

532

CELL

50_BAND4_TX_INT_OUT

1

C43011_RF

2

OMIT

C43028_RF

4.0PF

4

2.9NH+/-0.1NH-200MA

0.7PF

+/-0.1PF
16V
NP0-C0G
01005

12

+/-0.1PF

16V

NP0-C0G

01005

CELL

50_BAND1_TX_INT_OUT

1

L43021_RF

15NH-5%-140MA

01005

CELL

2

L43017_RF

21 21

01005

OMIT

50_BAND1_TX_PA_IN

1

L43002_RF

4.7NH+/-0.3NH-160MA

01005

NOSTUFF

2

50_BAND4_TX_PA_IN

1

L43008_RF

6.2NH-5NH%-140MA

01005

NOSTUFF

2

BOM OPTIONS

PART#

152S1407

131S0375

152S1407

152S1570

152S1570

131S0375

131S0377

131S0377

131S0377

152S1571

152S1567

131S0215

A

131S0198

131S0337

152S1407

152S1571

131S0219

131S0219

131S0307

131S0307

DESCRIPTION

QTY

1

6.2 NH INDUCTOR

1.0 PF CAPACITOR

6.2NH INDUCTOR

1

4.7NH INDUCTOR

1

4.7NH INDUCTOR

1

1.0PF CAPACITOR

1.2PF CAPACITOR

1.2PF CAPACITOR

1.2 PF CAPACITOR

5.6 NH INDUCTOR

1

3.3 NH INDUCTOR

1

22 PF CAPACITOR

1

1.8 PF CAPACITOR

1

1.5 PF CAPACITOR

1 Y

1

6.2NH INDUCTOR

5.6NH INDUCTOR

1

1

10PF CAPACITOR

1

10PF CAPACITOR

1

100PF CAPACITOR

100PF CAPACITOR

REFERENCE DESIGNATOR(S)

L43020_RF

C43015_RF

L43016_RF

L43016_RF

L43020_RF

C43020_RF

C43020_RF

C43015_RF

C43011_RF

C43011_RF

L43017_RF

L43017_RF

C43016_RF

C43016_RF

L43013_RF

L43013_RF

C43021_RF

C43022_RF

C43021_RF

C43022_RF

CRITICAL BOM OPTION

Y

Y1

Y1

Y

Y

Y

Y1

Y1

Y1

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y1

B3_13

B4_17

B3_13

B4_17

B4_17

B4_17

B3_13

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B4_17

B3_13

B3_13

6 3

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PP_PA

IN

PP_BATT_VCC_CONN

21 22 23 29 30 31 34

IN

30

23
16

50_TXRX_B4_PAD_ANT

50_TXRX_B1_PAD_ANT

1

C43026_RF

220PF

10%
10V

2

X7R-CERM
01005

CELL

1

C43017_RF

0.01UF

10%

6.3V

2

X5R
01005

CELL

RFIN_1

7

ANT_1

RFIN_4

ANT_4

35698

2.2NH+/-0.1NH-0.6A

27

L43024_RF

0201

OMIT

L43022_RF

2.2NH+/-0.1NH-0.6A

28

VBATT

U43001_RF

GND

15

1417182022

29

21

50_TXRX_B4_PAD_MCH

21

0201

OMIT

21

VCC

SKY77486

1

2

50_TXRX_B1_PAD_MCH

25

BS

PA_ON

VMODE0

VMODE1

LGA

OMIT

263231

333534383736403941

L43009_RF

3.0NH+/-0.1NH-0.45A

0201

CELL

C43016_RF

1.8PF

+/-0.1PF
25V
C0G
201

OMIT

1

C43027_RF

1.8PF

+/-0.1PF
25V

2

C0G
201

CELL

24

2

1

BOM OPTIONS

353S3255

353S3443

155S0590

155S0712

152S1063

152S1222

152S1284

152S1222

152S1063

152S1222

PA_R0

PA_R1

B1B4_SELECT

PA_ON_B1B4

1

C43005_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

4

CPL_IN

19

CPL_OUT

10

RX1Q

11

RX1

12

RX4Q

13

THRM_PAD

21

50_TXRX_B4_ASM

3.3NH+/-0.1NH-0.45A

PART#

RX4

42

32

BI

L43023_RF

21

0201

OMIT

DESCRIPTION

QTY

B1/4 PAD, AVAGO AFEM-7814

1

B1/3 PAD, AVAGO AFEM-7813

1

B4 TX FIL

1 Y

B3 TX FIL

1

2.2NH INDUCTOR

3.0NH INDUCTOR

1 Y

3.3NH INDUCTOR

3.0NH INDUCTOR

1

2.2NH INDUCTOR

1 Y

3.0NH INDUCTOR

1

C43006_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

50_CPL_B5_B8_OUT

50_CPL_B1_B4_OUT

100_BAND4_DUPLX_RX_P

100_BAND4_DUPLX_RX_N

50_TXRX_B1_ASM

1

2

BI

REFERENCE DESIGNATOR(S)

25

29 30 31 34

IN

25 29 30

IN

25

IN

25

IN

29

IN

OUT

100_BAND1_DUPLX_RX_P

PLACE CLOSE TO PAD

L43003_RF

4.7NH-3%-160MA

01005

CELL

100_BAND1_DUPLX_RX_N

R43005_RF

0.00

12

0%

1/32W

MF

01005

PLACE CLOSE TO PAD

NOSTUFF

R43006_RF

0.00

12

0%

CELL

1/32W

MF

01005

32

U43001_RF

U43001_RF

FL43002_RF

FL43002_RF

L43022_RF

L43022_RF

L43023_RF

L43023_RF

L43024_RF

L43024_RF

34

0.4NH+/-0.1NH-320MA

0.4NH+/-0.1NH-320MA

4.7NH+/-0.3NH-160MA

100_B4_DUPLX_P

1

R43004_RF

0.00

0%
1/32W
MF
01005

2

CELL

100_B4_DUPLX_N

CRITICAL BOM OPTION

Y

Y

Y

Y1

Y1

Y

Y1

L43012_RF

01005

CELL

L43014_RF

01005

CELL

L43020_RF

01005

OMIT

PLACE MATCHING
CLOSE TO XCVR

C43015_RF

1.0PF

12

+/-0.1PF

16V

NP0-C0G

01005

OMIT

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

B4_17

B3_13

21

100_BAND1_DUPLX_MATCH_RX_P

1

SIGNAL_MODEL=EMPTY

L43005_RF

3.3NH+/-0.3NH-150MA

01005

NOSTUFF

2

21

100_BAND1_DUPLX_MATCH_RX_N

100_BAND4_DUPLX_MATCH_RX_P

1

C43020_RF

1.0PF

+/-0.1PF
16V

2

NP0-C0G
01005

OMIT

100_BAND4_DUPLX_MATCH_RX_N

1

L43016_RF

4.7NH+/-0.3NH-160MA

01005

OMIT

2

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C43021_RF

1

SIGNAL_MODEL=EMPTY

L43013_RF

6.2NH-5NH%-140MA

01005

OMIT

2

C43022_RF

BAND 1/4 PAD

Apple Inc.

R

C43023_RF

27PF

12

5%

16V

NP0-C0G

01005

CELL

CELL

C43024_RF

27PF

12

5%

16V

NP0-C0G

01005

10PF

12

5%

16V

CERM

01005

OMIT

10PF

12

5%

16V

CERM

01005

OMIT

RCR1406

L
U

FL

100_BAND1_RX_P

PLACE MATCHING

CLOSE TO XCVR

100_BAND1_RX_N

100_BAND4_RX_P

100_BAND4_RX_N

C43027

L43018
U1401
FL1101

26

OUT

26

OUT

26

OUT

26

OUT

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

43 OF 102

SHEET

33 OF 46

124578

87

6 5

BAND2 PAD

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

4 3

12

D

PP_PA

29 30 31 33

IN

1

C44011_RF

220PF

10%
10V

2

X7R-CERM
01005

CELL

PP_BATT_VCC_CONN

21 22 23 29 30 31 33

IN

C

HIGH ATTENUATION

FL44001_RF

B2-25-TX-3.5DB

26

IN

C44001_RF

50_XCVR_3G_B2_TX

PLACE MATCHING
CLOSE TO XCVR

3.5PF

12

+/-0.1PF

16V

NP0-C0G

01005

CELL

50_3G_TX_B2_T

1

2

C44015_RF

18PF

12

50_BAND2_TX_INT_IN

2%

16V

CERM

01005

CELL

L44010_RF

2.1NH+/-0.1NH-0.2A-1.35OHM

01005

CELL

1

INPUT

SAFFB1G88KC1F57

LLP

GND

543

2

OUTPUT

CELL

C44003_RF

50_TX_B2

33PF

12

5%

16V

NP0-C0G

01005

CELL

2.3NH+/-0.1NH-0.2A-1.35OHM

50_TX_PCS_1

L44008_RF

01005

1

L44002_RF

3.6NH+/-0.1NH-180MA

01005

NOSTUFF

2

33

IN

CELL

50_CPL_B1_B4_OUT

21

1

2

50_TX_PCS_2

1

C44012_RF

1.0UF

20%

6.3V

2

X5R
0201-MUR

CELL

C44013_RF

0.01UF

10%

6.3V
X5R
01005

CELL

13

RFIN

4

ISO

9

NC

NC

2

1

11

VM

VCC2

VCC1

U44001_RF

BAND-2-25

TQM666083

LGA

OMIT

THRML

GND

PAD

538

14

12

VEN

10

CPL

7

ANT

6

RX

B

PA_R0

PA_ON_B2

1

C44005_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

50_CPL_PDET

50_TXRX_B2_PAD_ANT

50_B2_DUPLX_RX

25 29 30

31 33

IN

25

IN

L44011_RF

1.0NH+/-0.1NH-0.75A

26

OUT

C44007_RF

33PF

12

5%

16V

NP0-C0G

01005

CELL

21 21

0201

CELL

50_B2_RX_BAL

50_TXRX_B2_PAD_MCH

3.0NH+/-0.1NH-200MA

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

C44008_RF

1.5PF

+/-0.1PF
16V
NP0-C0G
01005-1

CELL

1

C44014_RF

0.5PF

+/-0.05PF
25V

2

COG-CERM
0201

CELL

L44005_RF

01005

CELL

L44009_RF

1.8NH+/-0.1NH-600MA

0201

CELL

21

C44009_RF

1.5PF

+/-0.1PF

1

L44007_RF

5.6NH-3%-140MA

01005

SIGNAL_MODEL=EMPTY

CELL

2

3.0NH+/-0.1NH-200MA

16V

NP0-C0G

01005-1

CELL

L44006_RF

01005

CELL

50_TXRX_B2_ASM

100_BAND2_RX_P

21

100_BAND2_RX_N

32

BI

26

OUT

B2_RX_BAL_TERM

26

OUT

C44010_RF

15PF

12

5%

16V

NP0-C0G-CERM

01005

CELL

D

C

B

R1501

BOM OPTIONS

PART#

353S3715

353S3459

DESCRIPTION

QTY

B2 PAD, TRIQUINT B2 PAD

B2 PAD, TRIQUINT B25 PAD

1

REFERENCE DESIGNATOR(S)

U44001_RF

U44001_RF

A

CRITICAL BOM OPTION

Y1

Y

B4_17

B3_13

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

R

C44014

C

L1509

L

U1501

U

FL FL1501

BAND2 PAD

Apple Inc.

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

44 OF 102

SHEET

34 OF 46

124578

SIZE

A

D

87

6 5

RX DIVERSITY

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

PP_LDO14_2P65

13 21 22 27 32

IN

1

C45001_RF

0.01UF

10%

6.3V

2

X5R

1

C45005_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

01005

CELL

4
5

6

8

D

DRX_MODE_SEL_A

25

IN

DRX_MODE_SEL_B

25

IN

DRX_MODE_SEL_C

25

IN

1

C45003_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

L45013_RF

1.4NH+/-0.1NH-0.6A-0.15OHM

50_DRX_ANT

36

IN

12

0201

CELL

50_DRX_ASM_MCH

C

R45010_RF

1

C45015_RF

1.2PF

+/-0.05PF
25V

2

C0G-CERM
0201

CELL

0

12

5%

1/20W

MF

201

CELL

1

C45004_RF

100PF

5%
16V

2

NP0-C0G
01005

CELL

50_DIVERSITY_SWITCH_MATCH

1

C45002_RF

56PF

5%
16V

2

NP0-C0G
01005

CELL

U45001_RF

B30374D5056V025

VC1

VC2

VC3

ANT

2

7109

3

VDD

LGA

OMIT

GND

1512182023

BAND17+

BAND17-

BAND5/8+

BAND5/8-

BAND2+

BAND2-

BAND1/4+
BAND1/4-

AUXBAND3

TERM

25

4 3

100_DRX_B13_B17_SW_N

1
24

22
21

17
16

14

13

19

11

50_OHM_TERM

1

R45003_RF

49.9

1%
1/20W
MF
201

2

CELL

100_DRX_B13_B17_SW_P

100_DRX_B5_B8_SW_P

100_DRX_B5_B8_SW_N

100_DRX_BAND2_SAW_OUT_P

100_DRX_BAND2_SAW_OUT_N

100_DRX_BAND1_BAND4_SAW_OUT_N

100_DRX_BAND1_BAND4_SAW_OUT_P

50_DRX_B3_OUT

12

DIVERSITY MODULE LOGIC

BAND

==================================

BAND 1/4

BAND 2

BAND 5
BAND 8

BAND 13/17

VC1

VC2 VC3

D

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

32

OUT

C

L45011_RF

100_DRX_BAND1_BAND4_SAW_OUT_P

35

IN

1

L45002_RF

4.7NH-3%-160MA

01005

CELL

2

35

IN

B

100_DRX_BAND1_BAND4_SAW_OUT_N

100_DRX_BAND2_SAW_OUT_P

35

IN

1

2

35

IN

100_DRX_BAND2_SAW_OUT_N

L45006_RF

5.1NH-3%-0.16A

01005

CELL

0.9NH+/-0.1NH-0.32A-0.6OHM

0.9NH+/-0.1NH-0.32A-0.6OHM

12

01005

CELL

L45012_RF

12

01005

CELL

C45013_RF

12PF

12

5%

16V

CERM

01005

CELL

C45014_RF

12PF

12

5%

16V

CERM

01005

CELL

100_DRX_BAND1_BAND4_P

1

L45003_RF

6.2NH-3%-140MA

01005

NOSTUFF

2

100_DRX_BAND1_BAND4_N

100_DRX_BAND2_RX_P

1

L45007_RF

4.3NH-3%-180MA

01005

NOSTUFF

2

100_DRX_BAND2_RX_N

26

OUT

26

OUT

26

OUT

26

OUT

100_DRX_B5_B8_SW_P

35

IN

35

IN

100_DRX_B5_B8_SW_N

35

IN

35

IN

100_DRX_B13_B17_SW_N

100_DRX_B13_B17_SW_P

A

BOM OPTIONS

PART#

353S3538

353S3537

6 3

R45006_RF

0.00

12

0%

1/32W

MF

01005

CELL

R45007_RF

0.00

12

0%

1/32W

MF

01005

CELL

R45004_RF

12

R45005_RF

12

DESCRIPTION

QTY

EPCOS B17 DIVERSITY MODULE

1

EPCOS B13/BC10 DIV. MODULE

1

100_DRX_B5_B8_SW_MATCH_P

100_DRX_B5_B8_SW_MATCH_N

0.00

0%

1/32W

MF

01005

CELL

0.00

100_DRX_B13_B17_MATCH_N

0%

1/32W

MF

01005

CELL

2

L45004_RF

01005

12NH-5NH%-140MA

NOSTUFF
SIGNAL_MODEL=EMPTY

1

1

L45009_RF

15NH-3%-140MA

01005

CELL

2

REFERENCE DESIGNATOR(S)

U45001_RF

U45001_RF

R45008_RF

0.00

12

0%

1/32W

MF

01005

CELL

R45009_RF

0.00

12

0%

1/32W

MF

01005

CELL

L45008_RF

7.5NH-5NH%-140MA

01005

CELL

L45010_RF

7.5NH-5NH%-140MA

01005

CELL

CRITICAL BOM OPTION

Y

Y

B4_17

B3_13

100_DRX_BAND5_BAND8_P

1

L45005_RF
15NH-3%-140MA

01005

CELL

2

100_DRX_BAND5_BAND8_N

21

21

100_DRX_BAND13_BAND17_N

26

OUT

26

OUT

B

100_DRX_BAND13_BAND17_P100_DRX_B13_B17_MATCH_P

PAGE TITLE

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

26

OUT

26

OUT

RX DIVERSITY

Apple Inc.

R

R1603

R

C1616

C

L1610

L

U1601

U

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

45 OF 102

SHEET

35 OF 46

SIZE

A

D

124578

8 7

GPS

6 5 4 3

12

PRIMARY ANTENNA

D

GPS & SECONDARY ANTENNA

J46004_RF

MM4829-2702

F-ST-SM

423

CELL

1

50_GPS_DIV_ANT_TEST_COAX

C

L46024_RF

50_GPS_DIV_SW_CONN 50_GPS_DIV_TRI_ANT

36

B

1.5NH+/-0.1NH-600MA

1

L46003_RF

10NH-3%-250MA

0201

NOSTUFF

2

0201

CELL

J46002_RF

MM5829-2700

F-ST-SM

1

423

CELL

27NH-3%-0.140A-2.3OHM

R46007_RF

0

1 2

5%

1/20W

MF

201

CELL

1

C46025_RF

1.5PF

+/-0.1PF
25V

2

C0G-CERM
0201

CELL

FL46001_RF

SASLE1G58AA0F57

21

1

L46004_RF

10NH-3%-250MA

0201

NOSTUFF

2

ANT

LGA

GPS/GNSS

GND

72458

PLACE CLOSE TO ANTENNA CONNECTOR

C46026_RF

1

L46022_RF

0201

CELL

2

50_GPS_DIV_ANT_MCH

1

L46002_RF

10NH-3%-250MA

0201

NOSTUFF

2

L46010_RF

8.2NH+/-3%-0.25A-0.7OHM

1

HB/LB

9

50_GPS_FILT1

36

CELL

C46013_RF

27PF

1 2

5%

25V

NP0-C0G

0201

CELL

5.0PF

1 2

+/-0.05PF

25V

C0G-CERM

0201

CELL

0201

CELL

50_GPS_FILT3

1

L46023_RF

47NH-100MA

0201

NOSTUFF

2

21

50_GPS_FILT2

50_PRI_ANT50_PRI_ANT_TEST_COAX

J46003_RF

MM8930-2600B

F-RT-SM

GND

5

6

0201

1 2

25V
C0G
201

1

CR

3

4

CELL

21

CELL

50_GPS_FILT4

CELL

2

L46016_RF

4.7NH-3%-0.35A

C46022_RF

0.75PF

+/-0.1PF

1

L46017_RF

12NH+/-3%-0.25A-0.7OHM

0201

CELL

2

1

C46021_RF

2.9PF

+/-0.05PF
25V

2

C0G-CERM
0201

CELL

1

L46027_RF

4.7NH-3%-0.35A

0201

NOSTUFF

2

50_WIFI_NOTCH

1

C46029_RF

0.75PF

+/-0.1PF
25V

2

C0G
201

NOSTUFF

50_GPS_DIV_SW_CONN

1

L46026_RF

4.7NH-3%-0.35A

0201

NOSTUFF

2

50_WIFI_NOTCH2

1

C46028_RF

0.75PF

+/-0.1PF
25V

2

C0G
201

NOSTUFF

C46030_RF

27PF

1 2

1%

25V

NP0-C0G

201

CELL

32

BI

C46020_RF

15PF

5%
16V

NP0-C0G-CERM

01005

CELL

C46027_RF

27PF

50_GPS_MCH

1 2

1%

25V

NP0-C0G

201

CELL

1

L46019_RF

27NH-3%-0.140A-2.3OHM

0201

CELL

2

PP_LDO5_GPS_LNA_2V5_FILT

1

R46005_RF

4.7K

1

1%
1/32W
MF

2

01005

2

CELL

GPS_LNA_BIAS

50_GPS_LNA_IN

1

1

2

GPS_LNA_VDD

674

VDD

VSD

U46001_RF

MGA300G

UDFN

RFIN

NC

GND

2

3

L46028_RF

22-OHM-25%-0.18A-0.9DCR

1

C46023_RF

10PF

5%
16V

2

CERM
01005

CELL

L46018_RF

4.7NH-3%-160MA

01005

CELL

5

50_GPS_LNA_OUT

THRM

PAD

RFOUT

CELL

01005

C46007_RF

PP_LDO5_GPS_LNA_2V5

21

CELL

56PF

1 2

50_GPS_FILT_IN

5%

16V

NP0-C0G

01005

CELL

22

SAFFB1G58FA0F57

1

FL46002_RF

LLP

IN

GND

2

D

C

PLACE THIS STUFF CLOSE TO U2

L46006_RF

100_GPS_FILT_OUT_P

3

OUT1

4

OUT2

5

CELL

1

2

100_GPS_FILT_OUT_N

10NH-3%-140MA

L46013_RF

1.0NH+/-0.1NH-0.22A-0.9OHM

01005

NOSTUFF

L46009_RF

10NH-3%-140MA

01005

CELL

01005

CELL

21

21

100_GPS_IN_P

1

L46007_RF

1.0NH+/-0.1NH-0.22A-0.9OHM

01005

NOSTUFF

2

100_GPS_IN_N

OUT

26

OUT

26

B

R46008_RF

0

50_TRI_DIV_RX

1

L46020_RF

10NH-3%-250MA

0201

NOSTUFF

2

1 2

5%

1/20W

MF

201

CELL

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

6 3

50_DRX_ANT

1

L46021_RF

10NH-3%-250MA

0201

NOSTUFF

2

35

OUT

R46007

R
C

C46030

L

L46027
U46001

U

SIZE

A

D

PAGE TITLE

GPS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

46 OF 102

SHEET

36 OF 46

124578

87

6 5

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

4 3

12

WLAN/BT

D

C

B

32K INTERFACE TO AP

XW47001_WIFI

SHORT-01005

21 37

CLK32K_AP

12

2.5UH-30%-0.7A-0.24OHM

1

2

WLAN_CLK32K

WLAN_BUCK_OUT

21 37

21

0603

L47011_WIFI

C47009_WIFI

4.7UF

20%

6.3V
X5R-CERM1
402

IN

IN

21

21

IN

WLAN_REG_ON

BT_REG_ON

21 37

21 37

PP_WLAN_MAIN_VCC

WLAN_SR_VLX1

50_HSIC_WLAN_DATA
50_HSIC_WLAN_STROBE

XW47002_WIFI

SHORT-0201

12

NOSTUFF

1

R47005_WIFI

10K

5%
1/32W
MF
01005

2

1

R47009_WIFI

10K

1%
1/32W
MF
01005

2

1

C47001_WIFI

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

R47007_WIFI

10K

1%
1/32W
MF
01005

2

37

GPIO_6

JTAG_SEL

RF_SW_CTRL_3 NC

32

6

29

31

30

14

28

24
25

40

NC

J47001_WIFI

MM4829-2702

J47002_WIFI

MM4829-2702

1

C47002_WIFI

27PF

5%
16V

2

NP0-C0G
01005

CLK32K_AP

GPIO_6

VIN_1P2LDO

WL_REG_ON

BT_REG_ON

JTAG_SEL

SR_VLX

WLAN_HSIC_DATA

WLAN_HSIC_STROBE

RF_SW_CTRL_3

18

19

17

F-ST-SM

1

423

F-ST-SM

1

423

PP_BATT_VCC_WLAN

15

VDDIO_1P8V

U47001_WIFI

LBEE5ZHTWC501

GND

1

1623222120

26

33

50_WIFI_ANT_2_4G

50_WIFI_ANT_5G

274647

BATT_VCC

VBATT_RF_VCC

LGA

41

43

4445484950

1.3NH+/-0.1NH-600MA

1.3NH+/-0.1NH-600MA

VBATT_RF_VCC

51

53

L47012_WIFI

0201

L47013_WIFI

0201

C47018_WIFI

PP_WLAN_VDDIO_1V8

1

C47003_WIFI

0.01UF

10%

6.3V

2

X5R
01005

2G_ANT

5G_ANT

HOST_WAKE_BT

BT_WAKE

BT_UART_RXD
BT_UART_TXD

BT_UART_RTS*

BT_UART_CTS*

BT_PCM_CLK

BT_PCM_SYNC

BT_PCM_OUT

BT_PCM_IN

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_12

THRML_PAD

60595857565554

21

C47017_WIFI

21

50_WIFI_ANT_FD_5G_1

1

C47004_WIFI

27PF

5%
16V

2

NP0-C0G
01005

42

52

34

39

38

37

35
36

3
5

2
4

9

WLAN_HOST_WAKE

8

AP_HSIC3_RDY

10

WLAN_HSIC3_RESUME

12

AGG_CHANNEL

7

WLAN_UART_RXD

11

WLAN_UART_TXD

13

HSIC_DEVICE_RDY

50_WIFI_ANT_FD_2_4G_1

1

0.2PF

+/-0.05PF
25V

2

COG-CERM
0201

1

0.2PF

+/-0.05PF
25V

2

COG-CERM
0201

R47008_WIFI

0.00

12

0%

1/32W

MF

01005

BT_HOST_WAKE

BT_WAKE

BT_UART_RXD
BT_UART_TXD

BT_UART_RTS_L

BT_UART_CTS_L

BT_PCM_CLK
BT_PCM_SYNC

BT_PCM_OUT

BT_PCM_IN

HSIC_DEVICE_RDY

C47015_WIFI

12PF

12

5%

25V

NP0-C0G

0201

C47016_WIFI

12PF

12

5%

25V

NP0-C0G

0201

PP_WL_BT_VDDIO_AP

50_WLAN_G

50_WLAN_A

21 37

37

21 37

IN

21 37

OUT

37

OUT

50_WIFI_ANT_FD_2_4G_2

50_WIFI_ANT_FD_5G_2

21 37

21

OUT

21

IN

21

IN

21

OUT

21

OUT

21

IN

21

BI

21

BI

21

OUT

21

IN

21 37

OUT

37

21

IN

1

R47011_WIFI

10K

1%
1/32W

PULL DOWN RESISTORS

MF
01005

2

NOSTUFF

WIFI_SPDT_VC1

37

WIFI_SPDT_VC2

37

C47014_WIFI

0.2PF

+/-0.1PF

COG-CERM

NOSTUFF

1

3

6

4

1

25V

2

201

U47005_WIFI

UPG2185T6R

TSSON

OUTPUT1

OUTPUT2

VCONT1

VCONT2

GND

C47007_WIFI

0.6NH+/-0.1NH-0.85A

GPIO_6

37

WIFI_SPDT_VC1

37

5

INPUT

2

20PF

12

5%
25V
C0H

0201

L47014_WIFI

0201

C47012_WIFI

12PF

50_WLAN_G_1

PP_WL_BT_VDDIO_AP

52

VCC

SOT891

1Y*

06

GND

12

5%

25V

NP0-C0G

0201

50_WLAN_A_DIPLX

6

WIFI_SPDT_VC1

37

WIFI_SPDT_VC2

37

50_WIFI_SPDT_IN

21

U47006_WIFI

74LVC2G06

1

1A

34

2A 2Y*

50_WIFI_SPDT_DCB

1

L47015_WIFI

6.8NH-3%-0.3A

0201

NOSTUFF

2

37

21

1

C47013_WIFI

0.01UF

10%

6.3V

2

X5R
01005

R47016_WIFI

100K

1/32W

01005

U47004_WIFI

DPX205850DT-9038A1SJ

5

COM

=PP3V0_S2R_WLAN

39

1

1

R47017_WIFI

1%

100K

1%

MF

1/32W

2

MF
01005

2

GND

SM

HI

LO

246

1

C47020_WIFI

0.01UF
10%

6.3V

2

X5R
01005

NOSTUFF

D

1

3

C

B

GPIO6 SDIO_DATA<1> SDIO_DATA<2> MODE DEFAULT ARM STATE
0 X X SDIO IN RESET

1 X 0 GSPI IN RESET

1 0 1 HSIC OUT OF RESET

1 1 1 BOOTLESS HSIC IN RESET

R47015_WIFI

0.00

AGG_CHANNEL

PP_WL_BT_VDDIO_AP

21 37

IN

1

R47013_WIFI

10K

1%
1/32W
MF
01005

HSIC_DEVICE_RDY

37

A

21 37

IN

R47012_WIFI

WLAN_REG_ON

1.00M

12

1%

1/32W

MF

01005

WLAN_REG_ON_RC

2

1

C47010_WIFI

0.22UF

20%

6.3V

2

X5R
0201

2

1

B

5

NC

U47002_WIFI

74AUP1G08GF

63

SOT891

VCC

4

YA

GND

DEV_HSIC3_RDY

21 37

37

ALTERNATES

PART NUMBER

311S0548 311S0398

339S0175 339S0171

339S0185

ALTERNATE FOR
PART NUMBER

339S0171

12

0%

1/32W

MF

01005

BOM OPTION

WLAN_TX_BLANK

REF DES

U47002_WIFI

U47001_WIFI

U47001_WIFI

25

OUT

COMMENTS:

WIFI MODULE - USI

WIFI MODULE - TDK

CLK32K_AP

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

21 37

WLAN_REG_ON

21 37

WLAN_HOST_WAKE

21 37

AP_HSIC3_RDY

21 37

DEV_HSIC3_RDY

21

37

WLAN_UART_RXD

21 37

WLAN_UART_TXD

21 37

GPIO_6

37

WLAN_HSIC3_RESUME

21 37

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

PP47001_RF

SM

P4MM

PP47002_RF

SM

P4MM

PP47003_RF

SM

P4MM

PP47004_RF

SM

P4MM

PP47005_RF

SM

P4MM

PP47006_RF

SM

P4MM

PP47007_RF

SM

P4MM

PP47008_RF

SM

P4MM

PP47009_RF

SM

P4MM

6 3

J47003_RF

MM4829-2702

F-ST-SM

J47004_RF

MM4829-2702

F-ST-SM

50_HSIC_WLAN_DATA

1

423

NOSTUFF

50_HSIC_WLAN_STROBE

1

423

NOSTUFF

21 37

21 37

PAGE TITLE

WIFI/BT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

RJR47015

C47012

LCL1801

U47005

U

J47002

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

47 OF 102

SHEET

37 OF 46

124578

SIZE

A

D

87

6 5

MOSFET

CHANNEL

RDS(ON)

IMAX

VGS MAX

D

NOSTUFF

J5700

SPKR_R_CONN_N

15 38 45

SPKR_R_CONN_P

15 38 45

CONN_DET_L

38

CONN_DP2_N

38 44

PPVBUS_CONN

38

CONN_DP1_N

38 44

SPKR_L_CONN_N

15 38 45

SPKR_L_CONN_P

15 38 45

MLB-X123

HB-SM

1

3
5

7

9
11

13

15
17

19

21
23

25
27

29

31

VOLTAGE=20V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM
NET_SPACING_TYPE=PWR

DZ5700

27V-100PF

0402

MAX_NECK_LENGTH=3 MM

1

C5700

27PF

1%
25V

2

NP0-C0G
201

2
4

6

8
10

12

14
16

18
20

22

24
26

28

30
32

SPKR_R_CONN_N

SPKR_R_CONN_P

CONN_ACC2

CONN_DP2_P

PPVBUS_CONN

CONN_ACC1

CONN_DP1_P

SPKR_L_CONN_N

SPKR_L_CONN_P

15 38 45

15 38 45

38

38 44

38

38

38 44

15 38 45

15 38 45

PPVBUS_CONN

38

2

1

L5700

FERR-70-OHM-4A

C5701

0.01UF

10%
25V
X7R
402

0603

1

2

VOLTAGE=20V
MIN_LINE_WIDTH=4.1MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

21

1

R5700

100K

1%
1/20W
MF
201

2

1

C5702

27PF

1%
25V

2

NP0-C0G
201

C

=PPVCC_MAIN_DOCK

NOTE: SPKR_L_CONN_N AND SPKR_L_CONN_P WERE SWAPPED ON 5/22/12 PER RADAR #11526818

CONN_DET_L

38

39

CRITICAL

C

DZ5702

14.2V-6PF

0201-1

A

1

C5704

6.8PF

+/-0.25PF
25V

2

CERM
201

1

R5705

100K

1%
1/32W
MF
01005

2

R5706

10K

12

1%

1/32W

MF

01005

CRITICAL

K

DZ5710

SM-201

DSF01S30SC

A

4 3

NOSTUFF

1

R5701

3215

S

D

470K

5%
1/20W
MF
201

2

G

4

R5702

220K

1/20W

201

10

PPVBUS_PROT

KA

VBUS_PROT_G

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=ANLG

1

1%

MF

2

FDMC6676BZ

P-TYPE

27 MOHM @-4.5V

6.9 A

+/- 25V

PPVBUS_EMI

1

C5703

6.8PF

+/-0.25PF
25V

2

CERM
201

CRITICAL

FDMC6676BZ

Q5700

MLP3.3X3.3

PPVBUS REVERSE VOLTAGE PROTECTION

PMU_ACC_DET_A_L

MAKE_BASE=TRUE

TS_CON_DET_L

42

OUT

10

OUT

PRELIMINARY - PENDING SIMULATIONS WITH TRISTAR

VOLTAGE=20V
MIN_LINE_WIDTH=4.1MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

DZ5701

BZT52C10LP

LLP

CRITICAL

NOTE: 10V ZENER

OVP_SW_EN_L

10

IN

CONN_DP1_P

38 44

CONN_DP1_N

38 44

CRITICAL

1

C5750

0.47UF

10%
25V

2

X5R
0402-1

CRITICAL

FDMC6676BZ

MLP3.3X3.3

3

S

2
1

1

R5703

470K

5%
1/20W
MF
201

2

OVP_SW_EN_R_L

A1

A2B1B2

Q5701

D

5

G

4

1

R5704

4.7K

5%
1/16W
MF-LF
402

2

L5703

90-OHM-50MA

TCM0605-1

SYM_VER-1

1

D5700

USBULC6-2F3K

BGA

CRITICAL

VOLTAGE=20V
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

NOSTUFF

1

R5760

4.7K

5%
1/20W
MF
201

2

4

32

12

PPVBUS_PMU

TS_E75_DPAIR1_P

TS_E75_DPAIR1_N

OUT

10 44

10

41

D

C

44

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

CONN_ACC1

B

38

CONN_ACC2

38

CRITICAL

C

DZ5703

14.2V-6PF

0201-1

A

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

CRITICAL

C

DZ5704

14.2V-6PF

0201-1

A

1

C5705

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

1

C5707

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

FERR-22-OHM-1A-0.065-OHM

FERR-22-OHM-1A-0.065-OHM

A

L5701

0201

0.055 OHM DCR

L5702

0201

0.055 OHM DCR

21

21

TS_ACC1

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

TS_ACC2

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

CONN_DP2_P

10

10

38 44

CONN_DP2_N

38 44

A1

A2B1B2

SYNC_MASTER=N/A

PAGE TITLE

D5701

USBULC6-2F3K

BGA

CRITICAL

IO FLEX: DOCK COMPONENTS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

L5704

90-OHM-50MA

TCM0605-1

SYM_VER-1

1

Apple Inc.

R

4

32

TS_E75_DPAIR2_P

TS_E75_DPAIR2_N

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-9374

REVISION

BRANCH

PAGE

57 OF 102

SHEET

38 OF 46

10 44

10 44

13.0.0

SIZE

B

A

D

124578

87

6 5

POWER CONN / ALIAS

4 3

12

LDO RAILS

PROGRAMMABLE ON/OFF

PP1V2_CPU

39 41

PP3V0_SPARE1

LDO1

D

LDO2

LDO3

LDO4

LDO5

C

LDO6

LDO7

LDO8

LDO9

LDO10

B

LDO11

LDO12

41

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V7_VA_VCP

15 41

MAKE_BASE=TRUE

VOLTAGE=1.7V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_S2R_TRISTAR

41

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_SENSOR

41

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V2_SPARE2

41

MAKE_BASE=TRUE

VOLTAGE=3.2V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V3_ACC

41 10

MAKE_BASE=TRUE

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V8_CAM

41

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_S2R_HALL

41 12

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V2_CAM

41 20

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP2V8_CAM_AF

41 20

MAKE_BASE=TRUE

VOLTAGE=2.8V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP2V8_CAM

41

MAKE_BASE=TRUE

VOLTAGE=2.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V0

39 41

MAKE_BASE=TRUE

VOLTAGE=1.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

=PP3V0_SPARE1

=PP1V7_VA_VCP

=PP3V0_S2R_TRISTAR
=PP3V0_S2R_WLAN

=PP3V0_SENSOR_ACCEL
=PP3V0_SENSOR_GYRO
=PP3V0_SENSOR_COMPASS
=PP3V0_SENSOR_PROX
=PP3V0_MLC_RST_LEVELSHIFTER
=PP3V0_ALS

=PP3V2_SPARE2

=PP3V3_ACC

=PP1V8_CAM_BACKUP

=PP3V0_S2R_HALL

=PP1V2_CAM_REAR

=PP2V8_CAM_REAR_AF

=PP2V8_CAM_FRONT
=PP2V8_CAM_REAR

=PP1V0_PLL_H4
=PP1V0_MIPI_H4
=PP1V0_DPORT_H4
=PP1V0_USB_H4
=PP1V0_MIPI_PLL_H4

14

14 15

10

37

18

18

18

19

17

17

20

3

6

6

3

6

4

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP1V2_SOC

39 41

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP1V8_S2R

39 41

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V8

39

41

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

BUCK3 - WDIG_SW

PP1V8_GRAPE

41 12

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V2_S2R

39 41

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP1V2

39 41

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP3V3_OUT

39 41

MAKE_BASE=TRUE

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

A

PP1V8_ALWAYS

41

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

=PP1V8_ALWAYS

4

BUCK RAILS

=PPVDD_CPU_H4

=PPVDD_SOC_H4

=PP1V8_S2R_H4
=PP1V8_S2R_WL
=PP1V8_S2R_TRISTAR
=PP1V8_S2R_MISC
=PP1V8_S2R_GRAPE
=PP1V8_S2R_4_NAND

=PP1V8_AUDIO
=PP1V8_H4
=PP1V8_VDDIO18_H4
=PP1V8_MIPI_H4
=PP1V8_DPORT_H4
=PP1V8_IO_H4
=PP1V8_NAND_H4
=PP1V8_PVDDP_H4
=PP1V8_USB_H4
=PP1V8_VDDIOD3_H4
=PP1V8_4_NAND
=PP1V8_CAM_REAR
=PP1V8_CAM_FRONT
=PP1V8_ACCEL
=PP1V8_GYRO
=PP1V8_COMPASS
=PP1V8_PROX
=PP1V8_DMIC
=PP1V8_MISC
=PP1V8_DMIC

=PP1V8_GRAPE

=PP1V2_S2R_H4

=PP1V2_VDDQ_H4
=PP1V2_VDDIOD_H4
=PP1V2_HSIC_H4

=PP3V3_NAND
=PP3V3_USB_H4

=PP3V3_MLC_HI

7

21

10

4 9

12

39

14

3 4 6

7

6

6

4 6 8

5 8

3

3

8

39

20

17

18

18

18

19

13 39

39

13

=PP1V8_S2R_4_NAND

39

PPVCC_MAIN

41 42

8

8

10

9

PPLED_OUT

42 16

MAKE_BASE=TRUE

VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

GND

MAKE_BASE=TRUE

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.10MM
NET_SPACING_TYPE=GND

MAX_NECK_LENGTH=5 MM

=PPLED_REG

NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

VOLTAGE=4.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PPBATT_VCC

41

MAKE_BASE=TRUE

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=1.7 MM

PP5V25_GRAPE

42

MAKE_BASE=TRUE

VOLTAGE=5.25V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=6 MM

DESENSE CAPS

PP3V3_OUT

PP1V0

39 41

1

2

PP1V2

39

7

7

7

3

11

3 8

39 41

PP1V8

39 41

PP1V2_S2R

39 41

1

2

1

2

1

2

C7300

27PF

5%
16V
NP0-C0G
01005

C7304

27PF

5%
16V
NP0-C0G
01005

C7308

27PF

5%
16V
NP0-C0G
01005

C7312

27PF

5%
16V
NP0-C0G
01005

1

2

1

2

1

2

1

2

C7301

27PF

5%
16V
NP0-C0G
01005

C7305

27PF

5%
16V
NP0-C0G
01005

C7309

27PF

5%
16V
NP0-C0G
01005

C7313

27PF

5%
16V
NP0-C0G
01005

1

2

1

2

1

2

1

2

C7302

27PF

5%
16V
NP0-C0G
01005

C7306

27PF

5%
16V
NP0-C0G
01005

C7310

27PF

5%
16V
NP0-C0G
01005

C7314

27PF

5%
16V
NP0-C0G
01005

1

2

1

2

1

2

1

2

C7303

27PF

5%
16V
NP0-C0G
01005

C7307

27PF

5%
16V
NP0-C0G
01005

C7311

27PF

5%
16V
NP0-C0G
01005

C7315

27PF

5%
16V
NP0-C0G
01005

=PP1V8_4_NAND

39

CRITICAL

U7300

TPS22924X

CSP

1

2

C7380

CRITICAL

10UF

20%

6.3V
CERM-X5R
0402-2

=PP1V8_MISC

39

1

2

C7350

0.01UF

10%

6.3V
X5R
01005

A2

VIN

B2

C2

ON

GND

A1

VOUT

B1

C1

39 41

PP1V2_SOC

39 41

PP1V2_CPU

39 41

PP1V8_S2R

39 41

PP1V8_NAND_LS

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

C7320

27PF

5%
16V

2

NP0-C0G
01005

1

C7324

27PF

5%
16V

2

NP0-C0G
01005

1

C7328

27PF

5%
16V

2

NP0-C0G
01005

1

C7316

27PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

R7300

0

12

5%

1/20W

MF

201

R7301

0

12

5%

1/20W

MF

201

1

C7321

27PF

5%
16V

2

NP0-C0G
01005

1

C7325

27PF

5%
16V

2

NP0-C0G
01005

1

C7329

27PF

5%
16V

2

NP0-C0G
01005

1

C7317

27PF

5%
16V

2

NP0-C0G
01005

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

SYNC_MASTER=N/A

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

CHARGER MAIN

BATTERY

BOOST->LDOS

C7322

27PF

5%
16V
NP0-C0G
01005

C7326

27PF

5%
16V
NP0-C0G
01005

C7330

27PF

5%
16V
NP0-C0G
01005

C7318

27PF

5%
16V
NP0-C0G
01005

MAKE_BASE=TRUE

1

2

1

2

1

2

1

2

R

1

2

1

2

1

2

1

2

PP1V8_NAND

=PPVCC_MAIN_AUDIO

=PPVCC_MAIN_DOCK
=PPVCC_MAIN_LED
=PPVCC_MAIN_LCD
=PPVCC_MAIN_ACC_SW
=PPVCC_MAIN_GRAPE

=BATT_POS_CONN
=PPBATT_VCC_RF
=PPBATT_VCC_WL

=PP5V25_GRAPE

C7323

27PF

5%
16V
NP0-C0G
01005

C7327

27PF

5%
16V
NP0-C0G
01005

C7331

27PF

5%
16V
NP0-C0G
01005

C7319

27PF

5%
16V
NP0-C0G
01005

=PP1V8_NAND

11

Power: Aliases

Apple Inc.

14 15

38

42

16

10

12

40

21

21

12

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

73 OF 102

SHEET

39 OF 46

124578

SIZE

D

C

B

A

D

87

6 5

4 3

12

D

XW7520

SM

BATT_SNS

41

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

=BATT_POS_CONN

39 40

240-OHM-0.2A-0.8-OHM

UART5_BATT_RTXD

4

42 44

40 42

BI

BI

BOM OPTION

BATTERY_NTC

NET_SPACING_TYPE=ANLG

REF DES

C

PART NUMBER

155S0644

FL7500,L1700,L1701,L1702,L1800,L1920,L2600,L2601,L2602,L2700,L2701,L2702,L2800,L2900,L2901,L2902,L2903,L2960,L2961,L2962,L2963

ALTERNATE FOR
PART NUMBER

155S0274

12

FL7500

COMMENTS:

RADAR:8391945

0201

21

TABLE_ALT_HEAD

TABLE_ALT_ITEM

C7522

33PF

NP0-C0G

01005

TP7500

A

TP-P55

NOSTUFF

1

5%

16V

2

1

C7523

33PF

NP0-C0G

01005

P/N 516S0906

CRITICAL

J7500

CPB2304-0101F

F-ST-SM

13

10

BATT_SWI_CONN

40 44

C7524

1000PF

1

10%
16V

2

X7R
201

1

5%

16V

2

C7525

27PF

NP0-C0G

01005

1

5%

16V

2

C7526

4.7PF

+/-0.1PF

NP0-C0G

01005

1

16V

2

TP7501

1

A

TP-P55

NOSTUFF

TP7502

1

A

TP-P55

NOSTUFF

TP7503

1

A

TP-P55

NOSTUFF

9

21

43
65

87

12

11

14

=BATT_POS_CONN

BATT_SWI_CONN

BATTERY_NTC

39 40

40 44

40

42

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=N/A

PAGE TITLE

POWER: BATTERY CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

75 OF 102

SHEET

40 OF 46

124578

87

D

C

NOTE: FOR NO BATTERY SITUATION

PPBATT_VCC

39 41

NOSTUFF

CRITICAL

C8100

22UF

6.3V

X5R-CERM-1

CRITICAL

R8100

1/16W

20%

603

0.5

402

1%

MF

B

CRITICAL

1

C8166

150UF-0.035OHM
20%

6.3V

2

POLY-TANT

A

NOTE: CONCERNED ABOUT ESR > 20MOHM

CASE-B15G-SM

CRITICAL

1

C8195

1.0UF

20%

6.3V

2

X5R
0201-MUR

1

2

X5R-CERM-1

1

2

CRITICAL

C8190

10UF

20%

6.3V
X5R
603

CRITICAL

1

2

CRITICAL

C8101

C8154

10UF

20%

6.3V
X5R
603

PART#

343S0593

PART NUMBER

197S0392 197S0299

1

22UF

20%

6.3V
2

603

BATT_POS_RC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.5V

PPVCC_MAIN

CRITICAL

C8191

150UF-0.035OHM

20%

6.3V
POLY-TANT
CASE-B15G-SM

PPVCC_MAIN

CRITICAL

1

C8155

10UF

20%

6.3V

2

X5R
603

DESCRIPTION

QTY

IC,PMU,ALISON,D1946A5,OTPXX,UFBGA292

1

ALTERNATE FOR
PART NUMBER

PPVBUS_PMU

38

CRITICAL

2.2UF

X5R-CERM

39 41 42

39 41 42

C8124

1

10%
25V

2

805

PP1V8_S2R

39 41

BOM OPTION

41 42

CRITICAL

1

C8135

1UF

10%

6.3V

2

CERM
402

REFERENCE DESIGNATOR(S)

U8100

REF DES

COMMENTS:

Y8138

ALT FOUNDRY

PPVCC_MAIN

39

4

G

PPBATT_VCC

39 41

3

LAYOUT NOTE: PLACE
RIGHT AT THE PIN

CRITICAL

1

C8129

1UF

10%

6.3V

2

CERM
402

ACT_DIO

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=ANLG

PPVBUS_USB

VOLTAGE=6V
MIN_LINE_WIDTH=0.085MM
MIN_NECK_WIDTH=0.085MM

1253

D

RDSON=0.0136@VGS=-2.5V
ID=12.0A

XW8114

12

NOSTUFF

(PLACE ONE 1UF CAP AT EACH VDD INPUT)

CRITICAL

1

2

C8156

10UF

20%

6.3V
CERM-X5R
0402-2

CRITICAL

1

C8157

10UF

20%

6.3V

2

CERM-X5R
0402-2

CRITICAL

1

C8158

10UF

20%

6.3V

2

CERM-X5R
0402-2

CRITICAL

1

C8159

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8160

10UF

20%

6.3V

2

CERM-X5R
0402-2

6 5

CRITICAL BOM OPTION

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL

L8112

2.2UH-3.5A-54M-OHM

PIME061E-SM

DCR=54MOHM MAX

PMEG4030ER

S

CRITICAL

Q8104

FDMC6683

MLP3.3X3.3

SM

1

2

PPVCC_MAIN

39 41 42

PP1V2_S2R

39 41

CRITICAL

1

C8136

1UF

10%

6.3V

2

CERM
402

CRITICAL

C8142

18PF

NP0-C0G

21

D8100

SOD-123W

CRITICAL

C8126

10UF

20%
25V
X5R-CERM
0603

CRITICAL

NET_SPACING_TYPE=CRYSTAL

32.768K-20PPM-12.5PF

PMU_XTAL

1

5%

25V

2

201

VCC_MAIN BYPASS

TOTAL CAPS = ~400UF

CRITICAL

1

2

C8161

10UF

20%

6.3V
CERM-X5R
0402-2

CRITICAL

1

C8162

10UF

20%

6.3V

2

CERM-X5R
0402-2

TABLE_5_HEAD

TABLE_5_ITEM

SW_CHGA

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

K

NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE

A

DIDT=TRUE

NET_SPACING_TYPE=ANLG

PMU_VCENTER

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V

NOSTUFF

1

C8125

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

LAYOUT NOTE: PLACE

RIGHT AT THE PIN

CRITICAL

Y8138

21

2012

CRITICAL

1

2

C8130

10UF

20%

6.3V
CERM-X5R
0402-2

1

2

CRITICAL

1

C8188

100PF

5%
25V

2

CERM
201

ALISON-A0-OTPXX

D1946A0-110-00

G24

CHG_A_LX

G25

NC_CHGB

BATT_SNS

40

PMU_EXTAL

H24

CHG_B_LX

H25

L25

VBAT

P25

IBAT_S

N17

P17

IBAT

N18
P18

P24

ACT_DIO

F24

VCENTER_A

F25

A22

VBUS_A

A23

B24

VBUS_A_OV_N

NC

J24

VCENTER_B

J25

P22

VBUS_B

P23
N22

VBUS_B_OV_N

NC

A10

VDD_BUCK0

B10

A3
B3

VDD_BUCK2

B7

B6

A17

VDD_BUCK3

A13

VDD_BUCK4

B13

E1

VDD_BUCK5

E2

G1
G2

VDD_BUCK5_BYP

H2

G22

VCC_MAIN_S

N19

P19

VCC_MAIN

N20

P20

K2

VDD_LDO1_6

L4

VDD_LDO2

N9

VDD_LDO3_5_8

N4

VDD_LDO4_7

N10

VDD_LDO9

N6

VDD_LDO10

L2

VDD_LDO11

N7

VDD_LDO12

P1

XTAL1

P2

XTAL2

NET_SPACING_TYPE=CRYSTAL

CRITICAL

1

C8143

18PF

5%
25V

2

NP0-C0G
201

(DISTRIBUTED AND NO DE-RATING)

PPVCC_MAIN

C8132

10UF

20%

6.3V
CERM-X5R
0402-2

CRITICAL

1

C8131

1.0UF

20%

6.3V

2

X5R
0201-MUR

1

2

C8163

27PF

5%
16V
NP0-C0G
01005

CRITICAL

BUCK4_LXL

BUCK4_LXM

CRITICAL

1

C8189

100PF

5%
25V

2

CERM
201

OMIT

U8100

UFBGA

(SYM 2 OF 3)

BUCK

USB/BAT

LDO

SWITCH POWER

LDO INPUT

XTAL VCC-MAIN

39 41 42

1

C8164

4.7PF

+/-0.1PF
16V

2

NP0-C0G
01005

BUCK0_LXL

BUCK0_LXM

BUCK0_FB

BUCK2_LXL

BUCK2_LXM

BUCK2_LXR

BUCK2_FB

BUCK3_LX

BUCK3_FB

BUCK4_LXL

BUCK4_LXM

BUCK4_FB

BUCK5_LX

BUCK5_BYP

BUCK5_FB

VLDO1

VLDO2

VLDO3
VLDO4

VLDO5
VLDO6

VLDO7

VLDO8
VLDO9

VLDO10

VLDO11
VLDO12

ON_BUF

VBUCK4

CPU1V2_SW

DSP_SW

VBUCK3

CPU1V8_SW

WDIG_SW

VBUCK0_SW0_G
VBUCK0_SW0_S

VPUMP

41

41

A11
A9

D9

A7
B8

A6

A4
D7

A16

D16

A14

B11
D14

F1

F2
H1

J1

J2
G4

L1
P3

P9
N5

P10

K1
P4

P8

P11
P5

M1

P6
M2

B17

A18

B20

A19
A20

B19

B21

A21

B18

4 3

BUCK0_LXL

20%

402

10%

X5R
402

CRITICAL

NOSTUFF

1

C8176

2

CRITICAL

1

NOSTUFF

2

NOSTUFF

1

2

39 41

39 41

39 41

39 41

39 41

100PF

5%
25V
CERM
201

C8178

100PF

CERM
201

CRITICAL

C8180

100PF

CERM
201

39

15 39 41

39 41

39 41

39 41

39 41

1

2

1

2

5%

25V

5%

25V

41

39 41

CRITICAL

C8146

2.2UF

CRITICAL

2.2UF

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK0_LXM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK0_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

BUCK2_LXL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK2_LXM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK2_LXR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

39 41

CRITICAL

C8171

100PF

5%
25V
CERM
201

CRITICAL

C8173

100PF

5%
25V
CERM
201

1

2

CRITICAL

NOSTUFF

C8175

100PF

5%
25V
CERM
201

CRITICAL

1

NOSTUFF

C8177

100PF

2

CERM

NOSTUFF

1

CRITICAL

C8179

100PF

2

CERM
201

1

2

1

2

25V5%201

1

2

1

2

1

2

CRITICAL

C8196

220PF

10%
25V
X7R-CERM
201

CRITICAL

C8197

220PF

10%
25V
X7R-CERM
201

CRITICAL

C8198

220PF

10%
25V

X7R-CERM
201

1

2

1

2

(BYPASS RON=0.14 OHM MAX)

(150MA; 2.5-3.55V)

(100MA; 1.65-1.805V; BUCK3)

(50MA; 2.5-3.3V)

(100MA; 1.8-3.3V)

(300MA; 2.5-3.6V)
(150MA; 2.5-3.6V)

(50MA; 1.5-3.3V)

(10MA; 2.0-3.55V)
(300MA; 1.2-3.0V)

(200MA; 2.5-3.55V)

(200MA; 1.7-3.0V)
(150MA; 0.6-1.3V)

(RON=0.1 OHM MAX)
(RON=1 OHM MAX)

(RON=0.2 OHM MAX)

(RON=0.5 OHM MAX)

NC_PMU_VBUCK0_SW0_G

NC_PMU_VBUCK0_SW0_S

PMU_VPUMP

CRITICAL

0.01UF

39 41

15 39 41

39 41

39 41

39 41

39 41

39 41

39 41

39 41

39 41

39 41

39 41

39 41

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

VOLTAGE=4.6V

C8137

10%
10V

2

X5R
201

PP3V0_SPARE1
PP1V7_VA_VCP
PP3V0_S2R_TRISTAR
PP3V0_SENSOR
PP3V2_SPARE2
PP3V3_ACC
PP1V8_CAM

CRITICAL

C8150

2.2UF

10%

6.3V
X5R
402

PP3V0_S2R_HALL
PP1V2_CAM
PP2V8_CAM_AF
PP2V8_CAM
PP1V0
PP1V8_ALWAYS

CRITICAL

C8169 C8153

0.22UF

20%

6.3V
X5R

0201

PP3V0_SPARE1
PP1V7_VA_VCP
PP3V0_S2R_TRISTAR
PP3V0_SENSOR
PP3V2_SPARE2
PP3V3_ACC
PP1V8_CAM
PP3V0_S2R_HALL
PP1V2_CAM
PP2V8_CAM_AF
PP2V8_CAM
PP1V0
PP1V8_ALWAYS

LDO BYPASS

CRITICAL

1

2

1

2

C8149

2.2UF

10%

6.3V
X5R
402

CRITICAL

C8168

2.2UF

10%

6.3V
X5R
402

1

2

1

2

CRITICAL

C8148

4.7UF

X5R-CERM1

CRITICAL

C8167

2.2UF

CRITICAL

C8172

100PF

5%
25V
CERM
201

CRITICAL

C8174

100PF

5%
25V
CERM
201

5%

25V

6.3V

6.3V

6 3

CRITICAL

2.2UH-20%-1.85A-80MOHM

12

PST25201B-SM

CRITICAL

2.2UH-20%-1.85A-80MOHM

12

PST25201B-SM

12

CRITICAL

2.2UH-20%-1.85A-80MOHM

12

PST25201B-SM

CRITICAL

2.2UH-20%-1.85A-80MOHM

12

PST25201B-SM

CRITICAL

2.2UH-20%-1.85A-80MOHM

12

PST25201B-SM

BUCK3_LX

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK3_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

CRITICAL

C8145

2.2UF

10%

6.3V
X5R
402

CRITICAL

C8152

4.7UF

20%

6.3V

X5R-CERM1

402

12

CRITICAL

1

2

1

2

1

2

BUCK2_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

1

10%

6.3V
2

X5R
402

1

10%

6.3V
2

X5R
402

L8100

L8101

XW8103

SM

NOSTUFF

L8105

L8107

L8110

XW8113

SM

NOSTUFF

BUCK4_LXL

41

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK4_LXM

41

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK4_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

BUCK5_LX

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK5_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

C8138

1UF

20%

6.3V
X5R
0201

CRITICAL

C8144

10UF

20%

6.3V

CERM-X5R

0402-2

CRITICAL

C8151

1UF

10%

6.3V
CERM

402

2.2UH-20%-1.85A-80MOHM

2.2UH-20%-1.85A-80MOHM

2.2UH-20%-1.85A-80MOHM

2.2UH-20%-1.85A-80MOHM

CRITICAL

1

2

C8140

1UF

10%

6.3V
CERM
402

1

2

1

2

CRITICAL

1

C8139

1UF

10%

6.3V

2

CERM
402

CRITICAL

C8147

2.2UF

10%

6.3V
X5R
402

1

2

CRITICAL

1

C8102

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8107

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

L8115

12

PST25201B-SM

XW8117

12

NOSTUFF

CRITICAL

L8119

12

PST25201B-SM

CRITICAL

L8121

12

PST25201B-SM

XW8126

12

NOSTUFF

CRITICAL

L8128

12

PST25201B-SM

XW8132

12

SM

NOSTUFF

CRITICAL

1

2

CRITICAL

1

C8103

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8108

22UF

20%

6.3V

2

X5R-CERM-1
603

SM

SM

CRITICAL

1

C8141

1UF

10%

6.3V
CERM
402

C8199

1UF

20%

6.3V

2

X5R
0201

LAYOUT NOTE:
C8147-48,50 CAN BE FURTHER AWAY

SYNC_MASTER=N/A

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PP1V2_CPU

ADDITIONAL DISTRIBUTED
42UF (NO DE-RATING)

PP1V2_SOC

ADDITIONAL DISTRIBUTED
32UF (NO DE-RATING)

PP1V8_S2R

ADDITIONAL DISTRIBUTED
9UF (NO DE-RATING)

1

C8117

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8121

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8119

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

ADDITIONAL DISTRIBUTED:
PP1V2: 33UF (NO DE-RATING)
PP1V8: 13UF (NO DE-RATING)

1

C8118

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

PP1V2_S2R

ADDITIONAL DISTRIBUTED
8UF (NO DE-RATING)

1

C8122

10UF

20%

6.3V

2

X5R
603

CRITICAL

PP3V3_OUT

ADDITIONAL DISTRIBUTED
32UF (NO DE-RATING)

1

C8120

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

PP1V2_S2R

PP1V2

DSP_SW

PP1V8_S2R

PP1V8

PP1V8_GRAPE

Power: PMU

Apple Inc.

R

12

39

39

39 41

39 41

39

39 41

39

TP8133

1

TP

39 41

39

39

DRAWING NUMBER

051-9374

REVISION

BRANCH

PAGE

81 OF 102

SHEET

41 OF 46

124578

NOSTUFF

TP-P55

SYNC_DATE=N/A

13.0.0

SIZE

D

C

B

A

D

87

6 5

4 3

12

PPVCC_MAIN

1

R8202

220K

1%
1/20W
MF
201

2

D

GPIO_BTN_HOME_L

4

12

IN

GPIO_BTN_POWER_L

4

20

IN

GPIO_BTN_SRL_L

4

20

SM

WLED_LX

IN

PMU_ACC_DET_A_L

38

IN

USB_BRICKID

10

IN

(E75 CONN)

(BETWEEN WLED AND CHARGER)
(AP)

(PANEL)

2

CRITICAL

C8220

100PF

NP0-C0G

01005

5%

16V

CRITICAL

1

2

1

PLACE CLOSE TO PMU

RESISTOR FOR TEMP CALIBRATION

DWI NAMING RELATIVE TO AP

WLED_STRING1

16

OUT

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

WLED_STRING2

16

OUT

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

WLED_STRING3

16

OUT

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

WLED_STRING4

16

OUT

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

WLED_STRING5

16

OUT

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

WLED_STRING6

16

OUT

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

1%

1/32W

R8219

3.92K

0.1%
402
1/16W
MF

CRITICAL

R8231

1.00

12

CRITICAL

R8235

1.00

12

CRITICAL

R8240

1.00

12

PMU_GPIO_BT_REG_ON_R

42

PMU_GPIO_WLAN_REG_ON_R

42

PMU_GPIO_BB_RST_R_L

42

1

C8208

2

6.3V

01005

1

CRITICAL

10KOHM-1%-0.31MA

0201

R8216

1

C8215

100PF

5%

16V

NP0-C0G

C

01005

2

BOARD_TEMP1_N

45

2

C8221

100PF

NP0-C0G

01005

XW8200

12

NOSTUFF

PLACE CLOSE TO PMU

=PPVCC_MAIN_LED

39

CRITICAL

C8226

10UF

20%
10V
X5R
603

B

0.01UF

10%

X5R

5%

16V

SM

1

2

39

1

2

1

2

45

BOARD_TEMP2_N

PPLED_OUT

C8207

0.01UF

10%

6.3V
X5R

01005

1

CRITICAL

10KOHM-1%-0.31MA

0201

R8222

2

C8217

100PF

16V

NP0-C0G

01005

XW8201

12

SM

NOSTUFF

PLACE CLOSE TO PMU

4.7UH-3.2A

1

2

C8299

27PF

5%
16V
NP0-C0G
01005

CRITICAL

1

C8233

10UF

20%
25V

2

X5R-CERM
0603

DCR=106MOHM MAX

ADC_IN7

1

5%

2

BOARD_TEMP3_N

45

CRITICAL

L8225

PIME051E-SM

CRITICAL

1

C8231

10UF

20%
25V

2

X5R-CERM
0603

PMU_ACC_ID

1

CRITICAL

10KOHM-1%-0.31MA

0201

R8218

2

C8223

100PF

5%

16V

NP0-C0G

01005

XW8202

12

SM

NOSTUFF

PLACE CLOSE TO PMU

CRITICAL

D8228

PMEG4010BEA

21

AK

SOD-323

CRITICAL

1

C8234

1UF

10%
25V

2

X5R
402

1

2

23

BOARD_TEMP4_N

45

CRITICAL

1

C8235

1UF

10%
25V

2

X5R
402

XW8203

12

NOSTUFF

PLACE CLOSE TO PMU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

1

C8295

56PF

5%
25V

2

NP0-C0G
201

CRITICAL

1

C8232

10UF

20%
25V

2

X5R-CERM
0603

R8299

6.34K

12

CRITICAL

R8227

1.00

12

1/20W

201

1%

CRITICAL

1/20W

R8232

MF

201

1.00

12

1/20W

201

1%

CRITICAL

1/20W

R8239

MF

201

1.00

12

1/20W

201

1%

1/20W

MF

201

1

C8206

0.01UF

10%

6.3V

2

X5R
01005

01005

MF

40

4

9

10

3

10 21

4

4

10 15 44

4

10 15 44

4

44

4

44

4

44

MIN_LINE_WIDTH=0.1 MM

1%

MIN_NECK_WIDTH=0.1 MM

MF

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.1 MM

1%

MIN_NECK_WIDTH=0.1 MM

MF

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.1 MM

1%

MIN_NECK_WIDTH=0.1 MM

MF

MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

BOARD_TEMP1_P

45

45

BOARD_TEMP2_P
BOARD_TEMP3_P

45

BOARD_TEMP4_P

23 45

BATTERY_NTC

IN

PMU_TCAL

GPIO_PMU_KEEPACT

IN

PMU_SHDWN

IN

NET_SPACING_TYPE=ANLG

PMU_RESET_IN

IN

RST_SYSTEM_L

OUT

GPIO_PMU_IRQ_L

OUT

I2C0_SCL

IN

I2C0_SDA

BI

DWI_CLK

IN

DWI_DO

IN

DWI_DI

OUT

NC_FW_DET

PMU_ACC_DET_B

USB_BRICKID_R

NET_SPACING_TYPE=TEMP

NET_SPACING_TYPE=TEMP

NET_SPACING_TYPE=TEMP

NET_SPACING_TYPE=TEMP

NET_SPACING_TYPE=ANLG

(INTERNAL PULL-DOWN)

NET_SPACING_TYPE=ANLG

NET_SPACING_TYPE=ANLG

(PULLUP INSIDE H4P)

(INTERNAL PULL-DOWN)

(INTERNAL PULL-DOWN)

NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

LED_IO1_R
LED_IO2_R
LED_IO3_R
LED_IO4_R
LED_IO5_R
LED_IO6_R

PLACEMENT_NOTE=PLACE NEAR U8100.N23

R8290
R8291
R8292

CRITICAL

C8201

A

6 3

42

39 41

OMIT

U8100

ALISON-A0-OTPXX

D1946A0-110-00

UFBGA

(SYM 1 OF 3)

F22

FW_DET

BUTTON1

BUTTON2
BUTTON3

ACC_DET_A

ACC_DET_B

ACC_ID
BRICK_ID

ADC_IN7

TDEV1

TDEV2
TDEV3

TDEV4

TBAT
TCAL

KEEPACT
SHDN

RESET_IN

RESET*

IRQ*

SCL

SDA

DWI_CK
DWI_DI

DWI_DO

WLED_LX

VOUT_LED

WLED1

WLED2

WLED3

WLED4

WLED5

WLED6

(PD)

(PD)

DIGITAL INPUT

INPUTRESET

ANALOG

TEMPERATURE

WDOG

I2C & DWI

LED

BACKLIGHT

VIB

1UF

L15

L16

L17

A2

A1

K24
K22

K25

M25

M24

L22
L24

N24

N25

C24

B1

F20
D24

B25

A25

A24

F21

D22
E21

N15

P15

N23
L11

L12

N13
P13

L13

L14

1

10%
25V

2

X5R
402

I2C ADDRESS: 0111100X (0X78)

5%

1/32W

MF

01005

10K

12

12

12

01005

MF

1/32W

1%

PMU_GPIO_BT_REG_ON

10K

PMU_GPIO_WLAN_REG_ON

1.00K

PMU_GPIO_BB_RST_L

VDD_REF_A

REFERENCES

GPIO

ANALOG MUX

VDD_LCM_SW

VBOOST_LCM

LCM/GRAPE

IREF

VREF

VDD_REF

VDD_RTC

ADC_REF

GPIO1

GPIO2
GPIO3

GPIO4
GPIO5

GPIO6

GPIO7
GPIO8

GPIO9

GPIO10
GPIO11

GPIO12

GPIO13
GPIO14

GPIO15
GPIO16

GPIO17

GPIO18

AMUX_A0

AMUX_A1
AMUX_A2

AMUX_A3

AMUX_AY
AMUX_B0

AMUX_B1
AMUX_B2

AMUX_B3

AMUX_BY

VDD_LCM

LCM_LX

LCM2_EN

VLCM2

VLCM1

VLCM3

OUT

OUT

OUT

N2
N1

H22

K4
P7

N8

D11

D12
D13

D18

D19
D20

D15

D17
E20

D21

B22
B23

L18
L19

L20

K20
K21

L21

E24

E25

G21
D25

G20
H21

H20

J20
J21

K19

N21

P21

P16
N12

C25
N11

P12

L10

CRITICAL

21

21

21

CRITICAL

1

C8204

0.1UF

10%

6.3V

2

X5R
201

CRITICAL

1

PMU_IREF

NET_SPACING_TYPE=ANLG

PMU_VREF

NET_SPACING_TYPE=ANLG

PMU_VDD_REF

NET_SPACING_TYPE=ANLG

PMU_VDD_RTC

NET_SPACING_TYPE=ANLG

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.1MM

MIN_NECK_WIDTH=0.1MM

NC

PMU_CLK_32K_WLAN
PMU_GPIO_BT_REG_ON_R
PMU_GPIO_WLAN_REG_ON_R
PMU_GPIO_BB_RST_R_L
UART5_BATT_RTXD
PMU_GPIO_BT_HOST_WAKE
PMU_GPIO_WLAN_HOST_WAKE
PMU_GPIO_BB_WAKE
PMU_GPIO_CODEC_HS_IRQ_L
PMU_GPIO_CODEC_RST_L
PMU_GPIO_TRISTAR_IRQ
PMU_GPIO_HALL_IRQ_1
PMU_GPIO_HALL_IRQ_2
PMU_GPIO_HALL_IRQ_3
PMU_GPIO_HALL_IRQ_4

NC_PMU_GPIO17

NC_PMU_GPIO18

NC_PMU_AMUX_A0

NC_PMU_AMUX_A1

NC_PMU_AMUX_A2

NC_PMU_AMUX_A3

NC_PMU_AMUX_AY

NC_PMU_AMUX_B0

NC_PMU_AMUX_B1

NC_PMU_AMUX_B2

NC_PMU_AMUX_B3

NC_PMU_AMUX_BY

PPVCC_MAIN

PP6V0_LCM_HI

LCM_LX

PP6V0_LCM_VBOOST

NC_LCM2_EN

NC_VLCM2

C8236

2.2UF

20%
10V

X5R-CERM

402

39 41

42

CRITICAL

1

1

C8237

4.7UF

20%
10V

2

X5R-CERM

2

0402

LAYOUT NOTE:
MAKE TRACE PP5V25_GRAPE 50 MOHM BETWEEN PMU AND C8238

C8212

0.1UF

10%

6.3V

2

X5R
201

21

OUT

42

42

42

4

OUT

21

IN

21

IN

21

IN

14

IN

14

OUT

4

IN

12

IN

12

IN

12

IN

12

IN

(WHAT SIGNALS DO YOU WANT MEASURED?)

CRITICAL

(NOTE: 2MHZ)

(NOTE: 2MHZ)

2.2UH-1.05A-0.195OHM

MAKE_BASE=TRUE

VOLTAGE=6V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

(INTERNAL PULLDOWN; TE ENABLE)

L8229

12

VLS201612E-SM

CRITICAL

1

C8288

4.7UF

20%
10V

2

X5R-CERM
0402

1

R8203

200K

1%
1/20W
MF
201

2

PLACEMENT NOTE: PLACE NEAR PIN K4

CRITICAL

1

C8209

1UF

10%

6.3V

2

CERM
402

(1.8 PUSH-PULL)

44

(1.8_S2R PUSH-PULL)

(1.8_S2R;NO PD REQ’D PER BB TEAM)

(1.8_S2R;NO PD REQ’D PER BB TEAM)

40 44

(2.5V ALWAYS ON PU IN BMU)

(INTERNAL PD)

(INTERNAL PD)

(INTERNAL PD; CAN’T BE USED FOR 32K CLK OUTPUT)

(INTERNAL PU TO PP1V8_S2R)

10

(EXTERNAL PU)

(PLACEHOLDER)

(EXTERNAL PU)

PP5V25_GRAPE

CRITICAL

1

C8238

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C8210

0.22UF

20%

6.3V

2

X5R
0201

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BB_VBUS_DET

1

2

PLACEMENT NOTE: PLACE NEAR PIN H22

39

21

CRITICAL

C8239

1UF

10%
16V
X5R
402

PMU_ADC_REF

1

2

CRITICAL

D8230

PMEG2005AEL

AK

SOD882

MAKE_BASE=TRUE

VOLTAGE=6V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

LAYOUT NOTE:
ONE VIA PER PIN FOR
VSS_* AND VSSA_* PINS

OMIT

U8100

ALISON-A0-OTPXX

D1946A0-110-00

UFBGA

(SYM 3 OF 3)

B2

B4

C2

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

H10

H11

H12

D4

D5

D6

E4

E5

E6

E7

E8

E9

F4

F5

F6

F7

F8

F9

VSS

G5

G6

G7

G8

G9

H4

H5

H6

H7

H8

H9

CRITICAL

C8214

1000PF

10%

6.3V
X5R-CERM
01005

SYNC_MASTER=N/A

PAGE TITLE

POWER: PMU

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

VSS_BUCK02

VSS_BUCK2

VSS_BUCK04

VSS_BUCK34

VSS_BUCK5

VSSA_BUCK0
VSSA_BUCK2

VSSA_BUCK3

VSSA_BUCK4
VSSA_BUCK5

PVSS_CHG_A

PVSS_CHG_B

VSS_WLED

VSS_LCM

VSS

SYNC_DATE=05/09/2011

DRAWING NUMBER

051-9374

REVISION

BRANCH

PAGE

SHEET

124578

A8

B9

A5

B5
A12

B12
A15

B15

D1
D2

D10

D8
B16

B14

C1
E22

J22
N14

P14

N16

N3
L8

L6

K18
K16

K14
K12

K10

K8
K6

J19

J17
J15

J13

J11
J9

J7
J5

H19

H13
H14

H15

H16
H17

H18

J4
J6

J8
J10

J12

J14
J16

J18

K5
K7

K9

K11
K13

K15
K17

L5

L7
L9

13.0.0

82 OF 102

42 OF 46

SIZE

D

C

B

A

D

87

MECHANCIAL PARTS

6 5

4 3

12

PD PARTS

QTY

D

C

PART#

806-4017

806-3782

806-3715

TOP BARCODE LABEL/EEE CODES
(ONLY ONE IS USED PER BOM)

PART#

825-7639

825-7639

825-7639

825-7639

825-7639

825-7639

825-7639

825-7639

825-7639 DY63

825-7639

825-7639

DESCRIPTION

1

FENCE,MAIN,MLB,YYY

CAN,MAIN,MLB,WIFI,YYY

1

FENCE,RADIO,MLB,SWAPPED,YYY

1

DESCRIPTION

QTY

1

EEEE FOR 639-3251 (X123 ENTRY)

1

EEEE FOR 639-4129 (X123A ENTRY)

EEEE FOR 639-4130 (X123B ENTRY)

1

1

EEEE FOR 639-3923 (X123 GOOD)

EEEE FOR 639-3924 (X123 BETTER)

1

1

EEEE FOR 639-3415 (X123A GOOD)

1

EEEE FOR 639-3925 (X123A BETTER)

EEEE FOR 639-3926 (X123A BEST)

1

EEEE FOR 639-3416 (X123B GOOD)

1

EEEE FOR 639-3927 (X123B BETTER)

1

EEEE FOR 639-3928 (X123B BEST)

1

REFERENCE DESIGNATOR(S)

FENCE_MLB

CAN_WIFI

CAN_RADIO

REFERENCE DESIGNATOR(S)

DWNV

F78H

F78J

F3JV

F3JQ

DY62

F3JN

F3JP

F3JR

F3JT

BOM OPTION

CELL

CRITICAL BOM OPTION

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

EEEE_X123_ENTRY

EEEE_X123A_ENTRY

EEEE_X123B_ENTRY

EEEE_X123_BETTER

EEEE_X123_BEST

EEEE_X123A_GOOD

EEEE_X123A_BETTER

EEEE_X123A_BEST

EEEE_X123B_GOOD

EEEE_X123B_BETTER

EEEE_X123B_BEST

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PLATED THROUGH HOLES

DRILL SIZE: 1.1MM X 0.4MM
PLATING SIZE: 1.4MM X 0.7MM

SL9300

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9302

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9304

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9305

TH-NSP

1

SL-1.1X0.4-1.4X0.7

STANDOFFS: P/N 860-1542

STDOFF-3.3X1.8R1.17H-SM

STDOFF-3.3X1.8R1.17H-SM

STDOFF-3.3X1.8R1.17H-SM

STD9300

1

STD9301

1

STD9302

1

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

MECHANCIAL PARTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

93 OF 102

SHEET

43 OF 46

124578

87

6 5

4 3

12

Clock Signal Constraints

NET_PHYSICAL_TYPE

CLK_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK

ELECTRICAL_CONSTRAINT_SET

D

I63

I162

I88

I89

I95

I96

I233

I130

I131

I157

I158

NAND

NET_SPACING_TYPE1 NET_SPACING_TYPE2

NAND

ELECTRICAL_CONSTRAINT_SET

C

I50

I45

I41

I42

I43

I44

I37

I49

I51

I55

I56

I57

I58

I59

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

USB

B

A

ELECTRICAL_CONSTRAINT_SET

I5

I6

I7

I8

I82

I83

I84

I85

I186

I187

I185

I188

HSIC

NET_SPACING_TYPE1 NET_SPACING_TYPE2

HSIC

NET_PHYSICAL_TYPE

ELECTRICAL_CONSTRAINT_SET

I182

I181

I183

I184

*

*

PHYSICAL_RULE_SET

45_OHM_SE

PHYSICAL

CLK_50S
CLK_50S

CLK_50S

CLK_50S
CLK_50S

CLK_50S

CLK_50S

CLK_50S
CLK_50S

CLK_50S

CLK_50S

AREA_TYPE

NET_PHYSICAL_TYPE

NAND_50S

**

PHYSICAL

NAND_50S
NAND_50S

NAND_50S NAND

NAND_50S NAND

NAND_50S NAND

NAND_50S

NET_PHYSICAL_TYPE

USB_90D

PHYSICAL

USB_90D
USB_90D

USB_90D
USB_90D

USB_90D

USB_90D

USB_90D
USB_90D

USB_90D

USB_90D
USB_90D

USB_90D

AREA_TYPE

HSIC_50S

AREA_TYPE

*

PHYSICAL

HSIC_50S HSIC
HSIC_50S

HSIC_50S

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

*

NET_TYPE

AREA_TYPE

*

AREA_TYPE

NET_TYPE

AREA_TYPE

*

AREA_TYPE

**

NET_TYPE

*

*

NET_TYPE

SPACING_RULE_SET

SPACING

CLK
CLK

CLK

CLK
CLK

CLK

CLK

CLK
CLK

CLK

CLK

PHYSICAL_RULE_SET

SPACING_RULE_SET

SPACING

NANDNAND_50S

NAND
NAND

NANDNAND_50S

NANDNAND_50S
NANDNAND_50S

NANDNAND_50S

NAND
NANDNAND_50S

NANDNAND_50S

NANDNAND_50S

PHYSICAL_RULE_SET

90_OHM_DIFF

SPACING_RULE_SET

SPACING

USB
USB

USB
USB

USB

USB

USB
USB

USB

USB
USB

USB

PHYSICAL_RULE_SET

45_OHM_SE

SPACING_RULE_SET

SPACING

HSIC

HSIC

HSICHSIC_50S

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

AP_CLK_32K_CUMULUS
PMU_CLK_32K_WLAN

ISP0_CAM_REAR_CLK_R
ISP0_CAM_REAR_CLK
ISP1_CAM_FRONT_CLK_R
ISP1_CAM_FRONT_CLK
ISP1_CAM_FRONT_CLK_F

I2S0_CODEC_ASP_MCK
I2S0_CODEC_ASP_MCK_R
I2S1_SPKAMP_MCK
I2S1_SPKAMP_MCK_R

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

45_OHM_SE

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

FMI0_AD<7..0>
FMI0_CE0_L
FMI0_CLE
FMI0_ALE
FMI0_RE_N
FMI0_WE_L
FMI0_DQS_P

FMI1_AD<7..0>
FMI1_CE0_L
FMI1_CLE
FMI1_ALE
FMI1_RE_N
FMI1_WE_L
FMI1_DQS_P

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

SOC_USB_D_P
SOC_USB_D_N
USB_BB_D_P
USB_BB_D_N

TS_E75_DPAIR1_P
TS_E75_DPAIR1_N
TS_E75_DPAIR2_P
TS_E75_DPAIR2_N

CONN_DP1_P
CONN_DP1_N
CONN_DP2_P
CONN_DP2_N

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

HSIC1_BB_STB
HSIC1_BB_DATA
HSIC2_WLAN_STB
HSIC2_WLAN_DATA

4

21 42

6

6

6

6

17

4

4

4

4

5

5

5

5

5

5

5

5

5

5

5

5

5

5

3

3

10 21

10 21

10 38

10 38

10

10 38

38

38

38

38

3

3

3

3

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

45_OHM_SE

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

JTAG_SOC_TCK

JTAG_SOC_TMS

JTAG_SOC_TDI
JTAG_SOC_TDO
JTAG_SOC_TRST_L

BB_JTAG_TCK
BB_JTAG_TMS
BB_JTAG_TDI
BB_JTAG_TDO
BB_JTAG_TRST_L

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

45_OHM_SE

2:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

I2C0_SDA
I2C0_SCL

I2C1_SDA
I2C1_SCL
I2C2_SDA
I2C2_SCL
I2C2_SDA_F
I2C2_SCL_F

ISP0_CAM_REAR_SCL
ISP0_CAM_REAR_SDA
ISP1_CAM_FRONT_SCL
ISP1_CAM_FRONT_SDA
ISP1_CAM_FRONT_SCL_F
ISP1_CAM_FRONT_SDA_F

MLC_SDA_3V3

MLC_SCL_3V3
LVDS_DDC_DATA
LVDS_DDC_CLK

I2S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

I2S

I2S

10

3

3

10

3

3 9

3 9

4

21 24

4

21 24

4

21 24

4

21 24

4

21 24

4

10 15 42

4

10 15 42

4

18 19

4

18 19

4

17 18

4

17 18

17

17

6

20

6

20

6

17

6

17

17

17

ELECTRICAL_CONSTRAINT_SET

I140

I143

I142

I141

I159

I144

I148

I147

I146

I160

I145

I149

I150

I151

I191

I192

I194

I193

UART

NET_SPACING_TYPE1 NET_SPACING_TYPE2

UART

ELECTRICAL_CONSTRAINT_SET

I206

I208

I207

I209

I210

I211

I212

I213

I214

I215

I217

I216

I218

I219

I220

I234

*

NET_TYPE

AREA_TYPE

*

AREA_TYPE

**

NET_TYPE

PHYSICAL_RULE_SET

SPACING_RULE_SET

SPACING

JTAG

JTAG

JTAG

JTAG

JTAGJTAG_50S

JTAG

JTAG
JTAGJTAG_50S

PHYSICAL_RULE_SET

SPACING

I2C
I2C

I2C

I2C
I2C

I2C

I2C
I2C

I2C

I2C
I2C

I2C

I2C
I2C

I2C

I2C
I2C

I2C

JTAG

NET_SPACING_TYPE1 NET_SPACING_TYPE2

JTAG

NET_PHYSICAL_TYPE

JTAG_50S

**

ELECTRICAL_CONSTRAINT_SET

12

20

17

14

15

I16

I15

I14

I13

I20

I196

I197

I195

I198

I199

I2C

NET_SPACING_TYPE1 NET_SPACING_TYPE2

I2C

NET_PHYSICAL_TYPE

I2C_50S

ELECTRICAL_CONSTRAINT_SET

I202

I205

I2

I3

I4

I61

I62

I230

I229

I98

I99

I100

I101

I231

I232

I203

I204

I1

11

11

11

11

11

11

11

11

11

11

11

11

11

11

AREA_TYPE

AREA_TYPE

PHYSICAL

JTAG_50S JTAG

JTAG_50S

JTAG_50S

JTAG_50S

JTAG_50S

JTAG_50S

JTAG_50S

JTAG_50S JTAG

PHYSICAL

I2C_50S
I2C_50S

I2C_50S

I2C_50S
I2C_50S

I2C_50S

I2C_50S
I2C_50S

I2C_50S

I2C_50S
I2C_50S

I2C_50S

I2C_50S
I2C_50S

I2C_50S

I2C_50S
I2C_50S

I2C_50S

NET_PHYSICAL_TYPE

I2S_45S

*

I2S

NET_PHYSICAL_TYPE

UART_45S

UART_45S UART

UART_45S UART

UART_45S UART

UART_45S UART
UART_45S

UART_45S UART

UART_45S UART

UART_45S UART

UART_45S
UART_45S UART

I2S_45S
I2S_45S

I2S_45S

I2S_45S
I2S_45S

I2S_45S

I2S_45S

I2S_45S
I2S_45S

I2S_45S

I2S_45S
I2S_45S

I2S_45S

I2S_45S

I2S_45S
I2S_45S

I2S_45S

I2S_45S

PHYSICAL

AREA_TYPE

AREA_TYPE

PHYSICAL

AREA_TYPE

AREA_TYPE

NET_TYPE

NET_TYPE

*

*

*

*

**

I2S
I2S

I2S

I2S
I2S

I2S

I2S

I2S
I2S

I2S

I2S
I2S

I2S

I2S

I2S
I2S

I2S

I2S

SPACING

UART

UARTUART_45S
UARTUART_45S

UARTUART_45S

UARTUART_45S
UARTUART_45S

UARTUART_45S

UART

PHYSICAL_RULE_SET

SPACING_RULE_SET

SPACING

PHYSICAL_RULE_SET

SPACING_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

45_OHM_SE

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

45_OHM_SE

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

UART0_DEBUG_RXD
UART0_DEBUG_TXD

UART1_BT_RXD
UART1_BT_TXD
UART1_BT_RTS_L
UART1_BT_CTS_L

UART2_ACC_RXD
UART2_ACC_TXD

UART3_WLAN_RXD
UART3_WLAN_TXD

UART4_BB_RXD
UART4_BB_TXD
UART4_BB_RTS_L
UART4_BB_CTS_L

UART5_BATT_RTXD
BATT_SWI_CONN

I2S0_CODEC_ASP_BCLK

I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT

I2S0_CODEC_ASP_DIN

I2S0_CODEC_ASP_SDOUT

I2S1_SPKAMP_BCLK

I2S1_SPKAMP_LRCK

I2S1_SPKAMP_DOUT
I2S1_SPKAMP_DIN

I2S2_CODEC_XSP_BCLK

I2S2_CODEC_XSP_LRCK

I2S2_CODEC_XSP_DOUT
I2S2_CODEC_XSP_DIN

I2S2_CODEC_XSP_SDOUT

I2S3_BT_BCLK
I2S3_BT_LRCK

I2S3_BT_DOUT

I2S3_BT_DIN

4

10

4

10

4

21

4

21

4

21

4

21

4

10

4

10

4

21

4

21

4

10 21

4

10 21

4

21

4

21

4

40 42

40

4

14

4

14

4

14

4

14

14

4

15

4

15

4

15

4

15

4

14

4

14

4

14

4

14

14

4

21

4

21

4

21

4

21

D

C

B

10

10

NET_TYPE

*

PHYSICAL_RULE_SET

SPACING_RULE_SET

SPACING

SPI

SPI
SPI

SPI

SPI

SPI
SPI

SPI

SPI

PHYSICAL

SPI_45S

SPI_45S
SPI_45S

SPI_45S

SPI_45S

SPI_45S
SPI_45S

SPI_45S

SPI_45S

AREA_TYPE

AREA_TYPE

SPI

38

NET_SPACING_TYPE1

VREF

ELECTRICAL_CONSTRAINT_SET

I136

I137

I139

I138

DWI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DWI

21

21

21

21

ELECTRICAL_CONSTRAINT_SET

I152

I153

I156

NET_SPACING_TYPE2

**

PHYSICAL

NET_PHYSICAL_TYPE

DWI_45S

PHYSICAL

DWI_45S

DWI_45S
DWI_45S

AREA_TYPE

NET_TYPE

AREA_TYPE

*

AREA_TYPE

**

NET_TYPE

SPACING_RULE_SET

SPACING

VREF
VREF

VREF

VREF

PHYSICAL_RULE_SET

SPACING_RULE_SET

SPACING

DWI

DWI
DWI

VREF

2:1_SPACING

45_OHM_SE

2:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PPVREF_DDR0_CA
PPVREF_DDR0_DQ
PPVREF_DDR1_CA
PPVREF_DDR1_DQ

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

DWI_CLK

DWI_DI
DWI_DO

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SPI

ELECTRICAL_CONSTRAINT_SET

7

7

7

7

4

42

4

42

4

42

I221

I222

I223

I235

I224

I225

I226

I227

I228

NET_PHYSICAL_TYPE

SPI_45S

**

6 3

45_OHM_SE

2:1_SPACING

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPI1_GRAPE_MISO

SPI1_GRAPE_MOSI
SPI1_GRAPE_SCLK

SPI1_GRAPE_SCLK_R

SPI1_GRAPE_CS_L

SPI2_CODEC_MISO
SPI2_CODEC_MOSI

SPI2_CODEC_SCLK

SPI2_CODEC_CS_L

SYNC_MASTER=N/A

PAGE TITLE

4

12

4

12

4

12

12

4

12

4

14

4

14

4

14

4

14

CONSTRAINTS: ASSIGNMENTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

100 OF 102

SHEET

44 OF 46

124578

SIZE

A

D

87

6 5

4 3

12

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

90_OHM_DIFF

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

MIPI0D_DATA_P<0>
MIPI0D_DATA_N<0>
MIPI0D_DATA_P<1>
MIPI0D_DATA_N<1>
MIPI0D_DATA_P<2>
MIPI0D_DATA_N<2>
MIPI0D_DATA_P<3>
MIPI0D_DATA_N<3>
MIPI0D_CLK_P
MIPI0D_CLK_N

MIPI0C_CAM_REAR_DATA_P<0>
MIPI0C_CAM_REAR_DATA_N<0>
MIPI0C_CAM_REAR_DATA_P<1>
MIPI0C_CAM_REAR_DATA_N<1>
MIPI0C_CAM_REAR_CLK_P
MIPI0C_CAM_REAR_CLK_N
MIPI0C_CAM_REAR_DATA_FILT_P<0>
MIPI0C_CAM_REAR_DATA_FILT_N<0>
MIPI0C_CAM_REAR_DATA_FILT_P<1>
MIPI0C_CAM_REAR_DATA_FILT_N<1>
MIPI0C_CAM_REAR_CLK_FILT_P
MIPI0C_CAM_REAR_CLK_FILT_N

MIPI1C_CAM_FRONT_DATA_P<0>
MIPI1C_CAM_FRONT_DATA_N<0>
MIPI1C_CAM_FRONT_CLK_P
MIPI1C_CAM_FRONT_CLK_N
MIPI1C_CAM_FRONT_DATA_FILT_P<0>
MIPI1C_CAM_FRONT_DATA_FILT_N<0>
MIPI1C_CAM_FRONT_CLK_FILT_P
MIPI1C_CAM_FRONT_CLK_FILT_N

6

6

NET_TYPE

NET_TYPE

*

*

USB
USB

USB

USB

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO
AUDIO

AUDIO

AUDIO

PHYSICAL_RULE_SET

SPACING_RULE_SET

SPACING

DMICDMIC_45S

DMICDMIC_45S

DMICDMIC_45S
DMICDMIC_45S

SPACING_RULE_SET

SPACING

DMIC

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DMIC

NET_PHYSICAL_TYPE

DMIC_45S

**

ELECTRICAL_CONSTRAINT_SET

6

16

6

16

6

16

6

16

6

16

6

16

6

16

6

16

16

16

6

20

6

20

6

20

6

20

6

20

6

20

6

17

6

17

20

20

20

20

20

20

6

17

6

17

17

17

17

17

I375

I374

I376

I373

I406

AUDIO

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AUDIO

ELECTRICAL_CONSTRAINT_SET

I287

I288

I392

I393

I289

I290

I359

I291

I395

I394

I396

I397

*

AREA_TYPE

AREA_TYPE

PHYSICAL

DMIC_45S DMIC

AREA_TYPE

PHYSICAL

USB_90D
USB_90D

USB_90D

USB_90D

SPEAKER

SPEAKER

SPEAKER

SPEAKER

AUDIO_DIFF
AUDIO_DIFF

AUDIO_DIFF

AUDIO_DIFF

*

**

SPACING

MIPI

MIPIMIPI_90D

MIPI

MIPIMIPI_90D
MIPIMIPI_90D

MIPIMIPI_90D
MIPI

MIPIMIPI_90D

MIPIMIPI_90D
MIPI

MIPI
MIPIMIPI_90D

MIPIMIPI_90D

MIPI
MIPIMIPI_90D

MIPIMIPI_90D

MIPI
MIPIMIPI_90D

MIPIMIPI_90D

MIPIMIPI_90D

MIPIMIPI_90D
MIPI

MIPIMIPI_90D

MIPI
MIPIMIPI_90D

PHYSICAL_RULE_SET

SPACING_RULE_SET

MIPI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

NET_PHYSICAL_TYPE

MIPI_90D

AREA_TYPE

AREA_TYPE

MIPI

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

D

C

I91

I92

I93

I94

I95

I96

I271

I270

I97

I98

I311

I312

I315

I316

I341

I344

I386

I387

I388

I389

I390

I391

I345

I346

I347

I348

I382

I383

I384

I385

PHYSICAL

MIPI_90D

MIPI_90D
MIPI_90D MIPI

MIPI_90D MIPI

MIPI_90D

MIPI_90D MIPI

MIPI_90D

MIPI_90D MIPI
MIPI_90D

MIPI_90D

MIPI_90D

MIPI_90D MIPI

MIPI_90D

MIPI_90D

45_OHM_SE

2:1_SPACING

3:1_SPACING

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

L81_DMIC1_FF_SCLK

L81_DMIC1_FF_SD

DMIC1_FF_SCLK

DMIC1_FF_SD

DMIC1_FF_SCLK_CONN

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MIKEY_TS_P
MIKEY_TS_N

L81_MBUS_P
L81_MBUS_N

SPKR_L_CONN_P
SPKR_L_CONN_N

SPKR_R_CONN_P
SPKR_R_CONN_N

HP_MIC_P
HP_MIC_N

L81_AIN2_P
L81_AIN2_N

14

14

13 14

13

13

D

14

10 14

10 14

14

14

15 38

15 38

15 38

15 38

14

14

14

14

C

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

90_OHM_DIFF

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

MIPI_DATA_CONN_P<3..0>
MIPI_DATA_CONN_N<3..0>

MIPI_CLK_CONN_P
MIPI_CLK_CONN_N

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

5:1_SPACING

XTAL_SOC_24M_I
XTAL_SOC_24M_O
XTAL_SOC_24M_O_R

B

16

16

16

16

3

3

3

6 3

TEMP SENSORS

NET_PHYSICAL_TYPE

TEMP

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TEMP

ELECTRICAL_CONSTRAINT_SET

I399

I398

I400

I401

I402

I403

I404

I405

AREA_TYPE

*

TEMP_SENSE

AREA_TYPE

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_TYPE

**

SPACING

TEMP

TEMPTEMP
TEMP

TEMP

TEMP

PHYSICAL_RULE_SET

TEMP

TEMP

TEMP TEMP

TEMP

TEMP TEMP

TEMP TEMP
TEMP

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

BOARD_TEMP1_P
BOARD_TEMP1_N
BOARD_TEMP2_P
BOARD_TEMP2_N

BOARD_TEMP3_P
BOARD_TEMP3_N
BOARD_TEMP4_P
BOARD_TEMP4_N

SPACING_RULE_SET

42

42

42

42

42

42

23 42

23 42

SYNC_MASTER=N/A

PAGE TITLE

CONSTRAINTS: ASSIGNMENTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-9374

REVISION

BRANCH

PAGE

101 OF 102

SHEET

45 OF 46

124578

SYNC_DATE=N/A

13.0.0

SIZE

A

D

NET_TYPE

PHYSICAL_RULE_SET

*

SPACING_RULE_SET

*

SPACING

LVDS

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LVDS

ELECTRICAL_CONSTRAINT_SET

NET_PHYSICAL_TYPE

LVDS_90D

*

AREA_TYPE

AREA_TYPE

PHYSICAL

B

NET_TYPE

LVDSLVDS_90D

LVDSLVDS_90D

LVDSLVDS_90D

SPACING_RULE_SET

SPACING

CRYSTAL
CRYSTAL

CRYSTAL

I245

I244

I234

I235

LVDS_90D LVDS

XTAL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CRYSTAL

A

ELECTRICAL_CONSTRAINT_SET

I379

I380

I381

**

AREA_TYPE

PHYSICAL

87

MLB CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM

BOARD AREAS

NO_TYPE,BGA

6 5

TABLE_BOARD_INFO

BOARD UNITS
(MIL or MM)

ALLEGRO
VERSION

MM

16.2

4 3

12

D

PHYSICAL CONSTRAINTS

LAYER

DEFAULT

ALLOW ROUTE
ON LAYER?

*Y

*

SINGLE-ENDED PHYSICAL RULES
45 OHMS

45_OHM_SE

45_OHM_SE

LAYER

ISL2,ISL9

ISL4,ISL6

ALLOW ROUTE
ON LAYER?

45_OHM_SE

50 OHMS - CLEAR ON LAYER 2 AND 9

TOP

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

LAYER

C

50_OHM_SE

TOP,BOTTOM

50_OHM_SE

DIFFERENTIAL PAIR PHYSICAL RULES
90 OHMS

LAYER

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

ISL2,ISL9

ISL4,ISL6

90_OHM_DIFF

Y

Y

Y

N*

Y

N

Y

Y

Y

N

MINIMUM LINE WIDTH

=45_OHM_SE

=DEFAULTSTANDARD

MINIMUM LINE WIDTH

0.055 MM

0.055 MM 0.055 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.085 MM

0.085 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.052 MM 0.052 MM

0.089 MM 0.089 MM

MINIMUM NECK WIDTH

=45_OHM_SE

=DEFAULT

MINIMUM NECK WIDTH

0.053 MM0.053 MM

0.055 MM

0.085 MM

0.085 MM

0.089 MM0.089 MM

0.051 MM0.051 MM

MAXIMUM NECK LENGTH

30 MM

12.7 MM

MAXIMUM NECK LENGTH

3.0 MM

3.0 MM

3.0 MM

MAXIMUM NECK LENGTH

3.0 MM

3.0 MM

MAXIMUM NECK LENGTH

=STANDARD

=STANDARD

=STANDARD

DIFFPAIR PRIMARY GAP

0 MM 0 MM

=DEFAULT =DEFAULT

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

0.120 MM 0.120 MM

0.150 MM 0.150 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.150 MM0.150 MM

TABLE_PHYSICAL_RULE_ITEM

0.120 MM0.120 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SPACING CONSTRAINTS

DEFAULT/BGA SPACING RULES

*

LINE-TO-LINE SPACING

0.055 MM

SPACING_RULE_SET

LAYER

DEFAULT 0.08 MM

STANDARD =DEFAULT

BGA_SPA

REGULAR SPACING RULES

SPACING_RULE_SET

LAYER

1:1_SPACING

0P08_SPACING

1.5:1_SPACING

2:1_SPACING

2.5:1_SPACING

3:1_SPACING

4:1_SPACING

5:1_SPACING

0P5MM_SPACING

0P64MM_SPACING 0.64 MM

*NOTE: ASSUMING 0.060MM DIELECTRIC THICKNESS

LINE-TO-LINE SPACING

*

* ?

0.055 MM

0.080 MM

0.0825 MM

0.11 MM

*

*

0.137 MM

0.165 MM

0.22 MM

*

*

0.275 MM

0.5 MM

*

POWER/GND SPACING RULES

*

*

*

LINE-TO-LINE SPACING

0.1 MM

0.1 MM

0.2 MM

SPACING_RULE_SET

PWR_P1SPACING

GND_P1SPACING

SWITCHNODE

LAYER

WEIGHT

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

*

CLK BGA

PWR

GND

ANLG

*

*

**

**

NOTES:

0.075 MM ~ 3 MIL

0.089 MM ~ 3.5 MIL

0.102 MM ~ 4 MIL

0.114 MM ~ 4.5 MIL

0.125 MM ~ 5 MIL

0.140 MM ~ 5.5 MIL

0.15 MM ~ 6 MIL

0.18 MM ~ 7 MIL

0.2 MM ~ 8 MIL

0.25 MM ~ 10 MIL

0.3 MM ~ 12 MIL

0.33 MM ~ 13 MIL

0.4 MM ~ 16 MIL

1.0 MM = 39.37 MIL

AREA_TYPE

BGA

**

**

BGA_SPA

BGA_SPA

PWR_P1SPACING

GND_P1SPACING

SWITCHNODESWITCHNODE

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

B

D

C

B

AUDIO/MISC PHYSICAL RULES

LAYER

1:1_DIFFPAIR

SPEAKER

AUDIO_DIFF

ALLOW ROUTE
ON LAYER?

*

*Y

*Y

TEMP_SENSE

BGA AREA PHYSICAL RULES

BGA

LAYER

*

PHYSICAL_RULE_SET

BGA_PHY

ALLOW ROUTE
ON LAYER?

A

NET_PHYSICAL_TYPE

AREA_TYPE

*

BGA_PHY

Y

Y*

Y

MINIMUM LINE WIDTH

=STANDARD

0.5 MM 0.20MM

0.1 MM 0.10MM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.10MM0.1 MM

MINIMUM NECK WIDTH

0.055 MM0.055 MM

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

10 MM

10 MM

10 MM

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

0.08 MM

0.10 MM

0.10 MM

DIFFPAIR PRIMARY GAP

0.076 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

6 3

0.08 MM

0.10 MM

0.10 MM

0.08 MM0.08 MM

0.075 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SYNC_MASTER=N/A

PAGE TITLE

CONSTRAINTS: MLB RULES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9374

REVISION

13.0.0

BRANCH

PAGE

102 OF 102

SHEET

46 OF 46

124578

SIZE

A

D