Apple iPad 4th Gen Schematics

820-3249-TOP MLB

WWW.AliSaler.Com

R8297

C8154

C8194

C8155

R8296

L8111

C8125

L8110

C8111

C8112

C8126

U8100

L8104

C8104

C8105

D8100

C8124

L8112

C8237

L8229

R8222

C8152
C8149
C8147

C8148
C8144

C8143

C8142

L8109

C8109

L8255

C8226

C8292

Y8138

D8228

C8232

C8233

C8234

C8110

L8225

C8235

C8256

C8113

C8195

C8118

C8117

C8108

C5936

U5903

R5933

C8100

L8100

L8102

R5932

C8114

L8107

C8107

L8106

C8119

L8105

C8101

L8101

C8120

C8121

C8103

C8122

L8103

C8102

C8123

R5935

C1652

C1635

C1621

C1611

J7500

J2200

J6050

R2205

C3060

U3060

R3060

R3025

R0760

R3611

R3610

R3613

R3640

C3602

C3631

U3600

R3620

C3620

R3614

C3615

C3041

C3618

C3601

C3605

C3608

C3607

L3620

C3606

C3691

R3612

C3616

C3617

C3610

C3603

C3614

C3630

R3630

R3631

C3632

R3009

R3012

C3001

C3009

C3008 C3002

C3112

R3180

R3171

C3110

C3108C3106

C3192

C3191

R3173

R3190

C3107

C3105

R3160

U3010

U3009

C3050

R3032

R3030

C3030

U3007

C3031

R3031

C3101

R3033

R3155

C3102

R3181

U3000

R3101

C3103

C3104

C3000

L3000

4R7

D3000

R3066

C1615

C1651 C1650

C1631

C3053

C3007

C1632

C1625

C1622

U1600

C1634

C1614

C1624

C3005

J6051

C3070

R3070

J5400 J5401

R3071

J3011J3010

C1623

C1612

C1613

C1633

C1408

C1424

C1406

C1432

C1431

C1420

C1423

C1422

R10234

C1425

C1022

R1083

C1462

R1453

C1412

C1085

C1405

C1084

C1454

R1454

C1419

R1084

R1420

C1434

C1407

C1413

C1401

C1463

C1426

C1435

C1456

C1402

C1409

C1411

R1456

C1421

R1455

R1022

C1096

R1096

R1095

C1095

C1403

C1430

C1404

C1414

C1104

C1630

R8281

C1610

C1620

R9000

R0714

C1101

C1103

R0718

R0715

R1208

R1209

R1220

R1203

U0600

R1205

R1204

R0703

R0704

R1020

C1023

C1427

R1055

C1433

C1192

C1058

C1327

C1304

R1056

C1197 C1311

C1144

C1306

C1312

C1056

C1333

C1313

C1335

C1324

R1355

C1363

C1356

R1356

C1322

C1330

C1307

C1334

C1308

C1320

C1301

C1323

C1326

C1321

C1318

C1362

R1353

C1302

C1331

C1354

R1354

C1309

C1314

C1021

R1053

C1057

C1325

C1054

R1054

C1100

C1305

C1319

R1021

C1303

C1020

C1105

C1102

R0642

R0643

R0608

C0640

R0622

R0621R0620

R0640

R0652

C1179

CA185

R0717

R0720

R1206

R0701

R0702

R0700

Y0602

C0650

R0713

R0711

R0650

R0651

C0651

R0716

R0708

R0709

R0710

R1201

R1202

R1200

R0730

U5902

R5960

C5960

R5934

R5962

R5961

R5991

C5991

R5990

C5931

R5929

C5935

U5900

C5940

C5934

C8163

C8164

C8131

D8258

C8262

C8263

C8264

C8265

R5930

C5930

R5931

C5932

C5942

C5933

C5944

C5943

C5941

C8166

J5900

LED9000

R9002

C8165

C3759

C3784

C3786

C3787

R3755

C3788

FL3750

R3754

FL3751

C3783

C3750

R3750

C3781

C3766

C3749

FL3740

C3764

C3761

FL3741

C3763

C3740

R6111_RF

C6101_RF

C6102_RF

R6107_RF

J3700

J5950

J6190_RF

C3741

L3740

C3758

R3751

C3756

C3754

C3753

C3752

R0721

C3751

C3748

R3741

C3744

C3743

C3742

C3712

C3745

U3740

C3711

C3710

L3750

C3713

C3746

C3767

R3745

C3768

C3747

R3744

R3742

C3760

R3743

R3740

C3723

U3750

C3757

C3722

C3721

R3752

C3780

R3753

C3755

C3720

C6109

L6111_RF

R6112_RF

U6102_RF

C6110_RF

R6113_RF

R6108_RF

R6109_RF

C6104_RF

R6114_RF

R6105_RF

C6103_RF

J6191_RF

820-3249-BOT MLB

L5701

DZ5792

L5700

DZ5791

C5920

C5910

DZ5900

DZ5901

DZ5902

R8216

C3773

C3772

C3771

C3770

C5741

FL5740

C5711

C5740

FL5710

C5710

DZ5740

DZ5710

C5730

C5732

L5730

C5731

C5733

C6107_RF

L6192_RF

C6192_RF

L6191_RF

U6104_RF

C6108_RF

L6190_RF

C6111_RF

C6190_RF

C6191_RF

DZ5903

L5931

DZ5990

DZ5750

C5765

C5766

FL5750

C5990

FL5990

U6101_RF

L5930

C5783

C5750

C5900

L5757

DZ5760

C5721

R5790

C5722

Q8104

C8173

C8171

R8100

R8280

Q8123

C8174

C8170

C8221

DZ8120

R8130

R9031

R8116

R9030

Q9030

R9021

R9020

Q9020

R8170

R8196

R8219

C8196

C8220

C8206

D8230

C8209

C8130

C8236

C8210

C8169

C8168

R8173

C8217

C8138

C8239

C8223

C8238

C8134

C8212

C8214

C8132

C8145

C8133

C8146

C8281

C8136

C8135

C8204

R8203

C8153

C8282

C8207

C8137

C8151

C8167

C8140

C8162 C8161 C8160 C8159 C8158

C8267
C8251

C8266

C8201

R8172

C8172

C8215

C8156

C8187

C8188C8189C8190C8191C8192C8193

C8157

C8139
C8141

R9001

D5990

C8290

R8290

R8292

Q8200

R8291

C8291

R8293

Q8201Q8203Q8202

R1320

C1310

C11A1

C11A0

R1321

C1165

C1166

C11B0

R0719

U1300

C1316

C1332

R1351

C1315

C1361

R1352

C1352

R1260

CA190

R1211

C0924

C0927

C1110

CA196

C1181

C0910

C0932

C1147

C0928

C11B1

C0934

C0930

C1148

C0929

C0909

C0933

C1136

C1191

CA186

C1198
CA191

CA189

CA152

CA151

C0955

R0920

C0950

C0623

C0952

FL0911

C0956

C0951

C1199

CA195

R0921

C0957

R0911

C0931

C1328 C1329

C1416 C1428 C1429

C1317

C1360

R1451

R1305

C1461

R1452

R1306

C1452

C1350

C1142

C1194

C1196

C1193

C1125

C1111

C1129

C1113

C1115

C1128

C1107

C1124

C1122

C0607

R0604

C1126

R1210

C1120

C1123

C1117

C1137

C1134

C1131

C1135

C1140

C1132

C1130

C1106

C1121

C1116

C1133

C0953

C1141

C0810

C1118

CA193

R0950

CA188

C0613

C0612

C0633

C0634

C0812

CA192

C0614

C0632

CA199

CA187

R0931

C0630

C0811

R0941

R9010

R9011

R0942

R0933

R0613

C0621

R0940

C0609

R0610

Q9010

C0608

C1143

C1195

C1109

C1119

C1108

C1138

C0606

C1151

C1150

C1182

C1153

C1183

R0900

R8218

C1156

C1152

C1149

C1184

C1180

C11E0

C11E1

C11D0

C11D1

C1139

C1155

C1162

C1164

C11C1

C1163

C1157

C1154

C1161

C1170

C1169

C1175

C1174

C1185

C1145

R0930

C1168

R0932

U1400

C0636

C1114

C1190

C0631

C0637

C1158

C0635

C11C0

C1159

C0960

C1160

C0982

C0908

C1178

C1172

C0904

C1177

C1171

C0907

C1173

CA198

CA194

C1176

C0820

CA153

C0821

CA150

C11F0

CA197

R0843

C0843

R0842

C0842

C1167

C1418

C1417

C1410

C1460

R1405

C1415

R1406

R1421

C1450

C0935

FL0910

C0903

C0981

C0961

C0980

R1207

C1608

C1605

C1601

R1690

C1690

C1691

R1691

C1607

C1600

C1604

U3003

R1655

C1609

C1606

C1602

R0831

R0832

R1654

C3006

C3109

C3111

U3101

R3107

R3120

C3690

C3604

C3609

C3613

C3612

R3601

C3611

C7525

C7524

FL7500

C7523

C7526

C7522

L2210

L2200

C2233

C2253

C2220

C2270

C2221

C2271

U3100

C5661

C5660

U5660

U5670

U5650

C5670

L5520

L5540

L5530

C5671

C2240

R8227

U5640

C2239

R8231

U2200

R8232

R8239

R8240

R8235

C5640

R5641 R5640

R5630

C7527

C2241

C2203

R8270

R8265

R8261

C2286

R2286

R2287

R8262

R8269

R8257

C2249

L5570

C5573

L5500

R5631

C5630

R2242

C2232

C2206

C2230

R2290

L2201

C2202

C2281

C2280

C2282C2283C2285C2287

C2284

R2280

R2282

R2284

R2281

R2285

R2283

L2212L2222L2232L2202

C2244

C2245

C2248

C2246

C2247

C2242

C2243

L2242

C2250

R2241R2240

C2251

R8282

C5581

C5561

C5551

L5580

L5560

C5550

C5580

C5571

C5562

C5570

C5582

L5550

C5563

C5560

C5572

C5552

C5583

C5553

C5584

L5510

C0605

U5600

U5630

U5620

R0706

R0705

U5610

J6000

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

2 1

REV ECN

A

0001554595

DESCRIPTION OF REVISION

PRODUCTION RELEASED

CK
APPD

DATE

2012-07-26

iPad 4th Gen

LAST_MODIFIED=Thu Jul 26 10:29:36 2012

SIZE

D

C

B

A

D

D

C

B

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CSAPDF

CONTENTS
Table of Contents

1

BLOCK DIAGRAM: SYSTEM

2

BOM TABLES

4

AP: MAIN

6

AP: I/Os

7

AP: NAND

8

AP: TV,DP,MIPI

9
10

AP: DDR
AP: POWER

11
12

AP: MISC & ALIASES

13

DDR 0 AND 1
DDR 2 AND 3

14

NAND

16

ALIASES

21

VIDEO: EDP CONNECTOR

22

GRAPE: GROUNDHOG,CONN,BOOST

30

GRAPE: Z1, Z2

31

AUDIO: L81 CODEC

36

AUDIO: SPEAKER AMP

37

SENSOR FLEX CONN

54

SENSOR CONN FILTERS 1

55

SENSOR CONN FILTERS 2

56

E75 DOCK SUPPORT

57

IO FLEX CONN

58

TRISTAR

59

CONNECTOR: CELLULAR

60
61

WIFI/BT

75

POWER: BATTERY CONNECTOR
PMU: ADRIANA PAGE 1

81
82

PMU: ADRIANA PAGE 2

SYNC MASTER

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

MADHAVI

MADHAVI

MADHAVI

DATE

N/A

N/A

N/AN/A

N/A

N/A

N/A

N/AN/A

N/A

N/A

N/AN/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

12/06/2011

12/06/2011

12/06/2011

A

DRAWING

MLB
DRAWING

(SYSTEM DRI)

(AMANDA)

(AMANDA)

(AMANDA)

(TERRY)

(AMANDA)

(TERRY)

(TERRY)

(TERRY)
(TERRY)

(TERRY)

(TERRY)

(TERRY)

(AMANDA)

(AMANDA)

(JOE)

(AMANDA)

(AMANDA)

(TERRY)

(TERRY)

(MARK)

(MARK)

(MARK)

(JOE)

(JOE)

(JOE)

(AMANDA)

(MATT)

(MADHAVI)

(MADHAVI)

(MADHAVI)

PDF

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CSA

83
90
93
121
150
151
152
153
154

CONTENTS
PMU: ADRIANA PAGE 3
DEBUG/MISC.
TEST/HOLES/FIDUCUALS
POWER ALIASES
CONSTRAINTS: MLB RULES
CONSTRAINTS: LOW SPEED BUS
CONSTRAINTS: DISPLAY/AUDIO
CONSTRAINTS: DDR/FMI
CONSTRAINTS: POWER / GND

3

SYNC MASTER

MADHAVI 12/06/2011

MLB

N/A N/A

N/A N/A

MIKE

MIKE

MIKE

MIKE

MIKE

DATE

11/09/2011

11/30/2011

11/30/2011

11/30/2011

11/30/2011

11/30/2011

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

(SYSTEM DRI)

(MADHAVI)

(AMANDA)

(AMANDA)

(MADHAVI)

(AMANDA)

(AMANDA)

(AMANDA)

(AMANDA)

(AMANDA)

X140 MLB

Apple Inc.

R

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

1 OF 154

SHEET

1 OF 39

1245678

8 7 6 5 4 3

WWW.AliSaler.Com

12

ISP_I2C1

Z2

CSA 31

SPI3

MIPI1C

ISP_I2C0

MIPI0C

D

GROUNDHOG

Z1

HSIC1_1

UART3

FF CAMERA

VGA FLEX

REAR CAMERA

VA5 FLEX

D

WIFI/BT ANT

WIFI/BT

CSA 30

CSA 31

LPDDR2

CSA 13-14

DISPLAY/

TOUCH PANEL

C

BACKLIGHT

EDP

BALI

UART4

I2S2

HSIC3

UART1

BT_I2S

CSA 61

CELLULAR/

HSIC1
IPC

USART
USART

CSA 60

GPS

NOT ON

WIFI-ONLY CONFIG

PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT

GPS ANT
SIM CARD

C

HALL EFF 1

BUTTON FLEX

HALL EFF 2

HOME BUTTON

PMU

ADRIANA

CSA 81,82

B

A

SENSOR BOARD

GYRO

PROX SENSOR

SENSOR BOARD

ACCELEROMETER

SENSOR BOARD

BATTERY

CSA 75

COMPASS

SENSOR BOARD

ALS

VGA FLEX

UART5

USB11

USB2.0

DWI
I2C0

UART2
UART6

I2S1

I2C1

SPI1

I2S0
I2S3

I2C2

FMI0 FMI1

I2S4

NC

NAND FLASH

CSA 16

6 3

AUDIO CODEC

L81

SPI
ASP

XSP

CSA 36

MBUS

MIC2MIC1

TRISTAR

AMP

SPEAKER

AMP

HP

SYNC_MASTER=N/A

PAGE TITLE

BLOCK DIAGRAM: SYSTEM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CSA 59

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=N/A

A.0.0

2 OF 154

2 OF 39

SIZE

B

A

D

8 7 6 5 4 3

12

SCH AND BOARD P/N

Page Notes

Power aliases required by this page:
(NONE)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:

D

BOM OPTIONS

COMMON
ALTERNATE

16GB_PROD: 16GB CONFIG
32GB_PROD: 32GB CONFIG
64GB_PROD: 64 GB CONFIG
DEV: DEV BOARD ONLY

MLB: MLB BOARD ONLY
MLB_A: WIFI ONLY CONFIG
MLB_B: CELLULAR CONFIG
MLB_C: CELLULAR CONFIG
MLB_D: LEGACY CELLULAR CONFIG
MLB_E: LEGACY CELLULAR CONFIG

PART#

SOC

PART#

343S0598 CRITICAL

PMU

PART#

343S0622

DESCRIPTION

QTY

1

SCH,MLB,X140

1

PCBF,MLB,X140

DESCRIPTION

QTY

IC,SOC,H5G,FCBGA1089,0.5MM

1

DESCRIPTION

QTY

1

IC,PMU,ADRIANA,D2018A1,FCBGA

REFERENCE DESIGNATOR(S)

SCH1051-9385

PCB1

REFERENCE DESIGNATOR(S)

U0600

REFERENCE DESIGNATOR(S)

U8100

CRITICAL BOM OPTION

CRITICAL

CRITICAL820-3249

CRITICAL BOM OPTION

CRITICAL BOM OPTION

CRITICAL

SDRAM

PART#

333S0636

BOM GROUP

BASIC

BOM OPTIONS

COMMON,ALTERNATE

C

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER

333S0637

333S0638 333S0636

DESCRIPTION

QTY

2

LPDDR2,533MHZ,512MB,SAMSUNG,35NM

ALTERNATE FOR
PART NUMBER

333S0636

BOM OPTION

REFERENCE DESIGNATOR(S)

U1300,U1400

REF DES

COMMENTS:

U1300,U1400

U1400,U1400

LPDDR2,533MHZ,HYNIX,38NM

LPDDR2,533MHZ,ELPIDA,38NM

CRITICAL BOM OPTION

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

D

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

C

NAND

16GB FLASH CONFIGURATIONS

PART#

335S0878

DESCRIPTION

QTY

TOSHIBA PPN1.5 16GB

1

REFERENCE DESIGNATOR(S)

U1600

CRITICAL BOM OPTION

CRITICAL

16GB_PROD

32GB FLASH CONFIGURATIONS

MECHANICAL PARTS

PART#

B

NAND
SOC/PMU

806-4195

806-3493

AUDIO
GRAPE
MEMORY

806-4196 CRITICAL

806-3492

DESCRIPTION

QTY

FENCE,NAND,TOP,MLB,X140

1

FENCE,LARGE,TOP,MLB,X140

1

FENCE,AMP,MLB,X140

1

FENCE,1,BTM,MLB,X140

1

FENCE,2,BTM,MLB,X140

1

REFERENCE DESIGNATOR(S)

PD_FENCE_NAND

PD_FENCE_LARGE

PD_FENCE_AMP

PD_FENCE_BTM1

PD_FENCE_BTM2

CRITICAL BOM OPTION

CRITICAL

CRITICAL

CRITICAL806-3956

CRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PART#

335S0879

DESCRIPTION

QTY

TOSHIBA PPN1.5 32GB

1

REFERENCE DESIGNATOR(S)

U1600

CRITICAL BOM OPTION

CRITICAL

32GB_PROD

64GB FLASH CONFIGURATIONS

BARCODE LABEL/EEEE CODES

PART#

825-7838

825-7838

825-7838

825-7838

825-7838

825-7838

825-7838

A

825-7838

825-7838

825-7838

825-7838

DESCRIPTION

QTY

EEEE FOR 639-3736 (MLB A 16G)

1

EEEE FOR 639-3737 (MLB A 32G)

1

1

EEEE FOR 639-3738 (MLB A 64G)

1

EEEE FOR 639-4176 (MLB A 128G)

1

EEEE FOR 639-3263 (MLB B 16G)

1

EEEE FOR 639-3739 (MLB B 32G)

EEEE FOR 639-3740 (MLB B 64G)

1

1

EEEE FOR 639-4177 (MLB B 128G) EEEE_MLB_B_128G

1

EEEE FOR 639-3741 (MLB C 16G)

1

EEEE FOR 639-3742 (MLB C 32G)

1

EEEE FOR 639-3743 (MLB C 64G)

1

EEEE FOR 639-4178 (MLB C 128G) EEEE_MLB_C_128G

REFERENCE DESIGNATOR(S)

EEEE_F1WD

EEEE_F1WH

EEEE_F1W8

EEEE_F80Q

EEEE_DWKG

EEEE_F1W7

EEEE_F1WC

EEEE_F80P

EEEE_F1WG

EEEE_F1WF

EEEE_F1W9

EEEE_F80R

CRITICAL BOM OPTION

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL825-7838

EEEE_MLB_A_16G

EEEE_MLB_A_32G

EEEE_MLB_A_64G

EEEE_MLB_A_128G

EEEE_MLB_B_16G

EEEE_MLB_B_32G

EEEE_MLB_B_64G

EEEE_MLB_C_16G

EEEE_MLB_C_32G

EEEE_MLB_C_64G

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PART#

335S0880

128GB FLASH CONFIGURATIONS

PART#

DESCRIPTION

QTY

1

TOSHIBA PPN1.5 64GB

DESCRIPTION

QTY

1

TOSHIBA PPN1.5 128GB

REFERENCE DESIGNATOR(S)

U1600

REFERENCE DESIGNATOR(S)

U1600

CRITICAL BOM OPTION

CRITICAL

CRITICAL BOM OPTION

CRITICAL

64GB_PROD

128GB_PROD335S0912

6 3

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

B

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

SIZE

A

D

SYNC_MASTER=N/A

PAGE TITLE

BOM TABLES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

4 OF 154

SHEET

3 OF 39

124578

8 7 6 5 4 3

WWW.AliSaler.Com

12

A1
A2

C33

F1
A11
A14
A17
A32
A33

B12
B15
B32
B33

C10
C13
C16

D11
D14
D17
U19
E10
E22
E24
E25

F22
F24
F25
F30
A31

G18
G21
G22
G26
V18

H10
H11
H12
H13
H14
H21
H22
H28
H33

J11
J13
J15
J21
T18

K10
K12
K14
K22
K26
K30

L11
L13
L15
L17
L19
L21
L33

M10
M12
M14
M16
M18
M20
M22

B1

B2

B4

B9

C7

A3

D3

D5

D8

F2

F5

G3

H4

H9

J2

J9

K3

K8

L1

L4

L9

M2

M3

M8

D

C

B

A

U0600

BALI-H5G

BGA

SYM 11 OF 12

OMIT_TABLE

C0605

0.1UF

20%
4V
X5R
01005

PP0600

SM

1

C0640

1000PF

10%
16V

2

X7R-CERM
0201

R0604

0.00

12

1/32W
01005

1

C0633

0.1UF

20%

6.3V

2

X5R-CERM
01005

PP

P4MM

39

PP1V8_PL0_F

C0637

8.2PF

+/-0.5PF
16V
NP0-C0G-CERM
01005

C0636

8.2PF

+/-0.5PF
16V
NP0-C0G-CERM
01005

R27

HSIC_VDD121

11.9MA

PER PIN

R33

HSIC1_DATA

T33

HSIC1_STB

R31

HSIC2_DATA

T31

HSIC2_STB

HSIC3_DATA
HSIC3_STB

H17

JTAG_SEL

J16

JTAG_TRTCK

K16

JTAG_TRST*

H16

JTAG_TDO

F16

JTAG_TDI

F17

JTAG_TMS

J17

JTAG_TCK

D18

TESTMODE

L31

FUSE1_FSRC

A19

TST_STPCLK

C19

TST_CLKOUT

N27

FAST_SCAN_CLK

G16

HOLD_RESET

G17

RESET*

A18

CFSB

L6

DDR0_CKEIN

F9

DDR1_CKEIN
DDR2_CKEIN

AD5

DDR3_CKEIN

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3MM

T28

AF19

HSIC_VDD123

HSIC2_DVDD102

2.7MA

PER PIN

HSIC_VSS121

R28

AF18

HSIC3_DVDD103

USB 1.1 BASEBAND/TRISTAR
NEEDED IF WE GO TO 9600

HSIC_VSS122

HSIC_VSS123

T29

AG18

R26

HSIC_VDD122

U18

VDD_ANA_PLL

8MA

U0600

BALI-H5G

BGA

SYM 1 OF 12

OMIT_TABLE

CPU_VDD CONTROL

HSIC2_DVSS

HSIC3_DVSS

T25

AG19

TRISTAR

NEW TO BALI

USB_BRICKID_DM_MON

USB_VSSA0

R29

R30

P26

USB_DVDD

5.4MA

USB11_DP
USB11_DM

USB_ANALOGTEST

USB_VBUS

USB_BRICKID

USB_REXT

CPU0_SWITCH
CPU1_SWITCH

USB_ASW_VSS18

P32

N26

USB_VDD330

USB_ASW_VDD18

<1MA

30MA

WDOG

XI0
XO0

USB_DP
USB_DM

USB_ID

1

C0621

8.2PF

+/-0.5PF

16V

2

NP0-C0G-CERM
01005

1

C0623

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

C18

J33
K33

E32
D32

M33
N33

R25

P28

P27
P31

T30

N32
N24

P29

AP_WDOG

36

XTAL_AP_24M_I
XTAL_AP_24M_O

36

USB11_AP_BBMUX_P
USB11_AP_BBMUX_N

USB_AP_P
USB_AP_N

NC_USB_ANALOGTEST

NO_TEST=TRUE

USB_AP_VBUS0

NC_USB_ID

NO_TEST=TRUE

NC_USB_BRICKID

NO_TEST=TRUE

USB_REXT0

CPU0_SWITCH
CPU1_SWITCH

NC_USB_BRICKID_DM_MON

NO_TEST=TRUE

1

C0608

0.01UF

10%

6.3V

2

X5R
01005

1

C0612

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

1

C0613

0.1UF

20%
4V

2

X5R
01005

MLB

R0652

0.00

12

0%

1/32W

MF

01005

25 36

BI

25 36

BI

25 36

BI

25 36

BI

30

OUT

30

OUT

1

C0609

0.01UF

10%

6.3V

2

X5R
01005

1

C0614

1UF

10%

6.3V

2

CERM
402

=PP1V8_VDDIO18_H5

MLB OPTION USED FOR FF

AP_WDOG_RESET_IN

1

R0650

1.00M

1%
1/32W
MF
01005

2

1

R0613

43.2

1%
1/20W
MF
201

2

12

=PP1V0_USB_H5

=PP3V3_USB_H5

OUT

R0651

22

36

5%

1/32W

MF

01005

SYNC_MASTER=N/A

PAGE TITLE

34

34

CHANGE TO USB 3.3V TO AVOID
ISSUE FOUND IN H5P:
FAILURE IN CHARGE DETECT CIRCUIT AT 3.0V-5%

6 7 9

34

25

CRITICAL

Y0602

24.000MHZ-16PF-60PPM

AP_24M_O

CRITICAL

1

C0650

22PF

5%
16V

2

CERM
01005

SM-2

13

PPVBUS_USB

1

R0610

68.1K

1%
1/20W
MF
201

2

24

29

AP: MAIN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

1

C0651

2

22PF

5%
16V
CERM
01005

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

6 OF 154

SHEET

4 OF 39

SIZE

D

C

B

A

D

0%
MF

1

14 36
14 36

26 36
26 36

10 36 39

10

10

10

10

BCM4330
WLAN

BI
BI

MDM9615
BB

BI
BI

10

IN

36

36
25 36
25 36

IN

OUT

OUT

IN

R0642

100K

1/32W
01005

R0643

221K

1/32W
01005

1

C0606

0.1UF

20%
4V

2

X5R
01005

1

C0630

0.01UF

10%

6.3V

2

X5R
01005

1

C0634

0.1UF

20%

6.3V

2

X5R-CERM
01005

HSIC1_WLAN_DATA
HSIC1_WLAN_STB

HSIC3_BB_DATA
HSIC3_BB_STB

JTAG_AP_SEL

JTAG_AP_TRST_L
TP_JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TMS
JTAG_AP_TCK

AP_TESTMODE

AP_TST_STPCLK

AP_FAST_SCAN_CLK

AP_HOLD_RESET

1

1%
MF

2

1

1%
MF

2

1

C0607

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

1

C0631

0.01UF

10%

6.3V

2

X5R
01005

1

C0635

0.01UF

10%

6.3V

2

X5R
01005

NC_HSIC2_DATA
NC_HSIC2_STB

NC_JTAG_AP_TRTCK

TP_AP_TST_CLKOUT

AP_DDR1_CKEIN_1V2

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

1

2

1

2

AN17
AM17

AG10

124578

M28
N3
N9
N11
N13
N15
N17
N19
N21
N23
P1
P8
P10
P12
P14
P16
P18
P20
P22
P30
P33
R2
R6
R9
R11
R13
R15
R17
R19
R21
R23
R32
T5
T6
T8
T10
T12
T14
T16
T22
T24
T32
U1
U2
U4
U9
U11

VSSVSS

U13
U15
U17
U21
U23
U33
V8
V10
V12
V14
V16
V19
V21
V23
V30
W3
W9
W11
W13
W15
W17
W20
W22
W24
Y1
Y10
Y12
Y14
Y16
Y18
Y19
Y21
Y23
Y25
Y28
Y32
AA2
AA9
AA11
AA13
AA15
AA17
AA20
AA22
AA24

25 26 30 39

IN

10 34

10 34

10 34

=PP1V8_H5

4 5 7

=PP1V8_H5

4 5 7

=PP1V8_H5

4 5 7

RST_AP_L

=PP1V8_PLL_H5

34

=PP1V0_HSIC_H5

34

=PP1V2_HSIC_H5

34

1

R0640

7.5K

5%
1/32W
MF
01005

2

1

2

1

C0632

0.1UF

20%

6.3V

2

X5R-CERM
01005

NOSTUFF

R0608

100K

12

5% MF

010051/32W

R0620

100K

12

5%

010051/32W

R0621

100K

12

5%

1/32W 01005

R0622

100K

12

5%

010051/32W

6 3

D

C

USED FOR DEBUG
AND SW UPDATE

OS CURRENTLY SUPPORTS
USB1.1 FOR DEBUG.

B

I2S0_CODEC_ASP_MCK_R

18 36

OUT

L81 CODEC ASP

1.8V

I2S1_SPKAMP_MCK_R

19

OUT

L19 AMPLIFIERS

1.8V

TO BB

1.8V IO

8 7 6 5 4 3

R0700

33.2

1%

1/32W

MF

BT

1.8V

L81 CODEC XSP

1.8V

NOT USED

26 36

OUT

R0720

01005

12

R0730

33.2

1%

1/32W

MF

01005

12

1

100K

5%

1/20W

MF

201

2

I2S0_CODEC_ASP_MCK

36

I2S0_CODEC_ASP_BCLK

18 36

OUT

I2S0_CODEC_ASP_LRCK

18 36

OUT

I2S0_CODEC_ASP_DIN

18 36

IN

I2S0_CODEC_ASP_DOUT

18 36

OUT

I2S1_SPKAMP_MCK
I2S1_SPKAMP_BCLK

19

OUT

I2S1_SPKAMP_LRCK

19

OUT

I2S1_SPKAMP_DIN

19

IN

I2S1_SPKAMP_DOUT

19

OUT

NC_I2S2_MCK
I2S2_BT_BCLK

14 36

OUT

I2S2_BT_LRCK

14 36

OUT

I2S2_BT_DIN

14 36

IN

I2S2_BT_DOUT

14 36

OUT

NC_I2S3_MCK
I2S3_CODEC_XSP_BCLK

18 36

OUT

I2S3_CODEC_XSP_LRCK

18 36

OUT

I2S3_CODEC_XSP_DIN

18 36

IN

I2S3_CODEC_XSP_DOUT

18 36

OUT

NC_I2S4_MCK
NC_I2S4_BCLK
NC_I2S4_LRCK
NC_I2S4_DIN
NC_I2S4_DOUT

NC_AP_GPIO216

GPIO_BOARD_ID_2

10

IN

GPIO_BOARD_ID_1

10

IN

GPIO_BOARD_ID_0

10

IN

TP_SPI0_SSIN

SPI1_CODEC_MISO

18 36

IN

SPI1_CODEC_MOSI

18 36

OUT

SPI1_CODEC_SCLK

18 36

OUT

SPI1_CODEC_CS_L

18 36

OUT

BB_JTAG_TRST_RF_L

26

IN

BB_JTAG_TDI_RF

26

OUT

BB_JTAG_TDO_RF

26

IN

GPIO_BB_HSIC_HOST_RDY

SPI3_GRAPE_MISO

16 36

IN

SPI3_GRAPE_MOSI

16 36

OUT

SPI3_GRAPE_SCLK

16 36

OUT

SPI3_GRAPE_CS_L

16 36

OUT

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

M27
M29
N31
M32
M26

H30
L24
L23
M24
N30

J29
L29
L28
L26
L25

L32
E29
K32
J25
M30

F31
H25
K28
K31
J32

K29

Y31
V28
V32
V29

AB29

Y29
AA28
AA32

AB28
AB33
AC29

W33

D19

G20

E19

F19

I2S0_MCK

I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

I2S4_MCK
I2S4_BCLK
I2S4_LRCK
I2S4_DIN
I2S4_DOUT

SPDIF

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

U0600

BALI-H5G

SYM 3 OF 12

OMIT_TABLE

GRAPE

3.0V

4 5 7

10 34

GPIO_GRAPE_IRQ_L

5

16

BGA

=PP1V8_H5

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

I2C2_SCL
I2C2_SDA

SWI_DATA

DWI_CLK

DWI_DI
DWI_DO

NOSTUFF

1

R0760

100K

5%
1/20W
MF
201

2

Y33
U29

W27
W29

H20
B19

AB27

T26
W32
W28

I2C0_SCL_1V8
I2C0_SDA_1V8

I2C1_SCL_1V8
I2C1_SDA_1V8

I2C2_SCL_3V0
I2C2_SDA_3V0

NC_SWI_AP

NO_TEST=TRUE

DWI_AP_CLK
DWI_AP_DI
DWI_AP_DO

5

19 25 30 36

BI

5

19 25 30 36

OUT

22 36

5

BI

5

22 36

OUT

5

22 36

BI

5

22 36

OUT

30 36

OUT

30 36

IN

30 36

OUT

TO:
TRISTAR 0011010X
ADRIANA PMU 0111100X
L19 LEFT 1000000X
L19 RIGHT 1000001X

TO SENSOR BOARD:
AD7149 PROX 0101100X
AKM8975B COMPASS 0001110X

TO SENSOR BOARD:
CT809 ALS 0111001X
LIS331DLH ACCEL 0011001X
AP3GDL8 GYRO 1101000X

GPIO_BTN_HOME_L

5

23 30

IN

20 30

26

14 36

30

32

20 30
16

19
19

GPIO_BTN_ONOFF_L

5

IN

GPIO_BB_HSIC_DEV_RDY

26 36

IN

GPIO_BTN_VOL_UP_L

20

IN

GPIO_ALS_IRQ_L

22

IN

GPIO_BT_WAKE

14

OUT

GPIO_AP_MODEM_WAKE

26

IN

BB_JTAG_TMS_RF

26

OUT

GPIO_BB_RST_L

26 39

OUT

GPIO_BB_RADIO_ON_L

5

OUT

GPIO_BB_RESET_DET_L

26

IN

GPIO_ACCEL_IRQ2_L

22

IN

GPIO_BB_HSIC_RESUME

26 36

IN

GPIO_WLAN_HSIC_HOST_RDY

5

OUT

GPIO_BTN_VOL_DOWN_L

20

IN

GPIO_BB_GSM_TXBURST

26

IN

GPIO_BOARD_ID_3

10

IN

PMU_GPIO_TS_INT

25 30

IN

GPIO_BOOT_CONFIG_0

10

IN

GPIO_BB_GPS_SYNC

26

OUT

GPIO_PROX_IRQ_L

22

IN

GPIO_GYRO_IRQ1

22

IN

GPIO_PMU_KEEPACT

5

OUT

GPIO_PMU_IRQ_L

30

IN

GPIO_WLAN_HSIC_DEV_RDY

14 36

IN

GPIO_BOOT_CONFIG_1

10

IN

GPIO_FORCE_DFU

5

IN

GPIO_DFU_STATUS

5

OUT

GPIO_BOOT_CONFIG_2

10

IN

GPIO_BOOT_CONFIG_3

10

IN

GPIO_BTN_SRL_L

5

IN

GPIO_GRAPE_IRQ_L

5

IN

GPIO_WL_HSIC_RESUME

14

IN

GPIO_SPKAMP_RST_L

5

OUT

GPIO_SPKAMP_KEEPALIVE

5

OUT

GPIO_SPKAMP_RIGHT_IRQ_L

19

IN

PM_LCDVDD_PWREN

15

OUT

GPIO_SPKAMP_LEFT_IRQ_L

19

IN

SPK_ID

19

IN

GPIO_CODEC_IRQ_L

18

IN

GPIO_GRAPE_FW_DNLD_EN_L

16

OUT

GPIO_GRAPE_RST_L

16

OUT

AK20
AJ19
AK22
AK19
AK21
AK24
AJ21
AK18
AL26
AH25
AJ18
AJ23
AK23
AJ20
AJ22
AJ24
AL25
AM26
AK25
AN26

F26
E26
J31
F29
E30
H31
J30
H32
G27
E27
F32
J28
G31
G32
G28
G33
J26
G30
G29
F27

H19
J19

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39

GPIO_3V0
GPIO_3V1

OMIT_TABLE

U0600

BALI-H5G

BGA

SYM 2 OF 12

EHCI_PORT_PWR0
EHCI_PORT_PWR1
EHCI_PORT_PWR2
EHCI_PORT_PWR3

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART0_RXD
UART0_TXD

UART1_CTSN
UART1_RTSN

UART1_RXD
UART1_TXD

UART2_CTSN
UART2_RTSN

UART2_RXD
UART2_TXD

UART3_CTSN
UART3_RTSN

UART3_RXD
UART3_TXD

UART4_CTSN
UART4_RTSN

UART4_RXD
UART4_TXD

UART5_RXD
UART5_TXD

UART6_CTSN
UART6_RTSN

UART6_RXD
UART6_TXD

GPIO_SVSEL18_FMI
GPIO_SVSEL25_FMI

GPIO_VSEL25_I2C2
GPIO_VSEL25_SPI3

VSEL18_FMI AND VSEL25_FMI LOW => FMI CHANNEL AT 1.8V
VSEL25_I2C2 HIGH => I2C2 3.0V
VSEL25_SPI3 HIGH => SPI3 3.0V

AK28

GPIO_BRD_REV0

AJ25

GPIO_BRD_REV1

AK26

GPIO_BRD_REV2

AK27

NC_EHCI_PORT_PWR3_AP

NO_TEST=TRUE

V33

GPIO_GYRO_IRQ2

W31

GPIO_ACCEL_IRQ1_L

V27

NC_TMR32_PWM2_AP

NO_TEST=TRUE

K18

NC_UART0_RXD

NO_TEST=TRUE

K19

NC_UART0_TXD

NO_TEST=TRUE

AM27

UART1_BB_CTS_L

AM28

UART1_BB_RTS_L

AN27

UART1_BB_RXD

AN28

UART1_BB_TXD

Y30

BB_JTAG_TCK_RF

AC27

NC_UART2_RTSN

NO_TEST=TRUE

AC33

UART2_TS_ACC_RXD

AD33

UART2_TS_ACC_TXD

AB32

UART3_BT_CTS_L

AC30

UART3_BT_RTS_L

AC32

UART3_BT_RXD

AD32

UART3_BT_TXD

NO_TEST=TRUE

Y27

NC_UART4_CTS_L

NO_TEST=TRUE

AA29

NC_UART4_RTC_L

AB31

UART4_WLAN_RXD

AC31

UART4_WLAN_TXD

J18

UART5_BATTERY_TRXD

K17

NC_UART5_TXD

NO_TEST=TRUE

AC28

NC_UART6_CTSN

NO_TEST=TRUE

W30

NC_UART6_RTSN

NO_TEST=TRUE

AA30

UART6_AP_RXD

AA31

UART6_AP_TXD

H27
G25

E31
H29

GPIO_VSEL25_I2C2
GPIO_VSEL25_SPI3

12

10

IN

10

IN

10

IN

22

IN

22

IN

26 36

IN

26 36

OUT

25 26 36

IN

25 26 36

OUT

26

OUT

25 36

IN

25 36

OUT

14 36

IN

14 36

OUT

14 36

IN

14 36

OUT

14 36

IN

14 36

OUT

35

25 36

IN

25 36

OUT

28 30

OUT

=PP1V8_H5

1

R0716

100K

5%
1/20W
MF
201

2

TO BB UART
MDM9600

TO TRISTAR

1.8V

TO BT UART
BCM4330

WIFI DEBUG

TO TRISTAR

1.8V

1

R0717

100K

5%
1/20W
MF
201

2

4 5 7

10 34

D

C

B

BUTTON PULLUPS

R0708

220K

=PP1V8_S2R_MISC

5

32 34

GPIO_BTN_HOME_L

5

23 30

=PP1V8_ALWAYS

34

GPIO_BTN_ONOFF_L

5

A

20 30

=PP1V8_S2R_MISC

32 34

5

GPIO_BTN_SRL_L

5

20 30

12

5%

1/20W

MF

201

R0709

220K

12

5%

1/20W

MF

201

R0710

220K

12

5%

1/20W

MF

201

1

R0711

100K

5%
1/20W
MF
201

2

1

R0713

5%
1/20W
MF
201

2

NOSTUFF

1

R0714

100K100K

5%
1/20W
MF
201

2

NOSTUFF

1

R0715

100K

5%
1/20W
MF
201

2

1

R0718

100K

5%
1/20W
MF
201

2

GPIO_PMU_KEEPACT
GPIO_FORCE_DFU
GPIO_DFU_STATUS
GPIO_BB_RADIO_ON_L
GPIO_WLAN_HSIC_HOST_RDY
GPIO_SPKAMP_RST_L

GPIO_SPKAMP_KEEPALIVE

1

R0719

100K

5%
1/20W 1/20W
MF
201

2

1

R0721

100K

2

5%
MF

201

5

30

5

32
5
5

26
5

14 36
5

19

5

19

10 34

I2C0_SDA_1V8

5

19 25 30 36

I2C0_SCL_1V8

19 25 30 36

5

I2C1_SDA_1V8

5

22 36

I2C1_SCL_1V8

5

22 36

I2C2_SDA_3V0

5

22 36

I2C2_SCL_3V0

5

22 36

=PP1V8_H5

4 5 7

6 3

I2C PULL-UPS

NEED TO CHARACTERIZE RISE TIME
AND SIZE THESE RESISTORS

R0701

2.2K

5%
1/32W
MF
01005

1

2

1

2

R0702

2.2K

5%
1/32W
MF
01005

PP3V0_SENSOR_FLT

20 21

1

R0703

1.00K

5%
1/32W
MF
01005

2

1

R0704

1.00K

5%
1/32W
MF
01005

2

1

R0705

5%
1/32W
MF
01005

2

1

R0706

1.00K1.00K

5%
1/32W
MF
01005

2

SYNC_MASTER=N/A

PAGE TITLE

AP: I/Os

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

7 OF 154

SHEET

5 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

D

=PP1V8_NAND_H5

34

AB8
AB10
AB12
AB14
AB16
AB18
AB19
AB21
AB23
AB25
AB30

AC1

AC3

AC9
AC11
AC13
AC15
AC17

C

B

AC20
AC22
AC24

AD10
AD12
AD14
AD16
AD18
AD19
AD21
AD23
AD25

AE10
AE11
AE12
AE13
AE14
AE15
AE17
AE22
AE30
AE32

AF16

AG16
AG17
AG25

AD8

AE4

AE9

AF3

AG2

VSS

A6

U0600

BALI-H5G

BGA

SYM 12 OF 12

OMIT_TABLE

VSS

AH5
AH10
AH15
AH16
AH17
AH30
AH32
P24
AJ17
AJ27
AK2
AK8
AK14
AK17
AH1
AL3
AL7
AL10
AL13
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL1
AL29
AM1
AM2
AM6
AM9
AM12
AM15
AM32
AM33
AN1
AN2
AL33
T20
AN11
AN14
AN32
AN33
AN3
AN31
AN6
C1

6 9

1

R0832

100K

5%
1/32W
MF
01005

FMI1_CE0_L

6

13 38

FMI0_CE0_L

6

13 38

FMI0_CE0_L

6

13 38

OUT

NC_FMI0_CE1_L
NC_FMI0_CE2_L
NC_FMI0_CE3_L
NC_FMI0_CE4_L
NC_FMI0_CE5_L
NC_FMI0_CE6_L
NC_FMI0_CE7_L

BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT
OUT

34

6 9

6

FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>

NC_FMI0_RE
FMI0_ALE
FMI0_CLE
FMI0_WE_L
FMI0_RE_L
FMI0_DQS
NC_FMI0_DQSN

=PP1V8_NAND_H5

13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38

13 38
13 38
13 38
13 38
13 38

2

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

AN29
AM30
AL28
AL27
AJ32
AJ31
AM31
AL30

AM29
AK33
AJ30
AK31
AH28
AJ29
AN30
AH27

AK29
AJ28
AH29
AK32
AK30
AL31
AL32
AG27

AF26
AB26

AG28

1

R0831

100K

5%
1/32W
MF
01005

2

FMI0_CEN0
FMI0_CEN1
FMI0_CEN2
FMI0_CEN3
FMI0_CEN4
FMI0_CEN5
FMI0_CEN6
FMI0_CEN7

FMI0_IO0
FMI0_IO1
FMI0_IO2
FMI0_IO3
FMI0_IO4
FMI0_IO5
FMI0_IO6
FMI0_IO7

FMI0_WENN
FMI0_ALE
FMI0_CLE
FMI0_WEN
FMI0_REN
FMI0_DQS
FMI0_DQSN
FMI0_DQVREF

PVDDP_GRP1
PVDDP_GRP2

U0600

BALI-H5G

BGA

SYM 4 OF 12

OMIT_TABLE

FMI1_CEN0
FMI1_CEN1
FMI1_CEN2
FMI1_CEN3
FMI1_CEN4
FMI1_CEN5
FMI1_CEN6
FMI1_CEN7

FMI1_IO0
FMI1_IO1
FMI1_IO2
FMI1_IO3
FMI1_IO4
FMI1_IO5
FMI1_IO6
FMI1_IO7

FMI1_WENN

FMI1_ALE
FMI1_CLE
FMI1_WEN
FMI1_REN
FMI1_DQS

FMI1_DQSN

FMI1_DQVREF

PVDDP_GRP3
PVDDP_GRP4
PVDDP_GRP5

FMI1_VREFFMI0_VREF

AF29
AF30
AE29
AD30
AF27
AE27
AF28
AE28

AE33
AH33
AG33
AG30
AD31
AE31
AG29
AD29

CKPLUS_WAIVE=PDIFPR_BADTERMCKPLUS_WAIVE=PDIFPR_BADTERM

AG31
AJ33
AH31
AG32
AF31
AF32
AF33
AD27

P25
G19
K24

AD28

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

FMI1_CE0_L
NC_FMI1_CE1_L
NC_FMI1_CE2_L
NC_FMI1_CE3_L
NC_FMI1_CE4_L
NC_FMI1_CE5_L
NC_FMI1_CE6_L
NC_FMI1_CE7_L

FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>

NC_FMI1_RE
FMI1_ALE
FMI1_CLE
FMI1_WE_L
FMI1_RE_L
FMI1_DQS
NC_FMI1_DQSN

=PP1V8_VDDIO18_H5

FMI_DQVREF_H5FMI_DQVREF_H5

6

6

13 38

OUT

13 38

BI

13 38

BI

13 38

BI

13 38

BI

13 38

BI

13 38

BI

13 38

BI

13 38

BI

13 38

OUT

13 38

OUT

13 38

OUT

13 38

OUT

13 38

OUT

1

R0842

51.1K

34

4 6 7 9

1

R0843

51.1K

1%
1/32W
MF
01005

2

2

1%
1/32W
MF
01005

=PP1V8_NAND_H5

1

C0842

0.1UF

20%
4V

2

X5R
01005

1

C0843

0.1UF

20%
4V

2

X5R
01005

6 9

34

D

C

B

A

=PP1V8_NAND_H5

34

6 9

1

C0820

0.1UF

20%
4V

2

X5R
01005

1

C0821

0.1UF

20%
4V

2

X5R
01005

4 6 7 9

34

=PP1V8_VDDIO18_H5

1

C0810

0.1UF

20%
4V

2

X5R
01005

1

C0811

0.1UF

20%
4V

2

X5R
01005

6 3

1

C0812

0.1UF

20%
4V

2

X5R
01005

SYNC_MASTER=N/A

PAGE TITLE

AP: NAND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

8 OF 154

SHEET

6 OF 39

124578

SIZE

A

D

0.01UF

10%

6.3V
X5R
01005

0.01UF

10%

6.3V
X5R
01005

12

NOSTUFF

1

C0950

0.01UF

10%

6.3V

2

X5R
01005

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

9 OF 154

SHEET

7 OF 39

124578

4 6 7 9

34

4 6 7 9

34

SYNC_DATE=N/A

A.0.0

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PP1V0_DP_PAD_DVDD_H5

34

R0911

0

C0931

56PF

5%

6.3V
NP0-C0G
01005

1

R0932

1.00K

5%
1/32W
MF
01005

2

NO_TEST=TRUE

0.00

12

0%

MF

01005

0.00

12

MF0%

12

5%

1/20W

MF

201

NOSTUFF

FL0911

240-OHM-0.2A-0.8-OHM

1 2

0201

NOSTUFF

C0955

1

0.1UF

10%

6.3V

2

X5R
201

=PP1V8_H5

1

R0933

1.00K

5%
1/32W
MF
01005

2

ISP0_CAM_RF_RST_L
NC_ISP0_CAM_RF_FLASH
ISP0_CAM_RF_I2C_SCL
ISP0_CAM_RF_I2C_SDA

REAR FACING CAM

FRONT FACING CAM

ISP1_CAM_FF_I2C_SCL
ISP1_CAM_FF_I2C_SDA

R0900

ISP0_CAM_RF_CLK

ISP0_CAM_RF_SHUTDOWN

R0940

ISP1_CAM_FF_CLK

ISP1_CAM_FF_SHUTDOWN_L

IN
IN

IN
IN

1

C0928

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

NOSTUFF

1

R0950

6.34K

1%
1/20W
MF
201

2

21 37
21 37

21 37
21 37

1

2

34

DAC_AP_COMP_FTR

4 5 7

10 34

TP_EDP_AP_ANALOG_TEST

OUT

OUT

BI

OUT

BI

OUT
OUT

OUT
OUT

1

C0929

8.2PF

+/-0.5PF
16V
NP0-C0G-CERM
01005

C0930

56PF

5%

6.3V

2

NP0-C0G
01005

=PP1V0_EDP_PAD_DVDD_H5

NOSTUFF

1

C0956

0.1UF

10%

6.3V

2

X5R

DAC_AP_VREF

39

201

DAC_AP_IREF

DAC_AP_COMP

15 37

IN

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

NOTE: 0.6V ANALOG REF

AP_EDP_R_BIAS

NOSTUFF

1

C0957

0.01UF

10%

6.3V

2

X5R
01005

22

22 36

22 36

22 36

22 36

22 36
22

22 36
22

EDP_HPD

EDP_AUX_P
EDP_AUX_N

EDP_DATA_P<0>
EDP_DATA_N<0>

EDP_DATA_P<1>
EDP_DATA_N<1>

EDP_DATA_P<2>
EDP_DATA_N<2>

EDP_DATA_P<3>
EDP_DATA_N<3>

1

R0921

4.99K

1%
1/32W
MF
01005

2

SHUTDOWN IS ACTIVE HIGH

SHUTDOWN IS ACTIVE LOW

1

C0932

0.22UF

20%

6.3V

2

X5R
402

1

C0909

0.1UF

10%

6.3V

2

X5R
201

J24

K23

E18

C30
C29

A30
A29

D28
D27

B28
B27

C26
C25

E28

F28

SOCHOT1_L PULL-UP ON CSA 90

32

=PP1V8_EDP_H5

34

D

=PP1V8_VDDIO18_H5

4 6 7 9

34

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

?

REF DES

FL0910155S0725 155S0359

COMMENTS:

RDAR://PROBLEM/11104943

C

FL0910

80-OHM-0.2A-0.4-OHM

=PP1V0_MIPI_PLL_H5

34

=PP1V0_MIPI_H5

34

1

2

C0935

1UF

10%

6.3V
CERM
402

1 2

0201-1

1

C0908

0.1UF

10%

6.3V

2

X5R
201

1

C0903

0.1UF

10%

6.3V

2

X5R
201

1

C0980

1UF

10%

6.3V

2

CERM
402

1

C0904

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

PP1V0_MIPI_PLL_F

39

1

C0981

0.01UF

10%

6.3V

2

X5R
01005

B

NC_MIPI_VSYNC_H5

MIPI0C_CAM_RF_DATA_P<0>

21 37

IN

MIPI0C_CAM_RF_DATA_N<0>

21 37

IN

MIPI0C_CAM_RF_DATA_P<1>

21 37

IN

MIPI0C_CAM_RF_DATA_N<1>

21 37

IN

NC_MIPI0C_CAM_RF_DATA_P<2>
NC_MIPI0C_CAM_RF_DATA_N<2>

NC_MIPI0C_CAM_RF_DATA_P<3>
NC_MIPI0C_CAM_RF_DATA_N<3>

MIPI0C_CAM_RF_CLK_P

21 37

IN

MIPI0C_CAM_RF_CLK_N

21 37

IN

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

U27

AM22
AN22

AM21
AN21

AM19
AN19

AM18
AN18

AM20
AN20

MIPI_VSYNC

MIPI0C_DPDATA0
MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI0C_DPDATA2
MIPI0C_DNDATA2

MIPI0C_DPDATA3
MIPI0C_DNDATA3

MIPI0C_DPCLK
MIPI0C_DNCLK

A

TABLE_ALT_HEAD

TABLE_ALT_ITEM

VOLTAGE=1.0V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3MM

1

C0982

56PF

5%

6.3V

2

NP0-C0G
01005

AF20

AF21

AF22

AF23

AF24

MIPI_VDD10

40MA

3.3MA

BALI-H5G

SYM 5 OF 12

OMIT_TABLE

AG20

AH22

AH24

AH21

AH19

MIPI0D_VDD18

MIPI1D_VDD18

2MA

PER PIN

MIPI0D_VDD10_PLL

MIPI1D_VDD10_PLL

3.3MA

U0600

BGA

MIPI_VSS

AG21

AG22

AG23

AG24

=PP1V8_MIPI_H5

1

C0907

0.1UF

10%

6.3V

2

X5R
201

AH23

AH20

MIPI1D_VREG_0P4V

MIPI0D_VREG_0P4V

ISP0_FLASH

ISP0_PRE_FLASH

ISP0_SCL
ISP0_SDA

ISP1_FLASH

ISP1_PRE_FLASH

ISP1_SCL
ISP1_SDA

SENSOR0_CLK
SENSOR0_RST

SENSOR1_CLK
SENSOR1_RST

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

PP0V4_MIPI0D

PP0V4_MIPI1D

1

R0930

1.00K

5%
1/32W
MF
01005

2

M25
M31
AA27
U28

N25

SOCHOT1_L

L30

SOCHOT0_L

AA33
U30

V31

ISP0_CAM_RF_CLK_R

36

U32

U31

ISP1_CAM_FF_CLK_R

36

T27

AM23
AN23

NO_TEST=TRUE

AM25

NO_TEST=TRUE

AN25

AM24
AN24

34

VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3MM

1

2

1

2

1

2

C0960

2.2NF

10%
10V
X5R-CERM
0201

VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3MM

C0961

2.2NF

10%
10V
X5R-CERM
0201

1

R0931

1.00K

5%
1/32W
MF
01005

2

7

32

7

1/32W

1/32W 01005

MIPI1C_CAM_FF_DATA_P<0>
MIPI1C_CAM_FF_DATA_N<0>

NC_MIPI1C_CAM_FF_DATA_P<1>
NC_MIPI1C_CAM_FF_DATA_N<1>

MIPI1C_CAM_FF_CLK_P
MIPI1C_CAM_FF_CLK_N

1

C0910

8.2PF

+/-0.1PF%
25V

2

CER
0201

1

PP1V8_EDP_AVDD_AUX

39

1

C0933

0.22UF

20%

6.3V

2

X5R
402

C31

EDP_PAD_DVDD

15MA

DAC_VREF DAC_OUT3

DAC_IREF

DAC_COMP

EDP_HPD

EDP_PAD_AUXP
EDP_PAD_AUXN

EDP_PAD_TX0P
EDP_PAD_TX0N

EDP_PAD_TX1P
EDP_PAD_TX1N

EDP_PAD_TX2P
EDP_PAD_TX2N

EDP_PAD_TX3P
EDP_PAD_TX3N

EDP_PAD_R_BIAS

EDP_PAD_DC_TP

EDP_PAD_AVSS3

EDP_PAD_AVSS2

B26

B25

1

C0934

0.22UF

20%

6.3V

2

X5R
402

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3MM

D26

D25

D29

B31

EDP_PAD_AVDDX

EDP_PAD_AVDD3

EDP_PAD_AVDD2

EDP_PAD_AVDDP0

65MA

PER PIN

22MA

10MA

EDP_PAD_AVSS0

EDP_PAD_DVSS

D31

A28

C32

EDP_PAD_AVSSX

EDP_PAD_AVSS1

A27

C28

C27

D30

EDP_PAD_AVDD1

EDP_PAD_AVDD0

EDP_PAD_AVDD_AUX

16MA

BALI-H5G

SYM 6 OF 12

OMIT_TABLE

EDP_PAD_AVSSP0

EDP_PAD_AVSS_AUX

B30

B29

C23

C24

DP_PAD_DVDD

15MA

U0600

BGA

DP_PAD_DVSS

A24

DP_PAD_AVDDX

22MA

=PP1V8_H5

NOSTUFF

7

7

SOCHOT1_L
SOCHOT0_L

1

R0942

100K

5%
1/32W
MF
01005

2

1

R0941

100K

5%
1/32W
MF
01005

2

2

A20

D21

DP_PAD_AVDD3

DP_PAD_AVDDP0

65MA

PER PIN

10MA

DP_PAD_AVSSP0

DP_PAD_AVSSX

B21

A23

C0927

0.1UF

20%

4V
X5R
01005

E20

B20

DP_PAD_AVDD2

DP_PAD_AVDD1

DP_PAD_AVSS3

DP_PAD_AVSS1

F20

C20

4 5 7

E21

D22

DP_PAD_AVDD0

DP_PAD_AVDD_AUX

16MA

DP_PAD_AUXP
DP_PAD_AUXN

DP_PAD_TX0P
DP_PAD_TX0N

DP_PAD_TX1P
DP_PAD_TX1N

DP_PAD_TX2P
DP_PAD_TX2N

DP_PAD_TX3P
DP_PAD_TX3N

DP_PAD_R_BIAS

DP_PAD_DC_TP

DP_PAD_AVSS2

DP_PAD_AVSS0

DP_PAD_AVSS_AUX

F21

D20

B22

10 34

=PP1V8_DP_H5

1

C0924

56PF

5%

6.3V

2

NP0-C0G
01005

H24

H23

DAC_AVDD18D

DAC_AVDD18A

15MA

15MA

DAC_OUT2

DAC_OUT1

DP_HPD

DAC_AVSS18D

G23

34

1

C0951

0.1UF

20%
4V

2

X5R
01005

NO_TEST=TRUE

D33J23

NO_TEST=TRUE

E33

NO_TEST=TRUE

F33

NO_TEST=TRUE

B18

NO_TEST=TRUE

A26

NO_TEST=TRUE

A25

NO_TEST=TRUE

D24

NO_TEST=TRUE

D23

NO_TEST=TRUE

B24

NO_TEST=TRUE

B23

NO_TEST=TRUE

C22

NO_TEST=TRUE

C21

NO_TEST=TRUE

A22

NO_TEST=TRUE

A21

E23

F23

TP_DP_AP_ANALOG_TEST

DAC_AVSS18A

G24

SYNC_MASTER=N/A

PAGE TITLE

NC_DAC_AP_OUT3

NC_DAC_AP_OUT2

NC_DAC_AP_OUT1

NC_DP_HPD

NC_DP_AUX_P
NC_DP_AUX_N

NC_DP_DATA_P<0>
NC_DP_DATA_N<0>

NC_DP_DATA_P<1>
NC_DP_DATA_N<1>

NC_DP_DATA_P<2>
NC_DP_DATA_N<2>

NC_DP_DATA_P<3>
NC_DP_DATA_N<3>

DP_R_BIAS

NOTE: 0.6V ANALOG REF

AP: TV,DP,MIPI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

=PP1V8_VDDIO18_H5

1

C0953

2

=PP1V8_VDDIO18_H5

1

C0952

2

1

R0920

4.99K

1%
1/32W
MF
01005

2

6 3

8 7 6 5 4 3

WWW.AliSaler.Com

12

NO_TEST=TRUE

NO_TEST=TRUE

1

2

C1022

0.22UF

20%

6.3V
X5R

0201

AH11
AG11
AG12
AH12
AG13

AH14
AH13
AN10

AB2
AB3
AC2
AC4
AD2
AD3
AE2
AE3
AF2
AF4
AG5
AH2
AJ2
AG3
AH3
AJ3

AA3
AA4
AA5
AK3
AL2
AM3
AM4
AL4
AL5
AK5
AJ5

AH6
AG6
AH7
AG7
AH8

AD4
AG4
AB6
AK4

AA1
AB1
AG1
AF1

AK1
AJ1

AN9
AH9
AG9
AG8
AB4

W2
W4
Y2
Y3
Y4

V1
W1

Y8

DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31

DDR2_CA0
DDR2_CA1
DDR2_CA2
DDR2_CA3
DDR2_CA4
DDR2_CA5
DDR2_CA6
DDR2_CA7
DDR2_CA8
DDR2_CA9

DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3

DDR2_NDQS0
DDR2_PDQS1
DDR2_NDQS1
DDR2_PDQS2
DDR2_NDQS2
DDR2_PDQS3
DDR2_NDQS3

DDR2_CK
DDR2_CKB
DDR2_CKE0
DDR2_CKE1
DDR2_RREF
DDR2_CSN0
DDR2_CSN1
DDR2_VREF_DQ
DDR2_VDD_CKE

U0600

BALI-H5G

BGA

SYM 8 OF 12

OMIT_TABLE

DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31

DDR3_PDQS0DDR2_PDQS0
DDR3_NDQS0
DDR3_PDQS1
DDR3_NDQS1
DDR3_PDQS2
DDR3_NDQS2
DDR3_PDQS3
DDR3_NDQS3

DDR3_CKE0
DDR3_CKE1
DDR3_RREF
DDR3_CSN0

DDR3_CSN1
DDR3_VREF_DQ
DDR3_VDD_CKE

1

2

NO_TEST=TRUE

NO_TEST=TRUE

C1020

0.22UF

20%

6.3V
X5R

0201

B14
B13
D13
C12
D12
B11
C11
B10

B17
C17
B16
E17
D16
E16
C15
D15

E12

C14

A13
A12

A16
A15

D10
H15

C9
D9
B8
C8
B7
B6
C6
D7

E6
B5
C5
E5
C4
D4
B3
C3

G5
G6
H5
H6
J5
M5
M6
N6
P5
P6

E9

D6

A7
A8

A4
A5

P4
N4
J1
K1
M4
K6
J6

DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31

DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CA6
DDR0_CA7
DDR0_CA8
DDR0_CA9

DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3

DDR0_PDQS0
DDR0_NDQS0
DDR0_PDQS1
DDR0_NDQS1
DDR0_PDQS2
DDR0_NDQS2
DDR0_PDQS3
DDR0_NDQS3

DDR0_CK
DDR0_CKB
DDR0_CKE0
DDR0_CKE1
DDR0_RREF
DDR0_CSN0
DDR0_CSN1
DDR0_VREF_DQ
DDR0_VDD_CKE

U0600

BALI-H5G

BGA

SYM 7 OF 12

OMIT_TABLE

DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR1_DQ16
DDR1_DQ17
DDR1_DQ18
DDR1_DQ19
DDR1_DQ20
DDR1_DQ21
DDR1_DQ22
DDR1_DQ23
DDR1_DQ24
DDR1_DQ25
DDR1_DQ26
DDR1_DQ27
DDR1_DQ28
DDR1_DQ29
DDR1_DQ30
DDR1_DQ31

DDR1_PDQS0
DDR1_NDQS0
DDR1_PDQS1
DDR1_NDQS1
DDR1_PDQS2
DDR1_NDQS2
DDR1_PDQS3
DDR1_NDQS3

DDR1_CKE0
DDR1_CKE1
DDR1_RREF
DDR1_CSN0

DDR1_CSN1
DDR1_VREF_DQ
DDR1_VDD_CKE

DDR0_DQ<0>

11 38

BI

DDR0_DQ<1>

11 38

BI

DDR0_DQ<2>

11 38

BI

DDR0_DQ<3>

11 38

BI

DDR0_DQ<4>

11 38

BI

DDR0_DQ<5>

11 38

BI

DDR0_DQ<6>

11 38

D

C

B

1

R1020

240

1%
1/20W
MF
201

2

BI

DDR0_DQ<7>

11 38

BI

DDR0_DQ<8>

11 38

BI

DDR0_DQ<9>

11 38

BI

DDR0_DQ<10>

11 38

BI

DDR0_DQ<11>

11 38

BI

DDR0_DQ<12>

11 38

BI

DDR0_DQ<13>

11 38

BI

DDR0_DQ<14>

11 38

BI

DDR0_DQ<15>

11 38

BI

DDR0_DQ<16>

11 38

BI

DDR0_DQ<17>

11 38

BI

DDR0_DQ<18>

11 38

BI

DDR0_DQ<19>

11 38

BI

DDR0_DQ<20>

11 38

BI

DDR0_DQ<21>

11 38

BI

DDR0_DQ<22>

11 38

BI

DDR0_DQ<23>

11 38

BI

DDR0_DQ<24>

11 38

BI

DDR0_DQ<25>

11 38

BI

DDR0_DQ<26>

11 38

BI

DDR0_DQ<27>

11 38

BI

DDR0_DQ<28>

11 38

BI

DDR0_DQ<29>

11 38

BI

DDR0_DQ<30>

11 38

BI

DDR0_DQ<31>

11 38

BI

DDR0_CA<0>

11 38

OUT

DDR0_CA<1>

11 38

OUT

DDR0_CA<2>

11 38

OUT

DDR0_CA<3>

11 38

OUT

DDR0_CA<4>

11 38

OUT

DDR0_CA<5>

11 38

OUT

DDR0_CA<6>

11 38

OUT

DDR0_CA<7>

11 38

OUT

DDR0_CA<8>

11 38

OUT

DDR0_CA<9>

11 38

OUT

DDR0_DM<0>

11 38

OUT

DDR0_DM<1>

11 38

OUT

DDR0_DM<2>

11 38

OUT

DDR0_DM<3>

11 38

OUT

DDR0_DQS_P<0>

11 38

BI

DDR0_DQS_N<0>

11 38

BI

DDR0_DQS_P<1>

11 38

BI

DDR0_DQS_N<1>

11 38

BI

DDR0_DQS_P<2>

11 38

BI

DDR0_DQS_N<2>

11 38

BI

DDR0_DQS_P<3>

11 38

BI

DDR0_DQS_N<3>

11 38

BI

DDR0_CK_P

11 38

OUT

DDR0_CK_N

11 38

OUT

DDR0_CKE<0>

11 38

OUT

NC_DDR0_CKE<1>
H5G_DDR0_ZQ H5G_DDR2_ZQ
DDR0_CSN<0>

11 38

OUT

NC_DDR0_CSN<1>

PPVREF_DDR0_DQ_H5

8 8

=PP1V2_S2R_H5 =PP1V2_S2R_H5

34

8

DDR1_DQ0
DDR1_DQ1
DDR1_DQ2
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9

DDR1_CA0
DDR1_CA1
DDR1_CA2
DDR1_CA3
DDR1_CA4
DDR1_CA5
DDR1_CA6
DDR1_CA7
DDR1_CA8
DDR1_CA9

DDR1_DM0
DDR1_DM1
DDR1_DM2
DDR1_DM3

DDR1_CK

DDR1_CKB

H2
H3
J3
J4
K2
L2
K4
K5
N2
P2
P3
R3
T2
R4
T3
T4
C2
D2
E2
E4
E3
F3
F4
G2
U3
V2
V3
U5
V4
V5
U6
V6

E15
F15
F14
E14
F13
E8
F8
F7
E7
F6

L5
N5
G4
R5

G1
H1
N1
M1
D1
E1
T1
R1

F11
F12
A10

NO_TEST=TRUE

A9
E11
F10

NO_TEST=TRUE

E13
L3

PPVREF_DDR1_DQ_H5

H8

DDR1_DQ<0>
DDR1_DQ<1>
DDR1_DQ<2>
DDR1_DQ<3>
DDR1_DQ<4>
DDR1_DQ<5>
DDR1_DQ<6>
DDR1_DQ<7>
DDR1_DQ<8>
DDR1_DQ<9>
DDR1_DQ<10>
DDR1_DQ<11>
DDR1_DQ<12>
DDR1_DQ<13>
DDR1_DQ<14>
DDR1_DQ<15>
DDR1_DQ<16>
DDR1_DQ<17>
DDR1_DQ<18>
DDR1_DQ<19>
DDR1_DQ<20>
DDR1_DQ<21>
DDR1_DQ<22>
DDR1_DQ<23>
DDR1_DQ<24>
DDR1_DQ<25>
DDR1_DQ<26>
DDR1_DQ<27>
DDR1_DQ<28>
DDR1_DQ<29>
DDR1_DQ<30>
DDR1_DQ<31>

DDR1_CA<0>
DDR1_CA<1>
DDR1_CA<2>
DDR1_CA<3>
DDR1_CA<4>
DDR1_CA<5>
DDR1_CA<6>
DDR1_CA<7>
DDR1_CA<8>
DDR1_CA<9>

DDR1_DM<0>
DDR1_DM<1>
DDR1_DM<2>
DDR1_DM<3>

DDR1_DQS_P<0>
DDR1_DQS_N<0>
DDR1_DQS_P<1>
DDR1_DQS_N<1>
DDR1_DQS_P<2>
DDR1_DQS_N<2>
DDR1_DQS_P<3>
DDR1_DQS_N<3>

DDR1_CK_P
DDR1_CK_N

DDR1_CKE<0>
NC_DDR1_CKE<1>
H5G_DDR1_ZQ
DDR1_CSN<0>
NC_DDR1_CSN<1>

=PP1V2_S2R_H5

1

C1021

0.22UF

20%

6.3V

2

X5R

0201

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

BI

11 38

OUT

11 38

OUT

11 38

OUT

11 38

OUT

8

8

34

1

R1021

240

1%
1/20W
MF
201

2

1

R1022

240

1%
1/20W
MF
201

2

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

8

34

DDR2_DQ<0>
DDR2_DQ<1>
DDR2_DQ<2>
DDR2_DQ<3>
DDR2_DQ<4>
DDR2_DQ<5>
DDR2_DQ<6>
DDR2_DQ<7>
DDR2_DQ<8>
DDR2_DQ<9>
DDR2_DQ<10>
DDR2_DQ<11>
DDR2_DQ<12>
DDR2_DQ<13>
DDR2_DQ<14>
DDR2_DQ<15>
DDR2_DQ<16>
DDR2_DQ<17>
DDR2_DQ<18>
DDR2_DQ<19>
DDR2_DQ<20>
DDR2_DQ<21>
DDR2_DQ<22>
DDR2_DQ<23>
DDR2_DQ<24>
DDR2_DQ<25>
DDR2_DQ<26>
DDR2_DQ<27>
DDR2_DQ<28>
DDR2_DQ<29>
DDR2_DQ<30>
DDR2_DQ<31>

DDR2_CA<0>
DDR2_CA<1>
DDR2_CA<2>
DDR2_CA<3>
DDR2_CA<4>
DDR2_CA<5>
DDR2_CA<6>
DDR2_CA<7>
DDR2_CA<8>
DDR2_CA<9>

DDR2_DM<0>
DDR2_DM<1>
DDR2_DM<2>
DDR2_DM<3>

DDR2_DQS_P<0>
DDR2_DQS_N<0>
DDR2_DQS_P<1>
DDR2_DQS_N<1>
DDR2_DQS_P<2>
DDR2_DQS_N<2>
DDR2_DQS_P<3>
DDR2_DQS_N<3>

DDR2_CK_P
DDR2_CK_N
DDR2_CKE<0>
NC_DDR2_CKE<1>

DDR2_CSN<0>
NC_DDR2_CSN<1>

PPVREF_DDR2_DQ_H5

DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9

DDR3_CA0
DDR3_CA1
DDR3_CA2
DDR3_CA3
DDR3_CA4
DDR3_CA5
DDR3_CA6
DDR3_CA7
DDR3_CA8
DDR3_CA9

DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3

DDR3_CK

DDR3_CKB

AL8
AL9
AK9
AJ9
AM10
AJ10
AK10
AL11
AM11
AL12
AK12
AJ12
AM13
AK13
AJ13
AJ14
AM5
AL6
AK6
AJ6
AM7
AK7
AJ7
AM8
AM14
AL14
AJ15
AK15
AL15
AJ16
AK16
AM16

W5
W6
Y5
Y6
AA6
AD6
AE5
AE6
AF6
AF5

AK11
AG14
AJ8
AG15

AN7
AN8
AN13
AN12
AN4
AN5
AN16
AN15

AH4
AJ4
AD1

NO_TEST=TRUE

AE1
AB5
AC6

NO_TEST=TRUE

AC5
AJ11

PPVREF_DDR3_DQ_H5

AE8

DDR3_DQ<0>
DDR3_DQ<1>
DDR3_DQ<2>
DDR3_DQ<3>
DDR3_DQ<4>
DDR3_DQ<5>
DDR3_DQ<6>
DDR3_DQ<7>
DDR3_DQ<8>
DDR3_DQ<9>
DDR3_DQ<10>
DDR3_DQ<11>
DDR3_DQ<12>
DDR3_DQ<13>
DDR3_DQ<14>
DDR3_DQ<15>
DDR3_DQ<16>
DDR3_DQ<17>
DDR3_DQ<18>
DDR3_DQ<19>
DDR3_DQ<20>
DDR3_DQ<21>
DDR3_DQ<22>
DDR3_DQ<23>
DDR3_DQ<24>
DDR3_DQ<25>
DDR3_DQ<26>
DDR3_DQ<27>
DDR3_DQ<28>
DDR3_DQ<29>
DDR3_DQ<30>
DDR3_DQ<31>

DDR3_CA<0>
DDR3_CA<1>
DDR3_CA<2>
DDR3_CA<3>
DDR3_CA<4>
DDR3_CA<5>
DDR3_CA<6>
DDR3_CA<7>
DDR3_CA<8>
DDR3_CA<9>

DDR3_DM<0>
DDR3_DM<1>
DDR3_DM<2>
DDR3_DM<3>

DDR3_DQS_P<0>
DDR3_DQS_N<0>
DDR3_DQS_P<1>
DDR3_DQS_N<1>
DDR3_DQS_P<2>
DDR3_DQS_N<2>
DDR3_DQS_P<3>
DDR3_DQS_N<3>

DDR3_CK_P
DDR3_CK_N
DDR3_CKE<0>

NC_DDR3_CKE<1>

H5G_DDR3_ZQ
DDR3_CSN<0>

NC_DDR3_CSN<1>

=PP1V2_S2R_H5

1

C1023

0.22UF

20%

6.3V

2

X5R

0201

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

BI

12 38

OUT

12 38

OUT

12 38

OUT

12 38

OUT

8

34

8

1

R10234

240

1%
1/20W
MF
201

2

D

C

B

=PP1V2_VDDIOD_H5

34

8 9

A

1

R1053

4.7K

1%
1/32W
MF
01005

2

1

R1054

4.7K

1%
1/32W
MF
01005

2

1

C1057

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR0_DQ_H5

1

C1054

0.01UF

10%

6.3V

2

X5R

01005

VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP1V2_VDDIOD_H5

34

=PP1V2_VDDIOD_H5

8 9

34

8

1

R1055

4.7K

1%
1/32W
MF
01005

2

1

R1056

4.7K

1%
1/32W
MF
01005

2

1

C1058

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR1_DQ_H5

1

C1056

0.01UF

10%

6.3V

2

X5R

01005

VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

8

8 9

1

R1083

4.7K

1%
1/32W
MF
01005

2

1

R1084

4.7K

1%
1/32W
MF
01005

2

1

C1085

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR2_DQ_H5

1

C1084

0.01UF

10%

6.3V

2

X5R

01005

VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

6 3

=PP1V2_VDDIOD_H5

34

8 9

1

R1095

4.7K

1%
1/32W
MF
01005

2

1

R1096

4.7K

1%
1/32W
MF
01005

2

1

C1095

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR3_DQ_H5

1

C1096

0.01UF

10%

6.3V

2

X5R

01005

VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

8 8

SYNC_MASTER=N/A

PAGE TITLE

AP: DDR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

10 OF 154

SHEET

8 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

=PPVDD_CPUB_H5

34

1

C1147

4.3UF

20%

4V

2

X5R-CERM

0610

=PPVDD_SOC_H5

34

9

D

VDD

C1103

10UF

6.3V

20%
X5R

603

1

2

U10
U12
U14
U16
U22
U24
V9
V11
V13
V15
V17
V25
W8
W10
W12
W14
W16
T19
W26
Y9
Y11
Y13
Y15
Y17
Y26
AA8
AA10
AA12
AA14
AA16
AA18
AA26
AB9
AB11
AB13
AB15
AB17
AC8
AC10
AC12
AC14
AC16
AC18
AD9
AD11
AD13
AD15
AD17
AE16
AE18
AF17
U20
R18
R24

C1104

10UF

6.3V

J8
J10
J12
J14
J22

K9
K11
K13
K15
K21

L8
L10
L12
L14
L16
L18
L20
L22

M9
M11
M13
M15
M17

C

B

=PPVDD_SOC_H5

9

34

M19
M21
M23

9500MA MAX

N8

VDD

N10
N12
N14
N16
N18
N20
N22

P9
P11
P15
P17
P19
P21
P23

R8
R10
R12
R14
R16
R20
R22

T9
T11
T13
T15
T17
T21
T23

U8

1

C1100

10UF 10UF

20%

6.3V
X5R
603

C1101

2

6.3V

20%
X5R

603

U0600

BALI-H5G

SYM 10 OF 12

OMIT_TABLE

1

2

BGA

C1102

10UF

6.3V

20%
X5R

603

1

2

1

C1148

4.3UF

20%

4V

2

X5R-CERM

0610

=PPVDD_CPU0_H5

34

=PPVDD_CPU1_H5

34

=PPVDD_SRAM_H5

34

1

C1179

10UF

20%

6.3V

2

X5R
603

34

1

C1105

20%

2

X5R
603

C1149

1UF

20%

6.3V
X5R

0201

1

C1161

1UF

20%

6.3V

2

X5R

0201

C1173

1UF

20%

6.3V
X5R

0201

C1180

4.3UF

20%

4V

X5R-CERM

0610

=PP3V0_VDDIO30_H5

9

34

=PP3V0_VDDIO30_H5

9

34

=PP1V8_NAND_H5

6

34

=PP1V8_VDDIO18_H5

4 6 7 9

1

10UF

20%

6.3V

2

X5R
603

1

2

C1162

1

2

1

2

1

C1150

1UF

20%

6.3V

2

X5R

CERM-X5R-1

0201

1

1UF

20%

6.3V

2

X5R

0201

1

C1174

1UF

20%

6.3V

2

X5R

0201

1

C1181

4.3UF

20%

4V

2

X5R-CERM

0610

1

CA193

10UF

20%

6.3V 6.3V

2

CERM-X5R
0402-1

1

C1151

0.47UF 0.47UF

20%
201

C1155

4.3UF

X5R-CERM

0610

C1163

1UF

20%

6.3V
X5R

0201

C1167

4.3UF

X5R-CERM

0610

C1175

1UF

20%

6.3V
X5R

0201

C1182

1UF

20%

6.3V
X5R

0201

CA185

10UF

20%

6.3V
X5R
603

1

CA194

4.3UF

20%
4V

2

X5R-CERM
0610

4V

20%

20%

4V

1

2

4V

2

CERM-X5R-1

1

2

1

2

1

2

1

2

1

2

1

CA189

2

1

CA150

2

C1152

C1156

4.3UF

X5R-CERM

C1164

1UF

6.3V
0201

C1168

4.3UF

X5R-CERM

C1176

C1183

CA186

0.22UF

0.22UF

20%

6.3V
X5R
0201

1

2

0.22UF

20%

6.3V
X5R
0201

0610

20%
X5R

0610

1UF

6.3V
0201

1UF

6.3V
0201

6.3V
0201

1

20%

4V

2

201

20%

4V

1

2

20%

4V

1

20%

2

X5R

1

20%

2

X5R

20%
X5R

CA195

1UF

10%

6.3V
CERM
402

X5R-CERM

1

2

X5R-CERM

1

2

X5R-CERM

0.47UF

CERM-X5R-1

1

0.22UF

2

1

CA190

0.22UF

20%

6.3V

2

X5R
0201

1

CA151

0.22UF

20%

6.3V

2

X5R
0201

C1153

0.1UF

C1157

C1165

0.1UF

C1169

C1177

0.1UF

C1184

CA187

20%

6.3V

01005

1UF

20%

6.3V
X5R

0201

20%

6.3V

01005

1UF

20%

6.3V
X5R

0201

20%

6.3V

01005

20%
201

20%

6.3V
X5R

0201

1

CA196

10UF

20%

6.3V

2

CERM-X5R
0402-1

4V

1

2

1

2

1

2

1

2

1

2

1

2

CERM-X5R-1

1

2

1

CA191

0.22UF

20%

6.3V

2

X5R
0201

1

CA152

0.22UF

20%

6.3V

2

X5R
0201

C1154

X5R-CERM

C1158

C1166

X5R-CERM

C1170

C1178

X5R-CERM

C1185

0.47UF

0.22UF

1

0.1UF

20%

2

1

1UF

20%

2

X5R

1

20%

2

1

1UF

20%

2

X5R

1

20%

2

1

20%

4V

2

201

1

20%

2

X5R

10UF

20%
CERM-X5R

0402-1

+/-0.5PF

NP0-C0G-CERM

+/-0.5PF

NP0-C0G-CERM

+/-0.5PF

NP0-C0G-CERM

+/-0.5PF

NP0-C0G-CERM

1

CA192

0.22UF

20%

6.3V

2

X5R
0201

1

CA153

0.22UF

20%

6.3V

2

X5R
0201

6.3V

01005

6.3V 6.3V
0201

0.1UF

6.3V

01005

6.3V
0201

0.1UF

6.3V

01005

CA188

6.3V
0201

1

CA197

2

1

C11B0

8.2PF

16V

2

NP0-C0G-CERM

01005

1

C1159

1UF 1UF

20%

2

X5R

0201

1

C11C0

8.2PF

16V

2

NP0-C0G-CERM

01005

1

C1171

1UF

20%

6.3V

2

X5R

0201

1

C11D0

8.2PF

16V

2

NP0-C0G-CERM

01005

1

C11E0

8.2PF

16V

2

NP0-C0G-CERM

01005

1

CA198

1UF

10%

6.3V

2

CERM
402

C11B1

8.2PF

+/-0.5PF

01005

C1160

6.3V
0201

C11C1

8.2PF

+/-0.5PF

01005

C1172

1UF

6.3V
0201

C11D1

8.2PF

+/-0.5PF

01005

C11E1

8.2PF

+/-0.5PF

01005

CRITICAL

1

CA199

0.47UF

20%
4V

2

X7S
0204

16V

20%
X5R

16V

20%
X5R

16V

16V

1

2

1

2

1

2

1

2

1

2

1

2

1

C11F0

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

V20
V22
V24
Y20
Y22
Y24

AA21
AB20
AB22
AC19
AC21
AD20
AE19
AE21

AA23
AB24
AC23
AC25
AD22
AD24
AE23
AE25

AA19
AA25

W19
W21
W23
W25

N28

VDDIO30_GRP1

F18

VDDIO30_GRP2

K25

VDDIO30_GRP3

J20

VDDIOD0

K20

VDDIOD1

AG26
AH26
AJ26

AC26
AD26
AE26

AE20

VDD_ANA0

AE24

VDD_ANA1

W18

VDD_ANA_TMPSADC0

P13

VDD_ANA_TMPSADC1

VDD_CPUB

1.1A@1.1V

VDD_CPU0

2.5A@1.1V

2.5A@1.1V

VDD_CPU1

550MA@1.1V

VDD_SRAM

52MA

2MA

2MA

VDDIOD2

45MA

VDDIOD3

45MA

5MA

5MA

U0600

BALI-H5G

BGA

SYM 9 OF 12

OMIT_TABLE

FAST SCAN CLK
GPIO_3V0
USB11

SPI3

I2C2

FMI0-3 (1.8V)

FMI1-3 (1.8V)

TEMP SENSOR

ANALOG

VDDIOD

1000MA@1.2V

12MA

VDDIO18_GRP1

45MA

VDDIO18_GRP2

18MA

VDDIO18_GRP3

35MA

VDDIO18_GRP4

10MA

VDDIO18_GRP5

12MA

VDDIO18_GRP6

G7
G8
G9
G10
G11
G12
G13
G14
G15
H7
J7
K7
L7
M7
N7
P7
R7
T7
U7
V7
W7
Y7
AA7
AB7
AC7
AD7
AE7
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15

H18

H26
J27
K27
L27

N29

U25
U26
V26

AF25

AH18

C1193

1UF

6.3V
0201

C1194

1UF

6.3V
0201

C1143

0.22UF

6.3V
0201

1

C1198

0.22UF

20%

6.3V

2

X5R
0201

20%
X5R

20%
X5R

20%
X5R

1

2

1

2

1

2

C1190

4.3UF

X5R-CERM

0610

C1195

0.47UF

CERM-X5R-1

C1144

0.22UF

6.3V
0201

1

C1191

4.3UF

2

1

2

CERM-X5R-1

1

2

X5R-CERM

0610

C1196

0.47UF

20%

20%

20%
201

20%
X5R

4V

4V

=PP1V8_VDDIO18_H5

1

C1199

0.22UF

20%

6.3V

2

X5R
0201

4V

20%
201

4V

1

2

1

2

1

2

C1145

56PF

5%

6.3V
NP0-C0G
01005

12

=PP1V2_VDDIOD_H5

1

C1192

10UF

20%

6.3V

2

X5R
603

C1197

0.22UF

20%

6.3V
X5R

0201

4 6 7 9

34

8

34

D

C1142

0.22UF

6.3V
0201

20%
X5R

1

2

1

2

C

B

C1107

4.3UF

X5R-CERM

0610

C1120

0.47UF0.47UF

C1130

20%

6.3V
X5R

0201

20%

20%

4V

4V

1

2

1

2

1

2

CERM-X5R-1

1

C1106

4.3UF

20%

4V

2

X5R-CERM

0610

1

C1119

A

C1128

0.22UF

20%

6.3V
X5R

0201

CERM-X5R-1

1

2

20%
201

C1129

0.22UF

20%

6.3V
X5R

0201

4V

2

CERM-X5R-1

1

0.22UF

2

C1108

4.3UF

X5R-CERM

C1121

0.47UF

C1131

0.22UF

6.3V
0201

20%

0610

20%
X5R

20%
201201

4V

4V

1

2

1

2

1

2

CERM-X5R-1

C1109

4.3UF

X5R-CERM

0610

C1122

0.47UF

C1132

0.22UF

6.3V
0201

20%

20%
X5R

1

4V

2

1

20%

4V

2

201

1

2

C1110

4.3UF

20%

X5R-CERM

0610

C1123

0.47UF

CERM-X5R-1

C1133

0.22UF

20%

6.3V
X5R

0201

1

4V

2

1

20%

4V

2

201

1

0.22UF

2

C1111

4.3UF

20%

X5R-CERM

0610

C1124

0.47UF

CERM-X5R-1

C1134

20%

6.3V
X5R

0201

1

4V

2

1

20%

4V

2

201

1

2

0.47UF

CERM-X5R-1

C1135

0.22UF

6.3V
0201

C1125

20%
X5R

1

C1113

1UF

10%

6.3V

2

CERM
402

20%

4V

201

1

2

1

2

1

2

C1126

0.47UF

CERM-X5R-1

C1114

1UF

10%

6.3V
CERM
402

20%

4V

201

1

2

C1136

0.1UF

X5R-CERM

01005

20%

6.3V

1

C1115

1UF

10%

6.3V

2

CERM
402

1

2

C1137

0.1UF

6.3V

X5R-CERM

01005

1

C1116

1UF

10%

6.3V

2

CERM
402

20%

1

C1117

1UF

10%

6.3V

2

CERM
402

1

C1138

0.1UF

20%

2

6.3V

X5R-CERM

01005

1

C1118

1UF

10%

6.3V

2

CERM
402

1

2

C1139

0.1UF

6.3V

X5R-CERM

01005

20%

1

2

C1140

0.1UF

20%

6.3V

X5R-CERM

01005

1

2

C1141

0.1UF

6.3V

X5R-CERM

01005

20%

1

2

NP0-C0G-CERM

C11A0

8.2PF

+/-0.5PF

01005

16V

1

2

C11A1

8.2PF

+/-0.5PF

NP0-C0G-CERM

01005

16V

PART NUMBER

138S0702 138S0657

1

2

ALTERNATE FOR
PART NUMBER

C1106,C1107,C1108,C1109,C1110,C1111,C1147,C1148,C1155,C1156,C1167,C1168,C1180,C1181,C1190,C1191,C1315,C1321,C1415,C1421,CA194

BOM OPTION

SYNC_MASTER=N/A

PAGE TITLE

REF DES

COMMENTS:

QTY 21 RDAR://PROBLEM/8837828

AP: POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

11 OF 154

SHEET

9 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

BOOT CONFIG ID

BOOT_CONFIG[3]
BOOT_CONFIG[2]

D

BOOT_CONFIG[1]
BOOT_CONFIG[0]

CURRENT SETTING --->

=PP1V8_H5

10 34

4 5 7

GPIO_BOOT_CONFIG_3

5

OUT

GPIO_BOOT_CONFIG_2

5

OUT

GPIO_BOOT_CONFIG_1

5

OUT

GPIO_BOOT_CONFIG_0

5

OUT

BOOT_CONFIG[3-0]
FMI0/1 2/2 CS

1100
1101

FMI0/1 4/4 CS

1110

FMI0/1 4/4 CS WITH TEST

STUFF FOR FORM FACTOR BOARD

1

R1200

10K

5%
1/32W
MF
01005

2

1

R1201

10K

5%
1/32W
MF
01005

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

NOSTUFF

1

R1202

10K

5%
1/32W
MF
01005

2

NOSTUFF

1

R1203

10K

5%
1/32W
MF
01005

2

JTAG

R1210

100

12

5%

1/32W

MF

01005

R1211

100

12

5%

1/32W

MF

01005

JTAG_AP_TRST_L

JTAG_AP_SEL

4

OUT

D

36 39

4

OUT

FOR REFERENCE

BOOT_CONFIG[3:0]

0000 SPI0
0001 SPI1
0010 SPI0 W/TEST
0011 SPI1 W/TEST
0100 FMI0 2CS
0101 FMI0 4CS
0110 FMI0 4CS W/TEST
0111 RESERVED
1000 FMI1 2 CS
1001 FMI1 4 CS
1010 FMI1 4CS W/TEST
1100 FMI0/1 2/2 CS
1101 FMI0/1 4/4 CS
1110 FMI0/1 4/4 CS W/TEST

C

1111 RESERVED

R1260

100K

12

5%

1/32W

MF

BOARD ID

BOARD_ID[3]
BOARD_ID[2]

BOARD_ID[1]
BOARD_ID[0]

BOARD_ID[3-0]

B

0000
0001
0010
0011
0100
0101
1010
1011
1110
1111

=PP1V8_H5

10 34

4 5 7

GPIO_BOARD_ID_3

5

OUT

GPIO_BOARD_ID_2

5

OUT

GPIO_BOARD_ID_1

5

OUT

GPIO_BOARD_ID_0

5

OUT

X140 AP WLAN (MLB A)
X140 DEV WLAN
X140 AP BB_41 (MLB B)
X140 DEV BB_41
X140 AP BB_42 (MLB C)
X140 DEV BB_42
X140 AP BB_26A (MLB D)
X140 DEV BB_26A
X140 AP BB_26 (MLB E)
X140 DEV BB_26

MLB_D&MLB_E

1

R1220

10K

5%
1/32W
MF
01005

2

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

1

2

S/W READ FLOW

MLB_C&MLB_E

R1204

10K

5%
1/32W
MF
01005

MLB_B&MLB_D

1

R1205

10K

5%
1/32W
MF
01005

2

DEV

1

R1206

10K

5%
1/32W
MF
01005

2

IN

USB_BRICKID

01005

NOSTUFF

XW1200

SHORT-01005

NOSTUFF

XW1201

SHORT-01005

NOSTUFF

XW1202

SHORT-01005

12

12

12

AP_TESTMODE

AP_TST_STPCLK

AP_FAST_SCAN_CLK

AP_HOLD_RESET

MAKE_BASE=TRUE

4

OUT

4

OUT

4

OUT

4

OUT

PMU_USB_BRICKID

30 25

OUT

C

B

BOARD REVISION

GPIO_BRD_REV2

5

OUT

GPIO_BRD_REV1

5

OUT

GPIO_BRD_REV0

5

OUT

A

BRD_REV[2-0]

000

PROTO
PROTO 2

001

EVT010

CURRENT SETTING --->

011 DVT

NOSTUFF

1

R1207

10K

5%
1/32W
MF
01005

2

1. SET GPIO AS INPUT

2. ENABLE PU AND DISABLE PD

3. READ

NOSTUFF

1

R1208

10K

5%
1/32W
MF
01005

2

S/W READ FLOW

1

R1209

10K

5%
1/32W
MF
01005

2

6 3

SYNC_MASTER=N/A

PAGE TITLE

AP: MISC & ALIASES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

12 OF 154

SHEET

10 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

12

DDR1_CA<0>

38

8

DDR1_CA<1>

8

38

DDR1_CA<2>

8

38

DDR1_CA<3>

8

38

DDR1_CA<4>

8

38

DDR1_CA<5>

8

=PP1V2_S2R_DDR

D

C

11 12 34

1

R1305

10K

1%
1/32W
MF
01005

2

1

R1306

10K

1%
1/32W
MF
01005

2

=PP1V2_S2R_DDR

11 12 34

1

R1351

10K

1%
1/32W
MF
01005

2

1

R1352

10K

1%
1/32W
MF
01005

2

=PP1V2_VDDQ_DDR

11 12 34

1

R1353

4.7K

1%
1/32W
MF
01005

2

1

R1354

4.7K

1%
1/32W
MF
01005

2

1

C1360

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR0_CA

1

C1350

0.01UF

10%

6.3V

2

X5R
01005

1

C1361

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR1_CA

1

C1352

0.01UF

10%

6.3V

2

X5R
01005

1

C1362

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR0_DQ

1

C1354

0.01UF

10%

6.3V

2

X5R
01005

11 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

11 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

11 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

B

=PP1V2_VDDQ_DDR

11 12 34

1

R1355

4.7K

1%
1/32W
MF
01005

2

1

R1356

4.7K

1%
1/32W
MF
01005

2

1

C1363

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR1_DQ

1

C1356

0.01UF

10%

6.3V

2

X5R
01005

11 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

38

DDR1_CA<6>

8

38

DDR1_CA<7>

8

38

DDR1_CA<8>

38

8

DDR1_CA<9>

8

38

DDR1_CK_P

38

8

DDR1_CK_N

8

38

DDR1_CKE<0>

38

8

DDR1_CSN<0>

8

38

DDR1_DM<1>

38

8

DDR1_DM<0>

8

38

DDR1_DM<3>

38

8

DDR1_DM<2>

8

38

DDR1_DQ<8>

38

8

DDR1_DQ<9>

8

38

DDR1_DQ<10>

8

38

DDR1_DQ<11>

8

38

DDR1_DQ<12>

8

38

DDR1_DQ<13>

38

8

DDR1_DQ<14>

8

38

DDR1_DQ<15>

8

38

DDR1_DQ<0>

8

38

DDR1_DQ<1>

8

38

DDR1_DQ<2>

8

38

DDR1_DQ<3>

8

38

DDR1_DQ<4>

8

38

DDR1_DQ<5>

8

38

DDR1_DQ<6>

8

38

DDR1_DQ<7>

8

38

DDR1_DQ<24>

8

38

DDR1_DQ<25>

38

8

DDR1_DQ<26>

38

8

DDR1_DQ<27>

8

38

DDR1_DQ<28>

8

38

DDR1_DQ<29>

8

38

DDR1_DQ<30>

8

38

DDR1_DQ<31>

8

38

DDR1_DQ<16>

8

38

DDR1_DQ<17>

8

38

DDR1_DQ<18>

8

38

DDR1_DQ<19>

8

38

DDR1_DQ<20>

8

38

DDR1_DQ<21>

8

38

DDR1_DQ<22>

8

38

DDR1_DQ<23>

8

38

8

38

8

38

DDR1_DQS_P<0>

8

38
38

8

DDR1_DQS_P<3>

8

38

DDR1_DQS_N<3>

8

38

DDR1_DQS_P<2>

8

38

DDR1_DQS_N<2>

8

38

PPVREF_DDR1_CA

11 38 39

PPVREF_DDR1_DQ

11 38 39

DDR1_ZQ DDR0_ZQ

38 38

T15 G16

CA0_1

U15 G17

CA1_1

U14 H17

CA2_1

V14 H18

CA3_1

T13 J16

CA4_1

T9 N16

CA5_1

U9 N17

CA6_1

U8 P17

CA7_1

V8 P18

CA8_1

T7 R16

CA9_1

U12 K17

CK_1

U11 L17

CKB_1

V13 J18

CKE_1

U13 J17

CSB_1

C12 K3

DM0_1

B10 M2

DM1_1

B16 G4

DM2_1

D7 T2

DM3_1

C15 G3

DQ0_1

D15 G2

DQ1_1

B14 H5

DQ2_1

C14 H4

DQ3_1

D14 H3

DQ4_1

E14 H2

DQ5_1

B13 J3

DQ6_1

C13 J2

DQ7_1

C9 N4

DQ8_1

D9 N3

DQ9_1

B8 P5

DQ10_1

C8 P4

DQ11_1

D8 P3

DQ12_1

E8 P2

DQ13_1

B7 R4

DQ14_1

C7 R3

DQ15_1

B18 B2

DQ16_1

C18 C2

DQ17_1

D18 D3

DQ18_1

E18 D2

DQ19_1

B17 E4

DQ20_1

D17 E3

DQ21_1

E17 E2

DQ22_1

E16 F2

DQ23_1

B6 T5

DQ24_1

B5 U5

DQ25_1

C5 U4

DQ26_1

D5 U2

DQ27_1

B4 V5

DQ28_1

C4 V4

DQ29_1

B3 V3

DQ30_1

C3 V2

DQ31_1

D13 J4
D12 K4

D10 M4

DQS1_1

C10 M3

C16 F4

DQS2_1

D16 F3

DQSB2_1

D6 T3

DQS3_1

C6 T4

DQSB3_1

U10 M17

VREFCA_1 VREFCA_2

D11 L4

VREFDQ_1 VREFDQ_2

U1300

H4G-DRAM

XXXMB

BGA

SYM 1 OF 2

OMIT_TABLE

DDR_1

U7 R17

DDR_2

DQSB0_2DQSB0_1

DQSB1_2DQSB1_1

DQSB2_2

DQSB3_2

CA0_2
CA1_2
CA2_2
CA3_2
CA4_2
CA5_2
CA6_2
CA7_2
CA8_2
CA9_2

CK_2
CKB_2
CKE_2

CSB_2

DM0_2

DM1_2

DM2_2
DM3_2

DQ0_2
DQ1_2
DQ2_2
DQ3_2
DQ4_2
DQ5_2
DQ6_2
DQ7_2
DQ8_2
DQ9_2

DQ10_2
DQ11_2
DQ12_2
DQ13_2
DQ14_2
DQ15_2
DQ16_2
DQ17_2
DQ18_2
DQ19_2
DQ20_2
DQ21_2
DQ22_2
DQ23_2
DQ24_2
DQ25_2
DQ26_2
DQ27_2
DQ28_2
DQ29_2
DQ30_2
DQ31_2

DQS0_2DQS0_1

DQS1_2

DQS2_2

DQS3_2

2_QZ1_QZ

DDR0_CA<0>
DDR0_CA<1>
DDR0_CA<2>
DDR0_CA<3>
DDR0_CA<4>
DDR0_CA<5>
DDR0_CA<6>
DDR0_CA<7>
DDR0_CA<8>
DDR0_CA<9>

DDR0_CK_P
DDR0_CK_N
DDR0_CKE<0>

DDR0_CSN<0>

DDR0_DM<1>
DDR0_DM<0>
DDR0_DM<3>
DDR0_DM<2>

DDR0_DQ<8>
DDR0_DQ<9>
DDR0_DQ<10>
DDR0_DQ<11>
DDR0_DQ<12>
DDR0_DQ<13>
DDR0_DQ<14>
DDR0_DQ<15>
DDR0_DQ<0>
DDR0_DQ<1>
DDR0_DQ<2>
DDR0_DQ<3>
DDR0_DQ<4>
DDR0_DQ<5>
DDR0_DQ<6>
DDR0_DQ<7>
DDR0_DQ<24>
DDR0_DQ<25>
DDR0_DQ<26>
DDR0_DQ<27>
DDR0_DQ<28>
DDR0_DQ<29>
DDR0_DQ<30>
DDR0_DQ<31>
DDR0_DQ<16>
DDR0_DQ<17>
DDR0_DQ<18>
DDR0_DQ<19>
DDR0_DQ<20>
DDR0_DQ<21>
DDR0_DQ<22>
DDR0_DQ<23>

DDR0_DQS_P<1>DDR1_DQS_P<1>
DDR0_DQS_N<1>DDR1_DQS_N<1>

DDR0_DQS_P<0>
DDR0_DQS_N<0>DDR1_DQS_N<0>

DDR0_DQS_P<3>
DDR0_DQS_N<3>

DDR0_DQS_P<2>
DDR0_DQS_N<2>

PPVREF_DDR0_CA
PPVREF_DDR0_DQ

38

8
8

38

8

38

8

38

8

38

8

38

8

38

8

38
38

8
8

38

38

8
8

38
38

8

8

38

38

8
8

38
38

8
8

38

38

8
8

38

8

38

8

38

8

38
38

8
8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38
38

8

38

8
8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38
38

8

8

38

8

38

8

38

8

38

11 38 39
11 38 39

=PP1V8_S2R_DDR

12 34

=PP1V2_VDDQ_DDR

11 12 34

1

C1323

56PF

5%

6.3V

2

NP0-C0G

01005

=PP1V2_S2R_DDR

11 12 34

C1314

10UF

C1320

10UF

6.3V

6.3V

20%
X5R

603

1

C1301

10UF

20%

6.3V
2

X5R
603

=PP1V2_S2R_DDR

11 12 34

C1315

1

4.3UF

20%

X5R-CERM

2

X5R
603

1

2

1

C1327

10UF

20%

6.3V
2

X5R
603

C1302

C1306

0.22UF

20%

4V

0610

C1321

4.3UF

X5R-CERM

C1328

C1332

0.22UF

1

2

20%

0610

1UF

10%

6.3V
CERM

402

20%

6.3V
X5R

0201

C1310

0.22UF

1

4V

2

1UF

10%

6.3V

CERM

402

20%

6.3V
X5R

0201

1

2

1

2

20%

6.3V
X5R

0201

C1316

1UF

6.3V
CERM

0.22UF

1

2

1

2

C1303

0.22UF

1

2

1

10%

2

402

C1324

6.3V
0201

C1329

0.22UF

1UF

10%

6.3V
CERM

402

C1307

20%

6.3V
X5R

0201

C1311

0.22UF

C1317

1

20%

2

X5R

1UF

10%

6.3V

CERM

402

C1333

20%

6.3V
X5R

0201

1

2

1

2

20%

6.3V
X5R

0201

1UF

10%

6.3V
CERM

402

C1325

0.22UF

1

2

1

2

1

2

1

2

C1304

0.01UF

C1308

0.22UF

0.22UF

0.01UF

20%

6.3V
X5R

0201

C1330

0.01UF

C1334

0.22UF

10%

6.3V
X5R

01005

20%

6.3V
X5R

0201

C1312

6.3V
0201

C1318

X5R-CERM

0201

1

2

10%

6.3V
X5R

01005

20%

6.3V
X5R

0201

1

2

1

2

20%
X5R

10%
10V

C1326

0.22UF

1

2

1

2

1

2

1

2

0.01UF

0.22UF

20%

6.3V
X5R

0201

0.01UF

C1305

6.3V

01005

C1309

56PF

6.3V

NP0-C0G

01005

C1313

6.3V
0201

C1319

56PF

NP0-C0G

01005

1

2

C1331

6.3V

01005

C1335

56PF

6.3V

NP0-C0G

01005

10%
X5R

5%

20%
X5R

5%

6.3V

C1322

0.01UF

10%
X5R

5%

1

2

1

2

1

2

1

2

1

2

1

2

01005

6.3V

D

A2

VDD1_0

B1

VDD1_1

B11

VDD1_2

F17

VDD1_3

L2

VDD1_4

M16

VDD1_5

T10

VDD1_6

U18

VDD1_7

V17

VDD1_8

V6

VDD1_9

W17

VDD1_10

U19

VDD1_11

E11

VDD2_1

E19

VDD2_2

L5

VDD2_3

M18

VDD2_4

U17

VDD2_5

T18

VDD2_6

V10

VDD2_7

V16

VDD2_8

V18

VDD2_9

W5

VDD2_10

W16

VDD2_11

W19

VDD2_12

W18

VDD2_13

V19

VDD2_14

A3

VDD2_15

T19

VDD2_16

H1

VDDQ27

M1

B12

A14
C17

C19
A10
A17

A13
E10
E15

F18
H16
K16
L16
P16
T11
T12
T14

W3
E1
U1

D4
U3

J5
K2
A8
N2
R5

P1

V7
T8

VDDQ32
VDDQ31
VDDQ
VDDQ1
VDDQ3
VDDQ6
VDDQ30
VDDQ23
VDDQ25
VDDQ26
VDDQ22
VDDQ34
VDDQ16
VDDQ17
VDDQ21
VDDQ19
VDDQ20
VDDQ24
VDDQ28
VDDQ29
VDDQ33

VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDDCA9
VDDCA10

1

10%

2

X5R

U1300

H4G-DRAM

XXXMB

BGA

SYM 2 OF 2

OMIT_TABLE

VDD1

VDD2VDDQ

VDDCA

VSS

VSS0

VSS55

VSS2
VSS3
VSS4

VSS49

VSS6
VSS7

VSS9

VSS10

VSS1
VSS12
VSS13
VSS51

VSS52
VSS50
VSS18
VSS48
VSS20
VSS53
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29

VSS47
VSS32
VSS33
VSS34
VSS35
VSS36

VSS54
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46

A16
A19
A4
A6
B15
C1
B9
C11

D1
D19
A1
E12
E13
G5

T16
E7
F16
B19
G18
V1
J1
K18
K5
L18
L3
M5
N18
N5

A18
R18
R2
T1
T17
U16

W2

U6
V11
V12
V15
T6
V9
W1
W4

C

B

1

R1320

240

1%
1/20W
MF
201

2

A

6 3

1

R1321

240

1%
1/20W
MF
201

2

SYNC_MASTER=N/A

PAGE TITLE

DDR 0 AND 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

13 OF 154

SHEET

11 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

DDR3_CA<0>

8

38

DDR3_CA<1>

8

38

DDR3_CA<2>

38

=PP1V2_S2R_DDR

11 12 34

1

R1405

10K

1%
1/32W
MF
01005

D

C

B

2

1

R1406

10K

1%
1/32W
MF
01005

2

=PP1V2_S2R_DDR

11 12 34

1

R1451

10K

1%
1/32W
MF
01005

2

1

R1452

10K

1%
1/32W
MF
01005

2

=PP1V2_VDDQ_DDR

11 12 34

1

R1453

4.7K

1%
1/32W
MF
01005

2

1

R1454

4.7K

1%
1/32W
MF
01005

2

=PP1V2_VDDQ_DDR

11 12 34

1

R1455

4.7K

1%
1/32W
MF
01005

2

1

R1456

4.7K

1%
1/32W
MF
01005

2

1

C1460

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR2_CA

1

C1450

0.01UF

10%

6.3V

2

X5R
01005

1

C1461

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR3_CA

1

C1452

0.01UF

10%

6.3V

2

X5R
01005

1

C1462

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR2_DQ

1

C1454

0.01UF

10%

6.3V

2

X5R
01005

1

C1463

0.01UF

10%

6.3V

2

X5R
01005

PPVREF_DDR3_DQ

1

C1456

0.01UF

10%

6.3V

2

X5R
01005

12 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

12 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

12 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

12 38 39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

8

DDR3_CA<3>

8

38

DDR3_CA<4>

8

38

DDR3_CA<5>

8

38

DDR3_CA<6>

8

38

DDR3_CA<7>

8

38

DDR3_CA<8>

8

38

DDR3_CA<9>

38

8

DDR3_CK_P

38

8

DDR3_CK_N

8

38

DDR3_CKE<0>

8

38

DDR3_CSN<0>

38

8

DDR3_DM<1>

38

8

DDR3_DM<0>

38

8

DDR3_DM<3>

8

38

DDR3_DM<2>

8

38

DDR3_DQ<8>

8

38

DDR3_DQ<9>

8

38

DDR3_DQ<10>

8

38

DDR3_DQ<11>

8

38

DDR3_DQ<12>

8

38

DDR3_DQ<13>

8

38

DDR3_DQ<14>

8

38

DDR3_DQ<15>

8

38

DDR3_DQ<0>

38

8

DDR3_DQ<1>

38

8

DDR3_DQ<2>

8

38

DDR3_DQ<3>

8

38

DDR3_DQ<4>

8

38

DDR3_DQ<5>

38

8

DDR3_DQ<6>

38

8

DDR3_DQ<7>

38

8

DDR3_DQ<24>

38

8

DDR3_DQ<25>

8

38

DDR3_DQ<26>

38

8

DDR3_DQ<27>

8

38

DDR3_DQ<28>

8

38

DDR3_DQ<29>

8

38

DDR3_DQ<30>

38

8

DDR3_DQ<31>

8

38

DDR3_DQ<16>

8

38

DDR3_DQ<17>

8

38

DDR3_DQ<18>

38

8

DDR3_DQ<19>

8

38

DDR3_DQ<20>

8

38

DDR3_DQ<21>

38

8

DDR3_DQ<22>

8

38

DDR3_DQ<23>

38

8

DDR3_DQS_P<1> DDR2_DQS_P<1>

8

38

DDR3_DQS_N<1> DDR2_DQS_N<1>

8

38

DDR3_DQS_P<0>

8

38

DDR3_DQS_N<0> DDR2_DQS_N<0>

8

38

DDR3_DQS_P<3>

8

38

DDR3_DQS_N<3>

8

38

DDR3_DQS_P<2>

8

38

DDR3_DQS_N<2>

8

38

DDR3_ZQ DDR2_ZQ

38 38

1

R1420

240

1%
1/20W
MF
201

2

T15 G16

CA0_1

U15 G17

CA1_1

U14 H17

CA2_1

V14 H18

CA3_1

T13 J16

CA4_1

T9 N16

CA5_1

U9 N17

CA6_1

U8 P17

CA7_1

V8 P18

CA8_1

T7 R16

CA9_1

U12 K17

CK_1

U11 L17

CKB_1

V13 J18

CKE_1

U13 J17

CSB_1

C12 K3

DM0_1

B10 M2

DM1_1

B16 G4

DM2_1

D7 T2

DM3_1

C15 G3

DQ0_1

D15 G2

DQ1_1

B14 H5

DQ2_1

C14 H4

DQ3_1

D14 H3

DQ4_1

E14 H2

DQ5_1

B13 J3

DQ6_1

C13 J2

DQ7_1

C9 N4

DQ8_1

D9 N3

DQ9_1

B8 P5

DQ10_1

C8 P4

DQ11_1

D8 P3

DQ12_1

E8 P2

DQ13_1

B7 R4

DQ14_1

C7 R3

DQ15_1

B18 B2

DQ16_1

C18 C2

DQ17_1

D18 D3

DQ18_1

E18 D2

DQ19_1

B17 E4

DQ20_1

D17 E3

DQ21_1

E17 E2

DQ22_1

E16 F2

DQ23_1

B6 T5

DQ24_1

B5 U5

DQ25_1

C5 U4

DQ26_1

D5 U2

DQ27_1

B4 V5

DQ28_1

C4 V4

DQ29_1

B3 V3

DQ30_1

C3 V2

DQ31_1

D13 J4
D12 K4

D10 M4

DQS1_1

C10 M3

C16 F4

DQS2_1

D16 F3

DQSB2_1

D6 T3

DQS3_1

C6 T4

DQSB3_1

U10 M17

VREFCA_1 VREFCA_2

D11 L4

VREFDQ_1 VREFDQ_2

U1400

H4G-DRAM

XXXMB

BGA

SYM 1 OF 2

OMIT_TABLE

DDR_1

U7 R17

DDR_2

DQ10_2
DQ11_2
DQ12_2
DQ13_2
DQ14_2
DQ15_2
DQ16_2
DQ17_2
DQ18_2
DQ19_2
DQ20_2
DQ21_2
DQ22_2
DQ23_2
DQ24_2
DQ25_2
DQ26_2
DQ27_2
DQ28_2
DQ29_2
DQ30_2
DQ31_2

DQS0_2DQS0_1

DQSB0_2DQSB0_1

DQS1_2

DQSB1_2DQSB1_1

DQS2_2

DQSB2_2

DQS3_2

DQSB3_2

CA0_2
CA1_2
CA2_2
CA3_2
CA4_2
CA5_2
CA6_2
CA7_2
CA8_2
CA9_2

CK_2
CKB_2
CKE_2

CSB_2

DM0_2
DM1_2
DM2_2
DM3_2

DQ0_2
DQ1_2
DQ2_2
DQ3_2
DQ4_2
DQ5_2
DQ6_2
DQ7_2
DQ8_2
DQ9_2

2_QZ1_QZ

DDR2_CA<0>
DDR2_CA<1>
DDR2_CA<2>
DDR2_CA<3>
DDR2_CA<4>
DDR2_CA<5>
DDR2_CA<6>
DDR2_CA<7>
DDR2_CA<8>
DDR2_CA<9>

DDR2_CK_P
DDR2_CK_N
DDR2_CKE<0>

DDR2_CSN<0>

DDR2_DM<1>
DDR2_DM<0>
DDR2_DM<3>
DDR2_DM<2>

DDR2_DQ<8>
DDR2_DQ<9>
DDR2_DQ<10>
DDR2_DQ<11>
DDR2_DQ<12>
DDR2_DQ<13>
DDR2_DQ<14>
DDR2_DQ<15>
DDR2_DQ<0>
DDR2_DQ<1>
DDR2_DQ<2>
DDR2_DQ<3>
DDR2_DQ<4>
DDR2_DQ<5>
DDR2_DQ<6>
DDR2_DQ<7>
DDR2_DQ<24>
DDR2_DQ<25>
DDR2_DQ<26>
DDR2_DQ<27>
DDR2_DQ<28>
DDR2_DQ<29>
DDR2_DQ<30>
DDR2_DQ<31>
DDR2_DQ<16>
DDR2_DQ<17>
DDR2_DQ<18>
DDR2_DQ<19>
DDR2_DQ<20>
DDR2_DQ<21>
DDR2_DQ<22>
DDR2_DQ<23>

DDR2_DQS_P<0>

DDR2_DQS_P<3>
DDR2_DQS_N<3>

DDR2_DQS_P<2>
DDR2_DQS_N<2>

PPVREF_DDR2_CAPPVREF_DDR3_CA
PPVREF_DDR2_DQPPVREF_DDR3_DQ

8

38

8

38
38

8
8

38

8

38

8

38

8

38

8

38

8

38
38

8

38

8
8

38

8

38

38

8

38

8

38

8
8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38
38

8

38

8
8

38

8

38

8

38
38

8

38

8

38

8

38

8
8

38
38

8
8

38

8

38

8

38
38

8
8

38

8

38

8

38
38

8
8

38

8

38
38

8
8

38
38

8

8

38

8

38

8

38

8

38

8

38

8

38

8

38

8

38

12 38 39 12 38 39
12 38 39 12 38 39

1

R1421

240

1%
1/20W
MF
201

2

=PP1V8_S2R_DDR

11 34

=PP1V2_VDDQ_DDR

11 12 34

1

C1423

56PF

5%

6.3V
2

NP0-C0G

01005

=PP1V2_S2R_DDR

11 12 34

C1401

10UF

6.3V

=PP1V2_S2R_DDR

11 12 34

1

C1414

10UF

20%

6.3V
2

X5R
603

1

C1420

10UF

20%

6.3V
2

X5R
603

C1427

10UF

20%
X5R

603

C1415

X5R-CERM

20%

6.3V
X5R
603

1

2

4.3UF

0610

1

2

C1402

C1406

0.22UF

1

20%

4V

2

C1421

4.3UF

X5R-CERM

0610

0.22UF

1UF

10%

6.3V
CERM

402

20%

6.3V
X5R

0201

C1410

0.22UF

1

20%

4V

2

C1428

1UF

6.3V
CERM

C1432

6.3V
0201

1

2

1

2

20%

6.3V
X5R

0201

C1416

1UF

6.3V
CERM

1

10%

2

402

1

20%

2

X5R

0.22UF

1

2

1

10%

2

402

C1424

0.22UF

C1403

1UF

6.3V
CERM

C1407

6.3V
0201

C1411

0.22UF

C1417

20%

6.3V
X5R

0201

C1429

C1433

0.22UF

10%

402

20%
X5R

1UF

1

2

1UF

6.3V
CERM

6.3V
0201

6.3V
0201

6.3V
CERM

10%

402

20%
X5R

1

2

1

2

20%
X5R

10%

402

1

2

1

2

C1425

0.22UF

6.3V
0201

1

2

1

2

C1404

0.01UF

6.3V

01005

C1408

0.22UF

6.3V
0201

C1412

0.22UF

C1418

0.01UF

X5R-CERM

1

20%

2

X5R

C1430

0.01UF

C1434

0.22UF

10%
X5R

20%
X5R

6.3V
0201

0201

01005

20%
X5R

10%
10V

0.22UF

10%

6.3V
X5R

20%

6.3V
X5R

0201

1

2

1

2

1

2

1

2

C1426

1

2

1

2

C1405

0.01UF

C1409

56PF

NP0-C0G

C1413

0.22UF

C1419

56PF

NP0-C0G

20%

6.3V
X5R

0201

0.01UF

10%

6.3V
X5R

01005

5%

6.3V

01005

20%

6.3V
X5R

0201

5%

6.3V

01005

1

2

C1431

6.3V

01005

C1435

56PF

6.3V

NP0-C0G

01005

1

2

1

2

1

2

1

2

C1422

0.01UF

10%
X5R

5%

1

2

1

2

6.3V

01005

A2

VDD1_0

B1

VDD1_1

B11

VDD1_2

F17

VDD1_3

L2

VDD1_4

M16

VDD1_5

T10

VDD1_6

U18

VDD1_7

V17

VDD1_8

V6

VDD1_9

W17

VDD1_10

U19

VDD1_11

E11

VDD2_1

E19

VDD2_2

L5

VDD2_3

M18

VDD2_4

U17

VDD2_5

T18

VDD2_6

V10

VDD2_7

V16

VDD2_8

V18

VDD2_9

W5

VDD2_10

W16

VDD2_11

W19

VDD2_12

W18

VDD2_13

V19

VDD2_14

A3

VDD2_15

T19

VDD2_16

H1

VDDQ27

M1

VDDQ32

W3

VDDQ31

E1

B12

A14
C17

C19
A10
A17

A13
E10
E15

F18
H16
K16
L16
P16
T11
T12
T14

U1

D4
U3

J5
K2
A8
N2
R5

P1

V7
T8

VDDQ
VDDQ1
VDDQ3
VDDQ6
VDDQ30
VDDQ23
VDDQ25
VDDQ26
VDDQ22
VDDQ34
VDDQ16
VDDQ17
VDDQ21
VDDQ19
VDDQ20
VDDQ24
VDDQ28
VDDQ29
VDDQ33

VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDDCA9
VDDCA10

1

10%

2

X5R

U1400

H4G-DRAM

XXXMB

BGA

SYM 2 OF 2

OMIT_TABLE

VDD1

VDD2VDDQ

VDDCA

VSS

VSS0

VSS55

VSS2
VSS3
VSS4

VSS49

VSS6
VSS7

VSS9

VSS10

VSS1
VSS12
VSS13
VSS51

VSS52
VSS50
VSS18
VSS48
VSS20
VSS53
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29

VSS47
VSS32
VSS33
VSS34
VSS35
VSS36

VSS54
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46

A16
A19
A4
A6
B15
C1
B9
C11

D1
D19
A1
E12
E13
G5

T16
E7
F16
B19
G18
V1
J1
K18
K5
L18
L3
M5
N18
N5

A18
R18
R2
T1
T17
U16

W2

U6
V11
V12
V15
T6
V9
W1
W4

D

C

B

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

DDR 2 AND 3

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

14 OF 154

SHEET

12 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

12

=PP3V3_NAND

34

1

C1600

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1601

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1602

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1610

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1611

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1612

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1613

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1614

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1615

10UF

20%

6.3V

2

CERM-X5R
0402-1

=PP1V8_NAND

D

1

C1604

0.22UF

20%

6.3V

2

X5R
0201

1

C1607

27PF

5%
25V

2

NP0-C0G
0201

1

C

C1652

27PF

5%
25V

2

NP0-C0G
0201

1

C1605

0.22UF

20%

6.3V

2

X5R
0201

1

C1608

27PF

5%
25V

2

NP0-C0G
0201

1

C1651

1UF

20%

6.3V

2

X5R
0201

13 38
38
38
38
38
38
38
38

13 38
38
38
38
38
38
38
38

B

1

C1606

0.22UF

20%

6.3V

2

X5R
0201

1

C1609

27PF

5%
25V

2

NP0-C0G
0201

PPVDDI_NAND_U1600

VOLTAGE=1.2V

1

2

FMI0_AD<0>

6

BI

FMI0_AD<1>

6

BI

FMI0_AD<2>

6

BI

FMI0_AD<3>

6

BI

FMI0_AD<4>

6

BI

FMI0_AD<5>

6

BI

FMI0_AD<6>

6

BI

FMI0_AD<7>

6

BI

FMI1_AD<0>

6

BI

FMI1_AD<1>

6

BI

FMI1_AD<2>

6

BI

FMI1_AD<3>

6

BI

FMI1_AD<4>

6

BI

FMI1_AD<5>

6

BI

FMI1_AD<6>

6

BI

FMI1_AD<7>

6

BI

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

C1650

NET_SPACING_TYPE=PWR

1UF

MAX_NECK_LENGTH=3MM

20%

6.3V
X5R
0201

TP_FMI_TCKC_U1600
TP_FMI_TMSC_U1600

OA0
OB0

G3
H2
J3
K2
L5
K6
J5
H6

G1
J1
L1
N3
N5
L7
J7
G7

IO0-0
IO1-0
IO2-0
IO3-0
IO4-0
IO5-0
IO6-0
IO7-0

IO0-1
IO1-1
IO2-1
IO3-1
IO4-1
IO5-1
IO6-1
IO7-1

TCKC
TMSC

VDDI

OB8

B6F2M6N1N7

VCC

OMIT_TABLE

U1600

LGA-12X17

VSS

B2F6L3A7M2

OC8

OD8

OE0

OF8G0OA8

VCCQ

CE0*
CLE0
ALE0
WE0*

RE0

RE0*

DQS0

DQS0*

R/B0*

CE1*
CLE1
ALE1
WE1*

XXNM-XGBX8-MLC-PPN1.5-ODP

VSSQ

OC0

OD0

OE8

OF0

G8

RE1*

DQS1

DQS1*
R/B1*

VREF

RE1

ZQ

1

2

1

2

A5
A3
C1
E3

B4

NC

C7

H4
F4

NC

E5

NAND_SLOT0_RDYBSY_L

C5
C3
D2
E1

D4

NC

D6

M4
K4

NC

E7

G5
A1

C1620

20%

6.3V
X5R
0201

C1630

27PF

5%
25V
NP0-C0G
0201

FMI0_CE0_L
FMI0_CLE
FMI0_ALE
FMI0_WE_L

FMI0_RE_L

FMI0_DQS

FMI1_CE0_L
FMI1_CLE
FMI1_ALE
FMI1_WE_L

FMI1_RE_L

FMI1_DQS

FMI_DQVREF_NAND

FMI_ZQ_U1600

1

C1621

0.22UF0.22UF

20%

6.3V

2

X5R
0201

1

C1631

27PF

5%
25V

2

NP0-C0G
0201

1

2

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

R1654

243

1%
1/20W
MF
201

38
13 38
13 38
13 38

13 38

13 38

38
13 38
13 38
13 38

13 38

13 38

1

C1622

2

1

C1632

27PF

5%
25V

2

NP0-C0G
0201

0.22UF

20%

6.3V
X5R
0201

1

C1623

0.22UF

20%

6.3V

2

X5R
0201

1

C1633

27PF

5%
25V

2

NP0-C0G
0201

1

C1624

0.22UF

20%

6.3V

2

X5R
0201

1

C1634

27PF

5%
25V

2

NP0-C0G
0201

=PP1V8_NAND

R1655

1

100K

5%
1/32W
MF
01005

2

1

2

1

C1635

27PF

5%
25V

2

NP0-C0G
0201

C1625

0.22UF

20%

6.3V
X5R
0201

13 34

1

R1691

51.1K

1%
1/32W
MF
01005

2

1

R1690

51.1K

1%
1/32W
MF
01005

2

=PP1V8_NAND

1

C1690

0.1UF

20%
4V

2

X5R
01005

1

C1691

0.1UF

20%
4V

2

X5R
01005

13 34

13 34

TEST POINTS

DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA

13 38
13 38
13 38
13 38

13 38

13 38

13 38
13 38
13 38
13 38

13 38

13 38

6
6
6
6

6

6

6
6
6
6

6

6

FMI0_AD<0>
FMI0_ALE
FMI0_CLE
FMI0_RE_L

FMI0_WE_L

FMI0_DQS

FMI1_AD<0>
FMI1_ALE
FMI1_CLE
FMI1_RE_L

FMI1_WE_L

FMI1_DQS

1
1
1
1

1

1

1
1
1
1

1

1

TP1600

TP

TP1601

TP

TP1602

TP

TP1603

TP

TP1605

TP

TP1613

TP

TP1606

TP

TP1607

TP

TP1608

TP

TP1609

TP

TP1611

TP

TP1615

TP

D

C

B

A

SYNC_MASTER=N/A

PAGE TITLE

NAND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

16 OF 154

SHEET

13 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

D

D

WIFI ALIASES

HSIC1_WLAN_DATA

4

36

HSIC1_WLAN_STB

4

36

GPIO_WLAN_HSIC_HOST_RDY

5

36

GPIO_WLAN_HSIC_DEV_RDY

5

36

PMU_GPIO_WLAN_REG_ON

30

PMU_GPIO_WLAN_HOST_WAKE

30

PMU_GPIO_BT_REG_ON

30

PMU_GPIO_BT_HOST_WAKE

30

GPIO_BT_WAKE

5

UART3_BT_RXD

36

5

UART3_BT_TXD

36

5

UART3_BT_CTS_L

5

36

UART3_BT_RTS_L

5

36

PMU_GPIO_CLK_32K_WLAN

30 36

I2S2_BT_BCLK

36

5

I2S2_BT_DOUT

5

36

C

I2S2_BT_DIN

36

5

I2S2_BT_LRCK

36

5

UART4_WLAN_RXD

5

36

UART4_WLAN_TXD

5

36 27

GPIO_WL_HSIC_RESUME

5

VDDIO_WLAN_BT_1V8

34

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

50_HSIC_WLAN_DATA
50_HSIC_WLAN_STROBE
AP_HSIC3_RDY
DEV_HSIC3_RDY
WLAN_REG_ON
HOST_WAKE_WLAN
BT_REG_ON
HOST_WAKE_BT
BT_WAKE
BT_UART_TXD
BT_UART_RXD
BT_UART_RTS_L
BT_UART_CTS_L
CLK32K_AP
BT_PCM_CLK
BT_PCM_IN
BT_PCM_OUT
BT_PCM_SYNC
WLAN_UART_TXD
WLAN_UART_RXD
WLAN_HSIC3_RESUME

PP_WL_BT_VDDIO_AP

27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27

27

27

C

B

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

ALIASES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

21 OF 154

SHEET

14 OF 39

124578

SIZE

B

A

D

8 7 6 5 4 3

=PP3V3_LCD

34

PPVCC_MAIN

25 29 30 34 39

D

PM_LCDVDD_PWREN

5

IN

1

R2205

100K

5%
1/20W
MF
201

2

1

2

LCD_RAMP

1

C2241

3900PF

10%
50V

2

X7R
0402

C2240

0.1UF

10%

6.3V
X5R
201

CAP
ON S

1
VDD

U2200

SLG5AP302

TDFN

CRITICAL

GND

8

1

C2239

0.1UF

10%

6.3V

2

X5R
201

37

D

52

LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION

EDP CONNECTOR

CRITICAL

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

15 39

PP3V3_S0_LCD_FERR

1

C2203

0.1UF

10%

6.3V

2

X5R
201

1

C2202

1UF

2

10%

6.3V
CERM
402

NOSTUFF

1

R2290

47K

5%
1/20W
MF
201

2

L2201

FERR-120-OHM-1.5A

1 2

0402A

1

C2230

82PF

5%
25V

2

NP0-C0G-CERM
0201

1

C2232

8.2PF

+/-0.1PF%
25V

2

CER
0201

1

2

C2206

1000PF

10%
16V
X7R-CERM
0201

PART NUMBER

ALTERNATE FOR
PART NUMBER

155S0583155S0667
155S0559155S0625

BOM OPTION

REF DES

L2242,L5500,L5510,L5520,L5530,L5540,L5930,L5931

L2202,L2212,L2222,L2232

COMMENTS:

RDAR://PROBLEM/8616060, RADAR://PROBLEM/9015335

RDAR://PROBLEM/9017591

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

12

D

R2280

1.00M

12

C2280

+/-0.1PF

12

C

C2281

+/-0.1PF

R2282

1.00M

12

C2282

+/-0.1PF

R2283

12

C2283

+/-0.1PF

R2284

B

12

C2284

+/-0.1PF

R2285

12

C2285

+/-0.1PF

R2286

12

C2286

A

+/-0.1PF

12

C2287

+/-0.1PF

CONN_EDP_DATA_EMI_N<0>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

R2281

1.00M

CONN_EDP_DATA_EMI_P<0>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

CONN_EDP_DATA_EMI_N<1>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

1.00M

CONN_EDP_DATA_EMI_P<1>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

1.00M

CONN_EDP_DATA_EMI_N<2>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

1.00M

CONN_EDP_DATA_EMI_P<2>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

1.00M

CONN_EDP_DATA_EMI_N<3>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

R2287

1.00M

CONN_EDP_DATA_EMI_P<3>

01005

1.2PF

12

NOSTUFF

16V

NP0-C0G

01005

15 37

15 37

15 37

15 37

15 37

15 37

15 37

15 37

7

37

37

7

7

37

37

7

7

37

7

37

7

37

7

37

7

37

7

37

EDP_AUX_N

IN

EDP_AUX_P

IN

EDP_DATA_N<0>

IN

EDP_DATA_P<0>

IN

EDP_DATA_N<1>

IN

EDP_DATA_P<1>

IN

EDP_DATA_N<2>

IN

EDP_DATA_P<2>

IN

EDP_DATA_N<3>

IN

EDP_DATA_P<3>

IN

C2250

C2251

C2242

201

C2243

201

C2244

C2245

C2246

201 X5R

C2247

C2248
C2249

12

6.3V
12

6.3V

12

6.3V
12

6.3V

12

6.3V
12

6.3V

12

6.3V
12

6.3V

12

6.3V
12

6.3V

R2295

12

R2296

12

R2297

12

10%201 X5R

0.1UF

10%201 X5R

10% X5R

0.1UF

10%X5R

10%201 X5R

0.1UF

10%201 X5R

10%

0.1UF

10%201 X5R

10%

0.1UF

1/20W

201

1/20W

201

1/20W

201

PP3V3_S0_LCD_FERR

15 39

0.1UF

EDP_AUX_EMI_N

37

37

EDP_AUX_EMI_P

0.1UF

0.1UF

0.1UF

0.1UF

0

5%
MF

0

5%
MF

0

5%
MF

X5R201

X5R201 10%

37

EDP_DATA_EMI_N<0>

37

EDP_DATA_EMI_P<0>

EDP_DATA_EMI_N<1>

37

EDP_DATA_EMI_P<1>

37

37

EDP_DATA_EMI_N<2>

37

EDP_DATA_EMI_P<2>

37

EDP_DATA_EMI_N<3>

37

EDP_DATA_EMI_P<3>

J2200_29_GND

J2200_36_GND

J2200_43_GND

1

R2240

100K

1%
1/32W
MF
01005

2

1

R2241

100K

1%
1/32W
MF
01005

2

90-OHM-50MA

2 3

1 4

2 3

1

12-OHM-100MA-8.5GHZ

2 3

1

12-OHM-100MA-8.5GHZ

2 3

1

12-OHM-100MA-8.5GHZ

12-OHM-100MA-8.5GHZ

15 39

15 39

15 39

CRITICAL

L2242

TCM0605-1

SYM_VER-2

CRITICAL

SYM_VER-2

TCM0806-4SM

L2212

CRITICAL

SYM_VER-2

TCM0806-4SM

L2222

CRITICAL

SYM_VER-2

TCM0806-4SM

L2232

CRITICAL

2 3

1

SYM_VER-2

TCM0806-4SM

L2202

4

4

4

4

=PPLED_REG_B

34

=PPLED_REG_A

34

CONN_EDP_AUX_EMI_N

CONN_EDP_AUX_EMI_P

CONN_EDP_DATA_EMI_N<0>

CONN_EDP_DATA_EMI_P<0>

CONN_EDP_DATA_EMI_N<1>

CONN_EDP_DATA_EMI_P<1>

CONN_EDP_DATA_EMI_N<2>

CONN_EDP_DATA_EMI_P<2>

CONN_EDP_DATA_EMI_N<3>

CONN_EDP_DATA_EMI_P<3>

FERR-240-OHM-25%-300MA

VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

1 2

FERR-240-OHM-25%-300MA

1 2

CRITICAL

L2210

0402

CRITICAL

L2200

0402

15 37

15 37

15 37

15 37

15 37

15 37

15 37

15 37

15 37

15 37

39

1

2

39

1

2

PPLED_BACK_REG_B

1

C2253

100PF

5%
50V
CERM
0402

C2270

820PF

10%
50V

2

CERM
0402

PPLED_BACK_REG_A

1

C2233

100PF

5%
50V
CERM
0402

C2220

820PF

10%
50V

2

CERM
0402

6 3

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

CONN_EDP_AUX_EMI_P

15 37

LED_IO_5_B

30 37

IN

LED_IO_3_B

30 37

IN

LED_IO_1_B

30 37

IN

LED_IO_6_A

30 37

IN

LED_IO_4_A

30 37

IN

LED_IO_2_A

30 37

IN

1

C2271

8.2PF

+/-0.25PF
50V

2

CERM
402-1

1

C2221

8.2PF

+/-0.25PF
50V

2

CERM
402-1

15 39

J2200_43_GND

15 39

J2200_29_GND

39

PP3V3_LCDVDD_SW_F

518S0827

CRITICAL

J2200

502250-8051-B

F-RT-SM

54
52

1

2

3

NC

11
13

NC

15
17

NC

19
21

NC

23
25

NC

27
29
31
33
35
37
39
41
43
45
47

NC

49
51

53
55

SYNC_MASTER=N/A

PAGE TITLE

4

5

6

7

8

9

NC

10

CONN_EDP_AUX_EMI_N

12

CONN_EDP_DATA_EMI_N<0>

14

CONN_EDP_DATA_EMI_P<0>

16

CONN_EDP_DATA_EMI_N<1>

18

CONN_EDP_DATA_EMI_P<1>

20

CONN_EDP_DATA_EMI_N<2>

22

CONN_EDP_DATA_EMI_P<2>

24

CONN_EDP_DATA_EMI_N<3>

26

CONN_EDP_DATA_EMI_P<3>

28
30

LED_IO_6_B

32

LED_IO_4_B

34

LED_IO_2_B

36

J2200_36_GND

38

LED_IO_5_A

40

LED_IO_3_A

42

LED_IO_1_A

44

NC

46
48
50

NC

VIDEO: EDP CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

15 39

IN
IN
IN

IN
IN
IN

EDP_HPD

1

2

30 37
30 37
30 37

30 37
30 37
30 37

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

SHEET

124578

7

OUT

R2242

100K

1%
1/32W
MF
01005

15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37

SYNC_DATE=N/A

A.0.0

22 OF 154

15 OF 39

37

C

B

A

SIZE

D

8 7 6 5 4 3

WWW.AliSaler.Com

PART#

343S0525

CONNECTORS TO GRAPE FLEX

D

C

16

16
16

17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16

DESCRIPTION

QTY

1

IC,ASIC,GROUNDHOG B0,120B BGA

AG_SHLD_TST_FLEX

R3070

12

NOSTUFF

1

R3071

0

5%
1/20W
MF
201

2

5%

1/20W

MF

201

0

REFERENCE DESIGNATOR(S)

AG_SHLD_TST

1

C3070

0.1UF

10%
25V

2

X5R
402

P/N 518S0828

MATES WITH LEFTMOST GRAPE FLEX TAIL

CRITICAL

J3010

502250-8037-B

F-RT-SM

41
39

MT_PANEL_OUT<36>
MT_PANEL_OUT<38>

MT_PANEL_IN<29>
MT_PANEL_IN<27>
MT_PANEL_IN<25>
MT_PANEL_IN<23>
MT_PANEL_IN<21>
MT_PANEL_IN<19>
MT_PANEL_IN<17>
MT_PANEL_IN<15>
MT_PANEL_IN<13>
MT_PANEL_IN<11>
MT_PANEL_IN<9>
MT_PANEL_IN<7>
MT_PANEL_IN<5>
MT_PANEL_IN<3>
MT_PANEL_IN<1>
AG_SHLD_TST_FLEX

37
35
33
31
29
27
25
23
21
19
17
15
13
11

9
7
5
3
1

38
40

MT_PANEL_OUT<37>

36

MT_PANEL_OUT<39>

34
32

MT_PANEL_IN<28>

30

MT_PANEL_IN<26>

28

MT_PANEL_IN<24>

26

MT_PANEL_IN<22>

24

MT_PANEL_IN<20>

22

MT_PANEL_IN<18>

20

MT_PANEL_IN<16>

18

MT_PANEL_IN<14>

16

MT_PANEL_IN<12>

14

MT_PANEL_IN<10>

12

MT_PANEL_IN<8>

10

MT_PANEL_IN<6>

8

MT_PANEL_IN<4>

6

MT_PANEL_IN<2>

4

MT_PANEL_IN<0>

2

U3003

B

MATES WITH RIGHTMOST GRAPE FLEX TAIL

MT_PANEL_OUT<1>

16

MT_PANEL_OUT<3>

16

MT_PANEL_OUT<5>

16

MT_PANEL_OUT<7>

16

MT_PANEL_OUT<9>

16

MT_PANEL_OUT<11>

16

MT_PANEL_OUT<13>

16

MT_PANEL_OUT<15>

16

MT_PANEL_OUT<17>

16

MT_PANEL_OUT<19>

16

MT_PANEL_OUT<21>

16

MT_PANEL_OUT<23>

16

MT_PANEL_OUT<25>

16

MT_PANEL_OUT<27>

16

MT_PANEL_OUT<29>

A

16

MT_PANEL_OUT<31>

16

MT_PANEL_OUT<33>

16

MT_PANEL_OUT<35>

16

CRITICAL

J3011

502250-8037-B

F-RT-SM

41
39

37
35
33
31
29
27
25
23
21
19
17
15
13
11

38
40

36
34
32
30
28
26
24
22
20
18
16
14
12
10

9

8

7

6

5

4

3

2

1

MT_PANEL_OUT<0>
MT_PANEL_OUT<2>
MT_PANEL_OUT<4>
MT_PANEL_OUT<6>
MT_PANEL_OUT<8>
MT_PANEL_OUT<10>
MT_PANEL_OUT<12>
MT_PANEL_OUT<14>
MT_PANEL_OUT<16>
MT_PANEL_OUT<18>
MT_PANEL_OUT<20>
MT_PANEL_OUT<22>
MT_PANEL_OUT<24>
MT_PANEL_OUT<26>
MT_PANEL_OUT<28>
MT_PANEL_OUT<30>
MT_PANEL_OUT<32>
MT_PANEL_OUT<34>

CRITICAL BOM OPTION

CRITICAL

17

16
16

17
17
17
17
17
17
17
17
17
17
17
17
17
17
17

BOOST CONVERTOR

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

PP18V_GRAPE

16

C3005

0.1UF

TABLE_5_HEAD

TABLE_5_ITEM

17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17

17
17
17
17
17
17

CRITICAL

L3000

4.7UH-700MA-280MOHM

NC

C3001

2.2UF

10%

6.3V
X5R
603

1 2

=PP3V0_GRAPE

16 17 34

CRITICAL

1

U3000

L

TPS61045

QFN-1

DO

THRML

PAD

9

VR_BOOST_L

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM

1

2

10%
25V
X5R
402

MUX_IN<0>
MUX_IN<1>
MUX_IN<2>
MUX_IN<3>
MUX_IN<4>
MUX_IN<5>
MUX_IN<6>
MUX_IN<7>
MUX_IN<8>
MUX_IN<9>
MUX_IN<10>
MUX_IN<11>
MUX_IN<12>
MUX_IN<13>
MUX_IN<14>
MUX_IN<15>
MUX_IN<16>
MUX_IN<17>
MUX_IN<18>
MUX_IN<19>

Z1_BON_L<0>
Z1_BON_L<1>
Z1_BON_L<2>
Z1_BON_L<3>
Z1_BON_L<4>
Z1_BON_L<5>

VLF

2

VIN

FB

CTRL

SW

PGND

GND

6

7

39

AGND_U3000

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM

2

XW3000

SM

1

1

C3007

2

0.1UF

1

C3053

10%
25V

2

X5R
402

B1

MUX0

C1

MUX1

E1

MUX2

F2

MUX3

H1

MUX4

J1

MUX5

J2

MUX6

J3

MUX7

K4

MUX8

H5

MUX9

I5

MUX10

J8

MUX11

J9

MUX12

K8

MUX13

J10

MUX14

I10

MUX15

H10

MUX16

F11

MUX17

C11

MUX18

E10

MUX19

A11

MUX20

NC

B4

MUX21

NC

A5

MUX22

NC

A2

MUX23

NC

C7

BON_L0

A7

BON_L1

B7

BON_L2

B8

BON_L3

A8

BON_L4

C8

BON_L5

C6

NC

D3

NC

D4

NC

D5

NC

D6

NC

D8

NC

D9

NC

E4

NC

E8

NC

F4

NC

F5

NC

NC

F8

NC

F9

NC

G3

NC

G4

NC

G9

NC

H3

NC

H4

NC

H7

NC

H8

NC

H9

NC

J6

NC

K7

NC

0.1UF

10%
25V
X5R
402

G8

1

2

VDDH

U3003

GROUNDHOG

BGA

CRITICAL

OMIT

GND

G7

B6E9F3

A6

VCC_DIG

E3

E5E6E7F6F7G5G6

=PP3V0_GRAPE_MARIO1

A1

VSTM0

B2

VSTM1

C2

VSTM2

D1

VSTM3

D2

VSTM4

E2

VSTM5

F1

VSTM6

G1

VSTM7

G2

VSTM8

I1

VSTM9

H2

VSTM10

I2

VSTM11

K1

VSTM12

K2

VSTM13

I3

VSTM14

K3

VSTM15

J4

VSTM16

I4

VSTM17

K6

VSTM18

H6

VSTM19

K5

VSTM20

J5

VSTM21

I7

VSTM22

K9

VSTM23

I8

VSTM24

K10

VSTM25

I6

VSTM26

J7

VSTM27

K11

VSTM28

I9

VSTM29

J11

VSTM30

I11

VSTM31

H11

VSTM32

G11

VSTM33

G10

VSTM34

F10

VSTM35

C10

VSTM36

D10

VSTM37

E11

VSTM38

D11

VSTM39

B11

VSTM40

B10

VSTM41

C4

VSTM42

A4

VSTM43

B5

VSTM44

A3

VSTM46

C5

VSTM45

B3

VSTM47

A10

A_AD_R0

B9

A_AD_R1

A9

A_AD_R2

C9

D7

1

C3006

0.1UF

10%

6.3V

2

X5R
201

MT_PANEL_OUT<0>
MT_PANEL_OUT<1>
MT_PANEL_OUT<2>
MT_PANEL_OUT<3>
MT_PANEL_OUT<4>
MT_PANEL_OUT<5>
MT_PANEL_OUT<6>
MT_PANEL_OUT<7>
MT_PANEL_OUT<8>
MT_PANEL_OUT<9>
MT_PANEL_OUT<10>
MT_PANEL_OUT<11>
MT_PANEL_OUT<12>
MT_PANEL_OUT<13>
MT_PANEL_OUT<14>
MT_PANEL_OUT<15>
MT_PANEL_OUT<16>
MT_PANEL_OUT<17>
MT_PANEL_OUT<18>
MT_PANEL_OUT<19>
MT_PANEL_OUT<20>
MT_PANEL_OUT<21>
MT_PANEL_OUT<22>
MT_PANEL_OUT<23>
MT_PANEL_OUT<24>
MT_PANEL_OUT<25>
MT_PANEL_OUT<26>
MT_PANEL_OUT<27>
MT_PANEL_OUT<28>
MT_PANEL_OUT<29>
MT_PANEL_OUT<30>
MT_PANEL_OUT<31>
MT_PANEL_OUT<32>
MT_PANEL_OUT<33>
MT_PANEL_OUT<34>
MT_PANEL_OUT<35>
MT_PANEL_OUT<36>
MT_PANEL_OUT<37>
MT_PANEL_OUT<38>
MT_PANEL_OUT<39>

NC
NC
NC
NC
NC
NC
NC
NC

Z1_B_ADR<0>
Z1_B_ADR<1>
Z1_B_ADR<2>

34

SPI3_GRAPE_SCLK

5

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

17
17
17

16 36

SPI3_GRAPE_CS_L

5

16 36

SPI3_GRAPE_MOSI

16 36

5

GPIO_GRAPE_RST_L

5

SPI3_GRAPE_MISO

5

16 36

SPI3_GRAPE_SCLK

5

16 36

IN

SPI3_GRAPE_CS_L

5

16 36

IN

SPI3_GRAPE_MOSI

5

16 36

IN

GPIO_GRAPE_FW_DNLD_EN_L

5

IN

5

MIN_NECK_MIDTH SHOULD BE 0.4MM

1

2

1%
1/20W
MF
201

LOAD CURRENT ~ 153UA

R3066

0.1

12

1%

1/20W

MF

201

1

C3000

1UF

10%
25V

2

X5R
603-1

PP18V_GRAPE

VOLTAGE=18V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

16

CRITICAL

6

VCC

U3010

SN74LVC1G126DRYR-M

Z1_CS_OE

16 17

IN

Z2_H_CS_L

16 17

IN

1

2

LLP

OE

A

NC

GND

3

5

NC

PART NUMBER

311S0524 311S0533

ALTERNATE FOR
PART NUMBER

311S0485311S0523

311S0532311S0525

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM

VR_BOOST_SW

C3009

12

0.1UF

10%
25V
X5R
402

VR_BOOST_FBK

4

53

PM_BOOST_EN

8

17

CRITICAL

D3000

SOD-323

AK

B0520WSXG

C3008

33PF

NPO-C0G

0201

5%

25V

1

C3002

470PF

10%
16V

2

X5R-X7R-CERM
0201

1

2

VOLTAGE=18V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR

PP18V_R_GRAPE

R3009

1M

1%
1/16W
MF-LF

402

1

R3012

71.5K

2

6 3

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

=PP3V0_GRAPE

=PP1V8_MISC

34

GPIO_GRAPE_IRQ_L

OUT

=PP3V0_GRAPE

1

C3050

0.1UF

10%

6.3V

2

X5R
201

Z1_CS_L

4

Y

BOM OPTION

1

R3030

10K

5%
1/20W
MF
201

2

DIR_U3007

16 17 34

OUT

REF DES

U3007

U3009

U3010

17

COMMENTS:

1

R3031

10K

5%
1/20W
MF
201

2

1

C3060

0.1UF

10%

6.3V

2

X5R
201

1

C3030

0.1UF

10%

6.3V

2

X5R
201

16

A1

VCCA

SN74LVC1T45YZPR

A

C1
B2

DIR

5

16 36

16 17

3

VCCA

VCCB

U3007

PQFP1

6

1A1

CRITICAL

8

2A1

4

1DIR

1

1OE*

7

1A2

9

2A2

5

2DIR

SN74AVCH4T245RSV

2OE*

(A -> B)

GND

10

=PP3V0_GRAPE

A2

VCCB

U3060

BGA

GND

B1

NOSTUFF

R3060

12

1/20W

SN74LVC1G125DRYR-M

SPI3_GRAPE_MISO

OUT

Z1_CS_OE

IN

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

12

=PP3V0_GRAPE

1

R3025

10K

5%
1/20W
MF
201

2

C3031

0.1UF

10%

6.3V
X5R
201

1

R3032

3.3K

5%
1/20W
MF
201

2

1

1B1
2B1

1B2
2B2

2

15
13

14
12

2

APN:311S0485

11

16 17 34

C2

B

GPIO_GRAPE_IRQ_3V0_L

0

5%
MF

201

CRITICAL

U3009

6

LLP
4

NC

OE*

3

1

SYNC_MASTER=N/A

PAGE TITLE

GRAPE: GROUNDHOG,CONN,BOOST

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

16 17 34

GRAPE_SCLK
GRAPE_CS_L

GRAPE_MOSI
RST_GRAPE_Z1_L

RST_GRAPE_Z2_L

GRAPE_MISO

=PP3V0_GRAPE

1

R3033

10K

5%
1/20W
MF
201

2

Z1_SCLK
Z2_H_CS_L

Z1_MISO

Z1_CS_OE

=PP3V0_GRAPE

1

C3041

0.1UF

10%

6.3V

2

X5R
201

2

5

NC

IN

16 17 34 16 17 34

OUT
OUT

OUT
OUT

17

17
17

17
17
17

17

17
16 17

TO Z1/Z2

17
16 17

16 17 34

Z1_MOSI

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

30 OF 154

SHEET

16 OF 39

124578

TO Z2

IN

D

C

B

17

A

SIZE

D

8 7 6 5 4 3

12

=PP3V0_GRAPE_Z1

34

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.2MM

4.7

1/20W

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

5%
MF

201

N13
N12
M10
M13

M12
K13
L13
L12
M11
N11

N10
K12
J13
F12
G13
J12
E12
E13
H13

D13
D12
H12
F13
C13

G12

H2
G2
D7
C1
F1
J1
D2
D1
K7
H1
E1
E2
J2
G1
F2
J7
K2
N4
M5
N5
M6
N3
M3
L1
K1
L2
N6
M2
M4
M1
N2
N1

N8

M8
N9
M9

N7

E7
M7

MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MT_3V3_INT

1

C3104

4.7UF

20%

6.3V

2

X5R-CERM1
402

IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
IN25
IN26
IN27
IN28
IN29
IN30
IN31
IN32
IN33
IN34
IN35
IN36
IN37
IN38
IN39
IN40
IN41
IN42
IN43
IN44
IN45
IN46
IN47
IN48
IN49
IN50
IN51
IN52
IN53
IN54
IN55
IN56
IN57
IN58
IN59
IN60
IN61
IN62
IN63

R3101

12

D

MT_PANEL_IN<0>

16

MT_PANEL_IN<1>

16

MT_PANEL_IN<2>

16

MT_PANEL_IN<3>

16

MT_PANEL_IN<4>

16

MT_PANEL_IN<5>
MT_PANEL_IN<6>

16

MT_PANEL_IN<7>

16

MT_PANEL_IN<8>

16

MT_PANEL_IN<9>

16

MT_PANEL_IN<10>

16

MT_PANEL_IN<11>

16

MT_PANEL_IN<12>

16

MT_PANEL_IN<13>

16

MT_PANEL_IN<14>

16

MT_PANEL_IN<15>

16

MT_PANEL_IN<16>

16

MT_PANEL_IN<17>

16

MT_PANEL_IN<18>

C

B

16

MT_PANEL_IN<19>

16

MT_PANEL_IN<20>

16

MT_PANEL_IN<21>

16

MT_PANEL_IN<22>

16

MT_PANEL_IN<23>

16

MT_PANEL_IN<24>

16

MT_PANEL_IN<25>

16

MT_PANEL_IN<26>

16

MT_PANEL_IN<27>

16

MT_PANEL_IN<28>

16

MT_PANEL_IN<29>

16

MUX_IN<0>

16

MUX_IN<1>

16

MUX_IN<2>

16

MUX_IN<3>

16

MUX_IN<4>

16

MUX_IN<5>

16

MUX_IN<6>

16

MUX_IN<7>

16

MUX_IN<8>

16

MUX_IN<9>

16

MUX_IN<10>

16

MUX_IN<11>

16

MUX_IN<12>

16

MUX_IN<13>

16

MUX_IN<14>

16

MUX_IN<15>

16

MUX_IN<16>

16

MUX_IN<17>

16

MUX_IN<18>

16

MUX_IN<19>

16

1

C3102

0.1UF

10%

6.3V

2

X5R
201

1

C3103

0.1UF

10%

6.3V

2

X5R
201

G6G7G8K4K10

VDDANA

C10C5C9

VDDDIG

CRITICAL

U3100

BCM5973

BGA

VDDIO

Z1_1V8_OUT

17

B6

V18

1

C3101

2.2UF

20%
4V

2

X5R
402

SCLK

MISO
MOSI

DONE

PCLK

STMOUT

STMIN

B_ADR0
B_ADR1
B_ADR2

BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5

RESET*

CS*

GO

TM

=PP3V0_GRAPE

1

R3155

100K

5%
1/20W
MF
201

2

A11
B10
B9
B8

A8

Z1_GO

B7

Z1_DONE

A12

Z1_PCLK

A10

Z1_STMIN

A13

A5

Z1_B_ADR<0>

B5

Z1_B_ADR<1>

A6

Z1_B_ADR<2>

A2

Z1_BON_L<0>

A1

Z1_BON_L<1>

A3

Z1_BON_L<2>

A4

Z1_BON_L<3>

B4

Z1_BON_L<4>

B3

Z1_BON_L<5>

A9

U3100_TM

A7

RST_GRAPE_Z1_L

Z1_SCLK
Z1_CS_L
Z1_MISO
Z1_MOSI

17 16
17

17

16
16
16

16
16
16
16
16
16

16 17 34

16

OUT

IN
IN
IN

1

2

16 17
16
16 17
16 17

R3181

100

5%
1/32W
MF
01005

ARM9 MCU (Z2 BASED)

C3111

10UF

20%

6.3V
CERM-X5R
0402-1

1

R3173

0

2

1

R3171

0

2

1

C3109

0.1UF

10%

6.3V

2

X5R
201

1

C3110

0.1UF

10%

6.3V

2

X5R
201

5%
1/20W
MF
201

BOOT_CFG0_R
BOOT_CFG1_R

5%
1/20W
MF
201

1

VDDANA AND VDDCORE
ARE EACH GENERATED WITHIN
Z2 AND BYPASSED OUTSIDE

CFG0CFG1
00
0

1

1

0

1

1

2

1

C3112

2.2UF

20%
4V

2

X5R
402

MODE
DEPENDENT 1
DEPENDENT 2
AUTONOMOUS
SLAVE

K48 USES DEPENDENT 2 MODE

=PP3V0_GRAPE

16 17 34

Z2_VDDCORE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

Z2_VDDANA

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

A9

IN0_0

NC

B9

IN0_1

NC

A7

IN1_0

NC

A8

IN1_1

NC

B8

IN2_0

NC

C8

IN2_1

NC

B7

IN3_0

NC

C7

IN3_1

NC

A6

IN4_0

NC

B6

IN4_1

NC

C6

IN5_0

NC

C5

IN5_1

NC

B5

IN6_0

NC

A5

IN6_1

NC

A4

IN7_0

NC

B4

IN7_1

NC

A3

IN8_0

NC

B3

IN8_1

NC

C2

IN9_0

NC

A2

IN9_1

NC

B2

IN10_0

NC

C1

IN10_1

NC

B1

IN11_0

NC

A1

IN11_1

NC

E6

ARMTAPMD*

NC

F6

BOOT_CFG0

D3

BOOT_CFG1

G5

FLOO

NC

F5

LFOO

NC

G7

EXTFLLIN

NC

D2

E1G8H2J5E2

VDDANA

VDDCORE

CRITICAL

U3101

BCM5974CKFBGH

C3H8C4D6D7D8C9D9G2

FBGA

VDDIO

INTERNAL PU

GND

VDDLDO

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

D1

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

1

C3108

0.1UF

10%

6.3V

2

X5R
201

E3

B_ADR0
B_ADR1
B_ADR2

BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

H_CS*

H_SCLK

H_SDI
H_SDO

A_CS*

A_SCLK

A_SDI
A_SDO

TM0
TM1

CLKIN

CLKOUT
RESET*

1

C3105

0.1UF

10%

6.3V

2

X5R
201

Z2_3V3_1V8_IN

1

C3106

0.1UF

10%

6.3V

2

X5R
201

F9
F8

Z1_PCLK

G9
J8

Z1_CS_OE_R

H9

NC_BON_L1

J9

AG_SHLD_TST

H7

NC_BON_L3

J7
H5

NC_BON_L5

J2

GPIO_GRAPE_IRQ_3V0_L

J3

PM_BOOST_EN

H4

Z1_GO

J6

Z1_DONE

G3

GRAPE_CS_L

F3

GRAPE_MOSI

F4

GRAPE_MISO

H6

GRAPE_SCLK

G6

TP_U3101_TCK

E8

TP_U3101_TDI

E9

TP_U3101_TDO

F7

TP_U3101_TMS

H1

Z2_H_CS_L

J1

Z1_SCLK

H3

Z1_MISO

J4

Z1_MOSI

F1

Z2_A_CS_L

G1

TP_Z2_A_SCLK

F2

TP_Z2_A_SDI

G4

TP_Z2_A_SDO

E7

TP_U3101_TM0

D4

U3101_TM1

E5

HOST_REFCLK

E4

NC

D5

RST_GRAPE_Z2_L

1

C3107

4.7UF

20%

6.3V

2

X5R-CERM1
402

1

C3191

10UF

20%

6.3V

2

CERM-X5R
0402-1

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

IN
IN
IN

OUT

16

17

17

16
16 17
16 17
16 17

17

=PP3V0_GRAPE_Z2

1

C3192

10UF

20%

6.3V

2

CERM-X5R
0402-1

R3120

0

5%

1/20W

MF

201

12

16

IN

16

IN

16

OUT

16

IN

=PP3V0_GRAPE

1

R3107

100K

5%
1/20W
MF
201

2

PMU_GPIO_CLK_32K_GRAPE

MAKE_BASE=TRUE

16

IN

34

R3190

1.00

12

1%

1/20W

MF

201

MIN_NECK_MIDTH SHOULD BE 0.4MM

Z1_CS_OE

1

R3160

100K

5%
1/20W
MF
201

2

16 17 34

Z1_1V8_OUT

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR

16

IN

16

OUT

16

OUT

30 36

IN

17

Z2 - PRODUCT STRAP OPTIONS

BON_L4

BON_L5

LOW
FLOAT
FLOAT
ALL OTHER STRAPS
DEFAULT

1

R3180

100

5%
1/32W
MF
01005

2

BON_L3

X

FLOAT FLOAT

LOW

FLOAT

MODE

X K48

K94
J2

CRITICAL ERROR

J2

D

C

B

ZEPHYR 1+ ASIC

A

B1

B2

C2C3C6C7C8

B12

B13

C12D3D11

C11

GNDANA

F7H7L3L4L5L6L7

GNDDIG

GNDIO

L8

L9

C4

L10

L11

B11

SYNC_MASTER=N/A

PAGE TITLE

GRAPE: Z1, Z2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

31 OF 154

SHEET

17 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

=PP1V7_VA_VCP

19 34

CRITICAL

C3612

4.7UF

12

20%

6.3V

X5R-CERM1

402

37

HP_MIC_P

37

HP_MIC_N

CRITICAL

1

C3699

4.7UF

20%

6.3V

2

X5R-CERM1
402

D

GND_AUDIO_CODEC

18 39

C

CRITICAL

C3611

1.0UF

6.3V

0201-MUR

20%
X5R

1

2

1

C3603

1.0UF

20%

6.3V

2

X5R
0201-MUR

R3601

2.21K

12

1%

1/20W

MF

201

L81_MIC2_BIAS_IN

L81_MIC2_BIAS

L81_MIC2_BIAS_FILT_IN

XW3602

CODEC_HP_HS4_REF

18

CODEC_HP_HS3_REF

18

SHORT-8L-0.25MM-SM

SHORT-8L-0.25MM-SM

NOSTUFF

XW3603

NOSTUFF

12

12

B

CODEC_AIN

MAKE_BASE=TRUE

1

C3690

0.01UF

10%

6.3V

2

X5R
01005

CODEC_MIC_BIAS_FILT

MAKE_BASE=TRUE

A

1

C3691

0.01UF

10%

6.3V

2

X5R
01005

AIN1P
AIN1N
AIN3P
AIN3N
AIN4P
AIN4N

MIC1_BIAS_FILT
MIC3_BIAS_FILT
MIC4_BIAS_FILT

C3616

0.01UF

12

10%10V

X5R-CERM0201

C3617

0.01UF

12

10%10V

X5R-CERM0201

R3699

12

CRITICAL

C3605

4.7UF

6.3V

X5R-CERM1

CRITICAL

C3606

4.7UF

6.3V

X5R-CERM1

18
18
18
18
18
18

18
18
18

=PPVCC_MAIN_AUDIO

19 34

=PP1V8_AUDIO

18 34

VOLTAGE=1.7V
MIN_LINE_WIDTH=0.6 MM

1.00

1/20W

20%
402

20%
402

MIN_NECK_WIDTH=0.2 MM

PP1V7_VA_VCP_R

1%
MF

201

12

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

12

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

NC_MIC1_BIAS
AIN1P

18

AIN1N

18

MIC1_BIAS_FILT

18

L82_MIC2_BIAS_FILT

37

L81_AIN2_P

37

L81_AIN2_N

NC_MIC3_BIAS
AIN3P

18

AIN3N

18

MIC3_BIAS_FILT

18

NC_MIC4_BIAS
AIN4P

18

AIN4N

18

MIC4_BIAS_FILT

18

NOSTUFF

CRITICAL

C3618

2.2UF

10%

6.3V
X5R
402

1

C3698

1.0UF

20%

6.3V

2

X5R
0201-MUR

L81_FLYP

L81_FLYC

L81_FLYN

L81_SPEAKER_VQ

1

2

GND_AUDIO_CODEC

1

C3602

0.1UF

20%
4V

2

X5R
01005

CRITICAL

1

C3601

4.7UF

20%

6.3V

2

X5R-CERM1
402

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

=PP1V8_AUDIO

18 34

30

IN

CRITICAL

1

1

1

C3615

0.1UF

20%
4V

2

X5R
01005

G1G8G9

H10

FLYP

J10

FLYC

K10

FLYN

H2

MIC1_BIAS

E3

AIN1+

E4

AIN1-

H3

MIC1_BIAS_FILT

J3

MIC2_BIAS_IN

G4

MIC2_BIAS

K3

MIC2_BIAS_FILT_IN

F3

MIC2_BIAS_FILT

C1

AIN2+

D1

AIN2M

H4

MIC3_BIAS

C3

AIN3+

C2

AIN3-

G3

MIC3_BIAS_FILT

F4

MIC4_BIAS

D2

AIN4+

E2

AIN4-

F2

MIC4_BIAS_FILT

C10

SPEAKER_VQ

18 39

A9

VA

VCP1

VCP0

CS42L81-CWZR-A1

SYM 1 OF 2

E10

NOSTUFF

1

R3640

1.00K

5%
1/32W
MF
01005

2

X5R-CERM

A8E8E9

VD

VP0VLVP1

CRITICAL

U3600

WLCSP

GNDA

GNDP

GNDD

GNDHS

GNDHS

G2

J2

K2

A10

NOSTUFF

SHORT-8L-0.25MM-SM

12

C3604

0.1UF

10%
16V

0201

PP_VPROG_CP_R

VOLTAGE=4.7V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

G10

VPROG_CP

+VCP_FILT

-VCP_FILT

HPDETECT

LINEOUTA
LINEOUTB

LINEOUT_REF

XW3600

NOSTUFF

R3614

0

12

5%

1/20W

MF

201

5

36

5

36

5

36
36

5
5

36

5

36

5

36

5

36

5

36

18 25

5

36

5

36

5

36

5

36

5

30

C3609

4.7UF

20%
10V

2

2

X5R-CERM
0402

1

C3614

0.1UF

10%
16V

2

X5R-CERM
0201

1

C3613

H1

VPROG_MB

GNDCP

AOUT1+

AOUT1_M

AOUT2+
AOUT2-

HPOUTA
HPOUTB

HS3_REF
HS4_REF

FILT+
FILT-

IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
OUT
OUT
IN
OUT

OUT
OUT

0.1UF

10%
16V

2

X5R-CERM
0201

H9

L81_PVCP

J9
K9

L81_NVCP

F10

NC_LEFT_CH_OUT_P

NO_TEST=TRUE

F9

NC_LEFT_CH_OUT_N

NO_TEST=TRUE

D10

NC_RIGHT_CH_OUT_P

NO_TEST=TRUE

D9

NC_RIGHT_CH_OUT_N

NO_TEST=TRUE

J4

L81_MBUS_P

DP

K4

L81_MBUS_N

DN

J8

CODEC_HP_LEFT

K8

CODEC_HP_RIGHT

J1
K1
K7
J7
H8

NO_TEST=TRUE

K6

NO_TEST=TRUE

J6
H6

E1

L81_FILT

F1

22
22

CODEC_HP_HS3
CODEC_HP_HS4

CODEC_HP_DET

IN
IN

HS3
HS4

I2S0_CODEC_ASP_MCK_R
I2S0_CODEC_ASP_BCLK

I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_DIN

I2S3_CODEC_XSP_BCLK
I2S3_CODEC_XSP_LRCK
I2S3_CODEC_XSP_DOUT
I2S3_CODEC_XSP_DIN

L81_MBUS_REF
SPI1_CODEC_CS_L
SPI1_CODEC_SCLK
SPI1_CODEC_MOSI
SPI1_CODEC_MISO

GPIO_CODEC_IRQ_L
PMU_GPIO_CODEC_HS_INT_L
PMU_GPIO_CODEC_RST_L

R3698

1.00

12

1%

1/20W

MF

201

PP_VPROG_MB_R

VOLTAGE=4.7V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

0.15MM

0.30MM

0.15MM

0.30MM

NC_CODEC_LINE_OUT_L
NC_CODEC_LINE_OUT_R

1

C3610

4.7UF

20%

6.3V

2

X5R-CERM1
402

GND_AUDIO_CODEC

L81_MBUS_REF

DIGITAL MIC

DMIC1_FF_SD
DMIC1_FF_SCLK

18 39

OUT

R3610

1/32W

R3611

1/32W

1

R3697

255K

1%
1/20W
MF
201

2

CRITICAL

X5R-CERM1

CRITICAL

X5R-CERM1

18 37
18 37

18 25

R3612

5%

1/32W

R3613

5%

1/32W

12

5%

12

5%

C3607

4.7UF

12

20%

6.3V
402

C3608

4.7UF

12

20%

6.3V
402

18

12

MF

12

MF

NC_DMIC2_SCLK

36

22

MF

01005

22

MF

01005

NOSTUFF

R3696

0

12

5%

1/20W

MF

201

GND_AUDIO_CODEC

L81_DMIC1_FF_SD

22

01005

L81_DMIC1_FF_SCLK

22

01005

I2S0_CODEC_ASP_SDOUT

I2S3_CODEC_XSP_SDOUT

LDO10

29 39

CODEC_HP_DET

18

18 39

CODEC_HP_HS3_REF

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

CODEC_HP_HS4_REF

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

B1

DMIC1_SD

B2

DMIC1_SCLK

B7

NO_TEST=TRUE

DMIC2_SD

B6

DMIC2_SCLK

C8

MCLK

A3

ASP_SCLK

B3

ASP_LRCK

A2

ASP_SDIN

A1

ASP_SDOUT

B4

XSP_SCLK

B5

XSP_LRCK_FSYNC

A5

XSP_SDIN_DAC2_MUTE

A4

XSP_SDOUT

K5

MBUS_REF

C5

CS*

A6

CCLK

B8

CDIN

A7

CDOUT

B9

INT*

B10

WAKE*

C9

RESET*

18

18

CS42L81-CWZR-A1

6 3

PLACE R3630 & R3631 CLOSE TO U3600

L81_MBUS_P

18 37

L81_MBUS_N

18 37

R3620

3.3K

12

CRITICAL

U3600

WLCSP

SYM 2 OF 2

1/32W
01005

5%
MF

CODEC_HP_DET_R

1

2

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18

TSTI0
TSTI1
TSTI2

240-OHM-0.2A-0.8-OHM

NOSTUFF

C3620

4700PF

10%
10V
X7R
201

PLACE L3600 TO 3605 CLOSE
TO THE HP CONNECTOR

C6
D3
D5
D6
D7
D8
E5
E6
E7
F5
F6
F7
F8
G5
G6
G7
H5
H7
J5

C4
C7
D4

MIKEY BUS FILTER

SIGNAL_MODEL=EMPTY

1

C3630

100PF

5%
25V

2

NP0-CERM

R3630

12

12

5%

1/20W

MF

201

R3631

12

12

5%

1/20W

MF

201

0201

NOSTUFF

1

C3631

100PF

5%
25V

2

NP0-CERM
0201

SIGNAL_MODEL=EMPTY

1

C3632

100PF

5%
25V

2

NP0-CERM
0201

L3620

1 2

0201

HP_LEFT_FILT

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

MAKE_BASE=TRUE

HP_RIGHT_FILT

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

MAKE_BASE=TRUE

HP_HS3_FILT

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

HP_HS4_FILT

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

HP_HS3_REF_FILT

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

MAKE_BASE=TRUE

HP_HS4_REF_FILT

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

MAKE_BASE=TRUE

CONN_HP_HEADSET_DET

SYNC_MASTER=N/A

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MIKEY_TS_P
MIKEY_TS_N

20

IN

22

OUT

22

OUT

22

IN

22

IN

22

IN

22

IN

TO HEADPHONE JACK

AUDIO: L81 CODEC

Apple Inc.

R

12

25 37

BI

25 37

BI

DRAWING NUMBER

051-9385

REVISION

BRANCH

18 OF 39

PAGE

36 OF 154

SHEET

124578

SYNC_DATE=N/A

A.0.0

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

34

=PPVCC_MAIN_AUDIO

18
19

D

C

34

=PPVCC_MAIN_AUDIO

18
19

B

A

CRITICAL

1

C3741

4.7UF

20%
10V

2

X5R-CERM
0402

CRITICAL

1

C3751

4.7UF

20%
10V

2

X5R-CERM
0402

CRITICAL

1

C3742

4.7UF

20%
10V

2

X5R-CERM
0402

CRITICAL

1

C3752

4.7UF

20%
10V

2

X5R-CERM
0402

29 34 39

CRITICAL

1

C3743

4.7UF

20%
10V

2

X5R-CERM
0402

CRITICAL

1

C3753

4.7UF

20%
10V

2

X5R-CERM
0402

PP1V7_VA_VCP

LEFT SPEAKER AMP

I2C ADDRESS: 1000000X

1

C3744

0.1UF

10%
16V

2

X5R-CERM
0201

19 25 30 36

5

19 25 30 36

5

5

5

19

19

5

19

5

19

5

5

19

5

19

5

19

L19_L_VBOOST

CRITICAL

1

2

2.2UH-20%-3.3A-0.115OHM

1 2
TFA302610A-SM

C3745

22UF

20%
10V
X5R-CERM
0603-1

CRITICAL

L3740

CRITICAL

1

C3710

22UF

20%
10V

2

X5R-CERM
0603-1

I2C0_SDA_1V8
I2C0_SCL_1V8
GPIO_SPKAMP_LEFT_IRQ_L
GPIO_SPKAMP_RST_L
GPIO_SPKAMP_KEEPALIVE

I2S1_SPKAMP_MCK_R
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_LRCK
I2S1_SPKAMP_DOUT
I2S1_SPKAMP_DIN

1

C3711

0.1UF

10%
16V

2

X5R-CERM
0201

L19_L_SWITCH

1

C3712

27PF

5%
16V

2

NP0-C0G
01005

A2
B2

D5
D6
A7
A6
D7
C7
E7
E6
F6
F7
E5

A1

B1

VBST

CS35L19B-CWZR

SW

SDA
SCL
INT*
RESET*
ALIVE

ADO

MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT

GNDP

A3B3B4

C1D1A4

CRITICAL

C3C4D3

VP

U3740

WLCSP
VER1

D4

F5

A5

VA

LDO_FILT

VSENSE­VSENSE+

ISENSE­ISENSE+

GNDA

B5

B6

C6E4F3

RIGHT SPEAKER AMP

I2C ADDRESS: 1000001X

L19_R_VBOOST

1

C3754

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

2

2.2UH-20%-3.3A-0.115OHM

I2C0_SDA_1V8

5

19 25 30 36

I2C0_SCL_1V8

5

19 25 30 36

GPIO_SPKAMP_RIGHT_IRQ_L

5

GPIO_SPKAMP_RST_L

5

19

GPIO_SPKAMP_KEEPALIVE

5

19

I2S1_SPKAMP_MCK_R

5

19

I2S1_SPKAMP_BCLK

5

19

I2S1_SPKAMP_LRCK

5

19

I2S1_SPKAMP_DOUT

5

19

I2S1_SPKAMP_DIN

5

19

CRITICAL

1

C3755

C3720

22UF

22UF

20%

20%

10V

10V

2

X5R-CERM

X5R-CERM

0603-1

0603-1

CRITICAL

L3750

1 2
TFA302610A-SM

1

C3721

0.1UF

10%
16V

2

X5R-CERM
0201

L19_R_SWITCH

1

C3722

27PF

5%
16V

2

NP0-C0G
01005

A2
B2

D5

SDA

D6

SCL

A7

INT*

A6

RESET*

D7

ALIVE

C7

ADO

E7

MCLK

E6

SCLK

F6

LRCK/FSYNC

F7

SDIN

E5

SDOUT

A1

B1

VBST

CS35L19B-CWZR

SW

GNDP

A3B3B4

C3C4D3

VP

CRITICAL

U3750

WLCSP
VER1

D4

F5

A5

VA

LDO_FILT

VSENSE­VSENSE+

ISENSE­ISENSE+

GNDA

B5

B6

C6E4F3

C1D1A4

6 3

FILT+

OUT+
OUT-

IREF+

FILT+

OUT+
OUT-

IREF+

1

C3713

27PF

5%
16V

2

NP0-C0G
01005

F2

L19_L_FILT

C5

L19_L_LDO_FILT

E3

SPKR_L_VSENSE_N_FILT

37

E2

37

SPKR_L_VSENSE_P_FILT

F1

37

SPKR_L_SES_N

E1

37

SPKR_L_SES_P

D2

37

SPKR_L_P

C2

37

SPKR_L_N

B7

L19_L_IREF

1

R3741

44.2K

1%
1/20W
MF
201

2

F4

1

C3723

27PF

5%
16V

2

NP0-C0G
01005

F2

L19_R_FILT

C5

L19_R_LDO_FILT

E3

SPKR_R_VSENSE_N_FILT

37

E2

37

SPKR_R_VSENSE_P_FILT

F1

37

SPKR_R_SES_N

E1

37

SPKR_R_SES_P

D2

37

SPKR_R_P

C2

SPKR_R_N

B7

L19_R_IREF

1

R3751

44.2K

1%
1/20W
MF
201

2

F4

=PP1V7_VA_VCP

1

C3746

0.1UF

10%

6.3V

2

X5R
201

6.3V

6.3V

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

NOSTUFF

1

C3764

18PF

5%
25V

2

NP0-C0G-CERM
0201

=PP1V7_VA_VCP

1

C3756

0.1UF

10%

6.3V

2

X5R
201

6.3V

6.3V

37

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

NOSTUFF

1

C3784

18PF

5%
25V

2

NP0-C0G-CERM
0201

C3747

4.7UF

12

20%

C3748

4.7UF

12

20%

OMIT_TABLE

1

R3743

10

5%
1/20W
MF
201

2

C3757

4.7UF

12

20%

C3758

4.7UF

12

20%

OMIT_TABLE

1

R3753

10

5%
1/20W
MF
201

2

18 19 34

X5R-CERM1

402

X5R-CERM1

402

NOSTUFF

C3760

0.01UF

12

X5R-CERM

10%

0201

10V

CRITICAL

R3740

0.100

12

1%

1/4W

MF

0805

18 19 34

X5R-CERM1

402

X5R-CERM1

402

NOSTUFF

C3780

0.01UF

12

X5R-CERM

10%

0201

10V

CRITICAL

R3750

0.100

12

1%

1/4W

MF

0805

OMIT_TABLE

1

R3742

10

5%
1/20W
MF
201

2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

SPKR_L_FLR

37

NOSTUFF

1

C3761

18PF

5%
25V

2

NP0-C0G-CERM
0201

OMIT_TABLE

1

R3752

10

5%
1/20W
MF
201

2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

37

SPKR_R_FLR

NOSTUFF

1

C3781

18PF

5%
25V

2

NP0-C0G-CERM
0201

OMIT_TABLE

CRITICAL

FL3741

220-OHM-2.0A

1 2

0603

OMIT_TABLE

CRITICAL

FL3740

220-OHM-2.0A

1 2

0603

OMIT_TABLE

CRITICAL

FL3751

220-OHM-2.0A

1 2

0603

OMIT_TABLE

CRITICAL

FL3750

220-OHM-2.0A

1 2

0603

1

C3740

8.2PF

+/-0.1PF%
25V

2

CER
0201

SPKR_L_CONN_N

1

C3749

8.2PF

+/-0.1PF%
25V

2

CER
0201

1

C3750

8.2PF

+/-0.1PF%
25V

2

CER
0201

SPKR_R_CONN_N

1

C3759

8.2PF

+/-0.1PF%
25V

2

CER
0201

SPKR_L_CONN_P

NOSTUFF

1

C3763

3.9PF

+/-0.1PF
25V

2

NP0-C0G-CERM
0201

NOSTUFF

1

C3766

3.9PF

+/-0.1PF
25V

2

NP0-C0G-CERM
0201

SPKR_R_CONN_P

NOSTUFF

1

C3783

3.9PF

+/-0.1PF
25V

2

NP0-C0G-CERM
0201

NOSTUFF

1

C3786

3.9PF

+/-0.1PF
25V

2

NP0-C0G-CERM
0201

NOSTUFF

NP0-CERM

NOSTUFF

NP0-CERM

19 37

19 37

19 37

19 37

C3767

100PF

0201

C3768

100PF

0201

25V

25V

PART#

117S0002

113S0022

DESCRIPTION

QTY

RES,MF,1/20W,0.0OHM,5,0201,SMD

4

RES,MF,1/10W,0OHM,5,0603,SMD,LF

4

REFERENCE DESIGNATOR(S)

R3742,R3743,R3752,R3753

FL3740,FL3741,FL3750,FL3751

CRITICAL BOM OPTION

? ?

? ?

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

D

R3745

SPKR_L_VSENSE_N

10K

12

5%

1

5%

2

1

5%

2

1/20W

MF

201

SPKR_L_VSENSE_P

R3744

10K

12

5%

1/20W

MF

201

19 37

19 37

SPEAKER CONNECTOR

C

APN 518S0672

CRITICAL

J3700

78171-6006

M-RT-SM

1

2

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

37 OF 154

SHEET

19 OF 39

124578

7

1
2
3
4
5
6

8

B

A

SIZE

D

NOSTUFF

C3787

100PF

NP0-CERM

0201

NOSTUFF

C3788

100PF

NP0-CERM

0201

5

25V

25V

19 37

19 37

19 37

19 37

OUT

19 37

19 37

19 37

19 37

1

5%

2

1

5%

2

SPKR_L_CONN_P

SPKR_L_VSENSE_P

SPKR_L_CONN_N

SPKR_L_VSENSE_N

SPK_ID

SPKR_R_CONN_P

SPKR_R_VSENSE_P

SPKR_R_CONN_N

SPKR_R_VSENSE_N

R3755

10K

12

5%

1/20W

MF

201

R3754

10K

12

5%

1/20W

MF

201

XW3774

SM

SIGNAL_MODEL=EMPTY

12

XW3775

SM

SIGNAL_MODEL=EMPTY

12

XW3776

SM

SIGNAL_MODEL=EMPTY

12

XW3777

SM

SIGNAL_MODEL=EMPTY

12

PLACE XWS CLOSE TO CONNECTOR

SPKR_R_VSENSE_N

SPKR_R_VSENSE_P

19 37

19 37

NOSTUFF

CRITICAL

1

C3770

100PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

SYNC_MASTER=N/A

PAGE TITLE

CRITICAL

C3771

100PF

NP0-C0G

01005

16V

1

5%

2

AUDIO: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NOSTUFF

CRITICAL

1

C3772

100PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

CRITICAL

C3773

100PF

NP0-C0G

01005

16V

5%

8 7 6 5 4 3

WWW.AliSaler.Com

12

D

CONN_ISP0_CAM_RF_SHUTDOWN

22

CONN_I2C2_SCL_3V0

22 36

CONN_I2C1_SCL_1V8

22 36

CONN_DMIC1_FF_SD

22

CONN_ISP0_CAM_RF_I2C_SCL

22 36

CONN_HALL_IRQ

22

MIPI0C_CAM_RF_DATA_F_P<0>

21 37

MIPI0C_CAM_RF_DATA_F_N<1>

21 37

C

APN: 518S0828

MIPI0C_CAM_RF_CLK_F_N

21 37

CONN_ISP1_CAM_FF_I2C_SCL

22 36

B

MIPI1C_CAM_FF_CLK_F_N

21 37

MIPI1C_CAM_FF_DATA_F_N<0>

21 37

CONN_PROX_IRQ_L

22

GPIO_BTN_ONOFF_L

5

30

GPIO_BTN_VOL_DOWN_L

5

CONN_ACCEL_IRQ1_L

22

CONN_HP_HEADSET_DET

18

CONN_HP_RIGHT_FILT1

22

CONN_HP_HS3_REF_MIC2

22

CONN_HP_HS4_REF_MIC1

22

CRITICAL

J5400

502250-8037-B

F-RT-SM

40
38

1

2

3

4

5

6

7

8

9

CRITICAL

J5401

F-RT-SM

1
3
5
7
9

10
12
14
16
18
20
22
24
26
28
30
32
34
36

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36

11
13
15
17

NC

19

NC

21

NC

23
25
27
29
31
33
35
37

39
41

502250-8037-B

40
38

NC
NC

11
13
15
17
19
21
23
25
27

NC

29
31
33
35
37

39
41

CONN_ISP1_CAM_FF_SHUTDOWN_L
CONN_I2C2_SDA_3V0
CONN_ALS_IRQ_L
CONN_I2C1_SDA_1V8
CONN_DMIC1_FF_SCLK
CONN_ISP0_CAM_RF_I2C_SDA

PP3V0_S2R_HALL_FLT

NC
NC
NC

CONN_ISP0_CAM_RF_RST_L

PP3V0_SENSOR_FLT
PP1V8_SENSOR_FLT
PP2V8_CAM_FLT

CONN_ISP0_CAM_RF_CLK
MIPI0C_CAM_RF_DATA_F_N<0>

MIPI0C_CAM_RF_DATA_F_P<1>

NC
NC

MIPI0C_CAM_RF_CLK_F_P
CONN_ISP1_CAM_FF_CLK
CONN_ISP1_CAM_FF_I2C_SDA
MIPI1C_CAM_FF_CLK_F_P

MIPI1C_CAM_FF_DATA_F_P<0>
CONN_GYRO_IRQ2
GPIO_BTN_SRL_L

NC

GPIO_BTN_VOL_UP_L

CONN_ACCEL_IRQ2_L
CONN_GYRO_IRQ1
CONN_HP_LEFT_FILT1
CONN_HP_HS3_FILT1
CONN_HP_HS4_FILT1

22
22 36
22
22 36
22
22 36
21
22

5
21
21
22 36
21 37

21 37

21

21 37
22 36
22 36
21 37

21 37
22
5

30

5

22
22
22
22
22

APN: 518S0828

D

C

B

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

SENSOR FLEX CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

54 OF 154

SHEET

20 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

NOSTUFF

R5500

0

12

5%

1/20W

MF

201

CRITICAL

L5500

90-OHM-50MA

TCM0605-1

SYM_VER-1

MIPI0C_CAM_RF_DATA_N<1>

7

37

D

BI

37

MIPI0C_CAM_RF_DATA_P<1>

7

BI

1

2 3

R5501

12

R5510

12

CRITICAL

90-OHM-50MA

TCM0605-1

MIPI0C_CAM_RF_DATA_N<0>

7

37

BI

MIPI0C_CAM_RF_DATA_P<0>

7

37

BI

C

1

2 3

R5511

12

R5520

12

CRITICAL

90-OHM-50MA

TCM0605-1

MIPI0C_CAM_RF_CLK_N

7

37

IN

7

IN

MIPI0C_CAM_RF_CLK_P

37

B

1

2 3

R5521

12

R5530

12

CRITICAL

90-OHM-50MA

TCM0605-1

7

IN

7

IN

MIPI1C_CAM_FF_CLK_P

MIPI1C_CAM_FF_CLK_N

37

37

A

MIPI1C_CAM_FF_DATA_P<0>

7

37

BI

MIPI1C_CAM_FF_DATA_N<0>

7

37

BI

1

2 3

R5531

12

R5540

12

CRITICAL

90-OHM-50MA

TCM0605-1

1

2 3

R5541

12

NOSTUFF

0

5%

1/20W

MF

201

NOSTUFF

0

5%

1/20W

MF

201

L5510

SYM_VER-1

NOSTUFF

0

5%

1/20W

MF

201

NOSTUFF

0

5%

1/20W

MF

201

L5520

SYM_VER-1

NOSTUFF

0

5%

1/20W

MF

201

NOSTUFF

0

5%

1/20W

MF

201

L5530

SYM_VER-1

NOSTUFF

0

5%

1/20W

MF

201

NOSTUFF

0

5%

1/20W

MF

201

L5540

SYM_VER-1

NOSTUFF

0

5%

1/20W

MF

201

4

MIPI0C_CAM_RF_DATA_F_N<1>

MIPI0C_CAM_RF_DATA_F_P<1>

4

MIPI0C_CAM_RF_DATA_F_N<0>

MIPI0C_CAM_RF_DATA_F_P<0>

4

MIPI0C_CAM_RF_CLK_F_N

MIPI0C_CAM_RF_CLK_F_P

4

MIPI1C_CAM_FF_CLK_F_P

MIPI1C_CAM_FF_CLK_F_N

4

MIPI1C_CAM_FF_DATA_F_P<0>

MIPI1C_CAM_FF_DATA_F_N<0>

20 37

BI

20 37

BI

20 37

BI

20 37

BI

20 37

OUT

20 37

OUT

20 37

OUT

20 37

OUT

20 37

BI

20 37

BI

=PP3V0_S2R_HALL

23 34

=PP1V8_SENSOR

34

=PP2V8_CAM

34

=PP3V0_SENSOR

34

L5550

240-OHM-0.2A-0.8-OHM

1 2

0201

L5560

240-OHM-25%-400MA

1 2

0402

DCR 0.31

L5570

240-OHM-25%-400MA

1 2

0402

DCR 0.31

L5580

240-OHM-25%-400MA

1 2

0402

DCR 0.31

1

C5550

82PF

25V

2

NP0-C0G-CERM
0201

1

C5560

82PF

25V

2

NP0-C0G-CERM
0201

1

C5570

82PF

25V

2

NP0-C0G-CERM
0201

1

C5580

82PF

25V

2

NP0-C0G-CERM
0201

1

C5551

1UF

10%5%
10V

2

X5R
402

1

C5561

1UF

10%5%
10V

2

X5R
402

1

2

1

2

C5571

1UF

10%5%
10V
X5R
402

C5581

1UF

10%5%
10V
X5R
402

1

C5552

1000PF

10%
16V

2

X7R-CERM
0201

1

C5562

1000PF

10%
16V

2

X7R-CERM
0201

1

2

C5572

1000PF

10%
16V
X7R-CERM
0201

1

C5582

0.1UF

10%

6.3V

2

X5R
201

1

C5553

8.2PF

+/-0.1PF%
25V

2

CER
0201

1

C5563

8.2PF

+/-0.1PF%
25V

2

CER
0201

1

2

C5573

8.2PF

+/-0.1PF%
25V
CER
0201

1

C5583

1000PF

10%
16V

2

X7R-CERM
0201

PP3V0_S2R_HALL_FLT

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V8_SENSOR_FLT

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP2V8_CAM_FLT

VOLTAGE=2.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_SENSOR_FLT

VOLTAGE=3.0V

C5584

8.2PF

+/-0.1PF%
25V
CER
0201

SYNC_MASTER=N/A

PAGE TITLE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

1

2

SENSOR CONN FILTERS 1

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

6 3

12

20

20

20

5

20

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

55 OF 154

SHEET

21 OF 39

124578

SYNC_DATE=N/A

A.0.0

SIZE

D

C

B

A

D

COMMENTS:

WWW.AliSaler.Com

OUT
OUT

IN

12

RADAR:8376668

18
18
18

OUT
OUT

IN

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

18
18
18

8 7 6 5 4 3

NC

ALTERNATE FOR
PART NUMBER

155S0373

BOM OPTION

?

REF DES

U5600,U5610,U5620,U5630,U5640,U5650,U5660,U5670

HP_HS4_FILT
HP_HS3_FILT
HP_LEFT_FILT

HP_HS4_REF_FILT
HP_HS3_REF_FILT
HP_RIGHT_FILT

PART NUMBER

155S0643

U5600

800MHZ-100MA-27PF

7
5

36

5
5

36

ISP1_CAM_FF_SHUTDOWN_L

IN

I2C2_SDA_3V0

BI

GPIO_ALS_IRQ_L

OUT

I2C1_SDA_1V8

BI

D

18

5

36

5

36

7

18

7

C

7

36

IN

ISP0_CAM_RF_CLK

22 OHM
PLACE IT NEAR U0600

R5630

22

12

36 36

5%
1/16W
MF-LF

402

ISP0_CAM_RF_C

NOSTUFF

1

C5630

1000PF

10%
16V

2

X7R-CERM
0201

R5631

22

12

5%
1/16W
MF-LF

402

36

7
7

36

30

DMIC1_FF_SD

IN

I2C1_SCL_1V8

IN

I2C2_SCL_3V0

IN

ISP0_CAM_RF_SHUTDOWN

IN

DMIC1_FF_SCLK

IN

ISP0_CAM_RF_I2C_SDA

BI

ISP0_CAM_RF_RST_L

IN

ISP0_CAM_RF_I2C_SCL

IN

ISP0_CAM_RF_FILT

PMU_GPIO_HALL_IRQ

OUT

0603

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

GND

9

10

U5610

800MHZ-100MA-27PF

0603

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

GND

9

10

U5620

800MHZ-100MA-27PF

0603

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

GND

9

10

U5630

800MHZ-100MA-27PF

0603

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

GND

9

10

5
6
7
8

CONN_ISP1_CAM_FF_SHUTDOWN_L
CONN_I2C2_SDA_3V0
CONN_ALS_IRQ_L
CONN_I2C1_SDA_1V8

5
6
7
8

5
6
7
8

5
6
7
8

CONN_DMIC1_FF_SD
CONN_I2C1_SCL_1V8
CONN_I2C2_SCL_3V0
CONN_ISP0_CAM_RF_SHUTDOWN

CONN_DMIC1_FF_SCLK
CONN_ISP0_CAM_RF_I2C_SDA
CONN_ISP0_CAM_RF_RST_L
CONN_ISP0_CAM_RF_I2C_SCL

DO NOT STUFF WITHOUT
AUDIO TEM APPROVAL

AND RECHARACTERIZATION

CONN_ISP0_CAM_RF_CLK

NCNC
NCNC

CONN_HALL_IRQ

NOSTUFF

1

C5620

27PF

5%
25V

2

NP0-C0G
0201

20

OUT

20 36

BI

20

IN

20 36

BI

20

IN

20 36

OUT

20 36

OUT

20

OUT

20

OUT

20 36

BI

20

OUT

20 36

OUT

CONN_HP_HS4_FILT1

20

IN

CONN_HP_HS3_FILT1

20

IN

CONN_HP_LEFT_FILT1

20

OUT

NC

CRITICAL

U5660

800MHZ-100MA-27PF

0603-1

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

GND

9

10

5
6
7
8

CRITICAL

U5670

800MHZ-100MA-27PF

CONN_HP_HS4_REF_MIC1

20

IN

CONN_HP_HS3_REF_MIC2

20

IN

CONN_HP_RIGHT_FILT1

20

OUT

20 36

OUT

20

IN

NC NC

0603-1

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

5
6
7
8

GND

9

10

B

R5640

22

7

36

ISP1_CAM_FF_CLK

IN

22 OHM
PLACE IT NEAR U0600

12

5%
1/16W
MF-LF

402

ISP1_CAM_FF_C

NOSTUFF

1

C5640

2

A

1000PF

10%
16V
X7R-CERM
0201

R5641

22

12

5%
1/16W
MF-LF

402

36

7

IN

5

OUT

7

36

BI

5

OUT

5

OUT

5

OUT

5

OUT

ISP1_CAM_FF_I2C_SCL
GPIO_PROX_IRQ_L
ISP1_CAM_FF_I2C_SDA
ISP1_CAM_FF_FILT

36 36

GPIO_GYRO_IRQ1
GPIO_ACCEL_IRQ2_L
GPIO_GYRO_IRQ2
GPIO_ACCEL_IRQ1_L

U5640

800MHZ-100MA-27PF

0603

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

GND

9

10

U5650

800MHZ-100MA-27PF

0603

1

IN1

2

IN2

3

IN3

4

IN4

OUT1
OUT2
OUT3
OUT4

GND

9

10

5
6
7
8

CONN_ISP1_CAM_FF_I2C_SCL
CONN_PROX_IRQ_L
CONN_ISP1_CAM_FF_I2C_SDA
CONN_ISP1_CAM_FF_CLK

CONN_GYRO_IRQ1

5

CONN_ACCEL_IRQ2_L

6

CONN_GYRO_IRQ2

7

CONN_ACCEL_IRQ1_L

8

20 36

OUT

20

IN

20 36

BI

20 36

OUT

20

IN

20

IN

20

IN

20

IN

6 3

SYNC_MASTER=N/A

PAGE TITLE

SENSOR CONN FILTERS 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

56 OF 154

SHEET

22 OF 39

124578

SIZE

B

A

D

8 7 6 5 4 3

12

D

E75_ACC_POUT_ID1

25

FERR-22-OHM-1A-0.065-OHM

FERR-22-OHM-1A-0.065-OHM

E75_ACC_POUT_ID2

PPVBUS_USB_EMI

C

34 39

1 2

0.055 OHM DCR

1 2

0.055 OHM DCR

1

C5721

27PF

5%
25V

2

NP0-C0G
0201

L5700

0201

L5701

0201

1

C5722

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

C

DZ5791

14.2V-6PF

0201-1

A

C

DZ5792

14.2V-6PF

0201-1

A

FERR-70-OHM-4A

1

R5790

100K

5%
1/20W
MF
201

2

CONN_E75_ACC_POUT_ID1

CONN_E75_ACC_POUT_ID2

L5757

1 2

0603

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

2

DZ5760

27V-100PF

0402

1

24

24 25

DISCRETE_BTN_HOME_L

24

IN

2

1

1

C5750

27PF

5%
25V

2

NP0-C0G
0201

1

C5783

0.01UF

10%
50V

2

X7R
402

CONN_E75_PPVBUS_USB

VOLTAGE=6.0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

24

CONN_HALL2_IRQ

24

IN

2

1

PART NUMBER

377S0116 377S0108
155S0320
155S0657

DZ5710

6.8V-100PF

0201

NOSTUFF

DZ5740

6.8V-100PF

0201

WHEN HALL2 WAS USED
USING PADS TO KEEP THIS UNUSED
SIGNAL FROM FLOATING

ALTERNATE FOR
PART NUMBER

155S0513
155S0537
155S0397155S0741

120-OHM-200MA

1

C5710

8.2PF

+/-0.1PF%
25V

2

CER
0201

120-OHM-200MA

1

C5740

0

5%
1/20W
MF
201

2

BOM OPTION

FL5710

1 2

0201

NOSTUFF

FL5740

1 2

0201

REF DES

COMMENTS:

RDAR://PROBLEM/8370432

DZ5760

RDAR://PROBLEM/9625601

L5700,L5701

FL5710,FL5750

L5757

RDAR://PROBLEM/11238851

GPIO_BTN_HOME_L

1

C5711

8.2PF

+/-0.1PF%
25V

2

CER
0201

PMU_GPIO_HALL2_IRQ

1

R5741

0

5%
1/20W
MF
201

2

USED TO BE C5741 27PF CAPUSED TO BE C5740 27PF CAP
WHEN HALL2 WAS USED
USING PADS TO KEEP THIS UNUSED
SIGNAL FROM FLOATING

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

5

30

OUT

30

OUT

D

C

NOSTUFF

=PP3V0_S2R_HALL

240-OHM-0.2A-0.8-OHM

B

A

6 3

L5730

1 2

0201

NOSTUFF

1

C5730

82PF

5%

25V

2

NP0-C0G-CERM
0201

NOSTUFF

1

C5731

1UF

10%
10V

2

X5R
402

NOSTUFF

1

C5732

1000PF

10%
16V

2

X7R-CERM
0201

1

C5733

0

5%
1/20W
MF
201

2

USED TO BE C5733 8.2PF CAP
WHEN HALL2 WAS USED
USING PADS TO KEEP THIS UNUSED
SIGNAL FROM FLOATING

SYNC_MASTER=N/A

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PP3V0_S2R_HALL2_FLT

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

E75 DOCK SUPPORT

Apple Inc.

R

24 21 34

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=N/A

A.0.0

57 OF 154

23 OF 39

SIZE

B

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

D

D

IO FLEX CONNECTOR

PN 516S0542 (PLUG - MALE)

CRITICAL

J5900

CPB6450-0101F

M-ST-SM

51

C

CONN_E75_ACC_DET_L

25

OUT

CONN_E75_DPAIR2_P

25 36

BI

CONN_E75_DPAIR2_N

25 36

BI

CONN_E75_DPAIR1_N

25 36

BI

CONN_E75_DPAIR1_P

25 36

BI

1

C5900

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

B

53

1

2

3

4

5

6

78

10

9
11 12
13 14
15 16
17 18
19

20
21 22
23 24
25 26
27 28
29

30
31 32
33 34
35 36
37 38
39

40
41 42
43 44
45 46
47 48
49

50

52

54

CONN_E75_ACC_POUT_ID1

1

C5910

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM

CONN_E75_ACC_POUT_ID2

1

C5920

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM

NC
NC

CONN_E75_PPVBUS_USBCONN_E75_PPVBUS_USB

01005

23 24 23 24

01005

23

23

C

B

A

518S0692

CRITICAL

J5950

FF18-6A-R11AD-B-3H

PP3V0_S2R_HALL2_FLT

23

CONN_HALL2_IRQ

23

OUT

DISCRETE_BTN_HOME_L

23

OUT

F-RT-SM
1

2

NC

3
4

NC

5
6

6 3

SYNC_MASTER=N/A

PAGE TITLE

IO FLEX CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

58 OF 154

SHEET

24 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

12

=PP3V0_S2R_TRISTAR

34

1

C5930

1.0UF

20%

6.3V

2

X5R
0201-MUR

=PP1V8_S2R_USBMUX

25 34

1

C5931

D

TO BB USB

ACCESSORY USB

ACCESSORY UART

AP DEBUG UART

UART1_BB_RXD

5

26 36

UART1_BB_TXD

5

26 36

BB DEBUG UART

(T’S OFF TO H5G UART1)

C

MLB_A

1

R5970

100K

5%
1/20W
MF
201

2

MLB_A

1

R5971

100K

5%
1/20W
MF
201

2

0.1UF

2

18 37
18 37 23

25 36
25 36

10

4

36

BI

4

36

BI

36

5
5

36

5

36
36

5

1

C5935

0.1UF

10%

6.3V

2

X5R
201

1

C5941

10%

6.3V
X5R
201

MIKEY_TS_P
MIKEY_TS_N

USB_TS_BBMUX_P
USB_TS_BBMUX_N

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

USB_BRICKID
USB_AP_P

USB_AP_N
UART2_TS_ACC_TXD

UART2_TS_ACC_RXD
UART6_AP_TXD

UART6_AP_RXD

JTAG_AP_TCK_TS_R
JTAG_AP_TMS_TS_R

1

C5940

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

C3
C4

A1
B1

C2
A3

B3
E2

E1
F2

F1
D2

D1
A5

B5

DIG_DP
DIG_DN

USB1_DP
USB1_DN

BRICK_ID
USB0_DP

USB0_DN
UART0_TX

UART0_RX
UART1_TX

UART1_RX
UART2_TX

UART2_RX
JTAG_CLK

JTAG_DIO

F3

VDD_1V8

U5900

THS7383IYKAR

OMIT_TABLE

TRISTAR

1

C5942

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM

DP1
DN1

DP2
DN2

SDA
SCL
INT

01005

F6
C5
E5

A2

36

B2

36

A4

36

B4

36

E3

30

D6
E4

B6
D3

D4
C6
E6

F4

D5

VDD_3V0

WCSP

CON_DET_L

OVP_SW_EN*

SWITCH_EN

HOST_RESET

DVSS

DVSS

A6C1F5

ACC_PWR

P_IN
ACC1
ACC2

BYPASS

DVSS

=PP3V3_ACC

1

C5932

0.1UF

10%

6.3V

2

X5R
201

E75_ACC_POUT_ID1
E75_ACC_POUT_ID2

TS_E75_DPAIR1_P
TS_E75_DPAIR1_N

TS_E75_DPAIR2_P
TS_E75_DPAIR2_N

PMU_E75_ACC_DET_L
OVP_SW_EN_L
RST_AP_L

TS_HOST_RESET
I2C0_SDA_1V8

I2C0_SCL_1V8
PMU_GPIO_TS_INT
BYPASS_U5900

1

C5944

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

34

23

5
5
5

OUT

IN

OUT

19 30 36
19 30 36
30

1

2

C5943

8.2PF

+/-0.5PF
16V
NP0-C0G-CERM
01005

29

4

26 30 39

25

1

C5933

1.0UF

20%

6.3V

2

X5R
0201-MUR

PPVBUS_PROT

1

2

C5934

1UF

10%
25V
X5R
0402

CRITICAL

L5930

29

90-OHM-50MA

TCM0605-1

SYM_VER-1

1

2 3

CRITICAL

L5931

90-OHM-50MA

TCM0605-1

SYM_VER-1

1

2 3

4

CRITICAL

2

DZ5900

ESD0P2RF-02LS

TSSLP-2-1

1

4

CRITICAL

2

DZ5902

ESD0P2RF-02LS

TSSLP-2-1

1

PART#

343S0614

CRITICAL

2

DZ5901

ESD0P2RF-02LS

TSSLP-2-1

1

CRITICAL

2

DZ5903

ESD0P2RF-02LS

TSSLP-2-1

1

DESCRIPTION

QTY

IC,ASIC,TRISTAR,CBTL1608,A1,WLCSP36

CONN_E75_DPAIR1_P

CONN_E75_DPAIR1_N

CONN_E75_DPAIR2_P

CONN_E75_DPAIR2_N

REFERENCE DESIGNATOR(S)

U59001

24 36

BI

24 36

BI

24 36

BI

24 36

BI

CRITICAL BOM OPTION

CRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

D

C

R5930

0.00

JTAG_AP_TCK

4

36

JTAG_AP_TMS

4

36

TRISTAR BASEBAND USB MUX

(NEEDED FOR MDM9600 BB)

=PP3V2_S2R_USBMUX

34

MLB_D&MLB_E

1

B

36

4

36

4

BI

25 36
25 36

A

C5960

0.1UF

10%

6.3V

2

X5R
201

USB11_AP_BBMUX_P
USB11_AP_BBMUX_N

USB_TS_BBMUX_P
USB_TS_BBMUX_N

TS_BBMUX_EN_L

MLB_D&MLB_E

1

R5960

10K

5%
1/20W
MF
201

2

BASEBAND USB MUX BYPASS

12

0%

1/32W

MF

01005

R5931

0.00

12

0%

1/32W

MF

01005

MLB_D&MLB_E

5

M+

4

M-

U5902

PI3USB102ZLE

7

D+

6

D-

8

MLB_B&MLB_C

R5965

12

5%

1/20W

MF

201

MLB_B&MLB_C

R5966

12

5%

1/20W

MF

201

VCC

TQFN

0

0

GND

9

3

1

Y+

2

Y-

10

SELOE*

DEFAULT =>

L81_MBUS_REF

18

OUT

MLB_D&MLB_E

1

R5961

10K

5%
1/20W
MF
201

2

USB_BBMUX_BB_P
USB_BBMUX_BB_N

PMU_GPIO_BBUSBTODOCK_EN_R

SEL

Y+D+Y­M+

0
1

M­D-

USB_BBMUX_BB_PUSB_TS_BBMUX_P

USB_BBMUX_BB_NUSB_TS_BBMUX_N

PLACE NEAR U5900

R5929

0.00

12

0%

1/32W

MF

01005

25 26 36

BIBI

25 26 36

BI

MLB_D&MLB_E

R5962

0.00

12

0%

1/32W

MF

01005

NOTE: ISOLATE SELECT SIGNAL FROM
PMU ON MLB_B AND MLB_C SO THE MUX
IS PERMANENTLY POINTED TO THE DOCK

25 26 36 25 36

25 26 36 25 36

PMU_GPIO_BBUSBTODOCK_EN

6 3

PPVCC_MAIN

1

R5991

100K

5%
1/32W
MF
01005

2

R5990

10K

12

5%

1/32W

MF

CRITICAL

K

D5990

SM-201

DSF01S30SC

A

TS_HOST_RESET

25

30

IN

IN

01005

PMU_E75_ACC_DET_R_L

R5934

0.00

12

0%

1/32W

MF

01005

AP_WDOG_RESET_IN

4

IN

TS_HOST_RESET_R

=PP1V8_S2R_USBMUX

25 34

1

C5991

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

1

2

R5932

220K

MF
1/32W
01005

R5933

220K

MF
1/32W
01005

C5936

0.1UF

10%

6.3V
X5R
201

12

5%

12

5%

15 29 30 34 39

FL5990

120-OHM-210MA

1 2

6

2

U5903

1

NC

3

5

PART NUMBER

01005

74LVC1G32

SOT891

4

PMU_RESET_IN_R

ALTERNATE FOR

PART NUMBER

SYNC_MASTER=N/A

PAGE TITLE

1

C5990

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

BOM OPTION

?

2

1

R5935

22

12

5%

1/32W

MF

01005

REF DES

FL5990155S0773 155S0453

CONN_E75_ACC_DET_L

CRITICAL

DZ5990

ESD0P2RF-02LS

TSSLP-2-1

PMU_RESET_IN

TRISTAR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

COMMENTS:

RDAR://PROBLEM/10882925

OUT

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

59 OF 154

SHEET

25 OF 39

TABLE_ALT_HEAD

TABLE_ALT_ITEM

IN

30

A.0.0

24

B

A

SIZE

D

124578

8 7 6 5 4 3

WWW.AliSaler.Com

12

D

D

CELLULAR/GPS HOTBAR PADS

OMIT

998-3732

J6000

HOT-BAR-PADS

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

40
41
42

HB-SM

1
2
3
4
5
6
7
8
9

HSIC3_BB_STB

4

26 36

HSIC3_BB_DATA

4

26 36

BB_JTAG_TMS_RF

5

IN

=BATT_POS_F_3G

34

C

WLAN_TX_BLANK

27

IN

RST_AP_L

4

25 30 39

OUT

GPIO_BB_RADIO_ON_L

5

IN

PMU_GPIO_BB_PMU_RST_L

30

IN

GPIO_BB_GSM_TXBURST

5

OUT

GPIO_BB_RST_L

5

39

IN

GPIO_BB_RESET_DET_L

5

OUT

GPIO_BB_HSIC_HOST_RDY

36

5

IN

GPIO_BB_HSIC_RESUME

5

36

OUT

BB_JTAG_TDO_RF

5

OUT

BB_JTAG_TDI_RF

5

IN

BB_JTAG_TRST_RF_L

5

IN

GPIO_BB_GPS_SYNC

5

OUT

PMU_GPIO_BB_HOST_WAKE

30

OUT

BB_VBUS_DET

30

IN

USB_BBMUX_BB_P

25 36

BI

USB_BBMUX_BB_N

25 36

BI

UART1_BB_RXD

5

25 36

OUT

UART1_BB_TXD

25 36

5

IN

UART1_BB_CTS_L

5

36

OUT

UART1_BB_RTS_L

5

36

B

IN

GPIO_AP_MODEM_WAKE

5

BI

GPIO_BB_HSIC_DEV_RDY

5

36

OUT

HSIC3_BB_STB

26 36

4

BI

HSIC3_BB_DATA

4

26 36

BI

BB_JTAG_TCK_RF

5

IN

DEBUG

NOSTUFF

J6050

MM4829-2702

F-ST-SM

1

234

NOSTUFF

J6051

MM4829-2702

F-ST-SM

1

234

C

B

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

CONNECTOR: CELLULAR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

60 OF 154

SHEET

26 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WLAN/BT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN

12

TABLE_5_HEAD

TABLE_5_ITEM

1

C6101_RF

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

R6107_RF

10K

5%
1/32W
MF
01005

2

GPIO_6

NC

1

C6102_RF

2

32

CLK32K_AP

6

GPIO_6

29

VIN_1P2LDO

31

WL_REG_ON

30

BT_REG_ON

14

JTAG_SEL

28

SR_VLX

24

WLAN_HSIC_DATA

25

WLAN_HSIC_STROBE

40

RF_SW_CTRL_3

17

18

27PF

5%
16V
NP0-C0G
01005

192021

BATT_VCC_WLAN

39

15

VDDIO_1P8V

GND

221162326

ANTENNA CONNECTOR

CRITICAL

J6190_RF

MM4829-2702

PP_WLAN_VDDIO_1V8

39

VOLTAGE=1.8V

27

46

47

BATT_VCC

VBATT_RF_VCC

VBATT_RF_VCC

U6101_RF

LBEE5ZHTWC501

LGA

OMIT_TABLE

334143444548495051

F-ST-SM

234

RF_ANT

1

WIFI_50S
50_OHM

1

C6103_RF

0.01UF

10%

6.3V

2

X5R
01005

HOST_WAKE_BT

BT_WAKE

BT_UART_RXD
BT_UART_TXD

BT_UART_RTS*
BT_UART_CTS*

BT_PCM_CLK

BT_PCM_SYNC

BT_PCM_OUT

BT_PCM_IN

GPIO_12

THRML_PAD

53545556575859

2G_ANT
5G_ANT

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5

42
52

34
39

38
37
35
36

3
5
2
4

9
8
10
12
7
11
13

60

CRITICAL

C6193_RF

3.9PF

12

+/-0.1PF

50V

NP0-CERM

0402

1

NOSTUFF

L6190_RF

5.6NH+/-0.3NH

0402

2

1

C6104_RF

27PF

5%
16V

2

NP0-C0G
01005

HOST_WAKE_WLAN
AP_HSIC3_RDY
WLAN_HSIC3_RESUME

14

AGG_CHANNEL
WLAN_UART_RXD
WLAN_UART_TXD
HSIC_DEVICE_RDY

WIFI_50S
50_OHM

R6108_RF

0.00

12

0%

1/32W

MF

01005

50_WLAN_G

38

50_WLAN_A

38

HOST_WAKE_BT
BT_WAKE

BT_UART_RXD
BT_UART_TXD
BT_UART_RTS_L
BT_UART_CTS_L

BT_PCM_CLK
BT_PCM_SYNC
BT_PCM_OUT
BT_PCM_IN

RF_ANT_MATCH1

PP_WL_BT_VDDIO_AP

34

=BATT_VCC

CRITICAL BOM OPTION

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

XW6102_RF

SHORT-0402

12

NOSTUFF

1

R6105_RF

10K

5%
1/32W
MF
01005

2

PART#

339S0171

D

PART NUMBER

311S0548 311S0398

C

DESCRIPTION

QTY

1

WIFI MODULE - MURATA

ALTERNATE FOR
PART NUMBER

339S0171339S0175

BOM OPTION

32K INTERFACE TO AP

14

CLK32K_AP

SHORT-01005

XW6101_RF

12

REFERENCE DESIGNATOR(S)

U6101_RF

REF DES

COMMENTS:

WIFI MODULE - USI

U6101_RF

U6102_RF

WLAN_CLK32K

WLAN_BUCK_OUT

WLAN_REG_ON

14 27

CRITICAL

L6111_RF

2.5UH-30%-0.7A-0.24OHM

1 2

0603

1

C6109

4.7UF

20%

6.3V

2

X5R-CERM1
402

IN

14

IN

14 27
14 27

BT_REG_ON

WLAN_SR_VLX1

50_HSIC_WLAN_DATA
50_HSIC_WLAN_STROBE

JTAG_SEL

1

R6109_RF

10K

5%
1/32W
MF
01005

2

NO LONGER NEEDED BASED
ON AND GATE REMOVAL

B

GPIO6 SDIO_DATA<1> SDIO_DATA<2> MODE DEFAULT ARM STATE
0 X X SDIO IN RESET
1 X 0 GSPI IN RESET
1 0 1 HSIC OUT OF RESET
1 1 1 BOOTLESS HSIC IN RESET

PP_WL_BT_VDDIO_AP

14 27

IN

1

R6113_RF

10K

5%
1/32W
MF
01005

HSIC_DEVICE_RDY

27

A

WLAN_REG_ON

14 27

IN

R6112_RF

1.00M

12

1%

1/32W

MF

01005

1

C6110_RF

0.22UF

20%

6.3V

2

X5R
0201

2

WLAN_REG_ON_RC

U6102_RF

74AUP1G08GF

SOT891

VCC

2
1
5

NC

4

DEV_HSIC3_RDY

YA
B
NC

GND

3 6

14 27

AGG_CHANNEL

27

R6114_RF

0.00

12

0%

1/32W

MF

01005

WLAN_TX_BLANK

26

OUT

6 3

CONDUCTED TEST PORT

CRITICAL

J6191_RF

MM8030-2600RK0

CRITICAL

1

C6191_RF

0.2PF

+/-0.05PF
50V

2

NP0-CERM
0402

VOLTAGE=1.8V

1

PP6101_RF

PP

SM

P4MM

27

14 27

IN

14 27

OUT

27

OUT

WLAN_REG_ON

14 27

HOST_WAKE_WLAN

14 27

AP_HSIC3_RDY

14 27

DEV_HSIC3_RDY

14 27

WLAN_UART_RXD

14 27

WLAN_UART_TXD

14 27

AGG_CHANNEL

27

50_HSIC_WLAN_DATA

14 27

50_HSIC_WLAN_STROBE

14 27

HSIC_DEVICE_RDY

27

1

R6111_RF

10K

5%
1/32W
MF
01005

2

OUT

14 27

14

OUT

14

IN

14

IN

14

OUT

14

OUT

14

IN

14

BI

14

BI

14

OUT

14

IN

14 27

OUT

14 27

IN

PULL DOWN RESISTORS

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

F-ST-SM

GND

4

PP6102_RF

P4MM

PP6103_RF

P4MM

PP6104_RF

P4MM

PP6105_RF

P4MM

PP6106_RF

P4MM

PP6107_RF

P4MM

PP6109_RF

P4MM

PP6110_RF

P4MM

PP6111_RF

P4MM

PP6112_RF

P4MM

CRITICAL

CRITICAL

C6192_RF

8.2PF

12

RF_CAL

WIFI_50S

IN

50_OHM

3

1

2

NOSTUFF

1

C6111_RF

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

12

+/-0.25PF%

25V

NP0-C0G

NOSTUFF

L6191_RF

0201

5.6NH-3%-0.35A

0201

CRITICAL

C6108_RF

4.7PF

12

+/-0.1PF

25V

COG-CERM

0201

RF_CAL_MATCH

WIFI_50S
50_OHM

1

NOSTUFF

L6192_RF

5.6NH-3%-0.35A

0201

2

CRITICAL

C6107_RF

8.2PF

12

+/-0.25PF%

25V

NP0-C0G

0201

38

50_WLAN_A_DIPLX

U6104_RF

DPX205850DT-9038A1SJ

5

COM

50_WLAN_G_1

38

CHANGE LIST

07FEB2012 MUSHTAQ COPIED FROM N41, ADDED J2 ANT MATCH/CONN
C6107 FROM 20PF TO 8.2PF, C6108 FROM 10PF TO 4.7PF
U6104 FROM SOSHIN TO MURATA LFD212G45DS5D355

13FEB2012 AMANDA CHANGED OMIT TO OMIT_TABLE AND UPDATED

SM

BOM OPTION TABLES TO ALTERNATE TABLES
REMOVED BOM TABLE FOR C6111_RF (NOW ALWAYS NOSTUFF)

SM

SM

SM

SM

SM

SM

SM

SM

SM

SYNC_MASTER=N/A

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SM

1

HI

3

LO

GND

246

WIFI/BT

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

61 OF 154

SHEET

27 OF 39

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

D

PART NUMBER

155S0644 155S0274

ALTERNATE FOR
PART NUMBER

BOM OPTION

?

FL7500,L3620,L5550,L5730

REF DES

COMMENTS:

RDAR://PROBLEM/11282371

TABLE_ALT_HEAD

TABLE_ALT_ITEM

C

34

30

5

BI

30

BI

=BATT_POS_CONN

UART5_BATTERY_TRXD

BATTERY_NTC

NET_SPACING_TYPE=ANLG

NOTE: REMOVED R7541

HAS TP7502

FL7500

240-OHM-0.2A-0.8-OHM

1 2

0201

TP7500

A

TP-P55

NOSTUFF

1

2

1

C7522

33PF

5%
25V
NPO-C0G
0201

1

C7523

33PF

5%
25V

2

NPO-C0G
0201

1

C7524

1000PF

10%
16V

2

X7R-CERM
0201

1

C7525

82PF

5%
25V

2

NP0-C0G-CERM
0201

1

C7526

33PF

5%
50V

2

C0G-CERM
0402

1

C7527

4.7PF

+/-0.1PF
50V

2

C0G-CERM
0402

BATT_SWI_CONN

CRITICAL

J7500

BATT-J2

F-RT-SMTH

7
6

1

HDQ

2

THERM

3

PACK_NEG

4

PACK_POS

5

SENSE

8

D

C

BATT_SNS

29

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

B

A

APN:516S0926

TP7501

1

A

TP-P55

NOSTUFF

TP7502

1

A

TP-P55

NOSTUFF

TP7503

1

A

TP-P55

NOSTUFF

6 3

SYNC_MASTER=MADHAVI

PAGE TITLE

POWER: BATTERY CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/06/2011

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

75 OF 154

SHEET

28 OF 39

124578

A.0.0

SIZE

B

A

D

8 7 6 5 4 3

VCC_MAIN BYPASS

TOTAL CAPS = ~400UF

PLACE ONE 10UF CAP
AT EACH VDD INPUT

PART#

152S1637

152S1638

PART NUMBER

D

138S0676 138S0654

25 29

DESCRIPTION

QTY

6

IND,1.0UH,20%,59MO,2.74A

1

IND,1.0UH,20%,64MO,2.3A

ALTERNATE FOR
PART NUMBER

152S1292152S1452

C8100,C8101,C8102,C8103,C8104,C8105,C8107,C8108,C8109,C8110,C8111,C8112,C8113,C8114,C8117,C8118,C8119,C8120,C8121,C8222,C8123,C8195

OVP_SW_EN_L

MOSFET
CHANNEL
RDS(ON)
IMAX
VGS MAX

BOM OPTION

?

NOSTUFF

R8170

4.7K

12

5%

1/20W

MF

201

FDMC6676BZ
P-TYPE
27 MOHM @-4.5V

6.9 A
+/- 25V

C

NOSTUFF

1

R8116

470K

1%

1/20W

MF

201

2

USB REVERSE VOLTAGE PROTECTION

PP3V0_GRAPE

29 34 39

PP1V7_VA_VCP

19 29 34 39

PP3V2_S2R_USBMUX

29 34 39

PP3V0_S2R_HALL

29 34 39

PP1V0

29 34 39

PP3V3_ACC

29 34 39

LDO5

29 39

LDO10

B

18 29 39

PP3V0_SENSOR

29 34 39

PP3V0_IO

29 34 39

PP3V0_S2R_TRISTAR

29 34

PP2V8_CAM

29 34 39

PP1V1_SRAM

29 34 39

PP1V8_ALWAYS

29 34 39

C8169

0.22UF

6.3V
0201

NOTE: FOR NO BATTERY SITUATION

29 32 34 39

FDMC6676BZ

MLP3.3X3.3

PPVBUS_USB_DCIN

34

CRITICAL

C8133

4.7UF

20%

6.3V

X5R-CERM1

402

CRITICAL

1

C8168

4.7UF

20%

2

X5R

X5R-CERM1

PPBATT_VCC

CRITICAL

Q8123

1

2

20%

6.3V
402

A

1

R8100

0.5

1%

1/16W

MF

402

2

REF DES

L8111

S

D

5

LDO BYPASS

CRITICAL

1

C8132

4.7UF

20%

6.3V

2

X5R-CERM1

402

CRITICAL

1

C8167

4.7UF

20%

6.3V

2

X5R-CERM1

402

NOSTUFF
CRITICAL

1

C8174

10UF

20%

6.3V

2

CERM-X5R
0402-1

39

PLACEMENT_NOTE=PLACE NEAR L8225.1

CRITICAL

C8166

150UF

20%

6.3V

TANT-1

B15G

ESR MAX=70MOHM

REFERENCE DESIGNATOR(S)

L8100,L8101,L8102,L8103,L8109,L8110

L8104

COMMENTS:

RDAR://PROBLEM/8376462

??

123

G

4

R8130

220K

1%

1/20W

MF

201

CRITICAL

1

C8149

2.2UF

10%

6.3V

2

X5R
402

CRITICAL

1

C8153

2.2UF

10%

6.3V

2

X5R
402

NOSTUFF
CRITICAL

1

C8173

10UF

20%

6.3V

2

CERM-X5R
0402-1

BATT_POS_RC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.6V

CRITICAL

1

2

ESR MAX=70MOHM

PPVCC_MAIN

15 25 29 30 34 39

PPBATT_VCC

29 32 34 39

CRITICAL

DZ8120

BZT52C10LP

LLP

AK

NOTE: 10V ZENER

VBUS_PROT_G

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=ANLG

1

2

CRITICAL

C8148

4.7UF

20%

6.3V

X5R-CERM1

402

CRITICAL

1

C8152

4.7UF

2

X5R-CERM1

CRITICAL

1

C8170

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C8165

150UF

20%

6.3V

2

TANT-1

B15G

CRITICAL BOM OPTION

CRITICAL

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

G

4

RDSON=0.0136@VGS=-2.5V

ID=12.0A

25

PPVBUS_PROT

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6.0V

CRITICAL

C8146

1UF

6.3V

1

2

CRITICAL

1

C8171

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

10%

2

X5R
402

CRITICAL

C8151

2.2UF

6.3V

1

2

6.3V

20%
402

CRITICAL

1

C8154

10UF

20%

6.3V

2

X5R
603

123

S

CRITICAL

Q8104

FDMC6683

MLP3.3X3.3

D

5

ACT_DIO

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=ANLG

CRITICAL

1

C8124

2.2UF

10%
25V

2

X5R-CERM

805

LAYOUT NOTE: PLACE
RIGHT AT THE PIN

OVP_SW_EN_L

25 29

LAYOUT NOTE:
R8196, C8196 CAN BE

ANYWHERE BET.TRISTAR
AND PMU

CRITICAL

1

C8145

2.2UF

10%

6.3V

2

X5R
402

1

10%

2

X5R
402

PP1V2_S2R

29 34 39

CRITICAL

1

C8155

10UF

20%

6.3V

2

X5R
603

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

2.2UH-20%-4A-32MOHM

CRITICAL

C8144

10UF

6.3V

CERM-X5R

0402

1

2

CRITICAL

1

C8156

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

L8112

1 2

PIME101E-SM

DCR=32MOHM MAX

BATT_SNS

28

LAYOUT NOTE ­R3172- PLACE NEAR BMU
C3172- PLACE NEAR PMU
R3173- PLACE NEAR PMU

PPVBUS_USB

4

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V

R8196

4.7K

12

1%

1/20W

MF

201

CRITICAL

1

C8147

2.2UF

20%

C8134

1UF

10%

6.3V
CERM
402

2

PP1V8_S2R

29 34 39

1

C8135

1UF

10%

6.3V

2

CERM
402

6.3V

1

2

10%
X5R

402

C8136

CRITICAL

1

C8157

10UF

20%

6.3V

2

CERM-X5R
0402

R8172

0

12

5%

1/20W

MF

201

NOSTUFF
XW8114

SHORT-0201

OVP_SW_EN_L_R

NOSTUFF

1

C8196

0.022UF

10%
25V

2

X7R
0402

1

2

1 CAP PER PIN N5 N14

1UF

10%

6.3V
CERM
402

CRITICAL

1

C8142

18PF

5%

25V

2

NP0-C0G

201

CRITICAL

1

C8162

10UF

20%

6.3V

2

CERM-X5R
0402

PPVCC_MAIN_CPU0

CRITICAL

1

C8159

10UF

20%

6.3V

2

CERM-X5R
0402

SW_CHGA

CRITICAL

D8100

SOD-123W

PMEG4030ER

BATT_SNS_R

NOSTUFF

1

C8172

0.022UF

10%
25V

2

X7R
0402

12

CRITICAL

1

C8125

4.7UF

10%
35V

2

X5R-CERM
0603

LAYOUT NOTE: PLACE
RIGHT AT THE PIN

32.768K-20PPM-12.5PF

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

K

NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

A

PMU_VCENTER

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V

1

C8126

2

PPVCC_MAIN_CPU0

29 34

PPVCC_MAIN_CPU1

29 34

PPVCC_MAIN

15 25 29 30 34 39

PPVCC_MAIN_SOC

29 34 29 34 39

PPVCC_MAIN

15 25 29 30 34 39

PPVCC_MAIN

15 25 29 30 34 39

NET_SPACING_TYPE=CRYSTAL

CRITICAL

Y8138

12

2012-1

CRITICAL

1

C8187

10UF

20%

6.3V

2

CERM-X5R
0402

1

2

CRITICAL

4.7UF

10%
35V
X5R-CERM
0603

CRITICAL

C8190

10UF

20%

6.3V
CERM-X5R
0402

1

R8173

499

1%
1/20W
MF
201

2

PMU_XTAL

36

PMU_EXTAL

36

NET_SPACING_TYPE=CRYSTAL

CRITICAL

1

C8143

18PF

5%
25V

2

NP0-C0G
201

CRITICAL

1

C8188

10UF

20%

6.3V

2

CERM-X5R
0402

29 34

1

2

PPVCC_MAIN_CPU1

CRITICAL

1

C8158

10UF

20%

6.3V

2

CERM-X5R
0402

F22
F23
G22
G23

CHG_LX

H22
H23
J22
J23
M14

VBAT

M17

IBAT_S

P15
P16

IBAT

P17
P18
M18

ACT_DIO

E22
E23

VCENTER

K22
K23

E20
E21
F19
F20
F21
G19
G20
G21

VBUS

H19
H20
H21
J19
J20
J21
K20
K21
E19
K19
L23

VBUS_OVP_OFF

A10

VDD_BUCK0A

B10

A6

VDD_BUCK0B

B6
D1

VDD_BUCK0C

D2

A14

VDD_BUCK2_01

B14
A18

VDD_BUCK2_23

B18

H1

VDD_BUCK3

H2
A2

VDD_BUCK4

B2

A22

VDD_BUCK5

B22
L20

VCC_MAIN_S

N15
N16

VCC_MAIN

N17
N18

N9

VDD_LDO1_6

N4

VDD_LDO2

N7

VDD_LDO3_5_8

N3

VDD_LDO4_7

N11

VDD_LDO9

N6

VDD_LDO10

N2

VDD_LDO11

N5

VDD_LDO12

N14

VDD_LDO16

N1

XTAL1

P1

XTAL2

PART NUMBER

197S0399

CRITICAL

C8193

10UF

20%

6.3V
CERM-X5R
0402

1

2

CRITICAL

1

C8194

10UF

20%

6.3V

2

X5R
603

CRITICAL

C8189

10UF

20%

6.3V
CERM-X5R
0402

OMIT_TABLE

U8100

D2018

FCBGA

SYM 2 OF 3

USB/BAT

VCC-MAIN

LDO INPUT

XTAL

ALTERNATE FOR
PART NUMBER

128S0279128S0339

197S0392

29 34

BUCK0A_LX0

BUCK0A_LX1

BUCK0A_FB

BUCK0B_LX0

BUCK0B_LX1

BUCK0B_FB

BUCK0C_LX0

BUCK0C_FB

BUCK2_LX0

BUCK2_LX1

BUCK

BUCK2_LX2

BUCK2_LX3

BUCK2_FB

BUCK3_LX0

BUCK3_FB

BUCK4_LX0

BUCK4_FB

BUCK5_LX0

BUCK5_BYP

BUCK5_FB

LDO

VLDO10
VLDO11
VLDO12
VLDO16
ON_BUF

VBUCK4
CPU1V2_SW
CPU1V2_SW

VBUCK3
CPU1V8_SW
CPU1V8_SW

WDIG_SW

SWITCH POWER

CRITICAL

1

C8130

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8160

10UF

20%

6.3V

2

CERM-X5R
0402

VLDO1
VLDO2
VLDO3
VLDO4
VLDO5
VLDO6
VLDO7
VLDO8
VLDO9

VPUMP

BOM OPTION

?

?

CRITICAL

1

C8131

1UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8161

10UF

20%

6.3V

2

CERM-X5R
0402

A9
B9
A11
B11
E11

A5
B5
A7
B7
E6

E1
E2
F5

A13
B13
A15
B15
A17
B17
A19

NC

B19

NC

E15

G1
G2
H5

A3
B3
D4

A21
B21
A23
B23
E18

(150MA; 1.2-3.1V)

P9

(100MA; 1.65-1.805V; BUCK3)

P4

(50MA; 2.5-3.3V)

N8

(100MA; 1.8-3.3V)

P2

(300MA; 1.7-3.0V)

P8

(150MA; 2.5-3.6V)

P10

(50MA; 1.2-3.1V)

P3

(15MA; 2.0-3.55V)

M6

(300MA; 1.2-3.0V)

P11

(200MA; 2.5-3.55V)

P6

(250MA; 1.7-3.0V)

M1

(150MA; 0.6-1.3V)

P5

(650MA; 1.1V)

P14

(5MA; 1.8V)

M16

M2

(RON=0.05 OHM MAX)

L1
L2

K2

(RON=0.05 OHM MAX)

J1

J2

(RON=0.2 OHM MAX)

K1

PMU_VPUMP

K3

REF DES

C8165,C8166

Y8138

PPVCC_MAIN

1

C8163

82PF

5%
25V

2

NP0-C0G-CERM
0201

PPVCC_MAIN_SOC

CRITICAL

1

C8191

10UF

20%

6.3V

2

0402

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.6V

C8137

1

0.01UF

10%
10V

2

X5R-CERM
0201

COMMENTS:

RDAR://PROBLEM/8967213

RDAR://PROBLEM/9936684

PP3V0_GRAPE
PP1V7_VA_VCP
PP3V2_S2R_USBMUX
PP3V0_SENSOR

LDO5

PP3V3_ACC
PP3V0_S2R_TRISTAR
PP3V0_S2R_HALL
PP3V0_IO

LDO10

PP2V8_CAM
PP1V0
PP1V1_SRAM
PP1V8_ALWAYS

1

C8164

8.2PF

+/-0.1PF%
25V

2

CER
0201

1

2

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL

C8192

10UF

20%

6.3V
CERM-X5RCERM-X5R
0402

15 25 29 30 34 39

29 34

39

BUCK2_LX0

39

BUCK2_LX1

39

BUCK2_LX2

BUCK2_FB

39

39

BUCK3_LX0

BUCK3_FB

39

BUCK4_LX0

39

39

BUCK4_FB

39

BUCK5_LX0

(PP3V3_OUT)

BUCK5_FB

39

29 34 39
19 29 34 39

1

2

6 3

29 34 39

29 39
29 34 39
29 34
29 34 39
29 34 39
18 29 39
29 34 39
29 34 39
29 34 39
29 34 39

C8138

1UF

20%

6.3V
X5R
0201

BUCK0A_LX0

39

39

BUCK0A_LX1

BUCK0A_FB

39

39

BUCK0B_LX0

39

BUCK0B_LX1

39

BUCK0B_FB

39

BUCK0C_LX0

39

BUCK0C_FB

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

1

C8140

1UF

10%

6.3V

2

CERM
402

1.0UH-20%-2.74A-59MOHM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

1.0UH-20%-2.74A-59MOHM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

1.0UH-20%-2.74A-59MOHM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

1.0UH-20%-2.74A-59MOHM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

1.0UH-20%-2.3A-64MOHM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

1.0UH-20%-3.9A-0.035OHM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

1 2

1.0UH-20%-3.9A-0.035OHM

1.0UH-20%-3.9A-0.035OHM

1.0UH-20%-2.74A-59MOHM

1.0UH-20%-2.74A-59MOHM

2.2UH-20%-3.3A-0.064OHM

PP1V2_S2R
PP1V2

PP1V8_S2R
PP1V8
TP_PP1V8_GRAPE

1

C8139

1UF

10%

6.3V

2

CERM
402

1

C8141

1UF

10%

6.3V

2

CERM
402

CRITICAL

OMIT_TABLE

L8100

1 2

PSB32251E-SM

CRITICAL

OMIT_TABLE

L8101

1 2

PSB32251E-SM

NOSTUFF

XW8100

12

SM

CRITICAL

OMIT_TABLE

L8102

1 2

PSB32251E-SM

CRITICAL

OMIT_TABLE

L8103

1 2

PSB32251E-SM

NOSTUFF

XW8101

12

SM

CRITICAL

OMIT_TABLE

L8104

1 2

PSB25201E-SM

NOSTUFF

XW8102

12

SM

CRITICAL

L8105

PILE32251E-SM

CRITICAL

L8106

1 2

PILE32251E-SM

CRITICAL

L8107

1 2

PILE32251E-SM

NOSTUFF

XW8103

12

SM

CRITICAL

L8109

1 2

PSB32251E-SM

NOSTUFF

XW8104

12

SM

CRITICAL

L8110

1 2

PSB32251E-SM

NOSTUFF

XW8105

12

SM

CRITICAL

L8111

1 2

PIME051E-SM

NOSTUFF

XW8106

12

SM

SYNC_MASTER=MADHAVI

PAGE TITLE

OMIT_TABLE

OMIT_TABLE

29 34 39

34 39

29 34 39

32 34 39

1

2

PMU: ADRIANA PAGE 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

1

C8100

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8180

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8102

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8182

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

C8104

22UF

20%

6.3V
X5R-CERM-1
603

CRITICAL

1

C8107

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8117

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8109

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8111

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8113

22UF

20%

6.3V

2

X5R-CERM-1
603

1

2

1

2

1

2

1

2

CRITICAL

1

C8105

22UF

20%

6.3V

2

X5R-CERM-1
603

1

2

1

2

1

2

PP1V1_CPU0_FET

CRITICAL

C8101

22UF

20%

6.3V
X5R-CERM-1
603

CRITICAL

C8181

10UF

20%

6.3V
CERM-X5R
0402

NOSTUFF
CRITICAL

C8103

22UF

20%

6.3V
X5R-CERM-1
603

CRITICAL

C8183

10UF

20%

6.3V
CERM-X5R
0402

1

2

1

2

1

2

1

2

PP1V1_CPU1_FET

1

2

1

2

ADDITIONAL DISTRIBUTED
12UF (NO DERATING)

ADDITIONAL DISTRIBUTED
98UF (NO DERATING)

CRITICAL

C8108

22UF

20%

6.3V
X5R-CERM-1
603

CRITICAL

C8118

22UF

20%

6.3V
X5R-CERM-1
603

ADDITIONAL DISTRIBUTED
27UF (NO DERATING)

CRITICAL

C8110

22UF

20%

6.3V
X5R-CERM-1
603

ADDITIONAL DISTRIBUTED
64UF (NO DERATING)

CRITICAL

C8112

22UF

20%

6.3V
X5R-CERM-1
603

ADDITIONAL DISTRIBUTED
32UF (NO DERATING)

CRITICAL

C8114

22UF

20%

6.3V
X5R-CERM-1
603

SYNC_DATE=12/06/2011

12

NOSTUFF

CRITICAL

C8120

22UF

20%

6.3V
X5R-CERM-1
603

NOSTUFF

CRITICAL

C8184

10UF

20%

6.3V
CERM-X5R
0402

CRITICAL

C8122

22UF

20%

6.3V
X5R-CERM-1
603

NOSTUFF
CRITICAL

C8185

10UF

20%

6.3V
CERM-X5R
0402

PP1V1_CPUB

PP1V2_SOC

CRITICAL

1

C8195

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8119

22UF

20%

6.3V

2

X5R-CERM-1
603

PP1V8_S2R

PP1V2_S2R

PP3V3_OUT

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

81 OF 154

SHEET

29 OF 39

124578

CRITICAL

1

C8121

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C8123

22UF

20%

6.3V

2

X5R-CERM-1
603

34 39

34 39

29 34 39

34 39

30 39

30 39

29 34 39

SIZE

D

C

B

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

C8281

100PF

6.3V
CERM

01005

1

CRITICAL

R8281

10KOHM-1%-0.31MA

1

5%

2

0201

2

C8282

100PF

5%

6.3V
CERM

01005

1

CRITICAL

R8282

10KOHM-1%-0.31MA

1

2

0201

2

LOCATION DESCRIPTIONS ARE FROM J2

SENSOR LOCATIONS TBD

D

XW8282

37

BOARD_TEMP6_N

XW8281

37

BOARD_TEMP5_N

PLACE XW AND CAP
CLOSE TO PMU

1

C8215

100PF

5%

6.3V

2

CERM

01005

C

37

BOARD_TEMP7_N

PLACE XW AND CAP

CLOSE TO PMU

30 34

30 34 39

12

SM

NOSTUFF

1

CRITICAL

R8218

10KOHM-1%-0.31MA

0201

2

C8221

100PF

5%

6.3V
CERM

01005

XW8200

12

SM

NOSTUFF

=PPVCC_MAIN_LED

CRITICAL

C8226

10UF

20%
10V
X5R

0603-1

PPLED_OUT_A

CRITICAL

1

C8232

4.7UF

10%
35V

2

X5R-CERM
0603

1

2

37

BOARD_TEMP8_N

PLACE XW AND CAP
CLOSE TO PMU

4.7UH-3.2A

1 2

DCR=106MOHM MAX

1

2

CRITICAL

1

C8233

4.7UF

10%
35V

2

X5R-CERM
0603

1

2

CRITICAL

L8225

PIME051E-SM

12

NOSTUFF

PLACE XW AND CAP
CLOSE TO PMU

CRITICAL

R8222

10KOHM-1%-0.31MA

0201

1

C8217

100PF

5%

6.3V
2

CERM

01005

37

XW8201

12

SM

NOSTUFF

CRITICAL CRITICAL

1

C8234

4.7UF

10%
35V

2

X5R-CERM
0603

B

CRITICAL

1

C8264

4.7UF

10%
35V

2

X5R-CERM
0603

CRITICAL

D8258

PMEG4010BEA

AK
SOD-323

=PPVCC_MAIN_LED

30 34

CRITICAL

C8256

PPLED_OUT_B

30 34 39

10UF

20%
10V
X5R

0603-1

CRITICAL

1

C8262

4.7UF

10%
35V

2

X5R-CERM
0603

4.7UH-3.2A

1

2

1

2

CRITICAL

L8255

1 2

PIME051E-SM

DCR=106MOHM MAX

CRITICAL

C8263

4.7UF

10%
35V
X5R-CERM
0603

A

PART NUMBER

ALTERNATE FOR
PART NUMBER

107S0208107S0150

BOM OPTION

?

R8216,R8218,R8222,R8280,R8281,R8282

REF DES

COMMENTS:

RDAR://PROBLEM/8380367

(TEMP5 - TOP SIDE NEAR NAND)
(TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX)

SM

PMU_USB_BRICKID

10

IN

1

CRITICAL

R8216

10KOHM-1%-0.31MA

0201

2

BOARD_TEMP3_N

PLACE XW AND CAP
CLOSE TO PMU

CRITICAL

D8228

PMEG4010BEA

AK

SOD-323

1

C8235

4.7UF

10%
35V

2

X5R-CERM
0603

CRITICAL

1

C8265

4.7UF

10%
35V

2

X5R-CERM
0603

C8223

100PF

5%

6.3V
CERM

01005

37

XW8202

12

SM

NOSTUFF

TABLE_ALT_HEAD

TABLE_ALT_ITEM

1

2

BOARD_TEMP4_N

WLED_LX_A

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

WLED_LX_B

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

1

C8292

0.01UF

10%

6.3V

2

X5R
01005

5

23

IN

20

5

IN

5

20

IN

25

IN

(TEMP1 - BOTTOM SIDE NEAR H5G)
(TEMP2 - BOTTOM SIDE NEAR PMU)
(TEMP3 - BOTTOM SIDE NEAR I/O FLEX CONN)
(TEMP4 - BOTTOM SIDE NEAR WIFI)

0201

1 2

10KOHM-1%-0.31MA

PLACE XW AND CAP
CLOSE TO PMU

XW8203

12

NOSTUFF

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

OUT

15 37

15 37

15 37

15 37

15 37

15 37

CRITICAL

R8280

SM

LED_IO_1_A

LED_IO_2_A

LED_IO_3_A

LED_IO_4_A

LED_IO_5_A

LED_IO_6_A

LED_IO_1_B

OUT

LED_IO_2_B

OUT

LED_IO_3_B

OUT

LED_IO_4_B

OUT

LED_IO_5_B

OUT

LED_IO_6_B

OUT

R8231

12

R8235

12

R8240

12

BOARD_TEMP5_P
BOARD_TEMP6_P

1

C8206

0.01UF

10%

6.3V

2

X5R
01005

GPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
GPIO_BTN_SRL_L
PMU_E75_ACC_DET_L

R8299

6.34K

12

1%

1/20W

MF

201

RESISTOR FOR TEMP CALIBRATION

1

C8220

100PF

5%

6.3V
2

CERM

01005

DWI NAMING RELATIVE TO AP

R8227

1.00

12

1%

1/20W

MF

201

1.00

1%

1/20W

R8232

MF

201

1.00

12

1%

1/20W

MF

201

1.00

1%

1/20W

R8239

MF

201

1.00

12

1%

1/20W

MF

201

1.00

1%

1/20W

MF

201

CRITICAL

2

R8219

3.92K

0.1%
402
1/16W
MF

1

30 37
30 37

1

C8207

0.01UF

10%

6.3V

2

X5R
01005

(PPLED_OUT_A)

28

IN

5

IN

32

IN

25

IN

25 26 39

4

OUT

5

OUT

5

19 25 36

IN

5

19 25 36

BI

36

5

IN

5

36

IN

5

36

OUT

BOARD_TEMP1

32 37

BOARD_TEMP2

32 37

37

BOARD_TEMP3_P

37

BOARD_TEMP4_P
BOARD_TEMP5_P

30 37

BOARD_TEMP6_P

30 37

37

BOARD_TEMP7_P

37

BOARD_TEMP8_P
BATTERY_NTC
PMU_TCAL

GPIO_PMU_KEEPACT
PMU_SHDWN

NET_SPACING_TYPE=ANLG

PMU_RESET_IN
RST_AP_L
GPIO_PMU_IRQ_L

I2C0_SCL_1V8
I2C0_SDA_1V8

DWI_AP_CLK
DWI_AP_DO
DWI_AP_DI

NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

(INTERNAL PULL-DOWN)

NC_FW_ZENER_PWR

PMU_ACC_ID
PMU_USB_BRICKID_R
ADC_IN7

NET_SPACING_TYPE=ANLG

(INTERNAL PULL-DOWN)

(INTERNAL PULL-DOWN)

(PULLUP INSIDE H5G)

(INTERNAL PULL-DOWN)
(INTERNAL PULL-DOWN)

37

LED_IO1_A_R

37

LED_IO2_A_R

37

LED_IO3_A_R

37

LED_IO4_A_R

37

LED_IO5_A_R

37

LED_IO6_A_R

37

LED_IO1_B_R

37

LED_IO2_B_R

37

LED_IO3_B_R
LED_IO4_B_R

37
37

LED_IO5_B_R

37

LED_IO6_B_R

I2C ADDRESS: 0111100X (0X78)

NO_TEST=TRUE

M19

M21

L19
K15
K14
M13

L21
M22

E10

N21
P21
K16

N23
P23
K17
K10
M11
K11
K12
M12
K13

C3
D3
E3
C1

M8

L4
L5

M5
M4
L3
M3

H3

G4
F4
H4

E7
E9

A1
B1
C2

K5
K6
K7
K8
M9
K9

FW_DPHP_DET
BUTTON1
BUTTON2
BUTTON3
ACC_DET

ACC_ID
BRICK_ID
ADC_IN7
ADC_IN31

TDEV1
TDEV2
TDEV3
TDEV4
TDEV5
TDEV6
TDEV7
TDEV8
TBAT
TCAL

KEEPACT
SHDN

RESET_IN
RESET*
IRQ*

SCL
SDA

DWI_CK
DWI_DI
DWI_DO

WLED_LXA

VOUT_WLED_A
WLED1_A
WLED2_A
WLED3_A
WLED4_A
WLED5_A
WLED6_A

WLED_LXB

VOUT_WLED_B
WLED1_B
WLED2_B
WLED3_B
WLED4_B
WLED5_B
WLED6_B

OMIT_TABLE

U8100

D2018

FCBGA

SYM 1 OF 3

INPUTINPUT

DIGITAL

REFERENCES

ANALOG

GPIO

TEMPERATURE

WDOG

RESET

ANALOG MUX

I2C & DWI

LCM/GRAPE

LED BACKLIGHT

IREF
VREF

VDD_REF

VDD_REF_A

VDD_RTC
ADC_REF

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17

AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_AY
AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_BY

VDD_LCM_SW

VDD_BOOST_LCM

BOOST_LCM_LX

VDD_LCM
LCM2_EN

LCM_FB

VLCM1

VLCM2

VLCM3

CPUA_EN
CPUA_SW_G
CPUA_SW_S

CPUB_EN
CPUB_SW_G
CPUB_SW_S

DPHP

39
39
39

M7
P7
K18
M15
N10
M10

D5
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20

C21
C22
E17
E14
C23
D21
D22
D19
E13
D23

N19
P19
P20
N13
F3
M20
P13
P12
N12

M23
J5
J4

L22
J3
K4

E4

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

TP_LCM2_EN

NC_VLCM1

NO_TEST=TRUE

NC_VLCM2

NO_TEST=TRUE

PMU_IREF

NET_SPACING_TYPE=ANLG

PMU_VREF

NET_SPACING_TYPE=ANLG

PMU_VDD_REF

NET_SPACING_TYPE=ANLG

PMU_VDD_RTC

NET_SPACING_TYPE=ANLG
NET_SPACING_TYPE=ANLG

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM

PMU_GPIO_CLK_32K_GRAPE
PMU_GPIO_CLK_32K_WLAN
PMU_GPIO_BT_REG_ON
PMU_GPIO_WLAN_REG_ON
PMU_GPIO_BB_PMU_RST_L
UART5_BATTERY_TRXD
PMU_GPIO_BT_HOST_WAKE
PMU_GPIO_WLAN_HOST_WAKE
PMU_GPIO_BB_HOST_WAKE
PMU_GPIO_CODEC_HS_INT_L
PMU_GPIO_BBUSBTODOCK_EN
PMU_GPIO_TS_INT
PMU_GPIO_HALL2_IRQ
PMU_GPIO_CODEC_RST_L
PMU_GPIO_HALL_IRQ
NC_PMU_GPIO16
PMU_GPIO_BB_VBUS_DET

PPVCC_MAIN
PP6V0_LCM_HI

LCM_LX

PP6V0_LCM_VBOOST

CPU0_SWITCH
CPU0_SW_G
CPU0_SW_S

CPU1_SWITCH
CPU1_SW_G
CPU1_SW_S

NC_PMU_DP_HPD

NO_TEST=TRUE

4

30

4

30

NO_TEST=TRUE

15 25 29 34 39

(PPLED_OUT_B)

R8257

1.00

12

1%

1/20W

R8261

12

R8265

12

R8270

12

1.00

1%

1/20W

MF

201

1.00

1%

1/20W

MF

201

1.00

1%

1/20W

MF

201

MF

201

R8262

1.00

12

1%

1/20W

MF

201

R8269

1.00

12

1%

1/20W

MF

201

C8201

0.01UF

C8251

0.01UF

PPLED_OUT_A

C8266

0.01UF

1

PLACEMENT_NOTE=PLACE NEAR U8100.K16

10%
50V

2

X7R
402

PPLED_OUT_B

C8267

0.01UF

1

PLACEMENT_NOTE=PLACE NEAR U8100.K17

10%
50V

2

X7R
402

30 34 39

1

PLACEMENT_NOTE=PLACE NEAR U8100.K16

10%
50V

2

X7R
402

30 34 39

1

PLACEMENT_NOTE=PLACE NEAR U8100.K17

10%
50V

2

X7R
402

6 3

1

1

C8204

0.1UF

10%

6.3V

2

X5R
201

R8203

200K

1%
1/20W
MF
201

2

PLACEMENT NOTE: PLACE NEAR PIN K4

1

C8212

0.1UF

10%

6.3V

2

X5R
201

OUT
OUT
OUT
OUT
OUT

OUT

OUT

30

1

C8209

1UF

10%

6.3V

2

CERM
402

USED BY Z2

17 36

(1.8_S2R PUSH-PULL)

14 36

(1.8_S2R;NO PD REQ’D PER BB TEAM)

14

(1.8_S2R;NO PD REQ’D PER BB TEAM)

14
26

(2.5V ALWAYS ON PU IN BMU)

5

28

IN

(INTERNAL PD)

14

IN

14

(INTERNAL PD)

IN

(INTERNAL PD; CAN’T BE USED FOR 32K CLK OUTPUT)

26

IN

(INTERNAL PU TO PP1V8_S2R)

18

IN

25

NEED RADAR TO STOP GENERATING 32K CLOCK

25

5

IN

23

IN

18
22

IN

(NOTE: 2MHZ)

2.2UH-1.05A-0.195OHM

MAKE_BASE=TRUE
VOLTAGE=6.0V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1 2

VLS201612E-SM

(INTERNAL PULLDOWN; TE ENABLE)

NOSTUFF

C8236

2.2UF

X5R-CERM

20%
10V

402

NOSTUFF

1

1

C8237

10UF

20%
25V

2

2

X5R-CERM
0603

NOSTUFF

1

R8290

1M

5%
1/20W
MF
201

2

NOSTUFF

1

R8291

1M

5%
1/20W
MF
201

2

NOSTUFF

CRITICAL

L8229

1

2

NOSTUFF

1

C8290

0.1UF

10%
16V

2

X5R-CERM
0201

NOSTUFF

1

C8291

0.1UF

10%
16V

2

X5R-CERM
0201

CPU1_SW_S

30

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM

1

C8210

0.22UF

20%

PLACEMENT NOTE: PLACE NEAR PIN K24

6.3V

2

X5R
0201

BB_VBUS_DET STUFFING OPTION
SELECTING GPIO OPTION BY DEFAULT
REMOVE STUFFING RES AND WIRE DIRECTLY FOR PRODUCTION

PMU_GPIO_BB_VBUS_DET

30

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

VLCM3

NOSTUFF

C8239

1UF

10%
10V
X5R
402

30

CPU0_SW_S

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM

30

NOSTUFF

1

C8238

1UF

10%
10V

2

X5R
402

R8292

0

12

R8293

12

CPU0_SW_G_R

5%

1/20W

MF

201

PP1V1_CPU0

34 39

0

CPU1_SW_G_R

5%

1/20W

MF

201

PP1V1_CPU1

34 39

XW8291

12

SM

NOSTUFF

SYNC_MASTER=MADHAVI

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PMU_ADC_REF

1

C8214

1000PF

10%

6.3V

2

X5R-CERM
01005

R8297

0.00

12

0%

1/32W

MF

VLCM3

30

NOSTUFF

CRITICAL

D8230

PMEG2005AEL

AK

SOD882

MAKE_BASE=TRUE
VOLTAGE=6.0V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

XW8290

12

SM

NOSTUFF

01005

NOSTUFF

R8296

0.00

12

0%

1/32W

MF

01005

Q8200

CSD58874W1015

BGA

D

A2

G

S

B2
C2

Q8201

CSD58874W1015

BGA

D

A2

G

S

B2
C2

BB_VBUS_DET

Q8202

CSD58874W1015

BGA

D

A2

G

S

B2
C2

A1
B1
C1

A1
B1
C1

Q8203

CSD58874W1015

A2

G

B2
C2

PP1V1_CPU1_FET

BGA

D

S

SYNC_DATE=12/06/2011

PMU: ADRIANA PAGE 2

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

OUT

A1
B1
C1

PP1V1_CPU0_FET

A1
B1
C1

051-9385

A.0.0

82 OF 154

30 OF 39

26

29 39

SIZE

D

C

B

29
39

A

D

8 7 6 5 4 3

12

D

OMIT_TABLE

U8100

D2018

FCBGA

VSS

SYM 3 OF 3

VSS/VSS_BUCK0A0B

VSS/VSS_BUCK0A2

VSS/VSS_BUCK0B4

VSS/VSS_BUCK0C3

VSS/VSS_BUCK2_01

VSS/VSS_BUCK25

VSS/VSSA_BUCK0A
VSS/VSSA_BUCK0B
VSS/VSSA_BUCK0C

VSS/VSSA_BUCK2
VSS/VSSA_BUCK3
VSS/VSSA_BUCK4
VSS/VSSA_BUCK5

VSS_WLED
VSS_WLED

VSS_LCM

VSS

A8
B8
A12
B12
A4
B4

F2

A16
B16
A20
B20

E12
E8
G6
E16
H6
E5
F18

N22
P22
N20

J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18

ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS

C4

D20

F6
F7
F8

F9
F10 F1
F11
F12
F13
F14
F15

C

B

F16
F17

G10
G11
G12
G13
G14
G15
G16
G17
G18

H10
H11
H12
H13
H14
H15
H16
H17
H18

G3

G5

G7

G8

G9

H7

H8

H9

D

C

B

A

SYNC_MASTER=MADHAVI

PAGE TITLE

PMU: ADRIANA PAGE 3

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=12/06/2011

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

83 OF 154

SHEET

31 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

D

D

DEBUG RESET ACCESS

PPBATT_VCC

=PP1V8_S2R_MISC

5

34

5

OUT

GPIO_FORCE_DFU

NOSTUFF

1

R9000

300

5%
1/20W
MF
201

2

C

29 34 39

NOSTUFF

1

R9002

1.5K

1%
1/20W
MF
201

2

PWR_ON_LED

NOSTUFF

A

LED9000

RED-50MCD-20MA

0603

K

30

29 32 34 39

OUT

PP1V8

PMU_SHDWN

NOSTUFF

1

R9001

300

5%
1/20W
MF
201

2

C

B

A

SOCHOT TO PMU TDEV1/TDEV2

PP1V8

29 32 34 39

R9020

470

12

1%

1/32W

MF

01005

R9030

470

12

1%

1/32W

MF

01005

1

R9021

10K

1%
1/32W
MF
01005

2

1

R9031

10K

1%
1/32W
MF
01005

2

7

IN

SOCHOT1_L

1

R9010

100K

5%
1/20W
MF
201

2

CRITICAL

1

R9011

100K

5%
1/20W
MF
201

2

SOCHOT1

3

D

G

1

Q9010

DMN26D0UFB4

S

DFN

SYM_VER_1

2

CRITICAL

1

CRITICAL

1

G

G

3

D

Q9020

DMN26D0UFB4

S

DFN

SYM_VER_1

2

3

D

Q9030

DMN26D0UFB4

S

DFN

SYM_VER_1

2

SOCHOT1_TDEV1

SOCHOT1_TDEV2

6 3

BOARD_TEMP1

BOARD_TEMP2

30 37

OUT

30 37

OUT

SYNC_MASTER=MLB

PAGE TITLE

DEBUG/MISC.

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/09/2011

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

90 OF 154

SHEET

32 OF 39

SIZE

B

A

D

124578

8 7 6 5 4 3

12

D

D

PLATED THROUGH HOLES

DRILL SIZE: 1.1MM X 0.4MM
PLATING SIZE: 1.4MM X 0.7MM

FID4200

FID

0P5SM1P0SQ-NSP

1

FID4201

FID

0P5SM1P0SQ-NSP

1

FID4202

FID

0P5SM1P0SQ-NSP

1

FID4203

C

FID

0P5SM1P0SQ-NSP

1

FID4204

FID

0P5SM1P0SQ-NSP

1

FID4205

FID

0P5SM1P0SQ-NSP

1

SL4201

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4204

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4205

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4206

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4210

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4212

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4213

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4214

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4215

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL4216

TH-NSP

1

SL-1.1X0.4-1.4X0.7

C

SIZE

B

A

D

B

A

SYNC_MASTER=N/A

PAGE TITLE

TEST/HOLES/FIDUCUALS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

93 OF 154

SHEET

33 OF 39

124578

8 7 6 5 4 3

WWW.AliSaler.Com

POWER CONNECTIONS

12

D

C

B

BUCK0A

PP1V1_CPU0

30 39

MAKE_BASE=TRUE

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

BUCK0B

PP1V1_CPU1

30 39

MAKE_BASE=TRUE

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

BUCK0C

PP1V1_CPUB

29 39

MAKE_BASE=TRUE

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

BUCK2

PP1V2_SOC

29 39

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

BUCK3

PP1V8_S2R

29 39

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

BUCK4

PP1V2_S2R

29 39

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PPVDD_CPU0_H5

=PPVDD_CPU1_H5

=PPVDD_CPUB_H5

=PPVDD_SOC_H5

=PP1V8_S2R_MISC

VDDIO_WLAN_BT_1V8

=PP1V8_S2R_USBMUX
=PP1V8_S2R_DDR

=PP1V2_S2R_H5
=PP1V2_S2R_DDR

9

5

14

25

11 12

8

11 12

BUCK5

PP3V3_OUT

29 39

MAKE_BASE=TRUE

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

9

9

BACKLIGHT BOOST

PPLED_OUT_A

30 39

MAKE_BASE=TRUE

VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PPLED_OUT_B

30 39 15

MAKE_BASE=TRUE

VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP3V3_NAND
=PP3V3_USB_H5
=PP3V3_LCD

=PPLED_REG_A

=PPLED_REG_B

13

4

15

15

LDO1

PP3V0_GRAPE

29 39

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

9

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP3V0_GRAPE
=PP3V0_GRAPE_MARIO1
=PP3V0_GRAPE_Z1
=PP3V0_GRAPE_Z2

16 17

16

17

17

LDO2

PP1V7_VA_VCP

19 29 39

MAKE_BASE=TRUE

VOLTAGE=1.7V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

32

MAX_NECK_LENGTH=3 MM

=PP1V7_VA_VCP

18 19

LDO3 (NO LONGER NEEDED)

PP3V2_S2R_USBMUX

29 39

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP3V2_S2R_USBMUX

25

LDO4

PP3V0_SENSOR

29 39

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP3V0_SENSOR

21

LDO9

PP3V0_IO

29 39

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP3V0_VDDIO30_H5

LDO11

PP2V8_CAM

29 39 21

MAKE_BASE=TRUE

VOLTAGE=2.8V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP2V8_CAM

LDO12

PP1V0

29 39

MAKE_BASE=TRUE

VOLTAGE=1.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP1V0_MIPI_H5
=PP1V0_DP_PAD_DVDD_H5
=PP1V0_EDP_PAD_DVDD_H5
=PP1V0_USB_H5
=PP1V0_HSIC_H5
=PP1V0_MIPI_PLL_H5

LDO16

PP1V1_SRAM

29 39

MAKE_BASE=TRUE

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V8_ALWAYS

29 39

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PPVDD_SRAM_H5

=PP1V8_ALWAYS

9

7

7

7

4

4

7

9

5

CHARGER MAIN

PPVCC_MAIN

15 25 29 30 39 18 19

MAKE_BASE=TRUE

VOLTAGE=4.7V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PPVCC_MAIN_AUDIO
=PPVCC_MAIN_LED

PPVCC_MAIN_CPU0
PPVCC_MAIN_CPU1
PPVCC_MAIN_SOC

BATTERY

PPBATT_VCC

29 32 39

MAKE_BASE=TRUE

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=BATT_POS_CONN

=BATT_POS_F_3G
=BATT_VCC

USB POWER INPUT

PPVBUS_USB_EMI

23 39

PPVBUS_USB_DCIN

MAKE_BASE=TRUE

VOLTAGE=6V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

30

29

29

29

28

26

27

29

D

CELLULAR RADIO

WLAN

C

B

BUCK3_SW

CPU1V8_SW

PP1V8

29 32
39

MAKE_BASE=TRUE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM

A

BUCK4_SW

CPU1V2_SW

PP1V2

MAKE_BASE=TRUE

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP1V8_SENSOR

=PP1V8_AUDIO
=PP1V8_VDDIO18_H5

=PP1V8_H5
=PP1V8_MIPI_H5
=PP1V8_DP_H5
=PP1V8_EDP_H5
=PP1V8_NAND_H5

=PP1V8_NAND
=PP1V8_PLL_H5
=PP1V8_MISC

=PP1V2_VDDQ_DDR
=PP1V2_VDDIOD_H5
=PP1V2_HSIC_H5

11 12 29 39
8 9
4

21
18

4 6 7 9
4 5 7
7
7
7
6 9
13
4
16

LDO6

PP3V3_ACC

29 39

MAKE_BASE=TRUE

10

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

=PP3V3_ACC

25

LDO7

PP3V0_S2R_TRISTAR

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

LDO8

PP3V0_S2R_HALL

MAKE_BASE=TRUE

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

6 3

=PP3V0_S2R_TRISTAR

I927

=PP3V0_S2R_HALL

25 29

SIZE

A

D

SYNC_MASTER=N/A

PAGE TITLE

POWER ALIASES

Apple Inc.

R

21 23 29 39

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

121 OF 154

SHEET

34 OF 39

124578

8 7 6 5 4 3

12

MLB CONSTRAINTS

TABLE_BOARD_INFO

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM

=DEFAULT

0.170 MM

0.190 MM

0.190 MM

0.190 MM0.190 MM

ALLEGRO
VERSION

16.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM

BOARD AREAS

NO_TYPE,BGA,BGA06-06,BGA_P4

BOARD UNITS
(MIL or MM)

PHYSICAL CONSTRAINTS

ISL5

ISL6

ALLOW ROUTE
ON LAYER?

*
*

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

LAYER

DEFAULT

D

STANDARD

SINGLE-ENDED PHYSICAL RULES
45 OHMS

LAYER

45_OHM_SE
45_OHM_SE
45_OHM_SE
45_OHM_SE

TOP,BOTTOM

ISL2,ISL9

ISL3,ISL8

ISL4,ISL7

45_OHM_SE
45_OHM_SE

90 OHMS

90_OHM_DIFF

DIFFERENTIAL PAIR PHYSICAL RULES

LAYER

TOP,BOTTOM
90_OHM_DIFF
90_OHM_DIFF

ISL3,ISL8 =STANDARD

90_OHM_DIFF

C

90_OHM_DIFF

DDR 45 OHMS

DDR_45_OHM_SE
DDR_45_OHM_SE
DDR_45_OHM_SE
DDR_45_OHM_SE
DDR_45_OHM_SE
DDR_45_OHM_SE

ISL5,ISL6

SINGLE-ENDED PHYSICAL RULES

LAYER

TOP,BOTTOM

ISL5,ISL6

ALLOW ROUTE
ON LAYER?

ISL2

ISL3

ISL4

* N

Y
Y

Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y

Y
Y
Y
Y
Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=45_OHM_SE

=DEFAULT

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.105 MM

0.055 MM

0.065 MM

0.053 MM

0.072 MM

0.059 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM

0.062 MM

0.062 MM

0.051 MM

0.052 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.105 MM 0.105 MM

0.053 MM

=45_OHM_SE

=DEFAULT

0.055 MM

0.055 MM

0.055 MM

0.055 MM

0.055 MM

0.055 MM

0.090 MM

0.062 MM

0.052 MM

0.051 MM

0.052 MM

0.055 MM0.055 MM

0.065 MM0.065 MM

0.053 MM

0.072 MM0.072 MM

0.055 MM0.055 MM

MAXIMUM NECK LENGTH

3.0 MM

12.7 MM

MAXIMUM NECK LENGTH

3.0 MM

3.0 MM

3.0 MM

3.0 MM

3.0 MM

3.0 MM

MAXIMUM NECK LENGTH

=STANDARD

=STANDARDISL2,ISL9

=STANDARDISL4,ISL7

=STANDARD

MAXIMUM NECK LENGTH

3.0 MM

3.0 MM

3.0 MM

3.0 MM

3.0 MM

3.0 MM

DIFFPAIR PRIMARY GAP

0 MM

=DEFAULT

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

0.170 MM

0.190 MM

0.190 MM

0.105 MM 0.105 MM

DIFFPAIR PRIMARY GAP

TCF VERSION (USING SPACING RULE)

SPACING_RULE_SET

TCF_VERSION

I1

LAYER

TCF_VERSION

LINE-TO-LINE SPACING

* ?

0.104 MM

NC_UART5_TXD

SPACING CONSTRAINTS

DEFAULT/BGA SPACING RULES

SPACING_RULE_SET

LAYER

DEFAULT

STANDARD

BGA_SPA

BGA_P4_SPA

REGULAR SPACING RULES

SPACING_RULE_SET

1:1_SPACING

0P08_SPACING

1.5:1_SPACING
2:1_SPACING

2.5:1_SPACING
3:1_SPACING
4:1_SPACING
5:1_SPACING

0P5MM_SPACING

0P2_SPACING

POWER/GND SPACING RULES

SPACING_RULE_SET

PWR_P1SPACING
GND_P1SPACING

SWITCHNODE

LINE-TO-LINE SPACING

* ?
*
* ?

0.100 MM
=DEFAULT
=DEFAULT

0.200 MM

*

LINE-TO-LINE SPACING

0.050 MM

LAYER

0.080 MM
* ?
*
*
*
* ?
*
*
*
*

LAYER

*
*
*

0.075 MM

0.100 MM

0.125 MM

0.150 MM

0.200 MM

0.250 MM

0.5 MM
MM 46.0GNICAPS_MM46P0

0.20 MM

LINE-TO-LINE SPACING

0.1 MM

0.1 MM

0.2 MM

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

0.104 - 11/30/2011

ASSIGNING RULE TO NC NET

5

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

NOTES:

0.075 MM ~ 3 MIL

0.089 MM ~ 3.5 MIL

0.102 MM ~ 4 MIL

0.114 MM ~ 4.5 MIL

0.125 MM ~ 5 MIL

0.140 MM ~ 5.5 MIL

0.15 MM ~ 6 MIL

0.18 MM ~ 7 MIL

0.2 MM ~ 8 MIL

0.25 MM ~ 10 MIL

0.3 MM ~ 12 MIL

0.33 MM ~ 13 MIL

0.4 MM ~ 16 MIL

1.0 MM = 39.37 MIL

D

C

DDR 90 OHMS

DDR_90_OHM_DIFF
DDR_90_OHM_DIFF
DDR_90_OHM_DIFF
DDR_90_OHM_DIFF
DDR_90_OHM_DIFF

B

DDR_90_OHM_DIFF

WIFI PHYSICAL RULES

WIFI_50S
WIFI_50S

WIFI_PWR100

WIFI_PWR1000

MISC PHYSICAL RULES

1:1_DIFFPAIR

SPEAKER

AUDIO_DIFF

LED

TEMP_SENSE

A

BGA AREA PHYSICAL RULES

NET_PHYSICAL_TYPE

*

BGA_PHY

DIFFERENTIAL PAIR PHYSICAL RULES

LAYER

TOP,BOTTOM

ISL2

ISL3

ISL4

ISL5,ISL6

*

LAYER

TOP,BOTTOM

*

*

*

LAYER

*

* Y
*
*

AREA_TYPE

BGA

LAYER

*

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

PHYSICAL_RULE_SET

BGA_PHY

ALLOW ROUTE
ON LAYER?

Y
Y
Y
Y
Y
N

Y
N
Y
Y

Y
Y*

Y
Y

Y

MINIMUM LINE WIDTH

0.062 MM

0.062 MM

0.051 MM

0.066 MM 0.066 MM

0.056 MM

MINIMUM LINE WIDTH

0.245 MM 0.2 MM

0.10 MM

1.00 MM

MINIMUM LINE WIDTH

0.5 MM

0.1 MM

0.1 MM

0.1 MM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

0.060 MM

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

0.090 MM0.090 MM

0.062 MM

0.062 MM

0.051 MM

0.056 MM

=STANDARD=STANDARD

0.050 MM

0.100 MM

=STANDARD =STANDARD=STANDARD

0.20 MM

0.09 MM

0.09 MM

0.09 MM

0.060 MM

MAXIMUM NECK LENGTH

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

=STANDARD

=STANDARD

=STANDARD

MAXIMUM NECK LENGTH

10 MM
10 MM
10 MM
10 MM

MAXIMUM NECK LENGTH

=STANDARD

0.170 MM

0.190 MM0.190 MM

0.190 MM0.190 MM

0.190 MM

0.180 MM0.180 MM

0.180 MM

0.08 MM

0.10 MM0.10 MM

0.08 MM

0.08 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

POWER

LAYER

PWR

*

GND_PH

PWR_PMU

MISC

NET_SPACING_TYPE1 NET_SPACING_TYPE2

*

CLK BGA

GND

ANLG

*
*

**

ALLOW ROUTE
ON LAYER?

Y
Y*
Y*

MINIMUM LINE WIDTH

AREA_TYPE

BGA

**

**

**

BGA_P4

0.6MM

0.6MM

0.6MM

SPACING_RULE_SET

BGA_SPA
BGA_SPA

GND_P1SPACING

SWITCHNODESWITCHNODE

3:1_SPACING

BGA_P4_SPA

DIFFPAIR PRIMARY GAP

0.170 MM

0.190 MM

0.180 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

0.08 MM

0.10 MM 0.10 MM

0.08 MM

0.08 MM

DIFFPAIR PRIMARY GAP

0.076 MM 0.075 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

6 3

MINIMUM NECK WIDTH

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

0.20 MM

0.075 MM

0.20 MM

MAXIMUM NECK LENGTH

3.0 MM

3.0 MM

3.0 MM

DIFFPAIR PRIMARY GAP

SYNC_MASTER=MIKE

PAGE TITLE

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

CONSTRAINTS: MLB RULES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SYNC_DATE=11/30/2011

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

150 OF 154

SHEET

35 OF 39

124578

SIZE

B

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

Clock Signal Constraints

45_OHM_SE

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

*

NET_TYPE

CLK
CLK

CLK
CLK
CLK
CLK

I2S
I2S
CLK
CLK
CLK
CLK
CLK
CLK

NET_PHYSICAL_TYPE

CLK_50S

AREA_TYPE

PHYSICAL_RULE_SET

*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK

D

ELECTRICAL_CONSTRAINT_SET

I63

I162

I88

I89

I96

I94

I130

I131

I157

I158

I234

I235

I256

I257

*

CLK_50S
CLK_50S

CLK_50S
CLK_50S
CLK_50S
CLK_50S

I2S_50S
I2S_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S

UART

NET_PHYSICAL_TYPE

UART_50S

AREA_TYPE

PHYSICAL_RULE_SET

*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

UART

TRAUTRAU

ELECTRICAL_CONSTRAINT_SET

I237

I236

I174

I173

I175

I176

I177

I178

I179

I182

I181

I180

I232

I233

SPI

B

NET_PHYSICAL_TYPE

SPI_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SPI

ELECTRICAL_CONSTRAINT_SET

I183

I184

I185

I186

I187

I188

I189

I190

I240

I241

I242

I243

A

DWI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DWI

ELECTRICAL_CONSTRAINT_SET

I152

I153

I156

AREA_TYPE

*

*

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

45_OHM_SE

AREA_TYPE

**

*

NET_TYPE

PHYSICAL

45_OHM_SE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_TYPE

PHYSICAL

SPI_50S
SPI_50S
SPI_50S
SPI_50S

SPI_50S
SPI_50S
SPI_50S
SPI_50S

SPI_50S
SPI_50S
SPI_50S
SPI_50S

AREA_TYPE

NET_TYPE

PHYSICAL

UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S
UARTUART_50S

*

**

SPACING_RULE_SET

3:1_SPACING

SPACING

SPACING_RULE_SET

3:1_SPACING

2:1_SPACING

SPACING

SPACING_RULE_SET

2:1_SPACING

SPACING

SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

SPACING_RULE_SET

2:1_SPACING

SPACING

DWI
DWI
DWI

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PMU_GPIO_CLK_32K_GRAPE
PMU_GPIO_CLK_32K_WLAN

ISP1_CAM_FF_CLK
CONN_ISP1_CAM_FF_CLK
ISP0_CAM_RF_CLK
CONN_ISP0_CAM_RF_CLK

I2S0_CODEC_ASP_MCK
I2S0_CODEC_ASP_MCK_R
ISP0_CAM_RF_CLK_R
ISP1_CAM_FF_CLK_R
ISP1_CAM_FF_C
ISP0_CAM_RF_C
ISP1_CAM_FF_FILT
ISP0_CAM_RF_FILT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

UART2_TS_ACC_RXD
UART2_TS_ACC_TXD
UART4_WLAN_RXD
UART4_WLAN_TXD
UART1_BB_CTS_L
UART1_BB_RTS_L
UART1_BB_TXD
UART1_BB_RXD
UART3_BT_CTS_L
UART3_BT_RTS_L
UART3_BT_RXD
UART3_BT_TXD
UART6_AP_RXD
UART6_AP_TXD

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPI3_GRAPE_MISO
SPI3_GRAPE_MOSI
SPI3_GRAPE_SCLK
SPI3_GRAPE_CS_L

SPI2_IPC_MISO
SPI2_IPC_MOSI
SPI2_IPC_SCLK
GPIO_BB_HSIC_RESUME

SPI1_CODEC_MISO
SPI1_CODEC_MOSI
SPI1_CODEC_SCLK
SPI1_CODEC_CS_L

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

DWI_AP_CLK
DWI_AP_DI
DWI_AP_DO

USB

90_OHM_DIFF

AREA_TYPE

NET_TYPE

PHYSICAL

45_OHM_SE

AREA_TYPE

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

*

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

**

**

SPACING

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB

SPACING_RULE_SET

SPACING

HSICHSIC
HSICHSIC
HSICHSIC
HSICHSIC

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

4:1_SPACING

USB_AP_P
USB_AP_N
USB_BBMUX_BB_P
USB_BBMUX_BB_N
USB_TS_BBMUX_P
USB_TS_BBMUX_N
USB11_AP_BBMUX_P
USB11_AP_BBMUX_N
CONN_E75_DPAIR1_P
CONN_E75_DPAIR1_N
CONN_E75_DPAIR2_P
CONN_E75_DPAIR2_N
TS_E75_DPAIR1_P
TS_E75_DPAIR1_N
TS_E75_DPAIR2_P
TS_E75_DPAIR2_N

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

4:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

HSIC3_BB_DATA
HSIC3_BB_STB
HSIC1_WLAN_DATA
HSIC1_WLAN_STB
GPIO_BB_HSIC_DEV_RDY
GPIO_BB_HSIC_HOST_RDY
GPIO_WLAN_HSIC_HOST_RDY
GPIO_WLAN_HSIC_HOST_RDY
GPIO_WLAN_HSIC_DEV_RDY

D

4

25
25

4
25 26
25 26
25
25
4

25

4

25
24 25
24 25
24 25
24 25
25
25
25
25

C

4

26

4

26

4

14

4

14

5

26

5

26

5

14 36

5

14 36

5

14

B

17 30
14 30

7
20 22
7
20 22

5
5
7
7
22
22
22
22

5
5
5
5
5
5
5
5
5
5
5
5
5
5

22

22

36
18 36

25
25
14
14
26
26
25 26
25 26
14
14
14
14
25
25

JTAG

NET_SPACING_TYPE1 NET_SPACING_TYPE2

JTAG

*

ELECTRICAL_CONSTRAINT_SET

I16

I15

I14

I13

I20

I2C

NET_PHYSICAL_TYPE

I2C_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

I2C

ELECTRICAL_CONSTRAINT_SET

I1

I2

I3

I4

I61

I62

I98

I99

I100

I101

I102

I103

I228

I229

I124

I125

I226

I227

AREA_TYPE

*

XTAL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CRYSTAL

ELECTRICAL_CONSTRAINT_SET

I92

I90

I93

I230

I231

*

AREA_TYPE

NET_TYPE

PHYSICAL

PHYSICAL_RULE_SET

45_OHM_SE

AREA_TYPE

NET_TYPE

PHYSICAL

I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S

AREA_TYPE

NET_TYPE

PHYSICAL

*

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

**

*

SPACING_RULE_SET

2:1_SPACING

SPACING

JTAG
JTAG
JTAG
JTAG
RST

SPACING_RULE_SET

1.5:1_SPACING

SPACING

I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C

SPACING_RULE_SET

5:1_SPACING

SPACING

CRYSTAL
CRYSTAL
CRYSTAL
CRYSTAL
CRYSTAL

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

JTAG_AP_TCK
JTAG_AP_TMS
JTAG_AP_TDI
TP_JTAG_AP_TDO

JTAG_AP_TRST_L

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

I2C1_SDA_1V8

I2C1_SCL_1V8
I2C0_SDA_1V8
I2C0_SCL_1V8
I2C2_SDA_3V0
I2C2_SCL_3V0
ISP0_CAM_RF_I2C_SCL
ISP0_CAM_RF_I2C_SDA
ISP1_CAM_FF_I2C_SCL
ISP1_CAM_FF_I2C_SDA

CONN_I2C1_SDA_1V8

CONN_I2C1_SCL_1V8
CONN_I2C2_SCL_3V0
CONN_I2C2_SDA_3V0
CONN_ISP0_CAM_RF_I2C_SCL
CONN_ISP0_CAM_RF_I2C_SDA
CONN_ISP1_CAM_FF_I2C_SCL
CONN_ISP1_CAM_FF_I2C_SDA

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

XTAL_AP_24M_I
XTAL_AP_24M_O
AP_24M_O
PMU_XTAL
PMU_EXTAL

NET_PHYSICAL_TYPE

USB_90D

AREA_TYPE

PHYSICAL_RULE_SET

*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AREA_TYPE

*

*

USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D

PHYSICAL_RULE_SET

PHYSICAL

HSIC HSIC_RDY
HSIC HSIC_RDY
HSIC HSIC_RDY
HSIC HSIC_RDY
HSIC HSIC_RDY

USB

4

25

4

25
4
4
4

10 39

5

22

5

22

5

19 25 30

5

19 25 30
22

5
5

22

7

22

7

22

7

22

7

22
20 22
20 22
20 22
20 22
20 22
20 22
20 22
20 22

4
4
4

29
29

ELECTRICAL_CONSTRAINT_SET

I5

I6

I266

I267

I268

I269

I270

I271

I258

I259

I260

I261

I263

I262

I265

I264

HSIC

NET_PHYSICAL_TYPE

HSIC

NET_SPACING_TYPE1 NET_SPACING_TYPE2

HSIC

HSIC_RDY

ELECTRICAL_CONSTRAINT_SET

I191

I194

I193

I192

I195

I196

I197

I198

I199

I2S

45_OHM_SE

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

*

*

NET_TYPE

SPACING_RULE_SET

SPACING

I2S
I2S
I2S
I2S
I2S
I2S
I2S

I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DIN
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_SDOUT
I2S0_CODEC_ASP_MCK
I2S0_CODEC_ASP_MCK_R

I2S3_CODEC_XSP_BCLK
I2S3_CODEC_XSP_LRCK
I2S3_CODEC_XSP_DIN
I2S3_CODEC_XSP_DOUT
I2S0_CODEC_XSP_SDOUT
I2S2_BT_BCLK
I2S2_BT_LRCK
I2S2_BT_DIN
I2S2_BT_DOUT

5

18

5

18

5

18

5

18
18
5

36
5

18 36

5

18
5

18

18

5
5

18

5

14
5

14
5

14
5

14

SYNC_MASTER=MIKE

PAGE TITLE

CONSTRAINTS: LOW SPEED BUS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/30/2011

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

151 OF 154

SHEET

36 OF 39

SIZE

A

D

124578

NET_PHYSICAL_TYPE

AREA_TYPE

I2S_50S

5

16

5

16

5

16

5

16

NET_SPACING_TYPE1 NET_SPACING_TYPE2

I2S

PHYSICAL_RULE_SET

*

*

I2SI2S

ELECTRICAL_CONSTRAINT_SET

5

26

5

18

5

18

5

18

5

18

5

30

5

30

5

30

I140

I143

I142

I141

I159

I144

I148

I145

I149

I150

I151

I161

I244

I245

I247

I246

I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S

I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S

6 3

8 7 6 5 4 3

12

EMBEDDED DISPLAYPORT

*

PHYSICAL_RULE_SET

PHYSICAL

EDP_90D
EDP_90D
EDP_50S
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D

MIPI

*

MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D

MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D

MIPI_90D
MIPI_90D

*

*

PHYSICAL_RULE_SET

PHYSICAL

NET_PHYSICAL_TYPE

AREA_TYPE

MIPI_90D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MIPI0C

D

MIPI1C

ELECTRICAL_CONSTRAINT_SET

I315

I316

I343

I342

I311

I312

I395

I394

I519

I518

I521

I520

I345

I346

I347

I348

I354

I356

I415

I414

90_OHM_DIFF

AREA_TYPE

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

*

*

MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C

MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI1C
MIPI1C
MIPI1C
MIPI1C
MIPI1C
MIPI1C

MIPI1C
MIPI1C

SPACING

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

4:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

4:1_SPACING

MIPI0C_CAM_RF_CLK_P
MIPI0C_CAM_RF_CLK_N
MIPI0C_CAM_RF_DATA_P<0>
MIPI0C_CAM_RF_DATA_N<0>
MIPI0C_CAM_RF_DATA_P<1>
MIPI0C_CAM_RF_DATA_N<1>

MIPI0C_CAM_RF_CLK_F_P
MIPI0C_CAM_RF_CLK_F_N
MIPI0C_CAM_RF_DATA_F_P<0>
MIPI0C_CAM_RF_DATA_F_N<0>
MIPI0C_CAM_RF_DATA_F_P<1>
MIPI0C_CAM_RF_DATA_F_N<1>
MIPI1C_CAM_FF_CLK_P
MIPI1C_CAM_FF_CLK_N
MIPI1C_CAM_FF_DATA_P<0>
MIPI1C_CAM_FF_DATA_N<0>
MIPI1C_CAM_FF_CLK_F_P
MIPI1C_CAM_FF_CLK_F_N

MIPI1C_CAM_FF_DATA_F_P<0>
MIPI1C_CAM_FF_DATA_F_N<0>

7
7
7
7
7
7

20 21
20 21
20 21
20 21
20 21
20 21
7
7
7
7
20 21
20 21

20 21
20 21

21
21
21
21
21
21

21
21
21
21

C

NET_PHYSICAL_TYPE

EDP_90D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

EDP

ELECTRICAL_CONSTRAINT_SET

I435

I436

I437

I439

I438

I440

I442

I441

I444

I443

I445

I447

I446

I449

I448

I450

I451

I452

I454

I453

I455

I457

I456

I458

I460

I459

I462

I461

I463

I464

I465

AREA_TYPE

90_OHM_DIFF

AREA_TYPE

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

**

SPACING

NET_PHYSICAL_TYPE

SPACING_RULE_SET

4:1_SPACING

EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP

EDP_50S

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

EDP_AUX_P
EDP_AUX_N
EDP_HPD
EDP_DATA_P<0>
EDP_DATA_N<0>
EDP_DATA_P<1>
EDP_DATA_N<1>
EDP_DATA_P<2>
EDP_DATA_N<2>
EDP_DATA_P<3>
EDP_DATA_N<3>
EDP_AUX_EMI_P
EDP_AUX_EMI_N
EDP_DATA_EMI_P<0>
EDP_DATA_EMI_N<0>
EDP_DATA_EMI_P<1>
EDP_DATA_EMI_N<1>
EDP_DATA_EMI_P<2>
EDP_DATA_EMI_N<2>
EDP_DATA_EMI_P<3>
EDP_DATA_EMI_N<3>
CONN_EDP_AUX_EMI_P
CONN_EDP_AUX_EMI_N
CONN_EDP_DATA_EMI_P<0>
CONN_EDP_DATA_EMI_N<0>
CONN_EDP_DATA_EMI_P<1>
CONN_EDP_DATA_EMI_N<1>
CONN_EDP_DATA_EMI_P<2>
CONN_EDP_DATA_EMI_N<2>
CONN_EDP_DATA_EMI_P<3>
CONN_EDP_DATA_EMI_N<3>

AREA_TYPE

*

PHYSICAL_RULE_SET

45_OHM_SE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

7

15
15

7
7

15
15

7
7

15

7

15
15

7
7

15

7

15

7

15

7

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

AUDIO/SPEAKER

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

HP_MIC_P
HP_MIC_N

L81_AIN2_P
L81_AIN2_N

SPKR_L_VSENSE_N_FILT
SPKR_L_VSENSE_P_FILT
SPKR_L_VSENSE_N
SPKR_L_VSENSE_P

SPKR_R_VSENSE_N_FILT
SPKR_R_VSENSE_P_FILT
SPKR_R_VSENSE_N
SPKR_R_VSENSE_P

SPKR_L_P
SPKR_L_N

SPKR_L_CONN_P
SPKR_L_CONN_N

SPKR_R_P
SPKR_R_N

SPKR_R_CONN_P
SPKR_R_CONN_N
SPKR_L_FLR
SPKR_R_FLR

18
18

18
18

19
19
19
19

19
19
19
19

19
19

19
19

19
19

19
19
19
19

PHYSICAL

AUDIO_DIFF
AUDIO_DIFF

AUDIO_DIFF
AUDIO_DIFF

AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF

AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF

SPEAKER
SPEAKER

SPEAKER
SPEAKER

SPEAKER
SPEAKER

SPEAKER
SPEAKER
SPEAKER
SPEAKER

AREA_TYPE

NET_TYPE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AUDIO

ELECTRICAL_CONSTRAINT_SET

I584
I585

I587
I586

I589
I588
I591

B

I590

I592
I593
I594
I595

I597
I596

I598
I599

I606
I607

I608
I609
I610
I611

**

AUDIO
AUDIO

AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO

AUDIO
AUDIO

AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO

SPACING_RULE_SET

SPACING

BACKLIGHT

*

PHYSICAL_RULE_SET

PHYSICAL

LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED

NET_PHYSICAL_TYPE

AREA_TYPE

ELECTRICAL_CONSTRAINT_SET

I482

I484

I483

I485

I487

I486

I489

I488

I490

I491

I492

I493

I494

I495

I496

I497

I498

I499

I500

I501

I502

I503

I504

I505

TEMP SENSORS

NET_PHYSICAL_TYPE

AREA_TYPE

BOARD_TEMP TEMP_SENSE

ELECTRICAL_CONSTRAINT_SET

I572

I574

I576

I577

I578

I579

I580

I581

I582

I583

I602
I603
I604
I605

PHYSICAL_RULE_SET

*

PHYSICAL

BOARD_TEMP

BOARD_TEMP BOARD_TEMP
BOARD_TEMP BOARD_TEMP
BOARD_TEMP BOARD_TEMP
BOARD_TEMP BOARD_TEMP

BOARD_TEMP BOARD_TEMP

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

DELDEL

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_TYPE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LEDA

LEDB

SPACING

BOARD_TEMP

LED_IO1_A_R
LED_IO1_B_R
LED_IO2_A_R
LED_IO2_B_R
LED_IO3_A_R

LED_IO3_B_R
LED_IO4_A_R
LED_IO4_B_R
LED_IO5_A_R
LED_IO5_B_R
LED_IO6_A_R
LED_IO6_B_R
LED_IO_1_A
LED_IO_1_B
LED_IO_2_A

LED_IO_2_B
LED_IO_3_A
LED_IO_3_B
LED_IO_4_A
LED_IO_4_B
LED_IO_5_A

LED_IO_5_B
LED_IO_6_A
LED_IO_6_B

BOARD_TEMP1

BOARD_TEMP2

BOARD_TEMP3_P
BOARD_TEMP3_N
BOARD_TEMP4_P
BOARD_TEMP4_N
BOARD_TEMP5_P
BOARD_TEMP5_N
BOARD_TEMP6_P
BOARD_TEMP6_N
BOARD_TEMP7_P
BOARD_TEMP7_N
BOARD_TEMP8_P
BOARD_TEMP8_N

LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SPACING

BOARD_TEMP

BOARD_TEMP

BOARD_TEMPBOARD_TEMP
BOARD_TEMP
BOARD_TEMPBOARD_TEMP

BOARD_TEMPBOARD_TEMP
BOARD_TEMPBOARD_TEMP
BOARD_TEMPBOARD_TEMP
BOARD_TEMPBOARD_TEMP

AREA_TYPE

**

**

30
30
30
30
30
30
30
30
30
30
30
30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30

AREA_TYPE

**

30 32

30 32

30
30
30
30
30
30
30
30
30
30
30
30

3:1_SPACING

3:1_SPACING

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

SPACING_RULE_SET

D

C

B

I564

I565

I558

I560

A

I570

I569

I600
I601

AUDIO_DIFF
AUDIO_DIFF

AUDIO_DIFF
AUDIO_DIFF

USB_90D
USB_90D

USB_90D
USB_90D

AUDIO
AUDIO

AUDIO
AUDIO

USB
USB

USB
USB

SPKR_L_SES_N
SPKR_L_SES_P

SPKR_R_SES_N
SPKR_R_SES_P

MIKEY_TS_P
MIKEY_TS_N

L81_MBUS_P
L81_MBUS_N

19
19

19
19

18 25
18 25

18
18

6 3

SYNC_MASTER=MIKE

PAGE TITLE

CONSTRAINTS: DISPLAY/AUDIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

SYNC_DATE=11/30/2011

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

152 OF 154

SHEET

37 OF 39

124578

SIZE

A

D

8 7 6 5 4 3

WWW.AliSaler.Com

12

DDR

NET_PHYSICAL_TYPE

DDR_50S

ELECTRICAL_CONSTRAINT_SET

AREA_TYPE

*

PHYSICAL_RULE_SET

DDR_45_OHM_SE

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_TYPE

D

I221
I222
I223
I225
I226
I224

I228
I230
I229
I231
I232
I233
I235
I234
I236
I237
I238
I239
I240

I201
I202

C

B

A

I203
I205
I206
I204

I208
I210
I209
I211
I212
I213
I215
I214
I216
I217
I218
I219
I220

I181
I182
I183
I185
I186
I184

I188
I190
I189
I191
I192
I193
I195
I194
I196
I197
I198
I199
I200

I38
I39
I41
I44
I43
I47

I48
I37
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I180

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S

DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DDR

NET_PHYSICAL_TYPE

AREA_TYPE

DDR_90D

SPACING

DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR
DDR
DDR
DDR
DDR

DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR

DDR0_CA<9..0>
DDR0_DM<3..0>
DDR0_CK_P
DDR0_CK_N
DDR0_CKE<1..0>
DDR0_CSN<2..0>

DDR0_ZQ
DDR0_DQ<7..0>
DDR0_DQS_P<0>
DDR0_DQS_N<0>
DDR0_DQ<15..8>
DDR0_DQS_P<1>
DDR0_DQS_N<1>
DDR0_DQ<23..16>
DDR0_DQS_P<2>
DDR0_DQS_N<2>
DDR0_DQ<31..24>
DDR0_DQS_P<3>
DDR0_DQS_N<3>

DDR1_CA<9..0>
DDR1_DM<3..0>
DDR1_CK_P
DDR1_CK_N
DDR1_CKE<1..0>
DDR1_CSN<2..0>

DDR1_ZQ
DDR1_DQ<7..0>
DDR1_DQS_P<0>
DDR1_DQS_N<0>
DDR1_DQ<15..8>
DDR1_DQS_P<1>
DDR1_DQS_N<1>
DDR1_DQ<23..16>
DDR1_DQS_P<2>
DDR1_DQS_N<2>
DDR1_DQ<31..24>
DDR1_DQS_P<3>
DDR1_DQS_N<3>

DDR2_CA<9..0>
DDR2_DM<3..0>
DDR2_CK_P
DDR2_CK_N
DDR2_CKE<1..0>
DDR2_CSN<2..0>

DDR2_ZQ
DDR2_DQ<7..0>
DDR2_DQS_P<0>
DDR2_DQS_N<0>
DDR2_DQ<15..8>
DDR2_DQS_P<1>
DDR2_DQS_N<1>
DDR2_DQ<23..16>
DDR2_DQS_P<2>
DDR2_DQS_N<2>
DDR2_DQ<31..24>
DDR2_DQS_P<3>
DDR2_DQS_N<3>

DDR3_CA<9..0>
DDR3_DM<3..0>
DDR3_CK_P
DDR3_CK_N
DDR3_CKE<1..0>
DDR3_CSN<2..0>

DDR3_ZQ
DDR3_DQ<7..0>
DDR3_DQS_P<0>
DDR3_DQS_N<0>
DDR3_DQ<15..8>
DDR3_DQS_P<1>
DDR3_DQS_N<1>
DDR3_DQ<23..16>
DDR3_DQS_P<2>
DDR3_DQS_N<2>
DDR3_DQ<31..24>
DDR3_DQS_P<3>
DDR3_DQS_N<3>

*

DDR_90_OHM_DIFF

AREA_TYPE

PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

8
8
8
8
8
8

11
8
8
8
8
8
8
8
8
8
8
8
8

8
8
8
8
8
8

11
8
8
8
8
8
8
8
8
8
8
8
8

8
8
8
8
8
8

12
8
8
8
8
8
8
8
8
8
8
8
8

8
8
8
8
8
8

12
8
8
8
8
8
8
8
8
8
8
8
8

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

**

11
11
11
11
11
11

11
11
11
11
11
11
11
11
11
11
11
11

11
11
11
11
11
11

11
11
11
11
11
11
11
11
11
11
11
11

12
12
12
12
12
12

12
12
12
12
12
12
12
12
12
12
12
12

12
12
12
12
12
12

12
12
12
12
12
12
12
12
12
12
12
12

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

NAND

NET_PHYSICAL_TYPE

NAND_50S

ELECTRICAL_CONSTRAINT_SET

I68
I69
I70
I71
I72
I73
I74
I75
I76
I77
I78
I120
I121
I122
I123
I124
I125
I126

I128

I131

I133

I135
I136
I137
I138
I139
I140
I141
I142
I143
I144

I146

I148
I149
I150
I151
I152

I154

I156

I160

AREA_TYPE

*

DDR VREF

NET_SPACING_TYPE1 NET_SPACING_TYPE2

VREF

ELECTRICAL_CONSTRAINT_SET

I166
I167
I169
I168
I244
I243
I241
I242

PHYSICAL_RULE_SET

45_OHM_SE

NET_TYPE

PHYSICAL

NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S

NAND_50S

NAND_50S

NAND_50S

NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S

NAND_50S

NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S

NAND_50S

NAND_50S

NAND_50S

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

**

NET_TYPE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

NAND0

NAND1

SPACING

SPACING_RULE_SET

5:1_SPACING

SPACING

FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>
FMI0_ALE
FMI0_CE0_L
TP_FMI0_CE1_L
TP_FMI0_CE2_L
TP_FMI0_CE3_L
TP_FMI0_CE4_L
TP_FMI0_CE5_L
TP_FMI0_CE6_L
TP_FMI0_CE7_L
FMI0_CLE

FMI0_DQS

FMI0_RE_L
FMI0_WE_L

FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>
FMI1_ALE
FMI1_CE0_L

TP_FMI1_CE2_L
TP_FMI1_CE4_L

TP_FMI1_CE5_L
TP_FMI1_CE6_L
TP_FMI1_CE7_L
FMI1_CLE

FMI1_DQS

FMI1_RE_L
FMI1_WE_L

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PPVREF_DDR0_CA
PPVREF_DDR0_DQ
PPVREF_DDR1_CA
PPVREF_DDR1_DQ
PPVREF_DDR2_CA
PPVREF_DDR2_DQ
PPVREF_DDR3_CA
PPVREF_DDR3_DQ

NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0

NAND0

NAND0

NAND0

NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1

NAND1

NAND1
NAND1
NAND1
NAND1
NAND1

NAND1

NAND1

NAND1

PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR

AREA_TYPE

**

**

13

6
6

13

6

13

6

13

6

13

6

13

6

13
13

6
6

13
13

6

13

6

6

13

6

13

6

13

6

13

6

13
13

6

13

6
6

13

6

13

6

13

6

13

6

13

6

13

6

13

6

13

13

6

6

13

11
11
11
11
12
12
12
12

39
39
39
39
39
39
39
39

SPACING_RULE_SET

2:1_SPACING

2:1_SPACING

6 3

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

WIFI

*
*
*

PHYSICAL_RULE_SET

WIFI_PWR1000

PHYSICAL

WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S

NET_PHYSICAL_TYPE

AREA_TYPE

WIFI_PWR100 WIFI_PWR100

WIFI_PWR1000

ELECTRICAL_CONSTRAINT_SET

I245
I246
I247
I248
I249
I250
I251

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

S05_IFIWS05_IFIW

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_TYPE

SPACING

SYNC_MASTER=MIKE

PAGE TITLE

50_WLAN_G
50_WLAN_A
50_WLAN_G_1
50_WLAN_A_DIPLX
50_WIFI_ANT_FD_2
50_WIFI_ANT_FD_1
50_WIFI_ANT_FD

CONSTRAINTS: DDR/FMI

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

27
27
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SYNC_DATE=11/30/2011

DRAWING NUMBER

051-9385

REVISION

A.0.0

BRANCH

PAGE

153 OF 154

SHEET

38 OF 39

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

PWR

*

PHYSICAL_RULE_SET

PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR

PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PWR500
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR

PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PWR500
PP_PWR

NET_PHYSICAL_TYPE

AREA_TYPE

PP_PWR

VOLTAGE

D

C

B

I221

I1

I2

I3

I4

I5

I6

I7

I8

I9

I12

I11

I10

I13

I15

I14

I16

I17

I18

I19

I20

I21

I23

I22

I24

I25

I26

I28

I29

I30

I31

I32

I33

I34

I35

I36

I37

I38

I39

I40

I41

I42

I43

I44

I45

I46

I47

I49

I51

I50

I53

I52

I54

I55

I56

I57

I58

I59

I60

I61

1.1V

1.1V

1.1V

1.1V

1.1V

1.1V

1.1V

1.1V

1.1V

1.1V

1.1V

1.2V

1.2V

1.2V

1.2V

1.2V

1.8V

1.8V

1.8V

1.2V

1.2V

1.2V

1.1V

1.1V

3.3V

3.0V

1.7V

3.0V

3.2V

3.3V

3.0V

3.0V

3.0V

3.0V

2.8V

1.0V

1.1V

1.8V

1.2V

1.8V

1.8V

4.7V

4.2V

6.0V

6.0V

6.0V

5.25V

1.1V

1.1V

20.4V

20.4V

1.8V

1.0V

1.8V

1.8V

3.3V

3.3V

20.4V

20.4V

PWR_PMU

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_TYPE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PWR

SPACING

PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR

PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR

PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR

BUCK0A_LX0
BUCK0A_LX1
BUCK0A_FB

PP1V1_CPU0_FET

BUCK0B_LX0
BUCK0B_LX1
BUCK0B_FB

PP1V1_CPU1_FET

BUCK0C_LX0
BUCK0C_FB

PP1V1_CPUB

BUCK2_LX0
BUCK2_LX1
BUCK2_LX2
BUCK2_FB

PP1V2_SOC

BUCK3_LX0
BUCK3_FB

PP1V8_S2R

BUCK4_LX0
BUCK4_FB

PP1V2_S2R

BUCK5_LX0
BUCK5_FB

PP3V3_OUT
PP3V0_GRAPE
PP1V7_VA_VCP
PP3V2_S2R_USBMUX

LDO5

PP3V3_ACC
PP3V0_S2R_HALL
PP3V2_S2R_USBMUX
PP3V0_IO
PP3V0_SENSOR
PP2V8_CAM
PP1V0
PP1V1_SRAM
PP1V8_ALWAYS
PP1V2

DSP_SW

PP1V8
PP1V8_GRAPE
PPVCC_MAIN
PPBATT_VCC
PP6V0_LCM_HI

LCM_LX

PP6V0_LCM_VBOOST
PP5V25_VLCM1
PP1V1_CPU0
PP1V1_CPU1

PPLED_OUT_A
PPLED_OUT_B
PP1V8_PL0_F
PP1V0_MIPI_PLL_F
PP1V8_EDP_AVDD_AUX
PP1V8_DP_AVDD_AUX
PP3V3_S0_LCD_FERR

PP3V3_LCDVDD_SW_F
PPLED_BACK_REG_B
PPLED_BACK_REG_A

AREA_TYPE

*

29
29
29
29 30
29
29
29
29 30
29
29
29 34
29
29
29
29
29 34
29
29
29 34
29
29
29 34
29
29
29 34
29 34
19 29 34
29 34 39

29
29 34
29 34
29 34 39
29 34
29 34
29 34
29 34
29 34
29 34
29 34

29 32 34

15 25 29 30 34
29 32 34
30
30
30

30 34
30 34

30 34
30 34
4
7
7

15
15
15
15

SPACING_RULE_SET

*

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

GND

VOLTAGE=0V

VOLTAGE=0V

VOLTAGE=0V
VOLTAGE=0V

VOLTAGE=0V

VOLTAGE=0V
VOLTAGE=0V
VOLTAGE=0V

AREA_TYPE

*

NET_PHYSICAL_TYPE

ELECTRICAL_CONSTRAINT_SET

I199

I200

I203

I207

I217

I224
I225
I226

RST

NET_SPACING_TYPE1 NET_SPACING_TYPE2

RST

ELECTRICAL_CONSTRAINT_SET

I165

I166

I167

I171

I169

I170

I168

I172

I174

I173

I175

I176

I177

I178

I179

I181

I182

I183

PHYSICAL

PHYSICAL

GND_PHGND

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_TYPE

AREA_TYPE

NET_TYPE

PHYSICAL_RULE_SET

GND GND
GND GND

*

*

RST
RST
RST
RST
RST
RST
RST
RST
RST
RST
RST
GRAPE
RST
RST
RST
RST

RST
RST

SPACING

GNDGND

GNDGND

GNDGND
GNDGND

GNDGND
GNDGND

SPACING_RULE_SET

4:1_SPACING

SPACING

GND
GND_AUDIO_CODEC

GND_SPKR_AMP1
GND_SPKR_AMP2

AGND_U3000
J2200_29_GND

J2200_36_GND
J2200_43_GND

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

BB_TRST_L
DBG_RST
DEBUG_RST_L
GSM_TXBURST_IND
JTAG_AP_TRST_L
RST_AP_1V8_L
RST_AP_L
GPIO_BB_RST_L
RST_BB_PMU_L
RST_BT_L
RST_DET_L
RST_GRAPE_L
RST_L63_L
RST_PMU_IN
RST_WLAN_L
SIMCRD_RST

UD881_RST
UD882_RST

18

16

15
15
15

4

10 36

4

25 26 30
26

5

D

C

B

I64

I67

I68

I69

I70

I71

I72

I73

I74

I76

I75

I223

A

I222

I227

0.6V

0.6V

0.6V

0.6V

0.6V

0.6V

0.6V

0.6V

4.6V

4.6V

1.8V

3.55V

PP_PWR

PP_PWR
PP_PWR
PP_PWR

PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR

PP_PWR
PP_PWR

PP_PWR

PWR6V

PWR
PWR
PWR

PWR
PWR
PWR
PWR
PWR
PWR
PWR

PWR
PWR

PWR

PPVBUS_USB_EMI

PPVREF_DDR0_CA
PPVREF_DDR0_DQ
PPVREF_DDR1_CA

PPVREF_DDR1_DQ
PPVREF_DDR2_CA
PPVREF_DDR2_DQ
PPVREF_DDR3_CA
PPVREF_DDR3_DQ

DAC_AP_VREF
BATT_POS_RC

BATT_VCC_WLAN
PP_WLAN_VDDIO_1V8

LDO10

23 34

11 38
11 38
11 38

11 38
12 38
12 38
12 38
12 38
7
29

27
27

18 29

6 3

SYNC_MASTER=MIKE

PAGE TITLE

CONSTRAINTS: POWER / GND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/30/2011

DRAWING NUMBER

051-9385

REVISION

BRANCH

PAGE

154 OF 154

SHEET

39 OF 39

124578

A.0.0

SIZE

A

D