Analog Devices SMP08FP, SMP08FS Datasheet

Octal Sample-and-Hold

a

FEATURES
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost

APPLICATIONS
Multiple Path Timing Deskew for ATE
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control

with Multiplexed Input

SMP08*

FUNCTIONAL BLOCK DIAGRAM

INPUT

3

(LSB)

A

SW

(MSB)

C

B

1 OF 8 DECODER

SW

SW

SW

SW

INH

691011

SW

SW

8
16
13

14

15

12

1

5

2

DGND
V

DD

CH0OUT

CH1OUT

CH2OUT

OUT

CH

3

OUT

CH

4

CH5OUT

CH6OUT

GENERAL DESCRIPTION

The SMP08 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP08 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 7 microseconds. The SMP08’s output
swing includes the negative supply in both single and dual sup­ply operation.

The SMP08 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP08 ideal for
calibration requirements that have previously required an
ASIC, or high cost multiple D/A converters.

*Protected by U.S. Patent No. 4,739,281.

SW

HOLD CAPS

(INTERNAL)

4

OUT

CH

7

V

7

SS

SMP08

The SMP08 is also ideally suited for a wide variety of sample­and-hold applications including amplifier offset or VCA gain
adjustments. One or more SMP08s can be used with single or
multiple DACs to provide multiple set points within a system.

The SMP08 offers significant cost and size reduction over dis­crete designs. It is available in a 16-pin plastic DIP, or surface­mount SOIC package.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

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Fax: [phone] © Analog Devices, Inc., 1996

SMP08–SPECIFICATIONS

(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units

Linearity Error –3 V ≤ V
Buffer Offset Voltage V

Hold Step V
Droop Rate ∆V

Output Source Current I
Output Sink Current I
Output Voltage Range RL = 20 kΩ –3.0 +3.0 V

LOGIC CHARACTERISTICS

Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I

DYNAMIC PERFORMANCE

Acquisition Time

3

2

Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t
Slew Rate SR 3 V/µs
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk –3 V to +3 V Step –72 dB

SUPPLY CHARACTERISTICS

Power Supply Rejection Ratio PSRR V
Supply Current I

OS

HS

CH
SOURCE
SINK

INH
INL

IN

t

AQ
H
CH
DCS
IR

DD

unless otherwise noted)

≤ +3 V 0.01 %

TA = +25°C, VIN = 0 V 2.5 10 mV
–40°C ≤ T
VIN = 0 V, TA = +25°C to +85°C 2.5 4 mV
V

/∆tTA = +25°C, VIN = 0 V 2 20 mV/s

VIN = 0 V
VIN = 0 V

VIN = 2.4 V 0.5 1 µA

TA = +25°C, –3 V to +3 V to 0.1% 3.6 7 µs
To ±1 mV of Final Value 1 µs

TA = +25°C 4 7.5 mA
–40°C ≤ TA ≤ +85°C 5 9.5 mA

IN

≤ +85°C, VIN = 0 V 3.5 20 mV

A

= 0 V, TA = –40°C5mV

IN

1
1

1.2 mA

0.5 mA

2.4 V

0.8 V

90 ns
45 ns
90 ns

= ±5 V to ±6 V 60 75 dB

S

(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units

Linearity Error 60 mV ≤ V
Buffer Offset Voltage V

Hold Step V
Droop Rate ∆V

Output Source Current I
Output Sink Current I
Output Voltage Range R

LOGIC CHARACTERISTICS

Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I

DYNAMIC PERFORMANCE

Acquisition Time

3

2

Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t
Slew Rate SR R
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk 0 V to 10 V Step –72 dB

SUPPLY CHARACTERISTICS

Power Supply Rejection Ratio PSRR 10.8 V ≤ V
Supply Current I

NOTES

1

Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels.

2

All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

3

This parameter is guaranteed without test.

4

Slew rate is measured in the sample mode with 0 V to 10 V step from 20% to 80%.

Specifications subject to change without notice.

OS

HS

CH
SOURCE
SINK

INH
INL

IN

t

AQ

H
CH
DCS
IR

DD

unless otherwise noted)

≤ 10 V 0.01 %

TA = +25°C, VIN = 6 V 2.5 10 mV
–40°C ≤ T
VIN = 6 V, TA = +25°C to +85°C 2.5 4 mV
V

IN

/∆tTA = +25°C, VIN = 6 V 2 20 mV/s

VIN = 6 V
VIN = 6 V

L

RL = 10 kΩ 0.06 9.5 V

VIN = 2.4 V 0.5 1 µA

TA = +25°C, 0 V to 10 V to 0.1% 3.5 4.25 µs
–40°C ≤ T
To ±1 mV of Final Value 1 µs

L

TA = +25°C 6.0 8.0 mA
–40°C ≤ TA ≤ +85°C 8.0 10.0 mA

IN

≤ +85°C, VIN = 6 V 3.5 20 mV

A

= 6 V, TA = –40°C5mV

1
1

1.2 mA

0.5 mA

= 20 kΩ 0.06 10.0 V

2.4 V

0.8 V

≤ +85°C 3.75 6.00 µs

A

90 ns
45 ns

= 20 kΩ

4

≤ 13.2 V 60 75 dB

DD

34 V/µs

90 ns

–2–

REV. D

SMP08

ABSOLUTE MAXIMUM RATINGS

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V

DD

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

LOGIC

VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

OUT

DD
DD
DD

Model Range Description Option

SMP08FP –40°C to +85°C Plastic DIP N-16
SMP08FS –40°C to +85°C SO-16 R-16A

ORDERING GUIDE

Temperature Package Package

Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

(Not Short-Circuit Protected)

Operating Temperature Range

PIN CONNECTIONS

FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

Package Type uJA* u

JC

Units

16-Pin Plastic DIP (P) 76 33 °C/W
16-Pin SOIC (S) 92 27 °C/W

*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device

in socket for plastic DIP package; θJA is specified for device soldered to printed
circuit board for SO package.

CH4OUT
CH6OUT

INPUT

OUT

CH

7

CH

OUT

5

INH
V

DGND

SS

1
2
3
4
5

(Not to Scale)

6
7
8

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP08 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

SMP08

TOP VIEW

WARNING!

V

16

DD

OUT

CH

15

2

CH

OUT

14

1

CH

OUT

13

0

CH

OUT

12

3

11

A CONTROL

10

B CONTROL

9

C CONTROL

ESD SENSITIVE DEVICE

REV. D

–3–