Octal Sample-and-Hold
a
FEATURES
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for ATE
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
with Multiplexed Input
SMP08*
FUNCTIONAL BLOCK DIAGRAM
INPUT
3
(LSB)
A
SW
(MSB)
C
B
1 OF 8 DECODER
SW
SW
SW
SW
INH
691011
SW
SW
8
16
13
14
15
12
1
5
2
DGND
V
DD
CH0OUT
CH1OUT
CH2OUT
OUT
CH
3
OUT
CH
4
CH5OUT
CH6OUT
GENERAL DESCRIPTION
The SMP08 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP08 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 7 microseconds. The SMP08’s output
swing includes the negative supply in both single and dual supply operation.
The SMP08 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP08 ideal for
calibration requirements that have previously required an
ASIC, or high cost multiple D/A converters.
*Protected by U.S. Patent No. 4,739,281.
SW
HOLD CAPS
(INTERNAL)
4
OUT
CH
7
V
7
SS
SMP08
The SMP08 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain
adjustments. One or more SMP08s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP08 offers significant cost and size reduction over discrete designs. It is available in a 16-pin plastic DIP, or surfacemount SOIC package.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1996
SMP08–SPECIFICATIONS
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units
Linearity Error –3 V ≤ V
Buffer Offset Voltage V
Hold Step V
Droop Rate ∆V
Output Source Current I
Output Sink Current I
Output Voltage Range RL = 20 kΩ –3.0 +3.0 V
LOGIC CHARACTERISTICS
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
DYNAMIC PERFORMANCE
Acquisition Time
3
2
Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t
Slew Rate SR 3 V/µs
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk –3 V to +3 V Step –72 dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio PSRR V
Supply Current I
OS
HS
CH
SOURCE
SINK
INH
INL
IN
t
AQ
H
CH
DCS
IR
DD
unless otherwise noted)
≤ +3 V 0.01 %
TA = +25°C, VIN = 0 V 2.5 10 mV
–40°C ≤ T
VIN = 0 V, TA = +25°C to +85°C 2.5 4 mV
V
/∆tTA = +25°C, VIN = 0 V 2 20 mV/s
VIN = 0 V
VIN = 0 V
VIN = 2.4 V 0.5 1 µA
TA = +25°C, –3 V to +3 V to 0.1% 3.6 7 µs
To ±1 mV of Final Value 1 µs
TA = +25°C 4 7.5 mA
–40°C ≤ TA ≤ +85°C 5 9.5 mA
IN
≤ +85°C, VIN = 0 V 3.5 20 mV
A
= 0 V, TA = –40°C5mV
IN
1
1
1.2 mA
0.5 mA
2.4 V
0.8 V
90 ns
45 ns
90 ns
= ±5 V to ±6 V 60 75 dB
S
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units
Linearity Error 60 mV ≤ V
Buffer Offset Voltage V
Hold Step V
Droop Rate ∆V
Output Source Current I
Output Sink Current I
Output Voltage Range R
LOGIC CHARACTERISTICS
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
DYNAMIC PERFORMANCE
Acquisition Time
3
2
Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t
Slew Rate SR R
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk 0 V to 10 V Step –72 dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio PSRR 10.8 V ≤ V
Supply Current I
NOTES
1
Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels.
2
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with 0 V to 10 V step from 20% to 80%.
Specifications subject to change without notice.
OS
HS
CH
SOURCE
SINK
INH
INL
IN
t
AQ
H
CH
DCS
IR
DD
unless otherwise noted)
≤ 10 V 0.01 %
TA = +25°C, VIN = 6 V 2.5 10 mV
–40°C ≤ T
VIN = 6 V, TA = +25°C to +85°C 2.5 4 mV
V
IN
/∆tTA = +25°C, VIN = 6 V 2 20 mV/s
VIN = 6 V
VIN = 6 V
L
RL = 10 kΩ 0.06 9.5 V
VIN = 2.4 V 0.5 1 µA
TA = +25°C, 0 V to 10 V to 0.1% 3.5 4.25 µs
–40°C ≤ T
To ±1 mV of Final Value 1 µs
L
TA = +25°C 6.0 8.0 mA
–40°C ≤ TA ≤ +85°C 8.0 10.0 mA
IN
≤ +85°C, VIN = 6 V 3.5 20 mV
A
= 6 V, TA = –40°C5mV
1
1
1.2 mA
0.5 mA
= 20 kΩ 0.06 10.0 V
2.4 V
0.8 V
≤ +85°C 3.75 6.00 µs
A
90 ns
45 ns
= 20 kΩ
4
≤ 13.2 V 60 75 dB
DD
34 V/µs
90 ns
–2–
REV. D
SMP08
ABSOLUTE MAXIMUM RATINGS
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
DD
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
LOGIC
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V
OUT
DD
DD
DD
Model Range Description Option
SMP08FP –40°C to +85°C Plastic DIP N-16
SMP08FS –40°C to +85°C SO-16 R-16A
ORDERING GUIDE
Temperature Package Package
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
(Not Short-Circuit Protected)
Operating Temperature Range
PIN CONNECTIONS
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Package Type uJA* u
JC
Units
16-Pin Plastic DIP (P) 76 33 °C/W
16-Pin SOIC (S) 92 27 °C/W
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for plastic DIP package; θJA is specified for device soldered to printed
circuit board for SO package.
CH4OUT
CH6OUT
INPUT
OUT
CH
7
CH
OUT
5
INH
V
DGND
SS
1
2
3
4
5
(Not to Scale)
6
7
8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP08 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
SMP08
TOP VIEW
WARNING!
V
16
DD
OUT
CH
15
2
CH
OUT
14
1
CH
OUT
13
0
CH
OUT
12
3
11
A CONTROL
10
B CONTROL
9
C CONTROL
ESD SENSITIVE DEVICE
REV. D
–3–
INPUT VOLTAGE – Volts
DROOP RATE – mV/s
1800
1200
600
01 10
23456789
1600
1400
1000
800
VDD = +12V
VSS = 0V
T
A
= +125°C
NO LOAD
VDD – Volts
SLEW RATE – V/µs
7
6
3
10 11 18
12 13 14 15 16 17
5
4
VSS = 0V
T
A
= +25°C
NO LOAD
–SR
+SR
INPUT VOLTAGE – Volts
OFFSET VOLTAGE – mV
4
–10
01 10
23456789
2
0
–2
–4
–6
–8
VDD = +12V
VSS = 0V
T
A
= –40°C
NO LOAD
RL =
∞
RL = 20kΩ
RL = 10kΩ
SMP08–Typical Performance Characteristics
1000
VDD = +12V
= 0V
V
SS
V
= +5V
IN
100
= 10kΩ
R
L
10
DROOP RATE – mV/s
1
0.1
–55 –35 125–15 5 25 65 85 10545
TEMPERATURE – °C
Figure 1. Droop Rate vs. Temperature
2
1
0
–1
–2
HOLD STEP – mV
VDD = +12V
VSS = 0V
T
= +25°C
A
NO LOAD
3
2
1
0
–1
DROOP RATE – mV/s
VDD = +12V
= 0V
V
SS
–2
T
= +25°C
A
NO LOAD
–3
234 567 89
01 10
INPUT VOLTAGE – Volts
Figure 2. Droop Rate vs. Input Voltage
2
VDD = +12V
= 0V
V
SS
1
V
= +5V
IN
NO LOAD
0
–1
–2
HOLD STEP – mV
Figure 3. Droop Rate vs. Input Voltage
–3
–4
23456789
01 10
INPUT VOLTAGE – Volts
Figure 4. Hold Step vs. Input Voltage
4
2
RL =
0
–2
–4
–6
OFFSET VOLTAGE – mV
–8
–10
01 10
∞
RL = 20kΩ
RL = 10kΩ
23456789
INPUT VOLTAGE – Volts
Figure 7. Offset Voltage vs. Input
Voltage
VDD = +12V
VSS = 0V
T
= +25°C
A
NO LOAD
–3
–4
–55 –35 85
–155 254565
TEMPERATURE – °C
Figure 5. Hold Step vs. Temperature
20
15
10
5
0
–5
–10
OFFSET VOLTAGE – mV
–15
–20
23456789
01 10
RL = 10kΩ
INPUT VOLTAGE – Volts
VDD = +12V
VSS = 0V
T
= +85°C
A
NO LOAD
RL =
RL = 20kΩ
∞
Figure 8. Offset Voltage vs. Input
Voltage
–4–
Figure 6. Slew Rate vs. V
DD
Figure 9. Offset Voltage vs. Input
Voltage
REV. D
FREQUENCY – Hz
90
80
0
10 100 1M1k 10k 100k
70
60
20
50
40
30
10
REJECTION RATIO – dB
VDD = +12V
VSS = 0V
V
IN
= +6V
T
A
= +25°C
NO LOAD
+PSRR
–PSRR
Typical Performance Characteristics–SMP08
FREQUENCY – Hz
OUTPUT IMPEDANCE – Ω
35
30
0
10 100 1M1k 10k 100k
25
20
15
10
5
VDD = +12V
VSS = 0V
T
A
= +25°C
NO LOAD
0
–1
–2
–3
–4
–5
–6
OFFSET VOLTAGE – mV
–7
–8
–55 –35 125
–15 5 25 65 85 10545
TEMPERATURE – °C
VDD = +12V
VSS = 0V
= +5V
V
IN
R
= 10kΩ
L
Figure 10. Offset Voltage vs.
Temperature
2
1
0
–1
–2
GAIN – dB
–3
–4
–5
100 1k 10M10k 100k 1M
FREQUENCY – Hz
GAIN
14
VSS = 0V
NO LOAD
12
10
8
6
SUPPLY CURRENT – mA
4
2
46 18
8 10121416
+85°C
+25°C
–40°C
VDD – Volts
Figure 11. Supply Current vs. V
= 0V
= +25°C
PHASE
90
45
0
–45
–90
–135
PHASE SHIFT – Degrees
–180
–225
VDD = +12V
V
SS
T
A
NO LOAD
DD
Figure 12. Sample Mode Power
Supply Rejection
REV. D
Figure 13. Gain, Phase Shift vs.
Frequency
15
12
9
6
3
PEAK-TO-PEAK OUTPUT – Volts
0
10k 100k 10M
Figure 15. Maximum Output Voltage
vs. Frequency
FREQUENCY – Hz
VDD = +6V
VSS = –6V
T
NO LOAD
1M
= +25°C
A
Figure 14. Output Impedance vs.
Frequency
60
50
= +25°C
A
+PSRR
SS
–PSRR
1k 10k 100k
FREQUENCY – Hz
40
VDD = +12V
30
VSS = 0V
T
20
NO LOAD
HOLD CAPACITORS
10
REFERENCED TO V
REJECTION RATIO – dB
0
–10
10 100 1M
Figure 16. Hold Mode Power Supply
Rejection
–5–
SMP08
R2
10kΩ
R2
10kΩ
R3
6.5kΩ
1
2
3
4
5
R2
10kΩ
R2
10kΩ
6
7
8
Figure 17. Burn-In Circuit
R4
1kΩ
SMP08
V
CC
+15V
10Ω
16
15
14
13
12
11
10
9
D1
C1
10µF
+
10kΩ
C2
1µF
R2
R2
R2
R2
10kΩ
10kΩ
10kΩ
R1
APPLICATIONS INFORMATION
The SMP08, a multiplexed octal S/H, minimizes board space in
systems requiring cycled calibration or an array of control voltages. When used in conjunction with a low cost 16-bit D/A, the
SMP08 can easily be integrated into microprocessor based systems. Since the SMP08 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP08 has an internally regulated TTL supply so that TTL/
CMOS compatibility is maintained over the full supply range.
See Figure 18 for channel decode address information.
POWER SUPPLIES
The SMP08 is capable of operating with either single or dual
supplies, over a voltage range of 7 volts to 15 volts. Based on the
supply voltages chosen, V
and VSS establish the input and
DD
output voltage range, which is:
(V
+0.06 V) ≤ V
SS
OUT/IN
≤ (V
DD
–2 V)
Note that several specifications, including acquisition time, offset and output voltage compliance, will degrade for supply voltages of less than 7 V.
If split supplies are used, the negative supply should be bypassed
with a 0.1 µF capacitor in parallel with a 10 µF to ground. The
internal hold capacitors are connected to this supply pin and any
noise will appear at the outputs.
In single supply applications, it is extremely important that the
V
(negative supply) pin is connected to a clean ground. The
SS
hold capacitors are internally tied to the V
(negative) rail. Any
SS
ground noise or disturbance will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise performance. The analog and digital ground traces on the circuit
board should be physically separated to reduce digital switching
noise from entering the analog circuitry.
POWER SUPPLY SEQUENCING
VDD should be applied to the SMP08 before the logic input signals. The SMP08 has been designed to be immune to latchup,
but standard precautions should still be taken.
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The buffer offset specification is 10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. The hold step (magnitude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset), is about 2.5 mV with little variation
over the full output voltage range, T
= +25°C to +85°C. The
A
droop rate of a held channel is 2 mV/s typical and 20 mV/s
maximum.
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA, over the full voltage
range, but have limited current sinking capability near V
. In
SS
split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 V from either supply.
On-chip SMP08 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capacitive loads up to 500 pF. However, since the SMP08’s
buffer outputs are not short-circuit protected, care should be
taken to avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pin 3)
The signal input should be driven from a low impedance voltage source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the
SMP08’s acquisition time characteristics are to be maintained.
As with all CMOS devices, all input voltages should be kept
within range of the supply rails (V
SS
< V
< VDD) to avoid the
IN
possibility of latchup. If single supply operation is desired, op
amps such as the OP183 or AD820 that have input and output
voltage compliances including ground, can be used to drive the
inputs. Split supplies, such as ±7.5 V, can be used with the
SMP08.
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW
and unused analog inputs connected to analog ground. For
connector-driven analog inputs that may become temporarily
disconnected, a resistor to V
, VSS or analog ground should
DD
be used with a value ranging from 200 kΩ to 1 MΩ.
–6–
REV. D
SMP08
DIGITAL
INPUTS
ADDRESS
WR
BUS
+12V
REF02
+5V
4
AV
V
REF
DAC8228
WR
ADDRESS
DECODE
CS
SMP08
13
CH
+12V
V
17
DD
V
OA
V
Z
GND
15
516
+12V
1
3
C
DGND
INH
3
A
11
B
10
9
8
6
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
16
7
0.1µF
0
14
CH
1
15
CH
2
12
CH
3
1
CH
4
5
CH
5
2
CH
6
4
CH
7
PIN 9CPIN 10BPIN 11APIN 6
CHANNEL DECODING
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
X
X
INH CH PIN
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
X
1
0
1
2
3
4
5
6
7
NONE
13
14
15
12
1
5
2
4
–
Figure 18. 8-Channel Multiplexed D/A Converter
Do not apply signals to the SMP08 with power off unless the
input current is limited to less than 10 mA.
TYPICAL APPLICATIONS
AN 8-CHANNEL MULTIPLEXED D/A CONVERTER
Figure 18 illustrates a typical demultiplexing function of the
SMP08. It is used to sample-and-hold eight different output
voltages corresponding to eight different digital codes from a
D/A converter. The SMP08’s droop rate of 20 mV/s requires a
refresh once every 500 ms, before the voltage drifts beyond
1/2 LSB accuracy (1 LSB of an 8-bit DAC is equivalent to
19.5 mV out of a full-scale voltage of 5 V). For a 10-bit DAC
the refresh rate must be less than 120 ms, and, for a 12-bit
system, 31 ms. This implementation is very cost effective compared to using multiple DACs as the number of output channels
increases.
REV. D
–7–
SMP08
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
18
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
9
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
16-Lead SOIC (Narrow Body)
(SO-16)
0.130
(3.30)
MIN
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
C2192–2–10/96
0.1574 (4.00)
0.1497 (5.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.3937 (10.00)
0.3859 (9.80)
16 9
PIN 1
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
0.2550 (6.20)
81
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
x 45°
–8–
PRINTED IN U.S.A.
REV. D
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