FEATURES
Low VOS: 75 V Max
Low V
Ultrastable vs. Time: 1.5 V/Month Max
Low Noise: 0.6 V p-p Max
Wide Input Voltage Range: 14 V
Wide Supply Voltage Range: 3 V to 18 V
Fits 725,108A/308A, 741, AD510 Sockets
125C Temperature-Tested Dice
APPLICATIONS
Wireless Base Station Control Circuits
Optical Network Control Circuits
Instrumentation
Sensors and Controls
Precision Filters
GENERAL DESCRIPTION
The OP07 has very low input offset voltage (75 µV max for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (±4 nA for the
OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offsets and high open-loop gain make the OP07 particularly useful for high gain instrumentation applications.
The wide input voltage range of ±13 V minimum combined with a
high CMRR of 106 dB (OP07E) and high input impedance provide high accuracy in the noninverting circuit configuration.
Excellent linearity and gain accuracy can be maintained even at
Drift: 1.3 V/C Max
OS
Thermocouples
RTDs
Strain Bridges
Shunt Current Measurements
Operational Amplifier
OP07
PIN CONNECTIONS
8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
high closed-loop gains. Stability of offsets and gain with time or
variations in temperature is excellent. The accuracy and stability
of the OP07, even at high gain, combined with the freedom
from external nulling have made the OP07 an industry standard
for instrumentation applications.
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range, and
the OP07C is specified over the –40°C to +85°C temperature range.
The OP07 is available in epoxy 8-lead PDIP and 8-lead SOIC. It
is a direct replacement for 725, 108A, and OP05 amplifiers;
741 types may be directly replaced by removing the 741’s nulling
potentiometer. For improved specifications, see the OP177 or
OP1177. For ceramic DIP and TO-99 packages and standard
micro circuit (SMD) versions, see the OP77.
V+
7
*NOTE
R2A AND R2B ARE
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY FOR
MINIMUM INPUT
OFFSET VOLTAGE.
NONINVERTING
INPUT
3
INVERTING
INPUT
2
R2A*
R1A
Q21
Q22
Q7
Q23
Q24
4
V–
Q5
R3
R4
1
Q3 Q6
Q1
(OPTIONAL
NULL)
Q8
R2B*
8
R1B
Q4
Q2
Q27
Q26
Q25
C1
Q9
Q11
C3
R5
C2
Q13
Q10
Q12
Q17
Q14
Q16
Q15
R7
Q19
R9
OUTPUT
6
R10
Q20
Q18
R8
R6
Figure 1. Simplified Schematic
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
use, nor for any infringements of patents or other rights of third parties that
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2
Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 µV, refer to the typical performance characteristics. Parameter is sample tested.
3
Sample tested.
4
Guaranteed by design.
5
Guaranteed but not tested.
Specifications subject to change without notice.
–2–
REV. C
OP07
OP07C ELECTRICAL CHARACTERISTICS
(VS = 15 V, TA = 25C, unless otherwise noted.)
ParameterSymbolConditionsMinTypMaxUnit
INPUT CHARACTERISTICS
Input Offset Voltage
Long-Term VOS Stability
Input Offset CurrentI
Input Bias CurrentI
Input Noise Voltageen p-p0.1 Hz to 10 Hz
Input Noise Voltage Densitye
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2
Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 µV, refer to the typical performance characteristics. Parameter is sample tested.
Input Offset Voltage
Voltage Drift without External Trim2TCV
Voltage Drift with External Trim
Input Offset CurrentI
Input Offset Current DriftTCI
Input Bias CurrentI
Input Bias Current DriftTCI
1
V
OS
TCV
OS
B
OS
OSN
OS
B
RP = 20 kΩ0.31.3µV/°C
3
45130µV
0.31.3µV/°C
0.95.3nA
835pA/°C±1.5±5.5nA
1335pA/°C
Input Voltage RangeIVR±13±13.5V
Common-Mode Rejection RatioCMRRV
= ±13 V103123dB
CM
Power Supply Rejection RatioPSRRVS = ±3 V to ± 18 V732µV/V
Large Signal Voltage GainA
VO
RL ≥ 2 kΩ, VO = ±10 V180450V/mV
OUTPUT CHARACTERISTICS
Output Voltage SwingV
NOTES
1
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Input Offset Voltage
Voltage Drift without External Trim
Voltage Drift with External Trim
Input Offset CurrentI
Input Offset Current DriftTCI
Input Bias CurrentI
Input Bias Current DriftTCI
1
V
OS
2
TCV
TCV
OS
B
OS
OSN
OS
B
RP = 20 kΩ0.41.8µV/°C
3
85250µV
0.51.8µV/°C
1.68.0nA
1250pA/°C±2.2±9.0nA
1850pA/°C
Input Voltage RangeIVR±13±13.5V
Common-Mode Rejection RatioCMRRV
Power Supply Rejection RatioPSRRV
Large Signal Voltage GainA
VO
= ±13 V97120dB
CM
= ±3 V to ± 18 V1051µV/V
S
RL ≥ 2 kΩ, VO = ±10 V100400V/mV
OUTPUT CHARACTERISTICS
Output Voltage SwingV
NOTES
1
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2
Guaranteed by design.
3
Sample tested.
Specifications subject to change without notice.
O
RL ≥ 10 kΩ±11±12.6V
–4–
REV. C
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