Analog Devices DA1845JST, DA1845JP-REEL, DA1845JP Datasheet
a
Parallel-Port 16-Bit
SoundPort® Stereo Codec
AD1845
FEATURES
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Microsoft® and Windows® Sound System Compatible
MPC Level-2+ Compliant Mixing
16 mA Bus Drive Capability
Supports Two DMA Channels for Full Duplex Operation
On-Chip Capture and Playback FIFOs
Advanced Power-Down Modes
Programmable Gain and Attenuation
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Pin Compatible with AD1848, AD1846, CS4248, CS4231
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT OVERVIEW
The Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
integrated circuit. The AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
applications. The codec includes stereo audio converters, com-
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1997
(Continued on Page 9)
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
plete on-chip filtering, MPC Level-2 compliant analog mixing,
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced powerdown modes. It provides a direct, byte-wide interface to both
ISA (“AT”) and EISA computer buses for simplified implementation on a computer motherboard or add-in card.
The AD1845 SoundPort Stereo Codec supports a DMA request/grant architecture for transferring data with the host computer bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
Two input control lines support mixed direct and indirect addressing of thirty-seven internal control registers over this asynchronous interface. The AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to capture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
FUNCTIONAL BLOCK DIAGRAM
GAM = GAIN
ATTENTUATE
MUTE
DIGITAL MIX
ATTENUATE
VARIABLE SAMPLE
FREQUENCY GENERATOR
MUTE
M_IN
L_AUX2
R_AUX2
L_MIC
R_MIC
ANALOG SUPPLY
0 dB/
20 dB
GAM
S
SD A/D
CONVERTER
GAIN
CONTROL
REGISTERS
HOST DMA
INTERRUPT
REFERENCE
L_OUT
M_OUT
R_OUT
L_LINE
R_LINE
L_AUX1
R_AUX1
AD1845
DIGITAL SUPPLY CLOCK SOURCE
POWER DOWN RESET
DIGITAL
ANALOG
BUS DRIVER
CONTROL
GAIN
L
R
L
R
EXTERNAL
CONTROL
V
REF
V
REF_F
GAM GAM
GAM GAM
SD A/D
CONVERTER
ATTENUATE
MUTE
SD D/A
CONVERTER
ATTENUATE
MUTE
SD D/A
CONVERTER
m-LAW
A-LAW
LINEAR
FIFO
m-LAW
A-LAW
LINEAR
CS
RD
WR
PLAYBACK ACK
CAPTURE ACK
PLAYBACK REQ
CAPTURE REQ
ADR1:0
DATA7:0
FIFO
P
A
R
A
L
L
E
L
P
O
R
T
S S
S S S
S
S
S
M
U
X
AD1845–SPECIFICA TIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature 25 °C
Digital Supply (V
DD
) 5.0 V
Analog Supply (V
CC
) 5.0 V
Word Rate (F
S
) 48 kHz
Input Signal 1008 Hz
Analog Output Passband 20 Hz to 20 kHz
ADC FFT Size 2048
DAC FFT Size 8192
V
IH
5V
V
IL
0V
ANALOG INPUT
Min Typ Max Units
Input Voltage (RMS Values Assume Sine Wave Input)
Line 1 V rms
2.55 2.83 3.35 V p-p
MIC with +20 dB Gain (MGE = 1) 0.1 V rms
0.255 0.283 0.335 V p-p
MIC with 0 dB Gain (MGE = 0) 1 V rms
2.55 2.83 3.35 V p-p
Input Impedance* 10 17 kΩ
Input Capacitance 15 pF
PROGRAMMABLE GAIN AMPLIFIER–ADC
Min Typ Max Units
Step Size (All Steps Tested)
(0 dB to 22.5 dB) 0.7 1.5 1.9 dB
PGA Gain Range Span 21.5 22.5 23.5 dB
AUXILIARY LINE, MONO, AND MICROPHONE INPUT ANALOG GAIN/AMPLIFIERS/ATTENUATORS
Min Typ Max Units
Step Size : AUX1, AUX2, LINE, MIC (All Steps Tested)
(+12 dB to –30 dB) 1.25 1.5 1.75 dB
(–31.5 dB to –34.5 dB) 1 1.5 2.0 dB
Step Size: M_IN (All Steps Tested)
(0 dB to –39 dB) 2.5 3.0 3.6 dB
(–42 dB to –45 dB) 2.2 3.0 3.85 dB
Input Gain/Attenuation Range: AUX1, AUX2, LINE, MIC 45.0 46.5 49.0 dB
Input Gain/Attenuation Range: M_IN 42 45 49 dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Min Max Units
Passband 0 0.4 × F
S
Hz
Passband Ripple ±0.1 dB
Transition Band 0.4 × F
S
0.6 × F
S
Hz
Stopband 0.6 × F
S
∞ Hz
Stopband Rejection 74 dB
Group Delay 15/F
S
Group Delay Variation Over Passband 0.0 µs
*Guaranteed, not tested.
DAC Test Conditions
Calibrated
0 dB Relative to Full Scale
16-Bit Linear Mode
10 kΩ Output Load
Mute Off, OL = 0
ADC Test Conditions
Calibrated
0 dB Gain
–1.0 dB Relative to Full Scale
Line Input
16-Bit Linear Mode
REV. C
–2–
ANALOG-TO-DIGITAL CONVERTERS
Min Typ Max Units
Resolution 16 Bits
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) 73 81 dB
THD+N (Referenced to Full Scale) 0.025 %
–76 –72 dB
Signal-to-Intermodulation Distortion 85 dB
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –90 –80 dB
Line to MIC (Input LINE, Ground and Select MIC, Read ADC) –90 –80 dB
Line to AUX1 –90 –80 dB
Line to AUX2 –90 –80 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) –18.5 +10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.9 dB
ADC Offset Error 10 mV
DIGITAL-TO-ANALOG CONVERTERS
Min Typ Max Units
Resolution 16 Bits
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) 74 82 dB
THD+N (Referenced to Full Scale) 0.032 %
–78 –70 dB
Signal-to-Intermodulation Distortion 90 dB
Gain Error (Full-Scale Span Relative to Nominal Output Voltage) –14.5 +10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.6 dB
DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) –80 dB
Total Out-of-Band Energy (Measured from 0.6 × F
S
to 100 kHz)* –50 dB
Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)* –70 dB
DAC ATTENUATOR
Min Typ Max Units
Step Size (0 dB to –22.5 dB) 1.3 1.5 1.7 dB
Step Size (–22.5 dB to –94.5 dB)* 1.0 1.5 2.0 dB
Output Attenuation Range Span* 93.5 94.5 95.5 dB
ANALOG OUTPUT
Min Typ Max Units
Full-Scale Output Voltage
OL = 0 1.7 2.0 2.2 V p-p
OL = 1 2.4 2.83 3.11 V p-p
Output Impedance* 600 Ω
External Load Impedance 10 kΩ
Output Capacitance* 15 pF
External Load Capacitance 100 pF
V
REF
2.05 2.25 2.60 V
V
REF
Current Drive 100 µA
V
REF
Output Impedance 4kΩ
Mute Attenuation of 0 dB Fundamental* (L_OUT, R_OUT, M_OUT) –80 dB
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)* ±5mV
*Guaranteed, not tested.
AD1845
–3–
REV. C
AD1845
–4–
REV. C
SYSTEM SPECIFICATIONS
Min Typ Max Units
System Frequency Response Ripple (Line In to Line Out)* 1.0 dB
Differential Nonlinearity* ± 1 LSB
Phase Linearity Deviation* 5 Degrees
STATIC DIGITAL SPECIFICATIONS
Min Max Units
High Level Input Voltage (V
IH
)
Digital Inputs 2.4 V
XTAL1I 2.4 V
Low Level Input Voltage (V
IL
) 0.8 V
High Level Output Voltage (V
OH
) IOH = –2 mA 2.4 V
Low Level Output Voltage (V
OL
) IOL = 2 mA 0.4 V
Input Leakage Current –10 10 µA
Output Leakage Current –10 10 µA
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE, VDD = VCC = 5.0 V)
Min Max Units
WR/RD Strobe Width (t
STW
) 100 ns
WR/RD Rising to WR/RD Falling (t
BWND
)80ns
Write Data Setup to
WR Rising (t
WDSU
)10ns
RD Falling to Valid Read Data (t
RDDV
)40ns
CS Setup to WR/RD Falling (t
CSSU
)10ns
CS Hold from WR/RD Rising (t
CSHD
)0ns
Adr Setup to
WR/RD Falling (t
ADSU
)10ns
Adr Hold from
WR/RD Rising (t
ADHD
)10ns
DAK Rising to WR/RD Falling (t
SUDK1
)20ns
DAK Falling to WR/RD Rising (t
SUDK2
)0ns
DAK Setup to WR/RD Falling (t
DKSU
)10ns
Data Hold from
RD Rising (t
DHD1
)20ns
Data Hold from
WR Rising (t
DHD2
)15ns
DRQ Hold from
WR/RD Falling (t
DRHD
)25ns
DAK Hold from WR Rising (t
DKHDa
)10ns
DAK Hold from RD Rising (t
DKHDb
) 10 ns
DBEN/DBDIR Delay from WR/RD Falling (t
DBDL
) 30 ns
PWRDWN and RESET Low Pulsewidth 300 ns
*Guaranteed, not tested.
POWER SUPPLY
Min Typ Max Units
Power Supply Range–Digital and Analog 4.75 5.25 V
Power Supply Current 130 mA
Analog Supply Current 45 mA
Digital Supply Current 85 mA
Power Dissipation
(Current × Nominal Supplies) 650 mW
Power-Down Supply Current 2mA
Reset Supply Current 2mA
Total Power-Down Supply Current 30 mA
Standby Supply Current 36 mA
Mixer Power-Down Supply Current 70 mA
Mixer Only Supply Current 52 mA
ADC Power-Down Supply Current 80 mA
DAC Power-Down Supply Current 85 mA
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, both ADCs and DACs) 40 dB
CLOCK SPECIFICATIONS*
Min Max Units
Input Clock Frequency 33 MHz
Recommended Clock Duty Cycle 10 90 %
Power Up Initialization Time 512 ms
*Guaranteed, not tested.
Specifications subject to change without notice.
AD1845
REV. C
–5–
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
1
AD1845JP 0°C to +70°C 68-Lead PLCC P-68A
AD1845JP-REEL
2
0°C to +70°C 68-Lead PLCC P-68A
AD1845JST 0°C to +70°C 100-Lead TQFP ST-100
NOTES
1
P = Plastic Leaded Chip Carrier; ST = Thin Quad Flatpack.
2
13" Reel, multiples of 250 pcs.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
T
AMB
= T
CASE
– (PD × θCA)
T
CASE
= Case Temperature in °C
PD = Power Dissipation in W
θ
CA
= Thermal Resistance (Case-to-Ambient)
θ
JA
= Thermal Resistance (Junction-to-Ambient)
θ
JC
= Thermal Resistance (Junction-to-Case)
Package u
JA
u
JC
u
CA
PLCC 38°C/W 8°C/W 30°C/W
TQFP 44°C/W 8 °C/W 93°C/W
ABSOLUTE MAXIMUM RATINGS*
Min Max Units
Power Supplies
Digital (V
DD
) –0.3 6.0 V
Analog (V
CC
) –0.3 6.0 V
Input Current
(Except Supply Pins) ±10.0 mA
Analog Input Voltage (Signal Pins) –0.3 V
CC
+0.3 V
Digital Input Voltage (Signal Pins) –0.3 V
DD
+0.3 V
Ambient Temperature (Operating) 0 +70 °C
Storage Temperature –65 +150 °C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1845 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD1845
–6–
REV. C
PIN DESIGNATIONS
100
9998979695949392919089888786858483828180797877
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RD
CS
XCTL1
INT
XCTL0
NC
NC
V
DD
GNDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
M_OUT
M_IN
V
DD
GNDD
NC
NC
NC
26272829303132333435363738394041424344454647484950
AD1845
TOP VIEW
(Not to Scale)
NC = NO CONNECT
ADR0
NC
NC
NC
NC
CDAK
CDRQ
PDAK
PDRQ
V
DD
GNDD
XTAL1I
XTAL1O
V
DD
GNDD
XTAL2I
XTAL2O
PWRDWN
RESET
GNDD
NC
NC
NC
NC
R_FILT
ADR1
GNDD
VDDNCNCNCNCDATA0
DATA1
DATA2
DATA3
GNDD
VDDDATA4
DATA5
DATA6
DATA7NCNCNCNC
GNDD
DBEN
DBDIR
WR
NC
NC
R_LINE
R_MIC
L_MIC
L_LINE
NC
L_FILT
NC
V
REF
NC
NC
V
REF_F
NC
GNDA
V
CCVCC
GNDA
L_AUX2
L_AUX1
L_OUT
R_OUT
R_AUX1
R_AUX2
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RD
CS
XCTL1
INT
XCTL0
NC
V
DD
GNDD
NC
NC
NC
NC
NC
M_OUT
M_IN
V
DD
GNDD
2728293031323334353637383940414243
AD1845
987654321
68676665646362
61
TOP VIEW
(Not to Scale)
NC = NO CONNECT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ADR0
CDAK
CDRQ
PDAK
PDRQ
V
DD
GNDD
XTAL1I
XTAL1O
V
DD
GNDD
XTAL2I
XTAL2O
PWRDWN
RESET
GNDD
R_FILT
ADR1
GNDD
VDDDATA0
DATA1
DATA2
DATA3
GNDD
VDDDATA4
DATA5
DATA6
DATA7
GNDD
DBEN
DBDIR
WR
R_LINE
R_MIC
L_MIC
L_LINE
L_FILT
V
REF
V
REF_F
GNDA
VCCV
CC
GNDA
L_AUX2
L_AUX1
L_OUT
R_OUT
R_AUX1
R_AUX2
100-Lead TQFP
68-Lead PLCC
AD1845
–7–
REV. C
PIN FUNCTION DESCRIPTIONS
Parallel Interface
Pin Name PLCC TQFP I/O Description
CDRQ 12 7 O Capture Data Request. The assertion of this signal HI indicates that the codec has a cap-
tured audio sample from the ADC ready for transfer. This signal will remain asserted
until the internal capture FIFO is empty.
CDAK 11 6 I Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD
cycle occurring is a DMA read from the capture buffer.
PDRQ 14 9 O Playback Data Request. The assertion of this signal HI indicates that the codec is ready
for more DAC playback data. The signal will remain asserted until the internal playback
FIFO is full.
PDAK 13 8 I Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR
cycle occurring is a DMA write to the playback buffer.
ADR1:0 9 & 10 100 & 1 I Codec Addresses. These address pins are asserted by the codec interface logic during a
control register/PIO access. The state of these address lines determine which direct
register is accessed.
RD 60 75 I Read Command Strobe. This active LO signal defines a read cycle from the codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from
the codec’s DMA sample registers.
WR 61 76 I Write Command Strobe. This active LO signal indicates a write cycle to the codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the
codec’s DMA sample registers.
CS 59 74 I AD1845 Chip Select. The codec will not respond to any control/PIO cycle accesses
unless this active LO signal is LO. This signal is ignored during DMA transfers.
DATA7:0 3–6 & 84–87 & I/O Data Bus. These pins transfer data and control information between the codec and
65–68 90–93 the host.
DBEN 63 78 O Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN = (WR or RD) and CS
For DMA cycles,
DBEN = (WR or RD) and (PDAK or CDAK).
DBDIR 62 77 O Data Bus Direction. This pin controls the direction of the data bus transceiver. HI
enables writes from the host bus to the AD1845; LO enables reads from the AD1845 to
the host bus. This signal is normally HI.
For control register/PIO cycles,
DBDIR =
RD and CS
For DMA cycles,
DBDIR = RD and (PDAK or CDAK).
AD1845
–8–
REV. C
Analog Signals
Pin Name PLCC TQFP I/O Description
L_LINE 30 31 I Left Line Input.
R_LINE 27 28 I Right Line Input.
L_MIC 29 30 I Left Microphone Input. This signal can be either line level or –20 dB from line level
(using the on-chip 20 dB gain block).
R_MIC 28 29 I Right Microphone Input. This signal can be either line level or –20 dB from line level
(using the on-chip 20 dB gain block).
L_AUX1 39 45 I Left Auxiliary #1 Line Input.
R_AUX1 42 48 I Right Auxiliary #1 Line Input.
L_AUX2 38 44 I Left Auxiliary #2 Line Input.
R_AUX2 43 49 I Right Auxiliary #2 Line Input.
L_OUT 40 46 O Left Line Output.
R_OUT 41 47 O Right Line Output.
M_IN 46 56 I Mono Input.
M_OUT 47 57 O Mono Output.
Miscellaneous
Pin Name PLCC TQFP I/O Description
XTAL1I 17 12 I 24.576 MHz Crystal #1 Input.
XTAL1O 18 13 O 24.576 MHz Crystal #1 Output.
XTAL2I 21 16 Not used on the AD1845.
XTAL2O 22 17 Not used on the AD1845.
PWRDWN 23 18 I Power Down Signal. Active LO places the AD1845 in its lowest power consumption
mode. All sections of the AD1845, including the digital interface, are shut down and
consume minimal power.
INT 57 72 O Host Interrupt Pin. A host interrupt is generated to notify the host that a specified
event has occurred.
XCTL1:0 58 & 56 73 & 71 O External Control. These signals reflect the current status of register bits inside the
AD1845. They can be used for signaling or to control external logic.
RESET 24 19 I Reset. Active LO resets all digital registers and filters, and resets all analog filters. Active
LO places the AD1845 in the lowest power consumption mode. XTAL1 is required to be
running during the minimum low pulsewidth of the reset signal.
V
REF
32 35 O Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-
shifting. V
REF
should not be used to sink or source current.
V
REF_F
33 38 I Voltage Reference Filter. Voltage reference filter point for external bypassing only.
L_FILT 31 33 I Left Channel Filter. This pin requires a 1.0 µF capacitor to analog ground for proper
operation.
R_FILT 26 25 I Right Channel Filter. This pin requires a 1.0 µF capacitor to analog ground for proper
operation.
NC 48–52, 2–5, 21–24 No Connect.
55 26, 27, 32, 34,
36, 37, 39,
50–53, 58–66,
69, 70, 80–83,
94–97
AD1845
–9–
REV. C
Power Supplies
Pin Name PLCC TQFP I/O Description
V
CC
35 & 36 41 & 42 I Analog Supply Voltage (+5 V).
GNDA 34 & 37 40 & 43 I Analog Ground.
V
DD
1, 7, 15, 10, 14, I Digital Supply Voltage (+5 V).
19, 45, 55, 68,
54 88, 98
GNDD 2, 8, 16, 11, 15, 20, I Digital Ground.
20, 25, 54, 67,
44, 53, 79, 89,
64 99
(Continued from page 1)
unsigned magnitude PCM linear data, and 8-bit µ-law or A-law
companded digital data.
The ∑∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantized noise are
removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters.
The AD1845 supports multiple low power and power-down
modes to support notebook and portable computing multimedia
applications. The ADC, DAC, and mixer paths can be suspended independently allowing the AD1845 to be used for
capture-only or playback-only, lessening power consumption
and extending battery life.
The AD1845 includes a variable sample frequency generator,
that allows the codec to instantaneously change sample rates
with a resolution of 1 Hz without “clicks” and “pops.” Additionally, ∑∆ quantization noise is kept out of the 20 kHz audio
band regardless of the chosen sample rate. The codec uses the
variable sample frequency generator to derive all internal clocks
from a single external crystal or clock source.
Expanded Mode (MODE2)
MODE1 is the initial state of the AD1845. In this state the
AD1845 appears as an AD1848 compatible device. To access
the expanded modes of operation on the AD1845, the MODE2
bit should be set in the Miscellaneous Information Control
Register. When this bit is set to one, 16 additional indirect
registers can be addressed allowing the user to access the
AD1845’s expanded features. The AD1845 can return to
MODE1 operation by clearing the MODE2 bit. In both
MODE1 and MODE2, the capture and playback FIFOs are
active to prevent data loss.
The additional MODE2 functions are:
1. Full-Duplex DMA support.
2. MIC input mixer, mute and volume control.
3. Mono output with mute control.
4. Mono input with mixer volume control.
5. Software controlled advanced power-down modes.
6. Programmable sample rates from 4kHz to 50 kHz in 1 Hz
increments.
ADDRESS
DECODE
CS
A1
A0
WR
RD
DATA7:0
DBDIR
DBEN
PDRQ
CDRQ
PDAK
CDAK
INT
AD1845
18
AEN
SA19:2
SA1
SA0
IOWC
IORC
DATA7:0
DRQ <X>
DRQ <Y>
DAK <X>
DAK <Y>
IRQ <Z>
8
8
G
74_245
BA
DIR
S
A
B
U
S
I
Figure 1. Interface to ISA Bus
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 80dB
over the 20 kHz audio band. Sample rates from 4 kHz to 50kHz
are supported from a single external crystal or clock source.
The AD1845 has built-in 8/16 mA (user selectable) bus drivers.
If 24 mA drive capability is required, the AD1845 generates
enable and direction controls for IC bus buffers such as the
74
245.
The codec includes a stereo pair of ∑∆ analog-to-digital converters and a stereo pair of ∑∆ digital-to-analog converters. The
AD1845 mixer surpasses MPC Level-2 recommendations.
Inputs to the ADC can be selected from four stereo pairs of
analog signals: line (LINE), microphone (MIC), auxiliary line
#1 (AUX1), and post-mixed DAC output. A software-controlled programmable gain stage allows independent gain for
each channel going into the ADC. In addition, the analog mixer
allows the mono input (M_IN), MIC, AUX1, LINE and auxiliary line #2 (AUX2) signals to be mixed with the DACs’ output.
The ADCs’ output can be digitally mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs is available over a
byte-wide bidirectional interface that also supports 16-bit digital
input to the DACs and control information. The AD1845 can
accept and generate 16-bit twos complement PCM linear digital
data in both little endian or big endian byte ordering, 8-bit
AD1845
–10–
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Digital Mixing
Stereo digital output from the ADCs can be digitally mixed with
the input to the DACs. Digital output from the ADCs going out
of the data port is unaffected by the digital mix. Along the
digital mix datapath, the 16-bit linear output from the ADCs
is attenuated by an amount specified with control bits. Both
channels of the digital mix datapath are attenuated by the same
amount. (Note that internally the AD1845 always works with
16-bit PCM linear data, digital mixing included; format conversions take place at the input and output.)
Sixty-four steps of –1.5 dB attenuation are supported to –94.5dB.
The digital mix datapath can also be completely muted. Note
that the level of the mixed signal is also a function of the input
PGA settings, since they affect the ADCs’ output.
The attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. The
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because both
stereo signals are mixed before the output attenuators, mix data is
attenuated a second time by the DACs’ datapath attenuators.
In case the AD1845 is capturing data, but ADC output data is
not removed in time (“ADC overrun”), the last sample captured
before overrun will be used for the digital mix. In case the
AD1845 is playing back data, but input digital DAC data fails
to arrive in time (“DAC underrun”), a midscale zero will be
added to the digital mix data when the DACZ control bit is set
to 0; otherwise, the DAC will output the previous valid sample
in an underrun condition.
Analog Outputs
Stereo and mono line-level outputs are available at external
pins. Each channel of this output can be independently muted.
When muted, the outputs will settle to a dc value near V
REF
, the
midscale reference voltage. The output is selectable for 2.0 V
peak-to-peak or 2.8 V peak-to-peak. When selecting the LINE
output as an input to the ADC, the ADC automatically compensates for the output level selection.
Digital Data Types
The AD1845 supports five global data types: 16-bit twos complement linear PCM (little endian and big endian byte ordering),
8-bit unsigned linear PCM, companded µ-law, and 8-bit com-
panded A-law, as specified by control register bits. Data in all
formats is always transferred MSB first. All data formats that are
less than 16 bits are MSB-aligned to ensure the use of full
system resolution.
The 16-bit PCM data format is capable of representing 96 dB
of dynamic range. Eight-bit PCM can represent 48 dB of dynamic range. Companded µ-law and A-law data formats use
nonlinear coding with less precision for large amplitude signals.
The loss of precision is compensated for by an increase in dynamic range to 64 dB and 72 dB, respectively.
On input, 8-bit companded data is expanded to an internal
linear representation, according to whether µ-law or A-law was
specified in the codec’s internal registers. Note that when µ-law
compressed data is expanded to a linear format, it requires
14 bits. A-law data expanded requires 13 bits.
FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1845 and is
intended as a general introduction to the capabilities of the
device. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The
user is not expected to refer repeatedly to this section.
Analog Inputs
The AD1845 SoundPort Stereo Codec accepts stereo line-level
and microphone-level inputs. The LINE, MIC, AUX1, and
post-mixed DAC output are available to the ADC multiplexer.
The DAC output can be mixed with LINE, MIC, AUX1,
AUX2 and M_IN. Each channel of the MIC inputs can be
amplified by +20 dB to compensate for the difference between
line levels and typical condenser microphone levels.
Analog Mixing
The M_IN mono input signal, MIC, LINE, AUX1 and AUX2
analog stereo signals can be mixed in the analog domain with
the DAC output. Each channel of each AUX, LINE and MIC
analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in 1.5 dB steps or completely muted.
M_IN can be attenuated from 0 dB to –45 dB in 3 dB steps or
muted. The post-mixed DAC outputs are available on L_OUT
and R_OUT and also to the ADC input multiplexer.
Even if the AD1845 is not playing back data from its DACs, the
analog mix function can still be active.
Analog-to-Digital Datapath
The PGA following the input multiplexer allows independent
selectable gains for each channel from 0dB to 22.5dB in
+1.5 dB steps. The codec can operate either in a global stereo
mode or in a global mono mode with left-channel inputs
appearing at both channel outputs.
The AD1845 ∑∆ ADCs incorporate a fourth-order modulator.
A single pole of passive filtering is all that is required for antialiasing the analog input because of the ADC’s high over sampling ratio. The ADCs include linear-phase digital decimation
filters that low-pass filter the input to 0.4 × F
S
. (“FS” is the
word rate or “sampling frequency.”) ADC input over range
conditions are reported on status bits in the Test and Initialization Register.
Digital-to-Analog Datapath
The ∑∆ DACs are preceded by a programmable attenuator and
a low-pass digital interpolation filter. The anti-imaging interpolation filter over samples and digitally filters the higher frequency images. The attenuator allows independent control of
each DAC channel from 0 dB to –94.5 dB in –1.5 dB steps plus
full mute. The DACs’ ∑∆ noise shapers also over sample and
convert the signal to a single-bit stream. The DAC outputs are
then filtered in the analog domain by a combination of switchedcapacitor and continuous-time filters. They remove the very
high frequency components of the DAC bit stream output. No
external components are required.
Changes in DAC output attenuation take effect only on zero
crossings, eliminating “zipper” noise on playback. Each channel has its own independent zero-crossing detector and attenuator change control circuitry. A timer guarantees that requested
volume changes will occur even in the absence of a zero crossing. The time-out period is 8 milliseconds at a 48 kHz sampling
rate and 48 milliseconds at an 8 kHz sampling rate. (Timeout
[ms] ≈ 384 ÷ F
S
[kHz].)
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MSB LSB
COMPRESSED
INPUT DATA
8 7
0
15
MSB LSB
3/2 2/1
0
15
EXPANSION
MSB LSB
3/2 2/1
0
15
DAC INPUT 000/00
Figure 2. µ-Law or A-Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
MSB LSB
0
15
MSB LSB
3/2 2/1
015
MSB LSB
8 7
0
15
00000000
ADC OUTPUT
TRUNCATION
COMPRESSION
Figure 3.µ-Law or A-Law Compression
Note that all format conversions take place at input or output.
Internally, the AD1845 always uses 16-bit linear PCM representations to maintain maximum precision.
Timer Registers
The timer registers are provided for system level synchronization, and for periodic interrupt generation. The 16-bit timer
time base is determined by the frequency of the connected input
clock source.
The timer is enabled by setting the Timer Enable bit, TE, in the
Alternate Feature Enable register. To set the timer, load the
Upper and Lower Timer Bits Registers. The timer value will
then be loaded into an internal count register with a value of
approximately 10 µs (the exact timer value is listed in the regis-
ter descriptions). The internal count register will decrement
until it reaches zero, then the Timer Interrupt bit, TI, is set and
an interrupt will be sent to the host. The next timer clock will
load the internal count register with the value of the Timer
Register, and the timer will be reinitialized. To clear the interrupt, write to the Status Register or write a “0” to TI.
Interrupts
The AD1845 supports interrupt conditions generated by DMA
playback count expiration, DMA capture count expiration, or
timer expiration. The INT bit will remain set, HI, until a write
has been completed to the Status Register or by clearing the TI,
CI, or PI bit (depending on the existing condition) in the Capture Playback Timer Register. The IEN bit of the Pin Control
Register determines whether the interrupt pin responds to an
interrupt condition and reflects the interrupt state on the
INT status bit.
Power Supplies and Voltage Reference
The AD1845 operates from a +5 V power supply. Independent
analog and digital supplies are recommended for optimal performance though excellent results can be obtained in single-supply
systems. A voltage reference is included on the codec and its
2.25 V buffered output is available on an external pin (V
REF
).
The reference output can be used for biasing op amps used in
dc coupling. The internal reference is externally bypassed to
analog ground at the V
REF_F
pin.
Clocks and Sample Rates
The AD1845 operates from a single external crystal or clock
source. From a single input, a wide range of sample rates can be
generated. The AD1845 default frequency source is a
24.576 MHz input. The AD1845 can also be driven from a
14.31818 MHz (OSC), 24 MHz, 25 MHz or 33 MHz input
frequency source. In MODE1, the input drives the internal
variable sample frequency generator to derive the following
AD1848 compatible sample rates: 5.5125, 6.615, 8, 9.6,
11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1,
48 kHz. In MODE2, the AD1845 can be programmed to generate any sample frequency between 4 kHz and 50kHz with
1 Hz resolution. Note that it is no longer required to enter
Mode Change Enable (MCE) to change the sample rate. This
feature allows the user to change the AD1845’s sample rate “on
the fly.”
CONTROL REGISTERS
Control Register Architecture
The AD1845 SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 37 of its byte-wide internal registers. Only two external address pins, ADR1:0, are required to accomplish all data
and control transfers. These pins select one of five direct registers. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is for a playback or capture.)
ADR1:0 Register Name
0 Index Address Register
1 Indexed Data Register
2 Status Register
3 PIO Data Register
Figure 4. Direct Register Map
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A write to or a read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently
written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without
indexing. The 32 Indirect Register indexes are shown in Figure 5:
Index Register Name Reset/Default State
0 Left Input Control 000x 0000
1 Right Input Control 000x 0000
2 Left Aux #1 Input Control 1xx0 1000
3 Right Aux #1 Input Control 1xx0 1000
4 Left Aux #2 Input Control 1xx0 1000
5 Right Aux #2 Input Control 1xx0 1000
6 Left Output Control 1x00 0000
7 Right Output Control 1x00 0000
8 Clock and Data Format 0000 0000
9 Interface Configuration 00xx 1000
10 Pin Control 00xx xx00
11 Test and Initialization 0000 0000
12 Miscellaneous Information 10x0 1010
13 Digital Mix/Attenuation 0000 00x0
14 Upper Base Count 0000 0000
15 Lower Base Count 0000 0000
16 Alternate Feature Enable/Left MIC Input Control 0001 0001
17 MIC Mix Enable/Right MIC Input Control 0001 000x
18 Left Line Gain, Attenuate, Mute, Mix 1xx0 1000
19 Right Line Gain, Attenuate, Mute, Mix 1xx0 1000
20 Lower Timer 0000 0000
21 Upper Timer 0000 0000
22 Upper Frequency Select 0001 1111
23 Lower Frequency Select 0100 0000
24 Capture Playback Timer x000 0000
25 Revision ID 100x x000
26 Mono Control 00xx 0011
27 Power-Down Control 000x 0xxx
28 Capture Data Format Control 0000 xxxx
29 Crystal Clock Select/Total Power-Down 000x xxx0
30 Capture Upper Base Count 0000 0000
31 Capture Lower Base Count 0000 0000
“x” indicates reserved bit, always write “0s” to these bits.
Figure 5. Indirect Register Map and Reset/Default States
A detailed map of all direct and indirect register contents is summarized for reference as follows:
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