Analog Devices CMP04FS, CMP04FP, CMP04BY Datasheet

Quad Low Power,

a

FEATURES
High Gain: 200 V/mV typ
Single or Dual Supply Operation
Input Voltage Range Includes Ground
Low Power Consumption (1.5 mW/Comparator)
Low Input Bias Current: 100 nA max
Low Input Offset Current: 10 nA max
Low Offset Voltage: 1 mV max
Low Output Saturation Voltage: 250 mV @ 4 mA
Logic Output Compatible with TTL, DTL, ECL, MOS and

CMOS
Directly Replaces LM139/239/339 Comparators
Available in Die Form

GENERAL DESCRIPTION

Four precision independent comparators comprise the CMP04.
Performance highlights include a very low offset voltage, low
output saturation voltage and high gain in a single supply de­sign. The input voltage range includes ground for single supply
operation and V– for split supplies. A low power supply current
of 2 mA, which is independent of supply voltage, makes this the
preferred comparator for precision applications requiring mini­mal power consumption. Maximum logic interface flexibility is
offered by the open-collector TTL output.

V+

+INPUT

*

*

SUBSTRATE DIODES

Q1

100mA 3.5mA3.5mA 100mA

Q2

Q3

Q6Q5

Q4

Q7

OUTPUT

Q8

–INPUT

*

Precision Comparator

PIN CONNECTIONS

14-Lead Cerdip

14-Lead Plastic DIP

OUT 2
OUT 1

V+
IN 1–
IN 1+
IN 2–
IN 2+

TYPICAL INTERFACE

3

1/4

CMP04

12

Figure 2a. Driving CMOS

5.0

3

1/4

CMP04

12

Figure 2b. Driving TTL

14-Lead SOIC

1

2

3

4

5

6

7

1

2

CMP04

100kV

10kV

14

13

4

12

11

10

3

9

8

5.0

CMP04

OUT 3
OUT 4
GND
IN 4+
IN 4–
IN 3+
IN 3–

1/4
CD4011

1/4 SN7400

Figure 1. Simplified Schematic (1/4 CMP04)

REV. C

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CMP04–SPECIFICATIONS

WARNING!

ESD SENSITIVE DEVICE

ELECTRICAL CHARACTERISTICS

(@ V+ = +5 V, TA = +25ⴗC, unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

Input Offset Voltage V
Input Offset Current I
Input Bias Current I
Voltage Gain A
Large-Signal Response Time t

Small-Signal Response Time t

OS

B

r

r

OS

V

R

= 0 Ω, RL = 5.1 kΩ, V

S

IIN(+) – IIN(–), R

= 5.1 kΩ, V

L

IIN(+) or IIN(–) 25 100 nA
R

≥ 15 kΩ, V+ = 15 V

L

VIN = TTL Logic Swing, V
VRL = 5 V, R

= 5.1 kΩ 300 ns

L

O

2

= 1.4 V

REF

VIN = 100 mV Step3, 5 mV Overdrive
V

= 5 V, R

RL

= 5.1 kΩ 1.3 µs

L

1

= 1.4 V 2 10 nA

O

80 200 V/mV

= 1.4 V

3

0.4 1 mV

Input Voltage Range CMVR (Note 4) 0 V+ –1.5 V
Common-Mode Rejection Ratio CMRR (Notes 2, 5) 80 100 dB
Power Supply Rejection Ratio PSRR V+ = +5 V to +18 V
Saturation Voltage V
Output Sink Current I
Output Leakage Current I

OL

SINK

LEAK

V

(–) ≥ 1 V, V

IN

V

(–) ≥ 1 V, V

IN

V

(+) ≥ 1 V, V

IN

2

(+) = 0, I

IN

(+) = 0, V

IN

(–) = 0, VO = 30 V 0.1 100 nA

IN

≤ 4 mA 250 400 mV

SINK

≤ 1.5 V 6 16 mA

O

80 100 dB

Supply Current I+ RL = ∞, All Comps V+ = 30 V 0.8 2.0 mA

NOTES

1

At output switch point, VO = 1.4 V, R

2

Guaranteed by design.

3

Sample tested.

4

The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range
is V+ –1.5 V, but either or both inputs can go to +30 V without damage.

5

R

≥ 15 kΩ, V+ = 15 V, V

L

Specifications subject to change without notice.

= 1.5 V to 13.5 V.

CM

= 0 Ω with V+ from 5 V; and over the full input common-mode range (0 V to V+ –1.5 V).

S

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .36 V or ±18 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 36 V dc

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +36 V

Operating Temperature Range

CMP04BY . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

CMP04FP, FS . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature (T

) . . . . . . . . . . . . . –65°C to +150°C

J

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

(P Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Input Current (V

< –3.0 V) . . . . . . . . . . . . . . . . . . . 50 mA

IN

Output Short-Circuit to GND . . . . . . . . . . . . . . . .Continuous

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C

1

Package Type ␪

14-Lead Hermetic DIP (Y) 94 10 °C/W
14-Lead Plastic DIP (P) 83 39 °C/W
14-Lead SOIC 120 36 °C/W

NOTES

1

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

θJA is specified for worst case mounting conditions, i.e., θ

in socket for cerdip and plastic DIP packages; θ

to printed circuit board for SO package.

ORDERING GUIDE

TA = +25ⴗC Temperature Package Package

Model V

OS

Ranges Descriptions Options

CMP04BY/883C 1 mV –55°C to +125°C 14-Lead Cerdip Q-14
CMP04FP 1 mV –40°C to +85°C 14-Lead Plastic DIP N-14
CMP04FS 1 mV –40°C to +85°C 14-Lead SOIC R-14/SO-14

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the CMP04 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

2

JA

␪

JC

is specified for device

JA

is specified for device soldered

JA

Units

–2–

REV. C

CMP04

(@ V+ = +5 V, –55ⴗC ≤ TA ≤ +125ⴗC for CMP04BY, –40ⴗC ≤ TA ≤ +85ⴗC for

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units

Input Offset Voltage V

Input Offset Current I

Input Bias Current I

Voltage Gain A

Large-Signal Response Time t

Small-Signal Response Time t

Input Voltage Range CMVR (Note 5) 0 V+ –1.5 V

Common-Mode Rejection Ratio CMRR (Notes 1, 3) 60 100 dB

Power Supply Rejection Ratio PSRR V+ = +5 V to +18 V 80 100 dB

Saturation Voltage V

Output Sink Current I

Output Leakage Current I

Supply Current I+ RL = ∞, All Comps 1.2 3.0 mA

NOTES

1

R

≥ 15 kΩ, V+ = 15 V, V

L

2

At output switch point, VO = 1.4 V, R

3

Guaranteed by design.

4

Sample tested.

5

The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode
voltage range is V+ –1.5 V, but either or both inputs can go to +30 V without damage.

Specifications subject to change without notice.

= 1.5 V to 13.5 V.

CM

OS

OS

B

V

r

r

OL

SINK

LEAK

= 0 Ω with V+ from 5 V; and over the full input common-mode range (0 V to V+ –1.5 V).

S

CMP04FP/FS, unless otherwise noted)

CMP04B/F

R

= 0 Ω, RL = 5.1 kΩ 12 mV

S

VO = 1.4 V

2

IIN(+) – IIN(–) 4 20 nA

= 5.1 kΩ 420nA

R

L

VO = 1.4 V 4 20 nA

IIN(+) or IIN(–) 40 200 nA

R

≥ 15 kΩ, V+ = 15 V

L

VIN = TTL Logic Swing 300 ns
V

REF

VRL = 5 V, R

= 1.4 V

4

= 5.1 kΩ 300 ns

L

VIN = 100 mV Step

3

4

70 125 V/mV

5 mV Overdrive 1.3 µs

VRL = 5 V, R

V

(–) ≥ 1 V, V

IN

I

≤ 4 mA 250 700 mV

SINK

V

(–) ≥ 1 V, 5 16 mA

IN

VIN(+) = 0, V

V

(+) ≥ 1 V, 0.1 200 nA

IN

= 5.1 kΩ 1.3 µs

L

(+) = 0, 250 700 mV

IN

≤ 1.5 V 5 16 mA

O

VIN(–) = 0, VO = 30 V 0.1 200 nA

V+ = 30 V 1.2 3.0 mA

1

12 mV

300 ns

1.3 µs

REV. C

–18V

+18V

ONE EACH

PER BOARD

100kV

3.6kV

3.6kV

ZENER

5.8V TO 6.2V
1 WATT

TO ADJACENT SOCKETS

3.6kV

13 12 11

4

CMP04

3

2345617

3.6kV

470kV

+30V

Figure 3. Burn-In Circuit

–3–

–18V

914 8

10

1

2

+18V

MIL-STD-883, METHOD 1015, CONDITION B