Analog Devices ADSP-2185L Datasheet
a
DSP Microcomputer
ADSP-2185L
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as 16K Words
Program Memory RAM and 16K Words
Data Memory RAM
Dual Purpose Program Memory for Instruction␣ and Data
Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
DATA ADDRESS
GENERATORS
DAG 2
DAG 1
ARITHMETIC UNITS
ALU
MAC
ADSP-2100 BASE
ARCHITECTURE
PROGRAM
SEQUENCER
SHIFTER
8K324 OVERLAY 1
()
8K324 OVERLAY 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
CONTROL
MEMORY
16K324 PM 16K316 DM
8K316 OVERLAY 1
8K316 OVERLAY 2
()
SERIAL PORTS
SPORT 1SPORT 0
PROGRAMMABLE
TIMER
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
GENERAL NOTE
This data sheet represents specifications for the ADSP-2185L
3.3 V processor.
GENERAL DESCRIPTION
The ADSP-2185L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2185L combines the ADSP-2100 family base architecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2185L integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable
equipment. The ADSP-2185L is available in 100-lead LQFP
package.
In addition, the ADSP-2185L supports instructions which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
ALU constants, multiplication instruction (x squared), biased
rounding, result free ALU operations, I/O memory transfers and
global interrupt masking, for increased flexibility.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2185L operates with a 19 ns instruction cycle time. Every instruction can execute in a single processor cycle.
ICE-Port is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
␣␣
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
ADSP-2185L
The ADSP-2185L’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-2185L can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive or transmit data through the internal DMA port
• Receive or transmit data through the byte DMA port
• Decrement timer
DEVELOPMENT SYSTEM
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports the ADSP-2185L. The System Builder provides a high
level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment.
A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2185L assembly source
code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite includes the following features:
• 33 MHz ADSP-218x
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort
• RS-232 Interface to PC with Windows 3.1 Control Software
• EZ-ICE
®
Connector for Emulator Control
®
Codec
• DSP Demo Programs
The ADSP-218x EZ-ICE Emulator aids in the hardware debugging of ADSP-2185L system. The emulator consists of hardware, host computer resident software and the target board
connector. The ADSP-2185L integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family
EZ-ICEs. The ADSP-2185L device need not be removed from
the target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
Additional Information
This data sheet provides a general overview of ADSP-2185L
functionality. For additional information on the architecture and
instruction set of the processor, see the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.
ARCHITECTURE OVERVIEW
The ADSP-2185L instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The ADSP-2185L assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
POWER-DOWN
DATA ADDRESS
GENERATORS
DAG 2
DAG 1
ARITHMETIC UNITS
ALU
MAC
ADSP-2100 BASE
ARCHITECTURE
PROGRAM
SEQUENCER
SHIFTER
8K324 OVERLAY 1
()
8K324 OVERLAY 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
CONTROL
MEMORY
16K324 PM 16K316 DM
8K316 OVERLAY 1
8K316 OVERLAY 2
()
SERIAL PORTS
SPORT 1SPORT 0
PROGRAMMABLE
TIMER
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the ADSP-2185L. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations.
The shifter can be used to efficiently implement numeric format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
–2–
REV. A
ADSP-2185L
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2185L executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting the ADSP-2185L to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2185L can fetch an operand from program memory and
the next instruction in the same cycle.
In lieu of the address and data bus for external memory connection, the ADSP-2185L may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH, and BG).
One execution mode (Go Mode) allows the ADSP-2185L to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted.
The ADSP-2185L can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two levelsensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2185L provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2185L incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2185L
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User’s Manual, Third Edition.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONS
The ADSP-2185L is available in a 100-lead LQFP package. In
order to maintain maximum functionality and reduce package
size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality.
The external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics. See Common-Mode Pin
Descriptions.
REV. A
–3–
ADSP-2185L
Common-Mode Pin Descriptions
Pin # of Input/
Name(s) Pins Output Function
RESET 1 I Processor Reset Input
BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2/ 1 I Edge- or Level-Sensitive Interrupt
PF7 I/O Request.
IRQL1/ 1 I Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
1
PF6 I/O Programmable I/O Pin
IRQL0/ 1 I Level-Sensitive Interrupt Requests
1
PF5 I/O Programmable I/O Pin
IRQE/ 1 I Edge-Sensitive Interrupt Requests
1
PF4 I/O Programmable I/O Pin
PF3 I/O Programmable I/O Pin During
Normal Operation
Mode C/ 1 I Mode Select Input—Checked
Only During RESET
PF2 I/O Programmable I/O Pin During
Normal Operation
Mode B/ 1 I Mode Select Input—Checked
Only During RESET
PF1 I/O Programmable I/O Pin During
Normal Operation
Mode A/ 1 I Mode Select Input—Checked
Only During RESET
PF0 I/O Programmable I/O Pin During
Normal Operation
CLKIN,
XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
IRQ1:0 Edge- or Level-Sensitive Interrupts,
FI, FO Flag In, Flag Out
2
PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1,
FL2 3 O Output Flags
VDD and
GND 16 I Power and Ground
EZ-Port 9 I/O For Emulation Use
N
OTES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the
corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software
configurable.
Memory Interface Pins
The ADSP-2185L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
Full Memory Mode Pins (Mode C = 0)
Pin # of Input/
Name(s) Pins Output Function
A13:0 14 O Address Output Pins for Program,
Data, Byte and I/O Spaces
D23:0 24 I/O Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)
Host Mode Pins (Mode C = 1)
Pin # of Input/
Name(s) Pins Output Function
IAD15:0 16 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O, Pro-
gram, Data or Byte access
D23:8 16 I/O Data I/O Pins for Program, Data
Byte and I/O spaces
IWR 1 I IDMA Write Enable
IRD 1 I IDMA Read Enable
IAL 1 I IDMA Address Latch Pin
IS 1 I IDMA Select
IACK 1 O IDMA Port Acknowledge
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
I/O Hi-Z*
Pin 3-State Reset Caused Unused
Name (Z) State By Configuration
XTAL I I Float
CLKOUT O O Float
A13:1 or O (Z) Hi-Z BR, EBR Float
IAD12:0 I/O (Z) Hi-Z IS Float
A0 O (Z) Hi-Z BR, EBR Float
D23:8 I/O (Z) Hi-Z BR, EBR Float
D7 or I/O (Z) Hi-Z BR, EBR Float
IWR I I High (Inactive)
D6 or I/O (Z) Hi-Z BR, EBR Float
IRD IIBR, EBR High (Inactive)
D5 or I/O (Z) Hi-Z Float
IAL I I Low (Inactive)
–4–
REV. A
ADSP-2185L
Pin Terminations (Continued)
I/O Hi-Z*
Pin 3-State Reset Caused Unused
Name (Z) State By Configuration
D4 or I/O (Z) Hi-Z BR, EBR Float
IS I I High (Inactive)
D3 or I/O (Z) Hi-Z BR, EBR Float
IACK Float
D2:0 or I/O (Z) Hi-Z BR, EBR Float
IAD15:13 I/O (Z) Hi-Z IS Float
PMS O (Z) O BR, EBR Float
DMS O (Z) O BR, EBR Float
BMS O (Z) O BR, EBR Float
IOMS O (Z) O BR, EBR Float
CMS O (Z) O BR, EBR Float
RD O (Z) O BR, EBR Float
WR O (Z) O BR, EBR Float
BR I I High (Inactive)
BG O (Z) O EE Float
BGH O O Float
IRQ2/PF7 I/O (Z) I Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
IRQL1/PF6 I/O (Z) I Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
IRQL0/PF5 I/O (Z) I Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
IRQE/PF4 I/O (Z) I Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
SCLK0 I/O I Input = High or Low,
Output = Float
RFS0 I/O I High or Low
DR0 I I High or Low
TFS0 I/O O High or Low
DT0 O O Float
SCLK1 I/O I Input = High or Low,
Output = Float
RFS1/RQ0 I/O I High or Low
DR1/FI I I High or Low
TFS1/RQ1 I/O O High or Low
DT1/FO O O Float
EE I I
EBR II
EBG OO
ERESET II
EMS OO
EINT II
ECLK I I
ELIN I I
ELOUT O O
NOTES
**Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF.
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
3. All bidirectional pins have three-stated outputs. When the pins is configured
as an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2185L provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP2185L also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
Table I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Source of Interrupt Address (Hex)
RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable) 002C
IRQ2 0004
IRQL1 0008
IRQL0 000C
SPORT0 Transmit 0010
SPORT0 Receive 0014
IRQE 0018
BDMA Interrupt 001C
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
Timer 0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in
IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable.
The ADSP-2185L masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks are
twelve levels deep to allow interrupt, loop and subroutine nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power down), regardless of
the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
REV. A
–5–
ADSP-2185L
LOW POWER OPERATION
The ADSP-2185L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-2185L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
• Quick recovery from power-down. The processor begins executing instructions in as few as 400 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during powerdown without affecting the 400 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 400 CLKIN cycle start up.
• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit Interrupt support allows
an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can
be used as a non-maskable, edge-sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
Idle
When the ADSP-2185L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In
Idle Mode IDMA, BDMA and autobuffer cycle steals still occur.
Slow Idle
The IDLE instruction on the ADSP-2185L slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the
IDLE instruction. The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2185L will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2185L, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSP-2185L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to
a single address bit (A0). Additional system peripherals can be
added in this mode through the use of external hardware to generate and latch address signals.
Clock Signals
The ADSP-2185L can be clocked by either a crystal or a TTLcompatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed information on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
The ADSP-2185L uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally, instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2185L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
–6–
REV. A
ADSP-2185L
FULL MEMORY MODE
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
mCONTROLLER
ADSP-2185L
CLKIN
XTAL
FL0-2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
PF2 [MODE C]
PF1 [MODE B]
PF0 [MODE A]
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FL0
DR1 OR FL1
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
HOST MEMORY MODE
ADSP-2185L
CLKIN
XTAL
FL0-2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
PF2 [MODE C]
PF1 [MODE B]
PF0 [MODE A]
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
16
IAD15-0
ADDR13-0
DATA23-0
BMS
WR
IOMS
PMS
DMS
CMS
BGH
PWD
PWDACK
DATA23-8
BMS
WR
IOMS
PMS
DMS
CMS
BGH
PWD
PWDACK
14
A
13-0
D
A0-A21
23-16
D
24
RD
BR
BG
1
A0
16
RD
BR
BG
15-8
DATA
CS
A
10-0
ADDR
D
23-8
DATA
CS
A
13-0
ADDR
D
23-0
DATA
Figure 2. ADSP-2185L Basic System Configuration
CLKIN CLKOUT
XTAL
DSP
Figure 3. External Crystal Connections
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
Reset
The RESET signal initiates a master reset of the ADSP-2185L.
The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, t
RSP
.
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, an external
Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
MODES OF OPERATION
Table II summarizes the ADSP-2185L memory modes.
Setting Memory Mode
Memory Mode selection for the ADSP-2185L is made during
chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the
pull-up or pull-down will hold the pin in a known state, and will
not switch.
Active configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output enable should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant level and not oscillate should the three-state driver’s level
hover around the logic switching point.
REV. A
–7–
ADSP-2185L
Table II. Modes of Operations
1
MODE C2MODE B3MODE A4Booting Method
0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is configured
in Full Memory Mode.
5
0 1 0 No Automatic boot operations occur. Program execution starts at external memory location
0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does
not automatically use or wait for these operations.
1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)
1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off
until internal program memory location 0 is written to. Chip is configured in Host Mode.
NOTES
1
All mode pins are recognized while RESET is active (low).
2
When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.
3
When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
4
When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
5
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
MEMORY ARCHITECTURE
The ADSP-2185L provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory, and I/O. Refer to the
following figures and tables for PM and DM memory allocations in the ADSP-2185L.
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.
Table III. PMOVLAY Bits
5
PMOVLAY Memory A13 A12:0
PROGRAM MEMORY
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The
ADSP-2185L has 16K words of Program Memory RAM on
chip, and the capability of accessing up to two 8K external
memory overlay spaces using the external data bus.
0 Internal Not Applicable Not Applicable
1 External 0 13 LSBs of Address
Overlay 1 Between 0x2000
and 0x3FFF
2 External 1 13 LSBs of Address
Overlay 2 Between 0x2000
and 0x3FFF
INTERNAL
MEMORY
EXTERNAL
MEMORY
PM (MODE B = 0)
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
ACCESSIBLE WHEN
PMOVLAY = 1
ACCESSIBLE WHEN
PMOVLAY = 2
PROGRAM MEMORY
MODE B = 0
8K INTERNAL
PMOVLAY = 0
OR
8K EXTERNAL
PMOVLAY = 1 OR 2
8K INTERNAL
PM (MODE B = 1)
RESERVED
INTERNAL
0x2000–
0x3FFF
0x2000–
0x3FFF
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
2
0x2000–
0x3FFF
MEMORY
2
ACCESSIBLE WHEN
PMOVLAY = 0
ACCESSIBLE WHEN
PMOVLAY = 0
EXTERNAL
MEMORY
1
WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2
SEE TABLE III FOR PMOVLAY BITS
PROGRAM MEMORY
MODE B = 1
8K INTERNAL
PMOVLAY = 0
8K EXTERNAL
Figure 4. Program Memory
–8–
1
RESERVED
0x2000–
0x3FFF
0x0000–
0x1FFF
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
2
REV. A
ADSP-2185L
DATA MEMORY
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2185L has 16K words on Data
Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus. All internal accesses complete in one cycle.
Accesses to external memory are timed using the wait states
specified by the DWAIT register.
INTERNAL
MEMORY
ACCESSIBLE WHEN
EXTERNAL
MEMORY
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0
x2000 – 0x3FFF
DMOVLAY = 0
ACCESSIBLE WHEN
DMOVLAY = 1
ACCESSIBLE WHEN
DMOVLAY = 2
x0000–
0
0
x1FFF
0
x0000–
x1FFF
0
0
x0000–
x1FFF
0
DATA MEMORY
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160
WORDS
8K INTERNAL
DMOVLAY = 0
OR
EXTERNAL 8K
DMOVLAY = 1, 2
ADDRESS
0x3FFF
x3FE0
0
x3FDF
0
0
x2000
0
x1FFF
x
0000
0
Figure 5. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table IV.
Table IV. DMOVLAY Bits
DMOVLAY Memory A13 A12:0
0 Internal Not Applicable Not Applicable
1 External 0 13 LSBs of Address
Overlay 1 Between 0x2000
and 0x3FFF
2 External 1 13 LSBs of Address
Overlay 2 Between 0x2000
and 0x3FFF
I/O Space (Full Memory Mode)
The ADSP-2185L supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table V.
Table V. Wait States
Address Range Wait State Register
0x000–0x1FF IOWAIT0
0x200–0x3FF IOWAIT1
0x400–0x5FF IOWAIT2
0x600–0x7FF IOWAIT3
REV. A
–9–
Composite Memory Select (CMS)
The ADSP-2185L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory; use either DMS or PMS as the additional
address bit.
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset, except the BMS bit.
Boot Memory Select (BMS) Disable
The ADSP-2185L also lets you boot the processor from one external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for
BDMA transfers and BMS to select the second external memory
space for booting. The BMS signal can be disabled by setting
Bit 3 of the System Control Register to 1. The System Control
Register is illustrated in Figure 6.
15 14 13 12 11 10
00 000100 00 00011 1
SPORT0 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO, IRQ0, IRQ1, SCLK
SYSTEM CONTROL REGISTER
9876543210
DM (033FFF)
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0 = ENABLED, 1 = DISABLED
Figure 6. System Control Register
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 7. The byte memory space consists of 256 pages,
each of which is 16K × 8.
1514131211109876543210
0000000000001000
BMPAGE
BDMA CONTROL
DM (033FE3)
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
Figure 7. BDMA Control Register
The byte memory space on the ADSP-2185L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
ADSP-2185L
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats supported by the BDMA circuit.
Table VI. Data Formats
Internal
BTYPE Memory Space Word Size Alignment
00 Program Memory 24 Full Word
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
11 Data Memory 8 LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the 14bit BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT
register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2185L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memorymapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch the DMA starting
address (IDMAA) into the DSP’s IDMA control registers.
IAD[15] must be set = 0.
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-
nal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2185L is operating at full speed.
The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the ADSP-2185L’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2185L that a particular
transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automatically incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2185L to write the address onto the IAD0–14
bus into the IDMA Control Register. The IDMAA register,
shown below, is memory mapped at address DM (0x3FE0).
Note that the latched address (IDMAA) cannot be read back by
the host. See Figure 8 for more information on IDMA and
DMA memory maps.
–10–
REV. A
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