ANALOG DEVICES ADSP-2184L, ADSP-2185L, ADSP-2186L, ADSP-2187L Service Manual
DSP Microcomputer
ARITHMETIC UNITS
SHIFTERMAC
ALU
PROGRAM MEMORYADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
UP TO
32K ⴛ 24-BIT
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
SPORT0
SERIAL PORTS
SPORT1
PROGRAMMABLE
I/O
AND
FLAGS
TIMER
HOST MODE
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
DAG1
DATA ADDRESS
GENERATORS
DAG2
PROGRAM
SEQUENCER
ADSP-2100 BASE
ARCHITECTURE
DATA
MEMORY
UP TO
32K ⴛ 16-BIT
FULL MEMORYMODE
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
PERFORMANCE FEATURES
Up to 19 ns instruction cycle time, 52 MIPS sustained
performance
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
instruction cycle
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
pation with 400 CLKIN cycle recovery from power-down
condition
Low power dissipation in idle mode
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
syntax), with instruction set extensions
Up to 160K bytes of on-chip RAM, configured
Up to 32K words program memory RAM
Up to 32K words data memory RAM
Dual-purpose program memory for both instruction and
data storage
Independent ALU, multiplier/accumulator, and barrel shifter
computational units
2 independent data address generators
Powerful program sequencer provides zero overhead loop-
ing conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
SYSTEM INTERFACE FEATURES
16-bit internal DMA port for high-speed access to on-chip
memory (mode selectable)
4M-byte memory interface for storage of data tables and pro-
gram overlays (mode selectable)
8-bit DMA to byte memory for transparent program and data
memory transfers (mode selectable)
Programmable memory strobe and separate I/O memory
space permits “glueless” system design
Programmable wait state generation
2 double-buffered serial ports with companding hardware
and automatic data buffering
Automatic booting of on-chip program memory from byte-
wide external memory, for example, EPROM, or through
internal DMA Port
6 external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port emulator interface supports debugging in final
systems
ICE-Port is a trademark of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Figure 1. Functional Block Diagram
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Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
TABLE OF CONTENTS
Performance Features ............................................... 1
Integration Features ................................................. 1
System Interface Features ........................................... 1
Table of Contents ..................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
Architecture Overview ........................................... 3
Modes Of Operation .............................................. 4
Interrupts ........................................................... 5
Low Power Operation ............................................ 6
System Interface ................................................... 7
Reset .................................................................. 8
Memory Architecture ............................................ 8
Bus Request and Bus Grant ................................... 13
Flag I/O Pins ..................................................... 13
Instruction Set Description ................................... 14
Development System ........................................... 14
Additional Information ........................................ 16
Pin Descriptions .................................................... 17
Memory Interface Pins ......................................... 18
Terminating Unused Pins ..................................... 19
Specifications ........................................................ 21
Operating Conditions ........................................... 21
Electrical Characteristics ....................................... 21
Absolute Maximum Ratings ................................... 22
Package Information ............................................ 22
ESD Sensitivity ................................................... 22
Timing Specifications ........................................... 22
Power Supply Current .......................................... 36
Power Dissipation ............................................... 37
Output Drive Currents ......................................... 40
Power-Down Current ........................................... 41
Capacitive Loading – ADSP-2184L, ADSP-2186L ... ..... 42
Capacitive Loading – ADSP-2185L, ADSP-2187L ... ..... 42
Test Conditions .................................................. 43
Environmental Conditions .................................... 43
LQFP Package Pinout ........................................... 44
BGA Package Pinout ............................................ 45
Outline Dimensions ................................................ 46
Surface Mount Design .......................................... 47
Ordering Guide ..................................................... 47
REVISION HISTORY
1/08—Rev. C
This revision of the ADSP-2184L/ADSP-2185L/
ADSP-2186L/ADSP-2187L processor data sheet combines the
ADSP-2184L, ADSP-2185L, ADSP-2186L, and ADSP-2187L.
This version also contains new RoHS compliant packages.
Rev. C | Page 2 of 48 | January 2008
GENERAL DESCRIPTION
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
The ADSP-218xL series consists of four single chip microcomputers optimized for digital signal processing applications. The
functional block diagram for the ADSP-218xL series members
appears in Figure 1 on Page 1. All series members are pin-compatible and are differentiated solely by the amount of on-chip
SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision.
Specific family members are shown in Table 1.
Table 1. ADSP-218xL DSP Microcomputer Family
Program Memory
Device
ADSP-2184L 4 4
ADSP-2185L 16 16
ADSP-2186L 8 8
ADSP-2187L 32 32
ADSP-218xL series members combine the ADSP-2100 family
base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
ADSP-218xL series members integrate up to 160K bytes of onchip memory configured as up to 32K words (24-bit) of program RAM, and up to 32K words (16-bit) of data RAM. Powerdown circuitry is also provided to meet the low power needs of
battery-operated portable equipment. The ADSP-218xL is available in 100-lead LQFP and 144-ball BGA packages.
Fabricated using high-speed, low-power, CMOS processes,
ADSP-218xL series members operate with a 19 ns instruction
cycle time (ADSP-2185L and ADSP-2187L) or a a 25 ns instruction cycle time (ADSP-2184L and ADSP-2186L). Every
instruction can execute in a single processor cycle.
The ADSP-218xL’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, ADSP-218xL series
members can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal
DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
(K words)
Data Memory
(K words)
ARCHITECTURE OVERVIEW
The ADSP-218xL series instruction set provides flexible data
moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a
single processor cycle. The ADSP-218xL assembly language uses
an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program
development.
The functional block diagram is an overall block diagram of the
ADSP-218xL series. The processor contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps,
subroutine calls, and returns in a single cycle. With internal
loop counters and loop stacks, ADSP-218xL series members
execute looped code with zero overhead; no explicit jump
instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for
circular buffers.
Five internal buses provide efficient data transfer:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
Rev. C | Page 3 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting ADSP-218xL series members to fetch two operands in a
single cycle, one from program memory and one from data
memory. ADSP-218xL series members can fetch an operand
from program memory and the next instruction in the
same cycle.
In lieu of the address and data bus for external memory connection, ADSP-218xL series members can be configured for 16-bit
Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 data/address pins and
five control pins. The IDMA port provides transparent, direct
access to the DSP’s on-chip program and data RAM.
An interface to low cost, byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR
, and BG). One execution mode (Go Mode) allows the
BGH
ADSP-218xL to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses
are granted.
ADSP-218xL series members can respond to eleven interrupts.
There can be up to six external interrupts (one edge-sensitive,
two level-sensitive, and three configurable) and seven internal
interrupts generated by the timer, the serial ports (SPORT), the
BDMA port, and the power-down circuitry. There is also a master RESET
synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit
and receive modes of operation. Each serial port can generate an
internal programmable serial clock or accept an external
serial clock.
ADSP-218xL series members provide up to 13 general-purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag. In
addition, eight flags are programmable as inputs or outputs, and
three flags are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
signal. The two serial ports provide a complete
,
Serial Ports
ADSP-218xL series members incorporate two complete synchronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-218xL
SPORTs. For additional information on Serial Ports, refer to the
ADSP-218x DSP Hardware Reference.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with
either of two pulse widths and timings.
• SPORTs support serial data word lengths from 3 bits to
16 bits and provide optional A-law and μ-law companding,
according to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word or 32-word, time-division multiplexed, serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0
and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this
configuration.
MODES OF OPERATION
The ADSP-218xL series modes of operation appear in Table 2.
Only the ADSP-2187L provides Mode D operation
Setting Memory Mode
Memory Mode selection for the ADSP-218xL series is made
during chip reset through the use of the Mode C pin. This pin is
multiplexed with the DSP’s PF2 pin, so care must be taken in
how the mode selection is made. The two methods for selecting
the value of Mode C are active and passive.
Passive Configuration
Passive Configuration involves the use of a pull-up or pulldown resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down resistance, on the
order of 10 kΩ, can be used. This value should be sufficient to
pull the pin to the desired level and still allow the pin to operate
as a programmable flag output without undue strain on the processor’s output driver. For minimum power consumption
Rev. C | Page 4 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Table 2. Modes of Operation
Mode D1Mode C Mode B Mode A Booting Method
X 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Full Memory Mode.
X 0 1 0 No automatic boot operations occur. Program execution starts at external memory
location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the
processor does not automatically use or wait for these operations.
0 1 0 0 BDMA feature is used to load the first 32 program memor y words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Host Mode. IACK
0 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held
off until the host writes to internal program memory location 0. Chip is configured in
Host Mode. IACK
1 1 0 0 BDMA feature is used to load the first 32 program memor y words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Host Mode; IACK
hardware.)
1 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held
off until the host writes to internal program memory location 0. Chip is configured in
Host Mode. IACK
1
Mode D applies to the ADSP-2187L processor only.
2
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
has active pull-down.
requires external pull-down.
2
has active pull-down. (Requires additional hardware.)
2
requires external pull-down. (Requires additional
2
during power-down, reconfigure PF2 to be an input, as the pullup or pull-down resistance will hold the pin in a known state,
and will not switch.
Active Configuration
Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET
it only drives the PF2 pin when RESET
RESET
is deasserted, the driver should be three-state, thus
is active (low). When
signal such that
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant
level, and will not oscillate should the three-state driver’s level
hover around the logic switching point.
IDMA ACK Configuration (ADSP-2187L Only)
Mode D = 0 and in Host Mode: IACK is an active, driven signal
and cannot be “wire-OR’ed.” Mode D = 1 and in Host Mode:
IACK
is an open drain and requires an external pull-down, but
multiple IACK pins can be “wire-OR’ed” together.
INTERRUPTS
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
ADSP-218xL series members provide four dedicated external
interrupt input pins: IRQ2
with the PF7–4 pins). In addition, SPORT1 may be reconfigured for IRQ0
, IRQ1, FI, and FO, for a total of six external
interrupts. The ADSP-218xL also supports internal interrupts
, IRQL0, IRQL1, and IRQE (shared
from the timer, the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels
are internally prioritized and individually maskable (except
power-down and reset). The IRQ2
, IRQ0, and IRQ1 input pins
can be programmed to be either level- or edge-sensitive. IRQL0
and IRQL1
are level-sensitive and IRQE is edge-sensitive. The
priorities and vector addresses of all interrupts are shown in
Table 3.
Table 3. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector Address
Source Of Interrupt
RESET
(or Power-Up with PUCR = 1) 0x0000 (highest priority)
Power-Down (Nonmaskable) 0x002C
IRQ2
IRQL1
IRQL0
SPORT0 Transmit 0x0010
SPORT0 Receive 0x0014
IRQE
BDMA Interrupt 0x001C
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer 0x0028 (lowest priority)
(Hex)
0x0004
0x0008
0x000C
0x0018
0x0020
0x0024
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register.
Rev. C | Page 5 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Individual interrupt requests are logically AND’ed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
ADSP-218xL series members mask all interrupts for one
instruction cycle following the execution of an instruction that
modifies the IMASK register. This does not affect serial port
autobuffering or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0
be either edge- or level-sensitive. The IRQE
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are 12 levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power-down), regardless
of the state of IMASK:
ENA INTS;
DIS INTS;
Disabling the interrupts does not affect serial port autobuffering
or DMA. When the processor is reset, interrupt servicing
is enabled.
, IRQ1, and IRQ2 external interrupts to
pin is an external
LOW POWER OPERATION
ADSP-218xL series members have three low-power modes that
significantly reduce the power dissipation when the device operates under standby conditions. These modes are:
• Power-Down
•Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
ADSP-218xL series members have a low-power feature that lets
the processor enter a very low-power dormant state through
hardware or software control. Following is a brief list of powerdown features. Refer to the ADSP-218x DSP Hardware Refer-
ence, “System Interface” chapter, for detailed information about
the power-down feature.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 400 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
400 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits
approximately 4096 CLKIN cycles for the crystal oscillator
to start or stabilize), and letting the oscillator run to allow
400 CLKIN cycle start-up.
• Power-down is initiated by either the power-down pin
(PWD
) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The powerdown interrupt also can be used as a nonmaskable, edgesensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving
the power-down state.
•The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin (PWDACK) indicates when
the processor has entered power-down.
Idle
When the ADSP-218xL is in the Idle Mode, the processor waits
indefinitely in a low-power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruction. In Idle Mode IDMA, BDMA, and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on ADSP-218xL series members to let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, ADSP-218xL series members
remain in the idle state for up to a maximum of n processor
cycles (n = 16, 32, 64, or 128) before resuming
normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
Rev. C | Page 6 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
I
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s
e
r
t
s
y
s
t
em
i
n
t
erf
a
ce d
i
a
g
r
a
m
h
er
e
1/2 ⴛ CLOCK
OR
CRYSTAL
FL0–2
CLKIN
XTAL
SERIAL
DEVICE
SCLK1
RFS1 OR IR Q0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
SERIAL
DEVICE
A0–A21
DATA
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
DATA
ADDR
DATA
ADDR
2048 L OCATIONS
OVERLAY
MEMORY
TWO 8K
PM S EGMENTS
D23–0
A13–0
D23–8
A10–0
D15–8
D23–16
A13–0
14
24
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
DATA23–0
ADSP-218xL
CS
CS
1/2 ⴛ CLOCK
OR
CRYSTAL
CLKIN
XTAL
FL0–2
SERIAL
DEVICE
SCLK1
RFS1 OR IR Q0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
16
IDMA POR T
IRD/D6
IS/D4
IAL/D5
IACK/D3
IAD15-0
SERIAL
DEVICE
SCLK 0
RFS0
TFS0
DT0
DR0
SPORT0
1
16
A0
DATA23–8
IOMS
BMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
HOST MEMORY MODE
FULL MEMORY MODE
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
IRQ2/P F7
IRQE/P F 4
IRQL0 /PF5
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
WR
RD
SYSTEM
INTER FACE
OR
µCONTROLLER
IRQ2/P F7
IRQE/P F 4
IRQL0 /PF5
IRQL1 /PF6
IOMS
BMS
PMS
CMS
BR
BG
BGH
PWD
PWDACK
WR
RD
ADSP-218xL
DMS
TWO 8K
DM SEGMENTS
PMS
ADDR13–0
IRQL1 /PF6
IWR/D 7
NOTE: M O DE D APPLIES TO T HE ADSP-2187L PRO CES S OR ONL Y
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xL series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xL series members also provide four external interrupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
Clock Signals
ADSP-218xL series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal operation. The only exception is while the processor is in the
power-down state. For additional information, refer to the
ADSP-218x DSP Hardware Reference, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
ADSP-218xL series members use an input clock with a frequency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xL series members include an on-chip oscillator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 3. Capacitor values are
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in Figure 3.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
Figure 2. Basic System Interface
Rev. C | Page 7 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
CLKIN
CLKOUTXTAL
DSP
1M⍀
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNALPM)
INTERNAL PM
PM OVERLAY 0
(RESERVED)
RESERVED
MODEB = 0
0x3FFF
0x2000
0x0000
0x0FFF
0x1000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x3000
0x2FFF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
4064 RESERVED
WORDS
DM OVERLAY 0
(RESERVED)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
sequence is performed. The first instruction is fetched from onchip program memory location 0x0000 once boot loading
completes.
MEMORY ARCHITECTURE
The ADSP-218xL series provides a variety of memory and
peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to
Figure 4 through Figure 7 for PM and DM memory allocations
in the ADSP-218xL series.
Figure 3. External Crystal Connections
RESET
The RESET signal initiates a master reset of the ADSP-218xL.
The RESET
sequence to assure proper initialization. RESET
power-up must be held long enough to allow the internal clock
to stabilize. If RESET
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence, the RESET
any subsequent resets, the RESET
mum pulse width specification (t
The RESET
circuit is used to generate the RESET
nal Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
signal must be asserted during the power-up
during initial
is activated any time after power-up, the
is
DD
signal should be held low. On
signal must meet the mini-
).
RSP
input contains some hysteresis; however, if an RC
signal, the use of an exter-
Program Memory
Program Memory (Full Memory Mode) is a 24-bit-wide space
for storing both instruction opcodes and data. The member
DSPs of this series have up to 32K words of Program Memory
RAM on chip, and the capability of accessing up to two 8K
external memory overlay spaces, using the external data bus.
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
Host Mode due to a restricted data bus that is only 16 bits wide.
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped control registers. The ADSP-218xL series has up to 32K words of
Data Memory RAM on-chip. Part of this space is used by 32
memory-mapped registers. Support also exists for up to two 8K
external memory overlay spaces through the external data bus.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register.
Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external
address line (A0).
Figure 4. ADSP-2184 Memory Architecture
Rev. C | Page 8 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNALPM)
INTERNAL PM
PM OVERLAY 0
(INTERNAL PM)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY 0
(INTERNAL DM)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNALPM)
INTERNAL PM
PM OVERLAY 0
(RESERVED)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY 0
(RESERVED)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNALPM)
INTERNAL PM
PM OVERLAY0,4,5
(INTERNAL PM)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY 0,4,5
(INTERNAL DM)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
Figure 5. ADSP-2185 Memory Architecture
Figure 6. ADSP-2186 Memory Architecture
Figure 7. ADSP-2187 Memory Architecture
Rev. C | Page 9 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
DWAIT IOWAIT3 IOWAIT2 IO WAIT1 IOWAIT0
DM(0x3FFE)
WAIT STATE CONTROL
0111111111111111
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
Table 4. PMOVLAY Bits
Processor PMOVLAY Memory A13 A12–0
ADSP-2184L No internal overlay
region
ADSP-2185L 0 Internal overlay Not applicable Not applicable
ADSP-2186L No internal overlay
region
ADSP-2187L 0, 4, 5 Internal overlay Not applicable Not applicable
All Processors 1 External overlay 1 0 13 LSBs of address between 0x2000 and 0x3FFF
All Processors 2 External overlay 2 1 13 LSBs of address between 0x2000 and 0x3FFF
Table 5. DMOVLAY Bits
Processor DMOVLAY Memory A13 A12 –0
ADSP-2184L No internal overlay
region
ADSP-2185L 0 Internal overlay Not applicable Not applicable
ADSP-2186L No internal overlay
region
ADSP-2187L 0, 4, 5 Internal overlay Not applicable Not applicable
All Processors 1 External overlay 1 0 13 LSBs of address between 0x0000 and 0x1FFF
All Processors 2 External overlay 2 1 13 LSBs of address between 0x0000 and 0x1FFF
Not Applicable Not applicable Not applicable
Not applicable Not applicable Not applicable
Not applicable Not applicable Not applicable
Not applicable Not applicable Not applicable
I/O Space (Full Memory Mode)
ADSP-218xL series members support an additional external
memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters
and external registers) or to bus interface ASIC data registers.
I/O space supports 2048 locations of 16-bit wide data. The lower
eleven bits of the external address bus are used; the upper three
bits are undefined.
Two instructions were added to the core ADSP-2100 family
instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated 3-bit wait state registers,
IOWAIT0–3 as shown in Figure 8, which specify up to seven
wait states to be automatically generated for each of four
regions. The wait states act on address ranges, as shown in
Table 6.
Note: In Full Memory Mode, all 2048 locations of I/O space are
directly addressable. In Host Memory Mode, only address pin
A0 is available; therefore, additional logic is required externally
to achieve complete addressability of the 2048 I/O space
locations.
Table 6. Wait States
Address Range Wait State Register
0x000–0x1FF IOWAIT0
0x200–0x3FF IOWAIT1
0x400–0x5FF IOWAIT2
0x600–0x7FF IOWAIT3
Figure 8. Wait State Control Register
Composite Memory Select
ADSP-218xL series members have a programmable memory
select signal that is useful for generating memory select signals
for memories mapped to more than one space. The CMS signal
is generated to have the same timing as each of the individual
memory select signals (PMS
, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when
set, causes the CMS
signal to be asserted when the selected
memory select is asserted. For example, to use a 32K word
memory to act as both program and data memory, set the PMS
and DMS
drive the chip select of the memory, and use either DMS
bits in the CMSSEL register and use the CMS pin to
or PMS
as the additional address bit.
The CMS
pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS
signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
Rev. C | Page 10 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
BMWAIT CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
DM(0x3FE6)
PFTYPE
0=INPUT
1=OUTPUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
0111101100000000
1514131211109876543210
PROGRAMMABLE FLAG AND COMPOSITE
SELECT CONTROL
RESERVED
RESERVED,ALWAYS
SET TO 0
SPORT0 ENABLE
0=DISABLE
1 = ENABL E
DM(0x3FFF)
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0=FI,FO,IRQ0,IRQ1,SCLK
1=SPORT1
DISABLE BMS
0 = ENABL E BMS
1=DISABLEBMS
PWAIT
PROGRAM MEMORY
WAIT STATES
0000010000000111
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE B ITS
SHOULD ALWAYS BE WRITTEN W ITH ZEROS.
RESERVED
SET TO 0
BDMA CONTROL
BMPAGE
BTYPE
BDIR
0=LOADFROMBM
1=STORETOBM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0000000000001000
1514131211109876543210
DM (0x3FE3)
BDMA
OVERLAY
BITS
(SEE TABLE 12)
See Figure 9 and Figure 10 for illustration of the programmable
flag and composite control register and the system
control register.
Figure 9. Programmable Flag and Composite Control Register
SYSTEM CONTROL
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller (Figure 11) allows loading
and storing of program instructions and data using the byte
memory space. The BDMA circuit is able to access the byte
memory space while the processor is operating normally and
steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.
Figure 11. BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number of
8-bit accesses are done from the byte memory space to build the
word size selected. Table 7 shows the data formats supported by
the BDMA circuit.
Table 7. Data Formats
Figure 10. System Control Register
Byte Memory Select
The ADSP-218xL’s BMS disable feature combined with the
CMS
pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
select, and a flash memory could be connected to CMS
at reset BMS
After booting, software could disable BMS
is enabled, the EPROM would be used for booting.
and set the CMS sig-
nal to respond to BMS, enabling the flash memory.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data. Byte
memory is accessed using the BDMA feature. The byte memory
space consists of 256 pages, each of which is 16K ⴛ 8bits.
The byte memory space on the ADSP-218xL series supports
read and write operations as well as four different data formats.
The byte memory uses data bits 15–8 for data. The byte memory uses data bits 23–16 and address bits 13–0 to create a 22-bit
address. This allows up to a 4 megabit ⴛ 8 (32 megabit) ROM
or RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register.
BTYPE
00 Program memory 24 Full word
01 Data memory 16 Full word
10 Data memory 8 MSBs
11 Data memory 8 LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
. Because
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations. The source or destination
of a BDMA transfer is always on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
Rev. C | Page 11 of 48 | January 2008
Internal Memory
Space Word Size Alignment
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte
memory accesses.
The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory. Set these bits as indicated in
Figure 11.
Note: BDMA cannot access external overlay memory regions 1
and 2.
The BMWAIT field, which has 3 bits on ADSP-218xL series
members, allows selection of up to 7 wait states for BDMA
transfers.
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
The IDMA Port provides an efficient means of communication
between a host system and ADSP-218xL series members. The
port is used to access the on-chip program memory and data
memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the
DSP’s memory-mapped control registers. A typical IDMA
transfer process is shown as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS
starting address (IDMAA) or the PM/DM OVLAY selection into the DSP’s IDMA control registers. If Bit 15 = 1,
the values of Bits 7–0 represent the IDMA overlay; Bits
14–8 must be set to 0. If Bit 15 = 0, the value of Bits 13– 0
represent the starting address of internal memory to be
accessed and Bit 14 reflects PM or DM for access. Set
IDDMOVLAY and IDPMOVLAY bits in the IDMA overlay register as indicted in Table 8.
4. Host uses IS
internal memory (PM or DM).
5. Host checks IACK
previous IDMA operation.
6. Host ends IDMA transfer.
and IAL control lines to latch either the DMA
and IRD (or IWR) to read (or write) DSP
line to see if the DSP has completed the
Table 8. IDMA/BDMA Overlay Bits
IDMA/BDMA
Processor
ADSP-2184L 0 0
ADSP-2185L 0 0
ADSP-2186L 0 0
ADSP-2187L 0, 4, 5 0, 4, 5
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-218xL
is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This
increases throughput as the address does not have to be sent for
each memory access.
IDMA port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or PM
access. The falling edge of the IDMA address latch signal (IAL)
or the missing edge of the IDMA select signal (IS
value into the IDMAA register.
Once the address is stored, data can be read from, or written to,
the ADSP-218xL’s on-chip memory. Asserting the select line
(IS
) and the appropriate read or write line (IRD and IWR
respectively) signals the ADSP-218xL that a particular transaction is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is automatically incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch enable
(IAL) directs the ADSP-218xL to write the address onto the
IAD14–0 bus into the IDMA Control Register (Figure 12). If Bit
15 is set to 0, IDMA latches the address. If Bit 15 is set to 1,
IDMA latches into the OVLAY register. This register, also
shown in Figure 12, is memory-mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) cannot be
read back by the host. The IDMA Overlay register applies to
The ADSP-2187L processor only.
When Bit 14 in 0x3FE7 is set to zero, short reads use the timing
shown in Figure 26 on Page 34. When Bit 14 in 0x3FE7 is set to
1, timing in Figure 27 on Page 35 applies for short reads in Short
Read Only Mode. Set IDDMOVLAY and IDPMOVLAY bits in
the IDMA overlay register as indicated in Table 8. Refer to the
ADSP-218x DSP Hardware Reference for additional details.
PMOVLAY
IDMA/BDMA
DMOVLAY
) latches this
Rev. C | Page 12 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
IDMA OV ERL AY
DM (0x3FE7)
RESERVED SET TO 0 IDDMOVLAY IDPMOVLAY
000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHOR T READ
ONLY
0 = DISABLE
1 = ENABLE
IDMA CONTROL (U = U NDEFINED AT RESET)
DM (0x3FE0)
IDMAA ADDRESS
UUUUUUUUUUUUUUU
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMAD DESTINATION MEMORY
TYPE
0=PM
1=DM
NOTE: RESERVED BITS ARE SHOWN ON A G RAY FIELD. THESE
BITS SHOULD ALWAYS BE W RITTEN WITH ZEROS.
0
RESERVED SET TO 0
0
RESERVED SET TO 0
Note: In Full Memory Mode, all locations of 4M-byte memory
space are directly addressable. In Host Memory Mode, only
address pin A0 is available, requiring additional external logic to
provide address information for the byte.
Figure 12. IDMA OVLAY/Control Registers
Bootstrap Loading (Booting)
ADSP-218xL series members have two mechanisms to allow
automatic loading of the internal program memory after reset.
The method for booting is controlled by the Mode A, Mode B,
and Mode C configuration bits.
When the mode pins specify BDMA booting, the ADSP-218xL
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is set
to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space-compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the
addresses to boot memory must be constructed externally to the
ADSP-218xL. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
ADSP-218xL series members can also boot programs through
its internal DMA port. If Mode C = 1, Mode B = 0, and Mode A
= 1, the ADSP-218xL boots from the IDMA port. IDMA feature
can load as much on-chip memory as desired. Program execution is held off until the host writes to on-chip program memory
location 0.
BUS REQUEST AND BUS GRANT
ADSP-218xL series members can relinquish control of the data
and address buses to an external device. When the external
device requires access to memory, it asserts the Bus Request
(BR
) signal. If the ADSP-218xL is not performing an external
memory access, it responds to the active BR
ing processor cycle by:
• Three-stating the data and address buses and the PMS
DMS, BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and
• Halting program execution.
If Go Mode is enabled, the ADSP-218xL will not halt program
execution until it encounters an instruction that requires an
external memory access.
If an ADSP-218xL series member is performing an external
memory access when the external device asserts the BR
will not three-state the memory interfaces nor assert the BG
nal until the processor cycle after the access completes. The
instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory
accesses, the bus will be granted between the two accesses.
When the BR
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active.
The BGH
pin is asserted when an ADSP-218xL series member
requires the external bus for a memory or BDMA access, but is
stopped. The other device can release the bus by deasserting bus
request. Once the bus is released, the ADSP-218xL deasserts BG
and BGH and executes the external memory access.
FLAG I/O PINS
ADSP-218xL series members have eight general-purpose programmable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction, 1 = output and 0 = input. The PFDATA register is
used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the
ADSP-218xL’s clock. Bits that are programmed as outputs
will read the value being output. The PF pins default to input
during reset.
In addition to the programmable flags, ADSP-218xL series
members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2.
FL0 to FL2 are dedicated output flags. FI and FO are available as
an alternate configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset.
Rev. C | Page 13 of 48 | January 2008
input in the follow-
,
signal, it
sig-
signal is released, the processor releases the BG
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
INSTRUCTION SET DESCRIPTION
The ADSP-218xL series assembly language instruction set has
an algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage
of the processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles
a simple equation.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible
with other family members. Programs may need to be
relocated to utilize on-chip memory and conform to the
ADSP-218xL’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the condition
can be checked and the operation executed in the same
instruction cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction, with up to two fetches or one write
to processor memory space, during a single
instruction cycle.
DEVELOPMENT SYSTEM
Analog Devices’ wide range of software and hardware
development tools supports the ADSP-218xL series. The DSP
tools include an integrated development environment, an evaluation kit, and a serial port emulator.
®
VisualDSP++
allowing for fast and easy development, debugging, and deployment. The VisualDSP++ project management environment lets
programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an
algebraic syntax; an archiver (librarian/library builder); a linker;
a PROM-splitter utility; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that includes DSP
and mathematical functions.
Debugging both C and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C and assembly code (interleaved source and
object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
†
is an integrated development environment,
• Fill and dump memory
• Source level debugging
The VisualDSP++ IDE lets programmers define and manage
DSP software development. The dialog boxes and property
pages let programmers configure and manage all of the
ADSP-218xL development tools, including the syntax highlighting in the VisualDSP++ editor. This capability controls how the
development tools process inputs and generate outputs.
®
The ADSP-2189M EZ-KIT Lite
‡
provides developers with a
cost-effective method for initial evaluation of the powerful
ADSP-218xL DSP family architecture. The ADSP-2189M
EZ-KIT Lite includes a standalone ADSP-2189M DSP board
supported by an evaluation suite of VisualDSP++. With this
EZ-KIT Lite, users can learn about DSP hardware and software
development and evaluate potential applications of the
ADSP-218xL series. The ADSP-2189M EZ-KIT Lite provides an
evaluation suite of the VisualDSP++ development environment
with the C compiler, assembler, and linker. The size of the DSP
executable that can be built using the EZ-KIT Lite tools is limited to 8K words.
The EZ-KIT Lite includes the following features:
• 75 MHz ADSP-2189M
• Full 16-Bit Stereo Audio I/O with AD73322 Codec
• RS-232 Interface
•EZ-ICE® Connector for Emulator Control
•DSP Demonstration Programs
• Evaluation Suite of VisualDSP++
The ADSP-218x EZ-ICE
§
Emulator provides an easier and more
cost-effective method for engineers to develop and optimize
DSP systems, shortening product development cycles for faster
time-to-market. ADSP-218xL series members integrate on-chip
emulation support with a 14-pin ICE-Port
TM
interface. This
interface provides a simpler target board connection that
requires fewer mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. ADSP-218xL series members need
not be removed from the target system when using the EZ-ICE,
nor are any adapters needed. Due to the small footprint of the
EZ-ICE connector, emulation can be supported in final board
designs.The EZ-ICE performs a full range of functions,
including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting
and execution
†
VisualDSP++ is a registered trademark of Analog Devices, Inc.
‡
EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
§
EZ-ICE is a registered trademark of Analog Devices, Inc.
Rev. C | Page 14 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
PROGRAMMAB LE I/O
MODE A/PF0
RESET
ERESET
ADSP-218xL
1k⍀
ⴛ
1
2
3
4
56
7
8
910
11
12
13 14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
• Complete assembly and disassembly of instructions
• C source-level debugging
Designing an EZ-ICE-Compatible System
ADSP-218xL series members have on-chip emulation support
and an ICE-Port, a special set of pins that interface to the
EZ-ICE. These features allow in-circuit emulation without
replacing the target system processor by using only a 14-pin
connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE’s incircuit probe, a 14-pin plug.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If a passive method of maintaining mode information
is being used (as discussed in Setting Memory Mode on Page 4),
it does not matter that the mode information is latched by an
emulator reset. However, if the RESET
pin is being used as a
method of setting the value of the mode pins, the effects of an
emulator reset must be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 13. This circuit forces the value located on the Mode A
pin to logic high, regardless of whether it is latched via the
RESET or ERESET pin.
The EZ-ICE connects to the target system via a ribbon cable and
a 14-pin female plug. The female plug is plugged onto the 14pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 14. This connector must be added to the target board
design to use the EZ-ICE. Be sure to allow enough room in the
system to fit the EZ-ICE probe onto the 14-pin connector.
Figure 14. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1ⴛ 0.1 inch. The pin strip header must have at least
0.15 inch clearance on all sides to accept the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Figure 13. Mode A Pin/EZ-ICE Circuit
The ICE-Port interface consists of the following ADSP-218xL
pins: EBR
, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and
ELOUT.
These ADSP-218xL pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the
ADSP-218xL and the connector must be kept as short as possible, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR
and GND.
The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-218xL in the target system. This causes the processor to use its ERESET
BR
do not need to be jumper-isolated in the system.
, EBR, and EBG pins instead of the RESET,
, and BG pins. The BG output is three-stated. These signals
, BG, RESET,
Rev. C | Page 15 of 48 | January 2008
Target Memory Interface
For the target system to be compatible with the EZ-ICE emulator, it must comply with the following memory interface
guidelines:
Design the Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst-case device
timing requirements and switching characteristics as specified
in this data sheet. The performance of the EZ-ICE may
approach published worst-case specification for some memory
access timing requirements and switching characteristics.
Note: If the target does not meet the worst-case chip specification for memory access parameters, the circuitry may not be
able to be emulated at the desired CLKIN frequency. Depending
on the severity of the specification violation, the system may be
difficult to manufacture, as DSP components statistically vary in
switching characteristic and timing requirements, within published limits.
Restriction: All memory strobe signals on the ADSP-218xL
(RD
, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
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